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Commit | Line | Data |
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1f1846c6 SH |
1 | /* |
2 | * drivers/dma/imx-dma.c | |
3 | * | |
4 | * This file contains a driver for the Freescale i.MX DMA engine | |
5 | * found on i.MX1/21/27 | |
6 | * | |
7 | * Copyright 2010 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de> | |
9e15db7c | 8 | * Copyright 2012 Javier Martin, Vista Silicon <javier.martin@vista-silicon.com> |
1f1846c6 SH |
9 | * |
10 | * The code contained herein is licensed under the GNU General Public | |
11 | * License. You may obtain a copy of the GNU General Public License | |
12 | * Version 2 or later at the following locations: | |
13 | * | |
14 | * http://www.opensource.org/licenses/gpl-license.html | |
15 | * http://www.gnu.org/copyleft/gpl.html | |
16 | */ | |
17 | #include <linux/init.h> | |
f8de8f4c | 18 | #include <linux/module.h> |
1f1846c6 SH |
19 | #include <linux/types.h> |
20 | #include <linux/mm.h> | |
21 | #include <linux/interrupt.h> | |
22 | #include <linux/spinlock.h> | |
23 | #include <linux/device.h> | |
24 | #include <linux/dma-mapping.h> | |
25 | #include <linux/slab.h> | |
26 | #include <linux/platform_device.h> | |
6bd08127 | 27 | #include <linux/clk.h> |
1f1846c6 | 28 | #include <linux/dmaengine.h> |
5170c051 | 29 | #include <linux/module.h> |
1f1846c6 SH |
30 | |
31 | #include <asm/irq.h> | |
6bd08127 | 32 | #include <mach/dma.h> |
1f1846c6 SH |
33 | #include <mach/hardware.h> |
34 | ||
d2ebfb33 | 35 | #include "dmaengine.h" |
9e15db7c | 36 | #define IMXDMA_MAX_CHAN_DESCRIPTORS 16 |
6bd08127 JM |
37 | #define IMX_DMA_CHANNELS 16 |
38 | ||
6bd08127 JM |
39 | #define IMX_DMA_LENGTH_LOOP ((unsigned int)-1) |
40 | #define IMX_DMA_MEMSIZE_32 (0 << 4) | |
41 | #define IMX_DMA_MEMSIZE_8 (1 << 4) | |
42 | #define IMX_DMA_MEMSIZE_16 (2 << 4) | |
43 | #define IMX_DMA_TYPE_LINEAR (0 << 10) | |
44 | #define IMX_DMA_TYPE_2D (1 << 10) | |
45 | #define IMX_DMA_TYPE_FIFO (2 << 10) | |
46 | ||
47 | #define IMX_DMA_ERR_BURST (1 << 0) | |
48 | #define IMX_DMA_ERR_REQUEST (1 << 1) | |
49 | #define IMX_DMA_ERR_TRANSFER (1 << 2) | |
50 | #define IMX_DMA_ERR_BUFFER (1 << 3) | |
51 | #define IMX_DMA_ERR_TIMEOUT (1 << 4) | |
52 | ||
53 | #define DMA_DCR 0x00 /* Control Register */ | |
54 | #define DMA_DISR 0x04 /* Interrupt status Register */ | |
55 | #define DMA_DIMR 0x08 /* Interrupt mask Register */ | |
56 | #define DMA_DBTOSR 0x0c /* Burst timeout status Register */ | |
57 | #define DMA_DRTOSR 0x10 /* Request timeout Register */ | |
58 | #define DMA_DSESR 0x14 /* Transfer Error Status Register */ | |
59 | #define DMA_DBOSR 0x18 /* Buffer overflow status Register */ | |
60 | #define DMA_DBTOCR 0x1c /* Burst timeout control Register */ | |
61 | #define DMA_WSRA 0x40 /* W-Size Register A */ | |
62 | #define DMA_XSRA 0x44 /* X-Size Register A */ | |
63 | #define DMA_YSRA 0x48 /* Y-Size Register A */ | |
64 | #define DMA_WSRB 0x4c /* W-Size Register B */ | |
65 | #define DMA_XSRB 0x50 /* X-Size Register B */ | |
66 | #define DMA_YSRB 0x54 /* Y-Size Register B */ | |
67 | #define DMA_SAR(x) (0x80 + ((x) << 6)) /* Source Address Registers */ | |
68 | #define DMA_DAR(x) (0x84 + ((x) << 6)) /* Destination Address Registers */ | |
69 | #define DMA_CNTR(x) (0x88 + ((x) << 6)) /* Count Registers */ | |
70 | #define DMA_CCR(x) (0x8c + ((x) << 6)) /* Control Registers */ | |
71 | #define DMA_RSSR(x) (0x90 + ((x) << 6)) /* Request source select Registers */ | |
72 | #define DMA_BLR(x) (0x94 + ((x) << 6)) /* Burst length Registers */ | |
73 | #define DMA_RTOR(x) (0x98 + ((x) << 6)) /* Request timeout Registers */ | |
74 | #define DMA_BUCR(x) (0x98 + ((x) << 6)) /* Bus Utilization Registers */ | |
75 | #define DMA_CCNR(x) (0x9C + ((x) << 6)) /* Channel counter Registers */ | |
76 | ||
77 | #define DCR_DRST (1<<1) | |
78 | #define DCR_DEN (1<<0) | |
79 | #define DBTOCR_EN (1<<15) | |
80 | #define DBTOCR_CNT(x) ((x) & 0x7fff) | |
81 | #define CNTR_CNT(x) ((x) & 0xffffff) | |
82 | #define CCR_ACRPT (1<<14) | |
83 | #define CCR_DMOD_LINEAR (0x0 << 12) | |
84 | #define CCR_DMOD_2D (0x1 << 12) | |
85 | #define CCR_DMOD_FIFO (0x2 << 12) | |
86 | #define CCR_DMOD_EOBFIFO (0x3 << 12) | |
87 | #define CCR_SMOD_LINEAR (0x0 << 10) | |
88 | #define CCR_SMOD_2D (0x1 << 10) | |
89 | #define CCR_SMOD_FIFO (0x2 << 10) | |
90 | #define CCR_SMOD_EOBFIFO (0x3 << 10) | |
91 | #define CCR_MDIR_DEC (1<<9) | |
92 | #define CCR_MSEL_B (1<<8) | |
93 | #define CCR_DSIZ_32 (0x0 << 6) | |
94 | #define CCR_DSIZ_8 (0x1 << 6) | |
95 | #define CCR_DSIZ_16 (0x2 << 6) | |
96 | #define CCR_SSIZ_32 (0x0 << 4) | |
97 | #define CCR_SSIZ_8 (0x1 << 4) | |
98 | #define CCR_SSIZ_16 (0x2 << 4) | |
99 | #define CCR_REN (1<<3) | |
100 | #define CCR_RPT (1<<2) | |
101 | #define CCR_FRC (1<<1) | |
102 | #define CCR_CEN (1<<0) | |
103 | #define RTOR_EN (1<<15) | |
104 | #define RTOR_CLK (1<<14) | |
105 | #define RTOR_PSC (1<<13) | |
9e15db7c JM |
106 | |
107 | enum imxdma_prep_type { | |
108 | IMXDMA_DESC_MEMCPY, | |
109 | IMXDMA_DESC_INTERLEAVED, | |
110 | IMXDMA_DESC_SLAVE_SG, | |
111 | IMXDMA_DESC_CYCLIC, | |
112 | }; | |
113 | ||
6bd08127 JM |
114 | /* |
115 | * struct imxdma_channel_internal - i.MX specific DMA extension | |
116 | * @name: name specified by DMA client | |
117 | * @irq_handler: client callback for end of transfer | |
118 | * @err_handler: client callback for error condition | |
119 | * @data: clients context data for callbacks | |
120 | * @dma_mode: direction of the transfer %DMA_MODE_READ or %DMA_MODE_WRITE | |
121 | * @sg: pointer to the actual read/written chunk for scatter-gather emulation | |
122 | * @resbytes: total residual number of bytes to transfer | |
123 | * (it can be lower or same as sum of SG mapped chunk sizes) | |
124 | * @sgcount: number of chunks to be read/written | |
125 | * | |
126 | * Structure is used for IMX DMA processing. It would be probably good | |
127 | * @struct dma_struct in the future for external interfacing and use | |
128 | * @struct imxdma_channel_internal only as extension to it. | |
129 | */ | |
130 | ||
131 | struct imxdma_channel_internal { | |
6bd08127 JM |
132 | struct timer_list watchdog; |
133 | ||
134 | int hw_chaining; | |
135 | }; | |
136 | ||
9e15db7c JM |
137 | struct imxdma_desc { |
138 | struct list_head node; | |
139 | struct dma_async_tx_descriptor desc; | |
140 | enum dma_status status; | |
141 | dma_addr_t src; | |
142 | dma_addr_t dest; | |
143 | size_t len; | |
2efc3449 | 144 | enum dma_transfer_direction direction; |
9e15db7c JM |
145 | enum imxdma_prep_type type; |
146 | /* For memcpy and interleaved */ | |
147 | unsigned int config_port; | |
148 | unsigned int config_mem; | |
149 | /* For interleaved transfers */ | |
150 | unsigned int x; | |
151 | unsigned int y; | |
152 | unsigned int w; | |
153 | /* For slave sg and cyclic */ | |
154 | struct scatterlist *sg; | |
155 | unsigned int sgcount; | |
156 | }; | |
157 | ||
1f1846c6 | 158 | struct imxdma_channel { |
6bd08127 | 159 | struct imxdma_channel_internal internal; |
1f1846c6 SH |
160 | struct imxdma_engine *imxdma; |
161 | unsigned int channel; | |
1f1846c6 | 162 | |
9e15db7c JM |
163 | struct tasklet_struct dma_tasklet; |
164 | struct list_head ld_free; | |
165 | struct list_head ld_queue; | |
166 | struct list_head ld_active; | |
167 | int descs_allocated; | |
1f1846c6 SH |
168 | enum dma_slave_buswidth word_size; |
169 | dma_addr_t per_address; | |
170 | u32 watermark_level; | |
171 | struct dma_chan chan; | |
172 | spinlock_t lock; | |
173 | struct dma_async_tx_descriptor desc; | |
1f1846c6 SH |
174 | enum dma_status status; |
175 | int dma_request; | |
176 | struct scatterlist *sg_list; | |
359291a1 JM |
177 | u32 ccr_from_device; |
178 | u32 ccr_to_device; | |
1f1846c6 SH |
179 | }; |
180 | ||
1f1846c6 SH |
181 | struct imxdma_engine { |
182 | struct device *dev; | |
1e070a60 | 183 | struct device_dma_parameters dma_parms; |
1f1846c6 | 184 | struct dma_device dma_device; |
6bd08127 | 185 | struct imxdma_channel channel[IMX_DMA_CHANNELS]; |
1f1846c6 SH |
186 | }; |
187 | ||
188 | static struct imxdma_channel *to_imxdma_chan(struct dma_chan *chan) | |
189 | { | |
190 | return container_of(chan, struct imxdma_channel, chan); | |
191 | } | |
192 | ||
9e15db7c | 193 | static inline bool imxdma_chan_is_doing_cyclic(struct imxdma_channel *imxdmac) |
1f1846c6 | 194 | { |
9e15db7c JM |
195 | struct imxdma_desc *desc; |
196 | ||
197 | if (!list_empty(&imxdmac->ld_active)) { | |
198 | desc = list_first_entry(&imxdmac->ld_active, struct imxdma_desc, | |
199 | node); | |
200 | if (desc->type == IMXDMA_DESC_CYCLIC) | |
201 | return true; | |
202 | } | |
203 | return false; | |
1f1846c6 SH |
204 | } |
205 | ||
6bd08127 JM |
206 | /* TODO: put this inside any struct */ |
207 | static void __iomem *imx_dmav1_baseaddr; | |
208 | static struct clk *dma_clk; | |
209 | ||
210 | static void imx_dmav1_writel(unsigned val, unsigned offset) | |
211 | { | |
212 | __raw_writel(val, imx_dmav1_baseaddr + offset); | |
213 | } | |
214 | ||
215 | static unsigned imx_dmav1_readl(unsigned offset) | |
1f1846c6 | 216 | { |
6bd08127 JM |
217 | return __raw_readl(imx_dmav1_baseaddr + offset); |
218 | } | |
1f1846c6 | 219 | |
6bd08127 JM |
220 | static int imxdma_hw_chain(struct imxdma_channel_internal *imxdma) |
221 | { | |
222 | if (cpu_is_mx27()) | |
223 | return imxdma->hw_chaining; | |
224 | else | |
225 | return 0; | |
226 | } | |
227 | ||
228 | /* | |
229 | * imxdma_sg_next - prepare next chunk for scatter-gather DMA emulation | |
230 | */ | |
2efc3449 | 231 | static inline int imxdma_sg_next(struct imxdma_desc *d, struct scatterlist *sg) |
6bd08127 | 232 | { |
2efc3449 | 233 | struct imxdma_channel *imxdmac = to_imxdma_chan(d->desc.chan); |
6bd08127 JM |
234 | unsigned long now; |
235 | ||
6b0e2f55 JM |
236 | now = min(d->len, sg->length); |
237 | if (d->len != IMX_DMA_LENGTH_LOOP) | |
238 | d->len -= now; | |
6bd08127 | 239 | |
2efc3449 | 240 | if (d->direction == DMA_DEV_TO_MEM) |
6bd08127 JM |
241 | imx_dmav1_writel(sg->dma_address, DMA_DAR(imxdmac->channel)); |
242 | else | |
243 | imx_dmav1_writel(sg->dma_address, DMA_SAR(imxdmac->channel)); | |
244 | ||
245 | imx_dmav1_writel(now, DMA_CNTR(imxdmac->channel)); | |
246 | ||
247 | pr_debug("imxdma%d: next sg chunk dst 0x%08x, src 0x%08x, " | |
248 | "size 0x%08x\n", imxdmac->channel, | |
249 | imx_dmav1_readl(DMA_DAR(imxdmac->channel)), | |
250 | imx_dmav1_readl(DMA_SAR(imxdmac->channel)), | |
251 | imx_dmav1_readl(DMA_CNTR(imxdmac->channel))); | |
252 | ||
253 | return now; | |
254 | } | |
255 | ||
2efc3449 | 256 | static void imxdma_enable_hw(struct imxdma_desc *d) |
6bd08127 | 257 | { |
2efc3449 | 258 | struct imxdma_channel *imxdmac = to_imxdma_chan(d->desc.chan); |
6bd08127 JM |
259 | int channel = imxdmac->channel; |
260 | unsigned long flags; | |
261 | ||
262 | pr_debug("imxdma%d: imx_dma_enable\n", channel); | |
263 | ||
6bd08127 JM |
264 | local_irq_save(flags); |
265 | ||
266 | imx_dmav1_writel(1 << channel, DMA_DISR); | |
267 | imx_dmav1_writel(imx_dmav1_readl(DMA_DIMR) & ~(1 << channel), DMA_DIMR); | |
268 | imx_dmav1_writel(imx_dmav1_readl(DMA_CCR(channel)) | CCR_CEN | | |
269 | CCR_ACRPT, DMA_CCR(channel)); | |
270 | ||
271 | if ((cpu_is_mx21() || cpu_is_mx27()) && | |
833bc03b JM |
272 | d->sg && imxdma_hw_chain(&imxdmac->internal)) { |
273 | d->sg = sg_next(d->sg); | |
274 | if (d->sg) { | |
6bd08127 | 275 | u32 tmp; |
833bc03b | 276 | imxdma_sg_next(d, d->sg); |
6bd08127 JM |
277 | tmp = imx_dmav1_readl(DMA_CCR(channel)); |
278 | imx_dmav1_writel(tmp | CCR_RPT | CCR_ACRPT, | |
279 | DMA_CCR(channel)); | |
280 | } | |
281 | } | |
6bd08127 JM |
282 | |
283 | local_irq_restore(flags); | |
284 | } | |
285 | ||
286 | static void imxdma_disable_hw(struct imxdma_channel *imxdmac) | |
287 | { | |
288 | int channel = imxdmac->channel; | |
289 | unsigned long flags; | |
290 | ||
291 | pr_debug("imxdma%d: imx_dma_disable\n", channel); | |
292 | ||
293 | if (imxdma_hw_chain(&imxdmac->internal)) | |
294 | del_timer(&imxdmac->internal.watchdog); | |
295 | ||
296 | local_irq_save(flags); | |
297 | imx_dmav1_writel(imx_dmav1_readl(DMA_DIMR) | (1 << channel), DMA_DIMR); | |
298 | imx_dmav1_writel(imx_dmav1_readl(DMA_CCR(channel)) & ~CCR_CEN, | |
299 | DMA_CCR(channel)); | |
300 | imx_dmav1_writel(1 << channel, DMA_DISR); | |
6bd08127 JM |
301 | local_irq_restore(flags); |
302 | } | |
303 | ||
6bd08127 | 304 | static void imxdma_watchdog(unsigned long data) |
1f1846c6 | 305 | { |
6bd08127 JM |
306 | struct imxdma_channel *imxdmac = (struct imxdma_channel *)data; |
307 | int channel = imxdmac->channel; | |
1f1846c6 | 308 | |
6bd08127 | 309 | imx_dmav1_writel(0, DMA_CCR(channel)); |
6bd08127 JM |
310 | |
311 | /* Tasklet watchdog error handler */ | |
9e15db7c | 312 | tasklet_schedule(&imxdmac->dma_tasklet); |
6bd08127 JM |
313 | pr_debug("imxdma%d: watchdog timeout!\n", imxdmac->channel); |
314 | } | |
315 | ||
316 | static irqreturn_t imxdma_err_handler(int irq, void *dev_id) | |
317 | { | |
318 | struct imxdma_engine *imxdma = dev_id; | |
319 | struct imxdma_channel_internal *internal; | |
320 | unsigned int err_mask; | |
321 | int i, disr; | |
322 | int errcode; | |
323 | ||
324 | disr = imx_dmav1_readl(DMA_DISR); | |
325 | ||
326 | err_mask = imx_dmav1_readl(DMA_DBTOSR) | | |
327 | imx_dmav1_readl(DMA_DRTOSR) | | |
328 | imx_dmav1_readl(DMA_DSESR) | | |
329 | imx_dmav1_readl(DMA_DBOSR); | |
330 | ||
331 | if (!err_mask) | |
332 | return IRQ_HANDLED; | |
333 | ||
334 | imx_dmav1_writel(disr & err_mask, DMA_DISR); | |
335 | ||
336 | for (i = 0; i < IMX_DMA_CHANNELS; i++) { | |
337 | if (!(err_mask & (1 << i))) | |
338 | continue; | |
339 | internal = &imxdma->channel[i].internal; | |
340 | errcode = 0; | |
341 | ||
342 | if (imx_dmav1_readl(DMA_DBTOSR) & (1 << i)) { | |
343 | imx_dmav1_writel(1 << i, DMA_DBTOSR); | |
344 | errcode |= IMX_DMA_ERR_BURST; | |
345 | } | |
346 | if (imx_dmav1_readl(DMA_DRTOSR) & (1 << i)) { | |
347 | imx_dmav1_writel(1 << i, DMA_DRTOSR); | |
348 | errcode |= IMX_DMA_ERR_REQUEST; | |
349 | } | |
350 | if (imx_dmav1_readl(DMA_DSESR) & (1 << i)) { | |
351 | imx_dmav1_writel(1 << i, DMA_DSESR); | |
352 | errcode |= IMX_DMA_ERR_TRANSFER; | |
353 | } | |
354 | if (imx_dmav1_readl(DMA_DBOSR) & (1 << i)) { | |
355 | imx_dmav1_writel(1 << i, DMA_DBOSR); | |
356 | errcode |= IMX_DMA_ERR_BUFFER; | |
357 | } | |
358 | /* Tasklet error handler */ | |
359 | tasklet_schedule(&imxdma->channel[i].dma_tasklet); | |
360 | ||
361 | printk(KERN_WARNING | |
362 | "DMA timeout on channel %d -%s%s%s%s\n", i, | |
363 | errcode & IMX_DMA_ERR_BURST ? " burst" : "", | |
364 | errcode & IMX_DMA_ERR_REQUEST ? " request" : "", | |
365 | errcode & IMX_DMA_ERR_TRANSFER ? " transfer" : "", | |
366 | errcode & IMX_DMA_ERR_BUFFER ? " buffer" : ""); | |
367 | } | |
368 | return IRQ_HANDLED; | |
1f1846c6 SH |
369 | } |
370 | ||
6bd08127 | 371 | static void dma_irq_handle_channel(struct imxdma_channel *imxdmac) |
1f1846c6 | 372 | { |
6bd08127 JM |
373 | struct imxdma_channel_internal *imxdma = &imxdmac->internal; |
374 | int chno = imxdmac->channel; | |
2efc3449 | 375 | struct imxdma_desc *desc; |
6bd08127 | 376 | |
833bc03b JM |
377 | spin_lock(&imxdmac->lock); |
378 | if (list_empty(&imxdmac->ld_active)) { | |
379 | spin_unlock(&imxdmac->lock); | |
380 | goto out; | |
381 | } | |
2efc3449 | 382 | |
833bc03b JM |
383 | desc = list_first_entry(&imxdmac->ld_active, |
384 | struct imxdma_desc, | |
385 | node); | |
386 | spin_unlock(&imxdmac->lock); | |
2efc3449 | 387 | |
833bc03b JM |
388 | if (desc->sg) { |
389 | u32 tmp; | |
390 | desc->sg = sg_next(desc->sg); | |
2efc3449 | 391 | |
833bc03b JM |
392 | if (desc->sg) { |
393 | imxdma_sg_next(desc, desc->sg); | |
6bd08127 JM |
394 | |
395 | tmp = imx_dmav1_readl(DMA_CCR(chno)); | |
396 | ||
397 | if (imxdma_hw_chain(imxdma)) { | |
398 | /* FIXME: The timeout should probably be | |
399 | * configurable | |
400 | */ | |
401 | mod_timer(&imxdma->watchdog, | |
402 | jiffies + msecs_to_jiffies(500)); | |
403 | ||
404 | tmp |= CCR_CEN | CCR_RPT | CCR_ACRPT; | |
405 | imx_dmav1_writel(tmp, DMA_CCR(chno)); | |
406 | } else { | |
407 | imx_dmav1_writel(tmp & ~CCR_CEN, DMA_CCR(chno)); | |
408 | tmp |= CCR_CEN; | |
409 | } | |
410 | ||
411 | imx_dmav1_writel(tmp, DMA_CCR(chno)); | |
412 | ||
413 | if (imxdma_chan_is_doing_cyclic(imxdmac)) | |
414 | /* Tasklet progression */ | |
415 | tasklet_schedule(&imxdmac->dma_tasklet); | |
1f1846c6 | 416 | |
6bd08127 JM |
417 | return; |
418 | } | |
419 | ||
420 | if (imxdma_hw_chain(imxdma)) { | |
421 | del_timer(&imxdma->watchdog); | |
422 | return; | |
423 | } | |
424 | } | |
425 | ||
2efc3449 | 426 | out: |
6bd08127 | 427 | imx_dmav1_writel(0, DMA_CCR(chno)); |
6bd08127 | 428 | /* Tasklet irq */ |
9e15db7c JM |
429 | tasklet_schedule(&imxdmac->dma_tasklet); |
430 | } | |
431 | ||
6bd08127 JM |
432 | static irqreturn_t dma_irq_handler(int irq, void *dev_id) |
433 | { | |
434 | struct imxdma_engine *imxdma = dev_id; | |
435 | struct imxdma_channel_internal *internal; | |
436 | int i, disr; | |
437 | ||
438 | if (cpu_is_mx21() || cpu_is_mx27()) | |
439 | imxdma_err_handler(irq, dev_id); | |
440 | ||
441 | disr = imx_dmav1_readl(DMA_DISR); | |
442 | ||
443 | pr_debug("imxdma: dma_irq_handler called, disr=0x%08x\n", | |
444 | disr); | |
445 | ||
446 | imx_dmav1_writel(disr, DMA_DISR); | |
447 | for (i = 0; i < IMX_DMA_CHANNELS; i++) { | |
448 | if (disr & (1 << i)) { | |
449 | internal = &imxdma->channel[i].internal; | |
450 | dma_irq_handle_channel(&imxdma->channel[i]); | |
451 | } | |
452 | } | |
453 | ||
454 | return IRQ_HANDLED; | |
455 | } | |
456 | ||
9e15db7c JM |
457 | static int imxdma_xfer_desc(struct imxdma_desc *d) |
458 | { | |
459 | struct imxdma_channel *imxdmac = to_imxdma_chan(d->desc.chan); | |
3b4b6dfc | 460 | struct imxdma_engine *imxdma = imxdmac->imxdma; |
9e15db7c JM |
461 | |
462 | /* Configure and enable */ | |
463 | switch (d->type) { | |
464 | case IMXDMA_DESC_MEMCPY: | |
3b4b6dfc JM |
465 | imx_dmav1_writel(d->src, DMA_SAR(imxdmac->channel)); |
466 | imx_dmav1_writel(d->dest, DMA_DAR(imxdmac->channel)); | |
467 | imx_dmav1_writel(d->config_mem | (d->config_port << 2), | |
468 | DMA_CCR(imxdmac->channel)); | |
6bd08127 | 469 | |
3b4b6dfc JM |
470 | imx_dmav1_writel(d->len, DMA_CNTR(imxdmac->channel)); |
471 | ||
472 | dev_dbg(imxdma->dev, "%s channel: %d dest=0x%08x src=0x%08x " | |
473 | "dma_length=%d\n", __func__, imxdmac->channel, | |
474 | d->dest, d->src, d->len); | |
475 | ||
476 | break; | |
6bd08127 | 477 | /* Cyclic transfer is the same as slave_sg with special sg configuration. */ |
9e15db7c | 478 | case IMXDMA_DESC_CYCLIC: |
9e15db7c | 479 | case IMXDMA_DESC_SLAVE_SG: |
359291a1 JM |
480 | if (d->direction == DMA_DEV_TO_MEM) { |
481 | imx_dmav1_writel(imxdmac->per_address, | |
482 | DMA_SAR(imxdmac->channel)); | |
483 | imx_dmav1_writel(imxdmac->ccr_from_device, | |
484 | DMA_CCR(imxdmac->channel)); | |
485 | ||
486 | dev_dbg(imxdma->dev, "%s channel: %d sg=%p sgcount=%d " | |
487 | "total length=%d dev_addr=0x%08x (dev2mem)\n", | |
488 | __func__, imxdmac->channel, d->sg, d->sgcount, | |
489 | d->len, imxdmac->per_address); | |
490 | } else if (d->direction == DMA_MEM_TO_DEV) { | |
491 | imx_dmav1_writel(imxdmac->per_address, | |
492 | DMA_DAR(imxdmac->channel)); | |
493 | imx_dmav1_writel(imxdmac->ccr_to_device, | |
494 | DMA_CCR(imxdmac->channel)); | |
495 | ||
496 | dev_dbg(imxdma->dev, "%s channel: %d sg=%p sgcount=%d " | |
497 | "total length=%d dev_addr=0x%08x (mem2dev)\n", | |
498 | __func__, imxdmac->channel, d->sg, d->sgcount, | |
499 | d->len, imxdmac->per_address); | |
500 | } else { | |
501 | dev_err(imxdma->dev, "%s channel: %d bad dma mode\n", | |
502 | __func__, imxdmac->channel); | |
503 | return -EINVAL; | |
504 | } | |
505 | ||
506 | imxdma_sg_next(d, d->sg); | |
507 | ||
9e15db7c JM |
508 | break; |
509 | default: | |
510 | return -EINVAL; | |
511 | } | |
2efc3449 | 512 | imxdma_enable_hw(d); |
9e15db7c JM |
513 | return 0; |
514 | } | |
515 | ||
516 | static void imxdma_tasklet(unsigned long data) | |
517 | { | |
518 | struct imxdma_channel *imxdmac = (void *)data; | |
519 | struct imxdma_engine *imxdma = imxdmac->imxdma; | |
520 | struct imxdma_desc *desc; | |
521 | ||
522 | spin_lock(&imxdmac->lock); | |
523 | ||
524 | if (list_empty(&imxdmac->ld_active)) { | |
525 | /* Someone might have called terminate all */ | |
526 | goto out; | |
527 | } | |
528 | desc = list_first_entry(&imxdmac->ld_active, struct imxdma_desc, node); | |
529 | ||
530 | if (desc->desc.callback) | |
531 | desc->desc.callback(desc->desc.callback_param); | |
532 | ||
1f3d6dc0 | 533 | dma_cookie_complete(&desc->desc); |
9e15db7c JM |
534 | |
535 | /* If we are dealing with a cyclic descriptor keep it on ld_active */ | |
536 | if (imxdma_chan_is_doing_cyclic(imxdmac)) | |
537 | goto out; | |
538 | ||
539 | list_move_tail(imxdmac->ld_active.next, &imxdmac->ld_free); | |
540 | ||
541 | if (!list_empty(&imxdmac->ld_queue)) { | |
542 | desc = list_first_entry(&imxdmac->ld_queue, struct imxdma_desc, | |
543 | node); | |
544 | list_move_tail(imxdmac->ld_queue.next, &imxdmac->ld_active); | |
545 | if (imxdma_xfer_desc(desc) < 0) | |
546 | dev_warn(imxdma->dev, "%s: channel: %d couldn't xfer desc\n", | |
547 | __func__, imxdmac->channel); | |
548 | } | |
549 | out: | |
550 | spin_unlock(&imxdmac->lock); | |
1f1846c6 SH |
551 | } |
552 | ||
553 | static int imxdma_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd, | |
554 | unsigned long arg) | |
555 | { | |
556 | struct imxdma_channel *imxdmac = to_imxdma_chan(chan); | |
557 | struct dma_slave_config *dmaengine_cfg = (void *)arg; | |
9e15db7c | 558 | unsigned long flags; |
1f1846c6 SH |
559 | unsigned int mode = 0; |
560 | ||
561 | switch (cmd) { | |
562 | case DMA_TERMINATE_ALL: | |
6bd08127 | 563 | imxdma_disable_hw(imxdmac); |
9e15db7c JM |
564 | |
565 | spin_lock_irqsave(&imxdmac->lock, flags); | |
566 | list_splice_tail_init(&imxdmac->ld_active, &imxdmac->ld_free); | |
567 | list_splice_tail_init(&imxdmac->ld_queue, &imxdmac->ld_free); | |
568 | spin_unlock_irqrestore(&imxdmac->lock, flags); | |
1f1846c6 SH |
569 | return 0; |
570 | case DMA_SLAVE_CONFIG: | |
db8196df | 571 | if (dmaengine_cfg->direction == DMA_DEV_TO_MEM) { |
1f1846c6 SH |
572 | imxdmac->per_address = dmaengine_cfg->src_addr; |
573 | imxdmac->watermark_level = dmaengine_cfg->src_maxburst; | |
574 | imxdmac->word_size = dmaengine_cfg->src_addr_width; | |
575 | } else { | |
576 | imxdmac->per_address = dmaengine_cfg->dst_addr; | |
577 | imxdmac->watermark_level = dmaengine_cfg->dst_maxburst; | |
578 | imxdmac->word_size = dmaengine_cfg->dst_addr_width; | |
579 | } | |
580 | ||
581 | switch (imxdmac->word_size) { | |
582 | case DMA_SLAVE_BUSWIDTH_1_BYTE: | |
583 | mode = IMX_DMA_MEMSIZE_8; | |
584 | break; | |
585 | case DMA_SLAVE_BUSWIDTH_2_BYTES: | |
586 | mode = IMX_DMA_MEMSIZE_16; | |
587 | break; | |
588 | default: | |
589 | case DMA_SLAVE_BUSWIDTH_4_BYTES: | |
590 | mode = IMX_DMA_MEMSIZE_32; | |
591 | break; | |
592 | } | |
1f1846c6 | 593 | |
bdc0c753 JM |
594 | imxdmac->internal.hw_chaining = 1; |
595 | if (!imxdma_hw_chain(&imxdmac->internal)) | |
596 | return -EINVAL; | |
359291a1 | 597 | imxdmac->ccr_from_device = (mode | IMX_DMA_TYPE_FIFO) | |
bdc0c753 JM |
598 | ((IMX_DMA_MEMSIZE_32 | IMX_DMA_TYPE_LINEAR) << 2) | |
599 | CCR_REN; | |
359291a1 | 600 | imxdmac->ccr_to_device = |
bdc0c753 JM |
601 | (IMX_DMA_MEMSIZE_32 | IMX_DMA_TYPE_LINEAR) | |
602 | ((mode | IMX_DMA_TYPE_FIFO) << 2) | CCR_REN; | |
603 | imx_dmav1_writel(imxdmac->dma_request, | |
604 | DMA_RSSR(imxdmac->channel)); | |
605 | ||
6bd08127 JM |
606 | /* Set burst length */ |
607 | imx_dmav1_writel(imxdmac->watermark_level * imxdmac->word_size, | |
608 | DMA_BLR(imxdmac->channel)); | |
1f1846c6 SH |
609 | |
610 | return 0; | |
611 | default: | |
612 | return -ENOSYS; | |
613 | } | |
614 | ||
615 | return -EINVAL; | |
616 | } | |
617 | ||
618 | static enum dma_status imxdma_tx_status(struct dma_chan *chan, | |
619 | dma_cookie_t cookie, | |
620 | struct dma_tx_state *txstate) | |
621 | { | |
96a2af41 | 622 | return dma_cookie_status(chan, cookie, txstate); |
1f1846c6 SH |
623 | } |
624 | ||
625 | static dma_cookie_t imxdma_tx_submit(struct dma_async_tx_descriptor *tx) | |
626 | { | |
627 | struct imxdma_channel *imxdmac = to_imxdma_chan(tx->chan); | |
628 | dma_cookie_t cookie; | |
9e15db7c | 629 | unsigned long flags; |
1f1846c6 | 630 | |
9e15db7c | 631 | spin_lock_irqsave(&imxdmac->lock, flags); |
884485e1 | 632 | cookie = dma_cookie_assign(tx); |
9e15db7c | 633 | spin_unlock_irqrestore(&imxdmac->lock, flags); |
1f1846c6 SH |
634 | |
635 | return cookie; | |
636 | } | |
637 | ||
638 | static int imxdma_alloc_chan_resources(struct dma_chan *chan) | |
639 | { | |
640 | struct imxdma_channel *imxdmac = to_imxdma_chan(chan); | |
641 | struct imx_dma_data *data = chan->private; | |
642 | ||
6c05f091 JM |
643 | if (data != NULL) |
644 | imxdmac->dma_request = data->dma_request; | |
1f1846c6 | 645 | |
9e15db7c JM |
646 | while (imxdmac->descs_allocated < IMXDMA_MAX_CHAN_DESCRIPTORS) { |
647 | struct imxdma_desc *desc; | |
1f1846c6 | 648 | |
9e15db7c JM |
649 | desc = kzalloc(sizeof(*desc), GFP_KERNEL); |
650 | if (!desc) | |
651 | break; | |
652 | __memzero(&desc->desc, sizeof(struct dma_async_tx_descriptor)); | |
653 | dma_async_tx_descriptor_init(&desc->desc, chan); | |
654 | desc->desc.tx_submit = imxdma_tx_submit; | |
655 | /* txd.flags will be overwritten in prep funcs */ | |
656 | desc->desc.flags = DMA_CTRL_ACK; | |
657 | desc->status = DMA_SUCCESS; | |
658 | ||
659 | list_add_tail(&desc->node, &imxdmac->ld_free); | |
660 | imxdmac->descs_allocated++; | |
661 | } | |
1f1846c6 | 662 | |
9e15db7c JM |
663 | if (!imxdmac->descs_allocated) |
664 | return -ENOMEM; | |
665 | ||
666 | return imxdmac->descs_allocated; | |
1f1846c6 SH |
667 | } |
668 | ||
669 | static void imxdma_free_chan_resources(struct dma_chan *chan) | |
670 | { | |
671 | struct imxdma_channel *imxdmac = to_imxdma_chan(chan); | |
9e15db7c JM |
672 | struct imxdma_desc *desc, *_desc; |
673 | unsigned long flags; | |
674 | ||
675 | spin_lock_irqsave(&imxdmac->lock, flags); | |
1f1846c6 | 676 | |
6bd08127 | 677 | imxdma_disable_hw(imxdmac); |
9e15db7c JM |
678 | list_splice_tail_init(&imxdmac->ld_active, &imxdmac->ld_free); |
679 | list_splice_tail_init(&imxdmac->ld_queue, &imxdmac->ld_free); | |
680 | ||
681 | spin_unlock_irqrestore(&imxdmac->lock, flags); | |
682 | ||
683 | list_for_each_entry_safe(desc, _desc, &imxdmac->ld_free, node) { | |
684 | kfree(desc); | |
685 | imxdmac->descs_allocated--; | |
686 | } | |
687 | INIT_LIST_HEAD(&imxdmac->ld_free); | |
1f1846c6 SH |
688 | |
689 | if (imxdmac->sg_list) { | |
690 | kfree(imxdmac->sg_list); | |
691 | imxdmac->sg_list = NULL; | |
692 | } | |
693 | } | |
694 | ||
695 | static struct dma_async_tx_descriptor *imxdma_prep_slave_sg( | |
696 | struct dma_chan *chan, struct scatterlist *sgl, | |
db8196df | 697 | unsigned int sg_len, enum dma_transfer_direction direction, |
185ecb5f | 698 | unsigned long flags, void *context) |
1f1846c6 SH |
699 | { |
700 | struct imxdma_channel *imxdmac = to_imxdma_chan(chan); | |
701 | struct scatterlist *sg; | |
9e15db7c JM |
702 | int i, dma_length = 0; |
703 | struct imxdma_desc *desc; | |
1f1846c6 | 704 | |
9e15db7c JM |
705 | if (list_empty(&imxdmac->ld_free) || |
706 | imxdma_chan_is_doing_cyclic(imxdmac)) | |
1f1846c6 SH |
707 | return NULL; |
708 | ||
9e15db7c | 709 | desc = list_first_entry(&imxdmac->ld_free, struct imxdma_desc, node); |
1f1846c6 SH |
710 | |
711 | for_each_sg(sgl, sg, sg_len, i) { | |
712 | dma_length += sg->length; | |
713 | } | |
714 | ||
d07102a1 SH |
715 | switch (imxdmac->word_size) { |
716 | case DMA_SLAVE_BUSWIDTH_4_BYTES: | |
717 | if (sgl->length & 3 || sgl->dma_address & 3) | |
718 | return NULL; | |
719 | break; | |
720 | case DMA_SLAVE_BUSWIDTH_2_BYTES: | |
721 | if (sgl->length & 1 || sgl->dma_address & 1) | |
722 | return NULL; | |
723 | break; | |
724 | case DMA_SLAVE_BUSWIDTH_1_BYTE: | |
725 | break; | |
726 | default: | |
727 | return NULL; | |
728 | } | |
729 | ||
9e15db7c JM |
730 | desc->type = IMXDMA_DESC_SLAVE_SG; |
731 | desc->sg = sgl; | |
732 | desc->sgcount = sg_len; | |
733 | desc->len = dma_length; | |
2efc3449 | 734 | desc->direction = direction; |
9e15db7c | 735 | if (direction == DMA_DEV_TO_MEM) { |
9e15db7c JM |
736 | desc->src = imxdmac->per_address; |
737 | } else { | |
9e15db7c JM |
738 | desc->dest = imxdmac->per_address; |
739 | } | |
740 | desc->desc.callback = NULL; | |
741 | desc->desc.callback_param = NULL; | |
1f1846c6 | 742 | |
9e15db7c | 743 | return &desc->desc; |
1f1846c6 SH |
744 | } |
745 | ||
746 | static struct dma_async_tx_descriptor *imxdma_prep_dma_cyclic( | |
747 | struct dma_chan *chan, dma_addr_t dma_addr, size_t buf_len, | |
185ecb5f AB |
748 | size_t period_len, enum dma_transfer_direction direction, |
749 | void *context) | |
1f1846c6 SH |
750 | { |
751 | struct imxdma_channel *imxdmac = to_imxdma_chan(chan); | |
752 | struct imxdma_engine *imxdma = imxdmac->imxdma; | |
9e15db7c JM |
753 | struct imxdma_desc *desc; |
754 | int i; | |
1f1846c6 | 755 | unsigned int periods = buf_len / period_len; |
1f1846c6 SH |
756 | |
757 | dev_dbg(imxdma->dev, "%s channel: %d buf_len=%d period_len=%d\n", | |
758 | __func__, imxdmac->channel, buf_len, period_len); | |
759 | ||
9e15db7c JM |
760 | if (list_empty(&imxdmac->ld_free) || |
761 | imxdma_chan_is_doing_cyclic(imxdmac)) | |
1f1846c6 | 762 | return NULL; |
1f1846c6 | 763 | |
9e15db7c | 764 | desc = list_first_entry(&imxdmac->ld_free, struct imxdma_desc, node); |
1f1846c6 SH |
765 | |
766 | if (imxdmac->sg_list) | |
767 | kfree(imxdmac->sg_list); | |
768 | ||
769 | imxdmac->sg_list = kcalloc(periods + 1, | |
770 | sizeof(struct scatterlist), GFP_KERNEL); | |
771 | if (!imxdmac->sg_list) | |
772 | return NULL; | |
773 | ||
774 | sg_init_table(imxdmac->sg_list, periods); | |
775 | ||
776 | for (i = 0; i < periods; i++) { | |
777 | imxdmac->sg_list[i].page_link = 0; | |
778 | imxdmac->sg_list[i].offset = 0; | |
779 | imxdmac->sg_list[i].dma_address = dma_addr; | |
780 | imxdmac->sg_list[i].length = period_len; | |
781 | dma_addr += period_len; | |
782 | } | |
783 | ||
784 | /* close the loop */ | |
785 | imxdmac->sg_list[periods].offset = 0; | |
786 | imxdmac->sg_list[periods].length = 0; | |
787 | imxdmac->sg_list[periods].page_link = | |
788 | ((unsigned long)imxdmac->sg_list | 0x01) & ~0x02; | |
789 | ||
9e15db7c JM |
790 | desc->type = IMXDMA_DESC_CYCLIC; |
791 | desc->sg = imxdmac->sg_list; | |
792 | desc->sgcount = periods; | |
793 | desc->len = IMX_DMA_LENGTH_LOOP; | |
2efc3449 | 794 | desc->direction = direction; |
9e15db7c | 795 | if (direction == DMA_DEV_TO_MEM) { |
9e15db7c JM |
796 | desc->src = imxdmac->per_address; |
797 | } else { | |
9e15db7c JM |
798 | desc->dest = imxdmac->per_address; |
799 | } | |
800 | desc->desc.callback = NULL; | |
801 | desc->desc.callback_param = NULL; | |
1f1846c6 | 802 | |
9e15db7c | 803 | return &desc->desc; |
1f1846c6 SH |
804 | } |
805 | ||
6c05f091 JM |
806 | static struct dma_async_tx_descriptor *imxdma_prep_dma_memcpy( |
807 | struct dma_chan *chan, dma_addr_t dest, | |
808 | dma_addr_t src, size_t len, unsigned long flags) | |
809 | { | |
810 | struct imxdma_channel *imxdmac = to_imxdma_chan(chan); | |
811 | struct imxdma_engine *imxdma = imxdmac->imxdma; | |
9e15db7c | 812 | struct imxdma_desc *desc; |
6c05f091 JM |
813 | |
814 | dev_dbg(imxdma->dev, "%s channel: %d src=0x%x dst=0x%x len=%d\n", | |
815 | __func__, imxdmac->channel, src, dest, len); | |
816 | ||
9e15db7c JM |
817 | if (list_empty(&imxdmac->ld_free) || |
818 | imxdma_chan_is_doing_cyclic(imxdmac)) | |
6c05f091 | 819 | return NULL; |
6c05f091 | 820 | |
9e15db7c | 821 | desc = list_first_entry(&imxdmac->ld_free, struct imxdma_desc, node); |
6c05f091 | 822 | |
9e15db7c JM |
823 | desc->type = IMXDMA_DESC_MEMCPY; |
824 | desc->src = src; | |
825 | desc->dest = dest; | |
826 | desc->len = len; | |
2efc3449 | 827 | desc->direction = DMA_MEM_TO_MEM; |
9e15db7c JM |
828 | desc->config_port = IMX_DMA_MEMSIZE_32 | IMX_DMA_TYPE_LINEAR; |
829 | desc->config_mem = IMX_DMA_MEMSIZE_32 | IMX_DMA_TYPE_LINEAR; | |
830 | desc->desc.callback = NULL; | |
831 | desc->desc.callback_param = NULL; | |
6c05f091 | 832 | |
9e15db7c | 833 | return &desc->desc; |
6c05f091 JM |
834 | } |
835 | ||
1f1846c6 SH |
836 | static void imxdma_issue_pending(struct dma_chan *chan) |
837 | { | |
5b316876 | 838 | struct imxdma_channel *imxdmac = to_imxdma_chan(chan); |
9e15db7c JM |
839 | struct imxdma_engine *imxdma = imxdmac->imxdma; |
840 | struct imxdma_desc *desc; | |
841 | unsigned long flags; | |
842 | ||
843 | spin_lock_irqsave(&imxdmac->lock, flags); | |
844 | if (list_empty(&imxdmac->ld_active) && | |
845 | !list_empty(&imxdmac->ld_queue)) { | |
846 | desc = list_first_entry(&imxdmac->ld_queue, | |
847 | struct imxdma_desc, node); | |
848 | ||
849 | if (imxdma_xfer_desc(desc) < 0) { | |
850 | dev_warn(imxdma->dev, | |
851 | "%s: channel: %d couldn't issue DMA xfer\n", | |
852 | __func__, imxdmac->channel); | |
853 | } else { | |
854 | list_move_tail(imxdmac->ld_queue.next, | |
855 | &imxdmac->ld_active); | |
856 | } | |
857 | } | |
858 | spin_unlock_irqrestore(&imxdmac->lock, flags); | |
1f1846c6 SH |
859 | } |
860 | ||
861 | static int __init imxdma_probe(struct platform_device *pdev) | |
6bd08127 | 862 | { |
1f1846c6 SH |
863 | struct imxdma_engine *imxdma; |
864 | int ret, i; | |
865 | ||
6bd08127 JM |
866 | if (cpu_is_mx1()) |
867 | imx_dmav1_baseaddr = MX1_IO_ADDRESS(MX1_DMA_BASE_ADDR); | |
868 | else if (cpu_is_mx21()) | |
869 | imx_dmav1_baseaddr = MX21_IO_ADDRESS(MX21_DMA_BASE_ADDR); | |
870 | else if (cpu_is_mx27()) | |
871 | imx_dmav1_baseaddr = MX27_IO_ADDRESS(MX27_DMA_BASE_ADDR); | |
872 | else | |
873 | return 0; | |
874 | ||
875 | dma_clk = clk_get(NULL, "dma"); | |
876 | if (IS_ERR(dma_clk)) | |
877 | return PTR_ERR(dma_clk); | |
878 | clk_enable(dma_clk); | |
879 | ||
880 | /* reset DMA module */ | |
881 | imx_dmav1_writel(DCR_DRST, DMA_DCR); | |
882 | ||
883 | if (cpu_is_mx1()) { | |
884 | ret = request_irq(MX1_DMA_INT, dma_irq_handler, 0, "DMA", imxdma); | |
885 | if (ret) { | |
886 | pr_crit("Can't register IRQ for DMA\n"); | |
887 | return ret; | |
888 | } | |
889 | ||
890 | ret = request_irq(MX1_DMA_ERR, imxdma_err_handler, 0, "DMA", imxdma); | |
891 | if (ret) { | |
892 | pr_crit("Can't register ERRIRQ for DMA\n"); | |
893 | free_irq(MX1_DMA_INT, NULL); | |
894 | return ret; | |
895 | } | |
896 | } | |
897 | ||
898 | /* enable DMA module */ | |
899 | imx_dmav1_writel(DCR_DEN, DMA_DCR); | |
900 | ||
901 | /* clear all interrupts */ | |
902 | imx_dmav1_writel((1 << IMX_DMA_CHANNELS) - 1, DMA_DISR); | |
903 | ||
904 | /* disable interrupts */ | |
905 | imx_dmav1_writel((1 << IMX_DMA_CHANNELS) - 1, DMA_DIMR); | |
906 | ||
1f1846c6 SH |
907 | imxdma = kzalloc(sizeof(*imxdma), GFP_KERNEL); |
908 | if (!imxdma) | |
909 | return -ENOMEM; | |
910 | ||
911 | INIT_LIST_HEAD(&imxdma->dma_device.channels); | |
912 | ||
f8a356ff SH |
913 | dma_cap_set(DMA_SLAVE, imxdma->dma_device.cap_mask); |
914 | dma_cap_set(DMA_CYCLIC, imxdma->dma_device.cap_mask); | |
6c05f091 | 915 | dma_cap_set(DMA_MEMCPY, imxdma->dma_device.cap_mask); |
f8a356ff | 916 | |
1f1846c6 | 917 | /* Initialize channel parameters */ |
6bd08127 | 918 | for (i = 0; i < IMX_DMA_CHANNELS; i++) { |
1f1846c6 | 919 | struct imxdma_channel *imxdmac = &imxdma->channel[i]; |
6bd08127 JM |
920 | memset(&imxdmac->internal, 0, sizeof(imxdmac->internal)); |
921 | if (cpu_is_mx21() || cpu_is_mx27()) { | |
922 | ret = request_irq(MX2x_INT_DMACH0 + i, | |
923 | dma_irq_handler, 0, "DMA", imxdma); | |
924 | if (ret) { | |
925 | pr_crit("Can't register IRQ %d for DMA channel %d\n", | |
926 | MX2x_INT_DMACH0 + i, i); | |
927 | goto err_init; | |
928 | } | |
929 | init_timer(&imxdmac->internal.watchdog); | |
930 | imxdmac->internal.watchdog.function = &imxdma_watchdog; | |
931 | imxdmac->internal.watchdog.data = (unsigned long)imxdmac; | |
8267f16e | 932 | } |
1f1846c6 | 933 | |
1f1846c6 SH |
934 | imxdmac->imxdma = imxdma; |
935 | spin_lock_init(&imxdmac->lock); | |
936 | ||
9e15db7c JM |
937 | INIT_LIST_HEAD(&imxdmac->ld_queue); |
938 | INIT_LIST_HEAD(&imxdmac->ld_free); | |
939 | INIT_LIST_HEAD(&imxdmac->ld_active); | |
940 | ||
941 | tasklet_init(&imxdmac->dma_tasklet, imxdma_tasklet, | |
942 | (unsigned long)imxdmac); | |
1f1846c6 | 943 | imxdmac->chan.device = &imxdma->dma_device; |
8ac69546 | 944 | dma_cookie_init(&imxdmac->chan); |
1f1846c6 SH |
945 | imxdmac->channel = i; |
946 | ||
947 | /* Add the channel to the DMAC list */ | |
9e15db7c JM |
948 | list_add_tail(&imxdmac->chan.device_node, |
949 | &imxdma->dma_device.channels); | |
1f1846c6 SH |
950 | } |
951 | ||
952 | imxdma->dev = &pdev->dev; | |
953 | imxdma->dma_device.dev = &pdev->dev; | |
954 | ||
955 | imxdma->dma_device.device_alloc_chan_resources = imxdma_alloc_chan_resources; | |
956 | imxdma->dma_device.device_free_chan_resources = imxdma_free_chan_resources; | |
957 | imxdma->dma_device.device_tx_status = imxdma_tx_status; | |
958 | imxdma->dma_device.device_prep_slave_sg = imxdma_prep_slave_sg; | |
959 | imxdma->dma_device.device_prep_dma_cyclic = imxdma_prep_dma_cyclic; | |
6c05f091 | 960 | imxdma->dma_device.device_prep_dma_memcpy = imxdma_prep_dma_memcpy; |
1f1846c6 SH |
961 | imxdma->dma_device.device_control = imxdma_control; |
962 | imxdma->dma_device.device_issue_pending = imxdma_issue_pending; | |
963 | ||
964 | platform_set_drvdata(pdev, imxdma); | |
965 | ||
6c05f091 | 966 | imxdma->dma_device.copy_align = 2; /* 2^2 = 4 bytes alignment */ |
1e070a60 SH |
967 | imxdma->dma_device.dev->dma_parms = &imxdma->dma_parms; |
968 | dma_set_max_seg_size(imxdma->dma_device.dev, 0xffffff); | |
969 | ||
1f1846c6 SH |
970 | ret = dma_async_device_register(&imxdma->dma_device); |
971 | if (ret) { | |
972 | dev_err(&pdev->dev, "unable to register\n"); | |
973 | goto err_init; | |
974 | } | |
975 | ||
976 | return 0; | |
977 | ||
978 | err_init: | |
6bd08127 JM |
979 | |
980 | if (cpu_is_mx21() || cpu_is_mx27()) { | |
981 | while (--i >= 0) | |
982 | free_irq(MX2x_INT_DMACH0 + i, NULL); | |
983 | } else if cpu_is_mx1() { | |
984 | free_irq(MX1_DMA_INT, NULL); | |
985 | free_irq(MX1_DMA_ERR, NULL); | |
1f1846c6 SH |
986 | } |
987 | ||
988 | kfree(imxdma); | |
989 | return ret; | |
990 | } | |
991 | ||
992 | static int __exit imxdma_remove(struct platform_device *pdev) | |
993 | { | |
994 | struct imxdma_engine *imxdma = platform_get_drvdata(pdev); | |
995 | int i; | |
996 | ||
997 | dma_async_device_unregister(&imxdma->dma_device); | |
998 | ||
6bd08127 JM |
999 | if (cpu_is_mx21() || cpu_is_mx27()) { |
1000 | for (i = 0; i < IMX_DMA_CHANNELS; i++) | |
1001 | free_irq(MX2x_INT_DMACH0 + i, NULL); | |
1002 | } else if cpu_is_mx1() { | |
1003 | free_irq(MX1_DMA_INT, NULL); | |
1004 | free_irq(MX1_DMA_ERR, NULL); | |
1f1846c6 SH |
1005 | } |
1006 | ||
1007 | kfree(imxdma); | |
1008 | ||
1009 | return 0; | |
1010 | } | |
1011 | ||
1012 | static struct platform_driver imxdma_driver = { | |
1013 | .driver = { | |
1014 | .name = "imx-dma", | |
1015 | }, | |
1016 | .remove = __exit_p(imxdma_remove), | |
1017 | }; | |
1018 | ||
1019 | static int __init imxdma_module_init(void) | |
1020 | { | |
1021 | return platform_driver_probe(&imxdma_driver, imxdma_probe); | |
1022 | } | |
1023 | subsys_initcall(imxdma_module_init); | |
1024 | ||
1025 | MODULE_AUTHOR("Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>"); | |
1026 | MODULE_DESCRIPTION("i.MX dma driver"); | |
1027 | MODULE_LICENSE("GPL"); |