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Commit | Line | Data |
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da9bb1d2 AC |
1 | # |
2 | # EDAC Kconfig | |
4577ca55 | 3 | # Copyright (c) 2008 Doug Thompson www.softwarebitmaker.com |
da9bb1d2 | 4 | # Licensed and distributed under the GPL |
b01aec9b BP |
5 | |
6 | config EDAC_ATOMIC_SCRUB | |
7 | bool | |
da9bb1d2 | 8 | |
54451663 BP |
9 | config EDAC_SUPPORT |
10 | bool | |
11 | ||
751cb5e5 | 12 | menuconfig EDAC |
e3c4ff6d BP |
13 | tristate "EDAC (Error Detection And Correction) reporting" |
14 | depends on HAS_IOMEM && EDAC_SUPPORT && RAS | |
da9bb1d2 | 15 | help |
a06b85ff BP |
16 | EDAC is a subsystem along with hardware-specific drivers designed to |
17 | report hardware errors. These are low-level errors that are reported | |
18 | in the CPU or supporting chipset or other subsystems: | |
8cb2a398 DT |
19 | memory errors, cache errors, PCI errors, thermal throttling, etc.. |
20 | If unsure, select 'Y'. | |
da9bb1d2 | 21 | |
a06b85ff | 22 | The mailing list for the EDAC project is linux-edac@vger.kernel.org. |
57c432b5 | 23 | |
751cb5e5 | 24 | if EDAC |
da9bb1d2 | 25 | |
19974710 MCC |
26 | config EDAC_LEGACY_SYSFS |
27 | bool "EDAC legacy sysfs" | |
28 | default y | |
29 | help | |
30 | Enable the compatibility sysfs nodes. | |
31 | Use 'Y' if your edac utilities aren't ported to work with the newer | |
32 | structures. | |
33 | ||
da9bb1d2 AC |
34 | config EDAC_DEBUG |
35 | bool "Debugging" | |
1c5bf781 | 36 | select DEBUG_FS |
da9bb1d2 | 37 | help |
37929874 BP |
38 | This turns on debugging information for the entire EDAC subsystem. |
39 | You do so by inserting edac_module with "edac_debug_level=x." Valid | |
40 | levels are 0-4 (from low to high) and by default it is set to 2. | |
41 | Usually you should select 'N' here. | |
da9bb1d2 | 42 | |
9cdeb404 | 43 | config EDAC_DECODE_MCE |
0d18b2e3 | 44 | tristate "Decode MCEs in human-readable form (only on AMD for now)" |
168eb34d | 45 | depends on CPU_SUP_AMD && X86_MCE_AMD |
0d18b2e3 BP |
46 | default y |
47 | ---help--- | |
48 | Enable this option if you want to decode Machine Check Exceptions | |
25985edc | 49 | occurring on your machine in human-readable form. |
0d18b2e3 BP |
50 | |
51 | You should definitely say Y here in case you want to decode MCEs | |
52 | which occur really early upon boot, before the module infrastructure | |
53 | has been initialized. | |
54 | ||
77c5f5d2 MCC |
55 | config EDAC_GHES |
56 | bool "Output ACPI APEI/GHES BIOS detected errors via EDAC" | |
e3c4ff6d | 57 | depends on ACPI_APEI_GHES && (EDAC=y) |
77c5f5d2 MCC |
58 | default y |
59 | help | |
60 | Not all machines support hardware-driven error report. Some of those | |
61 | provide a BIOS-driven error report mechanism via ACPI, using the | |
62 | APEI/GHES driver. By enabling this option, the error reports provided | |
63 | by GHES are sent to userspace via the EDAC API. | |
64 | ||
65 | When this option is enabled, it will disable the hardware-driven | |
66 | mechanisms, if a GHES BIOS is detected, entering into the | |
67 | "Firmware First" mode. | |
68 | ||
69 | It should be noticed that keeping both GHES and a hardware-driven | |
70 | error mechanism won't work well, as BIOS will race with OS, while | |
71 | reading the error registers. So, if you want to not use "Firmware | |
72 | first" GHES error mechanism, you should disable GHES either at | |
73 | compilation time or by passing "ghes.disable=1" Kernel parameter | |
74 | at boot time. | |
75 | ||
76 | In doubt, say 'Y'. | |
77 | ||
7d6034d3 | 78 | config EDAC_AMD64 |
f5b10c45 | 79 | tristate "AMD64 (Opteron, Athlon64)" |
e3c4ff6d | 80 | depends on AMD_NB && EDAC_DECODE_MCE |
7d6034d3 | 81 | help |
027dbd6f | 82 | Support for error detection and correction of DRAM ECC errors on |
f5b10c45 | 83 | the AMD64 families (>= K8) of memory controllers. |
7d6034d3 DT |
84 | |
85 | config EDAC_AMD64_ERROR_INJECTION | |
9cdeb404 | 86 | bool "Sysfs HW Error injection facilities" |
7d6034d3 DT |
87 | depends on EDAC_AMD64 |
88 | help | |
89 | Recent Opterons (Family 10h and later) provide for Memory Error | |
90 | Injection into the ECC detection circuits. The amd64_edac module | |
91 | allows the operator/user to inject Uncorrectable and Correctable | |
92 | errors into DRAM. | |
93 | ||
94 | When enabled, in each of the respective memory controller directories | |
95 | (/sys/devices/system/edac/mc/mcX), there are 3 input files: | |
96 | ||
97 | - inject_section (0..3, 16-byte section of 64-byte cacheline), | |
98 | - inject_word (0..8, 16-bit word of 16-byte section), | |
99 | - inject_ecc_vector (hex ecc vector: select bits of inject word) | |
100 | ||
101 | In addition, there are two control files, inject_read and inject_write, | |
102 | which trigger the DRAM ECC Read and Write respectively. | |
da9bb1d2 AC |
103 | |
104 | config EDAC_AMD76X | |
105 | tristate "AMD 76x (760, 762, 768)" | |
e3c4ff6d | 106 | depends on PCI && X86_32 |
da9bb1d2 AC |
107 | help |
108 | Support for error detection and correction on the AMD 76x | |
109 | series of chipsets used with the Athlon processor. | |
110 | ||
111 | config EDAC_E7XXX | |
112 | tristate "Intel e7xxx (e7205, e7500, e7501, e7505)" | |
e3c4ff6d | 113 | depends on PCI && X86_32 |
da9bb1d2 AC |
114 | help |
115 | Support for error detection and correction on the Intel | |
116 | E7205, E7500, E7501 and E7505 server chipsets. | |
117 | ||
118 | config EDAC_E752X | |
5135b797 | 119 | tristate "Intel e752x (e7520, e7525, e7320) and 3100" |
e3c4ff6d | 120 | depends on PCI && X86 |
da9bb1d2 AC |
121 | help |
122 | Support for error detection and correction on the Intel | |
123 | E7520, E7525, E7320 server chipsets. | |
124 | ||
5a2c675c TS |
125 | config EDAC_I82443BXGX |
126 | tristate "Intel 82443BX/GX (440BX/GX)" | |
e3c4ff6d | 127 | depends on PCI && X86_32 |
28f96eea | 128 | depends on BROKEN |
5a2c675c TS |
129 | help |
130 | Support for error detection and correction on the Intel | |
131 | 82443BX/GX memory controllers (440BX/GX chipsets). | |
132 | ||
da9bb1d2 AC |
133 | config EDAC_I82875P |
134 | tristate "Intel 82875p (D82875P, E7210)" | |
e3c4ff6d | 135 | depends on PCI && X86_32 |
da9bb1d2 AC |
136 | help |
137 | Support for error detection and correction on the Intel | |
138 | DP82785P and E7210 server chipsets. | |
139 | ||
420390f0 RD |
140 | config EDAC_I82975X |
141 | tristate "Intel 82975x (D82975x)" | |
e3c4ff6d | 142 | depends on PCI && X86 |
420390f0 RD |
143 | help |
144 | Support for error detection and correction on the Intel | |
145 | DP82975x server chipsets. | |
146 | ||
535c6a53 JU |
147 | config EDAC_I3000 |
148 | tristate "Intel 3000/3010" | |
e3c4ff6d | 149 | depends on PCI && X86 |
535c6a53 JU |
150 | help |
151 | Support for error detection and correction on the Intel | |
152 | 3000 and 3010 server chipsets. | |
153 | ||
dd8ef1db JU |
154 | config EDAC_I3200 |
155 | tristate "Intel 3200" | |
e3c4ff6d | 156 | depends on PCI && X86 |
dd8ef1db JU |
157 | help |
158 | Support for error detection and correction on the Intel | |
159 | 3200 and 3210 server chipsets. | |
160 | ||
7ee40b89 JB |
161 | config EDAC_IE31200 |
162 | tristate "Intel e312xx" | |
e3c4ff6d | 163 | depends on PCI && X86 |
7ee40b89 JB |
164 | help |
165 | Support for error detection and correction on the Intel | |
166 | E3-1200 based DRAM controllers. | |
167 | ||
df8bc08c HM |
168 | config EDAC_X38 |
169 | tristate "Intel X38" | |
e3c4ff6d | 170 | depends on PCI && X86 |
df8bc08c HM |
171 | help |
172 | Support for error detection and correction on the Intel | |
173 | X38 server chipsets. | |
174 | ||
920c8df6 MCC |
175 | config EDAC_I5400 |
176 | tristate "Intel 5400 (Seaburg) chipsets" | |
e3c4ff6d | 177 | depends on PCI && X86 |
920c8df6 MCC |
178 | help |
179 | Support for error detection and correction the Intel | |
180 | i5400 MCH chipset (Seaburg). | |
181 | ||
a0c36a1f MCC |
182 | config EDAC_I7CORE |
183 | tristate "Intel i7 Core (Nehalem) processors" | |
e3c4ff6d | 184 | depends on PCI && X86 && X86_MCE_INTEL |
a0c36a1f MCC |
185 | help |
186 | Support for error detection and correction the Intel | |
696e409d MCC |
187 | i7 Core (Nehalem) Integrated Memory Controller that exists on |
188 | newer processors like i7 Core, i7 Core Extreme, Xeon 35xx | |
189 | and Xeon 55xx processors. | |
a0c36a1f | 190 | |
da9bb1d2 AC |
191 | config EDAC_I82860 |
192 | tristate "Intel 82860" | |
e3c4ff6d | 193 | depends on PCI && X86_32 |
da9bb1d2 AC |
194 | help |
195 | Support for error detection and correction on the Intel | |
196 | 82860 chipset. | |
197 | ||
198 | config EDAC_R82600 | |
199 | tristate "Radisys 82600 embedded chipset" | |
e3c4ff6d | 200 | depends on PCI && X86_32 |
da9bb1d2 AC |
201 | help |
202 | Support for error detection and correction on the Radisys | |
203 | 82600 embedded chipset. | |
204 | ||
eb60705a EW |
205 | config EDAC_I5000 |
206 | tristate "Intel Greencreek/Blackford chipset" | |
e3c4ff6d | 207 | depends on X86 && PCI |
eb60705a EW |
208 | help |
209 | Support for error detection and correction the Intel | |
210 | Greekcreek/Blackford chipsets. | |
211 | ||
8f421c59 AJ |
212 | config EDAC_I5100 |
213 | tristate "Intel San Clemente MCH" | |
e3c4ff6d | 214 | depends on X86 && PCI |
8f421c59 AJ |
215 | help |
216 | Support for error detection and correction the Intel | |
217 | San Clemente MCH. | |
218 | ||
fcaf780b MCC |
219 | config EDAC_I7300 |
220 | tristate "Intel Clarksboro MCH" | |
e3c4ff6d | 221 | depends on X86 && PCI |
fcaf780b MCC |
222 | help |
223 | Support for error detection and correction the Intel | |
224 | Clarksboro MCH (Intel 7300 chipset). | |
225 | ||
3d78c9af | 226 | config EDAC_SBRIDGE |
50d1bb93 | 227 | tristate "Intel Sandy-Bridge/Ivy-Bridge/Haswell Integrated MC" |
e3c4ff6d | 228 | depends on PCI && X86_64 && X86_MCE_INTEL && PCI_MMCONFIG |
3d78c9af MCC |
229 | help |
230 | Support for error detection and correction the Intel | |
50d1bb93 | 231 | Sandy Bridge, Ivy Bridge and Haswell Integrated Memory Controllers. |
3d78c9af | 232 | |
4ec656bd TL |
233 | config EDAC_SKX |
234 | tristate "Intel Skylake server Integrated MC" | |
e3c4ff6d | 235 | depends on PCI && X86_64 && X86_MCE_INTEL && PCI_MMCONFIG |
4ec656bd TL |
236 | help |
237 | Support for error detection and correction the Intel | |
238 | Skylake server Integrated Memory Controllers. | |
239 | ||
5c71ad17 TL |
240 | config EDAC_PND2 |
241 | tristate "Intel Pondicherry2" | |
e3c4ff6d | 242 | depends on PCI && X86_64 && X86_MCE_INTEL |
5c71ad17 TL |
243 | help |
244 | Support for error detection and correction on the Intel | |
245 | Pondicherry2 Integrated Memory Controller. This SoC IP is | |
246 | first used on the Apollo Lake platform and Denverton | |
247 | micro-server but may appear on others in the future. | |
248 | ||
a9a753d5 | 249 | config EDAC_MPC85XX |
b4846251 | 250 | tristate "Freescale MPC83xx / MPC85xx" |
e3c4ff6d | 251 | depends on FSL_SOC |
a9a753d5 DJ |
252 | help |
253 | Support for error detection and correction on the Freescale | |
74210267 | 254 | MPC8349, MPC8560, MPC8540, MPC8548, T4240 |
a9a753d5 | 255 | |
eeb3d68b YS |
256 | config EDAC_LAYERSCAPE |
257 | tristate "Freescale Layerscape DDR" | |
e3c4ff6d | 258 | depends on ARCH_LAYERSCAPE |
eeb3d68b YS |
259 | help |
260 | Support for error detection and correction on Freescale memory | |
261 | controllers on Layerscape SoCs. | |
262 | ||
4f4aeeab DJ |
263 | config EDAC_MV64X60 |
264 | tristate "Marvell MV64x60" | |
e3c4ff6d | 265 | depends on MV64X60 |
4f4aeeab DJ |
266 | help |
267 | Support for error detection and correction on the Marvell | |
268 | MV64360 and MV64460 chipsets. | |
269 | ||
7d8536fb EM |
270 | config EDAC_PASEMI |
271 | tristate "PA Semi PWRficient" | |
e3c4ff6d | 272 | depends on PPC_PASEMI && PCI |
7d8536fb EM |
273 | help |
274 | Support for error detection and correction on PA Semi | |
275 | PWRficient. | |
276 | ||
48764e41 BH |
277 | config EDAC_CELL |
278 | tristate "Cell Broadband Engine memory controller" | |
e3c4ff6d | 279 | depends on PPC_CELL_COMMON |
48764e41 BH |
280 | help |
281 | Support for error detection and correction on the | |
282 | Cell Broadband Engine internal memory controller | |
283 | on platform without a hypervisor | |
7d8536fb | 284 | |
dba7a77c GE |
285 | config EDAC_PPC4XX |
286 | tristate "PPC4xx IBM DDR2 Memory Controller" | |
e3c4ff6d | 287 | depends on 4xx |
dba7a77c GE |
288 | help |
289 | This enables support for EDAC on the ECC memory used | |
290 | with the IBM DDR2 memory controller found in various | |
291 | PowerPC 4xx embedded processors such as the 405EX[r], | |
292 | 440SP, 440SPe, 460EX, 460GT and 460SX. | |
293 | ||
e8765584 HC |
294 | config EDAC_AMD8131 |
295 | tristate "AMD8131 HyperTransport PCI-X Tunnel" | |
e3c4ff6d | 296 | depends on PCI && PPC_MAPLE |
e8765584 HC |
297 | help |
298 | Support for error detection and correction on the | |
299 | AMD8131 HyperTransport PCI-X Tunnel chip. | |
715fe7af HC |
300 | Note, add more Kconfig dependency if it's adopted |
301 | on some machine other than Maple. | |
e8765584 | 302 | |
58b4ce6f HC |
303 | config EDAC_AMD8111 |
304 | tristate "AMD8111 HyperTransport I/O Hub" | |
e3c4ff6d | 305 | depends on PCI && PPC_MAPLE |
58b4ce6f HC |
306 | help |
307 | Support for error detection and correction on the | |
308 | AMD8111 HyperTransport I/O Hub chip. | |
715fe7af HC |
309 | Note, add more Kconfig dependency if it's adopted |
310 | on some machine other than Maple. | |
58b4ce6f | 311 | |
2a9036af HC |
312 | config EDAC_CPC925 |
313 | tristate "IBM CPC925 Memory Controller (PPC970FX)" | |
e3c4ff6d | 314 | depends on PPC64 |
2a9036af HC |
315 | help |
316 | Support for error detection and correction on the | |
317 | IBM CPC925 Bridge and Memory Controller, which is | |
318 | a companion chip to the PowerPC 970 family of | |
319 | processors. | |
320 | ||
5c770755 CM |
321 | config EDAC_TILE |
322 | tristate "Tilera Memory Controller" | |
e3c4ff6d | 323 | depends on TILE |
5c770755 CM |
324 | default y |
325 | help | |
326 | Support for error detection and correction on the | |
327 | Tilera memory controller. | |
328 | ||
a1b01edb RH |
329 | config EDAC_HIGHBANK_MC |
330 | tristate "Highbank Memory Controller" | |
e3c4ff6d | 331 | depends on ARCH_HIGHBANK |
a1b01edb RH |
332 | help |
333 | Support for error detection and correction on the | |
334 | Calxeda Highbank memory controller. | |
335 | ||
69154d06 RH |
336 | config EDAC_HIGHBANK_L2 |
337 | tristate "Highbank L2 Cache" | |
e3c4ff6d | 338 | depends on ARCH_HIGHBANK |
69154d06 RH |
339 | help |
340 | Support for error detection and correction on the | |
341 | Calxeda Highbank memory controller. | |
342 | ||
f65aad41 RB |
343 | config EDAC_OCTEON_PC |
344 | tristate "Cavium Octeon Primary Caches" | |
e3c4ff6d | 345 | depends on CPU_CAVIUM_OCTEON |
f65aad41 RB |
346 | help |
347 | Support for error detection and correction on the primary caches of | |
348 | the cnMIPS cores of Cavium Octeon family SOCs. | |
349 | ||
350 | config EDAC_OCTEON_L2C | |
351 | tristate "Cavium Octeon Secondary Caches (L2C)" | |
e3c4ff6d | 352 | depends on CAVIUM_OCTEON_SOC |
f65aad41 RB |
353 | help |
354 | Support for error detection and correction on the | |
355 | Cavium Octeon family of SOCs. | |
356 | ||
357 | config EDAC_OCTEON_LMC | |
358 | tristate "Cavium Octeon DRAM Memory Controller (LMC)" | |
e3c4ff6d | 359 | depends on CAVIUM_OCTEON_SOC |
f65aad41 RB |
360 | help |
361 | Support for error detection and correction on the | |
362 | Cavium Octeon family of SOCs. | |
363 | ||
364 | config EDAC_OCTEON_PCI | |
365 | tristate "Cavium Octeon PCI Controller" | |
e3c4ff6d | 366 | depends on PCI && CAVIUM_OCTEON_SOC |
f65aad41 RB |
367 | help |
368 | Support for error detection and correction on the | |
369 | Cavium Octeon family of SOCs. | |
370 | ||
41003396 ST |
371 | config EDAC_THUNDERX |
372 | tristate "Cavium ThunderX EDAC" | |
41003396 ST |
373 | depends on ARM64 |
374 | depends on PCI | |
375 | help | |
376 | Support for error detection and correction on the | |
377 | Cavium ThunderX memory controllers (LMC), Cache | |
378 | Coherent Processor Interconnect (CCPI) and L2 cache | |
379 | blocks (TAD, CBC, MCI). | |
380 | ||
c3eea194 TT |
381 | config EDAC_ALTERA |
382 | bool "Altera SOCFPGA ECC" | |
e3c4ff6d | 383 | depends on EDAC=y && ARCH_SOCFPGA |
71bcada8 TT |
384 | help |
385 | Support for error detection and correction on the | |
c3eea194 TT |
386 | Altera SOCs. This must be selected for SDRAM ECC. |
387 | Note that the preloader must initialize the SDRAM | |
388 | before loading the kernel. | |
389 | ||
390 | config EDAC_ALTERA_L2C | |
391 | bool "Altera L2 Cache ECC" | |
3a8f21f1 | 392 | depends on EDAC_ALTERA=y && CACHE_L2X0 |
c3eea194 TT |
393 | help |
394 | Support for error detection and correction on the | |
395 | Altera L2 cache Memory for Altera SoCs. This option | |
3a8f21f1 | 396 | requires L2 cache. |
c3eea194 TT |
397 | |
398 | config EDAC_ALTERA_OCRAM | |
399 | bool "Altera On-Chip RAM ECC" | |
400 | depends on EDAC_ALTERA=y && SRAM && GENERIC_ALLOCATOR | |
401 | help | |
402 | Support for error detection and correction on the | |
403 | Altera On-Chip RAM Memory for Altera SoCs. | |
71bcada8 | 404 | |
ab8c1e0f TT |
405 | config EDAC_ALTERA_ETHERNET |
406 | bool "Altera Ethernet FIFO ECC" | |
407 | depends on EDAC_ALTERA=y | |
408 | help | |
409 | Support for error detection and correction on the | |
410 | Altera Ethernet FIFO Memory for Altera SoCs. | |
411 | ||
c6882fb2 TT |
412 | config EDAC_ALTERA_NAND |
413 | bool "Altera NAND FIFO ECC" | |
414 | depends on EDAC_ALTERA=y && MTD_NAND_DENALI | |
415 | help | |
416 | Support for error detection and correction on the | |
417 | Altera NAND FIFO Memory for Altera SoCs. | |
418 | ||
e8263793 TT |
419 | config EDAC_ALTERA_DMA |
420 | bool "Altera DMA FIFO ECC" | |
421 | depends on EDAC_ALTERA=y && PL330_DMA=y | |
422 | help | |
423 | Support for error detection and correction on the | |
424 | Altera DMA FIFO Memory for Altera SoCs. | |
425 | ||
c609581d TT |
426 | config EDAC_ALTERA_USB |
427 | bool "Altera USB FIFO ECC" | |
428 | depends on EDAC_ALTERA=y && USB_DWC2 | |
429 | help | |
430 | Support for error detection and correction on the | |
431 | Altera USB FIFO Memory for Altera SoCs. | |
432 | ||
485fe9e2 TT |
433 | config EDAC_ALTERA_QSPI |
434 | bool "Altera QSPI FIFO ECC" | |
435 | depends on EDAC_ALTERA=y && SPI_CADENCE_QUADSPI | |
436 | help | |
437 | Support for error detection and correction on the | |
438 | Altera QSPI FIFO Memory for Altera SoCs. | |
439 | ||
91104984 TT |
440 | config EDAC_ALTERA_SDMMC |
441 | bool "Altera SDMMC FIFO ECC" | |
442 | depends on EDAC_ALTERA=y && MMC_DW | |
443 | help | |
444 | Support for error detection and correction on the | |
445 | Altera SDMMC FIFO Memory for Altera SoCs. | |
446 | ||
ae9b56e3 PCK |
447 | config EDAC_SYNOPSYS |
448 | tristate "Synopsys DDR Memory Controller" | |
e3c4ff6d | 449 | depends on ARCH_ZYNQ |
ae9b56e3 PCK |
450 | help |
451 | Support for error detection and correction on the Synopsys DDR | |
452 | memory controller. | |
453 | ||
0d442930 LH |
454 | config EDAC_XGENE |
455 | tristate "APM X-Gene SoC" | |
e3c4ff6d | 456 | depends on (ARM64 || COMPILE_TEST) |
0d442930 LH |
457 | help |
458 | Support for error detection and correction on the | |
459 | APM X-Gene family of SOCs. | |
460 | ||
751cb5e5 | 461 | endif # EDAC |