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Commit | Line | Data |
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2bc65418 DT |
1 | #include "amd64_edac.h" |
2 | ||
3 | static struct edac_pci_ctl_info *amd64_ctl_pci; | |
4 | ||
5 | static int report_gart_errors; | |
6 | module_param(report_gart_errors, int, 0644); | |
7 | ||
8 | /* | |
9 | * Set by command line parameter. If BIOS has enabled the ECC, this override is | |
10 | * cleared to prevent re-enabling the hardware by this driver. | |
11 | */ | |
12 | static int ecc_enable_override; | |
13 | module_param(ecc_enable_override, int, 0644); | |
14 | ||
15 | /* Lookup table for all possible MC control instances */ | |
16 | struct amd64_pvt; | |
17 | static struct mem_ctl_info *mci_lookup[MAX_NUMNODES]; | |
18 | static struct amd64_pvt *pvt_lookup[MAX_NUMNODES]; | |
19 | ||
20 | /* | |
21 | * Memory scrubber control interface. For K8, memory scrubbing is handled by | |
22 | * hardware and can involve L2 cache, dcache as well as the main memory. With | |
23 | * F10, this is extended to L3 cache scrubbing on CPU models sporting that | |
24 | * functionality. | |
25 | * | |
26 | * This causes the "units" for the scrubbing speed to vary from 64 byte blocks | |
27 | * (dram) over to cache lines. This is nasty, so we will use bandwidth in | |
28 | * bytes/sec for the setting. | |
29 | * | |
30 | * Currently, we only do dram scrubbing. If the scrubbing is done in software on | |
31 | * other archs, we might not have access to the caches directly. | |
32 | */ | |
33 | ||
34 | /* | |
35 | * scan the scrub rate mapping table for a close or matching bandwidth value to | |
36 | * issue. If requested is too big, then use last maximum value found. | |
37 | */ | |
38 | static int amd64_search_set_scrub_rate(struct pci_dev *ctl, u32 new_bw, | |
39 | u32 min_scrubrate) | |
40 | { | |
41 | u32 scrubval; | |
42 | int i; | |
43 | ||
44 | /* | |
45 | * map the configured rate (new_bw) to a value specific to the AMD64 | |
46 | * memory controller and apply to register. Search for the first | |
47 | * bandwidth entry that is greater or equal than the setting requested | |
48 | * and program that. If at last entry, turn off DRAM scrubbing. | |
49 | */ | |
50 | for (i = 0; i < ARRAY_SIZE(scrubrates); i++) { | |
51 | /* | |
52 | * skip scrub rates which aren't recommended | |
53 | * (see F10 BKDG, F3x58) | |
54 | */ | |
55 | if (scrubrates[i].scrubval < min_scrubrate) | |
56 | continue; | |
57 | ||
58 | if (scrubrates[i].bandwidth <= new_bw) | |
59 | break; | |
60 | ||
61 | /* | |
62 | * if no suitable bandwidth found, turn off DRAM scrubbing | |
63 | * entirely by falling back to the last element in the | |
64 | * scrubrates array. | |
65 | */ | |
66 | } | |
67 | ||
68 | scrubval = scrubrates[i].scrubval; | |
69 | if (scrubval) | |
70 | edac_printk(KERN_DEBUG, EDAC_MC, | |
71 | "Setting scrub rate bandwidth: %u\n", | |
72 | scrubrates[i].bandwidth); | |
73 | else | |
74 | edac_printk(KERN_DEBUG, EDAC_MC, "Turning scrubbing off.\n"); | |
75 | ||
76 | pci_write_bits32(ctl, K8_SCRCTRL, scrubval, 0x001F); | |
77 | ||
78 | return 0; | |
79 | } | |
80 | ||
81 | static int amd64_set_scrub_rate(struct mem_ctl_info *mci, u32 *bandwidth) | |
82 | { | |
83 | struct amd64_pvt *pvt = mci->pvt_info; | |
84 | u32 min_scrubrate = 0x0; | |
85 | ||
86 | switch (boot_cpu_data.x86) { | |
87 | case 0xf: | |
88 | min_scrubrate = K8_MIN_SCRUB_RATE_BITS; | |
89 | break; | |
90 | case 0x10: | |
91 | min_scrubrate = F10_MIN_SCRUB_RATE_BITS; | |
92 | break; | |
93 | case 0x11: | |
94 | min_scrubrate = F11_MIN_SCRUB_RATE_BITS; | |
95 | break; | |
96 | ||
97 | default: | |
98 | amd64_printk(KERN_ERR, "Unsupported family!\n"); | |
99 | break; | |
100 | } | |
101 | return amd64_search_set_scrub_rate(pvt->misc_f3_ctl, *bandwidth, | |
102 | min_scrubrate); | |
103 | } | |
104 | ||
105 | static int amd64_get_scrub_rate(struct mem_ctl_info *mci, u32 *bw) | |
106 | { | |
107 | struct amd64_pvt *pvt = mci->pvt_info; | |
108 | u32 scrubval = 0; | |
109 | int status = -1, i, ret = 0; | |
110 | ||
111 | ret = pci_read_config_dword(pvt->misc_f3_ctl, K8_SCRCTRL, &scrubval); | |
112 | if (ret) | |
113 | debugf0("Reading K8_SCRCTRL failed\n"); | |
114 | ||
115 | scrubval = scrubval & 0x001F; | |
116 | ||
117 | edac_printk(KERN_DEBUG, EDAC_MC, | |
118 | "pci-read, sdram scrub control value: %d \n", scrubval); | |
119 | ||
120 | for (i = 0; ARRAY_SIZE(scrubrates); i++) { | |
121 | if (scrubrates[i].scrubval == scrubval) { | |
122 | *bw = scrubrates[i].bandwidth; | |
123 | status = 0; | |
124 | break; | |
125 | } | |
126 | } | |
127 | ||
128 | return status; | |
129 | } | |
130 | ||
6775763a DT |
131 | /* Map from a CSROW entry to the mask entry that operates on it */ |
132 | static inline u32 amd64_map_to_dcs_mask(struct amd64_pvt *pvt, int csrow) | |
133 | { | |
134 | return csrow >> (pvt->num_dcsm >> 3); | |
135 | } | |
136 | ||
137 | /* return the 'base' address the i'th CS entry of the 'dct' DRAM controller */ | |
138 | static u32 amd64_get_dct_base(struct amd64_pvt *pvt, int dct, int csrow) | |
139 | { | |
140 | if (dct == 0) | |
141 | return pvt->dcsb0[csrow]; | |
142 | else | |
143 | return pvt->dcsb1[csrow]; | |
144 | } | |
145 | ||
146 | /* | |
147 | * Return the 'mask' address the i'th CS entry. This function is needed because | |
148 | * there number of DCSM registers on Rev E and prior vs Rev F and later is | |
149 | * different. | |
150 | */ | |
151 | static u32 amd64_get_dct_mask(struct amd64_pvt *pvt, int dct, int csrow) | |
152 | { | |
153 | if (dct == 0) | |
154 | return pvt->dcsm0[amd64_map_to_dcs_mask(pvt, csrow)]; | |
155 | else | |
156 | return pvt->dcsm1[amd64_map_to_dcs_mask(pvt, csrow)]; | |
157 | } | |
158 | ||
159 | ||
160 | /* | |
161 | * In *base and *limit, pass back the full 40-bit base and limit physical | |
162 | * addresses for the node given by node_id. This information is obtained from | |
163 | * DRAM Base (section 3.4.4.1) and DRAM Limit (section 3.4.4.2) registers. The | |
164 | * base and limit addresses are of type SysAddr, as defined at the start of | |
165 | * section 3.4.4 (p. 70). They are the lowest and highest physical addresses | |
166 | * in the address range they represent. | |
167 | */ | |
168 | static void amd64_get_base_and_limit(struct amd64_pvt *pvt, int node_id, | |
169 | u64 *base, u64 *limit) | |
170 | { | |
171 | *base = pvt->dram_base[node_id]; | |
172 | *limit = pvt->dram_limit[node_id]; | |
173 | } | |
174 | ||
175 | /* | |
176 | * Return 1 if the SysAddr given by sys_addr matches the base/limit associated | |
177 | * with node_id | |
178 | */ | |
179 | static int amd64_base_limit_match(struct amd64_pvt *pvt, | |
180 | u64 sys_addr, int node_id) | |
181 | { | |
182 | u64 base, limit, addr; | |
183 | ||
184 | amd64_get_base_and_limit(pvt, node_id, &base, &limit); | |
185 | ||
186 | /* The K8 treats this as a 40-bit value. However, bits 63-40 will be | |
187 | * all ones if the most significant implemented address bit is 1. | |
188 | * Here we discard bits 63-40. See section 3.4.2 of AMD publication | |
189 | * 24592: AMD x86-64 Architecture Programmer's Manual Volume 1 | |
190 | * Application Programming. | |
191 | */ | |
192 | addr = sys_addr & 0x000000ffffffffffull; | |
193 | ||
194 | return (addr >= base) && (addr <= limit); | |
195 | } | |
196 | ||
197 | /* | |
198 | * Attempt to map a SysAddr to a node. On success, return a pointer to the | |
199 | * mem_ctl_info structure for the node that the SysAddr maps to. | |
200 | * | |
201 | * On failure, return NULL. | |
202 | */ | |
203 | static struct mem_ctl_info *find_mc_by_sys_addr(struct mem_ctl_info *mci, | |
204 | u64 sys_addr) | |
205 | { | |
206 | struct amd64_pvt *pvt; | |
207 | int node_id; | |
208 | u32 intlv_en, bits; | |
209 | ||
210 | /* | |
211 | * Here we use the DRAM Base (section 3.4.4.1) and DRAM Limit (section | |
212 | * 3.4.4.2) registers to map the SysAddr to a node ID. | |
213 | */ | |
214 | pvt = mci->pvt_info; | |
215 | ||
216 | /* | |
217 | * The value of this field should be the same for all DRAM Base | |
218 | * registers. Therefore we arbitrarily choose to read it from the | |
219 | * register for node 0. | |
220 | */ | |
221 | intlv_en = pvt->dram_IntlvEn[0]; | |
222 | ||
223 | if (intlv_en == 0) { | |
224 | for (node_id = 0; ; ) { | |
225 | if (amd64_base_limit_match(pvt, sys_addr, node_id)) | |
226 | break; | |
227 | ||
228 | if (++node_id >= DRAM_REG_COUNT) | |
229 | goto err_no_match; | |
230 | } | |
231 | goto found; | |
232 | } | |
233 | ||
234 | if (unlikely((intlv_en != (0x01 << 8)) && | |
235 | (intlv_en != (0x03 << 8)) && | |
236 | (intlv_en != (0x07 << 8)))) { | |
237 | amd64_printk(KERN_WARNING, "junk value of 0x%x extracted from " | |
238 | "IntlvEn field of DRAM Base Register for node 0: " | |
239 | "This probably indicates a BIOS bug.\n", intlv_en); | |
240 | return NULL; | |
241 | } | |
242 | ||
243 | bits = (((u32) sys_addr) >> 12) & intlv_en; | |
244 | ||
245 | for (node_id = 0; ; ) { | |
246 | if ((pvt->dram_limit[node_id] & intlv_en) == bits) | |
247 | break; /* intlv_sel field matches */ | |
248 | ||
249 | if (++node_id >= DRAM_REG_COUNT) | |
250 | goto err_no_match; | |
251 | } | |
252 | ||
253 | /* sanity test for sys_addr */ | |
254 | if (unlikely(!amd64_base_limit_match(pvt, sys_addr, node_id))) { | |
255 | amd64_printk(KERN_WARNING, | |
256 | "%s(): sys_addr 0x%lx falls outside base/limit " | |
257 | "address range for node %d with node interleaving " | |
258 | "enabled.\n", __func__, (unsigned long)sys_addr, | |
259 | node_id); | |
260 | return NULL; | |
261 | } | |
262 | ||
263 | found: | |
264 | return edac_mc_find(node_id); | |
265 | ||
266 | err_no_match: | |
267 | debugf2("sys_addr 0x%lx doesn't match any node\n", | |
268 | (unsigned long)sys_addr); | |
269 | ||
270 | return NULL; | |
271 | } | |
e2ce7255 DT |
272 | |
273 | /* | |
274 | * Extract the DRAM CS base address from selected csrow register. | |
275 | */ | |
276 | static u64 base_from_dct_base(struct amd64_pvt *pvt, int csrow) | |
277 | { | |
278 | return ((u64) (amd64_get_dct_base(pvt, 0, csrow) & pvt->dcsb_base)) << | |
279 | pvt->dcs_shift; | |
280 | } | |
281 | ||
282 | /* | |
283 | * Extract the mask from the dcsb0[csrow] entry in a CPU revision-specific way. | |
284 | */ | |
285 | static u64 mask_from_dct_mask(struct amd64_pvt *pvt, int csrow) | |
286 | { | |
287 | u64 dcsm_bits, other_bits; | |
288 | u64 mask; | |
289 | ||
290 | /* Extract bits from DRAM CS Mask. */ | |
291 | dcsm_bits = amd64_get_dct_mask(pvt, 0, csrow) & pvt->dcsm_mask; | |
292 | ||
293 | other_bits = pvt->dcsm_mask; | |
294 | other_bits = ~(other_bits << pvt->dcs_shift); | |
295 | ||
296 | /* | |
297 | * The extracted bits from DCSM belong in the spaces represented by | |
298 | * the cleared bits in other_bits. | |
299 | */ | |
300 | mask = (dcsm_bits << pvt->dcs_shift) | other_bits; | |
301 | ||
302 | return mask; | |
303 | } | |
304 | ||
305 | /* | |
306 | * @input_addr is an InputAddr associated with the node given by mci. Return the | |
307 | * csrow that input_addr maps to, or -1 on failure (no csrow claims input_addr). | |
308 | */ | |
309 | static int input_addr_to_csrow(struct mem_ctl_info *mci, u64 input_addr) | |
310 | { | |
311 | struct amd64_pvt *pvt; | |
312 | int csrow; | |
313 | u64 base, mask; | |
314 | ||
315 | pvt = mci->pvt_info; | |
316 | ||
317 | /* | |
318 | * Here we use the DRAM CS Base and DRAM CS Mask registers. For each CS | |
319 | * base/mask register pair, test the condition shown near the start of | |
320 | * section 3.5.4 (p. 84, BKDG #26094, K8, revA-E). | |
321 | */ | |
322 | for (csrow = 0; csrow < CHIPSELECT_COUNT; csrow++) { | |
323 | ||
324 | /* This DRAM chip select is disabled on this node */ | |
325 | if ((pvt->dcsb0[csrow] & K8_DCSB_CS_ENABLE) == 0) | |
326 | continue; | |
327 | ||
328 | base = base_from_dct_base(pvt, csrow); | |
329 | mask = ~mask_from_dct_mask(pvt, csrow); | |
330 | ||
331 | if ((input_addr & mask) == (base & mask)) { | |
332 | debugf2("InputAddr 0x%lx matches csrow %d (node %d)\n", | |
333 | (unsigned long)input_addr, csrow, | |
334 | pvt->mc_node_id); | |
335 | ||
336 | return csrow; | |
337 | } | |
338 | } | |
339 | ||
340 | debugf2("no matching csrow for InputAddr 0x%lx (MC node %d)\n", | |
341 | (unsigned long)input_addr, pvt->mc_node_id); | |
342 | ||
343 | return -1; | |
344 | } | |
345 | ||
346 | /* | |
347 | * Return the base value defined by the DRAM Base register for the node | |
348 | * represented by mci. This function returns the full 40-bit value despite the | |
349 | * fact that the register only stores bits 39-24 of the value. See section | |
350 | * 3.4.4.1 (BKDG #26094, K8, revA-E) | |
351 | */ | |
352 | static inline u64 get_dram_base(struct mem_ctl_info *mci) | |
353 | { | |
354 | struct amd64_pvt *pvt = mci->pvt_info; | |
355 | ||
356 | return pvt->dram_base[pvt->mc_node_id]; | |
357 | } | |
358 | ||
359 | /* | |
360 | * Obtain info from the DRAM Hole Address Register (section 3.4.8, pub #26094) | |
361 | * for the node represented by mci. Info is passed back in *hole_base, | |
362 | * *hole_offset, and *hole_size. Function returns 0 if info is valid or 1 if | |
363 | * info is invalid. Info may be invalid for either of the following reasons: | |
364 | * | |
365 | * - The revision of the node is not E or greater. In this case, the DRAM Hole | |
366 | * Address Register does not exist. | |
367 | * | |
368 | * - The DramHoleValid bit is cleared in the DRAM Hole Address Register, | |
369 | * indicating that its contents are not valid. | |
370 | * | |
371 | * The values passed back in *hole_base, *hole_offset, and *hole_size are | |
372 | * complete 32-bit values despite the fact that the bitfields in the DHAR | |
373 | * only represent bits 31-24 of the base and offset values. | |
374 | */ | |
375 | int amd64_get_dram_hole_info(struct mem_ctl_info *mci, u64 *hole_base, | |
376 | u64 *hole_offset, u64 *hole_size) | |
377 | { | |
378 | struct amd64_pvt *pvt = mci->pvt_info; | |
379 | u64 base; | |
380 | ||
381 | /* only revE and later have the DRAM Hole Address Register */ | |
382 | if (boot_cpu_data.x86 == 0xf && pvt->ext_model < OPTERON_CPU_REV_E) { | |
383 | debugf1(" revision %d for node %d does not support DHAR\n", | |
384 | pvt->ext_model, pvt->mc_node_id); | |
385 | return 1; | |
386 | } | |
387 | ||
388 | /* only valid for Fam10h */ | |
389 | if (boot_cpu_data.x86 == 0x10 && | |
390 | (pvt->dhar & F10_DRAM_MEM_HOIST_VALID) == 0) { | |
391 | debugf1(" Dram Memory Hoisting is DISABLED on this system\n"); | |
392 | return 1; | |
393 | } | |
394 | ||
395 | if ((pvt->dhar & DHAR_VALID) == 0) { | |
396 | debugf1(" Dram Memory Hoisting is DISABLED on this node %d\n", | |
397 | pvt->mc_node_id); | |
398 | return 1; | |
399 | } | |
400 | ||
401 | /* This node has Memory Hoisting */ | |
402 | ||
403 | /* +------------------+--------------------+--------------------+----- | |
404 | * | memory | DRAM hole | relocated | | |
405 | * | [0, (x - 1)] | [x, 0xffffffff] | addresses from | | |
406 | * | | | DRAM hole | | |
407 | * | | | [0x100000000, | | |
408 | * | | | (0x100000000+ | | |
409 | * | | | (0xffffffff-x))] | | |
410 | * +------------------+--------------------+--------------------+----- | |
411 | * | |
412 | * Above is a diagram of physical memory showing the DRAM hole and the | |
413 | * relocated addresses from the DRAM hole. As shown, the DRAM hole | |
414 | * starts at address x (the base address) and extends through address | |
415 | * 0xffffffff. The DRAM Hole Address Register (DHAR) relocates the | |
416 | * addresses in the hole so that they start at 0x100000000. | |
417 | */ | |
418 | ||
419 | base = dhar_base(pvt->dhar); | |
420 | ||
421 | *hole_base = base; | |
422 | *hole_size = (0x1ull << 32) - base; | |
423 | ||
424 | if (boot_cpu_data.x86 > 0xf) | |
425 | *hole_offset = f10_dhar_offset(pvt->dhar); | |
426 | else | |
427 | *hole_offset = k8_dhar_offset(pvt->dhar); | |
428 | ||
429 | debugf1(" DHAR info for node %d base 0x%lx offset 0x%lx size 0x%lx\n", | |
430 | pvt->mc_node_id, (unsigned long)*hole_base, | |
431 | (unsigned long)*hole_offset, (unsigned long)*hole_size); | |
432 | ||
433 | return 0; | |
434 | } | |
435 | EXPORT_SYMBOL_GPL(amd64_get_dram_hole_info); | |
436 | ||
93c2df58 DT |
437 | /* |
438 | * Return the DramAddr that the SysAddr given by @sys_addr maps to. It is | |
439 | * assumed that sys_addr maps to the node given by mci. | |
440 | * | |
441 | * The first part of section 3.4.4 (p. 70) shows how the DRAM Base (section | |
442 | * 3.4.4.1) and DRAM Limit (section 3.4.4.2) registers are used to translate a | |
443 | * SysAddr to a DramAddr. If the DRAM Hole Address Register (DHAR) is enabled, | |
444 | * then it is also involved in translating a SysAddr to a DramAddr. Sections | |
445 | * 3.4.8 and 3.5.8.2 describe the DHAR and how it is used for memory hoisting. | |
446 | * These parts of the documentation are unclear. I interpret them as follows: | |
447 | * | |
448 | * When node n receives a SysAddr, it processes the SysAddr as follows: | |
449 | * | |
450 | * 1. It extracts the DRAMBase and DRAMLimit values from the DRAM Base and DRAM | |
451 | * Limit registers for node n. If the SysAddr is not within the range | |
452 | * specified by the base and limit values, then node n ignores the Sysaddr | |
453 | * (since it does not map to node n). Otherwise continue to step 2 below. | |
454 | * | |
455 | * 2. If the DramHoleValid bit of the DHAR for node n is clear, the DHAR is | |
456 | * disabled so skip to step 3 below. Otherwise see if the SysAddr is within | |
457 | * the range of relocated addresses (starting at 0x100000000) from the DRAM | |
458 | * hole. If not, skip to step 3 below. Else get the value of the | |
459 | * DramHoleOffset field from the DHAR. To obtain the DramAddr, subtract the | |
460 | * offset defined by this value from the SysAddr. | |
461 | * | |
462 | * 3. Obtain the base address for node n from the DRAMBase field of the DRAM | |
463 | * Base register for node n. To obtain the DramAddr, subtract the base | |
464 | * address from the SysAddr, as shown near the start of section 3.4.4 (p.70). | |
465 | */ | |
466 | static u64 sys_addr_to_dram_addr(struct mem_ctl_info *mci, u64 sys_addr) | |
467 | { | |
468 | u64 dram_base, hole_base, hole_offset, hole_size, dram_addr; | |
469 | int ret = 0; | |
470 | ||
471 | dram_base = get_dram_base(mci); | |
472 | ||
473 | ret = amd64_get_dram_hole_info(mci, &hole_base, &hole_offset, | |
474 | &hole_size); | |
475 | if (!ret) { | |
476 | if ((sys_addr >= (1ull << 32)) && | |
477 | (sys_addr < ((1ull << 32) + hole_size))) { | |
478 | /* use DHAR to translate SysAddr to DramAddr */ | |
479 | dram_addr = sys_addr - hole_offset; | |
480 | ||
481 | debugf2("using DHAR to translate SysAddr 0x%lx to " | |
482 | "DramAddr 0x%lx\n", | |
483 | (unsigned long)sys_addr, | |
484 | (unsigned long)dram_addr); | |
485 | ||
486 | return dram_addr; | |
487 | } | |
488 | } | |
489 | ||
490 | /* | |
491 | * Translate the SysAddr to a DramAddr as shown near the start of | |
492 | * section 3.4.4 (p. 70). Although sys_addr is a 64-bit value, the k8 | |
493 | * only deals with 40-bit values. Therefore we discard bits 63-40 of | |
494 | * sys_addr below. If bit 39 of sys_addr is 1 then the bits we | |
495 | * discard are all 1s. Otherwise the bits we discard are all 0s. See | |
496 | * section 3.4.2 of AMD publication 24592: AMD x86-64 Architecture | |
497 | * Programmer's Manual Volume 1 Application Programming. | |
498 | */ | |
499 | dram_addr = (sys_addr & 0xffffffffffull) - dram_base; | |
500 | ||
501 | debugf2("using DRAM Base register to translate SysAddr 0x%lx to " | |
502 | "DramAddr 0x%lx\n", (unsigned long)sys_addr, | |
503 | (unsigned long)dram_addr); | |
504 | return dram_addr; | |
505 | } | |
506 | ||
507 | /* | |
508 | * @intlv_en is the value of the IntlvEn field from a DRAM Base register | |
509 | * (section 3.4.4.1). Return the number of bits from a SysAddr that are used | |
510 | * for node interleaving. | |
511 | */ | |
512 | static int num_node_interleave_bits(unsigned intlv_en) | |
513 | { | |
514 | static const int intlv_shift_table[] = { 0, 1, 0, 2, 0, 0, 0, 3 }; | |
515 | int n; | |
516 | ||
517 | BUG_ON(intlv_en > 7); | |
518 | n = intlv_shift_table[intlv_en]; | |
519 | return n; | |
520 | } | |
521 | ||
522 | /* Translate the DramAddr given by @dram_addr to an InputAddr. */ | |
523 | static u64 dram_addr_to_input_addr(struct mem_ctl_info *mci, u64 dram_addr) | |
524 | { | |
525 | struct amd64_pvt *pvt; | |
526 | int intlv_shift; | |
527 | u64 input_addr; | |
528 | ||
529 | pvt = mci->pvt_info; | |
530 | ||
531 | /* | |
532 | * See the start of section 3.4.4 (p. 70, BKDG #26094, K8, revA-E) | |
533 | * concerning translating a DramAddr to an InputAddr. | |
534 | */ | |
535 | intlv_shift = num_node_interleave_bits(pvt->dram_IntlvEn[0]); | |
536 | input_addr = ((dram_addr >> intlv_shift) & 0xffffff000ull) + | |
537 | (dram_addr & 0xfff); | |
538 | ||
539 | debugf2(" Intlv Shift=%d DramAddr=0x%lx maps to InputAddr=0x%lx\n", | |
540 | intlv_shift, (unsigned long)dram_addr, | |
541 | (unsigned long)input_addr); | |
542 | ||
543 | return input_addr; | |
544 | } | |
545 | ||
546 | /* | |
547 | * Translate the SysAddr represented by @sys_addr to an InputAddr. It is | |
548 | * assumed that @sys_addr maps to the node given by mci. | |
549 | */ | |
550 | static u64 sys_addr_to_input_addr(struct mem_ctl_info *mci, u64 sys_addr) | |
551 | { | |
552 | u64 input_addr; | |
553 | ||
554 | input_addr = | |
555 | dram_addr_to_input_addr(mci, sys_addr_to_dram_addr(mci, sys_addr)); | |
556 | ||
557 | debugf2("SysAdddr 0x%lx translates to InputAddr 0x%lx\n", | |
558 | (unsigned long)sys_addr, (unsigned long)input_addr); | |
559 | ||
560 | return input_addr; | |
561 | } | |
562 | ||
563 | ||
564 | /* | |
565 | * @input_addr is an InputAddr associated with the node represented by mci. | |
566 | * Translate @input_addr to a DramAddr and return the result. | |
567 | */ | |
568 | static u64 input_addr_to_dram_addr(struct mem_ctl_info *mci, u64 input_addr) | |
569 | { | |
570 | struct amd64_pvt *pvt; | |
571 | int node_id, intlv_shift; | |
572 | u64 bits, dram_addr; | |
573 | u32 intlv_sel; | |
574 | ||
575 | /* | |
576 | * Near the start of section 3.4.4 (p. 70, BKDG #26094, K8, revA-E) | |
577 | * shows how to translate a DramAddr to an InputAddr. Here we reverse | |
578 | * this procedure. When translating from a DramAddr to an InputAddr, the | |
579 | * bits used for node interleaving are discarded. Here we recover these | |
580 | * bits from the IntlvSel field of the DRAM Limit register (section | |
581 | * 3.4.4.2) for the node that input_addr is associated with. | |
582 | */ | |
583 | pvt = mci->pvt_info; | |
584 | node_id = pvt->mc_node_id; | |
585 | BUG_ON((node_id < 0) || (node_id > 7)); | |
586 | ||
587 | intlv_shift = num_node_interleave_bits(pvt->dram_IntlvEn[0]); | |
588 | ||
589 | if (intlv_shift == 0) { | |
590 | debugf1(" InputAddr 0x%lx translates to DramAddr of " | |
591 | "same value\n", (unsigned long)input_addr); | |
592 | ||
593 | return input_addr; | |
594 | } | |
595 | ||
596 | bits = ((input_addr & 0xffffff000ull) << intlv_shift) + | |
597 | (input_addr & 0xfff); | |
598 | ||
599 | intlv_sel = pvt->dram_IntlvSel[node_id] & ((1 << intlv_shift) - 1); | |
600 | dram_addr = bits + (intlv_sel << 12); | |
601 | ||
602 | debugf1("InputAddr 0x%lx translates to DramAddr 0x%lx " | |
603 | "(%d node interleave bits)\n", (unsigned long)input_addr, | |
604 | (unsigned long)dram_addr, intlv_shift); | |
605 | ||
606 | return dram_addr; | |
607 | } | |
608 | ||
609 | /* | |
610 | * @dram_addr is a DramAddr that maps to the node represented by mci. Convert | |
611 | * @dram_addr to a SysAddr. | |
612 | */ | |
613 | static u64 dram_addr_to_sys_addr(struct mem_ctl_info *mci, u64 dram_addr) | |
614 | { | |
615 | struct amd64_pvt *pvt = mci->pvt_info; | |
616 | u64 hole_base, hole_offset, hole_size, base, limit, sys_addr; | |
617 | int ret = 0; | |
618 | ||
619 | ret = amd64_get_dram_hole_info(mci, &hole_base, &hole_offset, | |
620 | &hole_size); | |
621 | if (!ret) { | |
622 | if ((dram_addr >= hole_base) && | |
623 | (dram_addr < (hole_base + hole_size))) { | |
624 | sys_addr = dram_addr + hole_offset; | |
625 | ||
626 | debugf1("using DHAR to translate DramAddr 0x%lx to " | |
627 | "SysAddr 0x%lx\n", (unsigned long)dram_addr, | |
628 | (unsigned long)sys_addr); | |
629 | ||
630 | return sys_addr; | |
631 | } | |
632 | } | |
633 | ||
634 | amd64_get_base_and_limit(pvt, pvt->mc_node_id, &base, &limit); | |
635 | sys_addr = dram_addr + base; | |
636 | ||
637 | /* | |
638 | * The sys_addr we have computed up to this point is a 40-bit value | |
639 | * because the k8 deals with 40-bit values. However, the value we are | |
640 | * supposed to return is a full 64-bit physical address. The AMD | |
641 | * x86-64 architecture specifies that the most significant implemented | |
642 | * address bit through bit 63 of a physical address must be either all | |
643 | * 0s or all 1s. Therefore we sign-extend the 40-bit sys_addr to a | |
644 | * 64-bit value below. See section 3.4.2 of AMD publication 24592: | |
645 | * AMD x86-64 Architecture Programmer's Manual Volume 1 Application | |
646 | * Programming. | |
647 | */ | |
648 | sys_addr |= ~((sys_addr & (1ull << 39)) - 1); | |
649 | ||
650 | debugf1(" Node %d, DramAddr 0x%lx to SysAddr 0x%lx\n", | |
651 | pvt->mc_node_id, (unsigned long)dram_addr, | |
652 | (unsigned long)sys_addr); | |
653 | ||
654 | return sys_addr; | |
655 | } | |
656 | ||
657 | /* | |
658 | * @input_addr is an InputAddr associated with the node given by mci. Translate | |
659 | * @input_addr to a SysAddr. | |
660 | */ | |
661 | static inline u64 input_addr_to_sys_addr(struct mem_ctl_info *mci, | |
662 | u64 input_addr) | |
663 | { | |
664 | return dram_addr_to_sys_addr(mci, | |
665 | input_addr_to_dram_addr(mci, input_addr)); | |
666 | } | |
667 | ||
668 | /* | |
669 | * Find the minimum and maximum InputAddr values that map to the given @csrow. | |
670 | * Pass back these values in *input_addr_min and *input_addr_max. | |
671 | */ | |
672 | static void find_csrow_limits(struct mem_ctl_info *mci, int csrow, | |
673 | u64 *input_addr_min, u64 *input_addr_max) | |
674 | { | |
675 | struct amd64_pvt *pvt; | |
676 | u64 base, mask; | |
677 | ||
678 | pvt = mci->pvt_info; | |
679 | BUG_ON((csrow < 0) || (csrow >= CHIPSELECT_COUNT)); | |
680 | ||
681 | base = base_from_dct_base(pvt, csrow); | |
682 | mask = mask_from_dct_mask(pvt, csrow); | |
683 | ||
684 | *input_addr_min = base & ~mask; | |
685 | *input_addr_max = base | mask | pvt->dcs_mask_notused; | |
686 | } | |
687 | ||
688 | /* | |
689 | * Extract error address from MCA NB Address Low (section 3.6.4.5) and MCA NB | |
690 | * Address High (section 3.6.4.6) register values and return the result. Address | |
691 | * is located in the info structure (nbeah and nbeal), the encoding is device | |
692 | * specific. | |
693 | */ | |
694 | static u64 extract_error_address(struct mem_ctl_info *mci, | |
695 | struct amd64_error_info_regs *info) | |
696 | { | |
697 | struct amd64_pvt *pvt = mci->pvt_info; | |
698 | ||
699 | return pvt->ops->get_error_address(mci, info); | |
700 | } | |
701 | ||
702 | ||
703 | /* Map the Error address to a PAGE and PAGE OFFSET. */ | |
704 | static inline void error_address_to_page_and_offset(u64 error_address, | |
705 | u32 *page, u32 *offset) | |
706 | { | |
707 | *page = (u32) (error_address >> PAGE_SHIFT); | |
708 | *offset = ((u32) error_address) & ~PAGE_MASK; | |
709 | } | |
710 | ||
711 | /* | |
712 | * @sys_addr is an error address (a SysAddr) extracted from the MCA NB Address | |
713 | * Low (section 3.6.4.5) and MCA NB Address High (section 3.6.4.6) registers | |
714 | * of a node that detected an ECC memory error. mci represents the node that | |
715 | * the error address maps to (possibly different from the node that detected | |
716 | * the error). Return the number of the csrow that sys_addr maps to, or -1 on | |
717 | * error. | |
718 | */ | |
719 | static int sys_addr_to_csrow(struct mem_ctl_info *mci, u64 sys_addr) | |
720 | { | |
721 | int csrow; | |
722 | ||
723 | csrow = input_addr_to_csrow(mci, sys_addr_to_input_addr(mci, sys_addr)); | |
724 | ||
725 | if (csrow == -1) | |
726 | amd64_mc_printk(mci, KERN_ERR, | |
727 | "Failed to translate InputAddr to csrow for " | |
728 | "address 0x%lx\n", (unsigned long)sys_addr); | |
729 | return csrow; | |
730 | } | |
e2ce7255 | 731 | |
2da11654 DT |
732 | static int get_channel_from_ecc_syndrome(unsigned short syndrome); |
733 | ||
734 | static void amd64_cpu_display_info(struct amd64_pvt *pvt) | |
735 | { | |
736 | if (boot_cpu_data.x86 == 0x11) | |
737 | edac_printk(KERN_DEBUG, EDAC_MC, "F11h CPU detected\n"); | |
738 | else if (boot_cpu_data.x86 == 0x10) | |
739 | edac_printk(KERN_DEBUG, EDAC_MC, "F10h CPU detected\n"); | |
740 | else if (boot_cpu_data.x86 == 0xf) | |
741 | edac_printk(KERN_DEBUG, EDAC_MC, "%s detected\n", | |
742 | (pvt->ext_model >= OPTERON_CPU_REV_F) ? | |
743 | "Rev F or later" : "Rev E or earlier"); | |
744 | else | |
745 | /* we'll hardly ever ever get here */ | |
746 | edac_printk(KERN_ERR, EDAC_MC, "Unknown cpu!\n"); | |
747 | } | |
748 | ||
749 | /* | |
750 | * Determine if the DIMMs have ECC enabled. ECC is enabled ONLY if all the DIMMs | |
751 | * are ECC capable. | |
752 | */ | |
753 | static enum edac_type amd64_determine_edac_cap(struct amd64_pvt *pvt) | |
754 | { | |
755 | int bit; | |
756 | enum dev_type edac_cap = EDAC_NONE; | |
757 | ||
758 | bit = (boot_cpu_data.x86 > 0xf || pvt->ext_model >= OPTERON_CPU_REV_F) | |
759 | ? 19 | |
760 | : 17; | |
761 | ||
762 | if (pvt->dclr0 >> BIT(bit)) | |
763 | edac_cap = EDAC_FLAG_SECDED; | |
764 | ||
765 | return edac_cap; | |
766 | } | |
767 | ||
768 | ||
769 | static void f10_debug_display_dimm_sizes(int ctrl, struct amd64_pvt *pvt, | |
770 | int ganged); | |
771 | ||
772 | /* Display and decode various NB registers for debug purposes. */ | |
773 | static void amd64_dump_misc_regs(struct amd64_pvt *pvt) | |
774 | { | |
775 | int ganged; | |
776 | ||
777 | debugf1(" nbcap:0x%8.08x DctDualCap=%s DualNode=%s 8-Node=%s\n", | |
778 | pvt->nbcap, | |
779 | (pvt->nbcap & K8_NBCAP_DCT_DUAL) ? "True" : "False", | |
780 | (pvt->nbcap & K8_NBCAP_DUAL_NODE) ? "True" : "False", | |
781 | (pvt->nbcap & K8_NBCAP_8_NODE) ? "True" : "False"); | |
782 | debugf1(" ECC Capable=%s ChipKill Capable=%s\n", | |
783 | (pvt->nbcap & K8_NBCAP_SECDED) ? "True" : "False", | |
784 | (pvt->nbcap & K8_NBCAP_CHIPKILL) ? "True" : "False"); | |
785 | debugf1(" DramCfg0-low=0x%08x DIMM-ECC=%s Parity=%s Width=%s\n", | |
786 | pvt->dclr0, | |
787 | (pvt->dclr0 & BIT(19)) ? "Enabled" : "Disabled", | |
788 | (pvt->dclr0 & BIT(8)) ? "Enabled" : "Disabled", | |
789 | (pvt->dclr0 & BIT(11)) ? "128b" : "64b"); | |
790 | debugf1(" DIMM x4 Present: L0=%s L1=%s L2=%s L3=%s DIMM Type=%s\n", | |
791 | (pvt->dclr0 & BIT(12)) ? "Y" : "N", | |
792 | (pvt->dclr0 & BIT(13)) ? "Y" : "N", | |
793 | (pvt->dclr0 & BIT(14)) ? "Y" : "N", | |
794 | (pvt->dclr0 & BIT(15)) ? "Y" : "N", | |
795 | (pvt->dclr0 & BIT(16)) ? "UN-Buffered" : "Buffered"); | |
796 | ||
797 | ||
798 | debugf1(" online-spare: 0x%8.08x\n", pvt->online_spare); | |
799 | ||
800 | if (boot_cpu_data.x86 == 0xf) { | |
801 | debugf1(" dhar: 0x%8.08x Base=0x%08x Offset=0x%08x\n", | |
802 | pvt->dhar, dhar_base(pvt->dhar), | |
803 | k8_dhar_offset(pvt->dhar)); | |
804 | debugf1(" DramHoleValid=%s\n", | |
805 | (pvt->dhar & DHAR_VALID) ? "True" : "False"); | |
806 | ||
807 | debugf1(" dbam-dkt: 0x%8.08x\n", pvt->dbam0); | |
808 | ||
809 | /* everything below this point is Fam10h and above */ | |
810 | return; | |
811 | ||
812 | } else { | |
813 | debugf1(" dhar: 0x%8.08x Base=0x%08x Offset=0x%08x\n", | |
814 | pvt->dhar, dhar_base(pvt->dhar), | |
815 | f10_dhar_offset(pvt->dhar)); | |
816 | debugf1(" DramMemHoistValid=%s DramHoleValid=%s\n", | |
817 | (pvt->dhar & F10_DRAM_MEM_HOIST_VALID) ? | |
818 | "True" : "False", | |
819 | (pvt->dhar & DHAR_VALID) ? | |
820 | "True" : "False"); | |
821 | } | |
822 | ||
823 | /* Only if NOT ganged does dcl1 have valid info */ | |
824 | if (!dct_ganging_enabled(pvt)) { | |
825 | debugf1(" DramCfg1-low=0x%08x DIMM-ECC=%s Parity=%s " | |
826 | "Width=%s\n", pvt->dclr1, | |
827 | (pvt->dclr1 & BIT(19)) ? "Enabled" : "Disabled", | |
828 | (pvt->dclr1 & BIT(8)) ? "Enabled" : "Disabled", | |
829 | (pvt->dclr1 & BIT(11)) ? "128b" : "64b"); | |
830 | debugf1(" DIMM x4 Present: L0=%s L1=%s L2=%s L3=%s " | |
831 | "DIMM Type=%s\n", | |
832 | (pvt->dclr1 & BIT(12)) ? "Y" : "N", | |
833 | (pvt->dclr1 & BIT(13)) ? "Y" : "N", | |
834 | (pvt->dclr1 & BIT(14)) ? "Y" : "N", | |
835 | (pvt->dclr1 & BIT(15)) ? "Y" : "N", | |
836 | (pvt->dclr1 & BIT(16)) ? "UN-Buffered" : "Buffered"); | |
837 | } | |
838 | ||
839 | /* | |
840 | * Determine if ganged and then dump memory sizes for first controller, | |
841 | * and if NOT ganged dump info for 2nd controller. | |
842 | */ | |
843 | ganged = dct_ganging_enabled(pvt); | |
844 | ||
845 | f10_debug_display_dimm_sizes(0, pvt, ganged); | |
846 | ||
847 | if (!ganged) | |
848 | f10_debug_display_dimm_sizes(1, pvt, ganged); | |
849 | } | |
850 | ||
851 | /* Read in both of DBAM registers */ | |
852 | static void amd64_read_dbam_reg(struct amd64_pvt *pvt) | |
853 | { | |
854 | int err = 0; | |
855 | unsigned int reg; | |
856 | ||
857 | reg = DBAM0; | |
858 | err = pci_read_config_dword(pvt->dram_f2_ctl, reg, &pvt->dbam0); | |
859 | if (err) | |
860 | goto err_reg; | |
861 | ||
862 | if (boot_cpu_data.x86 >= 0x10) { | |
863 | reg = DBAM1; | |
864 | err = pci_read_config_dword(pvt->dram_f2_ctl, reg, &pvt->dbam1); | |
865 | ||
866 | if (err) | |
867 | goto err_reg; | |
868 | } | |
869 | ||
870 | err_reg: | |
871 | debugf0("Error reading F2x%03x.\n", reg); | |
872 | } | |
873 | ||
94be4bff DT |
874 | /* |
875 | * NOTE: CPU Revision Dependent code: Rev E and Rev F | |
876 | * | |
877 | * Set the DCSB and DCSM mask values depending on the CPU revision value. Also | |
878 | * set the shift factor for the DCSB and DCSM values. | |
879 | * | |
880 | * ->dcs_mask_notused, RevE: | |
881 | * | |
882 | * To find the max InputAddr for the csrow, start with the base address and set | |
883 | * all bits that are "don't care" bits in the test at the start of section | |
884 | * 3.5.4 (p. 84). | |
885 | * | |
886 | * The "don't care" bits are all set bits in the mask and all bits in the gaps | |
887 | * between bit ranges [35:25] and [19:13]. The value REV_E_DCS_NOTUSED_BITS | |
888 | * represents bits [24:20] and [12:0], which are all bits in the above-mentioned | |
889 | * gaps. | |
890 | * | |
891 | * ->dcs_mask_notused, RevF and later: | |
892 | * | |
893 | * To find the max InputAddr for the csrow, start with the base address and set | |
894 | * all bits that are "don't care" bits in the test at the start of NPT section | |
895 | * 4.5.4 (p. 87). | |
896 | * | |
897 | * The "don't care" bits are all set bits in the mask and all bits in the gaps | |
898 | * between bit ranges [36:27] and [21:13]. | |
899 | * | |
900 | * The value REV_F_F1Xh_DCS_NOTUSED_BITS represents bits [26:22] and [12:0], | |
901 | * which are all bits in the above-mentioned gaps. | |
902 | */ | |
903 | static void amd64_set_dct_base_and_mask(struct amd64_pvt *pvt) | |
904 | { | |
905 | if (pvt->ext_model >= OPTERON_CPU_REV_F) { | |
906 | pvt->dcsb_base = REV_F_F1Xh_DCSB_BASE_BITS; | |
907 | pvt->dcsm_mask = REV_F_F1Xh_DCSM_MASK_BITS; | |
908 | pvt->dcs_mask_notused = REV_F_F1Xh_DCS_NOTUSED_BITS; | |
909 | pvt->dcs_shift = REV_F_F1Xh_DCS_SHIFT; | |
910 | ||
911 | switch (boot_cpu_data.x86) { | |
912 | case 0xf: | |
913 | pvt->num_dcsm = REV_F_DCSM_COUNT; | |
914 | break; | |
915 | ||
916 | case 0x10: | |
917 | pvt->num_dcsm = F10_DCSM_COUNT; | |
918 | break; | |
919 | ||
920 | case 0x11: | |
921 | pvt->num_dcsm = F11_DCSM_COUNT; | |
922 | break; | |
923 | ||
924 | default: | |
925 | amd64_printk(KERN_ERR, "Unsupported family!\n"); | |
926 | break; | |
927 | } | |
928 | } else { | |
929 | pvt->dcsb_base = REV_E_DCSB_BASE_BITS; | |
930 | pvt->dcsm_mask = REV_E_DCSM_MASK_BITS; | |
931 | pvt->dcs_mask_notused = REV_E_DCS_NOTUSED_BITS; | |
932 | pvt->dcs_shift = REV_E_DCS_SHIFT; | |
933 | pvt->num_dcsm = REV_E_DCSM_COUNT; | |
934 | } | |
935 | } | |
936 | ||
937 | /* | |
938 | * Function 2 Offset F10_DCSB0; read in the DCS Base and DCS Mask hw registers | |
939 | */ | |
940 | static void amd64_read_dct_base_mask(struct amd64_pvt *pvt) | |
941 | { | |
942 | int cs, reg, err = 0; | |
943 | ||
944 | amd64_set_dct_base_and_mask(pvt); | |
945 | ||
946 | for (cs = 0; cs < CHIPSELECT_COUNT; cs++) { | |
947 | reg = K8_DCSB0 + (cs * 4); | |
948 | err = pci_read_config_dword(pvt->dram_f2_ctl, reg, | |
949 | &pvt->dcsb0[cs]); | |
950 | if (unlikely(err)) | |
951 | debugf0("Reading K8_DCSB0[%d] failed\n", cs); | |
952 | else | |
953 | debugf0(" DCSB0[%d]=0x%08x reg: F2x%x\n", | |
954 | cs, pvt->dcsb0[cs], reg); | |
955 | ||
956 | /* If DCT are NOT ganged, then read in DCT1's base */ | |
957 | if (boot_cpu_data.x86 >= 0x10 && !dct_ganging_enabled(pvt)) { | |
958 | reg = F10_DCSB1 + (cs * 4); | |
959 | err = pci_read_config_dword(pvt->dram_f2_ctl, reg, | |
960 | &pvt->dcsb1[cs]); | |
961 | if (unlikely(err)) | |
962 | debugf0("Reading F10_DCSB1[%d] failed\n", cs); | |
963 | else | |
964 | debugf0(" DCSB1[%d]=0x%08x reg: F2x%x\n", | |
965 | cs, pvt->dcsb1[cs], reg); | |
966 | } else { | |
967 | pvt->dcsb1[cs] = 0; | |
968 | } | |
969 | } | |
970 | ||
971 | for (cs = 0; cs < pvt->num_dcsm; cs++) { | |
972 | reg = K8_DCSB0 + (cs * 4); | |
973 | err = pci_read_config_dword(pvt->dram_f2_ctl, reg, | |
974 | &pvt->dcsm0[cs]); | |
975 | if (unlikely(err)) | |
976 | debugf0("Reading K8_DCSM0 failed\n"); | |
977 | else | |
978 | debugf0(" DCSM0[%d]=0x%08x reg: F2x%x\n", | |
979 | cs, pvt->dcsm0[cs], reg); | |
980 | ||
981 | /* If DCT are NOT ganged, then read in DCT1's mask */ | |
982 | if (boot_cpu_data.x86 >= 0x10 && !dct_ganging_enabled(pvt)) { | |
983 | reg = F10_DCSM1 + (cs * 4); | |
984 | err = pci_read_config_dword(pvt->dram_f2_ctl, reg, | |
985 | &pvt->dcsm1[cs]); | |
986 | if (unlikely(err)) | |
987 | debugf0("Reading F10_DCSM1[%d] failed\n", cs); | |
988 | else | |
989 | debugf0(" DCSM1[%d]=0x%08x reg: F2x%x\n", | |
990 | cs, pvt->dcsm1[cs], reg); | |
991 | } else | |
992 | pvt->dcsm1[cs] = 0; | |
993 | } | |
994 | } | |
995 | ||
996 | static enum mem_type amd64_determine_memory_type(struct amd64_pvt *pvt) | |
997 | { | |
998 | enum mem_type type; | |
999 | ||
1000 | if (boot_cpu_data.x86 >= 0x10 || pvt->ext_model >= OPTERON_CPU_REV_F) { | |
1001 | /* Rev F and later */ | |
1002 | type = (pvt->dclr0 & BIT(16)) ? MEM_DDR2 : MEM_RDDR2; | |
1003 | } else { | |
1004 | /* Rev E and earlier */ | |
1005 | type = (pvt->dclr0 & BIT(18)) ? MEM_DDR : MEM_RDDR; | |
1006 | } | |
1007 | ||
1008 | debugf1(" Memory type is: %s\n", | |
1009 | (type == MEM_DDR2) ? "MEM_DDR2" : | |
1010 | (type == MEM_RDDR2) ? "MEM_RDDR2" : | |
1011 | (type == MEM_DDR) ? "MEM_DDR" : "MEM_RDDR"); | |
1012 | ||
1013 | return type; | |
1014 | } | |
1015 | ||
ddff876d DT |
1016 | /* |
1017 | * Read the DRAM Configuration Low register. It differs between CG, D & E revs | |
1018 | * and the later RevF memory controllers (DDR vs DDR2) | |
1019 | * | |
1020 | * Return: | |
1021 | * number of memory channels in operation | |
1022 | * Pass back: | |
1023 | * contents of the DCL0_LOW register | |
1024 | */ | |
1025 | static int k8_early_channel_count(struct amd64_pvt *pvt) | |
1026 | { | |
1027 | int flag, err = 0; | |
1028 | ||
1029 | err = pci_read_config_dword(pvt->dram_f2_ctl, F10_DCLR_0, &pvt->dclr0); | |
1030 | if (err) | |
1031 | return err; | |
1032 | ||
1033 | if ((boot_cpu_data.x86_model >> 4) >= OPTERON_CPU_REV_F) { | |
1034 | /* RevF (NPT) and later */ | |
1035 | flag = pvt->dclr0 & F10_WIDTH_128; | |
1036 | } else { | |
1037 | /* RevE and earlier */ | |
1038 | flag = pvt->dclr0 & REVE_WIDTH_128; | |
1039 | } | |
1040 | ||
1041 | /* not used */ | |
1042 | pvt->dclr1 = 0; | |
1043 | ||
1044 | return (flag) ? 2 : 1; | |
1045 | } | |
1046 | ||
1047 | /* extract the ERROR ADDRESS for the K8 CPUs */ | |
1048 | static u64 k8_get_error_address(struct mem_ctl_info *mci, | |
1049 | struct amd64_error_info_regs *info) | |
1050 | { | |
1051 | return (((u64) (info->nbeah & 0xff)) << 32) + | |
1052 | (info->nbeal & ~0x03); | |
1053 | } | |
1054 | ||
1055 | /* | |
1056 | * Read the Base and Limit registers for K8 based Memory controllers; extract | |
1057 | * fields from the 'raw' reg into separate data fields | |
1058 | * | |
1059 | * Isolates: BASE, LIMIT, IntlvEn, IntlvSel, RW_EN | |
1060 | */ | |
1061 | static void k8_read_dram_base_limit(struct amd64_pvt *pvt, int dram) | |
1062 | { | |
1063 | u32 low; | |
1064 | u32 off = dram << 3; /* 8 bytes between DRAM entries */ | |
1065 | int err; | |
1066 | ||
1067 | err = pci_read_config_dword(pvt->addr_f1_ctl, | |
1068 | K8_DRAM_BASE_LOW + off, &low); | |
1069 | if (err) | |
1070 | debugf0("Reading K8_DRAM_BASE_LOW failed\n"); | |
1071 | ||
1072 | /* Extract parts into separate data entries */ | |
1073 | pvt->dram_base[dram] = ((u64) low & 0xFFFF0000) << 8; | |
1074 | pvt->dram_IntlvEn[dram] = (low >> 8) & 0x7; | |
1075 | pvt->dram_rw_en[dram] = (low & 0x3); | |
1076 | ||
1077 | err = pci_read_config_dword(pvt->addr_f1_ctl, | |
1078 | K8_DRAM_LIMIT_LOW + off, &low); | |
1079 | if (err) | |
1080 | debugf0("Reading K8_DRAM_LIMIT_LOW failed\n"); | |
1081 | ||
1082 | /* | |
1083 | * Extract parts into separate data entries. Limit is the HIGHEST memory | |
1084 | * location of the region, so lower 24 bits need to be all ones | |
1085 | */ | |
1086 | pvt->dram_limit[dram] = (((u64) low & 0xFFFF0000) << 8) | 0x00FFFFFF; | |
1087 | pvt->dram_IntlvSel[dram] = (low >> 8) & 0x7; | |
1088 | pvt->dram_DstNode[dram] = (low & 0x7); | |
1089 | } | |
1090 | ||
1091 | static void k8_map_sysaddr_to_csrow(struct mem_ctl_info *mci, | |
1092 | struct amd64_error_info_regs *info, | |
1093 | u64 SystemAddress) | |
1094 | { | |
1095 | struct mem_ctl_info *src_mci; | |
1096 | unsigned short syndrome; | |
1097 | int channel, csrow; | |
1098 | u32 page, offset; | |
1099 | ||
1100 | /* Extract the syndrome parts and form a 16-bit syndrome */ | |
1101 | syndrome = EXTRACT_HIGH_SYNDROME(info->nbsl) << 8; | |
1102 | syndrome |= EXTRACT_LOW_SYNDROME(info->nbsh); | |
1103 | ||
1104 | /* CHIPKILL enabled */ | |
1105 | if (info->nbcfg & K8_NBCFG_CHIPKILL) { | |
1106 | channel = get_channel_from_ecc_syndrome(syndrome); | |
1107 | if (channel < 0) { | |
1108 | /* | |
1109 | * Syndrome didn't map, so we don't know which of the | |
1110 | * 2 DIMMs is in error. So we need to ID 'both' of them | |
1111 | * as suspect. | |
1112 | */ | |
1113 | amd64_mc_printk(mci, KERN_WARNING, | |
1114 | "unknown syndrome 0x%x - possible error " | |
1115 | "reporting race\n", syndrome); | |
1116 | edac_mc_handle_ce_no_info(mci, EDAC_MOD_STR); | |
1117 | return; | |
1118 | } | |
1119 | } else { | |
1120 | /* | |
1121 | * non-chipkill ecc mode | |
1122 | * | |
1123 | * The k8 documentation is unclear about how to determine the | |
1124 | * channel number when using non-chipkill memory. This method | |
1125 | * was obtained from email communication with someone at AMD. | |
1126 | * (Wish the email was placed in this comment - norsk) | |
1127 | */ | |
1128 | channel = ((SystemAddress & BIT(3)) != 0); | |
1129 | } | |
1130 | ||
1131 | /* | |
1132 | * Find out which node the error address belongs to. This may be | |
1133 | * different from the node that detected the error. | |
1134 | */ | |
1135 | src_mci = find_mc_by_sys_addr(mci, SystemAddress); | |
1136 | if (src_mci) { | |
1137 | amd64_mc_printk(mci, KERN_ERR, | |
1138 | "failed to map error address 0x%lx to a node\n", | |
1139 | (unsigned long)SystemAddress); | |
1140 | edac_mc_handle_ce_no_info(mci, EDAC_MOD_STR); | |
1141 | return; | |
1142 | } | |
1143 | ||
1144 | /* Now map the SystemAddress to a CSROW */ | |
1145 | csrow = sys_addr_to_csrow(src_mci, SystemAddress); | |
1146 | if (csrow < 0) { | |
1147 | edac_mc_handle_ce_no_info(src_mci, EDAC_MOD_STR); | |
1148 | } else { | |
1149 | error_address_to_page_and_offset(SystemAddress, &page, &offset); | |
1150 | ||
1151 | edac_mc_handle_ce(src_mci, page, offset, syndrome, csrow, | |
1152 | channel, EDAC_MOD_STR); | |
1153 | } | |
1154 | } | |
1155 | ||
1156 | /* | |
1157 | * determrine the number of PAGES in for this DIMM's size based on its DRAM | |
1158 | * Address Mapping. | |
1159 | * | |
1160 | * First step is to calc the number of bits to shift a value of 1 left to | |
1161 | * indicate show many pages. Start with the DBAM value as the starting bits, | |
1162 | * then proceed to adjust those shift bits, based on CPU rev and the table. | |
1163 | * See BKDG on the DBAM | |
1164 | */ | |
1165 | static int k8_dbam_map_to_pages(struct amd64_pvt *pvt, int dram_map) | |
1166 | { | |
1167 | int nr_pages; | |
1168 | ||
1169 | if (pvt->ext_model >= OPTERON_CPU_REV_F) { | |
1170 | nr_pages = 1 << (revf_quad_ddr2_shift[dram_map] - PAGE_SHIFT); | |
1171 | } else { | |
1172 | /* | |
1173 | * RevE and less section; this line is tricky. It collapses the | |
1174 | * table used by RevD and later to one that matches revisions CG | |
1175 | * and earlier. | |
1176 | */ | |
1177 | dram_map -= (pvt->ext_model >= OPTERON_CPU_REV_D) ? | |
1178 | (dram_map > 8 ? 4 : (dram_map > 5 ? | |
1179 | 3 : (dram_map > 2 ? 1 : 0))) : 0; | |
1180 | ||
1181 | /* 25 shift is 32MiB minimum DIMM size in RevE and prior */ | |
1182 | nr_pages = 1 << (dram_map + 25 - PAGE_SHIFT); | |
1183 | } | |
1184 | ||
1185 | return nr_pages; | |
1186 | } | |
1187 | ||
1afd3c98 DT |
1188 | /* |
1189 | * Get the number of DCT channels in use. | |
1190 | * | |
1191 | * Return: | |
1192 | * number of Memory Channels in operation | |
1193 | * Pass back: | |
1194 | * contents of the DCL0_LOW register | |
1195 | */ | |
1196 | static int f10_early_channel_count(struct amd64_pvt *pvt) | |
1197 | { | |
1198 | int err = 0, channels = 0; | |
1199 | u32 dbam; | |
1200 | ||
1201 | err = pci_read_config_dword(pvt->dram_f2_ctl, F10_DCLR_0, &pvt->dclr0); | |
1202 | if (err) | |
1203 | goto err_reg; | |
1204 | ||
1205 | err = pci_read_config_dword(pvt->dram_f2_ctl, F10_DCLR_1, &pvt->dclr1); | |
1206 | if (err) | |
1207 | goto err_reg; | |
1208 | ||
1209 | /* If we are in 128 bit mode, then we are using 2 channels */ | |
1210 | if (pvt->dclr0 & F10_WIDTH_128) { | |
1211 | debugf0("Data WIDTH is 128 bits - 2 channels\n"); | |
1212 | channels = 2; | |
1213 | return channels; | |
1214 | } | |
1215 | ||
1216 | /* | |
1217 | * Need to check if in UN-ganged mode: In such, there are 2 channels, | |
1218 | * but they are NOT in 128 bit mode and thus the above 'dcl0' status bit | |
1219 | * will be OFF. | |
1220 | * | |
1221 | * Need to check DCT0[0] and DCT1[0] to see if only one of them has | |
1222 | * their CSEnable bit on. If so, then SINGLE DIMM case. | |
1223 | */ | |
1224 | debugf0("Data WIDTH is NOT 128 bits - need more decoding\n"); | |
ddff876d | 1225 | |
1afd3c98 DT |
1226 | /* |
1227 | * Check DRAM Bank Address Mapping values for each DIMM to see if there | |
1228 | * is more than just one DIMM present in unganged mode. Need to check | |
1229 | * both controllers since DIMMs can be placed in either one. | |
1230 | */ | |
1231 | channels = 0; | |
1232 | err = pci_read_config_dword(pvt->dram_f2_ctl, DBAM0, &dbam); | |
1233 | if (err) | |
1234 | goto err_reg; | |
1235 | ||
1236 | if (DBAM_DIMM(0, dbam) > 0) | |
1237 | channels++; | |
1238 | if (DBAM_DIMM(1, dbam) > 0) | |
1239 | channels++; | |
1240 | if (DBAM_DIMM(2, dbam) > 0) | |
1241 | channels++; | |
1242 | if (DBAM_DIMM(3, dbam) > 0) | |
1243 | channels++; | |
1244 | ||
1245 | /* If more than 2 DIMMs are present, then we have 2 channels */ | |
1246 | if (channels > 2) | |
1247 | channels = 2; | |
1248 | else if (channels == 0) { | |
1249 | /* No DIMMs on DCT0, so look at DCT1 */ | |
1250 | err = pci_read_config_dword(pvt->dram_f2_ctl, DBAM1, &dbam); | |
1251 | if (err) | |
1252 | goto err_reg; | |
1253 | ||
1254 | if (DBAM_DIMM(0, dbam) > 0) | |
1255 | channels++; | |
1256 | if (DBAM_DIMM(1, dbam) > 0) | |
1257 | channels++; | |
1258 | if (DBAM_DIMM(2, dbam) > 0) | |
1259 | channels++; | |
1260 | if (DBAM_DIMM(3, dbam) > 0) | |
1261 | channels++; | |
1262 | ||
1263 | if (channels > 2) | |
1264 | channels = 2; | |
1265 | } | |
1266 | ||
1267 | /* If we found ALL 0 values, then assume just ONE DIMM-ONE Channel */ | |
1268 | if (channels == 0) | |
1269 | channels = 1; | |
1270 | ||
1271 | debugf0("DIMM count= %d\n", channels); | |
1272 | ||
1273 | return channels; | |
1274 | ||
1275 | err_reg: | |
1276 | return -1; | |
1277 | ||
1278 | } | |
1279 | ||
1280 | static int f10_dbam_map_to_pages(struct amd64_pvt *pvt, int dram_map) | |
1281 | { | |
1282 | return 1 << (revf_quad_ddr2_shift[dram_map] - PAGE_SHIFT); | |
1283 | } | |
1284 | ||
1285 | /* Enable extended configuration access via 0xCF8 feature */ | |
1286 | static void amd64_setup(struct amd64_pvt *pvt) | |
1287 | { | |
1288 | u32 reg; | |
1289 | ||
1290 | pci_read_config_dword(pvt->misc_f3_ctl, F10_NB_CFG_HIGH, ®); | |
1291 | ||
1292 | pvt->flags.cf8_extcfg = !!(reg & F10_NB_CFG_LOW_ENABLE_EXT_CFG); | |
1293 | reg |= F10_NB_CFG_LOW_ENABLE_EXT_CFG; | |
1294 | pci_write_config_dword(pvt->misc_f3_ctl, F10_NB_CFG_HIGH, reg); | |
1295 | } | |
1296 | ||
1297 | /* Restore the extended configuration access via 0xCF8 feature */ | |
1298 | static void amd64_teardown(struct amd64_pvt *pvt) | |
1299 | { | |
1300 | u32 reg; | |
1301 | ||
1302 | pci_read_config_dword(pvt->misc_f3_ctl, F10_NB_CFG_HIGH, ®); | |
1303 | ||
1304 | reg &= ~F10_NB_CFG_LOW_ENABLE_EXT_CFG; | |
1305 | if (pvt->flags.cf8_extcfg) | |
1306 | reg |= F10_NB_CFG_LOW_ENABLE_EXT_CFG; | |
1307 | pci_write_config_dword(pvt->misc_f3_ctl, F10_NB_CFG_HIGH, reg); | |
1308 | } | |
1309 | ||
1310 | static u64 f10_get_error_address(struct mem_ctl_info *mci, | |
1311 | struct amd64_error_info_regs *info) | |
1312 | { | |
1313 | return (((u64) (info->nbeah & 0xffff)) << 32) + | |
1314 | (info->nbeal & ~0x01); | |
1315 | } | |
1316 | ||
1317 | /* | |
1318 | * Read the Base and Limit registers for F10 based Memory controllers. Extract | |
1319 | * fields from the 'raw' reg into separate data fields. | |
1320 | * | |
1321 | * Isolates: BASE, LIMIT, IntlvEn, IntlvSel, RW_EN. | |
1322 | */ | |
1323 | static void f10_read_dram_base_limit(struct amd64_pvt *pvt, int dram) | |
1324 | { | |
1325 | u32 high_offset, low_offset, high_base, low_base, high_limit, low_limit; | |
1326 | ||
1327 | low_offset = K8_DRAM_BASE_LOW + (dram << 3); | |
1328 | high_offset = F10_DRAM_BASE_HIGH + (dram << 3); | |
1329 | ||
1330 | /* read the 'raw' DRAM BASE Address register */ | |
1331 | pci_read_config_dword(pvt->addr_f1_ctl, low_offset, &low_base); | |
1332 | ||
1333 | /* Read from the ECS data register */ | |
1334 | pci_read_config_dword(pvt->addr_f1_ctl, high_offset, &high_base); | |
1335 | ||
1336 | /* Extract parts into separate data entries */ | |
1337 | pvt->dram_rw_en[dram] = (low_base & 0x3); | |
1338 | ||
1339 | if (pvt->dram_rw_en[dram] == 0) | |
1340 | return; | |
1341 | ||
1342 | pvt->dram_IntlvEn[dram] = (low_base >> 8) & 0x7; | |
1343 | ||
1344 | pvt->dram_base[dram] = (((((u64) high_base & 0x000000FF) << 32) | | |
1345 | ((u64) low_base & 0xFFFF0000))) << 8; | |
1346 | ||
1347 | low_offset = K8_DRAM_LIMIT_LOW + (dram << 3); | |
1348 | high_offset = F10_DRAM_LIMIT_HIGH + (dram << 3); | |
1349 | ||
1350 | /* read the 'raw' LIMIT registers */ | |
1351 | pci_read_config_dword(pvt->addr_f1_ctl, low_offset, &low_limit); | |
1352 | ||
1353 | /* Read from the ECS data register for the HIGH portion */ | |
1354 | pci_read_config_dword(pvt->addr_f1_ctl, high_offset, &high_limit); | |
1355 | ||
1356 | debugf0(" HW Regs: BASE=0x%08x-%08x LIMIT= 0x%08x-%08x\n", | |
1357 | high_base, low_base, high_limit, low_limit); | |
1358 | ||
1359 | pvt->dram_DstNode[dram] = (low_limit & 0x7); | |
1360 | pvt->dram_IntlvSel[dram] = (low_limit >> 8) & 0x7; | |
1361 | ||
1362 | /* | |
1363 | * Extract address values and form a LIMIT address. Limit is the HIGHEST | |
1364 | * memory location of the region, so low 24 bits need to be all ones. | |
1365 | */ | |
1366 | low_limit |= 0x0000FFFF; | |
1367 | pvt->dram_limit[dram] = | |
1368 | ((((u64) high_limit << 32) + (u64) low_limit) << 8) | (0xFF); | |
1369 | } | |
6163b5d4 DT |
1370 | |
1371 | static void f10_read_dram_ctl_register(struct amd64_pvt *pvt) | |
1372 | { | |
1373 | int err = 0; | |
1374 | ||
1375 | err = pci_read_config_dword(pvt->dram_f2_ctl, F10_DCTL_SEL_LOW, | |
1376 | &pvt->dram_ctl_select_low); | |
1377 | if (err) { | |
1378 | debugf0("Reading F10_DCTL_SEL_LOW failed\n"); | |
1379 | } else { | |
1380 | debugf0("DRAM_DCTL_SEL_LOW=0x%x DctSelBaseAddr=0x%x\n", | |
1381 | pvt->dram_ctl_select_low, dct_sel_baseaddr(pvt)); | |
1382 | ||
1383 | debugf0(" DRAM DCTs are=%s DRAM Is=%s DRAM-Ctl-" | |
1384 | "sel-hi-range=%s\n", | |
1385 | (dct_ganging_enabled(pvt) ? "GANGED" : "NOT GANGED"), | |
1386 | (dct_dram_enabled(pvt) ? "Enabled" : "Disabled"), | |
1387 | (dct_high_range_enabled(pvt) ? "Enabled" : "Disabled")); | |
1388 | ||
1389 | debugf0(" DctDatIntLv=%s MemCleared=%s DctSelIntLvAddr=0x%x\n", | |
1390 | (dct_data_intlv_enabled(pvt) ? "Enabled" : "Disabled"), | |
1391 | (dct_memory_cleared(pvt) ? "True " : "False "), | |
1392 | dct_sel_interleave_addr(pvt)); | |
1393 | } | |
1394 | ||
1395 | err = pci_read_config_dword(pvt->dram_f2_ctl, F10_DCTL_SEL_HIGH, | |
1396 | &pvt->dram_ctl_select_high); | |
1397 | if (err) | |
1398 | debugf0("Reading F10_DCTL_SEL_HIGH failed\n"); | |
1399 | } | |
1400 | ||
1401 | static u32 f10_determine_channel(struct amd64_pvt *pvt, u64 sys_addr, | |
1402 | int hi_range_sel, u32 intlv_en) | |
1403 | { | |
1404 | u32 cs, temp, dct_sel_high = (pvt->dram_ctl_select_low >> 1) & 1; | |
1405 | ||
1406 | if (dct_ganging_enabled(pvt)) | |
1407 | cs = 0; | |
1408 | else if (hi_range_sel) | |
1409 | cs = dct_sel_high; | |
1410 | else if (dct_interleave_enabled(pvt)) { | |
1411 | if (dct_sel_interleave_addr(pvt) == 0) | |
1412 | cs = sys_addr >> 6 & 1; | |
1413 | else if ((dct_sel_interleave_addr(pvt) >> 1) & 1) { | |
1414 | temp = hweight_long((u32) ((sys_addr >> 16) & 0x1F)) % 2; | |
1415 | ||
1416 | if (dct_sel_interleave_addr(pvt) & 1) | |
1417 | cs = (sys_addr >> 9 & 1) ^ temp; | |
1418 | else | |
1419 | cs = (sys_addr >> 6 & 1) ^ temp; | |
1420 | } else if (intlv_en & 4) | |
1421 | cs = sys_addr >> 15 & 1; | |
1422 | else if (intlv_en & 2) | |
1423 | cs = sys_addr >> 14 & 1; | |
1424 | else if (intlv_en & 1) | |
1425 | cs = sys_addr >> 13 & 1; | |
1426 | else | |
1427 | cs = sys_addr >> 12 & 1; | |
1428 | } else if (dct_high_range_enabled(pvt) && !dct_ganging_enabled(pvt)) | |
1429 | cs = ~dct_sel_high & 1; | |
1430 | else | |
1431 | cs = 0; | |
1432 | ||
1433 | return cs; | |
1434 | } | |
1435 | ||
1436 | static inline u32 f10_map_intlv_en_to_shift(u32 intlv_en) | |
1437 | { | |
1438 | if (intlv_en == 1) | |
1439 | return 1; | |
1440 | else if (intlv_en == 3) | |
1441 | return 2; | |
1442 | else if (intlv_en == 7) | |
1443 | return 3; | |
1444 | ||
1445 | return 0; | |
1446 | } | |
1447 | ||
1448 | static inline u64 f10_determine_base_addr_offset(u64 sys_addr, int hi_range_sel, | |
1449 | u32 dct_sel_base_addr, | |
1450 | u64 dct_sel_base_off, | |
1451 | u32 hole_en, u32 hole_off, | |
1452 | u64 dram_base) | |
1453 | { | |
1454 | u64 chan_off; | |
1455 | ||
1456 | if (hi_range_sel) { | |
1457 | if (!(dct_sel_base_addr & 0xFFFFF800) && | |
1458 | (hole_en & 1) && (sys_addr >= 0x100000000ULL)) | |
1459 | chan_off = hole_off << 16; | |
1460 | else | |
1461 | chan_off = dct_sel_base_off; | |
1462 | } else { | |
1463 | if ((hole_en & 1) && (sys_addr >= 0x100000000ULL)) | |
1464 | chan_off = hole_off << 16; | |
1465 | else | |
1466 | chan_off = dram_base & 0xFFFFF8000000ULL; | |
1467 | } | |
1468 | ||
1469 | return (sys_addr & 0x0000FFFFFFFFFFC0ULL) - | |
1470 | (chan_off & 0x0000FFFFFF800000ULL); | |
1471 | } | |
1472 | ||
1473 | /* Hack for the time being - Can we get this from BIOS?? */ | |
1474 | #define CH0SPARE_RANK 0 | |
1475 | #define CH1SPARE_RANK 1 | |
1476 | ||
1477 | /* | |
1478 | * checks if the csrow passed in is marked as SPARED, if so returns the new | |
1479 | * spare row | |
1480 | */ | |
1481 | static inline int f10_process_possible_spare(int csrow, | |
1482 | u32 cs, struct amd64_pvt *pvt) | |
1483 | { | |
1484 | u32 swap_done; | |
1485 | u32 bad_dram_cs; | |
1486 | ||
1487 | /* Depending on channel, isolate respective SPARING info */ | |
1488 | if (cs) { | |
1489 | swap_done = F10_ONLINE_SPARE_SWAPDONE1(pvt->online_spare); | |
1490 | bad_dram_cs = F10_ONLINE_SPARE_BADDRAM_CS1(pvt->online_spare); | |
1491 | if (swap_done && (csrow == bad_dram_cs)) | |
1492 | csrow = CH1SPARE_RANK; | |
1493 | } else { | |
1494 | swap_done = F10_ONLINE_SPARE_SWAPDONE0(pvt->online_spare); | |
1495 | bad_dram_cs = F10_ONLINE_SPARE_BADDRAM_CS0(pvt->online_spare); | |
1496 | if (swap_done && (csrow == bad_dram_cs)) | |
1497 | csrow = CH0SPARE_RANK; | |
1498 | } | |
1499 | return csrow; | |
1500 | } | |
1501 | ||
1502 | /* | |
1503 | * Iterate over the DRAM DCT "base" and "mask" registers looking for a | |
1504 | * SystemAddr match on the specified 'ChannelSelect' and 'NodeID' | |
1505 | * | |
1506 | * Return: | |
1507 | * -EINVAL: NOT FOUND | |
1508 | * 0..csrow = Chip-Select Row | |
1509 | */ | |
1510 | static int f10_lookup_addr_in_dct(u32 in_addr, u32 nid, u32 cs) | |
1511 | { | |
1512 | struct mem_ctl_info *mci; | |
1513 | struct amd64_pvt *pvt; | |
1514 | u32 cs_base, cs_mask; | |
1515 | int cs_found = -EINVAL; | |
1516 | int csrow; | |
1517 | ||
1518 | mci = mci_lookup[nid]; | |
1519 | if (!mci) | |
1520 | return cs_found; | |
1521 | ||
1522 | pvt = mci->pvt_info; | |
1523 | ||
1524 | debugf1("InputAddr=0x%x channelselect=%d\n", in_addr, cs); | |
1525 | ||
1526 | for (csrow = 0; csrow < CHIPSELECT_COUNT; csrow++) { | |
1527 | ||
1528 | cs_base = amd64_get_dct_base(pvt, cs, csrow); | |
1529 | if (!(cs_base & K8_DCSB_CS_ENABLE)) | |
1530 | continue; | |
1531 | ||
1532 | /* | |
1533 | * We have an ENABLED CSROW, Isolate just the MASK bits of the | |
1534 | * target: [28:19] and [13:5], which map to [36:27] and [21:13] | |
1535 | * of the actual address. | |
1536 | */ | |
1537 | cs_base &= REV_F_F1Xh_DCSB_BASE_BITS; | |
1538 | ||
1539 | /* | |
1540 | * Get the DCT Mask, and ENABLE the reserved bits: [18:16] and | |
1541 | * [4:0] to become ON. Then mask off bits [28:0] ([36:8]) | |
1542 | */ | |
1543 | cs_mask = amd64_get_dct_mask(pvt, cs, csrow); | |
1544 | ||
1545 | debugf1(" CSROW=%d CSBase=0x%x RAW CSMask=0x%x\n", | |
1546 | csrow, cs_base, cs_mask); | |
1547 | ||
1548 | cs_mask = (cs_mask | 0x0007C01F) & 0x1FFFFFFF; | |
1549 | ||
1550 | debugf1(" Final CSMask=0x%x\n", cs_mask); | |
1551 | debugf1(" (InputAddr & ~CSMask)=0x%x " | |
1552 | "(CSBase & ~CSMask)=0x%x\n", | |
1553 | (in_addr & ~cs_mask), (cs_base & ~cs_mask)); | |
1554 | ||
1555 | if ((in_addr & ~cs_mask) == (cs_base & ~cs_mask)) { | |
1556 | cs_found = f10_process_possible_spare(csrow, cs, pvt); | |
1557 | ||
1558 | debugf1(" MATCH csrow=%d\n", cs_found); | |
1559 | break; | |
1560 | } | |
1561 | } | |
1562 | return cs_found; | |
1563 | } | |
1564 | ||
1565 |