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1 | /* |
2 | * AMD64 class Memory Controller kernel module | |
3 | * | |
4 | * Copyright (c) 2009 SoftwareBitMaker. | |
5 | * Copyright (c) 2009 Advanced Micro Devices, Inc. | |
6 | * | |
7 | * This file may be distributed under the terms of the | |
8 | * GNU General Public License. | |
9 | * | |
10 | * Originally Written by Thayne Harbaugh | |
11 | * | |
12 | * Changes by Douglas "norsk" Thompson <dougthompson@xmission.com>: | |
13 | * - K8 CPU Revision D and greater support | |
14 | * | |
15 | * Changes by Dave Peterson <dsp@llnl.gov> <dave_peterson@pobox.com>: | |
16 | * - Module largely rewritten, with new (and hopefully correct) | |
17 | * code for dealing with node and chip select interleaving, | |
18 | * various code cleanup, and bug fixes | |
19 | * - Added support for memory hoisting using DRAM hole address | |
20 | * register | |
21 | * | |
22 | * Changes by Douglas "norsk" Thompson <dougthompson@xmission.com>: | |
23 | * -K8 Rev (1207) revision support added, required Revision | |
24 | * specific mini-driver code to support Rev F as well as | |
25 | * prior revisions | |
26 | * | |
27 | * Changes by Douglas "norsk" Thompson <dougthompson@xmission.com>: | |
28 | * -Family 10h revision support added. New PCI Device IDs, | |
29 | * indicating new changes. Actual registers modified | |
30 | * were slight, less than the Rev E to Rev F transition | |
31 | * but changing the PCI Device ID was the proper thing to | |
32 | * do, as it provides for almost automactic family | |
33 | * detection. The mods to Rev F required more family | |
34 | * information detection. | |
35 | * | |
36 | * Changes/Fixes by Borislav Petkov <borislav.petkov@amd.com>: | |
37 | * - misc fixes and code cleanups | |
38 | * | |
39 | * This module is based on the following documents | |
40 | * (available from http://www.amd.com/): | |
41 | * | |
42 | * Title: BIOS and Kernel Developer's Guide for AMD Athlon 64 and AMD | |
43 | * Opteron Processors | |
44 | * AMD publication #: 26094 | |
45 | *` Revision: 3.26 | |
46 | * | |
47 | * Title: BIOS and Kernel Developer's Guide for AMD NPT Family 0Fh | |
48 | * Processors | |
49 | * AMD publication #: 32559 | |
50 | * Revision: 3.00 | |
51 | * Issue Date: May 2006 | |
52 | * | |
53 | * Title: BIOS and Kernel Developer's Guide (BKDG) For AMD Family 10h | |
54 | * Processors | |
55 | * AMD publication #: 31116 | |
56 | * Revision: 3.00 | |
57 | * Issue Date: September 07, 2007 | |
58 | * | |
59 | * Sections in the first 2 documents are no longer in sync with each other. | |
60 | * The Family 10h BKDG was totally re-written from scratch with a new | |
61 | * presentation model. | |
62 | * Therefore, comments that refer to a Document section might be off. | |
63 | */ | |
64 | ||
65 | #include <linux/module.h> | |
66 | #include <linux/ctype.h> | |
67 | #include <linux/init.h> | |
68 | #include <linux/pci.h> | |
69 | #include <linux/pci_ids.h> | |
70 | #include <linux/slab.h> | |
71 | #include <linux/mmzone.h> | |
72 | #include <linux/edac.h> | |
73 | #include "edac_core.h" | |
74 | ||
75 | #define amd64_printk(level, fmt, arg...) \ | |
76 | edac_printk(level, "amd64", fmt, ##arg) | |
77 | ||
78 | #define amd64_mc_printk(mci, level, fmt, arg...) \ | |
79 | edac_mc_chipset_printk(mci, level, "amd64", fmt, ##arg) | |
80 | ||
81 | /* | |
82 | * Throughout the comments in this code, the following terms are used: | |
83 | * | |
84 | * SysAddr, DramAddr, and InputAddr | |
85 | * | |
86 | * These terms come directly from the amd64 documentation | |
87 | * (AMD publication #26094). They are defined as follows: | |
88 | * | |
89 | * SysAddr: | |
90 | * This is a physical address generated by a CPU core or a device | |
91 | * doing DMA. If generated by a CPU core, a SysAddr is the result of | |
92 | * a virtual to physical address translation by the CPU core's address | |
93 | * translation mechanism (MMU). | |
94 | * | |
95 | * DramAddr: | |
96 | * A DramAddr is derived from a SysAddr by subtracting an offset that | |
97 | * depends on which node the SysAddr maps to and whether the SysAddr | |
98 | * is within a range affected by memory hoisting. The DRAM Base | |
99 | * (section 3.4.4.1) and DRAM Limit (section 3.4.4.2) registers | |
100 | * determine which node a SysAddr maps to. | |
101 | * | |
102 | * If the DRAM Hole Address Register (DHAR) is enabled and the SysAddr | |
103 | * is within the range of addresses specified by this register, then | |
104 | * a value x from the DHAR is subtracted from the SysAddr to produce a | |
105 | * DramAddr. Here, x represents the base address for the node that | |
106 | * the SysAddr maps to plus an offset due to memory hoisting. See | |
107 | * section 3.4.8 and the comments in amd64_get_dram_hole_info() and | |
108 | * sys_addr_to_dram_addr() below for more information. | |
109 | * | |
110 | * If the SysAddr is not affected by the DHAR then a value y is | |
111 | * subtracted from the SysAddr to produce a DramAddr. Here, y is the | |
112 | * base address for the node that the SysAddr maps to. See section | |
113 | * 3.4.4 and the comments in sys_addr_to_dram_addr() below for more | |
114 | * information. | |
115 | * | |
116 | * InputAddr: | |
117 | * A DramAddr is translated to an InputAddr before being passed to the | |
118 | * memory controller for the node that the DramAddr is associated | |
119 | * with. The memory controller then maps the InputAddr to a csrow. | |
120 | * If node interleaving is not in use, then the InputAddr has the same | |
121 | * value as the DramAddr. Otherwise, the InputAddr is produced by | |
122 | * discarding the bits used for node interleaving from the DramAddr. | |
123 | * See section 3.4.4 for more information. | |
124 | * | |
125 | * The memory controller for a given node uses its DRAM CS Base and | |
126 | * DRAM CS Mask registers to map an InputAddr to a csrow. See | |
127 | * sections 3.5.4 and 3.5.5 for more information. | |
128 | */ | |
129 | ||
130 | #define EDAC_AMD64_VERSION " Ver: 3.2.0 " __DATE__ | |
131 | #define EDAC_MOD_STR "amd64_edac" | |
132 | ||
133 | /* Extended Model from CPUID, for CPU Revision numbers */ | |
134 | #define OPTERON_CPU_LE_REV_C 0 | |
135 | #define OPTERON_CPU_REV_D 1 | |
136 | #define OPTERON_CPU_REV_E 2 | |
137 | ||
138 | /* NPT processors have the following Extended Models */ | |
139 | #define OPTERON_CPU_REV_F 4 | |
140 | #define OPTERON_CPU_REV_FA 5 | |
141 | ||
142 | /* Hardware limit on ChipSelect rows per MC and processors per system */ | |
143 | #define CHIPSELECT_COUNT 8 | |
144 | #define DRAM_REG_COUNT 8 | |
145 | ||
146 | ||
147 | /* | |
148 | * PCI-defined configuration space registers | |
149 | */ | |
150 | ||
151 | ||
152 | /* | |
153 | * Function 1 - Address Map | |
154 | */ | |
155 | #define K8_DRAM_BASE_LOW 0x40 | |
156 | #define K8_DRAM_LIMIT_LOW 0x44 | |
157 | #define K8_DHAR 0xf0 | |
158 | ||
159 | #define DHAR_VALID BIT(0) | |
160 | #define F10_DRAM_MEM_HOIST_VALID BIT(1) | |
161 | ||
162 | #define DHAR_BASE_MASK 0xff000000 | |
163 | #define dhar_base(dhar) (dhar & DHAR_BASE_MASK) | |
164 | ||
165 | #define K8_DHAR_OFFSET_MASK 0x0000ff00 | |
166 | #define k8_dhar_offset(dhar) ((dhar & K8_DHAR_OFFSET_MASK) << 16) | |
167 | ||
168 | #define F10_DHAR_OFFSET_MASK 0x0000ff80 | |
169 | /* NOTE: Extra mask bit vs K8 */ | |
170 | #define f10_dhar_offset(dhar) ((dhar & F10_DHAR_OFFSET_MASK) << 16) | |
171 | ||
172 | ||
173 | /* F10 High BASE/LIMIT registers */ | |
174 | #define F10_DRAM_BASE_HIGH 0x140 | |
175 | #define F10_DRAM_LIMIT_HIGH 0x144 | |
176 | ||
177 | ||
178 | /* | |
179 | * Function 2 - DRAM controller | |
180 | */ | |
181 | #define K8_DCSB0 0x40 | |
182 | #define F10_DCSB1 0x140 | |
183 | ||
184 | #define K8_DCSB_CS_ENABLE BIT(0) | |
185 | #define K8_DCSB_NPT_SPARE BIT(1) | |
186 | #define K8_DCSB_NPT_TESTFAIL BIT(2) | |
187 | ||
188 | /* | |
189 | * REV E: select [31:21] and [15:9] from DCSB and the shift amount to form | |
190 | * the address | |
191 | */ | |
192 | #define REV_E_DCSB_BASE_BITS (0xFFE0FE00ULL) | |
193 | #define REV_E_DCS_SHIFT 4 | |
194 | #define REV_E_DCSM_COUNT 8 | |
195 | ||
196 | #define REV_F_F1Xh_DCSB_BASE_BITS (0x1FF83FE0ULL) | |
197 | #define REV_F_F1Xh_DCS_SHIFT 8 | |
198 | ||
199 | /* | |
200 | * REV F and later: selects [28:19] and [13:5] from DCSB and the shift amount | |
201 | * to form the address | |
202 | */ | |
203 | #define REV_F_DCSB_BASE_BITS (0x1FF83FE0ULL) | |
204 | #define REV_F_DCS_SHIFT 8 | |
205 | #define REV_F_DCSM_COUNT 4 | |
206 | #define F10_DCSM_COUNT 4 | |
207 | #define F11_DCSM_COUNT 2 | |
208 | ||
209 | /* DRAM CS Mask Registers */ | |
210 | #define K8_DCSM0 0x60 | |
211 | #define F10_DCSM1 0x160 | |
212 | ||
213 | /* REV E: select [29:21] and [15:9] from DCSM */ | |
214 | #define REV_E_DCSM_MASK_BITS 0x3FE0FE00 | |
215 | ||
216 | /* unused bits [24:20] and [12:0] */ | |
217 | #define REV_E_DCS_NOTUSED_BITS 0x01F01FFF | |
218 | ||
219 | /* REV F and later: select [28:19] and [13:5] from DCSM */ | |
220 | #define REV_F_F1Xh_DCSM_MASK_BITS 0x1FF83FE0 | |
221 | ||
222 | /* unused bits [26:22] and [12:0] */ | |
223 | #define REV_F_F1Xh_DCS_NOTUSED_BITS 0x07C01FFF | |
224 | ||
225 | #define DBAM0 0x80 | |
226 | #define DBAM1 0x180 | |
227 | ||
228 | /* Extract the DIMM 'type' on the i'th DIMM from the DBAM reg value passed */ | |
229 | #define DBAM_DIMM(i, reg) ((((reg) >> (4*i))) & 0xF) | |
230 | ||
231 | #define DBAM_MAX_VALUE 11 | |
232 | ||
233 | ||
234 | #define F10_DCLR_0 0x90 | |
235 | #define F10_DCLR_1 0x190 | |
236 | #define REVE_WIDTH_128 BIT(16) | |
237 | #define F10_WIDTH_128 BIT(11) | |
238 | ||
239 | ||
240 | #define F10_DCHR_0 0x94 | |
241 | #define F10_DCHR_1 0x194 | |
242 | ||
243 | #define F10_DCHR_FOUR_RANK_DIMM BIT(18) | |
244 | #define F10_DCHR_Ddr3Mode BIT(8) | |
245 | #define F10_DCHR_MblMode BIT(6) | |
246 | ||
247 | ||
248 | #define F10_DCTL_SEL_LOW 0x110 | |
249 | ||
250 | #define dct_sel_baseaddr(pvt) \ | |
251 | ((pvt->dram_ctl_select_low) & 0xFFFFF800) | |
252 | ||
253 | #define dct_sel_interleave_addr(pvt) \ | |
254 | (((pvt->dram_ctl_select_low) >> 6) & 0x3) | |
255 | ||
256 | enum { | |
257 | F10_DCTL_SEL_LOW_DctSelHiRngEn = BIT(0), | |
258 | F10_DCTL_SEL_LOW_DctSelIntLvEn = BIT(2), | |
259 | F10_DCTL_SEL_LOW_DctGangEn = BIT(4), | |
260 | F10_DCTL_SEL_LOW_DctDatIntLv = BIT(5), | |
261 | F10_DCTL_SEL_LOW_DramEnable = BIT(8), | |
262 | F10_DCTL_SEL_LOW_MemCleared = BIT(10), | |
263 | }; | |
264 | ||
265 | #define dct_high_range_enabled(pvt) \ | |
266 | (pvt->dram_ctl_select_low & F10_DCTL_SEL_LOW_DctSelHiRngEn) | |
267 | ||
268 | #define dct_interleave_enabled(pvt) \ | |
269 | (pvt->dram_ctl_select_low & F10_DCTL_SEL_LOW_DctSelIntLvEn) | |
270 | ||
271 | #define dct_ganging_enabled(pvt) \ | |
272 | (pvt->dram_ctl_select_low & F10_DCTL_SEL_LOW_DctGangEn) | |
273 | ||
274 | #define dct_data_intlv_enabled(pvt) \ | |
275 | (pvt->dram_ctl_select_low & F10_DCTL_SEL_LOW_DctDatIntLv) | |
276 | ||
277 | #define dct_dram_enabled(pvt) \ | |
278 | (pvt->dram_ctl_select_low & F10_DCTL_SEL_LOW_DramEnable) | |
279 | ||
280 | #define dct_memory_cleared(pvt) \ | |
281 | (pvt->dram_ctl_select_low & F10_DCTL_SEL_LOW_MemCleared) | |
282 | ||
283 | ||
284 | #define F10_DCTL_SEL_HIGH 0x114 | |
285 | ||
286 | ||
287 | /* | |
288 | * Function 3 - Misc Control | |
289 | */ | |
290 | #define K8_NBCTL 0x40 | |
291 | ||
292 | /* Correctable ECC error reporting enable */ | |
293 | #define K8_NBCTL_CECCEn BIT(0) | |
294 | ||
295 | /* UnCorrectable ECC error reporting enable */ | |
296 | #define K8_NBCTL_UECCEn BIT(1) | |
297 | ||
298 | #define K8_NBCFG 0x44 | |
299 | #define K8_NBCFG_CHIPKILL BIT(23) | |
300 | #define K8_NBCFG_ECC_ENABLE BIT(22) | |
301 | ||
302 | #define K8_NBSL 0x48 | |
303 | ||
304 | ||
305 | #define EXTRACT_HIGH_SYNDROME(x) (((x) >> 24) & 0xff) | |
306 | #define EXTRACT_EXT_ERROR_CODE(x) (((x) >> 16) & 0x1f) | |
307 | ||
308 | /* Family F10h: Normalized Extended Error Codes */ | |
309 | #define F10_NBSL_EXT_ERR_RES 0x0 | |
310 | #define F10_NBSL_EXT_ERR_CRC 0x1 | |
311 | #define F10_NBSL_EXT_ERR_SYNC 0x2 | |
312 | #define F10_NBSL_EXT_ERR_MST 0x3 | |
313 | #define F10_NBSL_EXT_ERR_TGT 0x4 | |
314 | #define F10_NBSL_EXT_ERR_GART 0x5 | |
315 | #define F10_NBSL_EXT_ERR_RMW 0x6 | |
316 | #define F10_NBSL_EXT_ERR_WDT 0x7 | |
317 | #define F10_NBSL_EXT_ERR_ECC 0x8 | |
318 | #define F10_NBSL_EXT_ERR_DEV 0x9 | |
319 | #define F10_NBSL_EXT_ERR_LINK_DATA 0xA | |
320 | ||
321 | /* Next two are overloaded values */ | |
322 | #define F10_NBSL_EXT_ERR_LINK_PROTO 0xB | |
323 | #define F10_NBSL_EXT_ERR_L3_PROTO 0xB | |
324 | ||
325 | #define F10_NBSL_EXT_ERR_NB_ARRAY 0xC | |
326 | #define F10_NBSL_EXT_ERR_DRAM_PARITY 0xD | |
327 | #define F10_NBSL_EXT_ERR_LINK_RETRY 0xE | |
328 | ||
329 | /* Next two are overloaded values */ | |
330 | #define F10_NBSL_EXT_ERR_GART_WALK 0xF | |
331 | #define F10_NBSL_EXT_ERR_DEV_WALK 0xF | |
332 | ||
333 | /* 0x10 to 0x1B: Reserved */ | |
334 | #define F10_NBSL_EXT_ERR_L3_DATA 0x1C | |
335 | #define F10_NBSL_EXT_ERR_L3_TAG 0x1D | |
336 | #define F10_NBSL_EXT_ERR_L3_LRU 0x1E | |
337 | ||
338 | /* K8: Normalized Extended Error Codes */ | |
339 | #define K8_NBSL_EXT_ERR_ECC 0x0 | |
340 | #define K8_NBSL_EXT_ERR_CRC 0x1 | |
341 | #define K8_NBSL_EXT_ERR_SYNC 0x2 | |
342 | #define K8_NBSL_EXT_ERR_MST 0x3 | |
343 | #define K8_NBSL_EXT_ERR_TGT 0x4 | |
344 | #define K8_NBSL_EXT_ERR_GART 0x5 | |
345 | #define K8_NBSL_EXT_ERR_RMW 0x6 | |
346 | #define K8_NBSL_EXT_ERR_WDT 0x7 | |
347 | #define K8_NBSL_EXT_ERR_CHIPKILL_ECC 0x8 | |
348 | #define K8_NBSL_EXT_ERR_DRAM_PARITY 0xD | |
349 | ||
350 | #define EXTRACT_ERROR_CODE(x) ((x) & 0xffff) | |
351 | #define TEST_TLB_ERROR(x) (((x) & 0xFFF0) == 0x0010) | |
352 | #define TEST_MEM_ERROR(x) (((x) & 0xFF00) == 0x0100) | |
353 | #define TEST_BUS_ERROR(x) (((x) & 0xF800) == 0x0800) | |
354 | #define EXTRACT_TT_CODE(x) (((x) >> 2) & 0x3) | |
355 | #define EXTRACT_II_CODE(x) (((x) >> 2) & 0x3) | |
356 | #define EXTRACT_LL_CODE(x) (((x) >> 0) & 0x3) | |
357 | #define EXTRACT_RRRR_CODE(x) (((x) >> 4) & 0xf) | |
358 | #define EXTRACT_TO_CODE(x) (((x) >> 8) & 0x1) | |
359 | #define EXTRACT_PP_CODE(x) (((x) >> 9) & 0x3) | |
360 | ||
361 | /* | |
362 | * The following are for BUS type errors AFTER values have been normalized by | |
363 | * shifting right | |
364 | */ | |
365 | #define K8_NBSL_PP_SRC 0x0 | |
366 | #define K8_NBSL_PP_RES 0x1 | |
367 | #define K8_NBSL_PP_OBS 0x2 | |
368 | #define K8_NBSL_PP_GENERIC 0x3 | |
369 | ||
370 | ||
371 | #define K8_NBSH 0x4C | |
372 | ||
373 | #define K8_NBSH_VALID_BIT BIT(31) | |
374 | #define K8_NBSH_OVERFLOW BIT(30) | |
375 | #define K8_NBSH_UNCORRECTED_ERR BIT(29) | |
376 | #define K8_NBSH_ERR_ENABLE BIT(28) | |
377 | #define K8_NBSH_MISC_ERR_VALID BIT(27) | |
378 | #define K8_NBSH_VALID_ERROR_ADDR BIT(26) | |
379 | #define K8_NBSH_PCC BIT(25) | |
380 | #define K8_NBSH_CECC BIT(14) | |
381 | #define K8_NBSH_UECC BIT(13) | |
382 | #define K8_NBSH_ERR_SCRUBER BIT(8) | |
383 | #define K8_NBSH_CORE3 BIT(3) | |
384 | #define K8_NBSH_CORE2 BIT(2) | |
385 | #define K8_NBSH_CORE1 BIT(1) | |
386 | #define K8_NBSH_CORE0 BIT(0) | |
387 | ||
388 | #define EXTRACT_LDT_LINK(x) (((x) >> 4) & 0x7) | |
389 | #define EXTRACT_ERR_CPU_MAP(x) ((x) & 0xF) | |
390 | #define EXTRACT_LOW_SYNDROME(x) (((x) >> 15) & 0xff) | |
391 | ||
392 | ||
393 | #define K8_NBEAL 0x50 | |
394 | #define K8_NBEAH 0x54 | |
395 | #define K8_SCRCTRL 0x58 | |
396 | ||
397 | #define F10_NB_CFG_LOW 0x88 | |
398 | #define F10_NB_CFG_LOW_ENABLE_EXT_CFG BIT(14) | |
399 | ||
400 | #define F10_NB_CFG_HIGH 0x8C | |
401 | ||
402 | #define F10_ONLINE_SPARE 0xB0 | |
403 | #define F10_ONLINE_SPARE_SWAPDONE0(x) ((x) & BIT(1)) | |
404 | #define F10_ONLINE_SPARE_SWAPDONE1(x) ((x) & BIT(3)) | |
405 | #define F10_ONLINE_SPARE_BADDRAM_CS0(x) (((x) >> 4) & 0x00000007) | |
406 | #define F10_ONLINE_SPARE_BADDRAM_CS1(x) (((x) >> 8) & 0x00000007) | |
407 | ||
408 | #define F10_NB_ARRAY_ADDR 0xB8 | |
409 | ||
410 | #define F10_NB_ARRAY_DRAM_ECC 0x80000000 | |
411 | ||
412 | /* Bits [2:1] are used to select 16-byte section within a 64-byte cacheline */ | |
413 | #define SET_NB_ARRAY_ADDRESS(section) (((section) & 0x3) << 1) | |
414 | ||
415 | #define F10_NB_ARRAY_DATA 0xBC | |
416 | ||
417 | #define SET_NB_DRAM_INJECTION_WRITE(word, bits) \ | |
418 | (BIT(((word) & 0xF) + 20) | \ | |
419 | BIT(17) | \ | |
420 | ((bits) & 0xF)) | |
421 | ||
422 | #define SET_NB_DRAM_INJECTION_READ(word, bits) \ | |
423 | (BIT(((word) & 0xF) + 20) | \ | |
424 | BIT(16) | \ | |
425 | ((bits) & 0xF)) | |
426 | ||
427 | #define K8_NBCAP 0xE8 | |
428 | #define K8_NBCAP_CORES (BIT(12)|BIT(13)) | |
429 | #define K8_NBCAP_CHIPKILL BIT(4) | |
430 | #define K8_NBCAP_SECDED BIT(3) | |
431 | #define K8_NBCAP_8_NODE BIT(2) | |
432 | #define K8_NBCAP_DUAL_NODE BIT(1) | |
433 | #define K8_NBCAP_DCT_DUAL BIT(0) | |
434 | ||
435 | /* | |
436 | * MSR Regs | |
437 | */ | |
438 | #define K8_MSR_MCGCTL 0x017b | |
439 | #define K8_MSR_MCGCTL_NBE BIT(4) | |
440 | ||
441 | #define K8_MSR_MC4CTL 0x0410 | |
442 | #define K8_MSR_MC4STAT 0x0411 | |
443 | #define K8_MSR_MC4ADDR 0x0412 | |
444 | ||
445 | /* AMD sets the first MC device at device ID 0x18. */ | |
446 | static inline int get_mc_node_id_from_pdev(struct pci_dev *pdev) | |
447 | { | |
448 | return PCI_SLOT(pdev->devfn) - 0x18; | |
449 | } | |
450 | ||
451 | enum amd64_chipset_families { | |
452 | K8_CPUS = 0, | |
453 | F10_CPUS, | |
454 | F11_CPUS, | |
455 | }; | |
456 | ||
457 | /* | |
458 | * Structure to hold: | |
459 | * | |
460 | * 1) dynamically read status and error address HW registers | |
461 | * 2) sysfs entered values | |
462 | * 3) MCE values | |
463 | * | |
464 | * Depends on entry into the modules | |
465 | */ | |
466 | struct amd64_error_info_regs { | |
467 | u32 nbcfg; | |
468 | u32 nbsh; | |
469 | u32 nbsl; | |
470 | u32 nbeah; | |
471 | u32 nbeal; | |
472 | }; | |
473 | ||
474 | /* Error injection control structure */ | |
475 | struct error_injection { | |
476 | u32 section; | |
477 | u32 word; | |
478 | u32 bit_map; | |
479 | }; | |
480 | ||
481 | struct amd64_pvt { | |
482 | /* pci_device handles which we utilize */ | |
483 | struct pci_dev *addr_f1_ctl; | |
484 | struct pci_dev *dram_f2_ctl; | |
485 | struct pci_dev *misc_f3_ctl; | |
486 | ||
487 | int mc_node_id; /* MC index of this MC node */ | |
488 | int ext_model; /* extended model value of this node */ | |
489 | ||
490 | struct low_ops *ops; /* pointer to per PCI Device ID func table */ | |
491 | ||
492 | int channel_count; | |
493 | ||
494 | /* Raw registers */ | |
495 | u32 dclr0; /* DRAM Configuration Low DCT0 reg */ | |
496 | u32 dclr1; /* DRAM Configuration Low DCT1 reg */ | |
497 | u32 dchr0; /* DRAM Configuration High DCT0 reg */ | |
498 | u32 dchr1; /* DRAM Configuration High DCT1 reg */ | |
499 | u32 nbcap; /* North Bridge Capabilities */ | |
500 | u32 nbcfg; /* F10 North Bridge Configuration */ | |
501 | u32 ext_nbcfg; /* Extended F10 North Bridge Configuration */ | |
502 | u32 dhar; /* DRAM Hoist reg */ | |
503 | u32 dbam0; /* DRAM Base Address Mapping reg for DCT0 */ | |
504 | u32 dbam1; /* DRAM Base Address Mapping reg for DCT1 */ | |
505 | ||
506 | /* DRAM CS Base Address Registers F2x[1,0][5C:40] */ | |
507 | u32 dcsb0[CHIPSELECT_COUNT]; | |
508 | u32 dcsb1[CHIPSELECT_COUNT]; | |
509 | ||
510 | /* DRAM CS Mask Registers F2x[1,0][6C:60] */ | |
511 | u32 dcsm0[CHIPSELECT_COUNT]; | |
512 | u32 dcsm1[CHIPSELECT_COUNT]; | |
513 | ||
514 | /* | |
515 | * Decoded parts of DRAM BASE and LIMIT Registers | |
516 | * F1x[78,70,68,60,58,50,48,40] | |
517 | */ | |
518 | u64 dram_base[DRAM_REG_COUNT]; | |
519 | u64 dram_limit[DRAM_REG_COUNT]; | |
520 | u8 dram_IntlvSel[DRAM_REG_COUNT]; | |
521 | u8 dram_IntlvEn[DRAM_REG_COUNT]; | |
522 | u8 dram_DstNode[DRAM_REG_COUNT]; | |
523 | u8 dram_rw_en[DRAM_REG_COUNT]; | |
524 | ||
525 | /* | |
526 | * The following fields are set at (load) run time, after CPU revision | |
527 | * has been determined, since the dct_base and dct_mask registers vary | |
528 | * based on revision | |
529 | */ | |
530 | u32 dcsb_base; /* DCSB base bits */ | |
531 | u32 dcsm_mask; /* DCSM mask bits */ | |
532 | u32 num_dcsm; /* Number of DCSM registers */ | |
533 | u32 dcs_mask_notused; /* DCSM notused mask bits */ | |
534 | u32 dcs_shift; /* DCSB and DCSM shift value */ | |
535 | ||
536 | u64 top_mem; /* top of memory below 4GB */ | |
537 | u64 top_mem2; /* top of memory above 4GB */ | |
538 | ||
539 | u32 dram_ctl_select_low; /* DRAM Controller Select Low Reg */ | |
540 | u32 dram_ctl_select_high; /* DRAM Controller Select High Reg */ | |
541 | u32 online_spare; /* On-Line spare Reg */ | |
542 | ||
543 | /* temp storage for when input is received from sysfs */ | |
544 | struct amd64_error_info_regs ctl_error_info; | |
545 | ||
546 | /* place to store error injection parameters prior to issue */ | |
547 | struct error_injection injection; | |
548 | ||
549 | /* Save old hw registers' values before we modified them */ | |
550 | u32 nbctl_mcgctl_saved; /* When true, following 2 are valid */ | |
551 | u32 old_nbctl; | |
552 | u32 *old_mcgctl; /* per core on this node */ | |
553 | ||
554 | /* MC Type Index value: socket F vs Family 10h */ | |
555 | u32 mc_type_index; | |
556 | ||
557 | /* misc settings */ | |
558 | struct flags { | |
559 | unsigned long cf8_extcfg:1; | |
560 | } flags; | |
561 | }; | |
562 | ||
563 | struct scrubrate { | |
564 | u32 scrubval; /* bit pattern for scrub rate */ | |
565 | u32 bandwidth; /* bandwidth consumed (bytes/sec) */ | |
566 | }; | |
567 | ||
568 | extern struct scrubrate scrubrates[23]; | |
569 | extern u32 revf_quad_ddr2_shift[16]; | |
570 | extern const char *tt_msgs[4]; | |
571 | extern const char *ll_msgs[4]; | |
572 | extern const char *rrrr_msgs[16]; | |
573 | extern const char *to_msgs[2]; | |
574 | extern const char *pp_msgs[4]; | |
575 | extern const char *ii_msgs[4]; | |
576 | extern const char *ext_msgs[32]; | |
577 | extern const char *htlink_msgs[8]; | |
578 | ||
579 | /* | |
580 | * Each of the PCI Device IDs types have their own set of hardware accessor | |
581 | * functions and per device encoding/decoding logic. | |
582 | */ | |
583 | struct low_ops { | |
584 | int (*probe_valid_hardware)(struct amd64_pvt *pvt); | |
585 | int (*early_channel_count)(struct amd64_pvt *pvt); | |
586 | ||
587 | u64 (*get_error_address)(struct mem_ctl_info *mci, | |
588 | struct amd64_error_info_regs *info); | |
589 | void (*read_dram_base_limit)(struct amd64_pvt *pvt, int dram); | |
590 | void (*read_dram_ctl_register)(struct amd64_pvt *pvt); | |
591 | void (*map_sysaddr_to_csrow)(struct mem_ctl_info *mci, | |
592 | struct amd64_error_info_regs *info, | |
593 | u64 SystemAddr); | |
594 | int (*dbam_map_to_pages)(struct amd64_pvt *pvt, int dram_map); | |
595 | }; | |
596 | ||
597 | struct amd64_family_type { | |
598 | const char *ctl_name; | |
599 | u16 addr_f1_ctl; | |
600 | u16 misc_f3_ctl; | |
601 | struct low_ops ops; | |
602 | }; | |
603 | ||
604 | static struct amd64_family_type amd64_family_types[]; | |
605 | ||
606 | static inline const char *get_amd_family_name(int index) | |
607 | { | |
608 | return amd64_family_types[index].ctl_name; | |
609 | } | |
610 | ||
611 | static inline struct low_ops *family_ops(int index) | |
612 | { | |
613 | return &amd64_family_types[index].ops; | |
614 | } | |
615 | ||
616 | /* | |
617 | * For future CPU versions, verify the following as new 'slow' rates appear and | |
618 | * modify the necessary skip values for the supported CPU. | |
619 | */ | |
620 | #define K8_MIN_SCRUB_RATE_BITS 0x0 | |
621 | #define F10_MIN_SCRUB_RATE_BITS 0x5 | |
622 | #define F11_MIN_SCRUB_RATE_BITS 0x6 | |
623 | ||
624 | int amd64_process_error_info(struct mem_ctl_info *mci, | |
625 | struct amd64_error_info_regs *info, | |
626 | int handle_errors); | |
627 | int amd64_get_dram_hole_info(struct mem_ctl_info *mci, u64 *hole_base, | |
628 | u64 *hole_offset, u64 *hole_size); |