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1 | /* |
2 | * Intel 5000(P/V/X) class Memory Controllers kernel module | |
3 | * | |
4 | * This file may be distributed under the terms of the | |
5 | * GNU General Public License. | |
6 | * | |
7 | * Written by Douglas Thompson Linux Networx (http://lnxi.com) | |
8 | * norsk5@xmission.com | |
9 | * | |
10 | * This module is based on the following document: | |
11 | * | |
12 | * Intel 5000X Chipset Memory Controller Hub (MCH) - Datasheet | |
13 | * http://developer.intel.com/design/chipsets/datashts/313070.htm | |
14 | * | |
15 | */ | |
16 | ||
17 | #include <linux/module.h> | |
18 | #include <linux/init.h> | |
19 | #include <linux/pci.h> | |
20 | #include <linux/pci_ids.h> | |
21 | #include <linux/slab.h> | |
c0d12172 | 22 | #include <linux/edac.h> |
eb60705a EW |
23 | #include <asm/mmzone.h> |
24 | ||
20bcb7a8 | 25 | #include "edac_core.h" |
eb60705a EW |
26 | |
27 | /* | |
28 | * Alter this version for the I5000 module when modifications are made | |
29 | */ | |
20bcb7a8 | 30 | #define I5000_REVISION " Ver: 2.0.12 " __DATE__ |
eb60705a EW |
31 | |
32 | #define i5000_printk(level, fmt, arg...) \ | |
33 | edac_printk(level, "i5000", fmt, ##arg) | |
34 | ||
35 | #define i5000_mc_printk(mci, level, fmt, arg...) \ | |
36 | edac_mc_chipset_printk(mci, level, "i5000", fmt, ##arg) | |
37 | ||
38 | #ifndef PCI_DEVICE_ID_INTEL_FBD_0 | |
39 | #define PCI_DEVICE_ID_INTEL_FBD_0 0x25F5 | |
40 | #endif | |
41 | #ifndef PCI_DEVICE_ID_INTEL_FBD_1 | |
42 | #define PCI_DEVICE_ID_INTEL_FBD_1 0x25F6 | |
43 | #endif | |
44 | ||
45 | /* Device 16, | |
46 | * Function 0: System Address | |
47 | * Function 1: Memory Branch Map, Control, Errors Register | |
48 | * Function 2: FSB Error Registers | |
49 | * | |
50 | * All 3 functions of Device 16 (0,1,2) share the SAME DID | |
51 | */ | |
52 | #define PCI_DEVICE_ID_INTEL_I5000_DEV16 0x25F0 | |
53 | ||
54 | /* OFFSETS for Function 0 */ | |
55 | ||
56 | /* OFFSETS for Function 1 */ | |
57 | #define AMBASE 0x48 | |
58 | #define MAXCH 0x56 | |
59 | #define MAXDIMMPERCH 0x57 | |
60 | #define TOLM 0x6C | |
61 | #define REDMEMB 0x7C | |
62 | #define RED_ECC_LOCATOR(x) ((x) & 0x3FFFF) | |
63 | #define REC_ECC_LOCATOR_EVEN(x) ((x) & 0x001FF) | |
64 | #define REC_ECC_LOCATOR_ODD(x) ((x) & 0x3FE00) | |
65 | #define MIR0 0x80 | |
66 | #define MIR1 0x84 | |
67 | #define MIR2 0x88 | |
68 | #define AMIR0 0x8C | |
69 | #define AMIR1 0x90 | |
70 | #define AMIR2 0x94 | |
71 | ||
72 | #define FERR_FAT_FBD 0x98 | |
73 | #define NERR_FAT_FBD 0x9C | |
74 | #define EXTRACT_FBDCHAN_INDX(x) (((x)>>28) & 0x3) | |
75 | #define FERR_FAT_FBDCHAN 0x30000000 | |
76 | #define FERR_FAT_M3ERR 0x00000004 | |
77 | #define FERR_FAT_M2ERR 0x00000002 | |
78 | #define FERR_FAT_M1ERR 0x00000001 | |
79 | #define FERR_FAT_MASK (FERR_FAT_M1ERR | \ | |
80 | FERR_FAT_M2ERR | \ | |
81 | FERR_FAT_M3ERR) | |
82 | ||
83 | #define FERR_NF_FBD 0xA0 | |
84 | ||
85 | /* Thermal and SPD or BFD errors */ | |
86 | #define FERR_NF_M28ERR 0x01000000 | |
87 | #define FERR_NF_M27ERR 0x00800000 | |
88 | #define FERR_NF_M26ERR 0x00400000 | |
89 | #define FERR_NF_M25ERR 0x00200000 | |
90 | #define FERR_NF_M24ERR 0x00100000 | |
91 | #define FERR_NF_M23ERR 0x00080000 | |
92 | #define FERR_NF_M22ERR 0x00040000 | |
93 | #define FERR_NF_M21ERR 0x00020000 | |
94 | ||
95 | /* Correctable errors */ | |
96 | #define FERR_NF_M20ERR 0x00010000 | |
97 | #define FERR_NF_M19ERR 0x00008000 | |
98 | #define FERR_NF_M18ERR 0x00004000 | |
99 | #define FERR_NF_M17ERR 0x00002000 | |
100 | ||
101 | /* Non-Retry or redundant Retry errors */ | |
102 | #define FERR_NF_M16ERR 0x00001000 | |
103 | #define FERR_NF_M15ERR 0x00000800 | |
104 | #define FERR_NF_M14ERR 0x00000400 | |
105 | #define FERR_NF_M13ERR 0x00000200 | |
106 | ||
107 | /* Uncorrectable errors */ | |
108 | #define FERR_NF_M12ERR 0x00000100 | |
109 | #define FERR_NF_M11ERR 0x00000080 | |
110 | #define FERR_NF_M10ERR 0x00000040 | |
111 | #define FERR_NF_M9ERR 0x00000020 | |
112 | #define FERR_NF_M8ERR 0x00000010 | |
113 | #define FERR_NF_M7ERR 0x00000008 | |
114 | #define FERR_NF_M6ERR 0x00000004 | |
115 | #define FERR_NF_M5ERR 0x00000002 | |
116 | #define FERR_NF_M4ERR 0x00000001 | |
117 | ||
118 | #define FERR_NF_UNCORRECTABLE (FERR_NF_M12ERR | \ | |
119 | FERR_NF_M11ERR | \ | |
120 | FERR_NF_M10ERR | \ | |
121 | FERR_NF_M8ERR | \ | |
122 | FERR_NF_M7ERR | \ | |
123 | FERR_NF_M6ERR | \ | |
124 | FERR_NF_M5ERR | \ | |
125 | FERR_NF_M4ERR) | |
126 | #define FERR_NF_CORRECTABLE (FERR_NF_M20ERR | \ | |
127 | FERR_NF_M19ERR | \ | |
128 | FERR_NF_M18ERR | \ | |
129 | FERR_NF_M17ERR) | |
130 | #define FERR_NF_DIMM_SPARE (FERR_NF_M27ERR | \ | |
131 | FERR_NF_M28ERR) | |
132 | #define FERR_NF_THERMAL (FERR_NF_M26ERR | \ | |
133 | FERR_NF_M25ERR | \ | |
134 | FERR_NF_M24ERR | \ | |
135 | FERR_NF_M23ERR) | |
136 | #define FERR_NF_SPD_PROTOCOL (FERR_NF_M22ERR) | |
137 | #define FERR_NF_NORTH_CRC (FERR_NF_M21ERR) | |
138 | #define FERR_NF_NON_RETRY (FERR_NF_M13ERR | \ | |
139 | FERR_NF_M14ERR | \ | |
140 | FERR_NF_M15ERR) | |
141 | ||
142 | #define NERR_NF_FBD 0xA4 | |
143 | #define FERR_NF_MASK (FERR_NF_UNCORRECTABLE | \ | |
144 | FERR_NF_CORRECTABLE | \ | |
145 | FERR_NF_DIMM_SPARE | \ | |
146 | FERR_NF_THERMAL | \ | |
147 | FERR_NF_SPD_PROTOCOL | \ | |
148 | FERR_NF_NORTH_CRC | \ | |
149 | FERR_NF_NON_RETRY) | |
150 | ||
151 | #define EMASK_FBD 0xA8 | |
152 | #define EMASK_FBD_M28ERR 0x08000000 | |
153 | #define EMASK_FBD_M27ERR 0x04000000 | |
154 | #define EMASK_FBD_M26ERR 0x02000000 | |
155 | #define EMASK_FBD_M25ERR 0x01000000 | |
156 | #define EMASK_FBD_M24ERR 0x00800000 | |
157 | #define EMASK_FBD_M23ERR 0x00400000 | |
158 | #define EMASK_FBD_M22ERR 0x00200000 | |
159 | #define EMASK_FBD_M21ERR 0x00100000 | |
160 | #define EMASK_FBD_M20ERR 0x00080000 | |
161 | #define EMASK_FBD_M19ERR 0x00040000 | |
162 | #define EMASK_FBD_M18ERR 0x00020000 | |
163 | #define EMASK_FBD_M17ERR 0x00010000 | |
164 | ||
165 | #define EMASK_FBD_M15ERR 0x00004000 | |
166 | #define EMASK_FBD_M14ERR 0x00002000 | |
167 | #define EMASK_FBD_M13ERR 0x00001000 | |
168 | #define EMASK_FBD_M12ERR 0x00000800 | |
169 | #define EMASK_FBD_M11ERR 0x00000400 | |
170 | #define EMASK_FBD_M10ERR 0x00000200 | |
171 | #define EMASK_FBD_M9ERR 0x00000100 | |
172 | #define EMASK_FBD_M8ERR 0x00000080 | |
173 | #define EMASK_FBD_M7ERR 0x00000040 | |
174 | #define EMASK_FBD_M6ERR 0x00000020 | |
175 | #define EMASK_FBD_M5ERR 0x00000010 | |
176 | #define EMASK_FBD_M4ERR 0x00000008 | |
177 | #define EMASK_FBD_M3ERR 0x00000004 | |
178 | #define EMASK_FBD_M2ERR 0x00000002 | |
179 | #define EMASK_FBD_M1ERR 0x00000001 | |
180 | ||
181 | #define ENABLE_EMASK_FBD_FATAL_ERRORS (EMASK_FBD_M1ERR | \ | |
182 | EMASK_FBD_M2ERR | \ | |
183 | EMASK_FBD_M3ERR) | |
184 | ||
185 | #define ENABLE_EMASK_FBD_UNCORRECTABLE (EMASK_FBD_M4ERR | \ | |
186 | EMASK_FBD_M5ERR | \ | |
187 | EMASK_FBD_M6ERR | \ | |
188 | EMASK_FBD_M7ERR | \ | |
189 | EMASK_FBD_M8ERR | \ | |
190 | EMASK_FBD_M9ERR | \ | |
191 | EMASK_FBD_M10ERR | \ | |
192 | EMASK_FBD_M11ERR | \ | |
193 | EMASK_FBD_M12ERR) | |
194 | #define ENABLE_EMASK_FBD_CORRECTABLE (EMASK_FBD_M17ERR | \ | |
195 | EMASK_FBD_M18ERR | \ | |
196 | EMASK_FBD_M19ERR | \ | |
197 | EMASK_FBD_M20ERR) | |
198 | #define ENABLE_EMASK_FBD_DIMM_SPARE (EMASK_FBD_M27ERR | \ | |
199 | EMASK_FBD_M28ERR) | |
200 | #define ENABLE_EMASK_FBD_THERMALS (EMASK_FBD_M26ERR | \ | |
201 | EMASK_FBD_M25ERR | \ | |
202 | EMASK_FBD_M24ERR | \ | |
203 | EMASK_FBD_M23ERR) | |
204 | #define ENABLE_EMASK_FBD_SPD_PROTOCOL (EMASK_FBD_M22ERR) | |
205 | #define ENABLE_EMASK_FBD_NORTH_CRC (EMASK_FBD_M21ERR) | |
206 | #define ENABLE_EMASK_FBD_NON_RETRY (EMASK_FBD_M15ERR | \ | |
207 | EMASK_FBD_M14ERR | \ | |
208 | EMASK_FBD_M13ERR) | |
209 | ||
210 | #define ENABLE_EMASK_ALL (ENABLE_EMASK_FBD_NON_RETRY | \ | |
211 | ENABLE_EMASK_FBD_NORTH_CRC | \ | |
212 | ENABLE_EMASK_FBD_SPD_PROTOCOL | \ | |
213 | ENABLE_EMASK_FBD_THERMALS | \ | |
214 | ENABLE_EMASK_FBD_DIMM_SPARE | \ | |
215 | ENABLE_EMASK_FBD_FATAL_ERRORS | \ | |
216 | ENABLE_EMASK_FBD_CORRECTABLE | \ | |
217 | ENABLE_EMASK_FBD_UNCORRECTABLE) | |
218 | ||
219 | #define ERR0_FBD 0xAC | |
220 | #define ERR1_FBD 0xB0 | |
221 | #define ERR2_FBD 0xB4 | |
222 | #define MCERR_FBD 0xB8 | |
223 | #define NRECMEMA 0xBE | |
224 | #define NREC_BANK(x) (((x)>>12) & 0x7) | |
225 | #define NREC_RDWR(x) (((x)>>11) & 1) | |
226 | #define NREC_RANK(x) (((x)>>8) & 0x7) | |
227 | #define NRECMEMB 0xC0 | |
228 | #define NREC_CAS(x) (((x)>>16) & 0xFFFFFF) | |
229 | #define NREC_RAS(x) ((x) & 0x7FFF) | |
230 | #define NRECFGLOG 0xC4 | |
231 | #define NREEECFBDA 0xC8 | |
232 | #define NREEECFBDB 0xCC | |
233 | #define NREEECFBDC 0xD0 | |
234 | #define NREEECFBDD 0xD4 | |
235 | #define NREEECFBDE 0xD8 | |
236 | #define REDMEMA 0xDC | |
237 | #define RECMEMA 0xE2 | |
238 | #define REC_BANK(x) (((x)>>12) & 0x7) | |
239 | #define REC_RDWR(x) (((x)>>11) & 1) | |
240 | #define REC_RANK(x) (((x)>>8) & 0x7) | |
241 | #define RECMEMB 0xE4 | |
242 | #define REC_CAS(x) (((x)>>16) & 0xFFFFFF) | |
243 | #define REC_RAS(x) ((x) & 0x7FFF) | |
244 | #define RECFGLOG 0xE8 | |
245 | #define RECFBDA 0xEC | |
246 | #define RECFBDB 0xF0 | |
247 | #define RECFBDC 0xF4 | |
248 | #define RECFBDD 0xF8 | |
249 | #define RECFBDE 0xFC | |
250 | ||
251 | /* OFFSETS for Function 2 */ | |
252 | ||
253 | /* | |
254 | * Device 21, | |
255 | * Function 0: Memory Map Branch 0 | |
256 | * | |
257 | * Device 22, | |
258 | * Function 0: Memory Map Branch 1 | |
259 | */ | |
260 | #define PCI_DEVICE_ID_I5000_BRANCH_0 0x25F5 | |
261 | #define PCI_DEVICE_ID_I5000_BRANCH_1 0x25F6 | |
262 | ||
263 | #define AMB_PRESENT_0 0x64 | |
264 | #define AMB_PRESENT_1 0x66 | |
265 | #define MTR0 0x80 | |
266 | #define MTR1 0x84 | |
267 | #define MTR2 0x88 | |
268 | #define MTR3 0x8C | |
269 | ||
270 | #define NUM_MTRS 4 | |
271 | #define CHANNELS_PER_BRANCH (2) | |
272 | ||
273 | /* Defines to extract the vaious fields from the | |
274 | * MTRx - Memory Technology Registers | |
275 | */ | |
276 | #define MTR_DIMMS_PRESENT(mtr) ((mtr) & (0x1 << 8)) | |
277 | #define MTR_DRAM_WIDTH(mtr) ((((mtr) >> 6) & 0x1) ? 8 : 4) | |
278 | #define MTR_DRAM_BANKS(mtr) ((((mtr) >> 5) & 0x1) ? 8 : 4) | |
279 | #define MTR_DRAM_BANKS_ADDR_BITS(mtr) ((MTR_DRAM_BANKS(mtr) == 8) ? 3 : 2) | |
280 | #define MTR_DIMM_RANK(mtr) (((mtr) >> 4) & 0x1) | |
281 | #define MTR_DIMM_RANK_ADDR_BITS(mtr) (MTR_DIM_RANKS(mtr) ? 2 : 1) | |
282 | #define MTR_DIMM_ROWS(mtr) (((mtr) >> 2) & 0x3) | |
283 | #define MTR_DIMM_ROWS_ADDR_BITS(mtr) (MTR_DIMM_ROWS(mtr) + 13) | |
284 | #define MTR_DIMM_COLS(mtr) ((mtr) & 0x3) | |
285 | #define MTR_DIMM_COLS_ADDR_BITS(mtr) (MTR_DIMM_COLS(mtr) + 10) | |
286 | ||
287 | #ifdef CONFIG_EDAC_DEBUG | |
288 | static char *numrow_toString[] = { | |
289 | "8,192 - 13 rows", | |
290 | "16,384 - 14 rows", | |
291 | "32,768 - 15 rows", | |
292 | "reserved" | |
293 | }; | |
294 | ||
295 | static char *numcol_toString[] = { | |
296 | "1,024 - 10 columns", | |
297 | "2,048 - 11 columns", | |
298 | "4,096 - 12 columns", | |
299 | "reserved" | |
300 | }; | |
301 | #endif | |
302 | ||
303 | /* Enumeration of supported devices */ | |
304 | enum i5000_chips { | |
305 | I5000P = 0, | |
306 | I5000V = 1, /* future */ | |
307 | I5000X = 2 /* future */ | |
308 | }; | |
309 | ||
310 | /* Device name and register DID (Device ID) */ | |
311 | struct i5000_dev_info { | |
312 | const char *ctl_name; /* name for this device */ | |
313 | u16 fsb_mapping_errors; /* DID for the branchmap,control */ | |
314 | }; | |
315 | ||
316 | /* Table of devices attributes supported by this driver */ | |
317 | static const struct i5000_dev_info i5000_devs[] = { | |
318 | [I5000P] = { | |
319 | .ctl_name = "I5000", | |
320 | .fsb_mapping_errors = PCI_DEVICE_ID_INTEL_I5000_DEV16, | |
321 | }, | |
322 | }; | |
323 | ||
324 | struct i5000_dimm_info { | |
325 | int megabytes; /* size, 0 means not present */ | |
326 | int dual_rank; | |
327 | }; | |
328 | ||
329 | #define MAX_CHANNELS 6 /* max possible channels */ | |
330 | #define MAX_CSROWS (8*2) /* max possible csrows per channel */ | |
331 | ||
332 | /* driver private data structure */ | |
333 | struct i5000_pvt { | |
334 | struct pci_dev *system_address; /* 16.0 */ | |
335 | struct pci_dev *branchmap_werrors; /* 16.1 */ | |
336 | struct pci_dev *fsb_error_regs; /* 16.2 */ | |
337 | struct pci_dev *branch_0; /* 21.0 */ | |
338 | struct pci_dev *branch_1; /* 22.0 */ | |
339 | ||
340 | int node_id; /* ID of this node */ | |
341 | ||
342 | u16 tolm; /* top of low memory */ | |
343 | u64 ambase; /* AMB BAR */ | |
344 | ||
345 | u16 mir0, mir1, mir2; | |
346 | ||
347 | u16 b0_mtr[NUM_MTRS]; /* Memory Technlogy Reg */ | |
348 | u16 b0_ambpresent0; /* Branch 0, Channel 0 */ | |
349 | u16 b0_ambpresent1; /* Brnach 0, Channel 1 */ | |
350 | ||
351 | u16 b1_mtr[NUM_MTRS]; /* Memory Technlogy Reg */ | |
352 | u16 b1_ambpresent0; /* Branch 1, Channel 8 */ | |
353 | u16 b1_ambpresent1; /* Branch 1, Channel 1 */ | |
354 | ||
355 | /* DIMM infomation matrix, allocating architecture maximums */ | |
356 | struct i5000_dimm_info dimm_info[MAX_CSROWS][MAX_CHANNELS]; | |
357 | ||
358 | /* Actual values for this controller */ | |
359 | int maxch; /* Max channels */ | |
360 | int maxdimmperch; /* Max DIMMs per channel */ | |
361 | }; | |
362 | ||
363 | /* I5000 MCH error information retrieved from Hardware */ | |
364 | struct i5000_error_info { | |
365 | ||
366 | /* These registers are always read from the MC */ | |
367 | u32 ferr_fat_fbd; /* First Errors Fatal */ | |
368 | u32 nerr_fat_fbd; /* Next Errors Fatal */ | |
369 | u32 ferr_nf_fbd; /* First Errors Non-Fatal */ | |
370 | u32 nerr_nf_fbd; /* Next Errors Non-Fatal */ | |
371 | ||
372 | /* These registers are input ONLY if there was a Recoverable Error */ | |
373 | u32 redmemb; /* Recoverable Mem Data Error log B */ | |
374 | u16 recmema; /* Recoverable Mem Error log A */ | |
375 | u32 recmemb; /* Recoverable Mem Error log B */ | |
376 | ||
377 | /* These registers are input ONLY if there was a | |
378 | * Non-Recoverable Error */ | |
379 | u16 nrecmema; /* Non-Recoverable Mem log A */ | |
380 | u16 nrecmemb; /* Non-Recoverable Mem log B */ | |
381 | ||
382 | }; | |
383 | ||
384 | /****************************************************************************** | |
385 | * i5000_get_error_info Retrieve the hardware error information from | |
386 | * the hardware and cache it in the 'info' | |
387 | * structure | |
388 | */ | |
389 | static void i5000_get_error_info(struct mem_ctl_info *mci, | |
390 | struct i5000_error_info * info) | |
391 | { | |
392 | struct i5000_pvt *pvt; | |
393 | u32 value; | |
394 | ||
395 | pvt = (struct i5000_pvt *)mci->pvt_info; | |
396 | ||
397 | /* read in the 1st FATAL error register */ | |
398 | pci_read_config_dword(pvt->branchmap_werrors, FERR_FAT_FBD, &value); | |
399 | ||
400 | /* Mask only the bits that the doc says are valid | |
401 | */ | |
402 | value &= (FERR_FAT_FBDCHAN | FERR_FAT_MASK); | |
403 | ||
404 | /* If there is an error, then read in the */ | |
405 | /* NEXT FATAL error register and the Memory Error Log Register A */ | |
406 | if (value & FERR_FAT_MASK) { | |
407 | info->ferr_fat_fbd = value; | |
408 | ||
409 | /* harvest the various error data we need */ | |
410 | pci_read_config_dword(pvt->branchmap_werrors, | |
411 | NERR_FAT_FBD, &info->nerr_fat_fbd); | |
412 | pci_read_config_word(pvt->branchmap_werrors, | |
413 | NRECMEMA, &info->nrecmema); | |
414 | pci_read_config_word(pvt->branchmap_werrors, | |
415 | NRECMEMB, &info->nrecmemb); | |
416 | ||
417 | /* Clear the error bits, by writing them back */ | |
418 | pci_write_config_dword(pvt->branchmap_werrors, | |
419 | FERR_FAT_FBD, value); | |
420 | } else { | |
421 | info->ferr_fat_fbd = 0; | |
422 | info->nerr_fat_fbd = 0; | |
423 | info->nrecmema = 0; | |
424 | info->nrecmemb = 0; | |
425 | } | |
426 | ||
427 | /* read in the 1st NON-FATAL error register */ | |
428 | pci_read_config_dword(pvt->branchmap_werrors, FERR_NF_FBD, &value); | |
429 | ||
430 | /* If there is an error, then read in the 1st NON-FATAL error | |
431 | * register as well */ | |
432 | if (value & FERR_NF_MASK) { | |
433 | info->ferr_nf_fbd = value; | |
434 | ||
435 | /* harvest the various error data we need */ | |
436 | pci_read_config_dword(pvt->branchmap_werrors, | |
437 | NERR_NF_FBD, &info->nerr_nf_fbd); | |
438 | pci_read_config_word(pvt->branchmap_werrors, | |
439 | RECMEMA, &info->recmema); | |
440 | pci_read_config_dword(pvt->branchmap_werrors, | |
441 | RECMEMB, &info->recmemb); | |
442 | pci_read_config_dword(pvt->branchmap_werrors, | |
443 | REDMEMB, &info->redmemb); | |
444 | ||
445 | /* Clear the error bits, by writing them back */ | |
446 | pci_write_config_dword(pvt->branchmap_werrors, | |
447 | FERR_NF_FBD, value); | |
448 | } else { | |
449 | info->ferr_nf_fbd = 0; | |
450 | info->nerr_nf_fbd = 0; | |
451 | info->recmema = 0; | |
452 | info->recmemb = 0; | |
453 | info->redmemb = 0; | |
454 | } | |
455 | } | |
456 | ||
457 | /****************************************************************************** | |
458 | * i5000_process_fatal_error_info(struct mem_ctl_info *mci, | |
459 | * struct i5000_error_info *info, | |
460 | * int handle_errors); | |
461 | * | |
462 | * handle the Intel FATAL errors, if any | |
463 | */ | |
464 | static void i5000_process_fatal_error_info(struct mem_ctl_info *mci, | |
465 | struct i5000_error_info * info, | |
466 | int handle_errors) | |
467 | { | |
468 | char msg[EDAC_MC_LABEL_LEN + 1 + 90]; | |
469 | u32 allErrors; | |
470 | int branch; | |
471 | int channel; | |
472 | int bank; | |
473 | int rank; | |
474 | int rdwr; | |
475 | int ras, cas; | |
476 | ||
477 | /* mask off the Error bits that are possible */ | |
478 | allErrors = (info->ferr_fat_fbd & FERR_FAT_MASK); | |
479 | if (!allErrors) | |
480 | return; /* if no error, return now */ | |
481 | ||
482 | /* ONLY ONE of the possible error bits will be set, as per the docs */ | |
483 | i5000_mc_printk(mci, KERN_ERR, | |
484 | "FATAL ERRORS Found!!! 1st FATAL Err Reg= 0x%x\n", | |
485 | allErrors); | |
486 | ||
487 | branch = EXTRACT_FBDCHAN_INDX(info->ferr_fat_fbd); | |
488 | channel = branch; | |
489 | ||
490 | /* Use the NON-Recoverable macros to extract data */ | |
491 | bank = NREC_BANK(info->nrecmema); | |
492 | rank = NREC_RANK(info->nrecmema); | |
493 | rdwr = NREC_RDWR(info->nrecmema); | |
494 | ras = NREC_RAS(info->nrecmemb); | |
495 | cas = NREC_CAS(info->nrecmemb); | |
496 | ||
497 | debugf0("\t\tCSROW= %d Channels= %d,%d (Branch= %d " | |
498 | "DRAM Bank= %d rdwr= %s ras= %d cas= %d)\n", | |
499 | rank, channel, channel + 1, branch >> 1, bank, | |
500 | rdwr ? "Write" : "Read", ras, cas); | |
501 | ||
502 | /* Only 1 bit will be on */ | |
503 | if (allErrors & FERR_FAT_M1ERR) { | |
504 | i5000_mc_printk(mci, KERN_ERR, | |
505 | "Alert on non-redundant retry or fast " | |
506 | "reset timeout\n"); | |
507 | ||
508 | } else if (allErrors & FERR_FAT_M2ERR) { | |
509 | i5000_mc_printk(mci, KERN_ERR, | |
510 | "Northbound CRC error on non-redundant " | |
511 | "retry\n"); | |
512 | ||
513 | } else if (allErrors & FERR_FAT_M3ERR) { | |
514 | i5000_mc_printk(mci, KERN_ERR, | |
515 | ">Tmid Thermal event with intelligent " | |
516 | "throttling disabled\n"); | |
517 | } | |
518 | ||
519 | /* Form out message */ | |
520 | snprintf(msg, sizeof(msg), | |
521 | "(Branch=%d DRAM-Bank=%d RDWR=%s RAS=%d CAS=%d " | |
522 | "FATAL Err=0x%x)", | |
523 | branch >> 1, bank, rdwr ? "Write" : "Read", ras, cas, | |
524 | allErrors); | |
525 | ||
526 | /* Call the helper to output message */ | |
527 | edac_mc_handle_fbd_ue(mci, rank, channel, channel + 1, msg); | |
528 | } | |
529 | ||
530 | /****************************************************************************** | |
531 | * i5000_process_fatal_error_info(struct mem_ctl_info *mci, | |
532 | * struct i5000_error_info *info, | |
533 | * int handle_errors); | |
534 | * | |
535 | * handle the Intel NON-FATAL errors, if any | |
536 | */ | |
537 | static void i5000_process_nonfatal_error_info(struct mem_ctl_info *mci, | |
538 | struct i5000_error_info * info, | |
539 | int handle_errors) | |
540 | { | |
541 | char msg[EDAC_MC_LABEL_LEN + 1 + 90]; | |
542 | u32 allErrors; | |
543 | u32 ue_errors; | |
544 | u32 ce_errors; | |
545 | u32 misc_errors; | |
546 | int branch; | |
547 | int channel; | |
548 | int bank; | |
549 | int rank; | |
550 | int rdwr; | |
551 | int ras, cas; | |
552 | ||
553 | /* mask off the Error bits that are possible */ | |
554 | allErrors = (info->ferr_nf_fbd & FERR_NF_MASK); | |
555 | if (!allErrors) | |
556 | return; /* if no error, return now */ | |
557 | ||
558 | /* ONLY ONE of the possible error bits will be set, as per the docs */ | |
559 | i5000_mc_printk(mci, KERN_WARNING, | |
560 | "NON-FATAL ERRORS Found!!! 1st NON-FATAL Err " | |
561 | "Reg= 0x%x\n", allErrors); | |
562 | ||
563 | ue_errors = allErrors & FERR_NF_UNCORRECTABLE; | |
564 | if (ue_errors) { | |
565 | debugf0("\tUncorrected bits= 0x%x\n", ue_errors); | |
566 | ||
567 | branch = EXTRACT_FBDCHAN_INDX(info->ferr_nf_fbd); | |
568 | channel = branch; | |
569 | bank = NREC_BANK(info->nrecmema); | |
570 | rank = NREC_RANK(info->nrecmema); | |
571 | rdwr = NREC_RDWR(info->nrecmema); | |
572 | ras = NREC_RAS(info->nrecmemb); | |
573 | cas = NREC_CAS(info->nrecmemb); | |
574 | ||
575 | debugf0 | |
576 | ("\t\tCSROW= %d Channels= %d,%d (Branch= %d " | |
577 | "DRAM Bank= %d rdwr= %s ras= %d cas= %d)\n", | |
578 | rank, channel, channel + 1, branch >> 1, bank, | |
579 | rdwr ? "Write" : "Read", ras, cas); | |
580 | ||
581 | /* Form out message */ | |
582 | snprintf(msg, sizeof(msg), | |
583 | "(Branch=%d DRAM-Bank=%d RDWR=%s RAS=%d " | |
584 | "CAS=%d, UE Err=0x%x)", | |
585 | branch >> 1, bank, rdwr ? "Write" : "Read", ras, cas, | |
586 | ue_errors); | |
587 | ||
588 | /* Call the helper to output message */ | |
589 | edac_mc_handle_fbd_ue(mci, rank, channel, channel + 1, msg); | |
590 | } | |
591 | ||
592 | /* Check correctable errors */ | |
593 | ce_errors = allErrors & FERR_NF_CORRECTABLE; | |
594 | if (ce_errors) { | |
595 | debugf0("\tCorrected bits= 0x%x\n", ce_errors); | |
596 | ||
597 | branch = EXTRACT_FBDCHAN_INDX(info->ferr_nf_fbd); | |
598 | ||
599 | channel = 0; | |
600 | if (REC_ECC_LOCATOR_ODD(info->redmemb)) | |
601 | channel = 1; | |
602 | ||
603 | /* Convert channel to be based from zero, instead of | |
604 | * from branch base of 0 */ | |
605 | channel += branch; | |
606 | ||
607 | bank = REC_BANK(info->recmema); | |
608 | rank = REC_RANK(info->recmema); | |
609 | rdwr = REC_RDWR(info->recmema); | |
610 | ras = REC_RAS(info->recmemb); | |
611 | cas = REC_CAS(info->recmemb); | |
612 | ||
613 | debugf0("\t\tCSROW= %d Channel= %d (Branch %d " | |
614 | "DRAM Bank= %d rdwr= %s ras= %d cas= %d)\n", | |
615 | rank, channel, branch >> 1, bank, | |
616 | rdwr ? "Write" : "Read", ras, cas); | |
617 | ||
618 | /* Form out message */ | |
619 | snprintf(msg, sizeof(msg), | |
620 | "(Branch=%d DRAM-Bank=%d RDWR=%s RAS=%d " | |
621 | "CAS=%d, CE Err=0x%x)", branch >> 1, bank, | |
622 | rdwr ? "Write" : "Read", ras, cas, ce_errors); | |
623 | ||
624 | /* Call the helper to output message */ | |
625 | edac_mc_handle_fbd_ce(mci, rank, channel, msg); | |
626 | } | |
627 | ||
628 | /* See if any of the thermal errors have fired */ | |
629 | misc_errors = allErrors & FERR_NF_THERMAL; | |
630 | if (misc_errors) { | |
631 | i5000_printk(KERN_WARNING, "\tTHERMAL Error, bits= 0x%x\n", | |
632 | misc_errors); | |
633 | } | |
634 | ||
635 | /* See if any of the thermal errors have fired */ | |
636 | misc_errors = allErrors & FERR_NF_NON_RETRY; | |
637 | if (misc_errors) { | |
638 | i5000_printk(KERN_WARNING, "\tNON-Retry Errors, bits= 0x%x\n", | |
639 | misc_errors); | |
640 | } | |
641 | ||
642 | /* See if any of the thermal errors have fired */ | |
643 | misc_errors = allErrors & FERR_NF_NORTH_CRC; | |
644 | if (misc_errors) { | |
645 | i5000_printk(KERN_WARNING, | |
646 | "\tNORTHBOUND CRC Error, bits= 0x%x\n", | |
647 | misc_errors); | |
648 | } | |
649 | ||
650 | /* See if any of the thermal errors have fired */ | |
651 | misc_errors = allErrors & FERR_NF_SPD_PROTOCOL; | |
652 | if (misc_errors) { | |
653 | i5000_printk(KERN_WARNING, | |
654 | "\tSPD Protocol Error, bits= 0x%x\n", | |
655 | misc_errors); | |
656 | } | |
657 | ||
658 | /* See if any of the thermal errors have fired */ | |
659 | misc_errors = allErrors & FERR_NF_DIMM_SPARE; | |
660 | if (misc_errors) { | |
661 | i5000_printk(KERN_WARNING, "\tDIMM-Spare Error, bits= 0x%x\n", | |
662 | misc_errors); | |
663 | } | |
664 | } | |
665 | ||
666 | /****************************************************************************** | |
667 | * i5000_process_error_info Process the error info that is | |
668 | * in the 'info' structure, previously retrieved from hardware | |
669 | */ | |
670 | static void i5000_process_error_info(struct mem_ctl_info *mci, | |
671 | struct i5000_error_info * info, | |
672 | int handle_errors) | |
673 | { | |
674 | /* First handle any fatal errors that occurred */ | |
675 | i5000_process_fatal_error_info(mci, info, handle_errors); | |
676 | ||
677 | /* now handle any non-fatal errors that occurred */ | |
678 | i5000_process_nonfatal_error_info(mci, info, handle_errors); | |
679 | } | |
680 | ||
681 | /****************************************************************************** | |
682 | * i5000_clear_error Retrieve any error from the hardware | |
683 | * but do NOT process that error. | |
684 | * Used for 'clearing' out of previous errors | |
685 | * Called by the Core module. | |
686 | */ | |
687 | static void i5000_clear_error(struct mem_ctl_info *mci) | |
688 | { | |
689 | struct i5000_error_info info; | |
690 | ||
691 | i5000_get_error_info(mci, &info); | |
692 | } | |
693 | ||
694 | /****************************************************************************** | |
695 | * i5000_check_error Retrieve and process errors reported by the | |
696 | * hardware. Called by the Core module. | |
697 | */ | |
698 | static void i5000_check_error(struct mem_ctl_info *mci) | |
699 | { | |
700 | struct i5000_error_info info; | |
701 | debugf4("MC%d: " __FILE__ ": %s()\n", mci->mc_idx, __func__); | |
702 | i5000_get_error_info(mci, &info); | |
703 | i5000_process_error_info(mci, &info, 1); | |
704 | } | |
705 | ||
706 | /****************************************************************************** | |
707 | * i5000_get_devices Find and perform 'get' operation on the MCH's | |
708 | * device/functions we want to reference for this driver | |
709 | * | |
710 | * Need to 'get' device 16 func 1 and func 2 | |
711 | */ | |
712 | static int i5000_get_devices(struct mem_ctl_info *mci, int dev_idx) | |
713 | { | |
714 | //const struct i5000_dev_info *i5000_dev = &i5000_devs[dev_idx]; | |
715 | struct i5000_pvt *pvt; | |
716 | struct pci_dev *pdev; | |
717 | ||
718 | pvt = (struct i5000_pvt *)mci->pvt_info; | |
719 | ||
720 | /* Attempt to 'get' the MCH register we want */ | |
721 | pdev = NULL; | |
722 | while (1) { | |
723 | pdev = pci_get_device(PCI_VENDOR_ID_INTEL, | |
724 | PCI_DEVICE_ID_INTEL_I5000_DEV16, pdev); | |
725 | ||
726 | /* End of list, leave */ | |
727 | if (pdev == NULL) { | |
728 | i5000_printk(KERN_ERR, | |
729 | "'system address,Process Bus' " | |
730 | "device not found:" | |
731 | "vendor 0x%x device 0x%x FUNC 1 " | |
732 | "(broken BIOS?)\n", | |
733 | PCI_VENDOR_ID_INTEL, | |
734 | PCI_DEVICE_ID_INTEL_I5000_DEV16); | |
735 | ||
736 | return 1; | |
737 | } | |
738 | ||
739 | /* Scan for device 16 func 1 */ | |
740 | if (PCI_FUNC(pdev->devfn) == 1) | |
741 | break; | |
742 | } | |
743 | ||
744 | pvt->branchmap_werrors = pdev; | |
745 | ||
746 | /* Attempt to 'get' the MCH register we want */ | |
747 | pdev = NULL; | |
748 | while (1) { | |
749 | pdev = pci_get_device(PCI_VENDOR_ID_INTEL, | |
750 | PCI_DEVICE_ID_INTEL_I5000_DEV16, pdev); | |
751 | ||
752 | if (pdev == NULL) { | |
753 | i5000_printk(KERN_ERR, | |
754 | "MC: 'branchmap,control,errors' " | |
755 | "device not found:" | |
756 | "vendor 0x%x device 0x%x Func 2 " | |
757 | "(broken BIOS?)\n", | |
758 | PCI_VENDOR_ID_INTEL, | |
759 | PCI_DEVICE_ID_INTEL_I5000_DEV16); | |
760 | ||
761 | pci_dev_put(pvt->branchmap_werrors); | |
762 | return 1; | |
763 | } | |
764 | ||
765 | /* Scan for device 16 func 1 */ | |
766 | if (PCI_FUNC(pdev->devfn) == 2) | |
767 | break; | |
768 | } | |
769 | ||
770 | pvt->fsb_error_regs = pdev; | |
771 | ||
772 | debugf1("System Address, processor bus- PCI Bus ID: %s %x:%x\n", | |
773 | pci_name(pvt->system_address), | |
774 | pvt->system_address->vendor, pvt->system_address->device); | |
775 | debugf1("Branchmap, control and errors - PCI Bus ID: %s %x:%x\n", | |
776 | pci_name(pvt->branchmap_werrors), | |
777 | pvt->branchmap_werrors->vendor, pvt->branchmap_werrors->device); | |
778 | debugf1("FSB Error Regs - PCI Bus ID: %s %x:%x\n", | |
779 | pci_name(pvt->fsb_error_regs), | |
780 | pvt->fsb_error_regs->vendor, pvt->fsb_error_regs->device); | |
781 | ||
782 | pdev = NULL; | |
783 | pdev = pci_get_device(PCI_VENDOR_ID_INTEL, | |
784 | PCI_DEVICE_ID_I5000_BRANCH_0, pdev); | |
785 | ||
786 | if (pdev == NULL) { | |
787 | i5000_printk(KERN_ERR, | |
788 | "MC: 'BRANCH 0' device not found:" | |
789 | "vendor 0x%x device 0x%x Func 0 (broken BIOS?)\n", | |
790 | PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_I5000_BRANCH_0); | |
791 | ||
792 | pci_dev_put(pvt->branchmap_werrors); | |
793 | pci_dev_put(pvt->fsb_error_regs); | |
794 | return 1; | |
795 | } | |
796 | ||
797 | pvt->branch_0 = pdev; | |
798 | ||
799 | /* If this device claims to have more than 2 channels then | |
800 | * fetch Branch 1's information | |
801 | */ | |
802 | if (pvt->maxch >= CHANNELS_PER_BRANCH) { | |
803 | pdev = NULL; | |
804 | pdev = pci_get_device(PCI_VENDOR_ID_INTEL, | |
805 | PCI_DEVICE_ID_I5000_BRANCH_1, pdev); | |
806 | ||
807 | if (pdev == NULL) { | |
808 | i5000_printk(KERN_ERR, | |
809 | "MC: 'BRANCH 1' device not found:" | |
810 | "vendor 0x%x device 0x%x Func 0 " | |
811 | "(broken BIOS?)\n", | |
812 | PCI_VENDOR_ID_INTEL, | |
813 | PCI_DEVICE_ID_I5000_BRANCH_1); | |
814 | ||
815 | pci_dev_put(pvt->branchmap_werrors); | |
816 | pci_dev_put(pvt->fsb_error_regs); | |
817 | pci_dev_put(pvt->branch_0); | |
818 | return 1; | |
819 | } | |
820 | ||
821 | pvt->branch_1 = pdev; | |
822 | } | |
823 | ||
824 | return 0; | |
825 | } | |
826 | ||
827 | /****************************************************************************** | |
828 | * i5000_put_devices 'put' all the devices that we have | |
829 | * reserved via 'get' | |
830 | */ | |
831 | static void i5000_put_devices(struct mem_ctl_info *mci) | |
832 | { | |
833 | struct i5000_pvt *pvt; | |
834 | ||
835 | pvt = (struct i5000_pvt *)mci->pvt_info; | |
836 | ||
837 | pci_dev_put(pvt->branchmap_werrors); /* FUNC 1 */ | |
838 | pci_dev_put(pvt->fsb_error_regs); /* FUNC 2 */ | |
839 | pci_dev_put(pvt->branch_0); /* DEV 21 */ | |
840 | ||
841 | /* Only if more than 2 channels do we release the second branch */ | |
842 | if (pvt->maxch >= CHANNELS_PER_BRANCH) { | |
843 | pci_dev_put(pvt->branch_1); /* DEV 22 */ | |
844 | } | |
845 | } | |
846 | ||
847 | /****************************************************************************** | |
848 | * determine_amb_resent | |
849 | * | |
850 | * the information is contained in NUM_MTRS different registers | |
851 | * determineing which of the NUM_MTRS requires knowing | |
852 | * which channel is in question | |
853 | * | |
854 | * 2 branches, each with 2 channels | |
855 | * b0_ambpresent0 for channel '0' | |
856 | * b0_ambpresent1 for channel '1' | |
857 | * b1_ambpresent0 for channel '2' | |
858 | * b1_ambpresent1 for channel '3' | |
859 | */ | |
860 | static int determine_amb_present_reg(struct i5000_pvt *pvt, int channel) | |
861 | { | |
862 | int amb_present; | |
863 | ||
864 | if (channel < CHANNELS_PER_BRANCH) { | |
865 | if (channel & 0x1) | |
866 | amb_present = pvt->b0_ambpresent1; | |
867 | else | |
868 | amb_present = pvt->b0_ambpresent0; | |
869 | } else { | |
870 | if (channel & 0x1) | |
871 | amb_present = pvt->b1_ambpresent1; | |
872 | else | |
873 | amb_present = pvt->b1_ambpresent0; | |
874 | } | |
875 | ||
876 | return amb_present; | |
877 | } | |
878 | ||
879 | /****************************************************************************** | |
880 | * determine_mtr(pvt, csrow, channel) | |
881 | * | |
882 | * return the proper MTR register as determine by the csrow and channel desired | |
883 | */ | |
884 | static int determine_mtr(struct i5000_pvt *pvt, int csrow, int channel) | |
885 | { | |
886 | int mtr; | |
887 | ||
888 | if (channel < CHANNELS_PER_BRANCH) | |
889 | mtr = pvt->b0_mtr[csrow >> 1]; | |
890 | else | |
891 | mtr = pvt->b1_mtr[csrow >> 1]; | |
892 | ||
893 | return mtr; | |
894 | } | |
895 | ||
896 | /****************************************************************************** | |
897 | */ | |
898 | static void decode_mtr(int slot_row, u16 mtr) | |
899 | { | |
900 | int ans; | |
901 | ||
902 | ans = MTR_DIMMS_PRESENT(mtr); | |
903 | ||
904 | debugf2("\tMTR%d=0x%x: DIMMs are %s\n", slot_row, mtr, | |
905 | ans ? "Present" : "NOT Present"); | |
906 | if (!ans) | |
907 | return; | |
908 | ||
909 | debugf2("\t\tWIDTH: x%d\n", MTR_DRAM_WIDTH(mtr)); | |
910 | debugf2("\t\tNUMBANK: %d bank(s)\n", MTR_DRAM_BANKS(mtr)); | |
911 | debugf2("\t\tNUMRANK: %s\n", MTR_DIMM_RANK(mtr) ? "double" : "single"); | |
912 | debugf2("\t\tNUMROW: %s\n", numrow_toString[MTR_DIMM_ROWS(mtr)]); | |
913 | debugf2("\t\tNUMCOL: %s\n", numcol_toString[MTR_DIMM_COLS(mtr)]); | |
914 | } | |
915 | ||
916 | static void handle_channel(struct i5000_pvt *pvt, int csrow, int channel, | |
917 | struct i5000_dimm_info *dinfo) | |
918 | { | |
919 | int mtr; | |
920 | int amb_present_reg; | |
921 | int addrBits; | |
922 | ||
923 | mtr = determine_mtr(pvt, csrow, channel); | |
924 | if (MTR_DIMMS_PRESENT(mtr)) { | |
925 | amb_present_reg = determine_amb_present_reg(pvt, channel); | |
926 | ||
927 | /* Determine if there is a DIMM present in this DIMM slot */ | |
928 | if (amb_present_reg & (1 << (csrow >> 1))) { | |
929 | dinfo->dual_rank = MTR_DIMM_RANK(mtr); | |
930 | ||
931 | if (!((dinfo->dual_rank == 0) && | |
932 | ((csrow & 0x1) == 0x1))) { | |
933 | /* Start with the number of bits for a Bank | |
934 | * on the DRAM */ | |
935 | addrBits = MTR_DRAM_BANKS_ADDR_BITS(mtr); | |
936 | /* Add thenumber of ROW bits */ | |
937 | addrBits += MTR_DIMM_ROWS_ADDR_BITS(mtr); | |
938 | /* add the number of COLUMN bits */ | |
939 | addrBits += MTR_DIMM_COLS_ADDR_BITS(mtr); | |
940 | ||
941 | addrBits += 6; /* add 64 bits per DIMM */ | |
942 | addrBits -= 20; /* divide by 2^^20 */ | |
943 | addrBits -= 3; /* 8 bits per bytes */ | |
944 | ||
945 | dinfo->megabytes = 1 << addrBits; | |
946 | } | |
947 | } | |
948 | } | |
949 | } | |
950 | ||
951 | /****************************************************************************** | |
952 | * calculate_dimm_size | |
953 | * | |
954 | * also will output a DIMM matrix map, if debug is enabled, for viewing | |
955 | * how the DIMMs are populated | |
956 | */ | |
957 | static void calculate_dimm_size(struct i5000_pvt *pvt) | |
958 | { | |
959 | struct i5000_dimm_info *dinfo; | |
960 | int csrow, max_csrows; | |
961 | char *p, *mem_buffer; | |
962 | int space, n; | |
963 | int channel; | |
964 | ||
965 | /* ================= Generate some debug output ================= */ | |
966 | space = PAGE_SIZE; | |
967 | mem_buffer = p = kmalloc(space, GFP_KERNEL); | |
968 | if (p == NULL) { | |
969 | i5000_printk(KERN_ERR, "MC: %s:%s() kmalloc() failed\n", | |
f4aff426 | 970 | __FILE__, __func__); |
eb60705a EW |
971 | return; |
972 | } | |
973 | ||
974 | n = snprintf(p, space, "\n"); | |
975 | p += n; | |
976 | space -= n; | |
977 | ||
978 | /* Scan all the actual CSROWS (which is # of DIMMS * 2) | |
979 | * and calculate the information for each DIMM | |
980 | * Start with the highest csrow first, to display it first | |
981 | * and work toward the 0th csrow | |
982 | */ | |
983 | max_csrows = pvt->maxdimmperch * 2; | |
984 | for (csrow = max_csrows - 1; csrow >= 0; csrow--) { | |
985 | ||
986 | /* on an odd csrow, first output a 'boundary' marker, | |
987 | * then reset the message buffer */ | |
988 | if (csrow & 0x1) { | |
989 | n = snprintf(p, space, "---------------------------" | |
990 | "--------------------------------"); | |
991 | p += n; | |
992 | space -= n; | |
993 | debugf2("%s\n", mem_buffer); | |
994 | p = mem_buffer; | |
995 | space = PAGE_SIZE; | |
996 | } | |
997 | n = snprintf(p, space, "csrow %2d ", csrow); | |
998 | p += n; | |
999 | space -= n; | |
1000 | ||
1001 | for (channel = 0; channel < pvt->maxch; channel++) { | |
1002 | dinfo = &pvt->dimm_info[csrow][channel]; | |
1003 | handle_channel(pvt, csrow, channel, dinfo); | |
1004 | n = snprintf(p, space, "%4d MB | ", dinfo->megabytes); | |
1005 | p += n; | |
1006 | space -= n; | |
1007 | } | |
1008 | n = snprintf(p, space, "\n"); | |
1009 | p += n; | |
1010 | space -= n; | |
1011 | } | |
1012 | ||
1013 | /* Output the last bottom 'boundary' marker */ | |
1014 | n = snprintf(p, space, "---------------------------" | |
1015 | "--------------------------------\n"); | |
1016 | p += n; | |
1017 | space -= n; | |
1018 | ||
1019 | /* now output the 'channel' labels */ | |
1020 | n = snprintf(p, space, " "); | |
1021 | p += n; | |
1022 | space -= n; | |
1023 | for (channel = 0; channel < pvt->maxch; channel++) { | |
1024 | n = snprintf(p, space, "channel %d | ", channel); | |
1025 | p += n; | |
1026 | space -= n; | |
1027 | } | |
1028 | n = snprintf(p, space, "\n"); | |
1029 | p += n; | |
1030 | space -= n; | |
1031 | ||
1032 | /* output the last message and free buffer */ | |
1033 | debugf2("%s\n", mem_buffer); | |
1034 | kfree(mem_buffer); | |
1035 | } | |
1036 | ||
1037 | /****************************************************************************** | |
1038 | * i5000_get_mc_regs read in the necessary registers and | |
1039 | * cache locally | |
1040 | * | |
1041 | * Fills in the private data members | |
1042 | */ | |
1043 | static void i5000_get_mc_regs(struct mem_ctl_info *mci) | |
1044 | { | |
1045 | struct i5000_pvt *pvt; | |
1046 | u32 actual_tolm; | |
1047 | u16 limit; | |
1048 | int slot_row; | |
1049 | int maxch; | |
1050 | int maxdimmperch; | |
1051 | int way0, way1; | |
1052 | ||
1053 | pvt = (struct i5000_pvt *)mci->pvt_info; | |
1054 | ||
1055 | pci_read_config_dword(pvt->system_address, AMBASE, | |
1056 | (u32 *) & pvt->ambase); | |
1057 | pci_read_config_dword(pvt->system_address, AMBASE + sizeof(u32), | |
1058 | ((u32 *) & pvt->ambase) + sizeof(u32)); | |
1059 | ||
1060 | maxdimmperch = pvt->maxdimmperch; | |
1061 | maxch = pvt->maxch; | |
1062 | ||
1063 | debugf2("AMBASE= 0x%lx MAXCH= %d MAX-DIMM-Per-CH= %d\n", | |
1064 | (long unsigned int)pvt->ambase, pvt->maxch, pvt->maxdimmperch); | |
1065 | ||
1066 | /* Get the Branch Map regs */ | |
1067 | pci_read_config_word(pvt->branchmap_werrors, TOLM, &pvt->tolm); | |
1068 | pvt->tolm >>= 12; | |
1069 | debugf2("\nTOLM (number of 256M regions) =%u (0x%x)\n", pvt->tolm, | |
1070 | pvt->tolm); | |
1071 | ||
1072 | actual_tolm = pvt->tolm << 28; | |
1073 | debugf2("Actual TOLM byte addr=%u (0x%x)\n", actual_tolm, actual_tolm); | |
1074 | ||
1075 | pci_read_config_word(pvt->branchmap_werrors, MIR0, &pvt->mir0); | |
1076 | pci_read_config_word(pvt->branchmap_werrors, MIR1, &pvt->mir1); | |
1077 | pci_read_config_word(pvt->branchmap_werrors, MIR2, &pvt->mir2); | |
1078 | ||
1079 | /* Get the MIR[0-2] regs */ | |
1080 | limit = (pvt->mir0 >> 4) & 0x0FFF; | |
1081 | way0 = pvt->mir0 & 0x1; | |
1082 | way1 = pvt->mir0 & 0x2; | |
1083 | debugf2("MIR0: limit= 0x%x WAY1= %u WAY0= %x\n", limit, way1, way0); | |
1084 | limit = (pvt->mir1 >> 4) & 0x0FFF; | |
1085 | way0 = pvt->mir1 & 0x1; | |
1086 | way1 = pvt->mir1 & 0x2; | |
1087 | debugf2("MIR1: limit= 0x%x WAY1= %u WAY0= %x\n", limit, way1, way0); | |
1088 | limit = (pvt->mir2 >> 4) & 0x0FFF; | |
1089 | way0 = pvt->mir2 & 0x1; | |
1090 | way1 = pvt->mir2 & 0x2; | |
1091 | debugf2("MIR2: limit= 0x%x WAY1= %u WAY0= %x\n", limit, way1, way0); | |
1092 | ||
1093 | /* Get the MTR[0-3] regs */ | |
1094 | for (slot_row = 0; slot_row < NUM_MTRS; slot_row++) { | |
1095 | int where = MTR0 + (slot_row * sizeof(u32)); | |
1096 | ||
1097 | pci_read_config_word(pvt->branch_0, where, | |
1098 | &pvt->b0_mtr[slot_row]); | |
1099 | ||
1100 | debugf2("MTR%d where=0x%x B0 value=0x%x\n", slot_row, where, | |
1101 | pvt->b0_mtr[slot_row]); | |
1102 | ||
1103 | if (pvt->maxch >= CHANNELS_PER_BRANCH) { | |
1104 | pci_read_config_word(pvt->branch_1, where, | |
1105 | &pvt->b1_mtr[slot_row]); | |
1106 | debugf2("MTR%d where=0x%x B1 value=0x%x\n", slot_row, | |
1107 | where, pvt->b0_mtr[slot_row]); | |
1108 | } else { | |
1109 | pvt->b1_mtr[slot_row] = 0; | |
1110 | } | |
1111 | } | |
1112 | ||
1113 | /* Read and dump branch 0's MTRs */ | |
1114 | debugf2("\nMemory Technology Registers:\n"); | |
1115 | debugf2(" Branch 0:\n"); | |
1116 | for (slot_row = 0; slot_row < NUM_MTRS; slot_row++) { | |
1117 | decode_mtr(slot_row, pvt->b0_mtr[slot_row]); | |
1118 | } | |
1119 | pci_read_config_word(pvt->branch_0, AMB_PRESENT_0, | |
1120 | &pvt->b0_ambpresent0); | |
1121 | debugf2("\t\tAMB-Branch 0-present0 0x%x:\n", pvt->b0_ambpresent0); | |
1122 | pci_read_config_word(pvt->branch_0, AMB_PRESENT_1, | |
1123 | &pvt->b0_ambpresent1); | |
1124 | debugf2("\t\tAMB-Branch 0-present1 0x%x:\n", pvt->b0_ambpresent1); | |
1125 | ||
1126 | /* Only if we have 2 branchs (4 channels) */ | |
1127 | if (pvt->maxch < CHANNELS_PER_BRANCH) { | |
1128 | pvt->b1_ambpresent0 = 0; | |
1129 | pvt->b1_ambpresent1 = 0; | |
1130 | } else { | |
1131 | /* Read and dump branch 1's MTRs */ | |
1132 | debugf2(" Branch 1:\n"); | |
1133 | for (slot_row = 0; slot_row < NUM_MTRS; slot_row++) { | |
1134 | decode_mtr(slot_row, pvt->b1_mtr[slot_row]); | |
1135 | } | |
1136 | pci_read_config_word(pvt->branch_1, AMB_PRESENT_0, | |
1137 | &pvt->b1_ambpresent0); | |
1138 | debugf2("\t\tAMB-Branch 1-present0 0x%x:\n", | |
1139 | pvt->b1_ambpresent0); | |
1140 | pci_read_config_word(pvt->branch_1, AMB_PRESENT_1, | |
1141 | &pvt->b1_ambpresent1); | |
1142 | debugf2("\t\tAMB-Branch 1-present1 0x%x:\n", | |
1143 | pvt->b1_ambpresent1); | |
1144 | } | |
1145 | ||
1146 | /* Go and determine the size of each DIMM and place in an | |
1147 | * orderly matrix */ | |
1148 | calculate_dimm_size(pvt); | |
1149 | } | |
1150 | ||
1151 | /****************************************************************************** | |
1152 | * i5000_init_csrows Initialize the 'csrows' table within | |
1153 | * the mci control structure with the | |
1154 | * addressing of memory. | |
1155 | * | |
1156 | * return: | |
1157 | * 0 success | |
1158 | * 1 no actual memory found on this MC | |
1159 | */ | |
1160 | static int i5000_init_csrows(struct mem_ctl_info *mci) | |
1161 | { | |
1162 | struct i5000_pvt *pvt; | |
1163 | struct csrow_info *p_csrow; | |
1164 | int empty, channel_count; | |
1165 | int max_csrows; | |
1166 | int mtr; | |
1167 | int csrow_megs; | |
1168 | int channel; | |
1169 | int csrow; | |
1170 | ||
1171 | pvt = (struct i5000_pvt *)mci->pvt_info; | |
1172 | ||
1173 | channel_count = pvt->maxch; | |
1174 | max_csrows = pvt->maxdimmperch * 2; | |
1175 | ||
1176 | empty = 1; /* Assume NO memory */ | |
1177 | ||
1178 | for (csrow = 0; csrow < max_csrows; csrow++) { | |
1179 | p_csrow = &mci->csrows[csrow]; | |
1180 | ||
1181 | p_csrow->csrow_idx = csrow; | |
1182 | ||
1183 | /* use branch 0 for the basis */ | |
1184 | mtr = pvt->b0_mtr[csrow >> 1]; | |
1185 | ||
1186 | /* if no DIMMS on this row, continue */ | |
1187 | if (!MTR_DIMMS_PRESENT(mtr)) | |
1188 | continue; | |
1189 | ||
1190 | /* FAKE OUT VALUES, FIXME */ | |
1191 | p_csrow->first_page = 0 + csrow * 20; | |
1192 | p_csrow->last_page = 9 + csrow * 20; | |
1193 | p_csrow->page_mask = 0xFFF; | |
1194 | ||
1195 | p_csrow->grain = 8; | |
1196 | ||
1197 | csrow_megs = 0; | |
1198 | for (channel = 0; channel < pvt->maxch; channel++) { | |
1199 | csrow_megs += pvt->dimm_info[csrow][channel].megabytes; | |
1200 | } | |
1201 | ||
1202 | p_csrow->nr_pages = csrow_megs << 8; | |
1203 | ||
1204 | /* Assume DDR2 for now */ | |
1205 | p_csrow->mtype = MEM_FB_DDR2; | |
1206 | ||
1207 | /* ask what device type on this row */ | |
1208 | if (MTR_DRAM_WIDTH(mtr)) | |
1209 | p_csrow->dtype = DEV_X8; | |
1210 | else | |
1211 | p_csrow->dtype = DEV_X4; | |
1212 | ||
1213 | p_csrow->edac_mode = EDAC_S8ECD8ED; | |
1214 | ||
1215 | empty = 0; | |
1216 | } | |
1217 | ||
1218 | return empty; | |
1219 | } | |
1220 | ||
1221 | /****************************************************************************** | |
1222 | * i5000_enable_error_reporting | |
1223 | * Turn on the memory reporting features of the hardware | |
1224 | */ | |
1225 | static void i5000_enable_error_reporting(struct mem_ctl_info *mci) | |
1226 | { | |
1227 | struct i5000_pvt *pvt; | |
1228 | u32 fbd_error_mask; | |
1229 | ||
1230 | pvt = (struct i5000_pvt *)mci->pvt_info; | |
1231 | ||
1232 | /* Read the FBD Error Mask Register */ | |
1233 | pci_read_config_dword(pvt->branchmap_werrors, EMASK_FBD, | |
1234 | &fbd_error_mask); | |
1235 | ||
1236 | /* Enable with a '0' */ | |
1237 | fbd_error_mask &= ~(ENABLE_EMASK_ALL); | |
1238 | ||
1239 | pci_write_config_dword(pvt->branchmap_werrors, EMASK_FBD, | |
1240 | fbd_error_mask); | |
1241 | } | |
1242 | ||
1243 | /****************************************************************************** | |
1244 | * i5000_get_dimm_and_channel_counts(pdev, &num_csrows, &num_channels) | |
1245 | * | |
1246 | * ask the device how many channels are present and how many CSROWS | |
1247 | * as well | |
1248 | */ | |
1249 | static void i5000_get_dimm_and_channel_counts(struct pci_dev *pdev, | |
1250 | int *num_dimms_per_channel, | |
1251 | int *num_channels) | |
1252 | { | |
1253 | u8 value; | |
1254 | ||
1255 | /* Need to retrieve just how many channels and dimms per channel are | |
1256 | * supported on this memory controller | |
1257 | */ | |
1258 | pci_read_config_byte(pdev, MAXDIMMPERCH, &value); | |
1259 | *num_dimms_per_channel = (int)value *2; | |
1260 | ||
1261 | pci_read_config_byte(pdev, MAXCH, &value); | |
1262 | *num_channels = (int)value; | |
1263 | } | |
1264 | ||
1265 | /****************************************************************************** | |
1266 | * i5000_probe1 Probe for ONE instance of device to see if it is | |
1267 | * present. | |
1268 | * return: | |
1269 | * 0 for FOUND a device | |
1270 | * < 0 for error code | |
1271 | */ | |
1272 | static int i5000_probe1(struct pci_dev *pdev, int dev_idx) | |
1273 | { | |
1274 | struct mem_ctl_info *mci; | |
1275 | struct i5000_pvt *pvt; | |
1276 | int num_channels; | |
1277 | int num_dimms_per_channel; | |
1278 | int num_csrows; | |
1279 | ||
1280 | debugf0("MC: " __FILE__ ": %s(), pdev bus %u dev=0x%x fn=0x%x\n", | |
1281 | __func__, | |
1282 | pdev->bus->number, | |
1283 | PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn)); | |
1284 | ||
1285 | /* We only are looking for func 0 of the set */ | |
1286 | if (PCI_FUNC(pdev->devfn) != 0) | |
1287 | return -ENODEV; | |
1288 | ||
c0d12172 | 1289 | /* make sure error reporting method is sane */ |
f4aff426 DT |
1290 | switch (edac_op_state) { |
1291 | case EDAC_OPSTATE_POLL: | |
1292 | case EDAC_OPSTATE_NMI: | |
1293 | break; | |
1294 | default: | |
1295 | edac_op_state = EDAC_OPSTATE_POLL; | |
1296 | break; | |
c0d12172 DJ |
1297 | } |
1298 | ||
eb60705a EW |
1299 | /* Ask the devices for the number of CSROWS and CHANNELS so |
1300 | * that we can calculate the memory resources, etc | |
1301 | * | |
1302 | * The Chipset will report what it can handle which will be greater | |
1303 | * or equal to what the motherboard manufacturer will implement. | |
1304 | * | |
1305 | * As we don't have a motherboard identification routine to determine | |
1306 | * actual number of slots/dimms per channel, we thus utilize the | |
1307 | * resource as specified by the chipset. Thus, we might have | |
1308 | * have more DIMMs per channel than actually on the mobo, but this | |
1309 | * allows the driver to support upto the chipset max, without | |
1310 | * some fancy mobo determination. | |
1311 | */ | |
1312 | i5000_get_dimm_and_channel_counts(pdev, &num_dimms_per_channel, | |
1313 | &num_channels); | |
1314 | num_csrows = num_dimms_per_channel * 2; | |
1315 | ||
1316 | debugf0("MC: %s(): Number of - Channels= %d DIMMS= %d CSROWS= %d\n", | |
1317 | __func__, num_channels, num_dimms_per_channel, num_csrows); | |
1318 | ||
1319 | /* allocate a new MC control structure */ | |
1320 | mci = edac_mc_alloc(sizeof(*pvt), num_csrows, num_channels); | |
1321 | ||
1322 | if (mci == NULL) | |
1323 | return -ENOMEM; | |
1324 | ||
1325 | debugf0("MC: " __FILE__ ": %s(): mci = %p\n", __func__, mci); | |
1326 | ||
1327 | mci->dev = &pdev->dev; /* record ptr to the generic device */ | |
1328 | ||
1329 | pvt = (struct i5000_pvt *)mci->pvt_info; | |
1330 | pvt->system_address = pdev; /* Record this device in our private */ | |
1331 | pvt->maxch = num_channels; | |
1332 | pvt->maxdimmperch = num_dimms_per_channel; | |
1333 | ||
1334 | /* 'get' the pci devices we want to reserve for our use */ | |
1335 | if (i5000_get_devices(mci, dev_idx)) | |
1336 | goto fail0; | |
1337 | ||
1338 | /* Time to get serious */ | |
1339 | i5000_get_mc_regs(mci); /* retrieve the hardware registers */ | |
1340 | ||
1341 | mci->mc_idx = 0; | |
1342 | mci->mtype_cap = MEM_FLAG_FB_DDR2; | |
1343 | mci->edac_ctl_cap = EDAC_FLAG_NONE; | |
1344 | mci->edac_cap = EDAC_FLAG_NONE; | |
1345 | mci->mod_name = "i5000_edac.c"; | |
1346 | mci->mod_ver = I5000_REVISION; | |
1347 | mci->ctl_name = i5000_devs[dev_idx].ctl_name; | |
c4192705 | 1348 | mci->dev_name = pci_name(pdev); |
eb60705a EW |
1349 | mci->ctl_page_to_phys = NULL; |
1350 | ||
1351 | /* Set the function pointer to an actual operation function */ | |
1352 | mci->edac_check = i5000_check_error; | |
1353 | ||
1354 | /* initialize the MC control structure 'csrows' table | |
1355 | * with the mapping and control information */ | |
1356 | if (i5000_init_csrows(mci)) { | |
1357 | debugf0("MC: Setting mci->edac_cap to EDAC_FLAG_NONE\n" | |
1358 | " because i5000_init_csrows() returned nonzero " | |
1359 | "value\n"); | |
1360 | mci->edac_cap = EDAC_FLAG_NONE; /* no csrows found */ | |
1361 | } else { | |
1362 | debugf1("MC: Enable error reporting now\n"); | |
1363 | i5000_enable_error_reporting(mci); | |
1364 | } | |
1365 | ||
1366 | /* add this new MC control structure to EDAC's list of MCs */ | |
1367 | if (edac_mc_add_mc(mci, pvt->node_id)) { | |
1368 | debugf0("MC: " __FILE__ | |
1369 | ": %s(): failed edac_mc_add_mc()\n", __func__); | |
1370 | /* FIXME: perhaps some code should go here that disables error | |
1371 | * reporting if we just enabled it | |
1372 | */ | |
1373 | goto fail1; | |
1374 | } | |
1375 | ||
1376 | i5000_clear_error(mci); | |
1377 | ||
1378 | return 0; | |
1379 | ||
1380 | /* Error exit unwinding stack */ | |
1381 | fail1: | |
1382 | ||
1383 | i5000_put_devices(mci); | |
1384 | ||
1385 | fail0: | |
1386 | edac_mc_free(mci); | |
1387 | return -ENODEV; | |
1388 | } | |
1389 | ||
1390 | /****************************************************************************** | |
1391 | * i5000_init_one constructor for one instance of device | |
1392 | * | |
1393 | * returns: | |
1394 | * negative on error | |
1395 | * count (>= 0) | |
1396 | */ | |
1397 | static int __devinit i5000_init_one(struct pci_dev *pdev, | |
1398 | const struct pci_device_id *id) | |
1399 | { | |
1400 | int rc; | |
1401 | ||
1402 | debugf0("MC: " __FILE__ ": %s()\n", __func__); | |
1403 | ||
1404 | /* wake up device */ | |
1405 | rc = pci_enable_device(pdev); | |
1406 | if (rc == -EIO) | |
1407 | return rc; | |
1408 | ||
1409 | /* now probe and enable the device */ | |
1410 | return i5000_probe1(pdev, id->driver_data); | |
1411 | } | |
1412 | ||
1413 | /************************************************************************** | |
1414 | * i5000_remove_one destructor for one instance of device | |
1415 | * | |
1416 | */ | |
1417 | static void __devexit i5000_remove_one(struct pci_dev *pdev) | |
1418 | { | |
1419 | struct mem_ctl_info *mci; | |
1420 | ||
1421 | debugf0(__FILE__ ": %s()\n", __func__); | |
1422 | ||
1423 | if ((mci = edac_mc_del_mc(&pdev->dev)) == NULL) | |
1424 | return; | |
1425 | ||
1426 | /* retrieve references to resources, and free those resources */ | |
1427 | i5000_put_devices(mci); | |
1428 | ||
1429 | edac_mc_free(mci); | |
1430 | } | |
1431 | ||
1432 | /************************************************************************** | |
1433 | * pci_device_id table for which devices we are looking for | |
1434 | * | |
1435 | * The "E500P" device is the first device supported. | |
1436 | */ | |
1437 | static const struct pci_device_id i5000_pci_tbl[] __devinitdata = { | |
1438 | {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I5000_DEV16), | |
1439 | .driver_data = I5000P}, | |
1440 | ||
1441 | {0,} /* 0 terminated list. */ | |
1442 | }; | |
1443 | ||
1444 | MODULE_DEVICE_TABLE(pci, i5000_pci_tbl); | |
1445 | ||
1446 | /************************************************************************** | |
1447 | * i5000_driver pci_driver structure for this module | |
1448 | * | |
1449 | */ | |
1450 | static struct pci_driver i5000_driver = { | |
1451 | .name = __stringify(KBUILD_BASENAME), | |
1452 | .probe = i5000_init_one, | |
1453 | .remove = __devexit_p(i5000_remove_one), | |
1454 | .id_table = i5000_pci_tbl, | |
1455 | }; | |
1456 | ||
1457 | /************************************************************************** | |
1458 | * i5000_init Module entry function | |
1459 | * Try to initialize this module for its devices | |
1460 | */ | |
1461 | static int __init i5000_init(void) | |
1462 | { | |
1463 | int pci_rc; | |
1464 | ||
1465 | debugf2("MC: " __FILE__ ": %s()\n", __func__); | |
1466 | ||
1467 | pci_rc = pci_register_driver(&i5000_driver); | |
1468 | ||
1469 | return (pci_rc < 0) ? pci_rc : 0; | |
1470 | } | |
1471 | ||
1472 | /************************************************************************** | |
1473 | * i5000_exit() Module exit function | |
1474 | * Unregister the driver | |
1475 | */ | |
1476 | static void __exit i5000_exit(void) | |
1477 | { | |
1478 | debugf2("MC: " __FILE__ ": %s()\n", __func__); | |
1479 | pci_unregister_driver(&i5000_driver); | |
1480 | } | |
1481 | ||
1482 | module_init(i5000_init); | |
1483 | module_exit(i5000_exit); | |
1484 | ||
1485 | MODULE_LICENSE("GPL"); | |
1486 | MODULE_AUTHOR | |
1487 | ("Linux Networx (http://lnxi.com) Doug Thompson <norsk5@xmission.com>"); | |
1488 | MODULE_DESCRIPTION("MC Driver for Intel I5000 memory controllers - " | |
1489 | I5000_REVISION); | |
c0d12172 DJ |
1490 | module_param(edac_op_state, int, 0444); |
1491 | MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting state: 0=Poll,1=NMI"); |