[mirror_ubuntu-bionic-kernel.git] / drivers / edac / i82860_edac.c

/*
 * Intel 82860 Memory Controller kernel module
 * (C) 2005 Red Hat (http://www.redhat.com)
 * This file may be distributed under the terms of the
 * GNU General Public License.
 *
 * Written by Ben Woodard <woodard@redhat.com>
 * shamelessly copied from and based upon the edac_i82875 driver
 * by Thayne Harbaugh of Linux Networx. (http://lnxi.com)
 */

#include <linux/module.h>
#include <linux/init.h>
#include <linux/pci.h>
#include <linux/pci_ids.h>
#include <linux/edac.h>
#include "edac_core.h"

#define  I82860_REVISION " Ver: 2.0.2"
#define EDAC_MOD_STR	"i82860_edac"

#define i82860_printk(level, fmt, arg...) \
	edac_printk(level, "i82860", fmt, ##arg)

#define i82860_mc_printk(mci, level, fmt, arg...) \
	edac_mc_chipset_printk(mci, level, "i82860", fmt, ##arg)

#ifndef PCI_DEVICE_ID_INTEL_82860_0
#define PCI_DEVICE_ID_INTEL_82860_0	0x2531
#endif				/* PCI_DEVICE_ID_INTEL_82860_0 */

#define I82860_MCHCFG 0x50
#define I82860_GBA 0x60
#define I82860_GBA_MASK 0x7FF
#define I82860_GBA_SHIFT 24
#define I82860_ERRSTS 0xC8
#define I82860_EAP 0xE4
#define I82860_DERRCTL_STS 0xE2

enum i82860_chips {
	I82860 = 0,
};

struct i82860_dev_info {
	const char *ctl_name;
};

struct i82860_error_info {
	u16 errsts;
	u32 eap;
	u16 derrsyn;
	u16 errsts2;
};

static const struct i82860_dev_info i82860_devs[] = {
	[I82860] = {
		.ctl_name = "i82860"},
};

static struct pci_dev *mci_pdev;	/* init dev: in case that AGP code
					 * has already registered driver
					 */
static struct edac_pci_ctl_info *i82860_pci;

static void i82860_get_error_info(struct mem_ctl_info *mci,
				struct i82860_error_info *info)
{
	struct pci_dev *pdev;

	pdev = to_pci_dev(mci->dev);

	/*
	 * This is a mess because there is no atomic way to read all the
	 * registers at once and the registers can transition from CE being
	 * overwritten by UE.
	 */
	pci_read_config_word(pdev, I82860_ERRSTS, &info->errsts);
	pci_read_config_dword(pdev, I82860_EAP, &info->eap);
	pci_read_config_word(pdev, I82860_DERRCTL_STS, &info->derrsyn);
	pci_read_config_word(pdev, I82860_ERRSTS, &info->errsts2);

	pci_write_bits16(pdev, I82860_ERRSTS, 0x0003, 0x0003);

	/*
	 * If the error is the same for both reads then the first set of reads
	 * is valid.  If there is a change then there is a CE no info and the
	 * second set of reads is valid and should be UE info.
	 */
	if (!(info->errsts2 & 0x0003))
		return;

	if ((info->errsts ^ info->errsts2) & 0x0003) {
		pci_read_config_dword(pdev, I82860_EAP, &info->eap);
		pci_read_config_word(pdev, I82860_DERRCTL_STS, &info->derrsyn);
	}
}

static int i82860_process_error_info(struct mem_ctl_info *mci,
				struct i82860_error_info *info,
				int handle_errors)
{
	int row;

	if (!(info->errsts2 & 0x0003))
		return 0;

	if (!handle_errors)
		return 1;

	if ((info->errsts ^ info->errsts2) & 0x0003) {
		edac_mc_handle_ce_no_info(mci, "UE overwrote CE");
		info->errsts = info->errsts2;
	}

	info->eap >>= PAGE_SHIFT;
	row = edac_mc_find_csrow_by_page(mci, info->eap);

	if (info->errsts & 0x0002)
		edac_mc_handle_ue(mci, info->eap, 0, row, "i82860 UE");
	else
		edac_mc_handle_ce(mci, info->eap, 0, info->derrsyn, row, 0,
				"i82860 UE");

	return 1;
}

static void i82860_check(struct mem_ctl_info *mci)
{
	struct i82860_error_info info;

	debugf1("MC%d: %s()\n", mci->mc_idx, __func__);
	i82860_get_error_info(mci, &info);
	i82860_process_error_info(mci, &info, 1);
}

static void i82860_init_csrows(struct mem_ctl_info *mci, struct pci_dev *pdev)
{
	unsigned long last_cumul_size;
	u16 mchcfg_ddim;	/* DRAM Data Integrity Mode 0=none, 2=edac */
	u16 value;
	u32 cumul_size;
	struct csrow_info *csrow;
	struct dimm_info *dimm;
	int index;

	pci_read_config_word(pdev, I82860_MCHCFG, &mchcfg_ddim);
	mchcfg_ddim = mchcfg_ddim & 0x180;
	last_cumul_size = 0;

	/* The group row boundary (GRA) reg values are boundary address
	 * for each DRAM row with a granularity of 16MB.  GRA regs are
	 * cumulative; therefore GRA15 will contain the total memory contained
	 * in all eight rows.
	 */
	for (index = 0; index < mci->nr_csrows; index++) {
		csrow = &mci->csrows[index];
		dimm = csrow->channels[0].dimm;

		pci_read_config_word(pdev, I82860_GBA + index * 2, &value);
		cumul_size = (value & I82860_GBA_MASK) <<
			(I82860_GBA_SHIFT - PAGE_SHIFT);
		debugf3("%s(): (%d) cumul_size 0x%x\n", __func__, index,
			cumul_size);

		if (cumul_size == last_cumul_size)
			continue;	/* not populated */

		csrow->first_page = last_cumul_size;
		csrow->last_page = cumul_size - 1;
		csrow->nr_pages = cumul_size - last_cumul_size;
		last_cumul_size = cumul_size;
		dimm->grain = 1 << 12;	/* I82860_EAP has 4KiB reolution */
		dimm->mtype = MEM_RMBS;
		dimm->dtype = DEV_UNKNOWN;
		dimm->edac_mode = mchcfg_ddim ? EDAC_SECDED : EDAC_NONE;
	}
}

static int i82860_probe1(struct pci_dev *pdev, int dev_idx)
{
	struct mem_ctl_info *mci;
	struct i82860_error_info discard;

	/* RDRAM has channels but these don't map onto the abstractions that
	   edac uses.
	   The device groups from the GRA registers seem to map reasonably
	   well onto the notion of a chip select row.
	   There are 16 GRA registers and since the name is associated with
	   the channel and the GRA registers map to physical devices so we are
	   going to make 1 channel for group.
	 */
	mci = edac_mc_alloc(0, 16, 1, 0);

	if (!mci)
		return -ENOMEM;

	debugf3("%s(): init mci\n", __func__);
	mci->dev = &pdev->dev;
	mci->mtype_cap = MEM_FLAG_DDR;
	mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_SECDED;
	/* I"m not sure about this but I think that all RDRAM is SECDED */
	mci->edac_cap = EDAC_FLAG_SECDED;
	mci->mod_name = EDAC_MOD_STR;
	mci->mod_ver = I82860_REVISION;
	mci->ctl_name = i82860_devs[dev_idx].ctl_name;
	mci->dev_name = pci_name(pdev);
	mci->edac_check = i82860_check;
	mci->ctl_page_to_phys = NULL;
	i82860_init_csrows(mci, pdev);
	i82860_get_error_info(mci, &discard);	/* clear counters */

	/* Here we assume that we will never see multiple instances of this
	 * type of memory controller.  The ID is therefore hardcoded to 0.
	 */
	if (edac_mc_add_mc(mci)) {
		debugf3("%s(): failed edac_mc_add_mc()\n", __func__);
		goto fail;
	}

	/* allocating generic PCI control info */
	i82860_pci = edac_pci_create_generic_ctl(&pdev->dev, EDAC_MOD_STR);
	if (!i82860_pci) {
		printk(KERN_WARNING
			"%s(): Unable to create PCI control\n",
			__func__);
		printk(KERN_WARNING
			"%s(): PCI error report via EDAC not setup\n",
			__func__);
	}

	/* get this far and it's successful */
	debugf3("%s(): success\n", __func__);

	return 0;

fail:
	edac_mc_free(mci);
	return -ENODEV;
}

/* returns count (>= 0), or negative on error */
static int __devinit i82860_init_one(struct pci_dev *pdev,
				const struct pci_device_id *ent)
{
	int rc;

	debugf0("%s()\n", __func__);
	i82860_printk(KERN_INFO, "i82860 init one\n");

	if (pci_enable_device(pdev) < 0)
		return -EIO;

	rc = i82860_probe1(pdev, ent->driver_data);

	if (rc == 0)
		mci_pdev = pci_dev_get(pdev);

	return rc;
}

static void __devexit i82860_remove_one(struct pci_dev *pdev)
{
	struct mem_ctl_info *mci;

	debugf0("%s()\n", __func__);

	if (i82860_pci)
		edac_pci_release_generic_ctl(i82860_pci);

	if ((mci = edac_mc_del_mc(&pdev->dev)) == NULL)
		return;

	edac_mc_free(mci);
}

static DEFINE_PCI_DEVICE_TABLE(i82860_pci_tbl) = {
	{
	 PCI_VEND_DEV(INTEL, 82860_0), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
	 I82860},
	{
	 0,
	 }			/* 0 terminated list. */
};

MODULE_DEVICE_TABLE(pci, i82860_pci_tbl);

static struct pci_driver i82860_driver = {
	.name = EDAC_MOD_STR,
	.probe = i82860_init_one,
	.remove = __devexit_p(i82860_remove_one),
	.id_table = i82860_pci_tbl,
};

static int __init i82860_init(void)
{
	int pci_rc;

	debugf3("%s()\n", __func__);

       /* Ensure that the OPSTATE is set correctly for POLL or NMI */
       opstate_init();

	if ((pci_rc = pci_register_driver(&i82860_driver)) < 0)
		goto fail0;

	if (!mci_pdev) {
		mci_pdev = pci_get_device(PCI_VENDOR_ID_INTEL,
					PCI_DEVICE_ID_INTEL_82860_0, NULL);

		if (mci_pdev == NULL) {
			debugf0("860 pci_get_device fail\n");
			pci_rc = -ENODEV;
			goto fail1;
		}

		pci_rc = i82860_init_one(mci_pdev, i82860_pci_tbl);

		if (pci_rc < 0) {
			debugf0("860 init fail\n");
			pci_rc = -ENODEV;
			goto fail1;
		}
	}

	return 0;

fail1:
	pci_unregister_driver(&i82860_driver);

fail0:
	if (mci_pdev != NULL)
		pci_dev_put(mci_pdev);

	return pci_rc;
}

static void __exit i82860_exit(void)
{
	debugf3("%s()\n", __func__);

	pci_unregister_driver(&i82860_driver);

	if (mci_pdev != NULL)
		pci_dev_put(mci_pdev);
}

module_init(i82860_init);
module_exit(i82860_exit);

MODULE_LICENSE("GPL");
MODULE_AUTHOR("Red Hat Inc. (http://www.redhat.com) "
		"Ben Woodard <woodard@redhat.com>");
MODULE_DESCRIPTION("ECC support for Intel 82860 memory hub controllers");

module_param(edac_op_state, int, 0444);
MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting state: 0=Poll,1=NMI");
Commit	Line	Data
0d88a10e AC	1	/*
	2	* Intel 82860 Memory Controller kernel module
	3	* (C) 2005 Red Hat (http://www.redhat.com)
	4	* This file may be distributed under the terms of the
	5	* GNU General Public License.
	6	*
	7	* Written by Ben Woodard <woodard@redhat.com>
	8	* shamelessly copied from and based upon the edac_i82875 driver
	9	* by Thayne Harbaugh of Linux Networx. (http://lnxi.com)
	10	*/
	11
0d88a10e AC	12	#include <linux/module.h>
	13	#include <linux/init.h>
	14	#include <linux/pci.h>
	15	#include <linux/pci_ids.h>
c3c52bce	16	#include <linux/edac.h>
20bcb7a8	17	#include "edac_core.h"
0d88a10e	18
152ba394	19	#define I82860_REVISION " Ver: 2.0.2"
929a40ec	20	#define EDAC_MOD_STR "i82860_edac"
37f04581	21
537fba28	22	#define i82860_printk(level, fmt, arg...) \
e7ecd891	23	edac_printk(level, "i82860", fmt, ##arg)
537fba28 DP	24
537fba28 DP	25	#define i82860_mc_printk(mci, level, fmt, arg...) \
e7ecd891	26	edac_mc_chipset_printk(mci, level, "i82860", fmt, ##arg)
537fba28	27
0d88a10e AC	28	#ifndef PCI_DEVICE_ID_INTEL_82860_0
	29	#define PCI_DEVICE_ID_INTEL_82860_0 0x2531
	30	#endif /* PCI_DEVICE_ID_INTEL_82860_0 */
	31
	32	#define I82860_MCHCFG 0x50
	33	#define I82860_GBA 0x60
	34	#define I82860_GBA_MASK 0x7FF
	35	#define I82860_GBA_SHIFT 24
	36	#define I82860_ERRSTS 0xC8
	37	#define I82860_EAP 0xE4
	38	#define I82860_DERRCTL_STS 0xE2
	39
	40	enum i82860_chips {
	41	I82860 = 0,
	42	};
	43
	44	struct i82860_dev_info {
	45	const char *ctl_name;
	46	};
	47
	48	struct i82860_error_info {
	49	u16 errsts;
	50	u32 eap;
	51	u16 derrsyn;
	52	u16 errsts2;
	53	};
	54
	55	static const struct i82860_dev_info i82860_devs[] = {
	56	[I82860] = {
052dfb45	57	.ctl_name = "i82860"},
0d88a10e AC	58	};
0d88a10e AC	59
f044091c	60	static struct pci_dev mci_pdev; / init dev: in case that AGP code
e7ecd891 DP	61	* has already registered driver
e7ecd891 DP	62	*/
456a2f95	63	static struct edac_pci_ctl_info *i82860_pci;
0d88a10e	64
e7ecd891	65	static void i82860_get_error_info(struct mem_ctl_info *mci,
052dfb45	66	struct i82860_error_info *info)
0d88a10e	67	{
37f04581 DT	68	struct pci_dev *pdev;
	69
	70	pdev = to_pci_dev(mci->dev);
	71
0d88a10e AC	72	/*
	73	* This is a mess because there is no atomic way to read all the
	74	* registers at once and the registers can transition from CE being
	75	* overwritten by UE.
	76	*/
37f04581 DT	77	pci_read_config_word(pdev, I82860_ERRSTS, &info->errsts);
	78	pci_read_config_dword(pdev, I82860_EAP, &info->eap);
	79	pci_read_config_word(pdev, I82860_DERRCTL_STS, &info->derrsyn);
	80	pci_read_config_word(pdev, I82860_ERRSTS, &info->errsts2);
0d88a10e	81
37f04581	82	pci_write_bits16(pdev, I82860_ERRSTS, 0x0003, 0x0003);
0d88a10e AC	83
	84	/*
	85	* If the error is the same for both reads then the first set of reads
	86	* is valid. If there is a change then there is a CE no info and the
	87	* second set of reads is valid and should be UE info.
	88	*/
	89	if (!(info->errsts2 & 0x0003))
	90	return;
e7ecd891	91
0d88a10e	92	if ((info->errsts ^ info->errsts2) & 0x0003) {
37f04581	93	pci_read_config_dword(pdev, I82860_EAP, &info->eap);
b4e8b372	94	pci_read_config_word(pdev, I82860_DERRCTL_STS, &info->derrsyn);
0d88a10e AC	95	}
	96	}
	97
e7ecd891	98	static int i82860_process_error_info(struct mem_ctl_info *mci,
052dfb45 DT	99	struct i82860_error_info *info,
052dfb45 DT	100	int handle_errors)
0d88a10e AC	101	{
	102	int row;
	103
	104	if (!(info->errsts2 & 0x0003))
	105	return 0;
	106
	107	if (!handle_errors)
	108	return 1;
	109
	110	if ((info->errsts ^ info->errsts2) & 0x0003) {
	111	edac_mc_handle_ce_no_info(mci, "UE overwrote CE");
	112	info->errsts = info->errsts2;
	113	}
	114
	115	info->eap >>= PAGE_SHIFT;
	116	row = edac_mc_find_csrow_by_page(mci, info->eap);
	117
	118	if (info->errsts & 0x0002)
	119	edac_mc_handle_ue(mci, info->eap, 0, row, "i82860 UE");
	120	else
e7ecd891	121	edac_mc_handle_ce(mci, info->eap, 0, info->derrsyn, row, 0,
052dfb45	122	"i82860 UE");
0d88a10e AC	123
	124	return 1;
	125	}
	126
	127	static void i82860_check(struct mem_ctl_info *mci)
	128	{
	129	struct i82860_error_info info;
	130
537fba28	131	debugf1("MC%d: %s()\n", mci->mc_idx, __func__);
0d88a10e AC	132	i82860_get_error_info(mci, &info);
	133	i82860_process_error_info(mci, &info, 1);
	134	}
	135
13189525	136	static void i82860_init_csrows(struct mem_ctl_info mci, struct pci_dev pdev)
0d88a10e	137	{
0d88a10e	138	unsigned long last_cumul_size;
b4e8b372	139	u16 mchcfg_ddim; /* DRAM Data Integrity Mode 0=none, 2=edac */
13189525 DT	140	u16 value;
	141	u32 cumul_size;
	142	struct csrow_info *csrow;
084a4fcc	143	struct dimm_info *dimm;
13189525 DT	144	int index;
	145
	146	pci_read_config_word(pdev, I82860_MCHCFG, &mchcfg_ddim);
	147	mchcfg_ddim = mchcfg_ddim & 0x180;
	148	last_cumul_size = 0;
	149
	150	/* The group row boundary (GRA) reg values are boundary address
	151	* for each DRAM row with a granularity of 16MB. GRA regs are
	152	* cumulative; therefore GRA15 will contain the total memory contained
	153	* in all eight rows.
	154	*/
	155	for (index = 0; index < mci->nr_csrows; index++) {
	156	csrow = &mci->csrows[index];
084a4fcc MCC	157	dimm = csrow->channels[0].dimm;
084a4fcc MCC	158
13189525 DT	159	pci_read_config_word(pdev, I82860_GBA + index * 2, &value);
13189525 DT	160	cumul_size = (value & I82860_GBA_MASK) <<
052dfb45	161	(I82860_GBA_SHIFT - PAGE_SHIFT);
13189525 DT	162	debugf3("%s(): (%d) cumul_size 0x%x\n", __func__, index,
13189525 DT	163	cumul_size);
0d88a10e	164
13189525 DT	165	if (cumul_size == last_cumul_size)
	166	continue; /* not populated */
	167
	168	csrow->first_page = last_cumul_size;
	169	csrow->last_page = cumul_size - 1;
	170	csrow->nr_pages = cumul_size - last_cumul_size;
	171	last_cumul_size = cumul_size;
084a4fcc MCC	172	dimm->grain = 1 << 12; /* I82860_EAP has 4KiB reolution */
	173	dimm->mtype = MEM_RMBS;
	174	dimm->dtype = DEV_UNKNOWN;
	175	dimm->edac_mode = mchcfg_ddim ? EDAC_SECDED : EDAC_NONE;
13189525 DT	176	}
	177	}
	178
	179	static int i82860_probe1(struct pci_dev *pdev, int dev_idx)
	180	{
	181	struct mem_ctl_info *mci;
	182	struct i82860_error_info discard;
0d88a10e AC	183
	184	/* RDRAM has channels but these don't map onto the abstractions that
	185	edac uses.
	186	The device groups from the GRA registers seem to map reasonably
	187	well onto the notion of a chip select row.
	188	There are 16 GRA registers and since the name is associated with
	189	the channel and the GRA registers map to physical devices so we are
	190	going to make 1 channel for group.
	191	*/
b8f6f975	192	mci = edac_mc_alloc(0, 16, 1, 0);
e7ecd891	193
0d88a10e AC	194	if (!mci)
	195	return -ENOMEM;
	196
537fba28	197	debugf3("%s(): init mci\n", __func__);
37f04581	198	mci->dev = &pdev->dev;
0d88a10e	199	mci->mtype_cap = MEM_FLAG_DDR;
0d88a10e AC	200	mci->edac_ctl_cap = EDAC_FLAG_NONE \| EDAC_FLAG_SECDED;
	201	/* I"m not sure about this but I think that all RDRAM is SECDED */
	202	mci->edac_cap = EDAC_FLAG_SECDED;
680cbbbb	203	mci->mod_name = EDAC_MOD_STR;
37f04581	204	mci->mod_ver = I82860_REVISION;
0d88a10e	205	mci->ctl_name = i82860_devs[dev_idx].ctl_name;
c4192705	206	mci->dev_name = pci_name(pdev);
0d88a10e AC	207	mci->edac_check = i82860_check;
0d88a10e AC	208	mci->ctl_page_to_phys = NULL;
13189525	209	i82860_init_csrows(mci, pdev);
b4e8b372	210	i82860_get_error_info(mci, &discard); /* clear counters */
0d88a10e	211
2d7bbb91 DT	212	/* Here we assume that we will never see multiple instances of this
	213	* type of memory controller. The ID is therefore hardcoded to 0.
	214	*/
b8f6f975	215	if (edac_mc_add_mc(mci)) {
537fba28	216	debugf3("%s(): failed edac_mc_add_mc()\n", __func__);
13189525	217	goto fail;
0d88a10e	218	}
e7ecd891	219
456a2f95 DJ	220	/* allocating generic PCI control info */
	221	i82860_pci = edac_pci_create_generic_ctl(&pdev->dev, EDAC_MOD_STR);
	222	if (!i82860_pci) {
	223	printk(KERN_WARNING
	224	"%s(): Unable to create PCI control\n",
	225	__func__);
	226	printk(KERN_WARNING
	227	"%s(): PCI error report via EDAC not setup\n",
	228	__func__);
	229	}
	230
13189525 DT	231	/* get this far and it's successful */
	232	debugf3("%s(): success\n", __func__);
	233
	234	return 0;
	235
052dfb45	236	fail:
13189525 DT	237	edac_mc_free(mci);
13189525 DT	238	return -ENODEV;
0d88a10e AC	239	}
	240
	241	/* returns count (>= 0), or negative on error */
	242	static int __devinit i82860_init_one(struct pci_dev *pdev,
052dfb45	243	const struct pci_device_id *ent)
0d88a10e AC	244	{
	245	int rc;
	246
537fba28	247	debugf0("%s()\n", __func__);
537fba28	248	i82860_printk(KERN_INFO, "i82860 init one\n");
e7ecd891 DP	249
e7ecd891 DP	250	if (pci_enable_device(pdev) < 0)
0d88a10e	251	return -EIO;
e7ecd891	252
0d88a10e	253	rc = i82860_probe1(pdev, ent->driver_data);
e7ecd891 DP	254
e7ecd891 DP	255	if (rc == 0)
0d88a10e	256	mci_pdev = pci_dev_get(pdev);
e7ecd891	257
0d88a10e AC	258	return rc;
	259	}
	260
	261	static void __devexit i82860_remove_one(struct pci_dev *pdev)
	262	{
	263	struct mem_ctl_info *mci;
	264
537fba28	265	debugf0("%s()\n", __func__);
0d88a10e	266
456a2f95 DJ	267	if (i82860_pci)
	268	edac_pci_release_generic_ctl(i82860_pci);
	269
37f04581	270	if ((mci = edac_mc_del_mc(&pdev->dev)) == NULL)
18dbc337 DP	271	return;
	272
	273	edac_mc_free(mci);
0d88a10e AC	274	}
0d88a10e AC	275
36c46f31	276	static DEFINE_PCI_DEVICE_TABLE(i82860_pci_tbl) = {
e7ecd891	277	{
b4e8b372 DJ	278	PCI_VEND_DEV(INTEL, 82860_0), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
b4e8b372 DJ	279	I82860},
e7ecd891	280	{
b4e8b372 DJ	281	0,
b4e8b372 DJ	282	} /* 0 terminated list. */
0d88a10e AC	283	};
	284
	285	MODULE_DEVICE_TABLE(pci, i82860_pci_tbl);
	286
	287	static struct pci_driver i82860_driver = {
680cbbbb	288	.name = EDAC_MOD_STR,
0d88a10e AC	289	.probe = i82860_init_one,
	290	.remove = __devexit_p(i82860_remove_one),
	291	.id_table = i82860_pci_tbl,
	292	};
	293
da9bb1d2	294	static int __init i82860_init(void)
0d88a10e AC	295	{
	296	int pci_rc;
	297
537fba28	298	debugf3("%s()\n", __func__);
e7ecd891	299
c3c52bce HM	300	/* Ensure that the OPSTATE is set correctly for POLL or NMI */
	301	opstate_init();
	302
0d88a10e	303	if ((pci_rc = pci_register_driver(&i82860_driver)) < 0)
e8a491b4	304	goto fail0;
0d88a10e AC	305
0d88a10e AC	306	if (!mci_pdev) {
0d88a10e	307	mci_pdev = pci_get_device(PCI_VENDOR_ID_INTEL,
052dfb45	308	PCI_DEVICE_ID_INTEL_82860_0, NULL);
e7ecd891	309
0d88a10e AC	310	if (mci_pdev == NULL) {
0d88a10e AC	311	debugf0("860 pci_get_device fail\n");
e8a491b4 DP	312	pci_rc = -ENODEV;
e8a491b4 DP	313	goto fail1;
0d88a10e	314	}
e7ecd891	315
0d88a10e	316	pci_rc = i82860_init_one(mci_pdev, i82860_pci_tbl);
e7ecd891	317
0d88a10e AC	318	if (pci_rc < 0) {
0d88a10e AC	319	debugf0("860 init fail\n");
e8a491b4 DP	320	pci_rc = -ENODEV;
e8a491b4 DP	321	goto fail1;
0d88a10e AC	322	}
0d88a10e AC	323	}
e7ecd891	324
0d88a10e	325	return 0;
e8a491b4	326
052dfb45	327	fail1:
e8a491b4 DP	328	pci_unregister_driver(&i82860_driver);
e8a491b4 DP	329
052dfb45	330	fail0:
e8a491b4 DP	331	if (mci_pdev != NULL)
	332	pci_dev_put(mci_pdev);
	333
	334	return pci_rc;
0d88a10e AC	335	}
	336
	337	static void __exit i82860_exit(void)
	338	{
537fba28	339	debugf3("%s()\n", __func__);
0d88a10e AC	340
0d88a10e AC	341	pci_unregister_driver(&i82860_driver);
e8a491b4 DP	342
e8a491b4 DP	343	if (mci_pdev != NULL)
0d88a10e	344	pci_dev_put(mci_pdev);
0d88a10e AC	345	}
	346
	347	module_init(i82860_init);
	348	module_exit(i82860_exit);
	349
	350	MODULE_LICENSE("GPL");
e7ecd891	351	MODULE_AUTHOR("Red Hat Inc. (http://www.redhat.com) "
052dfb45	352	"Ben Woodard <woodard@redhat.com>");
0d88a10e	353	MODULE_DESCRIPTION("ECC support for Intel 82860 memory hub controllers");
c3c52bce HM	354
	355	module_param(edac_op_state, int, 0444);
	356	MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting state: 0=Poll,1=NMI");