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1 | /* |
2 | * Radisys 82600 Embedded chipset Memory Controller kernel module | |
3 | * (C) 2005 EADS Astrium | |
4 | * This file may be distributed under the terms of the | |
5 | * GNU General Public License. | |
6 | * | |
7 | * Written by Tim Small <tim@buttersideup.com>, based on work by Thayne | |
8 | * Harbaugh, Dan Hollis <goemon at anime dot net> and others. | |
9 | * | |
10 | * $Id: edac_r82600.c,v 1.1.2.6 2005/10/05 00:43:44 dsp_llnl Exp $ | |
11 | * | |
12 | * Written with reference to 82600 High Integration Dual PCI System | |
13 | * Controller Data Book: | |
14 | * http://www.radisys.com/files/support_downloads/007-01277-0002.82600DataBook.pdf | |
15 | * references to this document given in [] | |
16 | */ | |
17 | ||
18 | #include <linux/config.h> | |
19 | #include <linux/module.h> | |
20 | #include <linux/init.h> | |
21 | ||
22 | #include <linux/pci.h> | |
23 | #include <linux/pci_ids.h> | |
24 | ||
25 | #include <linux/slab.h> | |
26 | ||
27 | #include "edac_mc.h" | |
28 | ||
29 | /* Radisys say "The 82600 integrates a main memory SDRAM controller that | |
30 | * supports up to four banks of memory. The four banks can support a mix of | |
31 | * sizes of 64 bit wide (72 bits with ECC) Synchronous DRAM (SDRAM) DIMMs, | |
32 | * each of which can be any size from 16MB to 512MB. Both registered (control | |
33 | * signals buffered) and unbuffered DIMM types are supported. Mixing of | |
34 | * registered and unbuffered DIMMs as well as mixing of ECC and non-ECC DIMMs | |
35 | * is not allowed. The 82600 SDRAM interface operates at the same frequency as | |
36 | * the CPU bus, 66MHz, 100MHz or 133MHz." | |
37 | */ | |
38 | ||
39 | #define R82600_NR_CSROWS 4 | |
40 | #define R82600_NR_CHANS 1 | |
41 | #define R82600_NR_DIMMS 4 | |
42 | ||
43 | #define R82600_BRIDGE_ID 0x8200 | |
44 | ||
45 | /* Radisys 82600 register addresses - device 0 function 0 - PCI bridge */ | |
46 | #define R82600_DRAMC 0x57 /* Various SDRAM related control bits | |
47 | * all bits are R/W | |
48 | * | |
49 | * 7 SDRAM ISA Hole Enable | |
50 | * 6 Flash Page Mode Enable | |
51 | * 5 ECC Enable: 1=ECC 0=noECC | |
52 | * 4 DRAM DIMM Type: 1= | |
53 | * 3 BIOS Alias Disable | |
54 | * 2 SDRAM BIOS Flash Write Enable | |
55 | * 1:0 SDRAM Refresh Rate: 00=Disabled | |
56 | * 01=7.8usec (256Mbit SDRAMs) | |
57 | * 10=15.6us 11=125usec | |
58 | */ | |
59 | ||
60 | #define R82600_SDRAMC 0x76 /* "SDRAM Control Register" | |
61 | * More SDRAM related control bits | |
62 | * all bits are R/W | |
63 | * | |
64 | * 15:8 Reserved. | |
65 | * | |
66 | * 7:5 Special SDRAM Mode Select | |
67 | * | |
68 | * 4 Force ECC | |
69 | * | |
70 | * 1=Drive ECC bits to 0 during | |
71 | * write cycles (i.e. ECC test mode) | |
72 | * | |
73 | * 0=Normal ECC functioning | |
74 | * | |
75 | * 3 Enhanced Paging Enable | |
76 | * | |
77 | * 2 CAS# Latency 0=3clks 1=2clks | |
78 | * | |
79 | * 1 RAS# to CAS# Delay 0=3 1=2 | |
80 | * | |
81 | * 0 RAS# Precharge 0=3 1=2 | |
82 | */ | |
83 | ||
84 | #define R82600_EAP 0x80 /* ECC Error Address Pointer Register | |
85 | * | |
86 | * 31 Disable Hardware Scrubbing (RW) | |
87 | * 0=Scrub on corrected read | |
88 | * 1=Don't scrub on corrected read | |
89 | * | |
90 | * 30:12 Error Address Pointer (RO) | |
91 | * Upper 19 bits of error address | |
92 | * | |
93 | * 11:4 Syndrome Bits (RO) | |
94 | * | |
95 | * 3 BSERR# on multibit error (RW) | |
96 | * 1=enable 0=disable | |
97 | * | |
98 | * 2 NMI on Single Bit Eror (RW) | |
99 | * 1=NMI triggered by SBE n.b. other | |
100 | * prerequeists | |
101 | * 0=NMI not triggered | |
102 | * | |
103 | * 1 MBE (R/WC) | |
104 | * read 1=MBE at EAP (see above) | |
105 | * read 0=no MBE, or SBE occurred first | |
106 | * write 1=Clear MBE status (must also | |
107 | * clear SBE) | |
108 | * write 0=NOP | |
109 | * | |
110 | * 1 SBE (R/WC) | |
111 | * read 1=SBE at EAP (see above) | |
112 | * read 0=no SBE, or MBE occurred first | |
113 | * write 1=Clear SBE status (must also | |
114 | * clear MBE) | |
115 | * write 0=NOP | |
116 | */ | |
117 | ||
118 | #define R82600_DRBA 0x60 /* + 0x60..0x63 SDRAM Row Boundry Address | |
119 | * Registers | |
120 | * | |
121 | * 7:0 Address lines 30:24 - upper limit of | |
122 | * each row [p57] | |
123 | */ | |
124 | ||
125 | struct r82600_error_info { | |
126 | u32 eapr; | |
127 | }; | |
128 | ||
129 | ||
130 | static unsigned int disable_hardware_scrub = 0; | |
131 | ||
132 | ||
133 | static void r82600_get_error_info (struct mem_ctl_info *mci, | |
134 | struct r82600_error_info *info) | |
135 | { | |
136 | pci_read_config_dword(mci->pdev, R82600_EAP, &info->eapr); | |
137 | ||
138 | if (info->eapr & BIT(0)) | |
139 | /* Clear error to allow next error to be reported [p.62] */ | |
140 | pci_write_bits32(mci->pdev, R82600_EAP, | |
141 | ((u32) BIT(0) & (u32) BIT(1)), | |
142 | ((u32) BIT(0) & (u32) BIT(1))); | |
143 | ||
144 | if (info->eapr & BIT(1)) | |
145 | /* Clear error to allow next error to be reported [p.62] */ | |
146 | pci_write_bits32(mci->pdev, R82600_EAP, | |
147 | ((u32) BIT(0) & (u32) BIT(1)), | |
148 | ((u32) BIT(0) & (u32) BIT(1))); | |
149 | } | |
150 | ||
151 | ||
152 | static int r82600_process_error_info (struct mem_ctl_info *mci, | |
153 | struct r82600_error_info *info, int handle_errors) | |
154 | { | |
155 | int error_found; | |
156 | u32 eapaddr, page; | |
157 | u32 syndrome; | |
158 | ||
159 | error_found = 0; | |
160 | ||
161 | /* bits 30:12 store the upper 19 bits of the 32 bit error address */ | |
162 | eapaddr = ((info->eapr >> 12) & 0x7FFF) << 13; | |
163 | /* Syndrome in bits 11:4 [p.62] */ | |
164 | syndrome = (info->eapr >> 4) & 0xFF; | |
165 | ||
166 | /* the R82600 reports at less than page * | |
167 | * granularity (upper 19 bits only) */ | |
168 | page = eapaddr >> PAGE_SHIFT; | |
169 | ||
170 | if (info->eapr & BIT(0)) { /* CE? */ | |
171 | error_found = 1; | |
172 | ||
173 | if (handle_errors) | |
174 | edac_mc_handle_ce( | |
175 | mci, page, 0, /* not avail */ | |
176 | syndrome, | |
177 | edac_mc_find_csrow_by_page(mci, page), | |
178 | 0, /* channel */ | |
179 | mci->ctl_name); | |
180 | } | |
181 | ||
182 | if (info->eapr & BIT(1)) { /* UE? */ | |
183 | error_found = 1; | |
184 | ||
185 | if (handle_errors) | |
186 | /* 82600 doesn't give enough info */ | |
187 | edac_mc_handle_ue(mci, page, 0, | |
188 | edac_mc_find_csrow_by_page(mci, page), | |
189 | mci->ctl_name); | |
190 | } | |
191 | ||
192 | return error_found; | |
193 | } | |
194 | ||
195 | static void r82600_check(struct mem_ctl_info *mci) | |
196 | { | |
197 | struct r82600_error_info info; | |
198 | ||
199 | debugf1("MC%d: " __FILE__ ": %s()\n", mci->mc_idx, __func__); | |
200 | r82600_get_error_info(mci, &info); | |
201 | r82600_process_error_info(mci, &info, 1); | |
202 | } | |
203 | ||
204 | static int r82600_probe1(struct pci_dev *pdev, int dev_idx) | |
205 | { | |
206 | int rc = -ENODEV; | |
207 | int index; | |
208 | struct mem_ctl_info *mci = NULL; | |
209 | u8 dramcr; | |
210 | u32 ecc_on; | |
211 | u32 reg_sdram; | |
212 | u32 eapr; | |
213 | u32 scrub_disabled; | |
214 | u32 sdram_refresh_rate; | |
215 | u32 row_high_limit_last = 0; | |
216 | u32 eap_init_bits; | |
217 | ||
218 | debugf0("MC: " __FILE__ ": %s()\n", __func__); | |
219 | ||
220 | ||
221 | pci_read_config_byte(pdev, R82600_DRAMC, &dramcr); | |
222 | pci_read_config_dword(pdev, R82600_EAP, &eapr); | |
223 | ||
224 | ecc_on = dramcr & BIT(5); | |
225 | reg_sdram = dramcr & BIT(4); | |
226 | scrub_disabled = eapr & BIT(31); | |
227 | sdram_refresh_rate = dramcr & (BIT(0) | BIT(1)); | |
228 | ||
229 | debugf2("MC: " __FILE__ ": %s(): sdram refresh rate = %#0x\n", | |
230 | __func__, sdram_refresh_rate); | |
231 | ||
232 | debugf2("MC: " __FILE__ ": %s(): DRAMC register = %#0x\n", __func__, | |
233 | dramcr); | |
234 | ||
235 | mci = edac_mc_alloc(0, R82600_NR_CSROWS, R82600_NR_CHANS); | |
236 | ||
237 | if (mci == NULL) { | |
238 | rc = -ENOMEM; | |
239 | goto fail; | |
240 | } | |
241 | ||
242 | debugf0("MC: " __FILE__ ": %s(): mci = %p\n", __func__, mci); | |
243 | ||
244 | mci->pdev = pdev; | |
245 | mci->mtype_cap = MEM_FLAG_RDDR | MEM_FLAG_DDR; | |
246 | ||
247 | mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_EC | EDAC_FLAG_SECDED; | |
248 | /* FIXME try to work out if the chip leads have been * | |
249 | * used for COM2 instead on this board? [MA6?] MAYBE: */ | |
250 | ||
251 | /* On the R82600, the pins for memory bits 72:65 - i.e. the * | |
252 | * EC bits are shared with the pins for COM2 (!), so if COM2 * | |
253 | * is enabled, we assume COM2 is wired up, and thus no EDAC * | |
254 | * is possible. */ | |
255 | mci->edac_cap = EDAC_FLAG_NONE | EDAC_FLAG_EC | EDAC_FLAG_SECDED; | |
256 | if (ecc_on) { | |
257 | if (scrub_disabled) | |
258 | debugf3("MC: " __FILE__ ": %s(): mci = %p - " | |
259 | "Scrubbing disabled! EAP: %#0x\n", __func__, | |
260 | mci, eapr); | |
261 | } else | |
262 | mci->edac_cap = EDAC_FLAG_NONE; | |
263 | ||
264 | mci->mod_name = BS_MOD_STR; | |
265 | mci->mod_ver = "$Revision: 1.1.2.6 $"; | |
266 | mci->ctl_name = "R82600"; | |
267 | mci->edac_check = r82600_check; | |
268 | mci->ctl_page_to_phys = NULL; | |
269 | ||
270 | for (index = 0; index < mci->nr_csrows; index++) { | |
271 | struct csrow_info *csrow = &mci->csrows[index]; | |
272 | u8 drbar; /* sDram Row Boundry Address Register */ | |
273 | u32 row_high_limit; | |
274 | u32 row_base; | |
275 | ||
276 | /* find the DRAM Chip Select Base address and mask */ | |
277 | pci_read_config_byte(mci->pdev, R82600_DRBA + index, &drbar); | |
278 | ||
279 | debugf1("MC%d: " __FILE__ ": %s() Row=%d DRBA = %#0x\n", | |
280 | mci->mc_idx, __func__, index, drbar); | |
281 | ||
282 | row_high_limit = ((u32) drbar << 24); | |
283 | /* row_high_limit = ((u32)drbar << 24) | 0xffffffUL; */ | |
284 | ||
285 | debugf1("MC%d: " __FILE__ ": %s() Row=%d, " | |
286 | "Boundry Address=%#0x, Last = %#0x \n", | |
287 | mci->mc_idx, __func__, index, row_high_limit, | |
288 | row_high_limit_last); | |
289 | ||
290 | /* Empty row [p.57] */ | |
291 | if (row_high_limit == row_high_limit_last) | |
292 | continue; | |
293 | ||
294 | row_base = row_high_limit_last; | |
295 | ||
296 | csrow->first_page = row_base >> PAGE_SHIFT; | |
297 | csrow->last_page = (row_high_limit >> PAGE_SHIFT) - 1; | |
298 | csrow->nr_pages = csrow->last_page - csrow->first_page + 1; | |
299 | /* Error address is top 19 bits - so granularity is * | |
300 | * 14 bits */ | |
301 | csrow->grain = 1 << 14; | |
302 | csrow->mtype = reg_sdram ? MEM_RDDR : MEM_DDR; | |
303 | /* FIXME - check that this is unknowable with this chipset */ | |
304 | csrow->dtype = DEV_UNKNOWN; | |
305 | ||
306 | /* Mode is global on 82600 */ | |
307 | csrow->edac_mode = ecc_on ? EDAC_SECDED : EDAC_NONE; | |
308 | row_high_limit_last = row_high_limit; | |
309 | } | |
310 | ||
311 | /* clear counters */ | |
312 | /* FIXME should we? */ | |
313 | ||
314 | if (edac_mc_add_mc(mci)) { | |
315 | debugf3("MC: " __FILE__ | |
316 | ": %s(): failed edac_mc_add_mc()\n", __func__); | |
317 | goto fail; | |
318 | } | |
319 | ||
320 | /* get this far and it's successful */ | |
321 | ||
322 | /* Clear error flags to allow next error to be reported [p.62] */ | |
323 | /* Test systems seem to always have the UE flag raised on boot */ | |
324 | ||
325 | eap_init_bits = BIT(0) & BIT(1); | |
326 | if (disable_hardware_scrub) { | |
327 | eap_init_bits |= BIT(31); | |
328 | debugf3("MC: " __FILE__ ": %s(): Disabling Hardware Scrub " | |
329 | "(scrub on error)\n", __func__); | |
330 | } | |
331 | ||
332 | pci_write_bits32(mci->pdev, R82600_EAP, eap_init_bits, | |
333 | eap_init_bits); | |
334 | ||
335 | debugf3("MC: " __FILE__ ": %s(): success\n", __func__); | |
336 | return 0; | |
337 | ||
338 | fail: | |
339 | if (mci) | |
340 | edac_mc_free(mci); | |
341 | ||
342 | return rc; | |
343 | } | |
344 | ||
345 | /* returns count (>= 0), or negative on error */ | |
346 | static int __devinit r82600_init_one(struct pci_dev *pdev, | |
347 | const struct pci_device_id *ent) | |
348 | { | |
349 | debugf0("MC: " __FILE__ ": %s()\n", __func__); | |
350 | ||
351 | /* don't need to call pci_device_enable() */ | |
352 | return r82600_probe1(pdev, ent->driver_data); | |
353 | } | |
354 | ||
355 | ||
356 | static void __devexit r82600_remove_one(struct pci_dev *pdev) | |
357 | { | |
358 | struct mem_ctl_info *mci; | |
359 | ||
360 | debugf0(__FILE__ ": %s()\n", __func__); | |
361 | ||
362 | if (((mci = edac_mc_find_mci_by_pdev(pdev)) != NULL) && | |
363 | !edac_mc_del_mc(mci)) | |
364 | edac_mc_free(mci); | |
365 | } | |
366 | ||
367 | ||
368 | static const struct pci_device_id r82600_pci_tbl[] __devinitdata = { | |
369 | {PCI_DEVICE(PCI_VENDOR_ID_RADISYS, R82600_BRIDGE_ID)}, | |
370 | {0,} /* 0 terminated list. */ | |
371 | }; | |
372 | ||
373 | MODULE_DEVICE_TABLE(pci, r82600_pci_tbl); | |
374 | ||
375 | ||
376 | static struct pci_driver r82600_driver = { | |
377 | .name = BS_MOD_STR, | |
378 | .probe = r82600_init_one, | |
379 | .remove = __devexit_p(r82600_remove_one), | |
380 | .id_table = r82600_pci_tbl, | |
381 | }; | |
382 | ||
383 | ||
384 | int __init r82600_init(void) | |
385 | { | |
386 | return pci_register_driver(&r82600_driver); | |
387 | } | |
388 | ||
389 | ||
390 | static void __exit r82600_exit(void) | |
391 | { | |
392 | pci_unregister_driver(&r82600_driver); | |
393 | } | |
394 | ||
395 | ||
396 | module_init(r82600_init); | |
397 | module_exit(r82600_exit); | |
398 | ||
399 | ||
400 | MODULE_LICENSE("GPL"); | |
401 | MODULE_AUTHOR("Tim Small <tim@buttersideup.com> - WPAD Ltd. " | |
402 | "on behalf of EADS Astrium"); | |
403 | MODULE_DESCRIPTION("MC support for Radisys 82600 memory controllers"); | |
404 | ||
405 | module_param(disable_hardware_scrub, bool, 0644); | |
406 | MODULE_PARM_DESC(disable_hardware_scrub, | |
407 | "If set, disable the chipset's automatic scrub for CEs"); |