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Commit | Line | Data |
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9e60fdcf | 1 | /* |
1e191695 | 2 | * PCA953x 4/8/16/24/40 bit I/O ports |
9e60fdcf | 3 | * |
4 | * Copyright (C) 2005 Ben Gardner <bgardner@wabtec.com> | |
5 | * Copyright (C) 2007 Marvell International Ltd. | |
6 | * | |
7 | * Derived from drivers/i2c/chips/pca9539.c | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License as published by | |
11 | * the Free Software Foundation; version 2 of the License. | |
12 | */ | |
13 | ||
14 | #include <linux/module.h> | |
15 | #include <linux/init.h> | |
d120c17f | 16 | #include <linux/gpio.h> |
89ea8bbe | 17 | #include <linux/interrupt.h> |
9e60fdcf | 18 | #include <linux/i2c.h> |
5877457a | 19 | #include <linux/platform_data/pca953x.h> |
5a0e3ad6 | 20 | #include <linux/slab.h> |
9b8e3ec3 | 21 | #include <asm/unaligned.h> |
1965d303 | 22 | #include <linux/of_platform.h> |
f32517bf | 23 | #include <linux/acpi.h> |
e23efa31 | 24 | #include <linux/regulator/consumer.h> |
9e60fdcf | 25 | |
33226ffd HZ |
26 | #define PCA953X_INPUT 0 |
27 | #define PCA953X_OUTPUT 1 | |
28 | #define PCA953X_INVERT 2 | |
29 | #define PCA953X_DIRECTION 3 | |
30 | ||
ae79c190 AS |
31 | #define REG_ADDR_AI 0x80 |
32 | ||
33226ffd HZ |
33 | #define PCA957X_IN 0 |
34 | #define PCA957X_INVRT 1 | |
35 | #define PCA957X_BKEN 2 | |
36 | #define PCA957X_PUPD 3 | |
37 | #define PCA957X_CFG 4 | |
38 | #define PCA957X_OUT 5 | |
39 | #define PCA957X_MSK 6 | |
40 | #define PCA957X_INTS 7 | |
41 | ||
44896bea YL |
42 | #define PCAL953X_IN_LATCH 34 |
43 | #define PCAL953X_INT_MASK 37 | |
44 | #define PCAL953X_INT_STAT 38 | |
45 | ||
33226ffd HZ |
46 | #define PCA_GPIO_MASK 0x00FF |
47 | #define PCA_INT 0x0100 | |
8c7a92da | 48 | #define PCA_PCAL 0x0200 |
33226ffd HZ |
49 | #define PCA953X_TYPE 0x1000 |
50 | #define PCA957X_TYPE 0x2000 | |
c6664149 AS |
51 | #define PCA_TYPE_MASK 0xF000 |
52 | ||
53 | #define PCA_CHIP_TYPE(x) ((x) & PCA_TYPE_MASK) | |
89ea8bbe | 54 | |
3760f736 | 55 | static const struct i2c_device_id pca953x_id[] = { |
89f5df01 | 56 | { "pca9505", 40 | PCA953X_TYPE | PCA_INT, }, |
33226ffd HZ |
57 | { "pca9534", 8 | PCA953X_TYPE | PCA_INT, }, |
58 | { "pca9535", 16 | PCA953X_TYPE | PCA_INT, }, | |
59 | { "pca9536", 4 | PCA953X_TYPE, }, | |
60 | { "pca9537", 4 | PCA953X_TYPE | PCA_INT, }, | |
61 | { "pca9538", 8 | PCA953X_TYPE | PCA_INT, }, | |
62 | { "pca9539", 16 | PCA953X_TYPE | PCA_INT, }, | |
63 | { "pca9554", 8 | PCA953X_TYPE | PCA_INT, }, | |
64 | { "pca9555", 16 | PCA953X_TYPE | PCA_INT, }, | |
65 | { "pca9556", 8 | PCA953X_TYPE, }, | |
66 | { "pca9557", 8 | PCA953X_TYPE, }, | |
67 | { "pca9574", 8 | PCA957X_TYPE | PCA_INT, }, | |
68 | { "pca9575", 16 | PCA957X_TYPE | PCA_INT, }, | |
eb32b5aa | 69 | { "pca9698", 40 | PCA953X_TYPE, }, |
33226ffd | 70 | |
747e42a1 AS |
71 | { "pcal9555a", 16 | PCA953X_TYPE | PCA_INT | PCA_PCAL, }, |
72 | ||
33226ffd HZ |
73 | { "max7310", 8 | PCA953X_TYPE, }, |
74 | { "max7312", 16 | PCA953X_TYPE | PCA_INT, }, | |
75 | { "max7313", 16 | PCA953X_TYPE | PCA_INT, }, | |
76 | { "max7315", 8 | PCA953X_TYPE | PCA_INT, }, | |
1208c935 | 77 | { "max7318", 16 | PCA953X_TYPE | PCA_INT, }, |
33226ffd HZ |
78 | { "pca6107", 8 | PCA953X_TYPE | PCA_INT, }, |
79 | { "tca6408", 8 | PCA953X_TYPE | PCA_INT, }, | |
80 | { "tca6416", 16 | PCA953X_TYPE | PCA_INT, }, | |
ae79c190 | 81 | { "tca6424", 24 | PCA953X_TYPE | PCA_INT, }, |
2db8aba8 | 82 | { "tca9539", 16 | PCA953X_TYPE | PCA_INT, }, |
e73760a6 | 83 | { "xra1202", 8 | PCA953X_TYPE }, |
3760f736 | 84 | { } |
f5e8ff48 | 85 | }; |
3760f736 | 86 | MODULE_DEVICE_TABLE(i2c, pca953x_id); |
9e60fdcf | 87 | |
f32517bf | 88 | static const struct acpi_device_id pca953x_acpi_ids[] = { |
44896bea | 89 | { "INT3491", 16 | PCA953X_TYPE | PCA_INT | PCA_PCAL, }, |
f32517bf AS |
90 | { } |
91 | }; | |
92 | MODULE_DEVICE_TABLE(acpi, pca953x_acpi_ids); | |
93 | ||
f5f0b7aa GC |
94 | #define MAX_BANK 5 |
95 | #define BANK_SZ 8 | |
96 | ||
a246b819 | 97 | #define NBANK(chip) DIV_ROUND_UP(chip->gpio_chip.ngpio, BANK_SZ) |
f5f0b7aa | 98 | |
53661f3b BG |
99 | struct pca953x_reg_config { |
100 | int direction; | |
101 | int output; | |
102 | int input; | |
103 | }; | |
104 | ||
105 | static const struct pca953x_reg_config pca953x_regs = { | |
106 | .direction = PCA953X_DIRECTION, | |
107 | .output = PCA953X_OUTPUT, | |
108 | .input = PCA953X_INPUT, | |
109 | }; | |
110 | ||
111 | static const struct pca953x_reg_config pca957x_regs = { | |
112 | .direction = PCA957X_CFG, | |
113 | .output = PCA957X_OUT, | |
114 | .input = PCA957X_IN, | |
115 | }; | |
116 | ||
f3dc3630 | 117 | struct pca953x_chip { |
9e60fdcf | 118 | unsigned gpio_start; |
f5f0b7aa GC |
119 | u8 reg_output[MAX_BANK]; |
120 | u8 reg_direction[MAX_BANK]; | |
6e20fb18 | 121 | struct mutex i2c_lock; |
9e60fdcf | 122 | |
89ea8bbe MZ |
123 | #ifdef CONFIG_GPIO_PCA953X_IRQ |
124 | struct mutex irq_lock; | |
f5f0b7aa GC |
125 | u8 irq_mask[MAX_BANK]; |
126 | u8 irq_stat[MAX_BANK]; | |
127 | u8 irq_trig_raise[MAX_BANK]; | |
128 | u8 irq_trig_fall[MAX_BANK]; | |
89ea8bbe MZ |
129 | #endif |
130 | ||
9e60fdcf | 131 | struct i2c_client *client; |
132 | struct gpio_chip gpio_chip; | |
62154991 | 133 | const char *const *names; |
c6664149 | 134 | unsigned long driver_data; |
e23efa31 | 135 | struct regulator *regulator; |
53661f3b BG |
136 | |
137 | const struct pca953x_reg_config *regs; | |
7acc66e3 BG |
138 | |
139 | int (*write_regs)(struct pca953x_chip *, int, u8 *); | |
c6e3cf01 | 140 | int (*read_regs)(struct pca953x_chip *, int, u8 *); |
9e60fdcf | 141 | }; |
142 | ||
f5f0b7aa GC |
143 | static int pca953x_read_single(struct pca953x_chip *chip, int reg, u32 *val, |
144 | int off) | |
145 | { | |
146 | int ret; | |
147 | int bank_shift = fls((chip->gpio_chip.ngpio - 1) / BANK_SZ); | |
148 | int offset = off / BANK_SZ; | |
149 | ||
150 | ret = i2c_smbus_read_byte_data(chip->client, | |
151 | (reg << bank_shift) + offset); | |
152 | *val = ret; | |
153 | ||
154 | if (ret < 0) { | |
155 | dev_err(&chip->client->dev, "failed reading register\n"); | |
156 | return ret; | |
157 | } | |
158 | ||
159 | return 0; | |
160 | } | |
161 | ||
162 | static int pca953x_write_single(struct pca953x_chip *chip, int reg, u32 val, | |
163 | int off) | |
164 | { | |
8c7a92da | 165 | int ret; |
f5f0b7aa GC |
166 | int bank_shift = fls((chip->gpio_chip.ngpio - 1) / BANK_SZ); |
167 | int offset = off / BANK_SZ; | |
168 | ||
169 | ret = i2c_smbus_write_byte_data(chip->client, | |
170 | (reg << bank_shift) + offset, val); | |
171 | ||
172 | if (ret < 0) { | |
173 | dev_err(&chip->client->dev, "failed writing register\n"); | |
174 | return ret; | |
175 | } | |
176 | ||
177 | return 0; | |
178 | } | |
179 | ||
7acc66e3 | 180 | static int pca953x_write_regs_8(struct pca953x_chip *chip, int reg, u8 *val) |
9e60fdcf | 181 | { |
7acc66e3 BG |
182 | return i2c_smbus_write_byte_data(chip->client, reg, *val); |
183 | } | |
f5e8ff48 | 184 | |
7acc66e3 BG |
185 | static int pca953x_write_regs_16(struct pca953x_chip *chip, int reg, u8 *val) |
186 | { | |
187 | __le16 word = cpu_to_le16(get_unaligned((u16 *)val)); | |
c4d1cbd7 | 188 | |
7acc66e3 BG |
189 | return i2c_smbus_write_word_data(chip->client, |
190 | reg << 1, (__force u16)word); | |
191 | } | |
192 | ||
193 | static int pca957x_write_regs_16(struct pca953x_chip *chip, int reg, u8 *val) | |
194 | { | |
195 | int ret; | |
196 | ||
197 | ret = i2c_smbus_write_byte_data(chip->client, reg << 1, val[0]); | |
198 | if (ret < 0) | |
199 | return ret; | |
200 | ||
201 | return i2c_smbus_write_byte_data(chip->client, (reg << 1) + 1, val[1]); | |
202 | } | |
f5e8ff48 | 203 | |
7acc66e3 BG |
204 | static int pca953x_write_regs_24(struct pca953x_chip *chip, int reg, u8 *val) |
205 | { | |
206 | int bank_shift = fls((chip->gpio_chip.ngpio - 1) / BANK_SZ); | |
207 | ||
208 | return i2c_smbus_write_i2c_block_data(chip->client, | |
209 | (reg << bank_shift) | REG_ADDR_AI, | |
210 | NBANK(chip), val); | |
211 | } | |
212 | ||
213 | static int pca953x_write_regs(struct pca953x_chip *chip, int reg, u8 *val) | |
214 | { | |
215 | int ret = 0; | |
216 | ||
217 | ret = chip->write_regs(chip, reg, val); | |
f5e8ff48 GL |
218 | if (ret < 0) { |
219 | dev_err(&chip->client->dev, "failed writing register\n"); | |
ab5dc372 | 220 | return ret; |
f5e8ff48 GL |
221 | } |
222 | ||
223 | return 0; | |
9e60fdcf | 224 | } |
225 | ||
c6e3cf01 | 226 | static int pca953x_read_regs_8(struct pca953x_chip *chip, int reg, u8 *val) |
9e60fdcf | 227 | { |
228 | int ret; | |
229 | ||
c6e3cf01 BG |
230 | ret = i2c_smbus_read_byte_data(chip->client, reg); |
231 | *val = ret; | |
f5f0b7aa | 232 | |
c6e3cf01 BG |
233 | return ret; |
234 | } | |
235 | ||
236 | static int pca953x_read_regs_16(struct pca953x_chip *chip, int reg, u8 *val) | |
237 | { | |
238 | int ret; | |
239 | ||
240 | ret = i2c_smbus_read_word_data(chip->client, reg << 1); | |
241 | val[0] = (u16)ret & 0xFF; | |
242 | val[1] = (u16)ret >> 8; | |
243 | ||
244 | return ret; | |
245 | } | |
246 | ||
247 | static int pca953x_read_regs_24(struct pca953x_chip *chip, int reg, u8 *val) | |
248 | { | |
249 | int bank_shift = fls((chip->gpio_chip.ngpio - 1) / BANK_SZ); | |
250 | ||
251 | return i2c_smbus_read_i2c_block_data(chip->client, | |
252 | (reg << bank_shift) | REG_ADDR_AI, | |
253 | NBANK(chip), val); | |
254 | } | |
255 | ||
256 | static int pca953x_read_regs(struct pca953x_chip *chip, int reg, u8 *val) | |
257 | { | |
258 | int ret; | |
259 | ||
260 | ret = chip->read_regs(chip, reg, val); | |
9e60fdcf | 261 | if (ret < 0) { |
262 | dev_err(&chip->client->dev, "failed reading register\n"); | |
ab5dc372 | 263 | return ret; |
9e60fdcf | 264 | } |
265 | ||
9e60fdcf | 266 | return 0; |
267 | } | |
268 | ||
f3dc3630 | 269 | static int pca953x_gpio_direction_input(struct gpio_chip *gc, unsigned off) |
9e60fdcf | 270 | { |
468e67f6 | 271 | struct pca953x_chip *chip = gpiochip_get_data(gc); |
f5f0b7aa | 272 | u8 reg_val; |
53661f3b | 273 | int ret; |
9e60fdcf | 274 | |
6e20fb18 | 275 | mutex_lock(&chip->i2c_lock); |
f5f0b7aa | 276 | reg_val = chip->reg_direction[off / BANK_SZ] | (1u << (off % BANK_SZ)); |
33226ffd | 277 | |
53661f3b | 278 | ret = pca953x_write_single(chip, chip->regs->direction, reg_val, off); |
9e60fdcf | 279 | if (ret) |
6e20fb18 | 280 | goto exit; |
9e60fdcf | 281 | |
f5f0b7aa | 282 | chip->reg_direction[off / BANK_SZ] = reg_val; |
6e20fb18 RS |
283 | exit: |
284 | mutex_unlock(&chip->i2c_lock); | |
285 | return ret; | |
9e60fdcf | 286 | } |
287 | ||
f3dc3630 | 288 | static int pca953x_gpio_direction_output(struct gpio_chip *gc, |
9e60fdcf | 289 | unsigned off, int val) |
290 | { | |
468e67f6 | 291 | struct pca953x_chip *chip = gpiochip_get_data(gc); |
f5f0b7aa | 292 | u8 reg_val; |
53661f3b | 293 | int ret; |
9e60fdcf | 294 | |
6e20fb18 | 295 | mutex_lock(&chip->i2c_lock); |
9e60fdcf | 296 | /* set output level */ |
297 | if (val) | |
f5f0b7aa GC |
298 | reg_val = chip->reg_output[off / BANK_SZ] |
299 | | (1u << (off % BANK_SZ)); | |
9e60fdcf | 300 | else |
f5f0b7aa GC |
301 | reg_val = chip->reg_output[off / BANK_SZ] |
302 | & ~(1u << (off % BANK_SZ)); | |
9e60fdcf | 303 | |
53661f3b | 304 | ret = pca953x_write_single(chip, chip->regs->output, reg_val, off); |
9e60fdcf | 305 | if (ret) |
6e20fb18 | 306 | goto exit; |
9e60fdcf | 307 | |
f5f0b7aa | 308 | chip->reg_output[off / BANK_SZ] = reg_val; |
9e60fdcf | 309 | |
310 | /* then direction */ | |
f5f0b7aa | 311 | reg_val = chip->reg_direction[off / BANK_SZ] & ~(1u << (off % BANK_SZ)); |
53661f3b | 312 | ret = pca953x_write_single(chip, chip->regs->direction, reg_val, off); |
9e60fdcf | 313 | if (ret) |
6e20fb18 | 314 | goto exit; |
9e60fdcf | 315 | |
f5f0b7aa | 316 | chip->reg_direction[off / BANK_SZ] = reg_val; |
6e20fb18 RS |
317 | exit: |
318 | mutex_unlock(&chip->i2c_lock); | |
319 | return ret; | |
9e60fdcf | 320 | } |
321 | ||
f3dc3630 | 322 | static int pca953x_gpio_get_value(struct gpio_chip *gc, unsigned off) |
9e60fdcf | 323 | { |
468e67f6 | 324 | struct pca953x_chip *chip = gpiochip_get_data(gc); |
ae79c190 | 325 | u32 reg_val; |
53661f3b | 326 | int ret; |
9e60fdcf | 327 | |
6e20fb18 | 328 | mutex_lock(&chip->i2c_lock); |
53661f3b | 329 | ret = pca953x_read_single(chip, chip->regs->input, ®_val, off); |
6e20fb18 | 330 | mutex_unlock(&chip->i2c_lock); |
9e60fdcf | 331 | if (ret < 0) { |
332 | /* NOTE: diagnostic already emitted; that's all we should | |
333 | * do unless gpio_*_value_cansleep() calls become different | |
334 | * from their nonsleeping siblings (and report faults). | |
335 | */ | |
336 | return 0; | |
337 | } | |
338 | ||
40a625da | 339 | return (reg_val & (1u << (off % BANK_SZ))) ? 1 : 0; |
9e60fdcf | 340 | } |
341 | ||
f3dc3630 | 342 | static void pca953x_gpio_set_value(struct gpio_chip *gc, unsigned off, int val) |
9e60fdcf | 343 | { |
468e67f6 | 344 | struct pca953x_chip *chip = gpiochip_get_data(gc); |
f5f0b7aa | 345 | u8 reg_val; |
53661f3b | 346 | int ret; |
9e60fdcf | 347 | |
6e20fb18 | 348 | mutex_lock(&chip->i2c_lock); |
9e60fdcf | 349 | if (val) |
f5f0b7aa GC |
350 | reg_val = chip->reg_output[off / BANK_SZ] |
351 | | (1u << (off % BANK_SZ)); | |
9e60fdcf | 352 | else |
f5f0b7aa GC |
353 | reg_val = chip->reg_output[off / BANK_SZ] |
354 | & ~(1u << (off % BANK_SZ)); | |
9e60fdcf | 355 | |
53661f3b | 356 | ret = pca953x_write_single(chip, chip->regs->output, reg_val, off); |
9e60fdcf | 357 | if (ret) |
6e20fb18 | 358 | goto exit; |
9e60fdcf | 359 | |
f5f0b7aa | 360 | chip->reg_output[off / BANK_SZ] = reg_val; |
6e20fb18 RS |
361 | exit: |
362 | mutex_unlock(&chip->i2c_lock); | |
9e60fdcf | 363 | } |
364 | ||
b4818afe | 365 | static void pca953x_gpio_set_multiple(struct gpio_chip *gc, |
ea3d579d | 366 | unsigned long *mask, unsigned long *bits) |
b4818afe | 367 | { |
468e67f6 | 368 | struct pca953x_chip *chip = gpiochip_get_data(gc); |
ea3d579d BG |
369 | unsigned int bank_mask, bank_val; |
370 | int bank_shift, bank; | |
b4818afe | 371 | u8 reg_val[MAX_BANK]; |
53661f3b | 372 | int ret; |
ea3d579d BG |
373 | |
374 | bank_shift = fls((chip->gpio_chip.ngpio - 1) / BANK_SZ); | |
b4818afe | 375 | |
b4818afe | 376 | mutex_lock(&chip->i2c_lock); |
386377b5 | 377 | memcpy(reg_val, chip->reg_output, NBANK(chip)); |
ea3d579d BG |
378 | for (bank = 0; bank < NBANK(chip); bank++) { |
379 | bank_mask = mask[bank / sizeof(*mask)] >> | |
380 | ((bank % sizeof(*mask)) * 8); | |
381 | if (bank_mask) { | |
382 | bank_val = bits[bank / sizeof(*bits)] >> | |
383 | ((bank % sizeof(*bits)) * 8); | |
53f8d322 | 384 | bank_val &= bank_mask; |
ea3d579d | 385 | reg_val[bank] = (reg_val[bank] & ~bank_mask) | bank_val; |
b4818afe PR |
386 | } |
387 | } | |
ea3d579d | 388 | |
53661f3b BG |
389 | ret = i2c_smbus_write_i2c_block_data(chip->client, |
390 | chip->regs->output << bank_shift, | |
391 | NBANK(chip), reg_val); | |
b4818afe PR |
392 | if (ret) |
393 | goto exit; | |
394 | ||
395 | memcpy(chip->reg_output, reg_val, NBANK(chip)); | |
396 | exit: | |
397 | mutex_unlock(&chip->i2c_lock); | |
398 | } | |
399 | ||
f5e8ff48 | 400 | static void pca953x_setup_gpio(struct pca953x_chip *chip, int gpios) |
9e60fdcf | 401 | { |
402 | struct gpio_chip *gc; | |
403 | ||
404 | gc = &chip->gpio_chip; | |
405 | ||
f3dc3630 GL |
406 | gc->direction_input = pca953x_gpio_direction_input; |
407 | gc->direction_output = pca953x_gpio_direction_output; | |
408 | gc->get = pca953x_gpio_get_value; | |
409 | gc->set = pca953x_gpio_set_value; | |
b4818afe | 410 | gc->set_multiple = pca953x_gpio_set_multiple; |
9fb1f39e | 411 | gc->can_sleep = true; |
9e60fdcf | 412 | |
413 | gc->base = chip->gpio_start; | |
f5e8ff48 GL |
414 | gc->ngpio = gpios; |
415 | gc->label = chip->client->name; | |
58383c78 | 416 | gc->parent = &chip->client->dev; |
d72cbed0 | 417 | gc->owner = THIS_MODULE; |
77906a54 | 418 | gc->names = chip->names; |
9e60fdcf | 419 | } |
420 | ||
89ea8bbe | 421 | #ifdef CONFIG_GPIO_PCA953X_IRQ |
6f5cfc0e | 422 | static void pca953x_irq_mask(struct irq_data *d) |
89ea8bbe | 423 | { |
7bcbce55 | 424 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); |
468e67f6 | 425 | struct pca953x_chip *chip = gpiochip_get_data(gc); |
89ea8bbe | 426 | |
f5f0b7aa | 427 | chip->irq_mask[d->hwirq / BANK_SZ] &= ~(1 << (d->hwirq % BANK_SZ)); |
89ea8bbe MZ |
428 | } |
429 | ||
6f5cfc0e | 430 | static void pca953x_irq_unmask(struct irq_data *d) |
89ea8bbe | 431 | { |
7bcbce55 | 432 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); |
468e67f6 | 433 | struct pca953x_chip *chip = gpiochip_get_data(gc); |
89ea8bbe | 434 | |
f5f0b7aa | 435 | chip->irq_mask[d->hwirq / BANK_SZ] |= 1 << (d->hwirq % BANK_SZ); |
89ea8bbe MZ |
436 | } |
437 | ||
6f5cfc0e | 438 | static void pca953x_irq_bus_lock(struct irq_data *d) |
89ea8bbe | 439 | { |
7bcbce55 | 440 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); |
468e67f6 | 441 | struct pca953x_chip *chip = gpiochip_get_data(gc); |
89ea8bbe MZ |
442 | |
443 | mutex_lock(&chip->irq_lock); | |
444 | } | |
445 | ||
6f5cfc0e | 446 | static void pca953x_irq_bus_sync_unlock(struct irq_data *d) |
89ea8bbe | 447 | { |
7bcbce55 | 448 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); |
468e67f6 | 449 | struct pca953x_chip *chip = gpiochip_get_data(gc); |
f5f0b7aa GC |
450 | u8 new_irqs; |
451 | int level, i; | |
44896bea YL |
452 | u8 invert_irq_mask[MAX_BANK]; |
453 | ||
454 | if (chip->driver_data & PCA_PCAL) { | |
455 | /* Enable latch on interrupt-enabled inputs */ | |
456 | pca953x_write_regs(chip, PCAL953X_IN_LATCH, chip->irq_mask); | |
457 | ||
458 | for (i = 0; i < NBANK(chip); i++) | |
459 | invert_irq_mask[i] = ~chip->irq_mask[i]; | |
460 | ||
461 | /* Unmask enabled interrupts */ | |
462 | pca953x_write_regs(chip, PCAL953X_INT_MASK, invert_irq_mask); | |
463 | } | |
a2cb9aeb MZ |
464 | |
465 | /* Look for any newly setup interrupt */ | |
f5f0b7aa GC |
466 | for (i = 0; i < NBANK(chip); i++) { |
467 | new_irqs = chip->irq_trig_fall[i] | chip->irq_trig_raise[i]; | |
468 | new_irqs &= ~chip->reg_direction[i]; | |
469 | ||
470 | while (new_irqs) { | |
471 | level = __ffs(new_irqs); | |
472 | pca953x_gpio_direction_input(&chip->gpio_chip, | |
473 | level + (BANK_SZ * i)); | |
474 | new_irqs &= ~(1 << level); | |
475 | } | |
a2cb9aeb | 476 | } |
89ea8bbe MZ |
477 | |
478 | mutex_unlock(&chip->irq_lock); | |
479 | } | |
480 | ||
6f5cfc0e | 481 | static int pca953x_irq_set_type(struct irq_data *d, unsigned int type) |
89ea8bbe | 482 | { |
7bcbce55 | 483 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); |
468e67f6 | 484 | struct pca953x_chip *chip = gpiochip_get_data(gc); |
f5f0b7aa GC |
485 | int bank_nb = d->hwirq / BANK_SZ; |
486 | u8 mask = 1 << (d->hwirq % BANK_SZ); | |
89ea8bbe MZ |
487 | |
488 | if (!(type & IRQ_TYPE_EDGE_BOTH)) { | |
489 | dev_err(&chip->client->dev, "irq %d: unsupported type %d\n", | |
6f5cfc0e | 490 | d->irq, type); |
89ea8bbe MZ |
491 | return -EINVAL; |
492 | } | |
493 | ||
494 | if (type & IRQ_TYPE_EDGE_FALLING) | |
f5f0b7aa | 495 | chip->irq_trig_fall[bank_nb] |= mask; |
89ea8bbe | 496 | else |
f5f0b7aa | 497 | chip->irq_trig_fall[bank_nb] &= ~mask; |
89ea8bbe MZ |
498 | |
499 | if (type & IRQ_TYPE_EDGE_RISING) | |
f5f0b7aa | 500 | chip->irq_trig_raise[bank_nb] |= mask; |
89ea8bbe | 501 | else |
f5f0b7aa | 502 | chip->irq_trig_raise[bank_nb] &= ~mask; |
89ea8bbe | 503 | |
a2cb9aeb | 504 | return 0; |
89ea8bbe MZ |
505 | } |
506 | ||
507 | static struct irq_chip pca953x_irq_chip = { | |
508 | .name = "pca953x", | |
6f5cfc0e LB |
509 | .irq_mask = pca953x_irq_mask, |
510 | .irq_unmask = pca953x_irq_unmask, | |
511 | .irq_bus_lock = pca953x_irq_bus_lock, | |
512 | .irq_bus_sync_unlock = pca953x_irq_bus_sync_unlock, | |
513 | .irq_set_type = pca953x_irq_set_type, | |
89ea8bbe MZ |
514 | }; |
515 | ||
b6ac1280 | 516 | static bool pca953x_irq_pending(struct pca953x_chip *chip, u8 *pending) |
89ea8bbe | 517 | { |
f5f0b7aa GC |
518 | u8 cur_stat[MAX_BANK]; |
519 | u8 old_stat[MAX_BANK]; | |
b6ac1280 JS |
520 | bool pending_seen = false; |
521 | bool trigger_seen = false; | |
522 | u8 trigger[MAX_BANK]; | |
53661f3b | 523 | int ret, i; |
33226ffd | 524 | |
44896bea YL |
525 | if (chip->driver_data & PCA_PCAL) { |
526 | /* Read the current interrupt status from the device */ | |
527 | ret = pca953x_read_regs(chip, PCAL953X_INT_STAT, trigger); | |
528 | if (ret) | |
529 | return false; | |
530 | ||
531 | /* Check latched inputs and clear interrupt status */ | |
532 | ret = pca953x_read_regs(chip, PCA953X_INPUT, cur_stat); | |
533 | if (ret) | |
534 | return false; | |
535 | ||
536 | for (i = 0; i < NBANK(chip); i++) { | |
537 | /* Apply filter for rising/falling edge selection */ | |
538 | pending[i] = (~cur_stat[i] & chip->irq_trig_fall[i]) | | |
539 | (cur_stat[i] & chip->irq_trig_raise[i]); | |
540 | pending[i] &= trigger[i]; | |
541 | if (pending[i]) | |
542 | pending_seen = true; | |
543 | } | |
544 | ||
545 | return pending_seen; | |
546 | } | |
547 | ||
53661f3b | 548 | ret = pca953x_read_regs(chip, chip->regs->input, cur_stat); |
89ea8bbe | 549 | if (ret) |
b6ac1280 | 550 | return false; |
89ea8bbe MZ |
551 | |
552 | /* Remove output pins from the equation */ | |
f5f0b7aa GC |
553 | for (i = 0; i < NBANK(chip); i++) |
554 | cur_stat[i] &= chip->reg_direction[i]; | |
89ea8bbe | 555 | |
f5f0b7aa | 556 | memcpy(old_stat, chip->irq_stat, NBANK(chip)); |
89ea8bbe | 557 | |
f5f0b7aa GC |
558 | for (i = 0; i < NBANK(chip); i++) { |
559 | trigger[i] = (cur_stat[i] ^ old_stat[i]) & chip->irq_mask[i]; | |
b6ac1280 JS |
560 | if (trigger[i]) |
561 | trigger_seen = true; | |
f5f0b7aa GC |
562 | } |
563 | ||
b6ac1280 JS |
564 | if (!trigger_seen) |
565 | return false; | |
89ea8bbe | 566 | |
f5f0b7aa | 567 | memcpy(chip->irq_stat, cur_stat, NBANK(chip)); |
89ea8bbe | 568 | |
f5f0b7aa GC |
569 | for (i = 0; i < NBANK(chip); i++) { |
570 | pending[i] = (old_stat[i] & chip->irq_trig_fall[i]) | | |
571 | (cur_stat[i] & chip->irq_trig_raise[i]); | |
572 | pending[i] &= trigger[i]; | |
b6ac1280 JS |
573 | if (pending[i]) |
574 | pending_seen = true; | |
f5f0b7aa | 575 | } |
89ea8bbe | 576 | |
b6ac1280 | 577 | return pending_seen; |
89ea8bbe MZ |
578 | } |
579 | ||
580 | static irqreturn_t pca953x_irq_handler(int irq, void *devid) | |
581 | { | |
582 | struct pca953x_chip *chip = devid; | |
f5f0b7aa GC |
583 | u8 pending[MAX_BANK]; |
584 | u8 level; | |
3275d072 | 585 | unsigned nhandled = 0; |
f5f0b7aa | 586 | int i; |
89ea8bbe | 587 | |
f5f0b7aa | 588 | if (!pca953x_irq_pending(chip, pending)) |
3275d072 | 589 | return IRQ_NONE; |
89ea8bbe | 590 | |
f5f0b7aa GC |
591 | for (i = 0; i < NBANK(chip); i++) { |
592 | while (pending[i]) { | |
593 | level = __ffs(pending[i]); | |
7bcbce55 | 594 | handle_nested_irq(irq_find_mapping(chip->gpio_chip.irqdomain, |
f5f0b7aa GC |
595 | level + (BANK_SZ * i))); |
596 | pending[i] &= ~(1 << level); | |
3275d072 | 597 | nhandled++; |
f5f0b7aa GC |
598 | } |
599 | } | |
89ea8bbe | 600 | |
3275d072 | 601 | return (nhandled > 0) ? IRQ_HANDLED : IRQ_NONE; |
89ea8bbe MZ |
602 | } |
603 | ||
604 | static int pca953x_irq_setup(struct pca953x_chip *chip, | |
c6dcf592 | 605 | int irq_base) |
89ea8bbe MZ |
606 | { |
607 | struct i2c_client *client = chip->client; | |
53661f3b | 608 | int ret, i; |
89ea8bbe | 609 | |
4bb93349 | 610 | if (client->irq && irq_base != -1 |
c6664149 | 611 | && (chip->driver_data & PCA_INT)) { |
53661f3b BG |
612 | ret = pca953x_read_regs(chip, |
613 | chip->regs->input, chip->irq_stat); | |
89ea8bbe | 614 | if (ret) |
b42748c9 | 615 | return ret; |
89ea8bbe MZ |
616 | |
617 | /* | |
618 | * There is no way to know which GPIO line generated the | |
619 | * interrupt. We have to rely on the previous read for | |
620 | * this purpose. | |
621 | */ | |
f5f0b7aa GC |
622 | for (i = 0; i < NBANK(chip); i++) |
623 | chip->irq_stat[i] &= chip->reg_direction[i]; | |
89ea8bbe MZ |
624 | mutex_init(&chip->irq_lock); |
625 | ||
b42748c9 LW |
626 | ret = devm_request_threaded_irq(&client->dev, |
627 | client->irq, | |
89ea8bbe MZ |
628 | NULL, |
629 | pca953x_irq_handler, | |
91329132 TS |
630 | IRQF_TRIGGER_LOW | IRQF_ONESHOT | |
631 | IRQF_SHARED, | |
89ea8bbe MZ |
632 | dev_name(&client->dev), chip); |
633 | if (ret) { | |
634 | dev_err(&client->dev, "failed to request irq %d\n", | |
635 | client->irq); | |
0e8f2fda | 636 | return ret; |
89ea8bbe MZ |
637 | } |
638 | ||
d245b3f9 LW |
639 | ret = gpiochip_irqchip_add_nested(&chip->gpio_chip, |
640 | &pca953x_irq_chip, | |
641 | irq_base, | |
642 | handle_simple_irq, | |
643 | IRQ_TYPE_NONE); | |
7bcbce55 LW |
644 | if (ret) { |
645 | dev_err(&client->dev, | |
646 | "could not connect irqchip to gpiochip\n"); | |
647 | return ret; | |
648 | } | |
fdd50409 | 649 | |
d245b3f9 LW |
650 | gpiochip_set_nested_irqchip(&chip->gpio_chip, |
651 | &pca953x_irq_chip, | |
652 | client->irq); | |
89ea8bbe MZ |
653 | } |
654 | ||
655 | return 0; | |
89ea8bbe MZ |
656 | } |
657 | ||
89ea8bbe MZ |
658 | #else /* CONFIG_GPIO_PCA953X_IRQ */ |
659 | static int pca953x_irq_setup(struct pca953x_chip *chip, | |
c6dcf592 | 660 | int irq_base) |
89ea8bbe MZ |
661 | { |
662 | struct i2c_client *client = chip->client; | |
89ea8bbe | 663 | |
c6664149 | 664 | if (irq_base != -1 && (chip->driver_data & PCA_INT)) |
89ea8bbe MZ |
665 | dev_warn(&client->dev, "interrupt support not compiled in\n"); |
666 | ||
667 | return 0; | |
668 | } | |
89ea8bbe MZ |
669 | #endif |
670 | ||
3836309d | 671 | static int device_pca953x_init(struct pca953x_chip *chip, u32 invert) |
33226ffd HZ |
672 | { |
673 | int ret; | |
f5f0b7aa | 674 | u8 val[MAX_BANK]; |
33226ffd | 675 | |
53661f3b BG |
676 | chip->regs = &pca953x_regs; |
677 | ||
678 | ret = pca953x_read_regs(chip, chip->regs->output, chip->reg_output); | |
33226ffd HZ |
679 | if (ret) |
680 | goto out; | |
681 | ||
53661f3b BG |
682 | ret = pca953x_read_regs(chip, chip->regs->direction, |
683 | chip->reg_direction); | |
33226ffd HZ |
684 | if (ret) |
685 | goto out; | |
686 | ||
687 | /* set platform specific polarity inversion */ | |
f5f0b7aa GC |
688 | if (invert) |
689 | memset(val, 0xFF, NBANK(chip)); | |
690 | else | |
691 | memset(val, 0, NBANK(chip)); | |
692 | ||
693 | ret = pca953x_write_regs(chip, PCA953X_INVERT, val); | |
33226ffd HZ |
694 | out: |
695 | return ret; | |
696 | } | |
697 | ||
3836309d | 698 | static int device_pca957x_init(struct pca953x_chip *chip, u32 invert) |
33226ffd HZ |
699 | { |
700 | int ret; | |
f5f0b7aa | 701 | u8 val[MAX_BANK]; |
33226ffd | 702 | |
53661f3b BG |
703 | chip->regs = &pca957x_regs; |
704 | ||
705 | ret = pca953x_read_regs(chip, chip->regs->output, chip->reg_output); | |
33226ffd HZ |
706 | if (ret) |
707 | goto out; | |
53661f3b BG |
708 | ret = pca953x_read_regs(chip, chip->regs->direction, |
709 | chip->reg_direction); | |
33226ffd HZ |
710 | if (ret) |
711 | goto out; | |
712 | ||
713 | /* set platform specific polarity inversion */ | |
f5f0b7aa GC |
714 | if (invert) |
715 | memset(val, 0xFF, NBANK(chip)); | |
716 | else | |
717 | memset(val, 0, NBANK(chip)); | |
c75a3772 NK |
718 | ret = pca953x_write_regs(chip, PCA957X_INVRT, val); |
719 | if (ret) | |
720 | goto out; | |
33226ffd | 721 | |
20a8a968 | 722 | /* To enable register 6, 7 to control pull up and pull down */ |
f5f0b7aa | 723 | memset(val, 0x02, NBANK(chip)); |
c75a3772 NK |
724 | ret = pca953x_write_regs(chip, PCA957X_BKEN, val); |
725 | if (ret) | |
726 | goto out; | |
33226ffd HZ |
727 | |
728 | return 0; | |
729 | out: | |
730 | return ret; | |
731 | } | |
732 | ||
6f29c9af BD |
733 | static const struct of_device_id pca953x_dt_ids[]; |
734 | ||
3836309d | 735 | static int pca953x_probe(struct i2c_client *client, |
6212e1d6 | 736 | const struct i2c_device_id *i2c_id) |
9e60fdcf | 737 | { |
f3dc3630 GL |
738 | struct pca953x_platform_data *pdata; |
739 | struct pca953x_chip *chip; | |
6a7b36aa | 740 | int irq_base = 0; |
7ea2aa20 | 741 | int ret; |
6a7b36aa | 742 | u32 invert = 0; |
e23efa31 | 743 | struct regulator *reg; |
9e60fdcf | 744 | |
b42748c9 LW |
745 | chip = devm_kzalloc(&client->dev, |
746 | sizeof(struct pca953x_chip), GFP_KERNEL); | |
1965d303 NC |
747 | if (chip == NULL) |
748 | return -ENOMEM; | |
749 | ||
e56aee18 | 750 | pdata = dev_get_platdata(&client->dev); |
c6dcf592 DJ |
751 | if (pdata) { |
752 | irq_base = pdata->irq_base; | |
753 | chip->gpio_start = pdata->gpio_base; | |
754 | invert = pdata->invert; | |
755 | chip->names = pdata->names; | |
756 | } else { | |
4bb93349 MP |
757 | chip->gpio_start = -1; |
758 | irq_base = 0; | |
1965d303 | 759 | } |
9e60fdcf | 760 | |
761 | chip->client = client; | |
762 | ||
e23efa31 PR |
763 | reg = devm_regulator_get(&client->dev, "vcc"); |
764 | if (IS_ERR(reg)) { | |
765 | ret = PTR_ERR(reg); | |
766 | if (ret != -EPROBE_DEFER) | |
767 | dev_err(&client->dev, "reg get err: %d\n", ret); | |
768 | return ret; | |
769 | } | |
770 | ret = regulator_enable(reg); | |
771 | if (ret) { | |
772 | dev_err(&client->dev, "reg en err: %d\n", ret); | |
773 | return ret; | |
774 | } | |
775 | chip->regulator = reg; | |
776 | ||
6212e1d6 WS |
777 | if (i2c_id) { |
778 | chip->driver_data = i2c_id->driver_data; | |
f32517bf | 779 | } else { |
6212e1d6 | 780 | const struct acpi_device_id *acpi_id; |
6f29c9af | 781 | const struct of_device_id *match; |
f32517bf | 782 | |
6f29c9af BD |
783 | match = of_match_device(pca953x_dt_ids, &client->dev); |
784 | if (match) { | |
785 | chip->driver_data = (int)(uintptr_t)match->data; | |
786 | } else { | |
6212e1d6 | 787 | acpi_id = acpi_match_device(pca953x_acpi_ids, &client->dev); |
87840a2b | 788 | if (!acpi_id) { |
e23efa31 PR |
789 | ret = -ENODEV; |
790 | goto err_exit; | |
791 | } | |
f32517bf | 792 | |
6212e1d6 | 793 | chip->driver_data = acpi_id->driver_data; |
6f29c9af | 794 | } |
f32517bf AS |
795 | } |
796 | ||
6e20fb18 | 797 | mutex_init(&chip->i2c_lock); |
74f47f07 BG |
798 | /* |
799 | * In case we have an i2c-mux controlled by a GPIO provided by an | |
800 | * expander using the same driver higher on the device tree, read the | |
801 | * i2c adapter nesting depth and use the retrieved value as lockdep | |
802 | * subclass for chip->i2c_lock. | |
803 | * | |
804 | * REVISIT: This solution is not complete. It protects us from lockdep | |
805 | * false positives when the expander controlling the i2c-mux is on | |
806 | * a different level on the device tree, but not when it's on the same | |
807 | * level on a different branch (in which case the subclass number | |
808 | * would be the same). | |
809 | * | |
810 | * TODO: Once a correct solution is developed, a similar fix should be | |
811 | * applied to all other i2c-controlled GPIO expanders (and potentially | |
812 | * regmap-i2c). | |
813 | */ | |
559b4699 BG |
814 | lockdep_set_subclass(&chip->i2c_lock, |
815 | i2c_adapter_depth(client->adapter)); | |
6e20fb18 | 816 | |
9e60fdcf | 817 | /* initialize cached registers from their original values. |
818 | * we can't share this chip with another i2c master. | |
819 | */ | |
c6664149 | 820 | pca953x_setup_gpio(chip, chip->driver_data & PCA_GPIO_MASK); |
f5e8ff48 | 821 | |
7acc66e3 BG |
822 | if (chip->gpio_chip.ngpio <= 8) { |
823 | chip->write_regs = pca953x_write_regs_8; | |
c6e3cf01 | 824 | chip->read_regs = pca953x_read_regs_8; |
7acc66e3 BG |
825 | } else if (chip->gpio_chip.ngpio >= 24) { |
826 | chip->write_regs = pca953x_write_regs_24; | |
c6e3cf01 | 827 | chip->read_regs = pca953x_read_regs_24; |
7acc66e3 BG |
828 | } else { |
829 | if (PCA_CHIP_TYPE(chip->driver_data) == PCA953X_TYPE) | |
830 | chip->write_regs = pca953x_write_regs_16; | |
831 | else | |
832 | chip->write_regs = pca957x_write_regs_16; | |
c6e3cf01 | 833 | chip->read_regs = pca953x_read_regs_16; |
7acc66e3 BG |
834 | } |
835 | ||
60f547be | 836 | if (PCA_CHIP_TYPE(chip->driver_data) == PCA953X_TYPE) |
7ea2aa20 | 837 | ret = device_pca953x_init(chip, invert); |
33226ffd | 838 | else |
7ea2aa20 WS |
839 | ret = device_pca957x_init(chip, invert); |
840 | if (ret) | |
e23efa31 | 841 | goto err_exit; |
9e60fdcf | 842 | |
0ece84f5 | 843 | ret = devm_gpiochip_add_data(&client->dev, &chip->gpio_chip, chip); |
89ea8bbe | 844 | if (ret) |
e23efa31 | 845 | goto err_exit; |
f5e8ff48 | 846 | |
c6664149 | 847 | ret = pca953x_irq_setup(chip, irq_base); |
9e60fdcf | 848 | if (ret) |
e23efa31 | 849 | goto err_exit; |
9e60fdcf | 850 | |
c6dcf592 | 851 | if (pdata && pdata->setup) { |
9e60fdcf | 852 | ret = pdata->setup(client, chip->gpio_chip.base, |
853 | chip->gpio_chip.ngpio, pdata->context); | |
854 | if (ret < 0) | |
855 | dev_warn(&client->dev, "setup failed, %d\n", ret); | |
856 | } | |
857 | ||
858 | i2c_set_clientdata(client, chip); | |
859 | return 0; | |
e23efa31 PR |
860 | |
861 | err_exit: | |
862 | regulator_disable(chip->regulator); | |
863 | return ret; | |
9e60fdcf | 864 | } |
865 | ||
f3dc3630 | 866 | static int pca953x_remove(struct i2c_client *client) |
9e60fdcf | 867 | { |
e56aee18 | 868 | struct pca953x_platform_data *pdata = dev_get_platdata(&client->dev); |
f3dc3630 | 869 | struct pca953x_chip *chip = i2c_get_clientdata(client); |
d147d548 | 870 | int ret; |
9e60fdcf | 871 | |
c6dcf592 | 872 | if (pdata && pdata->teardown) { |
9e60fdcf | 873 | ret = pdata->teardown(client, chip->gpio_chip.base, |
874 | chip->gpio_chip.ngpio, pdata->context); | |
e23efa31 | 875 | if (ret < 0) |
9e60fdcf | 876 | dev_err(&client->dev, "%s failed, %d\n", |
877 | "teardown", ret); | |
bf62efeb AB |
878 | } else { |
879 | ret = 0; | |
9e60fdcf | 880 | } |
881 | ||
e23efa31 PR |
882 | regulator_disable(chip->regulator); |
883 | ||
884 | return ret; | |
9e60fdcf | 885 | } |
886 | ||
6f29c9af BD |
887 | /* convenience to stop overlong match-table lines */ |
888 | #define OF_953X(__nrgpio, __int) (void *)(__nrgpio | PCA953X_TYPE | __int) | |
889 | #define OF_957X(__nrgpio, __int) (void *)(__nrgpio | PCA957X_TYPE | __int) | |
890 | ||
ed32620e | 891 | static const struct of_device_id pca953x_dt_ids[] = { |
6f29c9af BD |
892 | { .compatible = "nxp,pca9505", .data = OF_953X(40, PCA_INT), }, |
893 | { .compatible = "nxp,pca9534", .data = OF_953X( 8, PCA_INT), }, | |
894 | { .compatible = "nxp,pca9535", .data = OF_953X(16, PCA_INT), }, | |
895 | { .compatible = "nxp,pca9536", .data = OF_953X( 4, 0), }, | |
896 | { .compatible = "nxp,pca9537", .data = OF_953X( 4, PCA_INT), }, | |
897 | { .compatible = "nxp,pca9538", .data = OF_953X( 8, PCA_INT), }, | |
898 | { .compatible = "nxp,pca9539", .data = OF_953X(16, PCA_INT), }, | |
899 | { .compatible = "nxp,pca9554", .data = OF_953X( 8, PCA_INT), }, | |
900 | { .compatible = "nxp,pca9555", .data = OF_953X(16, PCA_INT), }, | |
901 | { .compatible = "nxp,pca9556", .data = OF_953X( 8, 0), }, | |
902 | { .compatible = "nxp,pca9557", .data = OF_953X( 8, 0), }, | |
903 | { .compatible = "nxp,pca9574", .data = OF_957X( 8, PCA_INT), }, | |
904 | { .compatible = "nxp,pca9575", .data = OF_957X(16, PCA_INT), }, | |
905 | { .compatible = "nxp,pca9698", .data = OF_953X(40, 0), }, | |
906 | ||
907 | { .compatible = "maxim,max7310", .data = OF_953X( 8, 0), }, | |
908 | { .compatible = "maxim,max7312", .data = OF_953X(16, PCA_INT), }, | |
909 | { .compatible = "maxim,max7313", .data = OF_953X(16, PCA_INT), }, | |
910 | { .compatible = "maxim,max7315", .data = OF_953X( 8, PCA_INT), }, | |
1208c935 | 911 | { .compatible = "maxim,max7318", .data = OF_953X(16, PCA_INT), }, |
6f29c9af BD |
912 | |
913 | { .compatible = "ti,pca6107", .data = OF_953X( 8, PCA_INT), }, | |
353661df | 914 | { .compatible = "ti,pca9536", .data = OF_953X( 4, 0), }, |
6f29c9af BD |
915 | { .compatible = "ti,tca6408", .data = OF_953X( 8, PCA_INT), }, |
916 | { .compatible = "ti,tca6416", .data = OF_953X(16, PCA_INT), }, | |
917 | { .compatible = "ti,tca6424", .data = OF_953X(24, PCA_INT), }, | |
918 | ||
919 | { .compatible = "onsemi,pca9654", .data = OF_953X( 8, PCA_INT), }, | |
920 | ||
921 | { .compatible = "exar,xra1202", .data = OF_953X( 8, 0), }, | |
ed32620e MR |
922 | { } |
923 | }; | |
924 | ||
925 | MODULE_DEVICE_TABLE(of, pca953x_dt_ids); | |
926 | ||
f3dc3630 | 927 | static struct i2c_driver pca953x_driver = { |
9e60fdcf | 928 | .driver = { |
f3dc3630 | 929 | .name = "pca953x", |
ed32620e | 930 | .of_match_table = pca953x_dt_ids, |
f32517bf | 931 | .acpi_match_table = ACPI_PTR(pca953x_acpi_ids), |
9e60fdcf | 932 | }, |
f3dc3630 GL |
933 | .probe = pca953x_probe, |
934 | .remove = pca953x_remove, | |
3760f736 | 935 | .id_table = pca953x_id, |
9e60fdcf | 936 | }; |
937 | ||
f3dc3630 | 938 | static int __init pca953x_init(void) |
9e60fdcf | 939 | { |
f3dc3630 | 940 | return i2c_add_driver(&pca953x_driver); |
9e60fdcf | 941 | } |
2f8d1197 DB |
942 | /* register after i2c postcore initcall and before |
943 | * subsys initcalls that may rely on these GPIOs | |
944 | */ | |
945 | subsys_initcall(pca953x_init); | |
9e60fdcf | 946 | |
f3dc3630 | 947 | static void __exit pca953x_exit(void) |
9e60fdcf | 948 | { |
f3dc3630 | 949 | i2c_del_driver(&pca953x_driver); |
9e60fdcf | 950 | } |
f3dc3630 | 951 | module_exit(pca953x_exit); |
9e60fdcf | 952 | |
953 | MODULE_AUTHOR("eric miao <eric.miao@marvell.com>"); | |
f3dc3630 | 954 | MODULE_DESCRIPTION("GPIO expander driver for PCA953x"); |
9e60fdcf | 955 | MODULE_LICENSE("GPL"); |