projects / mirror_ubuntu-zesty-kernel.git / blame
| Commit | Line | Data |
|---|---|---|
| d38ceaf9 AD |
1 | /** |
| 2 | * \file amdgpu_drv.c | |
| 3 | * AMD Amdgpu driver | |
| 4 | * | |
| 5 | * \author Gareth Hughes <gareth@valinux.com> | |
| 6 | */ | |
| 7 | ||
| 8 | /* | |
| 9 | * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. | |
| 10 | * All Rights Reserved. | |
| 11 | * | |
| 12 | * Permission is hereby granted, free of charge, to any person obtaining a | |
| 13 | * copy of this software and associated documentation files (the "Software"), | |
| 14 | * to deal in the Software without restriction, including without limitation | |
| 15 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
| 16 | * and/or sell copies of the Software, and to permit persons to whom the | |
| 17 | * Software is furnished to do so, subject to the following conditions: | |
| 18 | * | |
| 19 | * The above copyright notice and this permission notice (including the next | |
| 20 | * paragraph) shall be included in all copies or substantial portions of the | |
| 21 | * Software. | |
| 22 | * | |
| 23 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
| 24 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
| 25 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
| 26 | * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
| 27 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
| 28 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
| 29 | * OTHER DEALINGS IN THE SOFTWARE. | |
| 30 | */ | |
| 31 | ||
| 32 | #include <drm/drmP.h> | |
| 33 | #include <drm/amdgpu_drm.h> | |
| 34 | #include <drm/drm_gem.h> | |
| 35 | #include "amdgpu_drv.h" | |
| 36 | ||
| 37 | #include <drm/drm_pciids.h> | |
| 38 | #include <linux/console.h> | |
| 39 | #include <linux/module.h> | |
| 40 | #include <linux/pm_runtime.h> | |
| 41 | #include <linux/vga_switcheroo.h> | |
| 42 | #include "drm_crtc_helper.h" | |
| 43 | ||
| 44 | #include "amdgpu.h" | |
| 45 | #include "amdgpu_irq.h" | |
| 46 | ||
| 130e0371 OG |
47 | #include "amdgpu_amdkfd.h" |
| 48 | ||
| d38ceaf9 AD |
49 | /* |
| 50 | * KMS wrapper. | |
| 51 | * - 3.0.0 - initial driver | |
| 6055f37a | 52 | * - 3.1.0 - allow reading more status registers (GRBM, SRBM, SDMA, CP) |
| d38ceaf9 AD |
53 | */ |
| 54 | #define KMS_DRIVER_MAJOR 3 | |
| 6055f37a | 55 | #define KMS_DRIVER_MINOR 1 |
| d38ceaf9 AD |
56 | #define KMS_DRIVER_PATCHLEVEL 0 |
| 57 | ||
| 58 | int amdgpu_vram_limit = 0; | |
| 59 | int amdgpu_gart_size = -1; /* auto */ | |
| 60 | int amdgpu_benchmarking = 0; | |
| 61 | int amdgpu_testing = 0; | |
| 62 | int amdgpu_audio = -1; | |
| 63 | int amdgpu_disp_priority = 0; | |
| 64 | int amdgpu_hw_i2c = 0; | |
| 65 | int amdgpu_pcie_gen2 = -1; | |
| 66 | int amdgpu_msi = -1; | |
| a895c222 | 67 | int amdgpu_lockup_timeout = 0; |
| d38ceaf9 AD |
68 | int amdgpu_dpm = -1; |
| 69 | int amdgpu_smc_load_fw = 1; | |
| 70 | int amdgpu_aspm = -1; | |
| 71 | int amdgpu_runtime_pm = -1; | |
| 72 | int amdgpu_hard_reset = 0; | |
| 73 | unsigned amdgpu_ip_block_mask = 0xffffffff; | |
| 74 | int amdgpu_bapm = -1; | |
| 75 | int amdgpu_deep_color = 0; | |
| ed885b21 | 76 | int amdgpu_vm_size = 64; |
| d38ceaf9 | 77 | int amdgpu_vm_block_size = -1; |
| d9c13156 | 78 | int amdgpu_vm_fault_stop = 0; |
| b495bd3a | 79 | int amdgpu_vm_debug = 0; |
| d38ceaf9 | 80 | int amdgpu_exp_hw_support = 0; |
| 36b4ba07 | 81 | int amdgpu_enable_scheduler = 1; |
| b70f014d | 82 | int amdgpu_sched_jobs = 32; |
| 4afcb303 | 83 | int amdgpu_sched_hw_submission = 2; |
| d4edda3f | 84 | int amdgpu_enable_semaphores = 0; |
| e61710c5 | 85 | int amdgpu_powerplay = -1; |
| cd474ba0 AD |
86 | unsigned amdgpu_pcie_gen_cap = 0; |
| 87 | unsigned amdgpu_pcie_lane_cap = 0; | |
| d38ceaf9 AD |
88 | |
| 89 | MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing, in megabytes"); | |
| 90 | module_param_named(vramlimit, amdgpu_vram_limit, int, 0600); | |
| 91 | ||
| 92 | MODULE_PARM_DESC(gartsize, "Size of PCIE/IGP gart to setup in megabytes (32, 64, etc., -1 = auto)"); | |
| 93 | module_param_named(gartsize, amdgpu_gart_size, int, 0600); | |
| 94 | ||
| 95 | MODULE_PARM_DESC(benchmark, "Run benchmark"); | |
| 96 | module_param_named(benchmark, amdgpu_benchmarking, int, 0444); | |
| 97 | ||
| 98 | MODULE_PARM_DESC(test, "Run tests"); | |
| 99 | module_param_named(test, amdgpu_testing, int, 0444); | |
| 100 | ||
| 101 | MODULE_PARM_DESC(audio, "Audio enable (-1 = auto, 0 = disable, 1 = enable)"); | |
| 102 | module_param_named(audio, amdgpu_audio, int, 0444); | |
| 103 | ||
| 104 | MODULE_PARM_DESC(disp_priority, "Display Priority (0 = auto, 1 = normal, 2 = high)"); | |
| 105 | module_param_named(disp_priority, amdgpu_disp_priority, int, 0444); | |
| 106 | ||
| 107 | MODULE_PARM_DESC(hw_i2c, "hw i2c engine enable (0 = disable)"); | |
| 108 | module_param_named(hw_i2c, amdgpu_hw_i2c, int, 0444); | |
| 109 | ||
| 110 | MODULE_PARM_DESC(pcie_gen2, "PCIE Gen2 mode (-1 = auto, 0 = disable, 1 = enable)"); | |
| 111 | module_param_named(pcie_gen2, amdgpu_pcie_gen2, int, 0444); | |
| 112 | ||
| 113 | MODULE_PARM_DESC(msi, "MSI support (1 = enable, 0 = disable, -1 = auto)"); | |
| 114 | module_param_named(msi, amdgpu_msi, int, 0444); | |
| 115 | ||
| a895c222 | 116 | MODULE_PARM_DESC(lockup_timeout, "GPU lockup timeout in ms (default 0 = disable)"); |
| d38ceaf9 AD |
117 | module_param_named(lockup_timeout, amdgpu_lockup_timeout, int, 0444); |
| 118 | ||
| 119 | MODULE_PARM_DESC(dpm, "DPM support (1 = enable, 0 = disable, -1 = auto)"); | |
| 120 | module_param_named(dpm, amdgpu_dpm, int, 0444); | |
| 121 | ||
| 122 | MODULE_PARM_DESC(smc_load_fw, "SMC firmware loading(1 = enable, 0 = disable)"); | |
| 123 | module_param_named(smc_load_fw, amdgpu_smc_load_fw, int, 0444); | |
| 124 | ||
| 125 | MODULE_PARM_DESC(aspm, "ASPM support (1 = enable, 0 = disable, -1 = auto)"); | |
| 126 | module_param_named(aspm, amdgpu_aspm, int, 0444); | |
| 127 | ||
| 128 | MODULE_PARM_DESC(runpm, "PX runtime pm (1 = force enable, 0 = disable, -1 = PX only default)"); | |
| 129 | module_param_named(runpm, amdgpu_runtime_pm, int, 0444); | |
| 130 | ||
| 131 | MODULE_PARM_DESC(hard_reset, "PCI config reset (1 = force enable, 0 = disable (default))"); | |
| 132 | module_param_named(hard_reset, amdgpu_hard_reset, int, 0444); | |
| 133 | ||
| 134 | MODULE_PARM_DESC(ip_block_mask, "IP Block Mask (all blocks enabled (default))"); | |
| 135 | module_param_named(ip_block_mask, amdgpu_ip_block_mask, uint, 0444); | |
| 136 | ||
| 137 | MODULE_PARM_DESC(bapm, "BAPM support (1 = enable, 0 = disable, -1 = auto)"); | |
| 138 | module_param_named(bapm, amdgpu_bapm, int, 0444); | |
| 139 | ||
| 140 | MODULE_PARM_DESC(deep_color, "Deep Color support (1 = enable, 0 = disable (default))"); | |
| 141 | module_param_named(deep_color, amdgpu_deep_color, int, 0444); | |
| 142 | ||
| ed885b21 | 143 | MODULE_PARM_DESC(vm_size, "VM address space size in gigabytes (default 64GB)"); |
| d38ceaf9 AD |
144 | module_param_named(vm_size, amdgpu_vm_size, int, 0444); |
| 145 | ||
| 146 | MODULE_PARM_DESC(vm_block_size, "VM page table size in bits (default depending on vm_size)"); | |
| 147 | module_param_named(vm_block_size, amdgpu_vm_block_size, int, 0444); | |
| 148 | ||
| d9c13156 CK |
149 | MODULE_PARM_DESC(vm_fault_stop, "Stop on VM fault (0 = never (default), 1 = print first, 2 = always)"); |
| 150 | module_param_named(vm_fault_stop, amdgpu_vm_fault_stop, int, 0444); | |
| 151 | ||
| b495bd3a CK |
152 | MODULE_PARM_DESC(vm_debug, "Debug VM handling (0 = disabled (default), 1 = enabled)"); |
| 153 | module_param_named(vm_debug, amdgpu_vm_debug, int, 0644); | |
| 154 | ||
| d38ceaf9 AD |
155 | MODULE_PARM_DESC(exp_hw_support, "experimental hw support (1 = enable, 0 = disable (default))"); |
| 156 | module_param_named(exp_hw_support, amdgpu_exp_hw_support, int, 0444); | |
| 157 | ||
| 36b4ba07 | 158 | MODULE_PARM_DESC(enable_scheduler, "enable SW GPU scheduler (1 = enable (default), 0 = disable)"); |
| 02b9f0bf JZ |
159 | module_param_named(enable_scheduler, amdgpu_enable_scheduler, int, 0444); |
| 160 | ||
| b70f014d | 161 | MODULE_PARM_DESC(sched_jobs, "the max number of jobs supported in the sw queue (default 32)"); |
| 1333f723 JZ |
162 | module_param_named(sched_jobs, amdgpu_sched_jobs, int, 0444); |
| 163 | ||
| 4afcb303 JZ |
164 | MODULE_PARM_DESC(sched_hw_submission, "the max number of HW submissions (default 2)"); |
| 165 | module_param_named(sched_hw_submission, amdgpu_sched_hw_submission, int, 0444); | |
| 166 | ||
| d4edda3f | 167 | MODULE_PARM_DESC(enable_semaphores, "Enable semaphores (1 = enable, 0 = disable (default))"); |
| 3daea9e3 CK |
168 | module_param_named(enable_semaphores, amdgpu_enable_semaphores, int, 0644); |
| 169 | ||
| 3a74f6f2 | 170 | #ifdef CONFIG_DRM_AMD_POWERPLAY |
| e61710c5 | 171 | MODULE_PARM_DESC(powerplay, "Powerplay component (1 = enable, 0 = disable, -1 = auto (default))"); |
| 3a74f6f2 JZ |
172 | module_param_named(powerplay, amdgpu_powerplay, int, 0444); |
| 173 | #endif | |
| 174 | ||
| cd474ba0 AD |
175 | MODULE_PARM_DESC(pcie_gen_cap, "PCIE Gen Caps (0: autodetect (default))"); |
| 176 | module_param_named(pcie_gen_cap, amdgpu_pcie_gen_cap, uint, 0444); | |
| 177 | ||
| 178 | MODULE_PARM_DESC(pcie_lane_cap, "PCIE Lane Caps (0: autodetect (default))"); | |
| 179 | module_param_named(pcie_lane_cap, amdgpu_pcie_lane_cap, uint, 0444); | |
| 180 | ||
| d38ceaf9 | 181 | static struct pci_device_id pciidlist[] = { |
| 89330c39 AD |
182 | #ifdef CONFIG_DRM_AMDGPU_CIK |
| 183 | /* Kaveri */ | |
| 2f7d10b3 JZ |
184 | {0x1002, 0x1304, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, |
| 185 | {0x1002, 0x1305, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, | |
| 186 | {0x1002, 0x1306, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, | |
| 187 | {0x1002, 0x1307, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, | |
| 188 | {0x1002, 0x1309, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, | |
| 189 | {0x1002, 0x130A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, | |
| 190 | {0x1002, 0x130B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, | |
| 191 | {0x1002, 0x130C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, | |
| 192 | {0x1002, 0x130D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, | |
| 193 | {0x1002, 0x130E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, | |
| 194 | {0x1002, 0x130F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, | |
| 195 | {0x1002, 0x1310, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, | |
| 196 | {0x1002, 0x1311, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, | |
| 197 | {0x1002, 0x1312, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, | |
| 198 | {0x1002, 0x1313, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, | |
| 199 | {0x1002, 0x1315, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, | |
| 200 | {0x1002, 0x1316, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, | |
| 201 | {0x1002, 0x1317, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, | |
| 202 | {0x1002, 0x1318, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, | |
| 203 | {0x1002, 0x131B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, | |
| 204 | {0x1002, 0x131C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, | |
| 205 | {0x1002, 0x131D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, | |
| 89330c39 | 206 | /* Bonaire */ |
| 2f7d10b3 JZ |
207 | {0x1002, 0x6640, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, |
| 208 | {0x1002, 0x6641, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, | |
| 209 | {0x1002, 0x6646, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, | |
| 210 | {0x1002, 0x6647, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, | |
| 89330c39 AD |
211 | {0x1002, 0x6649, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, |
| 212 | {0x1002, 0x6650, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, | |
| 213 | {0x1002, 0x6651, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, | |
| 214 | {0x1002, 0x6658, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, | |
| 215 | {0x1002, 0x665c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, | |
| 216 | {0x1002, 0x665d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, | |
| fb4f1737 | 217 | {0x1002, 0x665f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, |
| 89330c39 AD |
218 | /* Hawaii */ |
| 219 | {0x1002, 0x67A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, | |
| 220 | {0x1002, 0x67A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, | |
| 221 | {0x1002, 0x67A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, | |
| 222 | {0x1002, 0x67A8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, | |
| 223 | {0x1002, 0x67A9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, | |
| 224 | {0x1002, 0x67AA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, | |
| 225 | {0x1002, 0x67B0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, | |
| 226 | {0x1002, 0x67B1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, | |
| 227 | {0x1002, 0x67B8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, | |
| 228 | {0x1002, 0x67B9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, | |
| 229 | {0x1002, 0x67BA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, | |
| 230 | {0x1002, 0x67BE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, | |
| 231 | /* Kabini */ | |
| 2f7d10b3 JZ |
232 | {0x1002, 0x9830, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, |
| 233 | {0x1002, 0x9831, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, | |
| 234 | {0x1002, 0x9832, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, | |
| 235 | {0x1002, 0x9833, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, | |
| 236 | {0x1002, 0x9834, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, | |
| 237 | {0x1002, 0x9835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, | |
| 238 | {0x1002, 0x9836, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, | |
| 239 | {0x1002, 0x9837, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, | |
| 240 | {0x1002, 0x9838, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, | |
| 241 | {0x1002, 0x9839, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, | |
| 242 | {0x1002, 0x983a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, | |
| 243 | {0x1002, 0x983b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, | |
| 244 | {0x1002, 0x983c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, | |
| 245 | {0x1002, 0x983d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, | |
| 246 | {0x1002, 0x983e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, | |
| 247 | {0x1002, 0x983f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, | |
| 89330c39 | 248 | /* mullins */ |
| 2f7d10b3 JZ |
249 | {0x1002, 0x9850, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, |
| 250 | {0x1002, 0x9851, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, | |
| 251 | {0x1002, 0x9852, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, | |
| 252 | {0x1002, 0x9853, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, | |
| 253 | {0x1002, 0x9854, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, | |
| 254 | {0x1002, 0x9855, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, | |
| 255 | {0x1002, 0x9856, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, | |
| 256 | {0x1002, 0x9857, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, | |
| 257 | {0x1002, 0x9858, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, | |
| 258 | {0x1002, 0x9859, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, | |
| 259 | {0x1002, 0x985A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, | |
| 260 | {0x1002, 0x985B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, | |
| 261 | {0x1002, 0x985C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, | |
| 262 | {0x1002, 0x985D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, | |
| 263 | {0x1002, 0x985E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, | |
| 264 | {0x1002, 0x985F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, | |
| 89330c39 | 265 | #endif |
| 1256a8b8 | 266 | /* topaz */ |
| dba280b2 AD |
267 | {0x1002, 0x6900, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, |
| 268 | {0x1002, 0x6901, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, | |
| 269 | {0x1002, 0x6902, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, | |
| 270 | {0x1002, 0x6903, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, | |
| 271 | {0x1002, 0x6907, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, | |
| 1256a8b8 AD |
272 | /* tonga */ |
| 273 | {0x1002, 0x6920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, | |
| 274 | {0x1002, 0x6921, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, | |
| 275 | {0x1002, 0x6928, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, | |
| 1f8d9625 | 276 | {0x1002, 0x6929, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, |
| 1256a8b8 AD |
277 | {0x1002, 0x692B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, |
| 278 | {0x1002, 0x692F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, | |
| 1f8d9625 | 279 | {0x1002, 0x6930, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, |
| 1256a8b8 AD |
280 | {0x1002, 0x6938, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, |
| 281 | {0x1002, 0x6939, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, | |
| 2da78e21 DZ |
282 | /* fiji */ |
| 283 | {0x1002, 0x7300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_FIJI}, | |
| 1256a8b8 | 284 | /* carrizo */ |
| 2f7d10b3 JZ |
285 | {0x1002, 0x9870, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, |
| 286 | {0x1002, 0x9874, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, | |
| 287 | {0x1002, 0x9875, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, | |
| 288 | {0x1002, 0x9876, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, | |
| 289 | {0x1002, 0x9877, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, | |
| 81b1509a SL |
290 | /* stoney */ |
| 291 | {0x1002, 0x98E4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_STONEY|AMD_IS_APU}, | |
| d38ceaf9 AD |
292 | |
| 293 | {0, 0, 0} | |
| 294 | }; | |
| 295 | ||
| 296 | MODULE_DEVICE_TABLE(pci, pciidlist); | |
| 297 | ||
| 298 | static struct drm_driver kms_driver; | |
| 299 | ||
| 300 | static int amdgpu_kick_out_firmware_fb(struct pci_dev *pdev) | |
| 301 | { | |
| 302 | struct apertures_struct *ap; | |
| 303 | bool primary = false; | |
| 304 | ||
| 305 | ap = alloc_apertures(1); | |
| 306 | if (!ap) | |
| 307 | return -ENOMEM; | |
| 308 | ||
| 309 | ap->ranges[0].base = pci_resource_start(pdev, 0); | |
| 310 | ap->ranges[0].size = pci_resource_len(pdev, 0); | |
| 311 | ||
| 312 | #ifdef CONFIG_X86 | |
| 313 | primary = pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW; | |
| 314 | #endif | |
| 315 | remove_conflicting_framebuffers(ap, "amdgpudrmfb", primary); | |
| 316 | kfree(ap); | |
| 317 | ||
| 318 | return 0; | |
| 319 | } | |
| 320 | ||
| 321 | static int amdgpu_pci_probe(struct pci_dev *pdev, | |
| 322 | const struct pci_device_id *ent) | |
| 323 | { | |
| 324 | unsigned long flags = ent->driver_data; | |
| 325 | int ret; | |
| 326 | ||
| 2f7d10b3 | 327 | if ((flags & AMD_EXP_HW_SUPPORT) && !amdgpu_exp_hw_support) { |
| d38ceaf9 AD |
328 | DRM_INFO("This hardware requires experimental hardware support.\n" |
| 329 | "See modparam exp_hw_support\n"); | |
| 330 | return -ENODEV; | |
| 331 | } | |
| 332 | ||
| 333 | /* Get rid of things like offb */ | |
| 334 | ret = amdgpu_kick_out_firmware_fb(pdev); | |
| 335 | if (ret) | |
| 336 | return ret; | |
| 337 | ||
| 338 | return drm_get_pci_dev(pdev, ent, &kms_driver); | |
| 339 | } | |
| 340 | ||
| 341 | static void | |
| 342 | amdgpu_pci_remove(struct pci_dev *pdev) | |
| 343 | { | |
| 344 | struct drm_device *dev = pci_get_drvdata(pdev); | |
| 345 | ||
| 346 | drm_put_dev(dev); | |
| 347 | } | |
| 348 | ||
| 349 | static int amdgpu_pmops_suspend(struct device *dev) | |
| 350 | { | |
| 351 | struct pci_dev *pdev = to_pci_dev(dev); | |
| 352 | struct drm_device *drm_dev = pci_get_drvdata(pdev); | |
| 353 | return amdgpu_suspend_kms(drm_dev, true, true); | |
| 354 | } | |
| 355 | ||
| 356 | static int amdgpu_pmops_resume(struct device *dev) | |
| 357 | { | |
| 358 | struct pci_dev *pdev = to_pci_dev(dev); | |
| 359 | struct drm_device *drm_dev = pci_get_drvdata(pdev); | |
| 360 | return amdgpu_resume_kms(drm_dev, true, true); | |
| 361 | } | |
| 362 | ||
| 363 | static int amdgpu_pmops_freeze(struct device *dev) | |
| 364 | { | |
| 365 | struct pci_dev *pdev = to_pci_dev(dev); | |
| 366 | struct drm_device *drm_dev = pci_get_drvdata(pdev); | |
| 367 | return amdgpu_suspend_kms(drm_dev, false, true); | |
| 368 | } | |
| 369 | ||
| 370 | static int amdgpu_pmops_thaw(struct device *dev) | |
| 371 | { | |
| 372 | struct pci_dev *pdev = to_pci_dev(dev); | |
| 373 | struct drm_device *drm_dev = pci_get_drvdata(pdev); | |
| 374 | return amdgpu_resume_kms(drm_dev, false, true); | |
| 375 | } | |
| 376 | ||
| 377 | static int amdgpu_pmops_runtime_suspend(struct device *dev) | |
| 378 | { | |
| 379 | struct pci_dev *pdev = to_pci_dev(dev); | |
| 380 | struct drm_device *drm_dev = pci_get_drvdata(pdev); | |
| 381 | int ret; | |
| 382 | ||
| 383 | if (!amdgpu_device_is_px(drm_dev)) { | |
| 384 | pm_runtime_forbid(dev); | |
| 385 | return -EBUSY; | |
| 386 | } | |
| 387 | ||
| 388 | drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; | |
| 389 | drm_kms_helper_poll_disable(drm_dev); | |
| 390 | vga_switcheroo_set_dynamic_switch(pdev, VGA_SWITCHEROO_OFF); | |
| 391 | ||
| 392 | ret = amdgpu_suspend_kms(drm_dev, false, false); | |
| 393 | pci_save_state(pdev); | |
| 394 | pci_disable_device(pdev); | |
| 395 | pci_ignore_hotplug(pdev); | |
| 396 | pci_set_power_state(pdev, PCI_D3cold); | |
| 397 | drm_dev->switch_power_state = DRM_SWITCH_POWER_DYNAMIC_OFF; | |
| 398 | ||
| 399 | return 0; | |
| 400 | } | |
| 401 | ||
| 402 | static int amdgpu_pmops_runtime_resume(struct device *dev) | |
| 403 | { | |
| 404 | struct pci_dev *pdev = to_pci_dev(dev); | |
| 405 | struct drm_device *drm_dev = pci_get_drvdata(pdev); | |
| 406 | int ret; | |
| 407 | ||
| 408 | if (!amdgpu_device_is_px(drm_dev)) | |
| 409 | return -EINVAL; | |
| 410 | ||
| 411 | drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; | |
| 412 | ||
| 413 | pci_set_power_state(pdev, PCI_D0); | |
| 414 | pci_restore_state(pdev); | |
| 415 | ret = pci_enable_device(pdev); | |
| 416 | if (ret) | |
| 417 | return ret; | |
| 418 | pci_set_master(pdev); | |
| 419 | ||
| 420 | ret = amdgpu_resume_kms(drm_dev, false, false); | |
| 421 | drm_kms_helper_poll_enable(drm_dev); | |
| 422 | vga_switcheroo_set_dynamic_switch(pdev, VGA_SWITCHEROO_ON); | |
| 423 | drm_dev->switch_power_state = DRM_SWITCH_POWER_ON; | |
| 424 | return 0; | |
| 425 | } | |
| 426 | ||
| 427 | static int amdgpu_pmops_runtime_idle(struct device *dev) | |
| 428 | { | |
| 429 | struct pci_dev *pdev = to_pci_dev(dev); | |
| 430 | struct drm_device *drm_dev = pci_get_drvdata(pdev); | |
| 431 | struct drm_crtc *crtc; | |
| 432 | ||
| 433 | if (!amdgpu_device_is_px(drm_dev)) { | |
| 434 | pm_runtime_forbid(dev); | |
| 435 | return -EBUSY; | |
| 436 | } | |
| 437 | ||
| 438 | list_for_each_entry(crtc, &drm_dev->mode_config.crtc_list, head) { | |
| 439 | if (crtc->enabled) { | |
| 440 | DRM_DEBUG_DRIVER("failing to power off - crtc active\n"); | |
| 441 | return -EBUSY; | |
| 442 | } | |
| 443 | } | |
| 444 | ||
| 445 | pm_runtime_mark_last_busy(dev); | |
| 446 | pm_runtime_autosuspend(dev); | |
| 447 | /* we don't want the main rpm_idle to call suspend - we want to autosuspend */ | |
| 448 | return 1; | |
| 449 | } | |
| 450 | ||
| 451 | long amdgpu_drm_ioctl(struct file *filp, | |
| 452 | unsigned int cmd, unsigned long arg) | |
| 453 | { | |
| 454 | struct drm_file *file_priv = filp->private_data; | |
| 455 | struct drm_device *dev; | |
| 456 | long ret; | |
| 457 | dev = file_priv->minor->dev; | |
| 458 | ret = pm_runtime_get_sync(dev->dev); | |
| 459 | if (ret < 0) | |
| 460 | return ret; | |
| 461 | ||
| 462 | ret = drm_ioctl(filp, cmd, arg); | |
| 463 | ||
| 464 | pm_runtime_mark_last_busy(dev->dev); | |
| 465 | pm_runtime_put_autosuspend(dev->dev); | |
| 466 | return ret; | |
| 467 | } | |
| 468 | ||
| 469 | static const struct dev_pm_ops amdgpu_pm_ops = { | |
| 470 | .suspend = amdgpu_pmops_suspend, | |
| 471 | .resume = amdgpu_pmops_resume, | |
| 472 | .freeze = amdgpu_pmops_freeze, | |
| 473 | .thaw = amdgpu_pmops_thaw, | |
| 474 | .poweroff = amdgpu_pmops_freeze, | |
| 475 | .restore = amdgpu_pmops_resume, | |
| 476 | .runtime_suspend = amdgpu_pmops_runtime_suspend, | |
| 477 | .runtime_resume = amdgpu_pmops_runtime_resume, | |
| 478 | .runtime_idle = amdgpu_pmops_runtime_idle, | |
| 479 | }; | |
| 480 | ||
| 481 | static const struct file_operations amdgpu_driver_kms_fops = { | |
| 482 | .owner = THIS_MODULE, | |
| 483 | .open = drm_open, | |
| 484 | .release = drm_release, | |
| 485 | .unlocked_ioctl = amdgpu_drm_ioctl, | |
| 486 | .mmap = amdgpu_mmap, | |
| 487 | .poll = drm_poll, | |
| 488 | .read = drm_read, | |
| 489 | #ifdef CONFIG_COMPAT | |
| 490 | .compat_ioctl = amdgpu_kms_compat_ioctl, | |
| 491 | #endif | |
| 492 | }; | |
| 493 | ||
| 494 | static struct drm_driver kms_driver = { | |
| 495 | .driver_features = | |
| 496 | DRIVER_USE_AGP | | |
| 497 | DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM | | |
| 498 | DRIVER_PRIME | DRIVER_RENDER, | |
| 499 | .dev_priv_size = 0, | |
| 500 | .load = amdgpu_driver_load_kms, | |
| 501 | .open = amdgpu_driver_open_kms, | |
| 502 | .preclose = amdgpu_driver_preclose_kms, | |
| 503 | .postclose = amdgpu_driver_postclose_kms, | |
| 504 | .lastclose = amdgpu_driver_lastclose_kms, | |
| 505 | .set_busid = drm_pci_set_busid, | |
| 506 | .unload = amdgpu_driver_unload_kms, | |
| 507 | .get_vblank_counter = amdgpu_get_vblank_counter_kms, | |
| 508 | .enable_vblank = amdgpu_enable_vblank_kms, | |
| 509 | .disable_vblank = amdgpu_disable_vblank_kms, | |
| 510 | .get_vblank_timestamp = amdgpu_get_vblank_timestamp_kms, | |
| 511 | .get_scanout_position = amdgpu_get_crtc_scanoutpos, | |
| 512 | #if defined(CONFIG_DEBUG_FS) | |
| 513 | .debugfs_init = amdgpu_debugfs_init, | |
| 514 | .debugfs_cleanup = amdgpu_debugfs_cleanup, | |
| 515 | #endif | |
| 516 | .irq_preinstall = amdgpu_irq_preinstall, | |
| 517 | .irq_postinstall = amdgpu_irq_postinstall, | |
| 518 | .irq_uninstall = amdgpu_irq_uninstall, | |
| 519 | .irq_handler = amdgpu_irq_handler, | |
| 520 | .ioctls = amdgpu_ioctls_kms, | |
| 521 | .gem_free_object = amdgpu_gem_object_free, | |
| 522 | .gem_open_object = amdgpu_gem_object_open, | |
| 523 | .gem_close_object = amdgpu_gem_object_close, | |
| 524 | .dumb_create = amdgpu_mode_dumb_create, | |
| 525 | .dumb_map_offset = amdgpu_mode_dumb_mmap, | |
| 526 | .dumb_destroy = drm_gem_dumb_destroy, | |
| 527 | .fops = &amdgpu_driver_kms_fops, | |
| 528 | ||
| 529 | .prime_handle_to_fd = drm_gem_prime_handle_to_fd, | |
| 530 | .prime_fd_to_handle = drm_gem_prime_fd_to_handle, | |
| 531 | .gem_prime_export = amdgpu_gem_prime_export, | |
| 532 | .gem_prime_import = drm_gem_prime_import, | |
| 533 | .gem_prime_pin = amdgpu_gem_prime_pin, | |
| 534 | .gem_prime_unpin = amdgpu_gem_prime_unpin, | |
| 535 | .gem_prime_res_obj = amdgpu_gem_prime_res_obj, | |
| 536 | .gem_prime_get_sg_table = amdgpu_gem_prime_get_sg_table, | |
| 537 | .gem_prime_import_sg_table = amdgpu_gem_prime_import_sg_table, | |
| 538 | .gem_prime_vmap = amdgpu_gem_prime_vmap, | |
| 539 | .gem_prime_vunmap = amdgpu_gem_prime_vunmap, | |
| 540 | ||
| 541 | .name = DRIVER_NAME, | |
| 542 | .desc = DRIVER_DESC, | |
| 543 | .date = DRIVER_DATE, | |
| 544 | .major = KMS_DRIVER_MAJOR, | |
| 545 | .minor = KMS_DRIVER_MINOR, | |
| 546 | .patchlevel = KMS_DRIVER_PATCHLEVEL, | |
| 547 | }; | |
| 548 | ||
| 549 | static struct drm_driver *driver; | |
| 550 | static struct pci_driver *pdriver; | |
| 551 | ||
| 552 | static struct pci_driver amdgpu_kms_pci_driver = { | |
| 553 | .name = DRIVER_NAME, | |
| 554 | .id_table = pciidlist, | |
| 555 | .probe = amdgpu_pci_probe, | |
| 556 | .remove = amdgpu_pci_remove, | |
| 557 | .driver.pm = &amdgpu_pm_ops, | |
| 558 | }; | |
| 559 | ||
| 560 | static int __init amdgpu_init(void) | |
| 561 | { | |
| 562 | #ifdef CONFIG_VGA_CONSOLE | |
| 563 | if (vgacon_text_force()) { | |
| 564 | DRM_ERROR("VGACON disables amdgpu kernel modesetting.\n"); | |
| 565 | return -EINVAL; | |
| 566 | } | |
| 567 | #endif | |
| 568 | DRM_INFO("amdgpu kernel modesetting enabled.\n"); | |
| 569 | driver = &kms_driver; | |
| 570 | pdriver = &amdgpu_kms_pci_driver; | |
| 571 | driver->driver_features |= DRIVER_MODESET; | |
| 572 | driver->num_ioctls = amdgpu_max_kms_ioctl; | |
| 573 | amdgpu_register_atpx_handler(); | |
| 574 | ||
| 130e0371 OG |
575 | amdgpu_amdkfd_init(); |
| 576 | ||
| d38ceaf9 AD |
577 | /* let modprobe override vga console setting */ |
| 578 | return drm_pci_init(driver, pdriver); | |
| 579 | } | |
| 580 | ||
| 581 | static void __exit amdgpu_exit(void) | |
| 582 | { | |
| 130e0371 | 583 | amdgpu_amdkfd_fini(); |
| d38ceaf9 AD |
584 | drm_pci_exit(driver, pdriver); |
| 585 | amdgpu_unregister_atpx_handler(); | |
| 586 | } | |
| 587 | ||
| 588 | module_init(amdgpu_init); | |
| 589 | module_exit(amdgpu_exit); | |
| 590 | ||
| 591 | MODULE_AUTHOR(DRIVER_AUTHOR); | |
| 592 | MODULE_DESCRIPTION(DRIVER_DESC); | |
| 593 | MODULE_LICENSE("GPL and additional rights"); |