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drm/amdgpu/gfx9: fullfill kiq irq funcs (v2)
[mirror_ubuntu-artful-kernel.git] / drivers / gpu / drm / amd / amdgpu / gfx_v9_0.c
CommitLineData
b1023571
KW		 1/*
2 * Copyright 2016 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23#include <linux/firmware.h>
24#include "drmP.h"
25#include "amdgpu.h"
26#include "amdgpu_gfx.h"
27#include "soc15.h"
28#include "soc15d.h"
29
30#include "vega10/soc15ip.h"
31#include "vega10/GC/gc_9_0_offset.h"
32#include "vega10/GC/gc_9_0_sh_mask.h"
33#include "vega10/vega10_enum.h"
34#include "vega10/HDP/hdp_4_0_offset.h"
35
36#include "soc15_common.h"
37#include "clearstate_gfx9.h"
38#include "v9_structs.h"
39
40#define GFX9_NUM_GFX_RINGS 1
41#define GFX9_NUM_COMPUTE_RINGS 8
42#define GFX9_NUM_SE 4
43#define RLCG_UCODE_LOADING_START_ADDRESS 0x2000
44
45MODULE_FIRMWARE("amdgpu/vega10_ce.bin");
46MODULE_FIRMWARE("amdgpu/vega10_pfp.bin");
47MODULE_FIRMWARE("amdgpu/vega10_me.bin");
48MODULE_FIRMWARE("amdgpu/vega10_mec.bin");
49MODULE_FIRMWARE("amdgpu/vega10_mec2.bin");
50MODULE_FIRMWARE("amdgpu/vega10_rlc.bin");
51
52static const struct amdgpu_gds_reg_offset amdgpu_gds_reg_offset[] =
53{
54 {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_SIZE),
55 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID0), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID0)},
56 {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID1_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID1_SIZE),
57 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID1), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID1)},
58 {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID2_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID2_SIZE),
59 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID2), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID2)},
60 {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID3_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID3_SIZE),
61 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID3), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID3)},
62 {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID4_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID4_SIZE),
63 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID4), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID4)},
64 {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID5_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID5_SIZE),
65 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID5), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID5)},
66 {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID6_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID6_SIZE),
67 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID6), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID6)},
68 {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID7_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID7_SIZE),
69 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID7), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID7)},
70 {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID8_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID8_SIZE),
71 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID8), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID8)},
72 {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID9_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID9_SIZE),
73 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID9), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID9)},
74 {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID10_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID10_SIZE),
75 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID10), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID10)},
76 {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID11_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID11_SIZE),
77 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID11), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID11)},
78 {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID12_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID12_SIZE),
79 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID12), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID12)},
80 {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID13_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID13_SIZE),
81 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID13), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID13)},
82 {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID14_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID14_SIZE),
83 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID14), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID14)},
84 {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID15_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID15_SIZE),
85 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID15), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID15)}
86};
87
88static const u32 golden_settings_gc_9_0[] =
89{
90 SOC15_REG_OFFSET(GC, 0, mmDB_DEBUG2), 0xf00ffeff, 0x00000400,
91 SOC15_REG_OFFSET(GC, 0, mmGB_GPU_ID), 0x0000000f, 0x00000000,
92 SOC15_REG_OFFSET(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_3), 0x00000003, 0x82400024,
93 SOC15_REG_OFFSET(GC, 0, mmPA_SC_ENHANCE), 0x3fffffff, 0x00000001,
94 SOC15_REG_OFFSET(GC, 0, mmPA_SC_LINE_STIPPLE_STATE), 0x0000ff0f, 0x00000000,
95 SOC15_REG_OFFSET(GC, 0, mmTA_CNTL_AUX), 0xfffffeef, 0x010b0000,
96 SOC15_REG_OFFSET(GC, 0, mmTCP_CHAN_STEER_HI), 0xffffffff, 0x4a2c0e68,
97 SOC15_REG_OFFSET(GC, 0, mmTCP_CHAN_STEER_LO), 0xffffffff, 0xb5d3f197,
98 SOC15_REG_OFFSET(GC, 0, mmVGT_GS_MAX_WAVE_ID), 0x00000fff, 0x000003ff
99};
100
101static const u32 golden_settings_gc_9_0_vg10[] =
102{
103 SOC15_REG_OFFSET(GC, 0, mmCB_HW_CONTROL), 0x0000f000, 0x00012107,
104 SOC15_REG_OFFSET(GC, 0, mmCB_HW_CONTROL_3), 0x30000000, 0x10000000,
105 SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG), 0xffff77ff, 0x2a114042,
106 SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG_READ), 0xffff77ff, 0x2a114042,
107 SOC15_REG_OFFSET(GC, 0, mmPA_SC_ENHANCE_1), 0x00008000, 0x00048000,
108 SOC15_REG_OFFSET(GC, 0, mmRMI_UTCL1_CNTL2), 0x00030000, 0x00020000,
109 SOC15_REG_OFFSET(GC, 0, mmTD_CNTL), 0x00001800, 0x00000800,
110 SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_1),0x0000000f, 0x00000007
111};
112
113#define VEGA10_GB_ADDR_CONFIG_GOLDEN 0x2a114042
114
115static void gfx_v9_0_set_ring_funcs(struct amdgpu_device *adev);
116static void gfx_v9_0_set_irq_funcs(struct amdgpu_device *adev);
117static void gfx_v9_0_set_gds_init(struct amdgpu_device *adev);
118static void gfx_v9_0_set_rlc_funcs(struct amdgpu_device *adev);
119static int gfx_v9_0_get_cu_info(struct amdgpu_device *adev,
120 struct amdgpu_cu_info *cu_info);
121static uint64_t gfx_v9_0_get_gpu_clock_counter(struct amdgpu_device *adev);
122static void gfx_v9_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, u32 sh_num, u32 instance);
123
124static void gfx_v9_0_init_golden_registers(struct amdgpu_device *adev)
125{
126 switch (adev->asic_type) {
127 case CHIP_VEGA10:
128 amdgpu_program_register_sequence(adev,
129 golden_settings_gc_9_0,
130 (const u32)ARRAY_SIZE(golden_settings_gc_9_0));
131 amdgpu_program_register_sequence(adev,
132 golden_settings_gc_9_0_vg10,
133 (const u32)ARRAY_SIZE(golden_settings_gc_9_0_vg10));
134 break;
135 default:
136 break;
137 }
138}
139
140static void gfx_v9_0_scratch_init(struct amdgpu_device *adev)
141{
142 adev->gfx.scratch.num_reg = 7;
143 adev->gfx.scratch.reg_base = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG0);
144 adev->gfx.scratch.free_mask = (1u << adev->gfx.scratch.num_reg) - 1;
145}
146
147static void gfx_v9_0_write_data_to_reg(struct amdgpu_ring *ring, int eng_sel,
148 bool wc, uint32_t reg, uint32_t val)
149{
150 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
151 amdgpu_ring_write(ring, WRITE_DATA_ENGINE_SEL(eng_sel) |
152 WRITE_DATA_DST_SEL(0) |
153 (wc ? WR_CONFIRM : 0));
154 amdgpu_ring_write(ring, reg);
155 amdgpu_ring_write(ring, 0);
156 amdgpu_ring_write(ring, val);
157}
158
159static void gfx_v9_0_wait_reg_mem(struct amdgpu_ring *ring, int eng_sel,
160 int mem_space, int opt, uint32_t addr0,
161 uint32_t addr1, uint32_t ref, uint32_t mask,
162 uint32_t inv)
163{
164 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
165 amdgpu_ring_write(ring,
166 /* memory (1) or register (0) */
167 (WAIT_REG_MEM_MEM_SPACE(mem_space) |
168 WAIT_REG_MEM_OPERATION(opt) | /* wait */
169 WAIT_REG_MEM_FUNCTION(3) | /* equal */
170 WAIT_REG_MEM_ENGINE(eng_sel)));
171
172 if (mem_space)
173 BUG_ON(addr0 & 0x3); /* Dword align */
174 amdgpu_ring_write(ring, addr0);
175 amdgpu_ring_write(ring, addr1);
176 amdgpu_ring_write(ring, ref);
177 amdgpu_ring_write(ring, mask);
178 amdgpu_ring_write(ring, inv); /* poll interval */
179}
180
181static int gfx_v9_0_ring_test_ring(struct amdgpu_ring *ring)
182{
183 struct amdgpu_device *adev = ring->adev;
184 uint32_t scratch;
185 uint32_t tmp = 0;
186 unsigned i;
187 int r;
188
189 r = amdgpu_gfx_scratch_get(adev, &scratch);
190 if (r) {
191 DRM_ERROR("amdgpu: cp failed to get scratch reg (%d).\n", r);
192 return r;
193 }
194 WREG32(scratch, 0xCAFEDEAD);
195 r = amdgpu_ring_alloc(ring, 3);
196 if (r) {
197 DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n",
198 ring->idx, r);
199 amdgpu_gfx_scratch_free(adev, scratch);
200 return r;
201 }
202 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1));
203 amdgpu_ring_write(ring, (scratch - PACKET3_SET_UCONFIG_REG_START));
204 amdgpu_ring_write(ring, 0xDEADBEEF);
205 amdgpu_ring_commit(ring);
206
207 for (i = 0; i < adev->usec_timeout; i++) {
208 tmp = RREG32(scratch);
209 if (tmp == 0xDEADBEEF)
210 break;
211 DRM_UDELAY(1);
212 }
213 if (i < adev->usec_timeout) {
214 DRM_INFO("ring test on %d succeeded in %d usecs\n",
215 ring->idx, i);
216 } else {
217 DRM_ERROR("amdgpu: ring %d test failed (scratch(0x%04X)=0x%08X)\n",
218 ring->idx, scratch, tmp);
219 r = -EINVAL;
220 }
221 amdgpu_gfx_scratch_free(adev, scratch);
222 return r;
223}
224
225static int gfx_v9_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
226{
227 struct amdgpu_device *adev = ring->adev;
228 struct amdgpu_ib ib;
229 struct dma_fence *f = NULL;
230 uint32_t scratch;
231 uint32_t tmp = 0;
232 long r;
233
234 r = amdgpu_gfx_scratch_get(adev, &scratch);
235 if (r) {
236 DRM_ERROR("amdgpu: failed to get scratch reg (%ld).\n", r);
237 return r;
238 }
239 WREG32(scratch, 0xCAFEDEAD);
240 memset(&ib, 0, sizeof(ib));
241 r = amdgpu_ib_get(adev, NULL, 256, &ib);
242 if (r) {
243 DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r);
244 goto err1;
245 }
246 ib.ptr[0] = PACKET3(PACKET3_SET_UCONFIG_REG, 1);
247 ib.ptr[1] = ((scratch - PACKET3_SET_UCONFIG_REG_START));
248 ib.ptr[2] = 0xDEADBEEF;
249 ib.length_dw = 3;
250
251 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
252 if (r)
253 goto err2;
254
255 r = dma_fence_wait_timeout(f, false, timeout);
256 if (r == 0) {
257 DRM_ERROR("amdgpu: IB test timed out.\n");
258 r = -ETIMEDOUT;
259 goto err2;
260 } else if (r < 0) {
261 DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r);
262 goto err2;
263 }
264 tmp = RREG32(scratch);
265 if (tmp == 0xDEADBEEF) {
266 DRM_INFO("ib test on ring %d succeeded\n", ring->idx);
267 r = 0;
268 } else {
269 DRM_ERROR("amdgpu: ib test failed (scratch(0x%04X)=0x%08X)\n",
270 scratch, tmp);
271 r = -EINVAL;
272 }
273err2:
274 amdgpu_ib_free(adev, &ib, NULL);
275 dma_fence_put(f);
276err1:
277 amdgpu_gfx_scratch_free(adev, scratch);
278 return r;
279}
280
281static int gfx_v9_0_init_microcode(struct amdgpu_device *adev)
282{
283 const char *chip_name;
284 char fw_name[30];
285 int err;
286 struct amdgpu_firmware_info *info = NULL;
287 const struct common_firmware_header *header = NULL;
288 const struct gfx_firmware_header_v1_0 *cp_hdr;
289
290 DRM_DEBUG("\n");
291
292 switch (adev->asic_type) {
293 case CHIP_VEGA10:
294 chip_name = "vega10";
295 break;
296 default:
297 BUG();
298 }
299
300 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_pfp.bin", chip_name);
301 err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev);
302 if (err)
303 goto out;
304 err = amdgpu_ucode_validate(adev->gfx.pfp_fw);
305 if (err)
306 goto out;
307 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data;
308 adev->gfx.pfp_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
309 adev->gfx.pfp_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
310
311 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me.bin", chip_name);
312 err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev);
313 if (err)
314 goto out;
315 err = amdgpu_ucode_validate(adev->gfx.me_fw);
316 if (err)
317 goto out;
318 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data;
319 adev->gfx.me_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
320 adev->gfx.me_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
321
322 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ce.bin", chip_name);
323 err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev);
324 if (err)
325 goto out;
326 err = amdgpu_ucode_validate(adev->gfx.ce_fw);
327 if (err)
328 goto out;
329 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data;
330 adev->gfx.ce_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
331 adev->gfx.ce_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
332
333 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", chip_name);
334 err = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev);
335 if (err)
336 goto out;
337 err = amdgpu_ucode_validate(adev->gfx.rlc_fw);
338 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.rlc_fw->data;
339 adev->gfx.rlc_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
340 adev->gfx.rlc_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
341
342 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec.bin", chip_name);
343 err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev);
344 if (err)
345 goto out;
346 err = amdgpu_ucode_validate(adev->gfx.mec_fw);
347 if (err)
348 goto out;
349 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
350 adev->gfx.mec_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
351 adev->gfx.mec_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
352
353
354 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec2.bin", chip_name);
355 err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev);
356 if (!err) {
357 err = amdgpu_ucode_validate(adev->gfx.mec2_fw);
358 if (err)
359 goto out;
360 cp_hdr = (const struct gfx_firmware_header_v1_0 *)
361 adev->gfx.mec2_fw->data;
362 adev->gfx.mec2_fw_version =
363 le32_to_cpu(cp_hdr->header.ucode_version);
364 adev->gfx.mec2_feature_version =
365 le32_to_cpu(cp_hdr->ucode_feature_version);
366 } else {
367 err = 0;
368 adev->gfx.mec2_fw = NULL;
369 }
370
371 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
372 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_PFP];
373 info->ucode_id = AMDGPU_UCODE_ID_CP_PFP;
374 info->fw = adev->gfx.pfp_fw;
375 header = (const struct common_firmware_header *)info->fw->data;
376 adev->firmware.fw_size +=
377 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
378
379 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_ME];
380 info->ucode_id = AMDGPU_UCODE_ID_CP_ME;
381 info->fw = adev->gfx.me_fw;
382 header = (const struct common_firmware_header *)info->fw->data;
383 adev->firmware.fw_size +=
384 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
385
386 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_CE];
387 info->ucode_id = AMDGPU_UCODE_ID_CP_CE;
388 info->fw = adev->gfx.ce_fw;
389 header = (const struct common_firmware_header *)info->fw->data;
390 adev->firmware.fw_size +=
391 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
392
393 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_G];
394 info->ucode_id = AMDGPU_UCODE_ID_RLC_G;
395 info->fw = adev->gfx.rlc_fw;
396 header = (const struct common_firmware_header *)info->fw->data;
397 adev->firmware.fw_size +=
398 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
399
400 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1];
401 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC1;
402 info->fw = adev->gfx.mec_fw;
403 header = (const struct common_firmware_header *)info->fw->data;
404 cp_hdr = (const struct gfx_firmware_header_v1_0 *)info->fw->data;
405 adev->firmware.fw_size +=
406 ALIGN(le32_to_cpu(header->ucode_size_bytes) - le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE);
407
408 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1_JT];
409 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC1_JT;
410 info->fw = adev->gfx.mec_fw;
411 adev->firmware.fw_size +=
412 ALIGN(le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE);
413
414 if (adev->gfx.mec2_fw) {
415 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC2];
416 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC2;
417 info->fw = adev->gfx.mec2_fw;
418 header = (const struct common_firmware_header *)info->fw->data;
419 cp_hdr = (const struct gfx_firmware_header_v1_0 *)info->fw->data;
420 adev->firmware.fw_size +=
421 ALIGN(le32_to_cpu(header->ucode_size_bytes) - le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE);
422 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC2_JT];
423 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC2_JT;
424 info->fw = adev->gfx.mec2_fw;
425 adev->firmware.fw_size +=
426 ALIGN(le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE);
427 }
428
429 }
430
431out:
432 if (err) {
433 dev_err(adev->dev,
434 "gfx9: Failed to load firmware \"%s\"\n",
435 fw_name);
436 release_firmware(adev->gfx.pfp_fw);
437 adev->gfx.pfp_fw = NULL;
438 release_firmware(adev->gfx.me_fw);
439 adev->gfx.me_fw = NULL;
440 release_firmware(adev->gfx.ce_fw);
441 adev->gfx.ce_fw = NULL;
442 release_firmware(adev->gfx.rlc_fw);
443 adev->gfx.rlc_fw = NULL;
444 release_firmware(adev->gfx.mec_fw);
445 adev->gfx.mec_fw = NULL;
446 release_firmware(adev->gfx.mec2_fw);
447 adev->gfx.mec2_fw = NULL;
448 }
449 return err;
450}
451
452static void gfx_v9_0_mec_fini(struct amdgpu_device *adev)
453{
454 int r;
455
456 if (adev->gfx.mec.hpd_eop_obj) {
457 r = amdgpu_bo_reserve(adev->gfx.mec.hpd_eop_obj, false);
458 if (unlikely(r != 0))
459 dev_warn(adev->dev, "(%d) reserve HPD EOP bo failed\n", r);
460 amdgpu_bo_unpin(adev->gfx.mec.hpd_eop_obj);
461 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj);
462
463 amdgpu_bo_unref(&adev->gfx.mec.hpd_eop_obj);
464 adev->gfx.mec.hpd_eop_obj = NULL;
465 }
466 if (adev->gfx.mec.mec_fw_obj) {
467 r = amdgpu_bo_reserve(adev->gfx.mec.mec_fw_obj, false);
468 if (unlikely(r != 0))
469 dev_warn(adev->dev, "(%d) reserve mec firmware bo failed\n", r);
470 amdgpu_bo_unpin(adev->gfx.mec.mec_fw_obj);
471 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj);
472
473 amdgpu_bo_unref(&adev->gfx.mec.mec_fw_obj);
474 adev->gfx.mec.mec_fw_obj = NULL;
475 }
476}
477
478#define MEC_HPD_SIZE 2048
479
480static int gfx_v9_0_mec_init(struct amdgpu_device *adev)
481{
482 int r;
483 u32 *hpd;
484 const __le32 *fw_data;
485 unsigned fw_size;
486 u32 *fw;
487
488 const struct gfx_firmware_header_v1_0 *mec_hdr;
489
490 /*
491 * we assign only 1 pipe because all other pipes will
492 * be handled by KFD
493 */
494 adev->gfx.mec.num_mec = 1;
495 adev->gfx.mec.num_pipe = 1;
496 adev->gfx.mec.num_queue = adev->gfx.mec.num_mec * adev->gfx.mec.num_pipe * 8;
497
498 if (adev->gfx.mec.hpd_eop_obj == NULL) {
499 r = amdgpu_bo_create(adev,
500 adev->gfx.mec.num_queue * MEC_HPD_SIZE,
501 PAGE_SIZE, true,
502 AMDGPU_GEM_DOMAIN_GTT, 0, NULL, NULL,
503 &adev->gfx.mec.hpd_eop_obj);
504 if (r) {
505 dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r);
506 return r;
507 }
508 }
509
510 r = amdgpu_bo_reserve(adev->gfx.mec.hpd_eop_obj, false);
511 if (unlikely(r != 0)) {
512 gfx_v9_0_mec_fini(adev);
513 return r;
514 }
515 r = amdgpu_bo_pin(adev->gfx.mec.hpd_eop_obj, AMDGPU_GEM_DOMAIN_GTT,
516 &adev->gfx.mec.hpd_eop_gpu_addr);
517 if (r) {
518 dev_warn(adev->dev, "(%d) pin HDP EOP bo failed\n", r);
519 gfx_v9_0_mec_fini(adev);
520 return r;
521 }
522 r = amdgpu_bo_kmap(adev->gfx.mec.hpd_eop_obj, (void **)&hpd);
523 if (r) {
524 dev_warn(adev->dev, "(%d) map HDP EOP bo failed\n", r);
525 gfx_v9_0_mec_fini(adev);
526 return r;
527 }
528
529 memset(hpd, 0, adev->gfx.mec.hpd_eop_obj->tbo.mem.size);
530
531 amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj);
532 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj);
533
534 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
535
536 fw_data = (const __le32 *)
537 (adev->gfx.mec_fw->data +
538 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes));
539 fw_size = le32_to_cpu(mec_hdr->header.ucode_size_bytes) / 4;
540
541 if (adev->gfx.mec.mec_fw_obj == NULL) {
542 r = amdgpu_bo_create(adev,
543 mec_hdr->header.ucode_size_bytes,
544 PAGE_SIZE, true,
545 AMDGPU_GEM_DOMAIN_GTT, 0, NULL, NULL,
546 &adev->gfx.mec.mec_fw_obj);
547 if (r) {
548 dev_warn(adev->dev, "(%d) create mec firmware bo failed\n", r);
549 return r;
550 }
551 }
552
553 r = amdgpu_bo_reserve(adev->gfx.mec.mec_fw_obj, false);
554 if (unlikely(r != 0)) {
555 gfx_v9_0_mec_fini(adev);
556 return r;
557 }
558 r = amdgpu_bo_pin(adev->gfx.mec.mec_fw_obj, AMDGPU_GEM_DOMAIN_GTT,
559 &adev->gfx.mec.mec_fw_gpu_addr);
560 if (r) {
561 dev_warn(adev->dev, "(%d) pin mec firmware bo failed\n", r);
562 gfx_v9_0_mec_fini(adev);
563 return r;
564 }
565 r = amdgpu_bo_kmap(adev->gfx.mec.mec_fw_obj, (void **)&fw);
566 if (r) {
567 dev_warn(adev->dev, "(%d) map firmware bo failed\n", r);
568 gfx_v9_0_mec_fini(adev);
569 return r;
570 }
571 memcpy(fw, fw_data, fw_size);
572
573 amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj);
574 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj);
575
576
577 return 0;
578}
579
ac104e99
XY		 580static void gfx_v9_0_kiq_fini(struct amdgpu_device *adev)
581{
582 struct amdgpu_kiq *kiq = &adev->gfx.kiq;
583
584 amdgpu_bo_free_kernel(&kiq->eop_obj, &kiq->eop_gpu_addr, NULL);
585}
586
587static int gfx_v9_0_kiq_init(struct amdgpu_device *adev)
588{
589 int r;
590 u32 *hpd;
591 struct amdgpu_kiq *kiq = &adev->gfx.kiq;
592
593 r = amdgpu_bo_create_kernel(adev, MEC_HPD_SIZE, PAGE_SIZE,
594 AMDGPU_GEM_DOMAIN_GTT, &kiq->eop_obj,
595 &kiq->eop_gpu_addr, (void **)&hpd);
596 if (r) {
597 dev_warn(adev->dev, "failed to create KIQ bo (%d).\n", r);
598 return r;
599 }
600
601 memset(hpd, 0, MEC_HPD_SIZE);
602
603 amdgpu_bo_kunmap(kiq->eop_obj);
604
605 return 0;
606}
607
608static int gfx_v9_0_kiq_init_ring(struct amdgpu_device *adev,
609 struct amdgpu_ring *ring,
610 struct amdgpu_irq_src *irq)
611{
612 int r = 0;
613
614 r = amdgpu_wb_get(adev, &adev->virt.reg_val_offs);
615 if (r)
616 return r;
617
618 ring->adev = NULL;
619 ring->ring_obj = NULL;
620 ring->use_doorbell = true;
621 ring->doorbell_index = AMDGPU_DOORBELL_KIQ;
622 if (adev->gfx.mec2_fw) {
623 ring->me = 2;
624 ring->pipe = 0;
625 } else {
626 ring->me = 1;
627 ring->pipe = 1;
628 }
629
630 irq->data = ring;
631 ring->queue = 0;
632 sprintf(ring->name, "kiq %d.%d.%d", ring->me, ring->pipe, ring->queue);
633 r = amdgpu_ring_init(adev, ring, 1024,
634 irq, AMDGPU_CP_KIQ_IRQ_DRIVER0);
635 if (r)
636 dev_warn(adev->dev, "(%d) failed to init kiq ring\n", r);
637
638 return r;
639}
640static void gfx_v9_0_kiq_free_ring(struct amdgpu_ring *ring,
641 struct amdgpu_irq_src *irq)
642{
643 amdgpu_wb_free(ring->adev, ring->adev->virt.reg_val_offs);
644 amdgpu_ring_fini(ring);
645 irq->data = NULL;
646}
647
b1023571
KW		 648static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t address)
649{
650 WREG32(SOC15_REG_OFFSET(GC, 0, mmSQ_IND_INDEX),
651 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
652 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) |
653 (address << SQ_IND_INDEX__INDEX__SHIFT) |
654 (SQ_IND_INDEX__FORCE_READ_MASK));
655 return RREG32(SOC15_REG_OFFSET(GC, 0, mmSQ_IND_DATA));
656}
657
658static void wave_read_regs(struct amdgpu_device *adev, uint32_t simd,
659 uint32_t wave, uint32_t thread,
660 uint32_t regno, uint32_t num, uint32_t *out)
661{
662 WREG32(SOC15_REG_OFFSET(GC, 0, mmSQ_IND_INDEX),
663 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
664 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) |
665 (regno << SQ_IND_INDEX__INDEX__SHIFT) |
666 (thread << SQ_IND_INDEX__THREAD_ID__SHIFT) |
667 (SQ_IND_INDEX__FORCE_READ_MASK) |
668 (SQ_IND_INDEX__AUTO_INCR_MASK));
669 while (num--)
670 *(out++) = RREG32(SOC15_REG_OFFSET(GC, 0, mmSQ_IND_DATA));
671}
672
673static void gfx_v9_0_read_wave_data(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields)
674{
675 /* type 1 wave data */
676 dst[(*no_fields)++] = 1;
677 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_STATUS);
678 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_LO);
679 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_HI);
680 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_LO);
681 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_HI);
682 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_HW_ID);
683 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW0);
684 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW1);
685 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_GPR_ALLOC);
686 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_LDS_ALLOC);
687 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TRAPSTS);
688 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_STS);
689 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_DBG0);
690 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_M0);
691}
692
693static void gfx_v9_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t simd,
694 uint32_t wave, uint32_t start,
695 uint32_t size, uint32_t *dst)
696{
697 wave_read_regs(
698 adev, simd, wave, 0,
699 start + SQIND_WAVE_SGPRS_OFFSET, size, dst);
700}
701
702
703static const struct amdgpu_gfx_funcs gfx_v9_0_gfx_funcs = {
704 .get_gpu_clock_counter = &gfx_v9_0_get_gpu_clock_counter,
705 .select_se_sh = &gfx_v9_0_select_se_sh,
706 .read_wave_data = &gfx_v9_0_read_wave_data,
707 .read_wave_sgprs = &gfx_v9_0_read_wave_sgprs,
708};
709
710static void gfx_v9_0_gpu_early_init(struct amdgpu_device *adev)
711{
712 u32 gb_addr_config;
713
714 adev->gfx.funcs = &gfx_v9_0_gfx_funcs;
715
716 switch (adev->asic_type) {
717 case CHIP_VEGA10:
718 adev->gfx.config.max_shader_engines = 4;
719 adev->gfx.config.max_tile_pipes = 8; //??
720 adev->gfx.config.max_cu_per_sh = 16;
721 adev->gfx.config.max_sh_per_se = 1;
722 adev->gfx.config.max_backends_per_se = 4;
723 adev->gfx.config.max_texture_channel_caches = 16;
724 adev->gfx.config.max_gprs = 256;
725 adev->gfx.config.max_gs_threads = 32;
726 adev->gfx.config.max_hw_contexts = 8;
727
728 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
729 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
730 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
731 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
732 gb_addr_config = VEGA10_GB_ADDR_CONFIG_GOLDEN;
733 break;
734 default:
735 BUG();
736 break;
737 }
738
739 adev->gfx.config.gb_addr_config = gb_addr_config;
740
741 adev->gfx.config.gb_addr_config_fields.num_pipes = 1 <<
742 REG_GET_FIELD(
743 adev->gfx.config.gb_addr_config,
744 GB_ADDR_CONFIG,
745 NUM_PIPES);
746 adev->gfx.config.gb_addr_config_fields.num_banks = 1 <<
747 REG_GET_FIELD(
748 adev->gfx.config.gb_addr_config,
749 GB_ADDR_CONFIG,
750 NUM_BANKS);
751 adev->gfx.config.gb_addr_config_fields.max_compress_frags = 1 <<
752 REG_GET_FIELD(
753 adev->gfx.config.gb_addr_config,
754 GB_ADDR_CONFIG,
755 MAX_COMPRESSED_FRAGS);
756 adev->gfx.config.gb_addr_config_fields.num_rb_per_se = 1 <<
757 REG_GET_FIELD(
758 adev->gfx.config.gb_addr_config,
759 GB_ADDR_CONFIG,
760 NUM_RB_PER_SE);
761 adev->gfx.config.gb_addr_config_fields.num_se = 1 <<
762 REG_GET_FIELD(
763 adev->gfx.config.gb_addr_config,
764 GB_ADDR_CONFIG,
765 NUM_SHADER_ENGINES);
766 adev->gfx.config.gb_addr_config_fields.pipe_interleave_size = 1 << (8 +
767 REG_GET_FIELD(
768 adev->gfx.config.gb_addr_config,
769 GB_ADDR_CONFIG,
770 PIPE_INTERLEAVE_SIZE));
771}
772
773static int gfx_v9_0_ngg_create_buf(struct amdgpu_device *adev,
774 struct amdgpu_ngg_buf *ngg_buf,
775 int size_se,
776 int default_size_se)
777{
778 int r;
779
780 if (size_se < 0) {
781 dev_err(adev->dev, "Buffer size is invalid: %d\n", size_se);
782 return -EINVAL;
783 }
784 size_se = size_se ? size_se : default_size_se;
785
786 ngg_buf->size = size_se * GFX9_NUM_SE;
787 r = amdgpu_bo_create_kernel(adev, ngg_buf->size,
788 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM,
789 &ngg_buf->bo,
790 &ngg_buf->gpu_addr,
791 NULL);
792 if (r) {
793 dev_err(adev->dev, "(%d) failed to create NGG buffer\n", r);
794 return r;
795 }
796 ngg_buf->bo_size = amdgpu_bo_size(ngg_buf->bo);
797
798 return r;
799}
800
801static int gfx_v9_0_ngg_fini(struct amdgpu_device *adev)
802{
803 int i;
804
805 for (i = 0; i < NGG_BUF_MAX; i++)
806 amdgpu_bo_free_kernel(&adev->gfx.ngg.buf[i].bo,
807 &adev->gfx.ngg.buf[i].gpu_addr,
808 NULL);
809
810 memset(&adev->gfx.ngg.buf[0], 0,
811 sizeof(struct amdgpu_ngg_buf) * NGG_BUF_MAX);
812
813 adev->gfx.ngg.init = false;
814
815 return 0;
816}
817
818static int gfx_v9_0_ngg_init(struct amdgpu_device *adev)
819{
820 int r;
821
822 if (!amdgpu_ngg || adev->gfx.ngg.init == true)
823 return 0;
824
825 /* GDS reserve memory: 64 bytes alignment */
826 adev->gfx.ngg.gds_reserve_size = ALIGN(5 * 4, 0x40);
827 adev->gds.mem.total_size -= adev->gfx.ngg.gds_reserve_size;
828 adev->gds.mem.gfx_partition_size -= adev->gfx.ngg.gds_reserve_size;
829 adev->gfx.ngg.gds_reserve_addr = amdgpu_gds_reg_offset[0].mem_base;
830 adev->gfx.ngg.gds_reserve_addr += adev->gds.mem.gfx_partition_size;
831
832 /* Primitive Buffer */
833 r = gfx_v9_0_ngg_create_buf(adev, &adev->gfx.ngg.buf[PRIM],
834 amdgpu_prim_buf_per_se,
835 64 * 1024);
836 if (r) {
837 dev_err(adev->dev, "Failed to create Primitive Buffer\n");
838 goto err;
839 }
840
841 /* Position Buffer */
842 r = gfx_v9_0_ngg_create_buf(adev, &adev->gfx.ngg.buf[POS],
843 amdgpu_pos_buf_per_se,
844 256 * 1024);
845 if (r) {
846 dev_err(adev->dev, "Failed to create Position Buffer\n");
847 goto err;
848 }
849
850 /* Control Sideband */
851 r = gfx_v9_0_ngg_create_buf(adev, &adev->gfx.ngg.buf[CNTL],
852 amdgpu_cntl_sb_buf_per_se,
853 256);
854 if (r) {
855 dev_err(adev->dev, "Failed to create Control Sideband Buffer\n");
856 goto err;
857 }
858
859 /* Parameter Cache, not created by default */
860 if (amdgpu_param_buf_per_se <= 0)
861 goto out;
862
863 r = gfx_v9_0_ngg_create_buf(adev, &adev->gfx.ngg.buf[PARAM],
864 amdgpu_param_buf_per_se,
865 512 * 1024);
866 if (r) {
867 dev_err(adev->dev, "Failed to create Parameter Cache\n");
868 goto err;
869 }
870
871out:
872 adev->gfx.ngg.init = true;
873 return 0;
874err:
875 gfx_v9_0_ngg_fini(adev);
876 return r;
877}
878
879static int gfx_v9_0_ngg_en(struct amdgpu_device *adev)
880{
881 struct amdgpu_ring *ring = &adev->gfx.gfx_ring[0];
882 int r;
883 u32 data;
884 u32 size;
885 u32 base;
886
887 if (!amdgpu_ngg)
888 return 0;
889
890 /* Program buffer size */
891 data = 0;
892 size = adev->gfx.ngg.buf[PRIM].size / 256;
893 data = REG_SET_FIELD(data, WD_BUF_RESOURCE_1, INDEX_BUF_SIZE, size);
894
895 size = adev->gfx.ngg.buf[POS].size / 256;
896 data = REG_SET_FIELD(data, WD_BUF_RESOURCE_1, POS_BUF_SIZE, size);
897
898 WREG32(SOC15_REG_OFFSET(GC, 0, mmWD_BUF_RESOURCE_1), data);
899
900 data = 0;
901 size = adev->gfx.ngg.buf[CNTL].size / 256;
902 data = REG_SET_FIELD(data, WD_BUF_RESOURCE_2, CNTL_SB_BUF_SIZE, size);
903
904 size = adev->gfx.ngg.buf[PARAM].size / 1024;
905 data = REG_SET_FIELD(data, WD_BUF_RESOURCE_2, PARAM_BUF_SIZE, size);
906
907 WREG32(SOC15_REG_OFFSET(GC, 0, mmWD_BUF_RESOURCE_2), data);
908
909 /* Program buffer base address */
910 base = lower_32_bits(adev->gfx.ngg.buf[PRIM].gpu_addr);
911 data = REG_SET_FIELD(0, WD_INDEX_BUF_BASE, BASE, base);
912 WREG32(SOC15_REG_OFFSET(GC, 0, mmWD_INDEX_BUF_BASE), data);
913
914 base = upper_32_bits(adev->gfx.ngg.buf[PRIM].gpu_addr);
915 data = REG_SET_FIELD(0, WD_INDEX_BUF_BASE_HI, BASE_HI, base);
916 WREG32(SOC15_REG_OFFSET(GC, 0, mmWD_INDEX_BUF_BASE_HI), data);
917
918 base = lower_32_bits(adev->gfx.ngg.buf[POS].gpu_addr);
919 data = REG_SET_FIELD(0, WD_POS_BUF_BASE, BASE, base);
920 WREG32(SOC15_REG_OFFSET(GC, 0, mmWD_POS_BUF_BASE), data);
921
922 base = upper_32_bits(adev->gfx.ngg.buf[POS].gpu_addr);
923 data = REG_SET_FIELD(0, WD_POS_BUF_BASE_HI, BASE_HI, base);
924 WREG32(SOC15_REG_OFFSET(GC, 0, mmWD_POS_BUF_BASE_HI), data);
925
926 base = lower_32_bits(adev->gfx.ngg.buf[CNTL].gpu_addr);
927 data = REG_SET_FIELD(0, WD_CNTL_SB_BUF_BASE, BASE, base);
928 WREG32(SOC15_REG_OFFSET(GC, 0, mmWD_CNTL_SB_BUF_BASE), data);
929
930 base = upper_32_bits(adev->gfx.ngg.buf[CNTL].gpu_addr);
931 data = REG_SET_FIELD(0, WD_CNTL_SB_BUF_BASE_HI, BASE_HI, base);
932 WREG32(SOC15_REG_OFFSET(GC, 0, mmWD_CNTL_SB_BUF_BASE_HI), data);
933
934 /* Clear GDS reserved memory */
935 r = amdgpu_ring_alloc(ring, 17);
936 if (r) {
937 DRM_ERROR("amdgpu: NGG failed to lock ring %d (%d).\n",
938 ring->idx, r);
939 return r;
940 }
941
942 gfx_v9_0_write_data_to_reg(ring, 0, false,
943 amdgpu_gds_reg_offset[0].mem_size,
944 (adev->gds.mem.total_size +
945 adev->gfx.ngg.gds_reserve_size) >>
946 AMDGPU_GDS_SHIFT);
947
948 amdgpu_ring_write(ring, PACKET3(PACKET3_DMA_DATA, 5));
949 amdgpu_ring_write(ring, (PACKET3_DMA_DATA_CP_SYNC |
950 PACKET3_DMA_DATA_SRC_SEL(2)));
951 amdgpu_ring_write(ring, 0);
952 amdgpu_ring_write(ring, 0);
953 amdgpu_ring_write(ring, adev->gfx.ngg.gds_reserve_addr);
954 amdgpu_ring_write(ring, 0);
955 amdgpu_ring_write(ring, adev->gfx.ngg.gds_reserve_size);
956
957
958 gfx_v9_0_write_data_to_reg(ring, 0, false,
959 amdgpu_gds_reg_offset[0].mem_size, 0);
960
961 amdgpu_ring_commit(ring);
962
963 return 0;
964}
965
966static int gfx_v9_0_sw_init(void *handle)
967{
968 int i, r;
969 struct amdgpu_ring *ring;
ac104e99 970 struct amdgpu_kiq *kiq;
b1023571
KW		 971 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
972
97031e25
XY		 973 /* KIQ event */
974 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_GRBM_CP, 178, &adev->gfx.kiq.irq);
975 if (r)
976 return r;
977
b1023571
KW		 978 /* EOP Event */
979 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_GRBM_CP, 181, &adev->gfx.eop_irq);
980 if (r)
981 return r;
982
983 /* Privileged reg */
984 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_GRBM_CP, 184,
985 &adev->gfx.priv_reg_irq);
986 if (r)
987 return r;
988
989 /* Privileged inst */
990 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_GRBM_CP, 185,
991 &adev->gfx.priv_inst_irq);
992 if (r)
993 return r;
994
995 adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE;
996
997 gfx_v9_0_scratch_init(adev);
998
999 r = gfx_v9_0_init_microcode(adev);
1000 if (r) {
1001 DRM_ERROR("Failed to load gfx firmware!\n");
1002 return r;
1003 }
1004
1005 r = gfx_v9_0_mec_init(adev);
1006 if (r) {
1007 DRM_ERROR("Failed to init MEC BOs!\n");
1008 return r;
1009 }
1010
1011 /* set up the gfx ring */
1012 for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
1013 ring = &adev->gfx.gfx_ring[i];
1014 ring->ring_obj = NULL;
1015 sprintf(ring->name, "gfx");
1016 ring->use_doorbell = true;
1017 ring->doorbell_index = AMDGPU_DOORBELL64_GFX_RING0 << 1;
1018 r = amdgpu_ring_init(adev, ring, 1024,
1019 &adev->gfx.eop_irq, AMDGPU_CP_IRQ_GFX_EOP);
1020 if (r)
1021 return r;
1022 }
1023
1024 /* set up the compute queues */
1025 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
1026 unsigned irq_type;
1027
1028 /* max 32 queues per MEC */
1029 if ((i >= 32) || (i >= AMDGPU_MAX_COMPUTE_RINGS)) {
1030 DRM_ERROR("Too many (%d) compute rings!\n", i);
1031 break;
1032 }
1033 ring = &adev->gfx.compute_ring[i];
1034 ring->ring_obj = NULL;
1035 ring->use_doorbell = true;
1036 ring->doorbell_index = (AMDGPU_DOORBELL64_MEC_RING0 + i) << 1;
1037 ring->me = 1; /* first MEC */
1038 ring->pipe = i / 8;
1039 ring->queue = i % 8;
1040 sprintf(ring->name, "comp %d.%d.%d", ring->me, ring->pipe, ring->queue);
1041 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP + ring->pipe;
1042 /* type-2 packets are deprecated on MEC, use type-3 instead */
1043 r = amdgpu_ring_init(adev, ring, 1024,
1044 &adev->gfx.eop_irq, irq_type);
1045 if (r)
1046 return r;
1047 }
1048
ac104e99
XY		 1049 if (amdgpu_sriov_vf(adev)) {
1050 r = gfx_v9_0_kiq_init(adev);
1051 if (r) {
1052 DRM_ERROR("Failed to init KIQ BOs!\n");
1053 return r;
1054 }
1055
1056 kiq = &adev->gfx.kiq;
1057 r = gfx_v9_0_kiq_init_ring(adev, &kiq->ring, &kiq->irq);
1058 if (r)
1059 return r;
1060 }
1061
b1023571
KW		 1062 /* reserve GDS, GWS and OA resource for gfx */
1063 r = amdgpu_bo_create_kernel(adev, adev->gds.mem.gfx_partition_size,
1064 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GDS,
1065 &adev->gds.gds_gfx_bo, NULL, NULL);
1066 if (r)
1067 return r;
1068
1069 r = amdgpu_bo_create_kernel(adev, adev->gds.gws.gfx_partition_size,
1070 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GWS,
1071 &adev->gds.gws_gfx_bo, NULL, NULL);
1072 if (r)
1073 return r;
1074
1075 r = amdgpu_bo_create_kernel(adev, adev->gds.oa.gfx_partition_size,
1076 PAGE_SIZE, AMDGPU_GEM_DOMAIN_OA,
1077 &adev->gds.oa_gfx_bo, NULL, NULL);
1078 if (r)
1079 return r;
1080
1081 adev->gfx.ce_ram_size = 0x8000;
1082
1083 gfx_v9_0_gpu_early_init(adev);
1084
1085 r = gfx_v9_0_ngg_init(adev);
1086 if (r)
1087 return r;
1088
1089 return 0;
1090}
1091
1092
1093static int gfx_v9_0_sw_fini(void *handle)
1094{
1095 int i;
1096 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1097
1098 amdgpu_bo_free_kernel(&adev->gds.oa_gfx_bo, NULL, NULL);
1099 amdgpu_bo_free_kernel(&adev->gds.gws_gfx_bo, NULL, NULL);
1100 amdgpu_bo_free_kernel(&adev->gds.gds_gfx_bo, NULL, NULL);
1101
1102 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
1103 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]);
1104 for (i = 0; i < adev->gfx.num_compute_rings; i++)
1105 amdgpu_ring_fini(&adev->gfx.compute_ring[i]);
1106
ac104e99
XY		 1107 if (amdgpu_sriov_vf(adev)) {
1108 gfx_v9_0_kiq_free_ring(&adev->gfx.kiq.ring, &adev->gfx.kiq.irq);
1109 gfx_v9_0_kiq_fini(adev);
1110 }
1111
b1023571
KW		 1112 gfx_v9_0_mec_fini(adev);
1113 gfx_v9_0_ngg_fini(adev);
1114
1115 return 0;
1116}
1117
1118
1119static void gfx_v9_0_tiling_mode_table_init(struct amdgpu_device *adev)
1120{
1121 /* TODO */
1122}
1123
1124static void gfx_v9_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, u32 sh_num, u32 instance)
1125{
1126 u32 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES, 1);
1127
1128 if ((se_num == 0xffffffff) && (sh_num == 0xffffffff)) {
1129 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_BROADCAST_WRITES, 1);
1130 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES, 1);
1131 } else if (se_num == 0xffffffff) {
1132 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_INDEX, sh_num);
1133 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES, 1);
1134 } else if (sh_num == 0xffffffff) {
1135 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_BROADCAST_WRITES, 1);
1136 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num);
1137 } else {
1138 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_INDEX, sh_num);
1139 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num);
1140 }
1141 WREG32( SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_INDEX), data);
1142}
1143
1144static u32 gfx_v9_0_create_bitmask(u32 bit_width)
1145{
1146 return (u32)((1ULL << bit_width) - 1);
1147}
1148
1149static u32 gfx_v9_0_get_rb_active_bitmap(struct amdgpu_device *adev)
1150{
1151 u32 data, mask;
1152
1153 data = RREG32(SOC15_REG_OFFSET(GC, 0, mmCC_RB_BACKEND_DISABLE));
1154 data |= RREG32(SOC15_REG_OFFSET(GC, 0, mmGC_USER_RB_BACKEND_DISABLE));
1155
1156 data &= CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK;
1157 data >>= GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT;
1158
1159 mask = gfx_v9_0_create_bitmask(adev->gfx.config.max_backends_per_se /
1160 adev->gfx.config.max_sh_per_se);
1161
1162 return (~data) & mask;
1163}
1164
1165static void gfx_v9_0_setup_rb(struct amdgpu_device *adev)
1166{
1167 int i, j;
1168 u32 data, tmp, num_rbs = 0;
1169 u32 active_rbs = 0;
1170 u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se /
1171 adev->gfx.config.max_sh_per_se;
1172
1173 mutex_lock(&adev->grbm_idx_mutex);
1174 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
1175 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
1176 gfx_v9_0_select_se_sh(adev, i, j, 0xffffffff);
1177 data = gfx_v9_0_get_rb_active_bitmap(adev);
1178 active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) *
1179 rb_bitmap_width_per_sh);
1180 }
1181 }
1182 gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
1183 mutex_unlock(&adev->grbm_idx_mutex);
1184
1185 adev->gfx.config.backend_enable_mask = active_rbs;
1186 tmp = active_rbs;
1187 while (tmp >>= 1)
1188 num_rbs++;
1189 adev->gfx.config.num_rbs = num_rbs;
1190}
1191
1192#define DEFAULT_SH_MEM_BASES (0x6000)
1193#define FIRST_COMPUTE_VMID (8)
1194#define LAST_COMPUTE_VMID (16)
1195static void gfx_v9_0_init_compute_vmid(struct amdgpu_device *adev)
1196{
1197 int i;
1198 uint32_t sh_mem_config;
1199 uint32_t sh_mem_bases;
1200
1201 /*
1202 * Configure apertures:
1203 * LDS: 0x60000000'00000000 - 0x60000001'00000000 (4GB)
1204 * Scratch: 0x60000001'00000000 - 0x60000002'00000000 (4GB)
1205 * GPUVM: 0x60010000'00000000 - 0x60020000'00000000 (1TB)
1206 */
1207 sh_mem_bases = DEFAULT_SH_MEM_BASES | (DEFAULT_SH_MEM_BASES << 16);
1208
1209 sh_mem_config = SH_MEM_ADDRESS_MODE_64 |
1210 SH_MEM_ALIGNMENT_MODE_UNALIGNED <<
1211 SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT;
1212
1213 mutex_lock(&adev->srbm_mutex);
1214 for (i = FIRST_COMPUTE_VMID; i < LAST_COMPUTE_VMID; i++) {
1215 soc15_grbm_select(adev, 0, 0, 0, i);
1216 /* CP and shaders */
1217 WREG32(SOC15_REG_OFFSET(GC, 0, mmSH_MEM_CONFIG), sh_mem_config);
1218 WREG32(SOC15_REG_OFFSET(GC, 0, mmSH_MEM_BASES), sh_mem_bases);
1219 }
1220 soc15_grbm_select(adev, 0, 0, 0, 0);
1221 mutex_unlock(&adev->srbm_mutex);
1222}
1223
1224static void gfx_v9_0_gpu_init(struct amdgpu_device *adev)
1225{
1226 u32 tmp;
1227 int i;
1228
1229 tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmGRBM_CNTL));
1230 tmp = REG_SET_FIELD(tmp, GRBM_CNTL, READ_TIMEOUT, 0xff);
1231 WREG32(SOC15_REG_OFFSET(GC, 0, mmGRBM_CNTL), tmp);
1232
1233 gfx_v9_0_tiling_mode_table_init(adev);
1234
1235 gfx_v9_0_setup_rb(adev);
1236 gfx_v9_0_get_cu_info(adev, &adev->gfx.cu_info);
1237
1238 /* XXX SH_MEM regs */
1239 /* where to put LDS, scratch, GPUVM in FSA64 space */
1240 mutex_lock(&adev->srbm_mutex);
1241 for (i = 0; i < 16; i++) {
1242 soc15_grbm_select(adev, 0, 0, 0, i);
1243 /* CP and shaders */
1244 tmp = 0;
1245 tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, ALIGNMENT_MODE,
1246 SH_MEM_ALIGNMENT_MODE_UNALIGNED);
1247 WREG32(SOC15_REG_OFFSET(GC, 0, mmSH_MEM_CONFIG), tmp);
1248 WREG32(SOC15_REG_OFFSET(GC, 0, mmSH_MEM_BASES), 0);
1249 }
1250 soc15_grbm_select(adev, 0, 0, 0, 0);
1251
1252 mutex_unlock(&adev->srbm_mutex);
1253
1254 gfx_v9_0_init_compute_vmid(adev);
1255
1256 mutex_lock(&adev->grbm_idx_mutex);
1257 /*
1258 * making sure that the following register writes will be broadcasted
1259 * to all the shaders
1260 */
1261 gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
1262
1263 WREG32(SOC15_REG_OFFSET(GC, 0, mmPA_SC_FIFO_SIZE),
1264 (adev->gfx.config.sc_prim_fifo_size_frontend <<
1265 PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE__SHIFT) |
1266 (adev->gfx.config.sc_prim_fifo_size_backend <<
1267 PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE__SHIFT) |
1268 (adev->gfx.config.sc_hiz_tile_fifo_size <<
1269 PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE__SHIFT) |
1270 (adev->gfx.config.sc_earlyz_tile_fifo_size <<
1271 PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE__SHIFT));
1272 mutex_unlock(&adev->grbm_idx_mutex);
1273
1274}
1275
1276static void gfx_v9_0_wait_for_rlc_serdes(struct amdgpu_device *adev)
1277{
1278 u32 i, j, k;
1279 u32 mask;
1280
1281 mutex_lock(&adev->grbm_idx_mutex);
1282 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
1283 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
1284 gfx_v9_0_select_se_sh(adev, i, j, 0xffffffff);
1285 for (k = 0; k < adev->usec_timeout; k++) {
1286 if (RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SERDES_CU_MASTER_BUSY)) == 0)
1287 break;
1288 udelay(1);
1289 }
1290 }
1291 }
1292 gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
1293 mutex_unlock(&adev->grbm_idx_mutex);
1294
1295 mask = RLC_SERDES_NONCU_MASTER_BUSY__SE_MASTER_BUSY_MASK |
1296 RLC_SERDES_NONCU_MASTER_BUSY__GC_MASTER_BUSY_MASK |
1297 RLC_SERDES_NONCU_MASTER_BUSY__TC0_MASTER_BUSY_MASK |
1298 RLC_SERDES_NONCU_MASTER_BUSY__TC1_MASTER_BUSY_MASK;
1299 for (k = 0; k < adev->usec_timeout; k++) {
1300 if ((RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SERDES_NONCU_MASTER_BUSY)) & mask) == 0)
1301 break;
1302 udelay(1);
1303 }
1304}
1305
1306static void gfx_v9_0_enable_gui_idle_interrupt(struct amdgpu_device *adev,
1307 bool enable)
1308{
1309 u32 tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING0));
1310
1311 if (enable)
1312 return;
1313
1314 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, enable ? 1 : 0);
1315 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, enable ? 1 : 0);
1316 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, enable ? 1 : 0);
1317 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE, enable ? 1 : 0);
1318
1319 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING0), tmp);
1320}
1321
1322void gfx_v9_0_rlc_stop(struct amdgpu_device *adev)
1323{
1324 u32 tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CNTL));
1325
1326 tmp = REG_SET_FIELD(tmp, RLC_CNTL, RLC_ENABLE_F32, 0);
1327 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CNTL), tmp);
1328
1329 gfx_v9_0_enable_gui_idle_interrupt(adev, false);
1330
1331 gfx_v9_0_wait_for_rlc_serdes(adev);
1332}
1333
1334static void gfx_v9_0_rlc_reset(struct amdgpu_device *adev)
1335{
1336 u32 tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmGRBM_SOFT_RESET));
1337
1338 tmp = REG_SET_FIELD(tmp, GRBM_SOFT_RESET, SOFT_RESET_RLC, 1);
1339 WREG32(SOC15_REG_OFFSET(GC, 0, mmGRBM_SOFT_RESET), tmp);
1340 udelay(50);
1341 tmp = REG_SET_FIELD(tmp, GRBM_SOFT_RESET, SOFT_RESET_RLC, 0);
1342 WREG32(SOC15_REG_OFFSET(GC, 0, mmGRBM_SOFT_RESET), tmp);
1343 udelay(50);
1344}
1345
1346static void gfx_v9_0_rlc_start(struct amdgpu_device *adev)
1347{
1348#ifdef AMDGPU_RLC_DEBUG_RETRY
1349 u32 rlc_ucode_ver;
1350#endif
1351 u32 tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CNTL));
1352
1353 tmp = REG_SET_FIELD(tmp, RLC_CNTL, RLC_ENABLE_F32, 1);
1354 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CNTL), tmp);
1355
1356 /* carrizo do enable cp interrupt after cp inited */
1357 if (!(adev->flags & AMD_IS_APU))
1358 gfx_v9_0_enable_gui_idle_interrupt(adev, true);
1359
1360 udelay(50);
1361
1362#ifdef AMDGPU_RLC_DEBUG_RETRY
1363 /* RLC_GPM_GENERAL_6 : RLC Ucode version */
1364 rlc_ucode_ver = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_GENERAL_6));
1365 if(rlc_ucode_ver == 0x108) {
1366 DRM_INFO("Using rlc debug ucode. mmRLC_GPM_GENERAL_6 ==0x08%x / fw_ver == %i \n",
1367 rlc_ucode_ver, adev->gfx.rlc_fw_version);
1368 /* RLC_GPM_TIMER_INT_3 : Timer interval in RefCLK cycles,
1369 * default is 0x9C4 to create a 100us interval */
1370 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_TIMER_INT_3), 0x9C4);
1371 /* RLC_GPM_GENERAL_12 : Minimum gap between wptr and rptr
1372 * to disable the page fault retry interrupts, default is
1373 * 0x100 (256) */
1374 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_GENERAL_12), 0x100);
1375 }
1376#endif
1377}
1378
1379static int gfx_v9_0_rlc_load_microcode(struct amdgpu_device *adev)
1380{
1381 const struct rlc_firmware_header_v2_0 *hdr;
1382 const __le32 *fw_data;
1383 unsigned i, fw_size;
1384
1385 if (!adev->gfx.rlc_fw)
1386 return -EINVAL;
1387
1388 hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
1389 amdgpu_ucode_print_rlc_hdr(&hdr->header);
1390
1391 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data +
1392 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
1393 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
1394
1395 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UCODE_ADDR),
1396 RLCG_UCODE_LOADING_START_ADDRESS);
1397 for (i = 0; i < fw_size; i++)
1398 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UCODE_DATA), le32_to_cpup(fw_data++));
1399 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UCODE_ADDR), adev->gfx.rlc_fw_version);
1400
1401 return 0;
1402}
1403
1404static int gfx_v9_0_rlc_resume(struct amdgpu_device *adev)
1405{
1406 int r;
1407
1408 gfx_v9_0_rlc_stop(adev);
1409
1410 /* disable CG */
1411 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CGCG_CGLS_CTRL), 0);
1412
1413 /* disable PG */
1414 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), 0);
1415
1416 gfx_v9_0_rlc_reset(adev);
1417
1418 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
1419 /* legacy rlc firmware loading */
1420 r = gfx_v9_0_rlc_load_microcode(adev);
1421 if (r)
1422 return r;
1423 }
1424
1425 gfx_v9_0_rlc_start(adev);
1426
1427 return 0;
1428}
1429
1430static void gfx_v9_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable)
1431{
1432 int i;
1433 u32 tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_ME_CNTL));
1434
1435 if (enable) {
1436 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, 0);
1437 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, 0);
1438 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, 0);
1439 } else {
1440 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, 1);
1441 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, 1);
1442 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, 1);
1443 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
1444 adev->gfx.gfx_ring[i].ready = false;
1445 }
1446 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_ME_CNTL), tmp);
1447 udelay(50);
1448}
1449
1450static int gfx_v9_0_cp_gfx_load_microcode(struct amdgpu_device *adev)
1451{
1452 const struct gfx_firmware_header_v1_0 *pfp_hdr;
1453 const struct gfx_firmware_header_v1_0 *ce_hdr;
1454 const struct gfx_firmware_header_v1_0 *me_hdr;
1455 const __le32 *fw_data;
1456 unsigned i, fw_size;
1457
1458 if (!adev->gfx.me_fw || !adev->gfx.pfp_fw || !adev->gfx.ce_fw)
1459 return -EINVAL;
1460
1461 pfp_hdr = (const struct gfx_firmware_header_v1_0 *)
1462 adev->gfx.pfp_fw->data;
1463 ce_hdr = (const struct gfx_firmware_header_v1_0 *)
1464 adev->gfx.ce_fw->data;
1465 me_hdr = (const struct gfx_firmware_header_v1_0 *)
1466 adev->gfx.me_fw->data;
1467
1468 amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header);
1469 amdgpu_ucode_print_gfx_hdr(&ce_hdr->header);
1470 amdgpu_ucode_print_gfx_hdr(&me_hdr->header);
1471
1472 gfx_v9_0_cp_gfx_enable(adev, false);
1473
1474 /* PFP */
1475 fw_data = (const __le32 *)
1476 (adev->gfx.pfp_fw->data +
1477 le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes));
1478 fw_size = le32_to_cpu(pfp_hdr->header.ucode_size_bytes) / 4;
1479 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_PFP_UCODE_ADDR), 0);
1480 for (i = 0; i < fw_size; i++)
1481 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_PFP_UCODE_DATA), le32_to_cpup(fw_data++));
1482 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_PFP_UCODE_ADDR), adev->gfx.pfp_fw_version);
1483
1484 /* CE */
1485 fw_data = (const __le32 *)
1486 (adev->gfx.ce_fw->data +
1487 le32_to_cpu(ce_hdr->header.ucode_array_offset_bytes));
1488 fw_size = le32_to_cpu(ce_hdr->header.ucode_size_bytes) / 4;
1489 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_CE_UCODE_ADDR), 0);
1490 for (i = 0; i < fw_size; i++)
1491 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_CE_UCODE_DATA), le32_to_cpup(fw_data++));
1492 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_CE_UCODE_ADDR), adev->gfx.ce_fw_version);
1493
1494 /* ME */
1495 fw_data = (const __le32 *)
1496 (adev->gfx.me_fw->data +
1497 le32_to_cpu(me_hdr->header.ucode_array_offset_bytes));
1498 fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes) / 4;
1499 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_ME_RAM_WADDR), 0);
1500 for (i = 0; i < fw_size; i++)
1501 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_ME_RAM_DATA), le32_to_cpup(fw_data++));
1502 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_ME_RAM_WADDR), adev->gfx.me_fw_version);
1503
1504 return 0;
1505}
1506
1507static u32 gfx_v9_0_get_csb_size(struct amdgpu_device *adev)
1508{
1509 u32 count = 0;
1510 const struct cs_section_def *sect = NULL;
1511 const struct cs_extent_def *ext = NULL;
1512
1513 /* begin clear state */
1514 count += 2;
1515 /* context control state */
1516 count += 3;
1517
1518 for (sect = gfx9_cs_data; sect->section != NULL; ++sect) {
1519 for (ext = sect->section; ext->extent != NULL; ++ext) {
1520 if (sect->id == SECT_CONTEXT)
1521 count += 2 + ext->reg_count;
1522 else
1523 return 0;
1524 }
1525 }
1526 /* pa_sc_raster_config/pa_sc_raster_config1 */
1527 count += 4;
1528 /* end clear state */
1529 count += 2;
1530 /* clear state */
1531 count += 2;
1532
1533 return count;
1534}
1535
1536static int gfx_v9_0_cp_gfx_start(struct amdgpu_device *adev)
1537{
1538 struct amdgpu_ring *ring = &adev->gfx.gfx_ring[0];
1539 const struct cs_section_def *sect = NULL;
1540 const struct cs_extent_def *ext = NULL;
1541 int r, i;
1542
1543 /* init the CP */
1544 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_MAX_CONTEXT), adev->gfx.config.max_hw_contexts - 1);
1545 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_DEVICE_ID), 1);
1546
1547 gfx_v9_0_cp_gfx_enable(adev, true);
1548
1549 r = amdgpu_ring_alloc(ring, gfx_v9_0_get_csb_size(adev) + 4);
1550 if (r) {
1551 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r);
1552 return r;
1553 }
1554
1555 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
1556 amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
1557
1558 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
1559 amdgpu_ring_write(ring, 0x80000000);
1560 amdgpu_ring_write(ring, 0x80000000);
1561
1562 for (sect = gfx9_cs_data; sect->section != NULL; ++sect) {
1563 for (ext = sect->section; ext->extent != NULL; ++ext) {
1564 if (sect->id == SECT_CONTEXT) {
1565 amdgpu_ring_write(ring,
1566 PACKET3(PACKET3_SET_CONTEXT_REG,
1567 ext->reg_count));
1568 amdgpu_ring_write(ring,
1569 ext->reg_index - PACKET3_SET_CONTEXT_REG_START);
1570 for (i = 0; i < ext->reg_count; i++)
1571 amdgpu_ring_write(ring, ext->extent[i]);
1572 }
1573 }
1574 }
1575
1576 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
1577 amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE);
1578
1579 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
1580 amdgpu_ring_write(ring, 0);
1581
1582 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2));
1583 amdgpu_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE));
1584 amdgpu_ring_write(ring, 0x8000);
1585 amdgpu_ring_write(ring, 0x8000);
1586
1587 amdgpu_ring_commit(ring);
1588
1589 return 0;
1590}
1591
1592static int gfx_v9_0_cp_gfx_resume(struct amdgpu_device *adev)
1593{
1594 struct amdgpu_ring *ring;
1595 u32 tmp;
1596 u32 rb_bufsz;
3fc08b61 1597 u64 rb_addr, rptr_addr, wptr_gpu_addr;
b1023571
KW		 1598
1599 /* Set the write pointer delay */
1600 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB_WPTR_DELAY), 0);
1601
1602 /* set the RB to use vmid 0 */
1603 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB_VMID), 0);
1604
1605 /* Set ring buffer size */
1606 ring = &adev->gfx.gfx_ring[0];
1607 rb_bufsz = order_base_2(ring->ring_size / 8);
1608 tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz);
1609 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2);
1610#ifdef __BIG_ENDIAN
1611 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, BUF_SWAP, 1);
1612#endif
1613 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB0_CNTL), tmp);
1614
1615 /* Initialize the ring buffer's write pointers */
1616 ring->wptr = 0;
1617 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB0_WPTR), lower_32_bits(ring->wptr));
1618 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB0_WPTR_HI), upper_32_bits(ring->wptr));
1619
1620 /* set the wb address wether it's enabled or not */
1621 rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
1622 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB0_RPTR_ADDR), lower_32_bits(rptr_addr));
1623 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB0_RPTR_ADDR_HI), upper_32_bits(rptr_addr) & CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK);
1624
3fc08b61
ML		 1625 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
1626 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO), lower_32_bits(wptr_gpu_addr));
1627 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI), upper_32_bits(wptr_gpu_addr));
1628
b1023571
KW		 1629 mdelay(1);
1630 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB0_CNTL), tmp);
1631
1632 rb_addr = ring->gpu_addr >> 8;
1633 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB0_BASE), rb_addr);
1634 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB0_BASE_HI), upper_32_bits(rb_addr));
1635
1636 tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB_DOORBELL_CONTROL));
1637 if (ring->use_doorbell) {
1638 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
1639 DOORBELL_OFFSET, ring->doorbell_index);
1640 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
1641 DOORBELL_EN, 1);
1642 } else {
1643 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, DOORBELL_EN, 0);
1644 }
1645 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB_DOORBELL_CONTROL), tmp);
1646
1647 tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER,
1648 DOORBELL_RANGE_LOWER, ring->doorbell_index);
1649 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB_DOORBELL_RANGE_LOWER), tmp);
1650
1651 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB_DOORBELL_RANGE_UPPER),
1652 CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK);
1653
1654
1655 /* start the ring */
1656 gfx_v9_0_cp_gfx_start(adev);
1657 ring->ready = true;
1658
1659 return 0;
1660}
1661
1662static void gfx_v9_0_cp_compute_enable(struct amdgpu_device *adev, bool enable)
1663{
1664 int i;
1665
1666 if (enable) {
1667 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_MEC_CNTL), 0);
1668 } else {
1669 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_MEC_CNTL),
1670 (CP_MEC_CNTL__MEC_ME1_HALT_MASK | CP_MEC_CNTL__MEC_ME2_HALT_MASK));
1671 for (i = 0; i < adev->gfx.num_compute_rings; i++)
1672 adev->gfx.compute_ring[i].ready = false;
ac104e99 1673 adev->gfx.kiq.ring.ready = false;
b1023571
KW		 1674 }
1675 udelay(50);
1676}
1677
1678static int gfx_v9_0_cp_compute_start(struct amdgpu_device *adev)
1679{
1680 gfx_v9_0_cp_compute_enable(adev, true);
1681
1682 return 0;
1683}
1684
1685static int gfx_v9_0_cp_compute_load_microcode(struct amdgpu_device *adev)
1686{
1687 const struct gfx_firmware_header_v1_0 *mec_hdr;
1688 const __le32 *fw_data;
1689 unsigned i;
1690 u32 tmp;
1691
1692 if (!adev->gfx.mec_fw)
1693 return -EINVAL;
1694
1695 gfx_v9_0_cp_compute_enable(adev, false);
1696
1697 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
1698 amdgpu_ucode_print_gfx_hdr(&mec_hdr->header);
1699
1700 fw_data = (const __le32 *)
1701 (adev->gfx.mec_fw->data +
1702 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes));
1703 tmp = 0;
1704 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, VMID, 0);
1705 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0);
1706 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_CPC_IC_BASE_CNTL), tmp);
1707
1708 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_CPC_IC_BASE_LO),
1709 adev->gfx.mec.mec_fw_gpu_addr & 0xFFFFF000);
1710 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_CPC_IC_BASE_HI),
1711 upper_32_bits(adev->gfx.mec.mec_fw_gpu_addr));
1712
1713 /* MEC1 */
1714 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_MEC_ME1_UCODE_ADDR),
1715 mec_hdr->jt_offset);
1716 for (i = 0; i < mec_hdr->jt_size; i++)
1717 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_MEC_ME1_UCODE_DATA),
1718 le32_to_cpup(fw_data + mec_hdr->jt_offset + i));
1719
1720 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_MEC_ME1_UCODE_ADDR),
1721 adev->gfx.mec_fw_version);
1722 /* Todo : Loading MEC2 firmware is only necessary if MEC2 should run different microcode than MEC1. */
1723
1724 return 0;
1725}
1726
1727static void gfx_v9_0_cp_compute_fini(struct amdgpu_device *adev)
1728{
1729 int i, r;
1730
1731 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
1732 struct amdgpu_ring *ring = &adev->gfx.compute_ring[i];
1733
1734 if (ring->mqd_obj) {
1735 r = amdgpu_bo_reserve(ring->mqd_obj, false);
1736 if (unlikely(r != 0))
1737 dev_warn(adev->dev, "(%d) reserve MQD bo failed\n", r);
1738
1739 amdgpu_bo_unpin(ring->mqd_obj);
1740 amdgpu_bo_unreserve(ring->mqd_obj);
1741
1742 amdgpu_bo_unref(&ring->mqd_obj);
1743 ring->mqd_obj = NULL;
1744 }
1745 }
1746}
1747
1748static int gfx_v9_0_init_queue(struct amdgpu_ring *ring);
1749
1750static int gfx_v9_0_cp_compute_resume(struct amdgpu_device *adev)
1751{
1752 int i, r;
1753 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
1754 struct amdgpu_ring *ring = &adev->gfx.compute_ring[i];
1755 if (gfx_v9_0_init_queue(ring))
1756 dev_warn(adev->dev, "compute queue %d init failed!\n", i);
1757 }
1758
1759 r = gfx_v9_0_cp_compute_start(adev);
1760 if (r)
1761 return r;
1762
1763 return 0;
1764}
1765
1766static int gfx_v9_0_cp_resume(struct amdgpu_device *adev)
1767{
1768 int r,i;
1769 struct amdgpu_ring *ring;
1770
1771 if (!(adev->flags & AMD_IS_APU))
1772 gfx_v9_0_enable_gui_idle_interrupt(adev, false);
1773
1774 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
1775 /* legacy firmware loading */
1776 r = gfx_v9_0_cp_gfx_load_microcode(adev);
1777 if (r)
1778 return r;
1779
1780 r = gfx_v9_0_cp_compute_load_microcode(adev);
1781 if (r)
1782 return r;
1783 }
1784
1785 r = gfx_v9_0_cp_gfx_resume(adev);
1786 if (r)
1787 return r;
1788
1789 r = gfx_v9_0_cp_compute_resume(adev);
1790 if (r)
1791 return r;
1792
1793 ring = &adev->gfx.gfx_ring[0];
1794 r = amdgpu_ring_test_ring(ring);
1795 if (r) {
1796 ring->ready = false;
1797 return r;
1798 }
1799 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
1800 ring = &adev->gfx.compute_ring[i];
1801
1802 ring->ready = true;
1803 r = amdgpu_ring_test_ring(ring);
1804 if (r)
1805 ring->ready = false;
1806 }
1807
1808 gfx_v9_0_enable_gui_idle_interrupt(adev, true);
1809
1810 return 0;
1811}
1812
1813static void gfx_v9_0_cp_enable(struct amdgpu_device *adev, bool enable)
1814{
1815 gfx_v9_0_cp_gfx_enable(adev, enable);
1816 gfx_v9_0_cp_compute_enable(adev, enable);
1817}
1818
1819static int gfx_v9_0_hw_init(void *handle)
1820{
1821 int r;
1822 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1823
1824 gfx_v9_0_init_golden_registers(adev);
1825
1826 gfx_v9_0_gpu_init(adev);
1827
1828 r = gfx_v9_0_rlc_resume(adev);
1829 if (r)
1830 return r;
1831
1832 r = gfx_v9_0_cp_resume(adev);
1833 if (r)
1834 return r;
1835
1836 r = gfx_v9_0_ngg_en(adev);
1837 if (r)
1838 return r;
1839
1840 return r;
1841}
1842
1843static int gfx_v9_0_hw_fini(void *handle)
1844{
1845 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1846
1847 amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0);
1848 amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0);
1849 gfx_v9_0_cp_enable(adev, false);
1850 gfx_v9_0_rlc_stop(adev);
1851 gfx_v9_0_cp_compute_fini(adev);
1852
1853 return 0;
1854}
1855
1856static int gfx_v9_0_suspend(void *handle)
1857{
1858 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1859
1860 return gfx_v9_0_hw_fini(adev);
1861}
1862
1863static int gfx_v9_0_resume(void *handle)
1864{
1865 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1866
1867 return gfx_v9_0_hw_init(adev);
1868}
1869
1870static bool gfx_v9_0_is_idle(void *handle)
1871{
1872 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1873
1874 if (REG_GET_FIELD(RREG32(SOC15_REG_OFFSET(GC, 0, mmGRBM_STATUS)),
1875 GRBM_STATUS, GUI_ACTIVE))
1876 return false;
1877 else
1878 return true;
1879}
1880
1881static int gfx_v9_0_wait_for_idle(void *handle)
1882{
1883 unsigned i;
1884 u32 tmp;
1885 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1886
1887 for (i = 0; i < adev->usec_timeout; i++) {
1888 /* read MC_STATUS */
1889 tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmGRBM_STATUS)) &
1890 GRBM_STATUS__GUI_ACTIVE_MASK;
1891
1892 if (!REG_GET_FIELD(tmp, GRBM_STATUS, GUI_ACTIVE))
1893 return 0;
1894 udelay(1);
1895 }
1896 return -ETIMEDOUT;
1897}
1898
1899static void gfx_v9_0_print_status(void *handle)
1900{
1901 int i;
1902 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1903
1904 dev_info(adev->dev, "GFX 9.x registers\n");
1905 dev_info(adev->dev, " GRBM_STATUS=0x%08X\n",
1906 RREG32(SOC15_REG_OFFSET(GC, 0, mmGRBM_STATUS)));
1907 dev_info(adev->dev, " GRBM_STATUS2=0x%08X\n",
1908 RREG32(SOC15_REG_OFFSET(GC, 0, mmGRBM_STATUS2)));
1909 dev_info(adev->dev, " GRBM_STATUS_SE0=0x%08X\n",
1910 RREG32(SOC15_REG_OFFSET(GC, 0, mmGRBM_STATUS_SE0)));
1911 dev_info(adev->dev, " GRBM_STATUS_SE1=0x%08X\n",
1912 RREG32(SOC15_REG_OFFSET(GC, 0, mmGRBM_STATUS_SE1)));
1913 dev_info(adev->dev, " GRBM_STATUS_SE2=0x%08X\n",
1914 RREG32(SOC15_REG_OFFSET(GC, 0, mmGRBM_STATUS_SE2)));
1915 dev_info(adev->dev, " GRBM_STATUS_SE3=0x%08X\n",
1916 RREG32(SOC15_REG_OFFSET(GC, 0, mmGRBM_STATUS_SE3)));
1917 dev_info(adev->dev, " CP_STAT = 0x%08x\n", RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_STAT)));
1918 dev_info(adev->dev, " CP_STALLED_STAT1 = 0x%08x\n",
1919 RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_STALLED_STAT1)));
1920 dev_info(adev->dev, " CP_STALLED_STAT2 = 0x%08x\n",
1921 RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_STALLED_STAT2)));
1922 dev_info(adev->dev, " CP_STALLED_STAT3 = 0x%08x\n",
1923 RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_STALLED_STAT3)));
1924 dev_info(adev->dev, " CP_CPF_BUSY_STAT = 0x%08x\n",
1925 RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_CPF_BUSY_STAT)));
1926 dev_info(adev->dev, " CP_CPF_STALLED_STAT1 = 0x%08x\n",
1927 RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_CPF_STALLED_STAT1)));
1928 dev_info(adev->dev, " CP_CPF_STATUS = 0x%08x\n", RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_CPF_STATUS)));
1929 dev_info(adev->dev, " CP_CPC_BUSY_STAT = 0x%08x\n", RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_CPC_BUSY_STAT)));
1930 dev_info(adev->dev, " CP_CPC_STALLED_STAT1 = 0x%08x\n",
1931 RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_CPC_STALLED_STAT1)));
1932 dev_info(adev->dev, " CP_CPC_STATUS = 0x%08x\n", RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_CPC_STATUS)));
1933
1934 for (i = 0; i < 32; i++) {
1935 dev_info(adev->dev, " GB_TILE_MODE%d=0x%08X\n",
1936 i, RREG32(SOC15_REG_OFFSET(GC, 0, mmGB_TILE_MODE0 ) + i*4));
1937 }
1938 for (i = 0; i < 16; i++) {
1939 dev_info(adev->dev, " GB_MACROTILE_MODE%d=0x%08X\n",
1940 i, RREG32(SOC15_REG_OFFSET(GC, 0, mmGB_MACROTILE_MODE0) + i*4));
1941 }
1942 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
1943 dev_info(adev->dev, " se: %d\n", i);
1944 gfx_v9_0_select_se_sh(adev, i, 0xffffffff, 0xffffffff);
1945 dev_info(adev->dev, " PA_SC_RASTER_CONFIG=0x%08X\n",
1946 RREG32(SOC15_REG_OFFSET(GC, 0, mmPA_SC_RASTER_CONFIG)));
1947 dev_info(adev->dev, " PA_SC_RASTER_CONFIG_1=0x%08X\n",
1948 RREG32(SOC15_REG_OFFSET(GC, 0, mmPA_SC_RASTER_CONFIG_1)));
1949 }
1950 gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
1951
1952 dev_info(adev->dev, " GB_ADDR_CONFIG=0x%08X\n",
1953 RREG32(SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG)));
1954
1955 dev_info(adev->dev, " CP_MEQ_THRESHOLDS=0x%08X\n",
1956 RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_MEQ_THRESHOLDS)));
1957 dev_info(adev->dev, " SX_DEBUG_1=0x%08X\n",
1958 RREG32(SOC15_REG_OFFSET(GC, 0, mmSX_DEBUG_1)));
1959 dev_info(adev->dev, " TA_CNTL_AUX=0x%08X\n",
1960 RREG32(SOC15_REG_OFFSET(GC, 0, mmTA_CNTL_AUX)));
1961 dev_info(adev->dev, " SPI_CONFIG_CNTL=0x%08X\n",
1962 RREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL)));
1963 dev_info(adev->dev, " SQ_CONFIG=0x%08X\n",
1964 RREG32(SOC15_REG_OFFSET(GC, 0, mmSQ_CONFIG)));
1965 dev_info(adev->dev, " DB_DEBUG=0x%08X\n",
1966 RREG32(SOC15_REG_OFFSET(GC, 0, mmDB_DEBUG)));
1967 dev_info(adev->dev, " DB_DEBUG2=0x%08X\n",
1968 RREG32(SOC15_REG_OFFSET(GC, 0, mmDB_DEBUG2)));
1969 dev_info(adev->dev, " DB_DEBUG3=0x%08X\n",
1970 RREG32(SOC15_REG_OFFSET(GC, 0, mmDB_DEBUG3)));
1971 dev_info(adev->dev, " CB_HW_CONTROL=0x%08X\n",
1972 RREG32(SOC15_REG_OFFSET(GC, 0, mmCB_HW_CONTROL)));
1973 dev_info(adev->dev, " SPI_CONFIG_CNTL_1=0x%08X\n",
1974 RREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_1)));
1975 dev_info(adev->dev, " PA_SC_FIFO_SIZE=0x%08X\n",
1976 RREG32(SOC15_REG_OFFSET(GC, 0, mmPA_SC_FIFO_SIZE)));
1977 dev_info(adev->dev, " VGT_NUM_INSTANCES=0x%08X\n",
1978 RREG32(SOC15_REG_OFFSET(GC, 0, mmVGT_NUM_INSTANCES)));
1979 dev_info(adev->dev, " CP_PERFMON_CNTL=0x%08X\n",
1980 RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_PERFMON_CNTL)));
1981 dev_info(adev->dev, " PA_SC_FORCE_EOV_MAX_CNTS=0x%08X\n",
1982 RREG32(SOC15_REG_OFFSET(GC, 0, mmPA_SC_FORCE_EOV_MAX_CNTS)));
1983 dev_info(adev->dev, " VGT_CACHE_INVALIDATION=0x%08X\n",
1984 RREG32(SOC15_REG_OFFSET(GC, 0, mmVGT_CACHE_INVALIDATION)));
1985 dev_info(adev->dev, " VGT_GS_VERTEX_REUSE=0x%08X\n",
1986 RREG32(SOC15_REG_OFFSET(GC, 0, mmVGT_GS_VERTEX_REUSE)));
1987 dev_info(adev->dev, " PA_SC_LINE_STIPPLE_STATE=0x%08X\n",
1988 RREG32(SOC15_REG_OFFSET(GC, 0, mmPA_SC_LINE_STIPPLE_STATE)));
1989 dev_info(adev->dev, " PA_CL_ENHANCE=0x%08X\n",
1990 RREG32(SOC15_REG_OFFSET(GC, 0, mmPA_CL_ENHANCE)));
1991 dev_info(adev->dev, " PA_SC_ENHANCE=0x%08X\n",
1992 RREG32(SOC15_REG_OFFSET(GC, 0, mmPA_SC_ENHANCE)));
1993
1994 dev_info(adev->dev, " CP_ME_CNTL=0x%08X\n",
1995 RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_ME_CNTL)));
1996 dev_info(adev->dev, " CP_MAX_CONTEXT=0x%08X\n",
1997 RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_MAX_CONTEXT)));
1998 dev_info(adev->dev, " CP_DEVICE_ID=0x%08X\n",
1999 RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_DEVICE_ID)));
2000
2001 dev_info(adev->dev, " CP_SEM_WAIT_TIMER=0x%08X\n",
2002 RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_SEM_WAIT_TIMER)));
2003
2004 dev_info(adev->dev, " CP_RB_WPTR_DELAY=0x%08X\n",
2005 RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB_WPTR_DELAY)));
2006 dev_info(adev->dev, " CP_RB_VMID=0x%08X\n",
2007 RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB_VMID)));
2008 dev_info(adev->dev, " CP_RB0_CNTL=0x%08X\n",
2009 RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB0_CNTL)));
2010 dev_info(adev->dev, " CP_RB0_WPTR=0x%08X\n",
2011 RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB0_WPTR)));
2012 dev_info(adev->dev, " CP_RB0_RPTR_ADDR=0x%08X\n",
2013 RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB0_RPTR_ADDR)));
2014 dev_info(adev->dev, " CP_RB0_RPTR_ADDR_HI=0x%08X\n",
2015 RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB0_RPTR_ADDR_HI)));
2016 dev_info(adev->dev, " CP_RB0_CNTL=0x%08X\n",
2017 RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB0_CNTL)));
2018 dev_info(adev->dev, " CP_RB0_BASE=0x%08X\n",
2019 RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB0_BASE)));
2020 dev_info(adev->dev, " CP_RB0_BASE_HI=0x%08X\n",
2021 RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB0_BASE_HI)));
2022 dev_info(adev->dev, " CP_MEC_CNTL=0x%08X\n",
2023 RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_MEC_CNTL)));
2024
2025 dev_info(adev->dev, " SCRATCH_ADDR=0x%08X\n",
2026 RREG32(SOC15_REG_OFFSET(GC, 0, mmSCRATCH_ADDR)));
2027 dev_info(adev->dev, " SCRATCH_UMSK=0x%08X\n",
2028 RREG32(SOC15_REG_OFFSET(GC, 0, mmSCRATCH_UMSK)));
2029
2030 dev_info(adev->dev, " CP_INT_CNTL_RING0=0x%08X\n",
2031 RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING0)));
2032 dev_info(adev->dev, " RLC_LB_CNTL=0x%08X\n",
2033 RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_LB_CNTL)));
2034 dev_info(adev->dev, " RLC_CNTL=0x%08X\n",
2035 RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CNTL)));
2036 dev_info(adev->dev, " RLC_CGCG_CGLS_CTRL=0x%08X\n",
2037 RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CGCG_CGLS_CTRL)));
2038 dev_info(adev->dev, " RLC_LB_CNTR_INIT=0x%08X\n",
2039 RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_LB_CNTR_INIT)));
2040 dev_info(adev->dev, " RLC_LB_CNTR_MAX=0x%08X\n",
2041 RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_LB_CNTR_MAX)));
2042 dev_info(adev->dev, " RLC_LB_INIT_CU_MASK=0x%08X\n",
2043 RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_LB_INIT_CU_MASK)));
2044 dev_info(adev->dev, " RLC_LB_PARAMS=0x%08X\n",
2045 RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_LB_PARAMS)));
2046 dev_info(adev->dev, " RLC_LB_CNTL=0x%08X\n",
2047 RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_LB_CNTL)));
2048 dev_info(adev->dev, " RLC_UCODE_CNTL=0x%08X\n",
2049 RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_UCODE_CNTL)));
2050
2051 dev_info(adev->dev, " RLC_GPM_GENERAL_6=0x%08X\n",
2052 RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_GENERAL_6)));
2053 dev_info(adev->dev, " RLC_GPM_GENERAL_12=0x%08X\n",
2054 RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_GENERAL_12)));
2055 dev_info(adev->dev, " RLC_GPM_TIMER_INT_3=0x%08X\n",
2056 RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_TIMER_INT_3)));
2057 mutex_lock(&adev->srbm_mutex);
2058 for (i = 0; i < 16; i++) {
2059 soc15_grbm_select(adev, 0, 0, 0, i);
2060 dev_info(adev->dev, " VM %d:\n", i);
2061 dev_info(adev->dev, " SH_MEM_CONFIG=0x%08X\n",
2062 RREG32(SOC15_REG_OFFSET(GC, 0, mmSH_MEM_CONFIG)));
2063 dev_info(adev->dev, " SH_MEM_BASES=0x%08X\n",
2064 RREG32(SOC15_REG_OFFSET(GC, 0, mmSH_MEM_BASES)));
2065 }
2066 soc15_grbm_select(adev, 0, 0, 0, 0);
2067 mutex_unlock(&adev->srbm_mutex);
2068}
2069
2070static int gfx_v9_0_soft_reset(void *handle)
2071{
2072 u32 grbm_soft_reset = 0;
2073 u32 tmp;
2074 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2075
2076 /* GRBM_STATUS */
2077 tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmGRBM_STATUS));
2078 if (tmp & (GRBM_STATUS__PA_BUSY_MASK | GRBM_STATUS__SC_BUSY_MASK |
2079 GRBM_STATUS__BCI_BUSY_MASK | GRBM_STATUS__SX_BUSY_MASK |
2080 GRBM_STATUS__TA_BUSY_MASK | GRBM_STATUS__VGT_BUSY_MASK |
2081 GRBM_STATUS__DB_BUSY_MASK | GRBM_STATUS__CB_BUSY_MASK |
2082 GRBM_STATUS__GDS_BUSY_MASK | GRBM_STATUS__SPI_BUSY_MASK |
2083 GRBM_STATUS__IA_BUSY_MASK | GRBM_STATUS__IA_BUSY_NO_DMA_MASK)) {
2084 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
2085 GRBM_SOFT_RESET, SOFT_RESET_CP, 1);
2086 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
2087 GRBM_SOFT_RESET, SOFT_RESET_GFX, 1);
2088 }
2089
2090 if (tmp & (GRBM_STATUS__CP_BUSY_MASK | GRBM_STATUS__CP_COHERENCY_BUSY_MASK)) {
2091 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
2092 GRBM_SOFT_RESET, SOFT_RESET_CP, 1);
2093 }
2094
2095 /* GRBM_STATUS2 */
2096 tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmGRBM_STATUS2));
2097 if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY))
2098 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
2099 GRBM_SOFT_RESET, SOFT_RESET_RLC, 1);
2100
2101
2102 if (grbm_soft_reset ) {
2103 gfx_v9_0_print_status((void *)adev);
2104 /* stop the rlc */
2105 gfx_v9_0_rlc_stop(adev);
2106
2107 /* Disable GFX parsing/prefetching */
2108 gfx_v9_0_cp_gfx_enable(adev, false);
2109
2110 /* Disable MEC parsing/prefetching */
2111 gfx_v9_0_cp_compute_enable(adev, false);
2112
2113 if (grbm_soft_reset) {
2114 tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmGRBM_SOFT_RESET));
2115 tmp |= grbm_soft_reset;
2116 dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp);
2117 WREG32(SOC15_REG_OFFSET(GC, 0, mmGRBM_SOFT_RESET), tmp);
2118 tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmGRBM_SOFT_RESET));
2119
2120 udelay(50);
2121
2122 tmp &= ~grbm_soft_reset;
2123 WREG32(SOC15_REG_OFFSET(GC, 0, mmGRBM_SOFT_RESET), tmp);
2124 tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmGRBM_SOFT_RESET));
2125 }
2126
2127 /* Wait a little for things to settle down */
2128 udelay(50);
2129 gfx_v9_0_print_status((void *)adev);
2130 }
2131 return 0;
2132}
2133
2134static uint64_t gfx_v9_0_get_gpu_clock_counter(struct amdgpu_device *adev)
2135{
2136 uint64_t clock;
2137
2138 mutex_lock(&adev->gfx.gpu_clock_mutex);
2139 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CAPTURE_GPU_CLOCK_COUNT), 1);
2140 clock = (uint64_t)RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPU_CLOCK_COUNT_LSB)) |
2141 ((uint64_t)RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPU_CLOCK_COUNT_MSB)) << 32ULL);
2142 mutex_unlock(&adev->gfx.gpu_clock_mutex);
2143 return clock;
2144}
2145
2146static void gfx_v9_0_ring_emit_gds_switch(struct amdgpu_ring *ring,
2147 uint32_t vmid,
2148 uint32_t gds_base, uint32_t gds_size,
2149 uint32_t gws_base, uint32_t gws_size,
2150 uint32_t oa_base, uint32_t oa_size)
2151{
2152 gds_base = gds_base >> AMDGPU_GDS_SHIFT;
2153 gds_size = gds_size >> AMDGPU_GDS_SHIFT;
2154
2155 gws_base = gws_base >> AMDGPU_GWS_SHIFT;
2156 gws_size = gws_size >> AMDGPU_GWS_SHIFT;
2157
2158 oa_base = oa_base >> AMDGPU_OA_SHIFT;
2159 oa_size = oa_size >> AMDGPU_OA_SHIFT;
2160
2161 /* GDS Base */
2162 gfx_v9_0_write_data_to_reg(ring, 0, false,
2163 amdgpu_gds_reg_offset[vmid].mem_base,
2164 gds_base);
2165
2166 /* GDS Size */
2167 gfx_v9_0_write_data_to_reg(ring, 0, false,
2168 amdgpu_gds_reg_offset[vmid].mem_size,
2169 gds_size);
2170
2171 /* GWS */
2172 gfx_v9_0_write_data_to_reg(ring, 0, false,
2173 amdgpu_gds_reg_offset[vmid].gws,
2174 gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base);
2175
2176 /* OA */
2177 gfx_v9_0_write_data_to_reg(ring, 0, false,
2178 amdgpu_gds_reg_offset[vmid].oa,
2179 (1 << (oa_size + oa_base)) - (1 << oa_base));
2180}
2181
2182static int gfx_v9_0_early_init(void *handle)
2183{
2184 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2185
2186 adev->gfx.num_gfx_rings = GFX9_NUM_GFX_RINGS;
2187 adev->gfx.num_compute_rings = GFX9_NUM_COMPUTE_RINGS;
2188 gfx_v9_0_set_ring_funcs(adev);
2189 gfx_v9_0_set_irq_funcs(adev);
2190 gfx_v9_0_set_gds_init(adev);
2191 gfx_v9_0_set_rlc_funcs(adev);
2192
2193 return 0;
2194}
2195
2196static int gfx_v9_0_late_init(void *handle)
2197{
2198 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2199 int r;
2200
2201 r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0);
2202 if (r)
2203 return r;
2204
2205 r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0);
2206 if (r)
2207 return r;
2208
2209 return 0;
2210}
2211
2212static void gfx_v9_0_enter_rlc_safe_mode(struct amdgpu_device *adev)
2213{
2214 uint32_t rlc_setting, data;
2215 unsigned i;
2216
2217 if (adev->gfx.rlc.in_safe_mode)
2218 return;
2219
2220 /* if RLC is not enabled, do nothing */
2221 rlc_setting = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CNTL));
2222 if (!(rlc_setting & RLC_CNTL__RLC_ENABLE_F32_MASK))
2223 return;
2224
2225 if (adev->cg_flags &
2226 (AMD_CG_SUPPORT_GFX_CGCG | AMD_CG_SUPPORT_GFX_MGCG |
2227 AMD_CG_SUPPORT_GFX_3D_CGCG)) {
2228 data = RLC_SAFE_MODE__CMD_MASK;
2229 data |= (1 << RLC_SAFE_MODE__MESSAGE__SHIFT);
2230 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SAFE_MODE), data);
2231
2232 /* wait for RLC_SAFE_MODE */
2233 for (i = 0; i < adev->usec_timeout; i++) {
2234 if (!REG_GET_FIELD(SOC15_REG_OFFSET(GC, 0, mmRLC_SAFE_MODE), RLC_SAFE_MODE, CMD))
2235 break;
2236 udelay(1);
2237 }
2238 adev->gfx.rlc.in_safe_mode = true;
2239 }
2240}
2241
2242static void gfx_v9_0_exit_rlc_safe_mode(struct amdgpu_device *adev)
2243{
2244 uint32_t rlc_setting, data;
2245
2246 if (!adev->gfx.rlc.in_safe_mode)
2247 return;
2248
2249 /* if RLC is not enabled, do nothing */
2250 rlc_setting = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CNTL));
2251 if (!(rlc_setting & RLC_CNTL__RLC_ENABLE_F32_MASK))
2252 return;
2253
2254 if (adev->cg_flags &
2255 (AMD_CG_SUPPORT_GFX_CGCG | AMD_CG_SUPPORT_GFX_MGCG)) {
2256 /*
2257 * Try to exit safe mode only if it is already in safe
2258 * mode.
2259 */
2260 data = RLC_SAFE_MODE__CMD_MASK;
2261 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SAFE_MODE), data);
2262 adev->gfx.rlc.in_safe_mode = false;
2263 }
2264}
2265
2266static void gfx_v9_0_update_medium_grain_clock_gating(struct amdgpu_device *adev,
2267 bool enable)
2268{
2269 uint32_t data, def;
2270
2271 /* It is disabled by HW by default */
2272 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) {
2273 /* 1 - RLC_CGTT_MGCG_OVERRIDE */
2274 def = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE));
2275 data &= ~(RLC_CGTT_MGCG_OVERRIDE__CPF_CGTT_SCLK_OVERRIDE_MASK |
2276 RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK |
2277 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK |
2278 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK);
2279
2280 /* only for Vega10 & Raven1 */
2281 data |= RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK;
2282
2283 if (def != data)
2284 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE), data);
2285
2286 /* MGLS is a global flag to control all MGLS in GFX */
2287 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) {
2288 /* 2 - RLC memory Light sleep */
2289 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_RLC_LS) {
2290 def = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_MEM_SLP_CNTL));
2291 data |= RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK;
2292 if (def != data)
2293 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_MEM_SLP_CNTL), data);
2294 }
2295 /* 3 - CP memory Light sleep */
2296 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS) {
2297 def = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_MEM_SLP_CNTL));
2298 data |= CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
2299 if (def != data)
2300 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_MEM_SLP_CNTL), data);
2301 }
2302 }
2303 } else {
2304 /* 1 - MGCG_OVERRIDE */
2305 def = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE));
2306 data |= (RLC_CGTT_MGCG_OVERRIDE__CPF_CGTT_SCLK_OVERRIDE_MASK |
2307 RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK |
2308 RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK |
2309 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK |
2310 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK);
2311 if (def != data)
2312 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE), data);
2313
2314 /* 2 - disable MGLS in RLC */
2315 data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_MEM_SLP_CNTL));
2316 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) {
2317 data &= ~RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK;
2318 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_MEM_SLP_CNTL), data);
2319 }
2320
2321 /* 3 - disable MGLS in CP */
2322 data = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_MEM_SLP_CNTL));
2323 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) {
2324 data &= ~CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
2325 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_MEM_SLP_CNTL), data);
2326 }
2327 }
2328}
2329
2330static void gfx_v9_0_update_3d_clock_gating(struct amdgpu_device *adev,
2331 bool enable)
2332{
2333 uint32_t data, def;
2334
2335 adev->gfx.rlc.funcs->enter_safe_mode(adev);
2336
2337 /* Enable 3D CGCG/CGLS */
2338 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG)) {
2339 /* write cmd to clear cgcg/cgls ov */
2340 def = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE));
2341 /* unset CGCG override */
2342 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_GFX3D_CG_OVERRIDE_MASK;
2343 /* update CGCG and CGLS override bits */
2344 if (def != data)
2345 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE), data);
2346 /* enable 3Dcgcg FSM(0x0020003f) */
2347 def = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D));
2348 data = (0x2000 << RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD__SHIFT) |
2349 RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK;
2350 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS)
2351 data |= (0x000F << RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY__SHIFT) |
2352 RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK;
2353 if (def != data)
2354 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D), data);
2355
2356 /* set IDLE_POLL_COUNT(0x00900100) */
2357 def = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB_WPTR_POLL_CNTL));
2358 data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) |
2359 (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT);
2360 if (def != data)
2361 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB_WPTR_POLL_CNTL), data);
2362 } else {
2363 /* Disable CGCG/CGLS */
2364 def = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D));
2365 /* disable cgcg, cgls should be disabled */
2366 data &= ~(RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK |
2367 RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK);
2368 /* disable cgcg and cgls in FSM */
2369 if (def != data)
2370 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D), data);
2371 }
2372
2373 adev->gfx.rlc.funcs->exit_safe_mode(adev);
2374}
2375
2376static void gfx_v9_0_update_coarse_grain_clock_gating(struct amdgpu_device *adev,
2377 bool enable)
2378{
2379 uint32_t def, data;
2380
2381 adev->gfx.rlc.funcs->enter_safe_mode(adev);
2382
2383 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)) {
2384 def = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE));
2385 /* unset CGCG override */
2386 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE_MASK;
2387 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS)
2388 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK;
2389 else
2390 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK;
2391 /* update CGCG and CGLS override bits */
2392 if (def != data)
2393 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE), data);
2394
2395 /* enable cgcg FSM(0x0020003F) */
2396 def = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CGCG_CGLS_CTRL));
2397 data = (0x2000 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) |
2398 RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK;
2399 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS)
2400 data |= (0x000F << RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT) |
2401 RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK;
2402 if (def != data)
2403 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CGCG_CGLS_CTRL), data);
2404
2405 /* set IDLE_POLL_COUNT(0x00900100) */
2406 def = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB_WPTR_POLL_CNTL));
2407 data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) |
2408 (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT);
2409 if (def != data)
2410 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB_WPTR_POLL_CNTL), data);
2411 } else {
2412 def = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CGCG_CGLS_CTRL));
2413 /* reset CGCG/CGLS bits */
2414 data &= ~(RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK);
2415 /* disable cgcg and cgls in FSM */
2416 if (def != data)
2417 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CGCG_CGLS_CTRL), data);
2418 }
2419
2420 adev->gfx.rlc.funcs->exit_safe_mode(adev);
2421}
2422
2423static int gfx_v9_0_update_gfx_clock_gating(struct amdgpu_device *adev,
2424 bool enable)
2425{
2426 if (enable) {
2427 /* CGCG/CGLS should be enabled after MGCG/MGLS
2428 * === MGCG + MGLS ===
2429 */
2430 gfx_v9_0_update_medium_grain_clock_gating(adev, enable);
2431 /* === CGCG /CGLS for GFX 3D Only === */
2432 gfx_v9_0_update_3d_clock_gating(adev, enable);
2433 /* === CGCG + CGLS === */
2434 gfx_v9_0_update_coarse_grain_clock_gating(adev, enable);
2435 } else {
2436 /* CGCG/CGLS should be disabled before MGCG/MGLS
2437 * === CGCG + CGLS ===
2438 */
2439 gfx_v9_0_update_coarse_grain_clock_gating(adev, enable);
2440 /* === CGCG /CGLS for GFX 3D Only === */
2441 gfx_v9_0_update_3d_clock_gating(adev, enable);
2442 /* === MGCG + MGLS === */
2443 gfx_v9_0_update_medium_grain_clock_gating(adev, enable);
2444 }
2445 return 0;
2446}
2447
2448static const struct amdgpu_rlc_funcs gfx_v9_0_rlc_funcs = {
2449 .enter_safe_mode = gfx_v9_0_enter_rlc_safe_mode,
2450 .exit_safe_mode = gfx_v9_0_exit_rlc_safe_mode
2451};
2452
2453static int gfx_v9_0_set_powergating_state(void *handle,
2454 enum amd_powergating_state state)
2455{
2456 return 0;
2457}
2458
2459static int gfx_v9_0_set_clockgating_state(void *handle,
2460 enum amd_clockgating_state state)
2461{
2462 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2463
2464 switch (adev->asic_type) {
2465 case CHIP_VEGA10:
2466 gfx_v9_0_update_gfx_clock_gating(adev,
2467 state == AMD_CG_STATE_GATE ? true : false);
2468 break;
2469 default:
2470 break;
2471 }
2472 return 0;
2473}
2474
2475static u64 gfx_v9_0_ring_get_rptr_gfx(struct amdgpu_ring *ring)
2476{
2477 return ring->adev->wb.wb[ring->rptr_offs]; /* gfx9 is 32bit rptr*/
2478}
2479
2480static u64 gfx_v9_0_ring_get_wptr_gfx(struct amdgpu_ring *ring)
2481{
2482 struct amdgpu_device *adev = ring->adev;
2483 u64 wptr;
2484
2485 /* XXX check if swapping is necessary on BE */
2486 if (ring->use_doorbell) {
2487 wptr = atomic64_read((atomic64_t *)&adev->wb.wb[ring->wptr_offs]);
2488 } else {
2489 wptr = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB0_WPTR));
2490 wptr += (u64)RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB0_WPTR_HI)) << 32;
2491 }
2492
2493 return wptr;
2494}
2495
2496static void gfx_v9_0_ring_set_wptr_gfx(struct amdgpu_ring *ring)
2497{
2498 struct amdgpu_device *adev = ring->adev;
2499
2500 if (ring->use_doorbell) {
2501 /* XXX check if swapping is necessary on BE */
2502 atomic64_set((atomic64_t*)&adev->wb.wb[ring->wptr_offs], ring->wptr);
2503 WDOORBELL64(ring->doorbell_index, ring->wptr);
2504 } else {
2505 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB0_WPTR), lower_32_bits(ring->wptr));
2506 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB0_WPTR_HI), upper_32_bits(ring->wptr));
2507 }
2508}
2509
2510static void gfx_v9_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
2511{
2512 u32 ref_and_mask, reg_mem_engine;
2513 struct nbio_hdp_flush_reg *nbio_hf_reg;
2514
2515 if (ring->adev->asic_type == CHIP_VEGA10)
2516 nbio_hf_reg = &nbio_v6_1_hdp_flush_reg;
2517
2518 if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) {
2519 switch (ring->me) {
2520 case 1:
2521 ref_and_mask = nbio_hf_reg->ref_and_mask_cp2 << ring->pipe;
2522 break;
2523 case 2:
2524 ref_and_mask = nbio_hf_reg->ref_and_mask_cp6 << ring->pipe;
2525 break;
2526 default:
2527 return;
2528 }
2529 reg_mem_engine = 0;
2530 } else {
2531 ref_and_mask = nbio_hf_reg->ref_and_mask_cp0;
2532 reg_mem_engine = 1; /* pfp */
2533 }
2534
2535 gfx_v9_0_wait_reg_mem(ring, reg_mem_engine, 0, 1,
2536 nbio_hf_reg->hdp_flush_req_offset,
2537 nbio_hf_reg->hdp_flush_done_offset,
2538 ref_and_mask, ref_and_mask, 0x20);
2539}
2540
2541static void gfx_v9_0_ring_emit_hdp_invalidate(struct amdgpu_ring *ring)
2542{
2543 gfx_v9_0_write_data_to_reg(ring, 0, true,
2544 SOC15_REG_OFFSET(HDP, 0, mmHDP_DEBUG0), 1);
2545}
2546
2547static void gfx_v9_0_ring_emit_ib_gfx(struct amdgpu_ring *ring,
2548 struct amdgpu_ib *ib,
2549 unsigned vm_id, bool ctx_switch)
2550{
2551 u32 header, control = 0;
2552
2553 if (ib->flags & AMDGPU_IB_FLAG_CE)
2554 header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2);
2555 else
2556 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);
2557
2558 control |= ib->length_dw | (vm_id << 24);
2559
2560 amdgpu_ring_write(ring, header);
2561 BUG_ON(ib->gpu_addr & 0x3); /* Dword align */
2562 amdgpu_ring_write(ring,
2563#ifdef __BIG_ENDIAN
2564 (2 << 0) |
2565#endif
2566 lower_32_bits(ib->gpu_addr));
2567 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
2568 amdgpu_ring_write(ring, control);
2569}
2570
2571#define INDIRECT_BUFFER_VALID (1 << 23)
2572
2573static void gfx_v9_0_ring_emit_ib_compute(struct amdgpu_ring *ring,
2574 struct amdgpu_ib *ib,
2575 unsigned vm_id, bool ctx_switch)
2576{
2577 u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vm_id << 24);
2578
2579 amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
2580 BUG_ON(ib->gpu_addr & 0x3); /* Dword align */
2581 amdgpu_ring_write(ring,
2582#ifdef __BIG_ENDIAN
2583 (2 << 0) |
2584#endif
2585 lower_32_bits(ib->gpu_addr));
2586 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
2587 amdgpu_ring_write(ring, control);
2588}
2589
2590static void gfx_v9_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr,
2591 u64 seq, unsigned flags)
2592{
2593 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
2594 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT;
2595
2596 /* RELEASE_MEM - flush caches, send int */
2597 amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 6));
2598 amdgpu_ring_write(ring, (EOP_TCL1_ACTION_EN |
2599 EOP_TC_ACTION_EN |
2600 EOP_TC_WB_ACTION_EN |
2601 EOP_TC_MD_ACTION_EN |
2602 EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |
2603 EVENT_INDEX(5)));
2604 amdgpu_ring_write(ring, DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0));
2605
2606 /*
2607 * the address should be Qword aligned if 64bit write, Dword
2608 * aligned if only send 32bit data low (discard data high)
2609 */
2610 if (write64bit)
2611 BUG_ON(addr & 0x7);
2612 else
2613 BUG_ON(addr & 0x3);
2614 amdgpu_ring_write(ring, lower_32_bits(addr));
2615 amdgpu_ring_write(ring, upper_32_bits(addr));
2616 amdgpu_ring_write(ring, lower_32_bits(seq));
2617 amdgpu_ring_write(ring, upper_32_bits(seq));
2618 amdgpu_ring_write(ring, 0);
2619}
2620
2621static void gfx_v9_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
2622{
2623 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
2624 uint32_t seq = ring->fence_drv.sync_seq;
2625 uint64_t addr = ring->fence_drv.gpu_addr;
2626
2627 gfx_v9_0_wait_reg_mem(ring, usepfp, 1, 0,
2628 lower_32_bits(addr), upper_32_bits(addr),
2629 seq, 0xffffffff, 4);
2630}
2631
2632static void gfx_v9_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
2633 unsigned vm_id, uint64_t pd_addr)
2634{
2635 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
2636 unsigned eng = ring->idx;
2637 unsigned i;
2638
2639 pd_addr = pd_addr | 0x1; /* valid bit */
2640 /* now only use physical base address of PDE and valid */
2641 BUG_ON(pd_addr & 0xFFFF00000000003EULL);
2642
2643 for (i = 0; i < AMDGPU_MAX_VMHUBS; ++i) {
2644 struct amdgpu_vmhub *hub = &ring->adev->vmhub[i];
2645 uint32_t req = hub->get_invalidate_req(vm_id);
2646
2647 gfx_v9_0_write_data_to_reg(ring, usepfp, true,
2648 hub->ctx0_ptb_addr_lo32
2649 + (2 * vm_id),
2650 lower_32_bits(pd_addr));
2651
2652 gfx_v9_0_write_data_to_reg(ring, usepfp, true,
2653 hub->ctx0_ptb_addr_hi32
2654 + (2 * vm_id),
2655 upper_32_bits(pd_addr));
2656
2657 gfx_v9_0_write_data_to_reg(ring, usepfp, true,
2658 hub->vm_inv_eng0_req + eng, req);
2659
2660 /* wait for the invalidate to complete */
2661 gfx_v9_0_wait_reg_mem(ring, 0, 0, 0, hub->vm_inv_eng0_ack +
2662 eng, 0, 1 << vm_id, 1 << vm_id, 0x20);
2663 }
2664
2665 /* compute doesn't have PFP */
2666 if (usepfp) {
2667 /* sync PFP to ME, otherwise we might get invalid PFP reads */
2668 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));
2669 amdgpu_ring_write(ring, 0x0);
2670 /* Emits 128 dw nop to prevent CE access VM before vm_flush finish */
2671 amdgpu_ring_insert_nop(ring, 128);
2672 }
2673}
2674
2675static u64 gfx_v9_0_ring_get_rptr_compute(struct amdgpu_ring *ring)
2676{
2677 return ring->adev->wb.wb[ring->rptr_offs]; /* gfx9 hardware is 32bit rptr */
2678}
2679
2680static u64 gfx_v9_0_ring_get_wptr_compute(struct amdgpu_ring *ring)
2681{
2682 u64 wptr;
2683
2684 /* XXX check if swapping is necessary on BE */
2685 if (ring->use_doorbell)
2686 wptr = atomic64_read((atomic64_t *)&ring->adev->wb.wb[ring->wptr_offs]);
2687 else
2688 BUG();
2689 return wptr;
2690}
2691
2692static void gfx_v9_0_ring_set_wptr_compute(struct amdgpu_ring *ring)
2693{
2694 struct amdgpu_device *adev = ring->adev;
2695
2696 /* XXX check if swapping is necessary on BE */
2697 if (ring->use_doorbell) {
2698 atomic64_set((atomic64_t*)&adev->wb.wb[ring->wptr_offs], ring->wptr);
2699 WDOORBELL64(ring->doorbell_index, ring->wptr);
2700 } else{
2701 BUG(); /* only DOORBELL method supported on gfx9 now */
2702 }
2703}
2704
aa6faa44
XY		 2705static void gfx_v9_0_ring_emit_fence_kiq(struct amdgpu_ring *ring, u64 addr,
2706 u64 seq, unsigned int flags)
2707{
2708 /* we only allocate 32bit for each seq wb address */
2709 BUG_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
2710
2711 /* write fence seq to the "addr" */
2712 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
2713 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
2714 WRITE_DATA_DST_SEL(5) | WR_CONFIRM));
2715 amdgpu_ring_write(ring, lower_32_bits(addr));
2716 amdgpu_ring_write(ring, upper_32_bits(addr));
2717 amdgpu_ring_write(ring, lower_32_bits(seq));
2718
2719 if (flags & AMDGPU_FENCE_FLAG_INT) {
2720 /* set register to trigger INT */
2721 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
2722 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
2723 WRITE_DATA_DST_SEL(0) | WR_CONFIRM));
2724 amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, 0, mmCPC_INT_STATUS));
2725 amdgpu_ring_write(ring, 0);
2726 amdgpu_ring_write(ring, 0x20000000); /* src_id is 178 */
2727 }
2728}
2729
b1023571
KW		 2730static void gfx_v9_ring_emit_sb(struct amdgpu_ring *ring)
2731{
2732 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
2733 amdgpu_ring_write(ring, 0);
2734}
2735
2736static void gfx_v9_ring_emit_cntxcntl(struct amdgpu_ring *ring, uint32_t flags)
2737{
2738 uint32_t dw2 = 0;
2739
2740 dw2 |= 0x80000000; /* set load_enable otherwise this package is just NOPs */
2741 if (flags & AMDGPU_HAVE_CTX_SWITCH) {
2742 /* set load_global_config & load_global_uconfig */
2743 dw2 |= 0x8001;
2744 /* set load_cs_sh_regs */
2745 dw2 |= 0x01000000;
2746 /* set load_per_context_state & load_gfx_sh_regs for GFX */
2747 dw2 |= 0x10002;
2748
2749 /* set load_ce_ram if preamble presented */
2750 if (AMDGPU_PREAMBLE_IB_PRESENT & flags)
2751 dw2 |= 0x10000000;
2752 } else {
2753 /* still load_ce_ram if this is the first time preamble presented
2754 * although there is no context switch happens.
2755 */
2756 if (AMDGPU_PREAMBLE_IB_PRESENT_FIRST & flags)
2757 dw2 |= 0x10000000;
2758 }
2759
2760 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
2761 amdgpu_ring_write(ring, dw2);
2762 amdgpu_ring_write(ring, 0);
2763}
2764
aa6faa44
XY		 2765static void gfx_v9_0_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg)
2766{
2767 struct amdgpu_device *adev = ring->adev;
2768
2769 amdgpu_ring_write(ring, PACKET3(PACKET3_COPY_DATA, 4));
2770 amdgpu_ring_write(ring, 0 | /* src: register*/
2771 (5 << 8) | /* dst: memory */
2772 (1 << 20)); /* write confirm */
2773 amdgpu_ring_write(ring, reg);
2774 amdgpu_ring_write(ring, 0);
2775 amdgpu_ring_write(ring, lower_32_bits(adev->wb.gpu_addr +
2776 adev->virt.reg_val_offs * 4));
2777 amdgpu_ring_write(ring, upper_32_bits(adev->wb.gpu_addr +
2778 adev->virt.reg_val_offs * 4));
2779}
2780
2781static void gfx_v9_0_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg,
2782 uint32_t val)
2783{
2784 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
2785 amdgpu_ring_write(ring, (1 << 16)); /* no inc addr */
2786 amdgpu_ring_write(ring, reg);
2787 amdgpu_ring_write(ring, 0);
2788 amdgpu_ring_write(ring, val);
2789}
2790
b1023571
KW		 2791static void gfx_v9_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev,
2792 enum amdgpu_interrupt_state state)
2793{
2794 u32 cp_int_cntl;
2795
2796 switch (state) {
2797 case AMDGPU_IRQ_STATE_DISABLE:
2798 cp_int_cntl = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING0));
2799 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
2800 TIME_STAMP_INT_ENABLE, 0);
2801 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING0), cp_int_cntl);
2802 break;
2803 case AMDGPU_IRQ_STATE_ENABLE:
2804 cp_int_cntl = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING0));
2805 cp_int_cntl =
2806 REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
2807 TIME_STAMP_INT_ENABLE, 1);
2808 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING0), cp_int_cntl);
2809 break;
2810 default:
2811 break;
2812 }
2813}
2814
2815static void gfx_v9_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev,
2816 int me, int pipe,
2817 enum amdgpu_interrupt_state state)
2818{
2819 u32 mec_int_cntl, mec_int_cntl_reg;
2820
2821 /*
2822 * amdgpu controls only pipe 0 of MEC1. That's why this function only
2823 * handles the setting of interrupts for this specific pipe. All other
2824 * pipes' interrupts are set by amdkfd.
2825 */
2826
2827 if (me == 1) {
2828 switch (pipe) {
2829 case 0:
2830 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL);
2831 break;
2832 default:
2833 DRM_DEBUG("invalid pipe %d\n", pipe);
2834 return;
2835 }
2836 } else {
2837 DRM_DEBUG("invalid me %d\n", me);
2838 return;
2839 }
2840
2841 switch (state) {
2842 case AMDGPU_IRQ_STATE_DISABLE:
2843 mec_int_cntl = RREG32(mec_int_cntl_reg);
2844 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
2845 TIME_STAMP_INT_ENABLE, 0);
2846 WREG32(mec_int_cntl_reg, mec_int_cntl);
2847 break;
2848 case AMDGPU_IRQ_STATE_ENABLE:
2849 mec_int_cntl = RREG32(mec_int_cntl_reg);
2850 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
2851 TIME_STAMP_INT_ENABLE, 1);
2852 WREG32(mec_int_cntl_reg, mec_int_cntl);
2853 break;
2854 default:
2855 break;
2856 }
2857}
2858
2859static int gfx_v9_0_set_priv_reg_fault_state(struct amdgpu_device *adev,
2860 struct amdgpu_irq_src *source,
2861 unsigned type,
2862 enum amdgpu_interrupt_state state)
2863{
2864 u32 cp_int_cntl;
2865
2866 switch (state) {
2867 case AMDGPU_IRQ_STATE_DISABLE:
2868 cp_int_cntl = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING0));
2869 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
2870 PRIV_REG_INT_ENABLE, 0);
2871 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING0), cp_int_cntl);
2872 break;
2873 case AMDGPU_IRQ_STATE_ENABLE:
2874 cp_int_cntl = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING0));
2875 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
2876 PRIV_REG_INT_ENABLE, 1);
2877 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING0), cp_int_cntl);
2878 break;
2879 default:
2880 break;
2881 }
2882
2883 return 0;
2884}
2885
2886static int gfx_v9_0_set_priv_inst_fault_state(struct amdgpu_device *adev,
2887 struct amdgpu_irq_src *source,
2888 unsigned type,
2889 enum amdgpu_interrupt_state state)
2890{
2891 u32 cp_int_cntl;
2892
2893 switch (state) {
2894 case AMDGPU_IRQ_STATE_DISABLE:
2895 cp_int_cntl = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING0));
2896 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
2897 PRIV_INSTR_INT_ENABLE, 0);
2898 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING0), cp_int_cntl);
2899 break;
2900 case AMDGPU_IRQ_STATE_ENABLE:
2901 cp_int_cntl = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING0));
2902 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
2903 PRIV_INSTR_INT_ENABLE, 1);
2904 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING0), cp_int_cntl);
2905 break;
2906 default:
2907 break;
2908 }
2909
2910 return 0;
2911}
2912
2913static int gfx_v9_0_set_eop_interrupt_state(struct amdgpu_device *adev,
2914 struct amdgpu_irq_src *src,
2915 unsigned type,
2916 enum amdgpu_interrupt_state state)
2917{
2918 switch (type) {
2919 case AMDGPU_CP_IRQ_GFX_EOP:
2920 gfx_v9_0_set_gfx_eop_interrupt_state(adev, state);
2921 break;
2922 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP:
2923 gfx_v9_0_set_compute_eop_interrupt_state(adev, 1, 0, state);
2924 break;
2925 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP:
2926 gfx_v9_0_set_compute_eop_interrupt_state(adev, 1, 1, state);
2927 break;
2928 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP:
2929 gfx_v9_0_set_compute_eop_interrupt_state(adev, 1, 2, state);
2930 break;
2931 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP:
2932 gfx_v9_0_set_compute_eop_interrupt_state(adev, 1, 3, state);
2933 break;
2934 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP:
2935 gfx_v9_0_set_compute_eop_interrupt_state(adev, 2, 0, state);
2936 break;
2937 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP:
2938 gfx_v9_0_set_compute_eop_interrupt_state(adev, 2, 1, state);
2939 break;
2940 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP:
2941 gfx_v9_0_set_compute_eop_interrupt_state(adev, 2, 2, state);
2942 break;
2943 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP:
2944 gfx_v9_0_set_compute_eop_interrupt_state(adev, 2, 3, state);
2945 break;
2946 default:
2947 break;
2948 }
2949 return 0;
2950}
2951
2952static int gfx_v9_0_eop_irq(struct amdgpu_device *adev,
2953 struct amdgpu_irq_src *source,
2954 struct amdgpu_iv_entry *entry)
2955{
2956 int i;
2957 u8 me_id, pipe_id, queue_id;
2958 struct amdgpu_ring *ring;
2959
2960 DRM_DEBUG("IH: CP EOP\n");
2961 me_id = (entry->ring_id & 0x0c) >> 2;
2962 pipe_id = (entry->ring_id & 0x03) >> 0;
2963 queue_id = (entry->ring_id & 0x70) >> 4;
2964
2965 switch (me_id) {
2966 case 0:
2967 amdgpu_fence_process(&adev->gfx.gfx_ring[0]);
2968 break;
2969 case 1:
2970 case 2:
2971 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
2972 ring = &adev->gfx.compute_ring[i];
2973 /* Per-queue interrupt is supported for MEC starting from VI.
2974 * The interrupt can only be enabled/disabled per pipe instead of per queue.
2975 */
2976 if ((ring->me == me_id) && (ring->pipe == pipe_id) && (ring->queue == queue_id))
2977 amdgpu_fence_process(ring);
2978 }
2979 break;
2980 }
2981 return 0;
2982}
2983
2984static int gfx_v9_0_priv_reg_irq(struct amdgpu_device *adev,
2985 struct amdgpu_irq_src *source,
2986 struct amdgpu_iv_entry *entry)
2987{
2988 DRM_ERROR("Illegal register access in command stream\n");
2989 schedule_work(&adev->reset_work);
2990 return 0;
2991}
2992
2993static int gfx_v9_0_priv_inst_irq(struct amdgpu_device *adev,
2994 struct amdgpu_irq_src *source,
2995 struct amdgpu_iv_entry *entry)
2996{
2997 DRM_ERROR("Illegal instruction in command stream\n");
2998 schedule_work(&adev->reset_work);
2999 return 0;
3000}
3001
97031e25
XY		 3002static int gfx_v9_0_kiq_set_interrupt_state(struct amdgpu_device *adev,
3003 struct amdgpu_irq_src *src,
3004 unsigned int type,
3005 enum amdgpu_interrupt_state state)
3006{
3007 uint32_t tmp, target;
3008 struct amdgpu_ring *ring = (struct amdgpu_ring *)src->data;
3009
3010 BUG_ON(!ring || (ring->funcs->type != AMDGPU_RING_TYPE_KIQ));
3011
3012 if (ring->me == 1)
3013 target = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL);
3014 else
3015 target = SOC15_REG_OFFSET(GC, 0, mmCP_ME2_PIPE0_INT_CNTL);
3016 target += ring->pipe;
3017
3018 switch (type) {
3019 case AMDGPU_CP_KIQ_IRQ_DRIVER0:
3020 if (state == AMDGPU_IRQ_STATE_DISABLE) {
3021 tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmCPC_INT_CNTL));
3022 tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL,
3023 GENERIC2_INT_ENABLE, 0);
3024 WREG32(SOC15_REG_OFFSET(GC, 0, mmCPC_INT_CNTL), tmp);
3025
3026 tmp = RREG32(target);
3027 tmp = REG_SET_FIELD(tmp, CP_ME2_PIPE0_INT_CNTL,
3028 GENERIC2_INT_ENABLE, 0);
3029 WREG32(target, tmp);
3030 } else {
3031 tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmCPC_INT_CNTL));
3032 tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL,
3033 GENERIC2_INT_ENABLE, 1);
3034 WREG32(SOC15_REG_OFFSET(GC, 0, mmCPC_INT_CNTL), tmp);
3035
3036 tmp = RREG32(target);
3037 tmp = REG_SET_FIELD(tmp, CP_ME2_PIPE0_INT_CNTL,
3038 GENERIC2_INT_ENABLE, 1);
3039 WREG32(target, tmp);
3040 }
3041 break;
3042 default:
3043 BUG(); /* kiq only support GENERIC2_INT now */
3044 break;
3045 }
3046 return 0;
3047}
3048
3049static int gfx_v9_0_kiq_irq(struct amdgpu_device *adev,
3050 struct amdgpu_irq_src *source,
3051 struct amdgpu_iv_entry *entry)
3052{
3053 u8 me_id, pipe_id, queue_id;
3054 struct amdgpu_ring *ring = (struct amdgpu_ring *)source->data;
3055
3056 BUG_ON(!ring || (ring->funcs->type != AMDGPU_RING_TYPE_KIQ));
3057
3058 me_id = (entry->ring_id & 0x0c) >> 2;
3059 pipe_id = (entry->ring_id & 0x03) >> 0;
3060 queue_id = (entry->ring_id & 0x70) >> 4;
3061 DRM_DEBUG("IH: CPC GENERIC2_INT, me:%d, pipe:%d, queue:%d\n",
3062 me_id, pipe_id, queue_id);
3063
3064 amdgpu_fence_process(ring);
3065 return 0;
3066}
3067
b1023571
KW		 3068const struct amd_ip_funcs gfx_v9_0_ip_funcs = {
3069 .name = "gfx_v9_0",
3070 .early_init = gfx_v9_0_early_init,
3071 .late_init = gfx_v9_0_late_init,
3072 .sw_init = gfx_v9_0_sw_init,
3073 .sw_fini = gfx_v9_0_sw_fini,
3074 .hw_init = gfx_v9_0_hw_init,
3075 .hw_fini = gfx_v9_0_hw_fini,
3076 .suspend = gfx_v9_0_suspend,
3077 .resume = gfx_v9_0_resume,
3078 .is_idle = gfx_v9_0_is_idle,
3079 .wait_for_idle = gfx_v9_0_wait_for_idle,
3080 .soft_reset = gfx_v9_0_soft_reset,
3081 .set_clockgating_state = gfx_v9_0_set_clockgating_state,
3082 .set_powergating_state = gfx_v9_0_set_powergating_state,
3083};
3084
3085static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_gfx = {
3086 .type = AMDGPU_RING_TYPE_GFX,
3087 .align_mask = 0xff,
3088 .nop = PACKET3(PACKET3_NOP, 0x3FFF),
3089 .support_64bit_ptrs = true,
3090 .get_rptr = gfx_v9_0_ring_get_rptr_gfx,
3091 .get_wptr = gfx_v9_0_ring_get_wptr_gfx,
3092 .set_wptr = gfx_v9_0_ring_set_wptr_gfx,
3093 .emit_frame_size =
3094 20 + /* gfx_v9_0_ring_emit_gds_switch */
3095 7 + /* gfx_v9_0_ring_emit_hdp_flush */
3096 5 + /* gfx_v9_0_ring_emit_hdp_invalidate */
3097 8 + 8 + 8 +/* gfx_v9_0_ring_emit_fence x3 for user fence, vm fence */
3098 7 + /* gfx_v9_0_ring_emit_pipeline_sync */
3099 128 + 66 + /* gfx_v9_0_ring_emit_vm_flush */
3100 2 + /* gfx_v9_ring_emit_sb */
3101 3, /* gfx_v9_ring_emit_cntxcntl */
3102 .emit_ib_size = 4, /* gfx_v9_0_ring_emit_ib_gfx */
3103 .emit_ib = gfx_v9_0_ring_emit_ib_gfx,
3104 .emit_fence = gfx_v9_0_ring_emit_fence,
3105 .emit_pipeline_sync = gfx_v9_0_ring_emit_pipeline_sync,
3106 .emit_vm_flush = gfx_v9_0_ring_emit_vm_flush,
3107 .emit_gds_switch = gfx_v9_0_ring_emit_gds_switch,
3108 .emit_hdp_flush = gfx_v9_0_ring_emit_hdp_flush,
3109 .emit_hdp_invalidate = gfx_v9_0_ring_emit_hdp_invalidate,
3110 .test_ring = gfx_v9_0_ring_test_ring,
3111 .test_ib = gfx_v9_0_ring_test_ib,
3112 .insert_nop = amdgpu_ring_insert_nop,
3113 .pad_ib = amdgpu_ring_generic_pad_ib,
3114 .emit_switch_buffer = gfx_v9_ring_emit_sb,
3115 .emit_cntxcntl = gfx_v9_ring_emit_cntxcntl,
3116};
3117
3118static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_compute = {
3119 .type = AMDGPU_RING_TYPE_COMPUTE,
3120 .align_mask = 0xff,
3121 .nop = PACKET3(PACKET3_NOP, 0x3FFF),
3122 .support_64bit_ptrs = true,
3123 .get_rptr = gfx_v9_0_ring_get_rptr_compute,
3124 .get_wptr = gfx_v9_0_ring_get_wptr_compute,
3125 .set_wptr = gfx_v9_0_ring_set_wptr_compute,
3126 .emit_frame_size =
3127 20 + /* gfx_v9_0_ring_emit_gds_switch */
3128 7 + /* gfx_v9_0_ring_emit_hdp_flush */
3129 5 + /* gfx_v9_0_ring_emit_hdp_invalidate */
3130 7 + /* gfx_v9_0_ring_emit_pipeline_sync */
3131 64 + /* gfx_v9_0_ring_emit_vm_flush */
3132 8 + 8 + 8, /* gfx_v9_0_ring_emit_fence x3 for user fence, vm fence */
3133 .emit_ib_size = 4, /* gfx_v9_0_ring_emit_ib_compute */
3134 .emit_ib = gfx_v9_0_ring_emit_ib_compute,
3135 .emit_fence = gfx_v9_0_ring_emit_fence,
3136 .emit_pipeline_sync = gfx_v9_0_ring_emit_pipeline_sync,
3137 .emit_vm_flush = gfx_v9_0_ring_emit_vm_flush,
3138 .emit_gds_switch = gfx_v9_0_ring_emit_gds_switch,
3139 .emit_hdp_flush = gfx_v9_0_ring_emit_hdp_flush,
3140 .emit_hdp_invalidate = gfx_v9_0_ring_emit_hdp_invalidate,
3141 .test_ring = gfx_v9_0_ring_test_ring,
3142 .test_ib = gfx_v9_0_ring_test_ib,
3143 .insert_nop = amdgpu_ring_insert_nop,
3144 .pad_ib = amdgpu_ring_generic_pad_ib,
3145};
3146
aa6faa44
XY		 3147static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_kiq = {
3148 .type = AMDGPU_RING_TYPE_KIQ,
3149 .align_mask = 0xff,
3150 .nop = PACKET3(PACKET3_NOP, 0x3FFF),
3151 .support_64bit_ptrs = true,
3152 .get_rptr = gfx_v9_0_ring_get_rptr_compute,
3153 .get_wptr = gfx_v9_0_ring_get_wptr_compute,
3154 .set_wptr = gfx_v9_0_ring_set_wptr_compute,
3155 .emit_frame_size =
3156 20 + /* gfx_v9_0_ring_emit_gds_switch */
3157 7 + /* gfx_v9_0_ring_emit_hdp_flush */
3158 5 + /* gfx_v9_0_ring_emit_hdp_invalidate */
3159 7 + /* gfx_v9_0_ring_emit_pipeline_sync */
3160 64 + /* gfx_v9_0_ring_emit_vm_flush */
3161 8 + 8 + 8, /* gfx_v9_0_ring_emit_fence_kiq x3 for user fence, vm fence */
3162 .emit_ib_size = 4, /* gfx_v9_0_ring_emit_ib_compute */
3163 .emit_ib = gfx_v9_0_ring_emit_ib_compute,
3164 .emit_fence = gfx_v9_0_ring_emit_fence_kiq,
3165 .emit_hdp_flush = gfx_v9_0_ring_emit_hdp_flush,
3166 .emit_hdp_invalidate = gfx_v9_0_ring_emit_hdp_invalidate,
3167 .test_ring = gfx_v9_0_ring_test_ring,
3168 .test_ib = gfx_v9_0_ring_test_ib,
3169 .insert_nop = amdgpu_ring_insert_nop,
3170 .pad_ib = amdgpu_ring_generic_pad_ib,
3171 .emit_rreg = gfx_v9_0_ring_emit_rreg,
3172 .emit_wreg = gfx_v9_0_ring_emit_wreg,
3173};
b1023571
KW		 3174
3175static void gfx_v9_0_set_ring_funcs(struct amdgpu_device *adev)
3176{
3177 int i;
3178
aa6faa44
XY		 3179 adev->gfx.kiq.ring.funcs = &gfx_v9_0_ring_funcs_kiq;
3180
b1023571
KW		 3181 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
3182 adev->gfx.gfx_ring[i].funcs = &gfx_v9_0_ring_funcs_gfx;
3183
3184 for (i = 0; i < adev->gfx.num_compute_rings; i++)
3185 adev->gfx.compute_ring[i].funcs = &gfx_v9_0_ring_funcs_compute;
3186}
3187
97031e25
XY		 3188static const struct amdgpu_irq_src_funcs gfx_v9_0_kiq_irq_funcs = {
3189 .set = gfx_v9_0_kiq_set_interrupt_state,
3190 .process = gfx_v9_0_kiq_irq,
3191};
3192
b1023571
KW		 3193static const struct amdgpu_irq_src_funcs gfx_v9_0_eop_irq_funcs = {
3194 .set = gfx_v9_0_set_eop_interrupt_state,
3195 .process = gfx_v9_0_eop_irq,
3196};
3197
3198static const struct amdgpu_irq_src_funcs gfx_v9_0_priv_reg_irq_funcs = {
3199 .set = gfx_v9_0_set_priv_reg_fault_state,
3200 .process = gfx_v9_0_priv_reg_irq,
3201};
3202
3203static const struct amdgpu_irq_src_funcs gfx_v9_0_priv_inst_irq_funcs = {
3204 .set = gfx_v9_0_set_priv_inst_fault_state,
3205 .process = gfx_v9_0_priv_inst_irq,
3206};
3207
3208static void gfx_v9_0_set_irq_funcs(struct amdgpu_device *adev)
3209{
3210 adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST;
3211 adev->gfx.eop_irq.funcs = &gfx_v9_0_eop_irq_funcs;
3212
3213 adev->gfx.priv_reg_irq.num_types = 1;
3214 adev->gfx.priv_reg_irq.funcs = &gfx_v9_0_priv_reg_irq_funcs;
3215
3216 adev->gfx.priv_inst_irq.num_types = 1;
3217 adev->gfx.priv_inst_irq.funcs = &gfx_v9_0_priv_inst_irq_funcs;
97031e25
XY		 3218
3219 adev->gfx.kiq.irq.num_types = AMDGPU_CP_KIQ_IRQ_LAST;
3220 adev->gfx.kiq.irq.funcs = &gfx_v9_0_kiq_irq_funcs;
b1023571
KW		 3221}
3222
3223static void gfx_v9_0_set_rlc_funcs(struct amdgpu_device *adev)
3224{
3225 switch (adev->asic_type) {
3226 case CHIP_VEGA10:
3227 adev->gfx.rlc.funcs = &gfx_v9_0_rlc_funcs;
3228 break;
3229 default:
3230 break;
3231 }
3232}
3233
3234static void gfx_v9_0_set_gds_init(struct amdgpu_device *adev)
3235{
3236 /* init asci gds info */
3237 adev->gds.mem.total_size = RREG32(SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_SIZE));
3238 adev->gds.gws.total_size = 64;
3239 adev->gds.oa.total_size = 16;
3240
3241 if (adev->gds.mem.total_size == 64 * 1024) {
3242 adev->gds.mem.gfx_partition_size = 4096;
3243 adev->gds.mem.cs_partition_size = 4096;
3244
3245 adev->gds.gws.gfx_partition_size = 4;
3246 adev->gds.gws.cs_partition_size = 4;
3247
3248 adev->gds.oa.gfx_partition_size = 4;
3249 adev->gds.oa.cs_partition_size = 1;
3250 } else {
3251 adev->gds.mem.gfx_partition_size = 1024;
3252 adev->gds.mem.cs_partition_size = 1024;
3253
3254 adev->gds.gws.gfx_partition_size = 16;
3255 adev->gds.gws.cs_partition_size = 16;
3256
3257 adev->gds.oa.gfx_partition_size = 4;
3258 adev->gds.oa.cs_partition_size = 4;
3259 }
3260}
3261
3262static u32 gfx_v9_0_get_cu_active_bitmap(struct amdgpu_device *adev)
3263{
3264 u32 data, mask;
3265
3266 data = RREG32(SOC15_REG_OFFSET(GC, 0, mmCC_GC_SHADER_ARRAY_CONFIG));
3267 data |= RREG32(SOC15_REG_OFFSET(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG));
3268
3269 data &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK;
3270 data >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT;
3271
3272 mask = gfx_v9_0_create_bitmask(adev->gfx.config.max_cu_per_sh);
3273
3274 return (~data) & mask;
3275}
3276
3277static int gfx_v9_0_get_cu_info(struct amdgpu_device *adev,
3278 struct amdgpu_cu_info *cu_info)
3279{
3280 int i, j, k, counter, active_cu_number = 0;
3281 u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0;
3282
3283 if (!adev || !cu_info)
3284 return -EINVAL;
3285
3286 memset(cu_info, 0, sizeof(*cu_info));
3287
3288 mutex_lock(&adev->grbm_idx_mutex);
3289 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
3290 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
3291 mask = 1;
3292 ao_bitmap = 0;
3293 counter = 0;
3294 gfx_v9_0_select_se_sh(adev, i, j, 0xffffffff);
3295 bitmap = gfx_v9_0_get_cu_active_bitmap(adev);
3296 cu_info->bitmap[i][j] = bitmap;
3297
3298 for (k = 0; k < 16; k ++) {
3299 if (bitmap & mask) {
3300 if (counter < 2)
3301 ao_bitmap |= mask;
3302 counter ++;
3303 }
3304 mask <<= 1;
3305 }
3306 active_cu_number += counter;
3307 ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8));
3308 }
3309 }
3310 gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
3311 mutex_unlock(&adev->grbm_idx_mutex);
3312
3313 cu_info->number = active_cu_number;
3314 cu_info->ao_cu_mask = ao_cu_mask;
3315
3316 return 0;
3317}
3318
3319static int gfx_v9_0_init_queue(struct amdgpu_ring *ring)
3320{
3321 int r, j;
3322 u32 tmp;
3323 bool use_doorbell = true;
3324 u64 hqd_gpu_addr;
3325 u64 mqd_gpu_addr;
3326 u64 eop_gpu_addr;
3327 u64 wb_gpu_addr;
3328 u32 *buf;
3329 struct v9_mqd *mqd;
3330 struct amdgpu_device *adev;
3331
3332 adev = ring->adev;
3333 if (ring->mqd_obj == NULL) {
3334 r = amdgpu_bo_create(adev,
3335 sizeof(struct v9_mqd),
3336 PAGE_SIZE,true,
3337 AMDGPU_GEM_DOMAIN_GTT, 0, NULL,
3338 NULL, &ring->mqd_obj);
3339 if (r) {
3340 dev_warn(adev->dev, "(%d) create MQD bo failed\n", r);
3341 return r;
3342 }
3343 }
3344
3345 r = amdgpu_bo_reserve(ring->mqd_obj, false);
3346 if (unlikely(r != 0)) {
3347 gfx_v9_0_cp_compute_fini(adev);
3348 return r;
3349 }
3350
3351 r = amdgpu_bo_pin(ring->mqd_obj, AMDGPU_GEM_DOMAIN_GTT,
3352 &mqd_gpu_addr);
3353 if (r) {
3354 dev_warn(adev->dev, "(%d) pin MQD bo failed\n", r);
3355 gfx_v9_0_cp_compute_fini(adev);
3356 return r;
3357 }
3358 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&buf);
3359 if (r) {
3360 dev_warn(adev->dev, "(%d) map MQD bo failed\n", r);
3361 gfx_v9_0_cp_compute_fini(adev);
3362 return r;
3363 }
3364
3365 /* init the mqd struct */
3366 memset(buf, 0, sizeof(struct v9_mqd));
3367
3368 mqd = (struct v9_mqd *)buf;
3369 mqd->header = 0xC0310800;
3370 mqd->compute_pipelinestat_enable = 0x00000001;
3371 mqd->compute_static_thread_mgmt_se0 = 0xffffffff;
3372 mqd->compute_static_thread_mgmt_se1 = 0xffffffff;
3373 mqd->compute_static_thread_mgmt_se2 = 0xffffffff;
3374 mqd->compute_static_thread_mgmt_se3 = 0xffffffff;
3375 mqd->compute_misc_reserved = 0x00000003;
3376 mutex_lock(&adev->srbm_mutex);
3377 soc15_grbm_select(adev, ring->me,
3378 ring->pipe,
3379 ring->queue, 0);
3380 /* disable wptr polling */
3381 tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_PQ_WPTR_POLL_CNTL));
3382 tmp = REG_SET_FIELD(tmp, CP_PQ_WPTR_POLL_CNTL, EN, 0);
3383 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_PQ_WPTR_POLL_CNTL), tmp);
3384
3385 /* write the EOP addr */
3386 BUG_ON(ring->me != 1 || ring->pipe != 0); /* can't handle other cases eop address */
3387 eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr + (ring->queue * MEC_HPD_SIZE);
3388 eop_gpu_addr >>= 8;
3389
3390 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_EOP_BASE_ADDR), lower_32_bits(eop_gpu_addr));
3391 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_EOP_BASE_ADDR_HI), upper_32_bits(eop_gpu_addr));
3392 mqd->cp_hqd_eop_base_addr_lo = lower_32_bits(eop_gpu_addr);
3393 mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_gpu_addr);
3394
3395 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
3396 tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_EOP_CONTROL));
3397 tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE,
3398 (order_base_2(MEC_HPD_SIZE / 4) - 1));
3399 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_EOP_CONTROL), tmp);
3400
3401 /* enable doorbell? */
3402 tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL));
3403 if (use_doorbell)
3404 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, DOORBELL_EN, 1);
3405 else
3406 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, DOORBELL_EN, 0);
3407
3408 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL), tmp);
3409 mqd->cp_hqd_pq_doorbell_control = tmp;
3410
3411 /* disable the queue if it's active */
3412 ring->wptr = 0;
3413 mqd->cp_hqd_dequeue_request = 0;
3414 mqd->cp_hqd_pq_rptr = 0;
3415 mqd->cp_hqd_pq_wptr_lo = 0;
3416 mqd->cp_hqd_pq_wptr_hi = 0;
3417 if (RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_ACTIVE)) & 1) {
3418 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_DEQUEUE_REQUEST), 1);
3419 for (j = 0; j < adev->usec_timeout; j++) {
3420 if (!(RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_ACTIVE)) & 1))
3421 break;
3422 udelay(1);
3423 }
3424 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_DEQUEUE_REQUEST), mqd->cp_hqd_dequeue_request);
3425 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_RPTR), mqd->cp_hqd_pq_rptr);
3426 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_LO), mqd->cp_hqd_pq_wptr_lo);
3427 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_HI), mqd->cp_hqd_pq_wptr_hi);
3428 }
3429
3430 /* set the pointer to the MQD */
3431 mqd->cp_mqd_base_addr_lo = mqd_gpu_addr & 0xfffffffc;
3432 mqd->cp_mqd_base_addr_hi = upper_32_bits(mqd_gpu_addr);
3433 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_MQD_BASE_ADDR), mqd->cp_mqd_base_addr_lo);
3434 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_MQD_BASE_ADDR_HI), mqd->cp_mqd_base_addr_hi);
3435
3436 /* set MQD vmid to 0 */
3437 tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_MQD_CONTROL));
3438 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0);
3439 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_MQD_CONTROL), tmp);
3440 mqd->cp_mqd_control = tmp;
3441
3442 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
3443 hqd_gpu_addr = ring->gpu_addr >> 8;
3444 mqd->cp_hqd_pq_base_lo = hqd_gpu_addr;
3445 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr);
3446 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_BASE), mqd->cp_hqd_pq_base_lo);
3447 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_BASE_HI), mqd->cp_hqd_pq_base_hi);
3448
3449 /* set up the HQD, this is similar to CP_RB0_CNTL */
3450 tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_CONTROL));
3451 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE,
3452 (order_base_2(ring->ring_size / 4) - 1));
3453 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE,
3454 ((order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1) << 8));
3455#ifdef __BIG_ENDIAN
3456 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1);
3457#endif
3458 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0);
3459 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ROQ_PQ_IB_FLIP, 0);
3460 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1);
3461 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1);
3462 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_CONTROL), tmp);
3463 mqd->cp_hqd_pq_control = tmp;
3464
3465 /* set the wb address wether it's enabled or not */
3466 wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
3467 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc;
3468 mqd->cp_hqd_pq_rptr_report_addr_hi =
3469 upper_32_bits(wb_gpu_addr) & 0xffff;
3470 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR),
3471 mqd->cp_hqd_pq_rptr_report_addr_lo);
3472 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI),
3473 mqd->cp_hqd_pq_rptr_report_addr_hi);
3474
3475 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
3476 wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
3477 mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc;
3478 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;
3479 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR),
3480 mqd->cp_hqd_pq_wptr_poll_addr_lo);
3481 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI),
3482 mqd->cp_hqd_pq_wptr_poll_addr_hi);
3483
3484 /* enable the doorbell if requested */
3485 if (use_doorbell) {
3486 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_MEC_DOORBELL_RANGE_LOWER),
3487 (AMDGPU_DOORBELL64_KIQ * 2) << 2);
3488 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_MEC_DOORBELL_RANGE_UPPER),
3489 (AMDGPU_DOORBELL64_MEC_RING7 * 2) << 2);
3490 tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL));
3491 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
3492 DOORBELL_OFFSET, ring->doorbell_index);
3493 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, DOORBELL_EN, 1);
3494 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, DOORBELL_SOURCE, 0);
3495 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, DOORBELL_HIT, 0);
3496 mqd->cp_hqd_pq_doorbell_control = tmp;
3497
3498 } else {
3499 mqd->cp_hqd_pq_doorbell_control = 0;
3500 }
3501 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL),
3502 mqd->cp_hqd_pq_doorbell_control);
3503
3504 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
3505 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_LO), mqd->cp_hqd_pq_wptr_lo);
3506 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_HI), mqd->cp_hqd_pq_wptr_hi);
3507
3508 /* set the vmid for the queue */
3509 mqd->cp_hqd_vmid = 0;
3510 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_VMID), mqd->cp_hqd_vmid);
3511
3512 tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PERSISTENT_STATE));
3513 tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x53);
3514 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PERSISTENT_STATE), tmp);
3515 mqd->cp_hqd_persistent_state = tmp;
3516
3517 /* activate the queue */
3518 mqd->cp_hqd_active = 1;
3519 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_ACTIVE), mqd->cp_hqd_active);
3520
3521 soc15_grbm_select(adev, 0, 0, 0, 0);
3522 mutex_unlock(&adev->srbm_mutex);
3523
3524 amdgpu_bo_kunmap(ring->mqd_obj);
3525 amdgpu_bo_unreserve(ring->mqd_obj);
3526
3527 if (use_doorbell) {
3528 tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_PQ_STATUS));
3529 tmp = REG_SET_FIELD(tmp, CP_PQ_STATUS, DOORBELL_ENABLE, 1);
3530 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_PQ_STATUS), tmp);
3531 }
3532
3533 return 0;
3534}
3535
3536const struct amdgpu_ip_block_version gfx_v9_0_ip_block =
3537{
3538 .type = AMD_IP_BLOCK_TYPE_GFX,
3539 .major = 9,
3540 .minor = 0,
3541 .rev = 0,
3542 .funcs = &gfx_v9_0_ip_funcs,
3543};
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