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drm/amdgpu/gfx9: impl gfx9 meta data emit
[mirror_ubuntu-artful-kernel.git] / drivers / gpu / drm / amd / amdgpu / gfx_v9_0.c
CommitLineData
b1023571
KW		 1/*
2 * Copyright 2016 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23#include <linux/firmware.h>
24#include "drmP.h"
25#include "amdgpu.h"
26#include "amdgpu_gfx.h"
27#include "soc15.h"
28#include "soc15d.h"
29
30#include "vega10/soc15ip.h"
31#include "vega10/GC/gc_9_0_offset.h"
32#include "vega10/GC/gc_9_0_sh_mask.h"
33#include "vega10/vega10_enum.h"
34#include "vega10/HDP/hdp_4_0_offset.h"
35
36#include "soc15_common.h"
37#include "clearstate_gfx9.h"
38#include "v9_structs.h"
39
40#define GFX9_NUM_GFX_RINGS 1
41#define GFX9_NUM_COMPUTE_RINGS 8
42#define GFX9_NUM_SE 4
43#define RLCG_UCODE_LOADING_START_ADDRESS 0x2000
44
45MODULE_FIRMWARE("amdgpu/vega10_ce.bin");
46MODULE_FIRMWARE("amdgpu/vega10_pfp.bin");
47MODULE_FIRMWARE("amdgpu/vega10_me.bin");
48MODULE_FIRMWARE("amdgpu/vega10_mec.bin");
49MODULE_FIRMWARE("amdgpu/vega10_mec2.bin");
50MODULE_FIRMWARE("amdgpu/vega10_rlc.bin");
51
52static const struct amdgpu_gds_reg_offset amdgpu_gds_reg_offset[] =
53{
54 {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_SIZE),
55 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID0), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID0)},
56 {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID1_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID1_SIZE),
57 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID1), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID1)},
58 {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID2_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID2_SIZE),
59 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID2), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID2)},
60 {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID3_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID3_SIZE),
61 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID3), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID3)},
62 {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID4_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID4_SIZE),
63 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID4), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID4)},
64 {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID5_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID5_SIZE),
65 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID5), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID5)},
66 {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID6_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID6_SIZE),
67 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID6), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID6)},
68 {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID7_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID7_SIZE),
69 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID7), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID7)},
70 {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID8_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID8_SIZE),
71 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID8), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID8)},
72 {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID9_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID9_SIZE),
73 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID9), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID9)},
74 {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID10_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID10_SIZE),
75 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID10), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID10)},
76 {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID11_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID11_SIZE),
77 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID11), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID11)},
78 {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID12_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID12_SIZE),
79 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID12), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID12)},
80 {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID13_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID13_SIZE),
81 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID13), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID13)},
82 {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID14_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID14_SIZE),
83 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID14), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID14)},
84 {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID15_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID15_SIZE),
85 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID15), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID15)}
86};
87
88static const u32 golden_settings_gc_9_0[] =
89{
90 SOC15_REG_OFFSET(GC, 0, mmDB_DEBUG2), 0xf00ffeff, 0x00000400,
91 SOC15_REG_OFFSET(GC, 0, mmGB_GPU_ID), 0x0000000f, 0x00000000,
92 SOC15_REG_OFFSET(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_3), 0x00000003, 0x82400024,
93 SOC15_REG_OFFSET(GC, 0, mmPA_SC_ENHANCE), 0x3fffffff, 0x00000001,
94 SOC15_REG_OFFSET(GC, 0, mmPA_SC_LINE_STIPPLE_STATE), 0x0000ff0f, 0x00000000,
95 SOC15_REG_OFFSET(GC, 0, mmTA_CNTL_AUX), 0xfffffeef, 0x010b0000,
96 SOC15_REG_OFFSET(GC, 0, mmTCP_CHAN_STEER_HI), 0xffffffff, 0x4a2c0e68,
97 SOC15_REG_OFFSET(GC, 0, mmTCP_CHAN_STEER_LO), 0xffffffff, 0xb5d3f197,
98 SOC15_REG_OFFSET(GC, 0, mmVGT_GS_MAX_WAVE_ID), 0x00000fff, 0x000003ff
99};
100
101static const u32 golden_settings_gc_9_0_vg10[] =
102{
103 SOC15_REG_OFFSET(GC, 0, mmCB_HW_CONTROL), 0x0000f000, 0x00012107,
104 SOC15_REG_OFFSET(GC, 0, mmCB_HW_CONTROL_3), 0x30000000, 0x10000000,
105 SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG), 0xffff77ff, 0x2a114042,
106 SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG_READ), 0xffff77ff, 0x2a114042,
107 SOC15_REG_OFFSET(GC, 0, mmPA_SC_ENHANCE_1), 0x00008000, 0x00048000,
108 SOC15_REG_OFFSET(GC, 0, mmRMI_UTCL1_CNTL2), 0x00030000, 0x00020000,
109 SOC15_REG_OFFSET(GC, 0, mmTD_CNTL), 0x00001800, 0x00000800,
110 SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_1),0x0000000f, 0x00000007
111};
112
113#define VEGA10_GB_ADDR_CONFIG_GOLDEN 0x2a114042
114
115static void gfx_v9_0_set_ring_funcs(struct amdgpu_device *adev);
116static void gfx_v9_0_set_irq_funcs(struct amdgpu_device *adev);
117static void gfx_v9_0_set_gds_init(struct amdgpu_device *adev);
118static void gfx_v9_0_set_rlc_funcs(struct amdgpu_device *adev);
119static int gfx_v9_0_get_cu_info(struct amdgpu_device *adev,
120 struct amdgpu_cu_info *cu_info);
121static uint64_t gfx_v9_0_get_gpu_clock_counter(struct amdgpu_device *adev);
122static void gfx_v9_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, u32 sh_num, u32 instance);
123
124static void gfx_v9_0_init_golden_registers(struct amdgpu_device *adev)
125{
126 switch (adev->asic_type) {
127 case CHIP_VEGA10:
128 amdgpu_program_register_sequence(adev,
129 golden_settings_gc_9_0,
130 (const u32)ARRAY_SIZE(golden_settings_gc_9_0));
131 amdgpu_program_register_sequence(adev,
132 golden_settings_gc_9_0_vg10,
133 (const u32)ARRAY_SIZE(golden_settings_gc_9_0_vg10));
134 break;
135 default:
136 break;
137 }
138}
139
140static void gfx_v9_0_scratch_init(struct amdgpu_device *adev)
141{
142 adev->gfx.scratch.num_reg = 7;
143 adev->gfx.scratch.reg_base = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG0);
144 adev->gfx.scratch.free_mask = (1u << adev->gfx.scratch.num_reg) - 1;
145}
146
147static void gfx_v9_0_write_data_to_reg(struct amdgpu_ring *ring, int eng_sel,
148 bool wc, uint32_t reg, uint32_t val)
149{
150 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
151 amdgpu_ring_write(ring, WRITE_DATA_ENGINE_SEL(eng_sel) |
152 WRITE_DATA_DST_SEL(0) |
153 (wc ? WR_CONFIRM : 0));
154 amdgpu_ring_write(ring, reg);
155 amdgpu_ring_write(ring, 0);
156 amdgpu_ring_write(ring, val);
157}
158
159static void gfx_v9_0_wait_reg_mem(struct amdgpu_ring *ring, int eng_sel,
160 int mem_space, int opt, uint32_t addr0,
161 uint32_t addr1, uint32_t ref, uint32_t mask,
162 uint32_t inv)
163{
164 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
165 amdgpu_ring_write(ring,
166 /* memory (1) or register (0) */
167 (WAIT_REG_MEM_MEM_SPACE(mem_space) |
168 WAIT_REG_MEM_OPERATION(opt) | /* wait */
169 WAIT_REG_MEM_FUNCTION(3) | /* equal */
170 WAIT_REG_MEM_ENGINE(eng_sel)));
171
172 if (mem_space)
173 BUG_ON(addr0 & 0x3); /* Dword align */
174 amdgpu_ring_write(ring, addr0);
175 amdgpu_ring_write(ring, addr1);
176 amdgpu_ring_write(ring, ref);
177 amdgpu_ring_write(ring, mask);
178 amdgpu_ring_write(ring, inv); /* poll interval */
179}
180
181static int gfx_v9_0_ring_test_ring(struct amdgpu_ring *ring)
182{
183 struct amdgpu_device *adev = ring->adev;
184 uint32_t scratch;
185 uint32_t tmp = 0;
186 unsigned i;
187 int r;
188
189 r = amdgpu_gfx_scratch_get(adev, &scratch);
190 if (r) {
191 DRM_ERROR("amdgpu: cp failed to get scratch reg (%d).\n", r);
192 return r;
193 }
194 WREG32(scratch, 0xCAFEDEAD);
195 r = amdgpu_ring_alloc(ring, 3);
196 if (r) {
197 DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n",
198 ring->idx, r);
199 amdgpu_gfx_scratch_free(adev, scratch);
200 return r;
201 }
202 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1));
203 amdgpu_ring_write(ring, (scratch - PACKET3_SET_UCONFIG_REG_START));
204 amdgpu_ring_write(ring, 0xDEADBEEF);
205 amdgpu_ring_commit(ring);
206
207 for (i = 0; i < adev->usec_timeout; i++) {
208 tmp = RREG32(scratch);
209 if (tmp == 0xDEADBEEF)
210 break;
211 DRM_UDELAY(1);
212 }
213 if (i < adev->usec_timeout) {
214 DRM_INFO("ring test on %d succeeded in %d usecs\n",
215 ring->idx, i);
216 } else {
217 DRM_ERROR("amdgpu: ring %d test failed (scratch(0x%04X)=0x%08X)\n",
218 ring->idx, scratch, tmp);
219 r = -EINVAL;
220 }
221 amdgpu_gfx_scratch_free(adev, scratch);
222 return r;
223}
224
225static int gfx_v9_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
226{
227 struct amdgpu_device *adev = ring->adev;
228 struct amdgpu_ib ib;
229 struct dma_fence *f = NULL;
230 uint32_t scratch;
231 uint32_t tmp = 0;
232 long r;
233
234 r = amdgpu_gfx_scratch_get(adev, &scratch);
235 if (r) {
236 DRM_ERROR("amdgpu: failed to get scratch reg (%ld).\n", r);
237 return r;
238 }
239 WREG32(scratch, 0xCAFEDEAD);
240 memset(&ib, 0, sizeof(ib));
241 r = amdgpu_ib_get(adev, NULL, 256, &ib);
242 if (r) {
243 DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r);
244 goto err1;
245 }
246 ib.ptr[0] = PACKET3(PACKET3_SET_UCONFIG_REG, 1);
247 ib.ptr[1] = ((scratch - PACKET3_SET_UCONFIG_REG_START));
248 ib.ptr[2] = 0xDEADBEEF;
249 ib.length_dw = 3;
250
251 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
252 if (r)
253 goto err2;
254
255 r = dma_fence_wait_timeout(f, false, timeout);
256 if (r == 0) {
257 DRM_ERROR("amdgpu: IB test timed out.\n");
258 r = -ETIMEDOUT;
259 goto err2;
260 } else if (r < 0) {
261 DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r);
262 goto err2;
263 }
264 tmp = RREG32(scratch);
265 if (tmp == 0xDEADBEEF) {
266 DRM_INFO("ib test on ring %d succeeded\n", ring->idx);
267 r = 0;
268 } else {
269 DRM_ERROR("amdgpu: ib test failed (scratch(0x%04X)=0x%08X)\n",
270 scratch, tmp);
271 r = -EINVAL;
272 }
273err2:
274 amdgpu_ib_free(adev, &ib, NULL);
275 dma_fence_put(f);
276err1:
277 amdgpu_gfx_scratch_free(adev, scratch);
278 return r;
279}
280
281static int gfx_v9_0_init_microcode(struct amdgpu_device *adev)
282{
283 const char *chip_name;
284 char fw_name[30];
285 int err;
286 struct amdgpu_firmware_info *info = NULL;
287 const struct common_firmware_header *header = NULL;
288 const struct gfx_firmware_header_v1_0 *cp_hdr;
289
290 DRM_DEBUG("\n");
291
292 switch (adev->asic_type) {
293 case CHIP_VEGA10:
294 chip_name = "vega10";
295 break;
296 default:
297 BUG();
298 }
299
300 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_pfp.bin", chip_name);
301 err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev);
302 if (err)
303 goto out;
304 err = amdgpu_ucode_validate(adev->gfx.pfp_fw);
305 if (err)
306 goto out;
307 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data;
308 adev->gfx.pfp_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
309 adev->gfx.pfp_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
310
311 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me.bin", chip_name);
312 err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev);
313 if (err)
314 goto out;
315 err = amdgpu_ucode_validate(adev->gfx.me_fw);
316 if (err)
317 goto out;
318 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data;
319 adev->gfx.me_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
320 adev->gfx.me_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
321
322 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ce.bin", chip_name);
323 err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev);
324 if (err)
325 goto out;
326 err = amdgpu_ucode_validate(adev->gfx.ce_fw);
327 if (err)
328 goto out;
329 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data;
330 adev->gfx.ce_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
331 adev->gfx.ce_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
332
333 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", chip_name);
334 err = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev);
335 if (err)
336 goto out;
337 err = amdgpu_ucode_validate(adev->gfx.rlc_fw);
338 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.rlc_fw->data;
339 adev->gfx.rlc_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
340 adev->gfx.rlc_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
341
342 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec.bin", chip_name);
343 err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev);
344 if (err)
345 goto out;
346 err = amdgpu_ucode_validate(adev->gfx.mec_fw);
347 if (err)
348 goto out;
349 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
350 adev->gfx.mec_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
351 adev->gfx.mec_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
352
353
354 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec2.bin", chip_name);
355 err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev);
356 if (!err) {
357 err = amdgpu_ucode_validate(adev->gfx.mec2_fw);
358 if (err)
359 goto out;
360 cp_hdr = (const struct gfx_firmware_header_v1_0 *)
361 adev->gfx.mec2_fw->data;
362 adev->gfx.mec2_fw_version =
363 le32_to_cpu(cp_hdr->header.ucode_version);
364 adev->gfx.mec2_feature_version =
365 le32_to_cpu(cp_hdr->ucode_feature_version);
366 } else {
367 err = 0;
368 adev->gfx.mec2_fw = NULL;
369 }
370
371 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
372 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_PFP];
373 info->ucode_id = AMDGPU_UCODE_ID_CP_PFP;
374 info->fw = adev->gfx.pfp_fw;
375 header = (const struct common_firmware_header *)info->fw->data;
376 adev->firmware.fw_size +=
377 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
378
379 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_ME];
380 info->ucode_id = AMDGPU_UCODE_ID_CP_ME;
381 info->fw = adev->gfx.me_fw;
382 header = (const struct common_firmware_header *)info->fw->data;
383 adev->firmware.fw_size +=
384 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
385
386 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_CE];
387 info->ucode_id = AMDGPU_UCODE_ID_CP_CE;
388 info->fw = adev->gfx.ce_fw;
389 header = (const struct common_firmware_header *)info->fw->data;
390 adev->firmware.fw_size +=
391 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
392
393 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_G];
394 info->ucode_id = AMDGPU_UCODE_ID_RLC_G;
395 info->fw = adev->gfx.rlc_fw;
396 header = (const struct common_firmware_header *)info->fw->data;
397 adev->firmware.fw_size +=
398 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
399
400 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1];
401 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC1;
402 info->fw = adev->gfx.mec_fw;
403 header = (const struct common_firmware_header *)info->fw->data;
404 cp_hdr = (const struct gfx_firmware_header_v1_0 *)info->fw->data;
405 adev->firmware.fw_size +=
406 ALIGN(le32_to_cpu(header->ucode_size_bytes) - le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE);
407
408 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1_JT];
409 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC1_JT;
410 info->fw = adev->gfx.mec_fw;
411 adev->firmware.fw_size +=
412 ALIGN(le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE);
413
414 if (adev->gfx.mec2_fw) {
415 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC2];
416 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC2;
417 info->fw = adev->gfx.mec2_fw;
418 header = (const struct common_firmware_header *)info->fw->data;
419 cp_hdr = (const struct gfx_firmware_header_v1_0 *)info->fw->data;
420 adev->firmware.fw_size +=
421 ALIGN(le32_to_cpu(header->ucode_size_bytes) - le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE);
422 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC2_JT];
423 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC2_JT;
424 info->fw = adev->gfx.mec2_fw;
425 adev->firmware.fw_size +=
426 ALIGN(le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE);
427 }
428
429 }
430
431out:
432 if (err) {
433 dev_err(adev->dev,
434 "gfx9: Failed to load firmware \"%s\"\n",
435 fw_name);
436 release_firmware(adev->gfx.pfp_fw);
437 adev->gfx.pfp_fw = NULL;
438 release_firmware(adev->gfx.me_fw);
439 adev->gfx.me_fw = NULL;
440 release_firmware(adev->gfx.ce_fw);
441 adev->gfx.ce_fw = NULL;
442 release_firmware(adev->gfx.rlc_fw);
443 adev->gfx.rlc_fw = NULL;
444 release_firmware(adev->gfx.mec_fw);
445 adev->gfx.mec_fw = NULL;
446 release_firmware(adev->gfx.mec2_fw);
447 adev->gfx.mec2_fw = NULL;
448 }
449 return err;
450}
451
452static void gfx_v9_0_mec_fini(struct amdgpu_device *adev)
453{
454 int r;
455
456 if (adev->gfx.mec.hpd_eop_obj) {
457 r = amdgpu_bo_reserve(adev->gfx.mec.hpd_eop_obj, false);
458 if (unlikely(r != 0))
459 dev_warn(adev->dev, "(%d) reserve HPD EOP bo failed\n", r);
460 amdgpu_bo_unpin(adev->gfx.mec.hpd_eop_obj);
461 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj);
462
463 amdgpu_bo_unref(&adev->gfx.mec.hpd_eop_obj);
464 adev->gfx.mec.hpd_eop_obj = NULL;
465 }
466 if (adev->gfx.mec.mec_fw_obj) {
467 r = amdgpu_bo_reserve(adev->gfx.mec.mec_fw_obj, false);
468 if (unlikely(r != 0))
469 dev_warn(adev->dev, "(%d) reserve mec firmware bo failed\n", r);
470 amdgpu_bo_unpin(adev->gfx.mec.mec_fw_obj);
471 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj);
472
473 amdgpu_bo_unref(&adev->gfx.mec.mec_fw_obj);
474 adev->gfx.mec.mec_fw_obj = NULL;
475 }
476}
477
478#define MEC_HPD_SIZE 2048
479
480static int gfx_v9_0_mec_init(struct amdgpu_device *adev)
481{
482 int r;
483 u32 *hpd;
484 const __le32 *fw_data;
485 unsigned fw_size;
486 u32 *fw;
487
488 const struct gfx_firmware_header_v1_0 *mec_hdr;
489
490 /*
491 * we assign only 1 pipe because all other pipes will
492 * be handled by KFD
493 */
494 adev->gfx.mec.num_mec = 1;
495 adev->gfx.mec.num_pipe = 1;
496 adev->gfx.mec.num_queue = adev->gfx.mec.num_mec * adev->gfx.mec.num_pipe * 8;
497
498 if (adev->gfx.mec.hpd_eop_obj == NULL) {
499 r = amdgpu_bo_create(adev,
500 adev->gfx.mec.num_queue * MEC_HPD_SIZE,
501 PAGE_SIZE, true,
502 AMDGPU_GEM_DOMAIN_GTT, 0, NULL, NULL,
503 &adev->gfx.mec.hpd_eop_obj);
504 if (r) {
505 dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r);
506 return r;
507 }
508 }
509
510 r = amdgpu_bo_reserve(adev->gfx.mec.hpd_eop_obj, false);
511 if (unlikely(r != 0)) {
512 gfx_v9_0_mec_fini(adev);
513 return r;
514 }
515 r = amdgpu_bo_pin(adev->gfx.mec.hpd_eop_obj, AMDGPU_GEM_DOMAIN_GTT,
516 &adev->gfx.mec.hpd_eop_gpu_addr);
517 if (r) {
518 dev_warn(adev->dev, "(%d) pin HDP EOP bo failed\n", r);
519 gfx_v9_0_mec_fini(adev);
520 return r;
521 }
522 r = amdgpu_bo_kmap(adev->gfx.mec.hpd_eop_obj, (void **)&hpd);
523 if (r) {
524 dev_warn(adev->dev, "(%d) map HDP EOP bo failed\n", r);
525 gfx_v9_0_mec_fini(adev);
526 return r;
527 }
528
529 memset(hpd, 0, adev->gfx.mec.hpd_eop_obj->tbo.mem.size);
530
531 amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj);
532 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj);
533
534 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
535
536 fw_data = (const __le32 *)
537 (adev->gfx.mec_fw->data +
538 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes));
539 fw_size = le32_to_cpu(mec_hdr->header.ucode_size_bytes) / 4;
540
541 if (adev->gfx.mec.mec_fw_obj == NULL) {
542 r = amdgpu_bo_create(adev,
543 mec_hdr->header.ucode_size_bytes,
544 PAGE_SIZE, true,
545 AMDGPU_GEM_DOMAIN_GTT, 0, NULL, NULL,
546 &adev->gfx.mec.mec_fw_obj);
547 if (r) {
548 dev_warn(adev->dev, "(%d) create mec firmware bo failed\n", r);
549 return r;
550 }
551 }
552
553 r = amdgpu_bo_reserve(adev->gfx.mec.mec_fw_obj, false);
554 if (unlikely(r != 0)) {
555 gfx_v9_0_mec_fini(adev);
556 return r;
557 }
558 r = amdgpu_bo_pin(adev->gfx.mec.mec_fw_obj, AMDGPU_GEM_DOMAIN_GTT,
559 &adev->gfx.mec.mec_fw_gpu_addr);
560 if (r) {
561 dev_warn(adev->dev, "(%d) pin mec firmware bo failed\n", r);
562 gfx_v9_0_mec_fini(adev);
563 return r;
564 }
565 r = amdgpu_bo_kmap(adev->gfx.mec.mec_fw_obj, (void **)&fw);
566 if (r) {
567 dev_warn(adev->dev, "(%d) map firmware bo failed\n", r);
568 gfx_v9_0_mec_fini(adev);
569 return r;
570 }
571 memcpy(fw, fw_data, fw_size);
572
573 amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj);
574 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj);
575
576
577 return 0;
578}
579
ac104e99
XY		 580static void gfx_v9_0_kiq_fini(struct amdgpu_device *adev)
581{
582 struct amdgpu_kiq *kiq = &adev->gfx.kiq;
583
584 amdgpu_bo_free_kernel(&kiq->eop_obj, &kiq->eop_gpu_addr, NULL);
585}
586
587static int gfx_v9_0_kiq_init(struct amdgpu_device *adev)
588{
589 int r;
590 u32 *hpd;
591 struct amdgpu_kiq *kiq = &adev->gfx.kiq;
592
593 r = amdgpu_bo_create_kernel(adev, MEC_HPD_SIZE, PAGE_SIZE,
594 AMDGPU_GEM_DOMAIN_GTT, &kiq->eop_obj,
595 &kiq->eop_gpu_addr, (void **)&hpd);
596 if (r) {
597 dev_warn(adev->dev, "failed to create KIQ bo (%d).\n", r);
598 return r;
599 }
600
601 memset(hpd, 0, MEC_HPD_SIZE);
602
603 amdgpu_bo_kunmap(kiq->eop_obj);
604
605 return 0;
606}
607
608static int gfx_v9_0_kiq_init_ring(struct amdgpu_device *adev,
609 struct amdgpu_ring *ring,
610 struct amdgpu_irq_src *irq)
611{
612 int r = 0;
613
614 r = amdgpu_wb_get(adev, &adev->virt.reg_val_offs);
615 if (r)
616 return r;
617
618 ring->adev = NULL;
619 ring->ring_obj = NULL;
620 ring->use_doorbell = true;
621 ring->doorbell_index = AMDGPU_DOORBELL_KIQ;
622 if (adev->gfx.mec2_fw) {
623 ring->me = 2;
624 ring->pipe = 0;
625 } else {
626 ring->me = 1;
627 ring->pipe = 1;
628 }
629
630 irq->data = ring;
631 ring->queue = 0;
632 sprintf(ring->name, "kiq %d.%d.%d", ring->me, ring->pipe, ring->queue);
633 r = amdgpu_ring_init(adev, ring, 1024,
634 irq, AMDGPU_CP_KIQ_IRQ_DRIVER0);
635 if (r)
636 dev_warn(adev->dev, "(%d) failed to init kiq ring\n", r);
637
638 return r;
639}
640static void gfx_v9_0_kiq_free_ring(struct amdgpu_ring *ring,
641 struct amdgpu_irq_src *irq)
642{
643 amdgpu_wb_free(ring->adev, ring->adev->virt.reg_val_offs);
644 amdgpu_ring_fini(ring);
645 irq->data = NULL;
646}
647
464826d6
XY		 648/* create MQD for each compute queue */
649static int gfx_v9_0_compute_mqd_soft_init(struct amdgpu_device *adev)
650{
651 struct amdgpu_ring *ring = NULL;
652 int r, i;
653
654 /* create MQD for KIQ */
655 ring = &adev->gfx.kiq.ring;
656 if (!ring->mqd_obj) {
657 r = amdgpu_bo_create_kernel(adev, sizeof(struct v9_mqd), PAGE_SIZE,
658 AMDGPU_GEM_DOMAIN_GTT, &ring->mqd_obj,
659 &ring->mqd_gpu_addr, (void **)&ring->mqd_ptr);
660 if (r) {
661 dev_warn(adev->dev, "failed to create ring mqd ob (%d)", r);
662 return r;
663 }
664
665 /*TODO: prepare MQD backup */
666 }
667
668 /* create MQD for each KCQ */
669 for (i = 0; i < adev->gfx.num_compute_rings; i++)
670 {
671 ring = &adev->gfx.compute_ring[i];
672 if (!ring->mqd_obj) {
673 r = amdgpu_bo_create_kernel(adev, sizeof(struct v9_mqd), PAGE_SIZE,
674 AMDGPU_GEM_DOMAIN_GTT, &ring->mqd_obj,
675 &ring->mqd_gpu_addr, (void **)&ring->mqd_ptr);
676 if (r) {
677 dev_warn(adev->dev, "failed to create ring mqd ob (%d)", r);
678 return r;
679 }
680
681 /* TODO: prepare MQD backup */
682 }
683 }
684
685 return 0;
686}
687
688static void gfx_v9_0_compute_mqd_soft_fini(struct amdgpu_device *adev)
689{
690 struct amdgpu_ring *ring = NULL;
691 int i;
692
693 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
694 ring = &adev->gfx.compute_ring[i];
695 amdgpu_bo_free_kernel(&ring->mqd_obj, &ring->mqd_gpu_addr, (void **)&ring->mqd_ptr);
696 }
697
698 ring = &adev->gfx.kiq.ring;
699 amdgpu_bo_free_kernel(&ring->mqd_obj, &ring->mqd_gpu_addr, (void **)&ring->mqd_ptr);
700}
701
b1023571
KW		 702static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t address)
703{
704 WREG32(SOC15_REG_OFFSET(GC, 0, mmSQ_IND_INDEX),
705 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
706 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) |
707 (address << SQ_IND_INDEX__INDEX__SHIFT) |
708 (SQ_IND_INDEX__FORCE_READ_MASK));
709 return RREG32(SOC15_REG_OFFSET(GC, 0, mmSQ_IND_DATA));
710}
711
712static void wave_read_regs(struct amdgpu_device *adev, uint32_t simd,
713 uint32_t wave, uint32_t thread,
714 uint32_t regno, uint32_t num, uint32_t *out)
715{
716 WREG32(SOC15_REG_OFFSET(GC, 0, mmSQ_IND_INDEX),
717 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
718 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) |
719 (regno << SQ_IND_INDEX__INDEX__SHIFT) |
720 (thread << SQ_IND_INDEX__THREAD_ID__SHIFT) |
721 (SQ_IND_INDEX__FORCE_READ_MASK) |
722 (SQ_IND_INDEX__AUTO_INCR_MASK));
723 while (num--)
724 *(out++) = RREG32(SOC15_REG_OFFSET(GC, 0, mmSQ_IND_DATA));
725}
726
727static void gfx_v9_0_read_wave_data(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields)
728{
729 /* type 1 wave data */
730 dst[(*no_fields)++] = 1;
731 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_STATUS);
732 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_LO);
733 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_HI);
734 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_LO);
735 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_HI);
736 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_HW_ID);
737 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW0);
738 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW1);
739 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_GPR_ALLOC);
740 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_LDS_ALLOC);
741 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TRAPSTS);
742 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_STS);
743 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_DBG0);
744 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_M0);
745}
746
747static void gfx_v9_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t simd,
748 uint32_t wave, uint32_t start,
749 uint32_t size, uint32_t *dst)
750{
751 wave_read_regs(
752 adev, simd, wave, 0,
753 start + SQIND_WAVE_SGPRS_OFFSET, size, dst);
754}
755
756
757static const struct amdgpu_gfx_funcs gfx_v9_0_gfx_funcs = {
758 .get_gpu_clock_counter = &gfx_v9_0_get_gpu_clock_counter,
759 .select_se_sh = &gfx_v9_0_select_se_sh,
760 .read_wave_data = &gfx_v9_0_read_wave_data,
761 .read_wave_sgprs = &gfx_v9_0_read_wave_sgprs,
762};
763
764static void gfx_v9_0_gpu_early_init(struct amdgpu_device *adev)
765{
766 u32 gb_addr_config;
767
768 adev->gfx.funcs = &gfx_v9_0_gfx_funcs;
769
770 switch (adev->asic_type) {
771 case CHIP_VEGA10:
772 adev->gfx.config.max_shader_engines = 4;
773 adev->gfx.config.max_tile_pipes = 8; //??
774 adev->gfx.config.max_cu_per_sh = 16;
775 adev->gfx.config.max_sh_per_se = 1;
776 adev->gfx.config.max_backends_per_se = 4;
777 adev->gfx.config.max_texture_channel_caches = 16;
778 adev->gfx.config.max_gprs = 256;
779 adev->gfx.config.max_gs_threads = 32;
780 adev->gfx.config.max_hw_contexts = 8;
781
782 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
783 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
784 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
785 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
786 gb_addr_config = VEGA10_GB_ADDR_CONFIG_GOLDEN;
787 break;
788 default:
789 BUG();
790 break;
791 }
792
793 adev->gfx.config.gb_addr_config = gb_addr_config;
794
795 adev->gfx.config.gb_addr_config_fields.num_pipes = 1 <<
796 REG_GET_FIELD(
797 adev->gfx.config.gb_addr_config,
798 GB_ADDR_CONFIG,
799 NUM_PIPES);
800 adev->gfx.config.gb_addr_config_fields.num_banks = 1 <<
801 REG_GET_FIELD(
802 adev->gfx.config.gb_addr_config,
803 GB_ADDR_CONFIG,
804 NUM_BANKS);
805 adev->gfx.config.gb_addr_config_fields.max_compress_frags = 1 <<
806 REG_GET_FIELD(
807 adev->gfx.config.gb_addr_config,
808 GB_ADDR_CONFIG,
809 MAX_COMPRESSED_FRAGS);
810 adev->gfx.config.gb_addr_config_fields.num_rb_per_se = 1 <<
811 REG_GET_FIELD(
812 adev->gfx.config.gb_addr_config,
813 GB_ADDR_CONFIG,
814 NUM_RB_PER_SE);
815 adev->gfx.config.gb_addr_config_fields.num_se = 1 <<
816 REG_GET_FIELD(
817 adev->gfx.config.gb_addr_config,
818 GB_ADDR_CONFIG,
819 NUM_SHADER_ENGINES);
820 adev->gfx.config.gb_addr_config_fields.pipe_interleave_size = 1 << (8 +
821 REG_GET_FIELD(
822 adev->gfx.config.gb_addr_config,
823 GB_ADDR_CONFIG,
824 PIPE_INTERLEAVE_SIZE));
825}
826
827static int gfx_v9_0_ngg_create_buf(struct amdgpu_device *adev,
828 struct amdgpu_ngg_buf *ngg_buf,
829 int size_se,
830 int default_size_se)
831{
832 int r;
833
834 if (size_se < 0) {
835 dev_err(adev->dev, "Buffer size is invalid: %d\n", size_se);
836 return -EINVAL;
837 }
838 size_se = size_se ? size_se : default_size_se;
839
840 ngg_buf->size = size_se * GFX9_NUM_SE;
841 r = amdgpu_bo_create_kernel(adev, ngg_buf->size,
842 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM,
843 &ngg_buf->bo,
844 &ngg_buf->gpu_addr,
845 NULL);
846 if (r) {
847 dev_err(adev->dev, "(%d) failed to create NGG buffer\n", r);
848 return r;
849 }
850 ngg_buf->bo_size = amdgpu_bo_size(ngg_buf->bo);
851
852 return r;
853}
854
855static int gfx_v9_0_ngg_fini(struct amdgpu_device *adev)
856{
857 int i;
858
859 for (i = 0; i < NGG_BUF_MAX; i++)
860 amdgpu_bo_free_kernel(&adev->gfx.ngg.buf[i].bo,
861 &adev->gfx.ngg.buf[i].gpu_addr,
862 NULL);
863
864 memset(&adev->gfx.ngg.buf[0], 0,
865 sizeof(struct amdgpu_ngg_buf) * NGG_BUF_MAX);
866
867 adev->gfx.ngg.init = false;
868
869 return 0;
870}
871
872static int gfx_v9_0_ngg_init(struct amdgpu_device *adev)
873{
874 int r;
875
876 if (!amdgpu_ngg || adev->gfx.ngg.init == true)
877 return 0;
878
879 /* GDS reserve memory: 64 bytes alignment */
880 adev->gfx.ngg.gds_reserve_size = ALIGN(5 * 4, 0x40);
881 adev->gds.mem.total_size -= adev->gfx.ngg.gds_reserve_size;
882 adev->gds.mem.gfx_partition_size -= adev->gfx.ngg.gds_reserve_size;
883 adev->gfx.ngg.gds_reserve_addr = amdgpu_gds_reg_offset[0].mem_base;
884 adev->gfx.ngg.gds_reserve_addr += adev->gds.mem.gfx_partition_size;
885
886 /* Primitive Buffer */
887 r = gfx_v9_0_ngg_create_buf(adev, &adev->gfx.ngg.buf[PRIM],
888 amdgpu_prim_buf_per_se,
889 64 * 1024);
890 if (r) {
891 dev_err(adev->dev, "Failed to create Primitive Buffer\n");
892 goto err;
893 }
894
895 /* Position Buffer */
896 r = gfx_v9_0_ngg_create_buf(adev, &adev->gfx.ngg.buf[POS],
897 amdgpu_pos_buf_per_se,
898 256 * 1024);
899 if (r) {
900 dev_err(adev->dev, "Failed to create Position Buffer\n");
901 goto err;
902 }
903
904 /* Control Sideband */
905 r = gfx_v9_0_ngg_create_buf(adev, &adev->gfx.ngg.buf[CNTL],
906 amdgpu_cntl_sb_buf_per_se,
907 256);
908 if (r) {
909 dev_err(adev->dev, "Failed to create Control Sideband Buffer\n");
910 goto err;
911 }
912
913 /* Parameter Cache, not created by default */
914 if (amdgpu_param_buf_per_se <= 0)
915 goto out;
916
917 r = gfx_v9_0_ngg_create_buf(adev, &adev->gfx.ngg.buf[PARAM],
918 amdgpu_param_buf_per_se,
919 512 * 1024);
920 if (r) {
921 dev_err(adev->dev, "Failed to create Parameter Cache\n");
922 goto err;
923 }
924
925out:
926 adev->gfx.ngg.init = true;
927 return 0;
928err:
929 gfx_v9_0_ngg_fini(adev);
930 return r;
931}
932
933static int gfx_v9_0_ngg_en(struct amdgpu_device *adev)
934{
935 struct amdgpu_ring *ring = &adev->gfx.gfx_ring[0];
936 int r;
937 u32 data;
938 u32 size;
939 u32 base;
940
941 if (!amdgpu_ngg)
942 return 0;
943
944 /* Program buffer size */
945 data = 0;
946 size = adev->gfx.ngg.buf[PRIM].size / 256;
947 data = REG_SET_FIELD(data, WD_BUF_RESOURCE_1, INDEX_BUF_SIZE, size);
948
949 size = adev->gfx.ngg.buf[POS].size / 256;
950 data = REG_SET_FIELD(data, WD_BUF_RESOURCE_1, POS_BUF_SIZE, size);
951
952 WREG32(SOC15_REG_OFFSET(GC, 0, mmWD_BUF_RESOURCE_1), data);
953
954 data = 0;
955 size = adev->gfx.ngg.buf[CNTL].size / 256;
956 data = REG_SET_FIELD(data, WD_BUF_RESOURCE_2, CNTL_SB_BUF_SIZE, size);
957
958 size = adev->gfx.ngg.buf[PARAM].size / 1024;
959 data = REG_SET_FIELD(data, WD_BUF_RESOURCE_2, PARAM_BUF_SIZE, size);
960
961 WREG32(SOC15_REG_OFFSET(GC, 0, mmWD_BUF_RESOURCE_2), data);
962
963 /* Program buffer base address */
964 base = lower_32_bits(adev->gfx.ngg.buf[PRIM].gpu_addr);
965 data = REG_SET_FIELD(0, WD_INDEX_BUF_BASE, BASE, base);
966 WREG32(SOC15_REG_OFFSET(GC, 0, mmWD_INDEX_BUF_BASE), data);
967
968 base = upper_32_bits(adev->gfx.ngg.buf[PRIM].gpu_addr);
969 data = REG_SET_FIELD(0, WD_INDEX_BUF_BASE_HI, BASE_HI, base);
970 WREG32(SOC15_REG_OFFSET(GC, 0, mmWD_INDEX_BUF_BASE_HI), data);
971
972 base = lower_32_bits(adev->gfx.ngg.buf[POS].gpu_addr);
973 data = REG_SET_FIELD(0, WD_POS_BUF_BASE, BASE, base);
974 WREG32(SOC15_REG_OFFSET(GC, 0, mmWD_POS_BUF_BASE), data);
975
976 base = upper_32_bits(adev->gfx.ngg.buf[POS].gpu_addr);
977 data = REG_SET_FIELD(0, WD_POS_BUF_BASE_HI, BASE_HI, base);
978 WREG32(SOC15_REG_OFFSET(GC, 0, mmWD_POS_BUF_BASE_HI), data);
979
980 base = lower_32_bits(adev->gfx.ngg.buf[CNTL].gpu_addr);
981 data = REG_SET_FIELD(0, WD_CNTL_SB_BUF_BASE, BASE, base);
982 WREG32(SOC15_REG_OFFSET(GC, 0, mmWD_CNTL_SB_BUF_BASE), data);
983
984 base = upper_32_bits(adev->gfx.ngg.buf[CNTL].gpu_addr);
985 data = REG_SET_FIELD(0, WD_CNTL_SB_BUF_BASE_HI, BASE_HI, base);
986 WREG32(SOC15_REG_OFFSET(GC, 0, mmWD_CNTL_SB_BUF_BASE_HI), data);
987
988 /* Clear GDS reserved memory */
989 r = amdgpu_ring_alloc(ring, 17);
990 if (r) {
991 DRM_ERROR("amdgpu: NGG failed to lock ring %d (%d).\n",
992 ring->idx, r);
993 return r;
994 }
995
996 gfx_v9_0_write_data_to_reg(ring, 0, false,
997 amdgpu_gds_reg_offset[0].mem_size,
998 (adev->gds.mem.total_size +
999 adev->gfx.ngg.gds_reserve_size) >>
1000 AMDGPU_GDS_SHIFT);
1001
1002 amdgpu_ring_write(ring, PACKET3(PACKET3_DMA_DATA, 5));
1003 amdgpu_ring_write(ring, (PACKET3_DMA_DATA_CP_SYNC |
1004 PACKET3_DMA_DATA_SRC_SEL(2)));
1005 amdgpu_ring_write(ring, 0);
1006 amdgpu_ring_write(ring, 0);
1007 amdgpu_ring_write(ring, adev->gfx.ngg.gds_reserve_addr);
1008 amdgpu_ring_write(ring, 0);
1009 amdgpu_ring_write(ring, adev->gfx.ngg.gds_reserve_size);
1010
1011
1012 gfx_v9_0_write_data_to_reg(ring, 0, false,
1013 amdgpu_gds_reg_offset[0].mem_size, 0);
1014
1015 amdgpu_ring_commit(ring);
1016
1017 return 0;
1018}
1019
1020static int gfx_v9_0_sw_init(void *handle)
1021{
1022 int i, r;
1023 struct amdgpu_ring *ring;
ac104e99 1024 struct amdgpu_kiq *kiq;
b1023571
KW		 1025 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1026
97031e25
XY		 1027 /* KIQ event */
1028 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_GRBM_CP, 178, &adev->gfx.kiq.irq);
1029 if (r)
1030 return r;
1031
b1023571
KW		 1032 /* EOP Event */
1033 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_GRBM_CP, 181, &adev->gfx.eop_irq);
1034 if (r)
1035 return r;
1036
1037 /* Privileged reg */
1038 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_GRBM_CP, 184,
1039 &adev->gfx.priv_reg_irq);
1040 if (r)
1041 return r;
1042
1043 /* Privileged inst */
1044 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_GRBM_CP, 185,
1045 &adev->gfx.priv_inst_irq);
1046 if (r)
1047 return r;
1048
1049 adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE;
1050
1051 gfx_v9_0_scratch_init(adev);
1052
1053 r = gfx_v9_0_init_microcode(adev);
1054 if (r) {
1055 DRM_ERROR("Failed to load gfx firmware!\n");
1056 return r;
1057 }
1058
1059 r = gfx_v9_0_mec_init(adev);
1060 if (r) {
1061 DRM_ERROR("Failed to init MEC BOs!\n");
1062 return r;
1063 }
1064
1065 /* set up the gfx ring */
1066 for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
1067 ring = &adev->gfx.gfx_ring[i];
1068 ring->ring_obj = NULL;
1069 sprintf(ring->name, "gfx");
1070 ring->use_doorbell = true;
1071 ring->doorbell_index = AMDGPU_DOORBELL64_GFX_RING0 << 1;
1072 r = amdgpu_ring_init(adev, ring, 1024,
1073 &adev->gfx.eop_irq, AMDGPU_CP_IRQ_GFX_EOP);
1074 if (r)
1075 return r;
1076 }
1077
1078 /* set up the compute queues */
1079 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
1080 unsigned irq_type;
1081
1082 /* max 32 queues per MEC */
1083 if ((i >= 32) || (i >= AMDGPU_MAX_COMPUTE_RINGS)) {
1084 DRM_ERROR("Too many (%d) compute rings!\n", i);
1085 break;
1086 }
1087 ring = &adev->gfx.compute_ring[i];
1088 ring->ring_obj = NULL;
1089 ring->use_doorbell = true;
1090 ring->doorbell_index = (AMDGPU_DOORBELL64_MEC_RING0 + i) << 1;
1091 ring->me = 1; /* first MEC */
1092 ring->pipe = i / 8;
1093 ring->queue = i % 8;
1094 sprintf(ring->name, "comp %d.%d.%d", ring->me, ring->pipe, ring->queue);
1095 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP + ring->pipe;
1096 /* type-2 packets are deprecated on MEC, use type-3 instead */
1097 r = amdgpu_ring_init(adev, ring, 1024,
1098 &adev->gfx.eop_irq, irq_type);
1099 if (r)
1100 return r;
1101 }
1102
ac104e99
XY		 1103 if (amdgpu_sriov_vf(adev)) {
1104 r = gfx_v9_0_kiq_init(adev);
1105 if (r) {
1106 DRM_ERROR("Failed to init KIQ BOs!\n");
1107 return r;
1108 }
1109
1110 kiq = &adev->gfx.kiq;
1111 r = gfx_v9_0_kiq_init_ring(adev, &kiq->ring, &kiq->irq);
1112 if (r)
1113 return r;
464826d6
XY		 1114
1115 /* create MQD for all compute queues as wel as KIQ for SRIOV case */
1116 r = gfx_v9_0_compute_mqd_soft_init(adev);
1117 if (r)
1118 return r;
ac104e99
XY		 1119 }
1120
b1023571
KW		 1121 /* reserve GDS, GWS and OA resource for gfx */
1122 r = amdgpu_bo_create_kernel(adev, adev->gds.mem.gfx_partition_size,
1123 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GDS,
1124 &adev->gds.gds_gfx_bo, NULL, NULL);
1125 if (r)
1126 return r;
1127
1128 r = amdgpu_bo_create_kernel(adev, adev->gds.gws.gfx_partition_size,
1129 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GWS,
1130 &adev->gds.gws_gfx_bo, NULL, NULL);
1131 if (r)
1132 return r;
1133
1134 r = amdgpu_bo_create_kernel(adev, adev->gds.oa.gfx_partition_size,
1135 PAGE_SIZE, AMDGPU_GEM_DOMAIN_OA,
1136 &adev->gds.oa_gfx_bo, NULL, NULL);
1137 if (r)
1138 return r;
1139
1140 adev->gfx.ce_ram_size = 0x8000;
1141
1142 gfx_v9_0_gpu_early_init(adev);
1143
1144 r = gfx_v9_0_ngg_init(adev);
1145 if (r)
1146 return r;
1147
1148 return 0;
1149}
1150
1151
1152static int gfx_v9_0_sw_fini(void *handle)
1153{
1154 int i;
1155 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1156
1157 amdgpu_bo_free_kernel(&adev->gds.oa_gfx_bo, NULL, NULL);
1158 amdgpu_bo_free_kernel(&adev->gds.gws_gfx_bo, NULL, NULL);
1159 amdgpu_bo_free_kernel(&adev->gds.gds_gfx_bo, NULL, NULL);
1160
1161 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
1162 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]);
1163 for (i = 0; i < adev->gfx.num_compute_rings; i++)
1164 amdgpu_ring_fini(&adev->gfx.compute_ring[i]);
1165
ac104e99 1166 if (amdgpu_sriov_vf(adev)) {
464826d6 1167 gfx_v9_0_compute_mqd_soft_fini(adev);
ac104e99
XY		 1168 gfx_v9_0_kiq_free_ring(&adev->gfx.kiq.ring, &adev->gfx.kiq.irq);
1169 gfx_v9_0_kiq_fini(adev);
1170 }
1171
b1023571
KW		 1172 gfx_v9_0_mec_fini(adev);
1173 gfx_v9_0_ngg_fini(adev);
1174
1175 return 0;
1176}
1177
1178
1179static void gfx_v9_0_tiling_mode_table_init(struct amdgpu_device *adev)
1180{
1181 /* TODO */
1182}
1183
1184static void gfx_v9_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, u32 sh_num, u32 instance)
1185{
1186 u32 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES, 1);
1187
1188 if ((se_num == 0xffffffff) && (sh_num == 0xffffffff)) {
1189 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_BROADCAST_WRITES, 1);
1190 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES, 1);
1191 } else if (se_num == 0xffffffff) {
1192 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_INDEX, sh_num);
1193 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES, 1);
1194 } else if (sh_num == 0xffffffff) {
1195 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_BROADCAST_WRITES, 1);
1196 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num);
1197 } else {
1198 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_INDEX, sh_num);
1199 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num);
1200 }
1201 WREG32( SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_INDEX), data);
1202}
1203
1204static u32 gfx_v9_0_create_bitmask(u32 bit_width)
1205{
1206 return (u32)((1ULL << bit_width) - 1);
1207}
1208
1209static u32 gfx_v9_0_get_rb_active_bitmap(struct amdgpu_device *adev)
1210{
1211 u32 data, mask;
1212
1213 data = RREG32(SOC15_REG_OFFSET(GC, 0, mmCC_RB_BACKEND_DISABLE));
1214 data |= RREG32(SOC15_REG_OFFSET(GC, 0, mmGC_USER_RB_BACKEND_DISABLE));
1215
1216 data &= CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK;
1217 data >>= GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT;
1218
1219 mask = gfx_v9_0_create_bitmask(adev->gfx.config.max_backends_per_se /
1220 adev->gfx.config.max_sh_per_se);
1221
1222 return (~data) & mask;
1223}
1224
1225static void gfx_v9_0_setup_rb(struct amdgpu_device *adev)
1226{
1227 int i, j;
1228 u32 data, tmp, num_rbs = 0;
1229 u32 active_rbs = 0;
1230 u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se /
1231 adev->gfx.config.max_sh_per_se;
1232
1233 mutex_lock(&adev->grbm_idx_mutex);
1234 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
1235 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
1236 gfx_v9_0_select_se_sh(adev, i, j, 0xffffffff);
1237 data = gfx_v9_0_get_rb_active_bitmap(adev);
1238 active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) *
1239 rb_bitmap_width_per_sh);
1240 }
1241 }
1242 gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
1243 mutex_unlock(&adev->grbm_idx_mutex);
1244
1245 adev->gfx.config.backend_enable_mask = active_rbs;
1246 tmp = active_rbs;
1247 while (tmp >>= 1)
1248 num_rbs++;
1249 adev->gfx.config.num_rbs = num_rbs;
1250}
1251
1252#define DEFAULT_SH_MEM_BASES (0x6000)
1253#define FIRST_COMPUTE_VMID (8)
1254#define LAST_COMPUTE_VMID (16)
1255static void gfx_v9_0_init_compute_vmid(struct amdgpu_device *adev)
1256{
1257 int i;
1258 uint32_t sh_mem_config;
1259 uint32_t sh_mem_bases;
1260
1261 /*
1262 * Configure apertures:
1263 * LDS: 0x60000000'00000000 - 0x60000001'00000000 (4GB)
1264 * Scratch: 0x60000001'00000000 - 0x60000002'00000000 (4GB)
1265 * GPUVM: 0x60010000'00000000 - 0x60020000'00000000 (1TB)
1266 */
1267 sh_mem_bases = DEFAULT_SH_MEM_BASES | (DEFAULT_SH_MEM_BASES << 16);
1268
1269 sh_mem_config = SH_MEM_ADDRESS_MODE_64 |
1270 SH_MEM_ALIGNMENT_MODE_UNALIGNED <<
1271 SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT;
1272
1273 mutex_lock(&adev->srbm_mutex);
1274 for (i = FIRST_COMPUTE_VMID; i < LAST_COMPUTE_VMID; i++) {
1275 soc15_grbm_select(adev, 0, 0, 0, i);
1276 /* CP and shaders */
1277 WREG32(SOC15_REG_OFFSET(GC, 0, mmSH_MEM_CONFIG), sh_mem_config);
1278 WREG32(SOC15_REG_OFFSET(GC, 0, mmSH_MEM_BASES), sh_mem_bases);
1279 }
1280 soc15_grbm_select(adev, 0, 0, 0, 0);
1281 mutex_unlock(&adev->srbm_mutex);
1282}
1283
1284static void gfx_v9_0_gpu_init(struct amdgpu_device *adev)
1285{
1286 u32 tmp;
1287 int i;
1288
1289 tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmGRBM_CNTL));
1290 tmp = REG_SET_FIELD(tmp, GRBM_CNTL, READ_TIMEOUT, 0xff);
1291 WREG32(SOC15_REG_OFFSET(GC, 0, mmGRBM_CNTL), tmp);
1292
1293 gfx_v9_0_tiling_mode_table_init(adev);
1294
1295 gfx_v9_0_setup_rb(adev);
1296 gfx_v9_0_get_cu_info(adev, &adev->gfx.cu_info);
1297
1298 /* XXX SH_MEM regs */
1299 /* where to put LDS, scratch, GPUVM in FSA64 space */
1300 mutex_lock(&adev->srbm_mutex);
1301 for (i = 0; i < 16; i++) {
1302 soc15_grbm_select(adev, 0, 0, 0, i);
1303 /* CP and shaders */
1304 tmp = 0;
1305 tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, ALIGNMENT_MODE,
1306 SH_MEM_ALIGNMENT_MODE_UNALIGNED);
1307 WREG32(SOC15_REG_OFFSET(GC, 0, mmSH_MEM_CONFIG), tmp);
1308 WREG32(SOC15_REG_OFFSET(GC, 0, mmSH_MEM_BASES), 0);
1309 }
1310 soc15_grbm_select(adev, 0, 0, 0, 0);
1311
1312 mutex_unlock(&adev->srbm_mutex);
1313
1314 gfx_v9_0_init_compute_vmid(adev);
1315
1316 mutex_lock(&adev->grbm_idx_mutex);
1317 /*
1318 * making sure that the following register writes will be broadcasted
1319 * to all the shaders
1320 */
1321 gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
1322
1323 WREG32(SOC15_REG_OFFSET(GC, 0, mmPA_SC_FIFO_SIZE),
1324 (adev->gfx.config.sc_prim_fifo_size_frontend <<
1325 PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE__SHIFT) |
1326 (adev->gfx.config.sc_prim_fifo_size_backend <<
1327 PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE__SHIFT) |
1328 (adev->gfx.config.sc_hiz_tile_fifo_size <<
1329 PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE__SHIFT) |
1330 (adev->gfx.config.sc_earlyz_tile_fifo_size <<
1331 PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE__SHIFT));
1332 mutex_unlock(&adev->grbm_idx_mutex);
1333
1334}
1335
1336static void gfx_v9_0_wait_for_rlc_serdes(struct amdgpu_device *adev)
1337{
1338 u32 i, j, k;
1339 u32 mask;
1340
1341 mutex_lock(&adev->grbm_idx_mutex);
1342 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
1343 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
1344 gfx_v9_0_select_se_sh(adev, i, j, 0xffffffff);
1345 for (k = 0; k < adev->usec_timeout; k++) {
1346 if (RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SERDES_CU_MASTER_BUSY)) == 0)
1347 break;
1348 udelay(1);
1349 }
1350 }
1351 }
1352 gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
1353 mutex_unlock(&adev->grbm_idx_mutex);
1354
1355 mask = RLC_SERDES_NONCU_MASTER_BUSY__SE_MASTER_BUSY_MASK |
1356 RLC_SERDES_NONCU_MASTER_BUSY__GC_MASTER_BUSY_MASK |
1357 RLC_SERDES_NONCU_MASTER_BUSY__TC0_MASTER_BUSY_MASK |
1358 RLC_SERDES_NONCU_MASTER_BUSY__TC1_MASTER_BUSY_MASK;
1359 for (k = 0; k < adev->usec_timeout; k++) {
1360 if ((RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SERDES_NONCU_MASTER_BUSY)) & mask) == 0)
1361 break;
1362 udelay(1);
1363 }
1364}
1365
1366static void gfx_v9_0_enable_gui_idle_interrupt(struct amdgpu_device *adev,
1367 bool enable)
1368{
1369 u32 tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING0));
1370
1371 if (enable)
1372 return;
1373
1374 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, enable ? 1 : 0);
1375 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, enable ? 1 : 0);
1376 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, enable ? 1 : 0);
1377 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE, enable ? 1 : 0);
1378
1379 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING0), tmp);
1380}
1381
1382void gfx_v9_0_rlc_stop(struct amdgpu_device *adev)
1383{
1384 u32 tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CNTL));
1385
1386 tmp = REG_SET_FIELD(tmp, RLC_CNTL, RLC_ENABLE_F32, 0);
1387 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CNTL), tmp);
1388
1389 gfx_v9_0_enable_gui_idle_interrupt(adev, false);
1390
1391 gfx_v9_0_wait_for_rlc_serdes(adev);
1392}
1393
1394static void gfx_v9_0_rlc_reset(struct amdgpu_device *adev)
1395{
1396 u32 tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmGRBM_SOFT_RESET));
1397
1398 tmp = REG_SET_FIELD(tmp, GRBM_SOFT_RESET, SOFT_RESET_RLC, 1);
1399 WREG32(SOC15_REG_OFFSET(GC, 0, mmGRBM_SOFT_RESET), tmp);
1400 udelay(50);
1401 tmp = REG_SET_FIELD(tmp, GRBM_SOFT_RESET, SOFT_RESET_RLC, 0);
1402 WREG32(SOC15_REG_OFFSET(GC, 0, mmGRBM_SOFT_RESET), tmp);
1403 udelay(50);
1404}
1405
1406static void gfx_v9_0_rlc_start(struct amdgpu_device *adev)
1407{
1408#ifdef AMDGPU_RLC_DEBUG_RETRY
1409 u32 rlc_ucode_ver;
1410#endif
1411 u32 tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CNTL));
1412
1413 tmp = REG_SET_FIELD(tmp, RLC_CNTL, RLC_ENABLE_F32, 1);
1414 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CNTL), tmp);
1415
1416 /* carrizo do enable cp interrupt after cp inited */
1417 if (!(adev->flags & AMD_IS_APU))
1418 gfx_v9_0_enable_gui_idle_interrupt(adev, true);
1419
1420 udelay(50);
1421
1422#ifdef AMDGPU_RLC_DEBUG_RETRY
1423 /* RLC_GPM_GENERAL_6 : RLC Ucode version */
1424 rlc_ucode_ver = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_GENERAL_6));
1425 if(rlc_ucode_ver == 0x108) {
1426 DRM_INFO("Using rlc debug ucode. mmRLC_GPM_GENERAL_6 ==0x08%x / fw_ver == %i \n",
1427 rlc_ucode_ver, adev->gfx.rlc_fw_version);
1428 /* RLC_GPM_TIMER_INT_3 : Timer interval in RefCLK cycles,
1429 * default is 0x9C4 to create a 100us interval */
1430 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_TIMER_INT_3), 0x9C4);
1431 /* RLC_GPM_GENERAL_12 : Minimum gap between wptr and rptr
1432 * to disable the page fault retry interrupts, default is
1433 * 0x100 (256) */
1434 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_GENERAL_12), 0x100);
1435 }
1436#endif
1437}
1438
1439static int gfx_v9_0_rlc_load_microcode(struct amdgpu_device *adev)
1440{
1441 const struct rlc_firmware_header_v2_0 *hdr;
1442 const __le32 *fw_data;
1443 unsigned i, fw_size;
1444
1445 if (!adev->gfx.rlc_fw)
1446 return -EINVAL;
1447
1448 hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
1449 amdgpu_ucode_print_rlc_hdr(&hdr->header);
1450
1451 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data +
1452 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
1453 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
1454
1455 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UCODE_ADDR),
1456 RLCG_UCODE_LOADING_START_ADDRESS);
1457 for (i = 0; i < fw_size; i++)
1458 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UCODE_DATA), le32_to_cpup(fw_data++));
1459 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UCODE_ADDR), adev->gfx.rlc_fw_version);
1460
1461 return 0;
1462}
1463
1464static int gfx_v9_0_rlc_resume(struct amdgpu_device *adev)
1465{
1466 int r;
1467
1468 gfx_v9_0_rlc_stop(adev);
1469
1470 /* disable CG */
1471 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CGCG_CGLS_CTRL), 0);
1472
1473 /* disable PG */
1474 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), 0);
1475
1476 gfx_v9_0_rlc_reset(adev);
1477
1478 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
1479 /* legacy rlc firmware loading */
1480 r = gfx_v9_0_rlc_load_microcode(adev);
1481 if (r)
1482 return r;
1483 }
1484
1485 gfx_v9_0_rlc_start(adev);
1486
1487 return 0;
1488}
1489
1490static void gfx_v9_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable)
1491{
1492 int i;
1493 u32 tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_ME_CNTL));
1494
1495 if (enable) {
1496 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, 0);
1497 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, 0);
1498 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, 0);
1499 } else {
1500 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, 1);
1501 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, 1);
1502 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, 1);
1503 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
1504 adev->gfx.gfx_ring[i].ready = false;
1505 }
1506 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_ME_CNTL), tmp);
1507 udelay(50);
1508}
1509
1510static int gfx_v9_0_cp_gfx_load_microcode(struct amdgpu_device *adev)
1511{
1512 const struct gfx_firmware_header_v1_0 *pfp_hdr;
1513 const struct gfx_firmware_header_v1_0 *ce_hdr;
1514 const struct gfx_firmware_header_v1_0 *me_hdr;
1515 const __le32 *fw_data;
1516 unsigned i, fw_size;
1517
1518 if (!adev->gfx.me_fw || !adev->gfx.pfp_fw || !adev->gfx.ce_fw)
1519 return -EINVAL;
1520
1521 pfp_hdr = (const struct gfx_firmware_header_v1_0 *)
1522 adev->gfx.pfp_fw->data;
1523 ce_hdr = (const struct gfx_firmware_header_v1_0 *)
1524 adev->gfx.ce_fw->data;
1525 me_hdr = (const struct gfx_firmware_header_v1_0 *)
1526 adev->gfx.me_fw->data;
1527
1528 amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header);
1529 amdgpu_ucode_print_gfx_hdr(&ce_hdr->header);
1530 amdgpu_ucode_print_gfx_hdr(&me_hdr->header);
1531
1532 gfx_v9_0_cp_gfx_enable(adev, false);
1533
1534 /* PFP */
1535 fw_data = (const __le32 *)
1536 (adev->gfx.pfp_fw->data +
1537 le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes));
1538 fw_size = le32_to_cpu(pfp_hdr->header.ucode_size_bytes) / 4;
1539 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_PFP_UCODE_ADDR), 0);
1540 for (i = 0; i < fw_size; i++)
1541 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_PFP_UCODE_DATA), le32_to_cpup(fw_data++));
1542 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_PFP_UCODE_ADDR), adev->gfx.pfp_fw_version);
1543
1544 /* CE */
1545 fw_data = (const __le32 *)
1546 (adev->gfx.ce_fw->data +
1547 le32_to_cpu(ce_hdr->header.ucode_array_offset_bytes));
1548 fw_size = le32_to_cpu(ce_hdr->header.ucode_size_bytes) / 4;
1549 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_CE_UCODE_ADDR), 0);
1550 for (i = 0; i < fw_size; i++)
1551 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_CE_UCODE_DATA), le32_to_cpup(fw_data++));
1552 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_CE_UCODE_ADDR), adev->gfx.ce_fw_version);
1553
1554 /* ME */
1555 fw_data = (const __le32 *)
1556 (adev->gfx.me_fw->data +
1557 le32_to_cpu(me_hdr->header.ucode_array_offset_bytes));
1558 fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes) / 4;
1559 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_ME_RAM_WADDR), 0);
1560 for (i = 0; i < fw_size; i++)
1561 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_ME_RAM_DATA), le32_to_cpup(fw_data++));
1562 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_ME_RAM_WADDR), adev->gfx.me_fw_version);
1563
1564 return 0;
1565}
1566
1567static u32 gfx_v9_0_get_csb_size(struct amdgpu_device *adev)
1568{
1569 u32 count = 0;
1570 const struct cs_section_def *sect = NULL;
1571 const struct cs_extent_def *ext = NULL;
1572
1573 /* begin clear state */
1574 count += 2;
1575 /* context control state */
1576 count += 3;
1577
1578 for (sect = gfx9_cs_data; sect->section != NULL; ++sect) {
1579 for (ext = sect->section; ext->extent != NULL; ++ext) {
1580 if (sect->id == SECT_CONTEXT)
1581 count += 2 + ext->reg_count;
1582 else
1583 return 0;
1584 }
1585 }
1586 /* pa_sc_raster_config/pa_sc_raster_config1 */
1587 count += 4;
1588 /* end clear state */
1589 count += 2;
1590 /* clear state */
1591 count += 2;
1592
1593 return count;
1594}
1595
1596static int gfx_v9_0_cp_gfx_start(struct amdgpu_device *adev)
1597{
1598 struct amdgpu_ring *ring = &adev->gfx.gfx_ring[0];
1599 const struct cs_section_def *sect = NULL;
1600 const struct cs_extent_def *ext = NULL;
1601 int r, i;
1602
1603 /* init the CP */
1604 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_MAX_CONTEXT), adev->gfx.config.max_hw_contexts - 1);
1605 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_DEVICE_ID), 1);
1606
1607 gfx_v9_0_cp_gfx_enable(adev, true);
1608
1609 r = amdgpu_ring_alloc(ring, gfx_v9_0_get_csb_size(adev) + 4);
1610 if (r) {
1611 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r);
1612 return r;
1613 }
1614
1615 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
1616 amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
1617
1618 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
1619 amdgpu_ring_write(ring, 0x80000000);
1620 amdgpu_ring_write(ring, 0x80000000);
1621
1622 for (sect = gfx9_cs_data; sect->section != NULL; ++sect) {
1623 for (ext = sect->section; ext->extent != NULL; ++ext) {
1624 if (sect->id == SECT_CONTEXT) {
1625 amdgpu_ring_write(ring,
1626 PACKET3(PACKET3_SET_CONTEXT_REG,
1627 ext->reg_count));
1628 amdgpu_ring_write(ring,
1629 ext->reg_index - PACKET3_SET_CONTEXT_REG_START);
1630 for (i = 0; i < ext->reg_count; i++)
1631 amdgpu_ring_write(ring, ext->extent[i]);
1632 }
1633 }
1634 }
1635
1636 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
1637 amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE);
1638
1639 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
1640 amdgpu_ring_write(ring, 0);
1641
1642 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2));
1643 amdgpu_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE));
1644 amdgpu_ring_write(ring, 0x8000);
1645 amdgpu_ring_write(ring, 0x8000);
1646
1647 amdgpu_ring_commit(ring);
1648
1649 return 0;
1650}
1651
1652static int gfx_v9_0_cp_gfx_resume(struct amdgpu_device *adev)
1653{
1654 struct amdgpu_ring *ring;
1655 u32 tmp;
1656 u32 rb_bufsz;
3fc08b61 1657 u64 rb_addr, rptr_addr, wptr_gpu_addr;
b1023571
KW		 1658
1659 /* Set the write pointer delay */
1660 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB_WPTR_DELAY), 0);
1661
1662 /* set the RB to use vmid 0 */
1663 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB_VMID), 0);
1664
1665 /* Set ring buffer size */
1666 ring = &adev->gfx.gfx_ring[0];
1667 rb_bufsz = order_base_2(ring->ring_size / 8);
1668 tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz);
1669 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2);
1670#ifdef __BIG_ENDIAN
1671 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, BUF_SWAP, 1);
1672#endif
1673 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB0_CNTL), tmp);
1674
1675 /* Initialize the ring buffer's write pointers */
1676 ring->wptr = 0;
1677 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB0_WPTR), lower_32_bits(ring->wptr));
1678 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB0_WPTR_HI), upper_32_bits(ring->wptr));
1679
1680 /* set the wb address wether it's enabled or not */
1681 rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
1682 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB0_RPTR_ADDR), lower_32_bits(rptr_addr));
1683 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB0_RPTR_ADDR_HI), upper_32_bits(rptr_addr) & CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK);
1684
3fc08b61
ML		 1685 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
1686 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO), lower_32_bits(wptr_gpu_addr));
1687 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI), upper_32_bits(wptr_gpu_addr));
1688
b1023571
KW		 1689 mdelay(1);
1690 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB0_CNTL), tmp);
1691
1692 rb_addr = ring->gpu_addr >> 8;
1693 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB0_BASE), rb_addr);
1694 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB0_BASE_HI), upper_32_bits(rb_addr));
1695
1696 tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB_DOORBELL_CONTROL));
1697 if (ring->use_doorbell) {
1698 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
1699 DOORBELL_OFFSET, ring->doorbell_index);
1700 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
1701 DOORBELL_EN, 1);
1702 } else {
1703 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, DOORBELL_EN, 0);
1704 }
1705 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB_DOORBELL_CONTROL), tmp);
1706
1707 tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER,
1708 DOORBELL_RANGE_LOWER, ring->doorbell_index);
1709 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB_DOORBELL_RANGE_LOWER), tmp);
1710
1711 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB_DOORBELL_RANGE_UPPER),
1712 CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK);
1713
1714
1715 /* start the ring */
1716 gfx_v9_0_cp_gfx_start(adev);
1717 ring->ready = true;
1718
1719 return 0;
1720}
1721
1722static void gfx_v9_0_cp_compute_enable(struct amdgpu_device *adev, bool enable)
1723{
1724 int i;
1725
1726 if (enable) {
1727 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_MEC_CNTL), 0);
1728 } else {
1729 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_MEC_CNTL),
1730 (CP_MEC_CNTL__MEC_ME1_HALT_MASK | CP_MEC_CNTL__MEC_ME2_HALT_MASK));
1731 for (i = 0; i < adev->gfx.num_compute_rings; i++)
1732 adev->gfx.compute_ring[i].ready = false;
ac104e99 1733 adev->gfx.kiq.ring.ready = false;
b1023571
KW		 1734 }
1735 udelay(50);
1736}
1737
1738static int gfx_v9_0_cp_compute_start(struct amdgpu_device *adev)
1739{
1740 gfx_v9_0_cp_compute_enable(adev, true);
1741
1742 return 0;
1743}
1744
1745static int gfx_v9_0_cp_compute_load_microcode(struct amdgpu_device *adev)
1746{
1747 const struct gfx_firmware_header_v1_0 *mec_hdr;
1748 const __le32 *fw_data;
1749 unsigned i;
1750 u32 tmp;
1751
1752 if (!adev->gfx.mec_fw)
1753 return -EINVAL;
1754
1755 gfx_v9_0_cp_compute_enable(adev, false);
1756
1757 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
1758 amdgpu_ucode_print_gfx_hdr(&mec_hdr->header);
1759
1760 fw_data = (const __le32 *)
1761 (adev->gfx.mec_fw->data +
1762 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes));
1763 tmp = 0;
1764 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, VMID, 0);
1765 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0);
1766 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_CPC_IC_BASE_CNTL), tmp);
1767
1768 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_CPC_IC_BASE_LO),
1769 adev->gfx.mec.mec_fw_gpu_addr & 0xFFFFF000);
1770 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_CPC_IC_BASE_HI),
1771 upper_32_bits(adev->gfx.mec.mec_fw_gpu_addr));
1772
1773 /* MEC1 */
1774 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_MEC_ME1_UCODE_ADDR),
1775 mec_hdr->jt_offset);
1776 for (i = 0; i < mec_hdr->jt_size; i++)
1777 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_MEC_ME1_UCODE_DATA),
1778 le32_to_cpup(fw_data + mec_hdr->jt_offset + i));
1779
1780 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_MEC_ME1_UCODE_ADDR),
1781 adev->gfx.mec_fw_version);
1782 /* Todo : Loading MEC2 firmware is only necessary if MEC2 should run different microcode than MEC1. */
1783
1784 return 0;
1785}
1786
1787static void gfx_v9_0_cp_compute_fini(struct amdgpu_device *adev)
1788{
1789 int i, r;
1790
1791 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
1792 struct amdgpu_ring *ring = &adev->gfx.compute_ring[i];
1793
1794 if (ring->mqd_obj) {
1795 r = amdgpu_bo_reserve(ring->mqd_obj, false);
1796 if (unlikely(r != 0))
1797 dev_warn(adev->dev, "(%d) reserve MQD bo failed\n", r);
1798
1799 amdgpu_bo_unpin(ring->mqd_obj);
1800 amdgpu_bo_unreserve(ring->mqd_obj);
1801
1802 amdgpu_bo_unref(&ring->mqd_obj);
1803 ring->mqd_obj = NULL;
1804 }
1805 }
1806}
1807
1808static int gfx_v9_0_init_queue(struct amdgpu_ring *ring);
1809
1810static int gfx_v9_0_cp_compute_resume(struct amdgpu_device *adev)
1811{
1812 int i, r;
1813 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
1814 struct amdgpu_ring *ring = &adev->gfx.compute_ring[i];
1815 if (gfx_v9_0_init_queue(ring))
1816 dev_warn(adev->dev, "compute queue %d init failed!\n", i);
1817 }
1818
1819 r = gfx_v9_0_cp_compute_start(adev);
1820 if (r)
1821 return r;
1822
1823 return 0;
1824}
1825
464826d6
XY		 1826/* KIQ functions */
1827static void gfx_v9_0_kiq_setting(struct amdgpu_ring *ring)
1828{
1829 uint32_t tmp;
1830 struct amdgpu_device *adev = ring->adev;
1831
1832 /* tell RLC which is KIQ queue */
1833 tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CP_SCHEDULERS));
1834 tmp &= 0xffffff00;
1835 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue);
1836 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CP_SCHEDULERS), tmp);
1837 tmp |= 0x80;
1838 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CP_SCHEDULERS), tmp);
1839}
1840
1841static void gfx_v9_0_kiq_enable(struct amdgpu_ring *ring)
1842{
1843 amdgpu_ring_alloc(ring, 8);
1844 /* set resources */
1845 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_RESOURCES, 6));
1846 amdgpu_ring_write(ring, 0); /* vmid_mask:0 queue_type:0 (KIQ) */
1847 amdgpu_ring_write(ring, 0x000000FF); /* queue mask lo */
1848 amdgpu_ring_write(ring, 0); /* queue mask hi */
1849 amdgpu_ring_write(ring, 0); /* gws mask lo */
1850 amdgpu_ring_write(ring, 0); /* gws mask hi */
1851 amdgpu_ring_write(ring, 0); /* oac mask */
1852 amdgpu_ring_write(ring, 0); /* gds heap base:0, gds heap size:0 */
1853 amdgpu_ring_commit(ring);
1854 udelay(50);
1855}
1856
1857static void gfx_v9_0_map_queue_enable(struct amdgpu_ring *kiq_ring,
1858 struct amdgpu_ring *ring)
1859{
1860 struct amdgpu_device *adev = kiq_ring->adev;
1861 uint64_t mqd_addr, wptr_addr;
1862
1863 mqd_addr = amdgpu_bo_gpu_offset(ring->mqd_obj);
1864 wptr_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
1865 amdgpu_ring_alloc(kiq_ring, 8);
1866
1867 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5));
1868 /* Q_sel:0, vmid:0, vidmem: 1, engine:0, num_Q:1*/
1869 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
1870 (0 << 4) | /* Queue_Sel */
1871 (0 << 8) | /* VMID */
1872 (ring->queue << 13 ) |
1873 (ring->pipe << 16) |
1874 ((ring->me == 1 ? 0 : 1) << 18) |
1875 (0 << 21) | /*queue_type: normal compute queue */
1876 (1 << 24) | /* alloc format: all_on_one_pipe */
1877 (0 << 26) | /* engine_sel: compute */
1878 (1 << 29)); /* num_queues: must be 1 */
1879 amdgpu_ring_write(kiq_ring, (ring->doorbell_index << 2));
1880 amdgpu_ring_write(kiq_ring, lower_32_bits(mqd_addr));
1881 amdgpu_ring_write(kiq_ring, upper_32_bits(mqd_addr));
1882 amdgpu_ring_write(kiq_ring, lower_32_bits(wptr_addr));
1883 amdgpu_ring_write(kiq_ring, upper_32_bits(wptr_addr));
1884 amdgpu_ring_commit(kiq_ring);
1885 udelay(50);
1886}
1887
1888static int gfx_v9_0_mqd_init(struct amdgpu_device *adev,
1889 struct v9_mqd *mqd,
1890 uint64_t mqd_gpu_addr,
1891 uint64_t eop_gpu_addr,
1892 struct amdgpu_ring *ring)
1893{
1894 uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr;
1895 uint32_t tmp;
1896
1897 mqd->header = 0xC0310800;
1898 mqd->compute_pipelinestat_enable = 0x00000001;
1899 mqd->compute_static_thread_mgmt_se0 = 0xffffffff;
1900 mqd->compute_static_thread_mgmt_se1 = 0xffffffff;
1901 mqd->compute_static_thread_mgmt_se2 = 0xffffffff;
1902 mqd->compute_static_thread_mgmt_se3 = 0xffffffff;
1903 mqd->compute_misc_reserved = 0x00000003;
1904
1905 eop_base_addr = eop_gpu_addr >> 8;
1906 mqd->cp_hqd_eop_base_addr_lo = eop_base_addr;
1907 mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr);
1908
1909 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
1910 tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_EOP_CONTROL));
1911 tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE,
1912 (order_base_2(MEC_HPD_SIZE / 4) - 1));
1913
1914 mqd->cp_hqd_eop_control = tmp;
1915
1916 /* enable doorbell? */
1917 tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL));
1918
1919 if (ring->use_doorbell) {
1920 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
1921 DOORBELL_OFFSET, ring->doorbell_index);
1922 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
1923 DOORBELL_EN, 1);
1924 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
1925 DOORBELL_SOURCE, 0);
1926 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
1927 DOORBELL_HIT, 0);
1928 }
1929 else
1930 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
1931 DOORBELL_EN, 0);
1932
1933 mqd->cp_hqd_pq_doorbell_control = tmp;
1934
1935 /* disable the queue if it's active */
1936 ring->wptr = 0;
1937 mqd->cp_hqd_dequeue_request = 0;
1938 mqd->cp_hqd_pq_rptr = 0;
1939 mqd->cp_hqd_pq_wptr_lo = 0;
1940 mqd->cp_hqd_pq_wptr_hi = 0;
1941
1942 /* set the pointer to the MQD */
1943 mqd->cp_mqd_base_addr_lo = mqd_gpu_addr & 0xfffffffc;
1944 mqd->cp_mqd_base_addr_hi = upper_32_bits(mqd_gpu_addr);
1945
1946 /* set MQD vmid to 0 */
1947 tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_MQD_CONTROL));
1948 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0);
1949 mqd->cp_mqd_control = tmp;
1950
1951 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
1952 hqd_gpu_addr = ring->gpu_addr >> 8;
1953 mqd->cp_hqd_pq_base_lo = hqd_gpu_addr;
1954 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr);
1955
1956 /* set up the HQD, this is similar to CP_RB0_CNTL */
1957 tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_CONTROL));
1958 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE,
1959 (order_base_2(ring->ring_size / 4) - 1));
1960 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE,
1961 ((order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1) << 8));
1962#ifdef __BIG_ENDIAN
1963 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1);
1964#endif
1965 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0);
1966 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ROQ_PQ_IB_FLIP, 0);
1967 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1);
1968 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1);
1969 mqd->cp_hqd_pq_control = tmp;
1970
1971 /* set the wb address whether it's enabled or not */
1972 wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
1973 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc;
1974 mqd->cp_hqd_pq_rptr_report_addr_hi =
1975 upper_32_bits(wb_gpu_addr) & 0xffff;
1976
1977 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
1978 wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
1979 mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc;
1980 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;
1981
1982 tmp = 0;
1983 /* enable the doorbell if requested */
1984 if (ring->use_doorbell) {
1985 tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL));
1986 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
1987 DOORBELL_OFFSET, ring->doorbell_index);
1988
1989 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
1990 DOORBELL_EN, 1);
1991 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
1992 DOORBELL_SOURCE, 0);
1993 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
1994 DOORBELL_HIT, 0);
1995 }
1996
1997 mqd->cp_hqd_pq_doorbell_control = tmp;
1998
1999 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
2000 ring->wptr = 0;
2001 mqd->cp_hqd_pq_rptr = RREG32(mmCP_HQD_PQ_RPTR);
2002
2003 /* set the vmid for the queue */
2004 mqd->cp_hqd_vmid = 0;
2005
2006 tmp = RREG32(mmCP_HQD_PERSISTENT_STATE);
2007 tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x53);
2008 mqd->cp_hqd_persistent_state = tmp;
2009
2010 /* activate the queue */
2011 mqd->cp_hqd_active = 1;
2012
2013 return 0;
2014}
2015
2016static int gfx_v9_0_kiq_init_register(struct amdgpu_device *adev,
2017 struct v9_mqd *mqd,
2018 struct amdgpu_ring *ring)
2019{
2020 uint32_t tmp;
2021 int j;
2022
2023 /* disable wptr polling */
2024 tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_PQ_WPTR_POLL_CNTL));
2025 tmp = REG_SET_FIELD(tmp, CP_PQ_WPTR_POLL_CNTL, EN, 0);
2026 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_PQ_WPTR_POLL_CNTL), tmp);
2027
2028 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_EOP_BASE_ADDR),
2029 mqd->cp_hqd_eop_base_addr_lo);
2030 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_EOP_BASE_ADDR_HI),
2031 mqd->cp_hqd_eop_base_addr_hi);
2032
2033 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
2034 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_EOP_CONTROL),
2035 mqd->cp_hqd_eop_control);
2036
2037 /* enable doorbell? */
2038 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL),
2039 mqd->cp_hqd_pq_doorbell_control);
2040
2041 /* disable the queue if it's active */
2042 if (RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_ACTIVE)) & 1) {
2043 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_DEQUEUE_REQUEST), 1);
2044 for (j = 0; j < adev->usec_timeout; j++) {
2045 if (!(RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_ACTIVE)) & 1))
2046 break;
2047 udelay(1);
2048 }
2049 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_DEQUEUE_REQUEST),
2050 mqd->cp_hqd_dequeue_request);
2051 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_RPTR),
2052 mqd->cp_hqd_pq_rptr);
2053 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_LO),
2054 mqd->cp_hqd_pq_wptr_lo);
2055 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_HI),
2056 mqd->cp_hqd_pq_wptr_hi);
2057 }
2058
2059 /* set the pointer to the MQD */
2060 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_MQD_BASE_ADDR),
2061 mqd->cp_mqd_base_addr_lo);
2062 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_MQD_BASE_ADDR_HI),
2063 mqd->cp_mqd_base_addr_hi);
2064
2065 /* set MQD vmid to 0 */
2066 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_MQD_CONTROL),
2067 mqd->cp_mqd_control);
2068
2069 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
2070 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_BASE),
2071 mqd->cp_hqd_pq_base_lo);
2072 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_BASE_HI),
2073 mqd->cp_hqd_pq_base_hi);
2074
2075 /* set up the HQD, this is similar to CP_RB0_CNTL */
2076 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_CONTROL),
2077 mqd->cp_hqd_pq_control);
2078
2079 /* set the wb address whether it's enabled or not */
2080 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR),
2081 mqd->cp_hqd_pq_rptr_report_addr_lo);
2082 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI),
2083 mqd->cp_hqd_pq_rptr_report_addr_hi);
2084
2085 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
2086 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR),
2087 mqd->cp_hqd_pq_wptr_poll_addr_lo);
2088 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI),
2089 mqd->cp_hqd_pq_wptr_poll_addr_hi);
2090
2091 /* enable the doorbell if requested */
2092 if (ring->use_doorbell) {
2093 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_MEC_DOORBELL_RANGE_LOWER),
2094 (AMDGPU_DOORBELL64_KIQ *2) << 2);
2095 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_MEC_DOORBELL_RANGE_UPPER),
2096 (AMDGPU_DOORBELL64_USERQUEUE_END * 2) << 2);
2097 }
2098
2099 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL),
2100 mqd->cp_hqd_pq_doorbell_control);
2101
2102 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
2103 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_LO),
2104 mqd->cp_hqd_pq_wptr_lo);
2105 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_HI),
2106 mqd->cp_hqd_pq_wptr_hi);
2107
2108 /* set the vmid for the queue */
2109 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_VMID), mqd->cp_hqd_vmid);
2110
2111 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PERSISTENT_STATE),
2112 mqd->cp_hqd_persistent_state);
2113
2114 /* activate the queue */
2115 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_ACTIVE),
2116 mqd->cp_hqd_active);
2117
2118 if (ring->use_doorbell) {
2119 tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_PQ_STATUS));
2120 tmp = REG_SET_FIELD(tmp, CP_PQ_STATUS, DOORBELL_ENABLE, 1);
2121 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_PQ_STATUS), tmp);
2122 }
2123
2124 return 0;
2125}
2126
2127static int gfx_v9_0_kiq_init_queue(struct amdgpu_ring *ring,
2128 struct v9_mqd *mqd,
2129 u64 mqd_gpu_addr)
2130{
2131 struct amdgpu_device *adev = ring->adev;
2132 struct amdgpu_kiq *kiq = &adev->gfx.kiq;
2133 uint64_t eop_gpu_addr;
2134 bool is_kiq = (ring->funcs->type == AMDGPU_RING_TYPE_KIQ);
2135 int mqd_idx = AMDGPU_MAX_COMPUTE_RINGS;
2136
2137 if (is_kiq) {
2138 eop_gpu_addr = kiq->eop_gpu_addr;
2139 gfx_v9_0_kiq_setting(&kiq->ring);
2140 } else {
2141 eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr +
2142 ring->queue * MEC_HPD_SIZE;
2143 mqd_idx = ring - &adev->gfx.compute_ring[0];
2144 }
2145
2146 if (!adev->gfx.in_reset) {
2147 memset((void *)mqd, 0, sizeof(*mqd));
2148 mutex_lock(&adev->srbm_mutex);
2149 soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
2150 gfx_v9_0_mqd_init(adev, mqd, mqd_gpu_addr, eop_gpu_addr, ring);
2151 if (is_kiq)
2152 gfx_v9_0_kiq_init_register(adev, mqd, ring);
2153 soc15_grbm_select(adev, 0, 0, 0, 0);
2154 mutex_unlock(&adev->srbm_mutex);
2155
2156 } else { /* for GPU_RESET case */
2157 /* reset MQD to a clean status */
2158
2159 /* reset ring buffer */
2160 ring->wptr = 0;
2161
2162 if (is_kiq) {
2163 mutex_lock(&adev->srbm_mutex);
2164 soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
2165 gfx_v9_0_kiq_init_register(adev, mqd, ring);
2166 soc15_grbm_select(adev, 0, 0, 0, 0);
2167 mutex_unlock(&adev->srbm_mutex);
2168 }
2169 }
2170
2171 if (is_kiq)
2172 gfx_v9_0_kiq_enable(ring);
2173 else
2174 gfx_v9_0_map_queue_enable(&kiq->ring, ring);
2175
2176 return 0;
2177}
2178
2179static int gfx_v9_0_kiq_resume(struct amdgpu_device *adev)
2180{
2181 struct amdgpu_ring *ring = NULL;
2182 int r = 0, i;
2183
2184 gfx_v9_0_cp_compute_enable(adev, true);
2185
2186 ring = &adev->gfx.kiq.ring;
2187 if (!amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr)) {
2188 r = gfx_v9_0_kiq_init_queue(ring, ring->mqd_ptr, ring->mqd_gpu_addr);
2189 amdgpu_bo_kunmap(ring->mqd_obj);
2190 ring->mqd_ptr = NULL;
2191 if (r)
2192 return r;
2193 } else {
2194 return r;
2195 }
2196
2197 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
2198 ring = &adev->gfx.compute_ring[i];
2199 if (!amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr)) {
2200 r = gfx_v9_0_kiq_init_queue(ring, ring->mqd_ptr, ring->mqd_gpu_addr);
2201 amdgpu_bo_kunmap(ring->mqd_obj);
2202 ring->mqd_ptr = NULL;
2203 if (r)
2204 return r;
2205 } else {
2206 return r;
2207 }
2208 }
2209
2210 return 0;
2211}
2212
b1023571
KW		 2213static int gfx_v9_0_cp_resume(struct amdgpu_device *adev)
2214{
2215 int r,i;
2216 struct amdgpu_ring *ring;
2217
2218 if (!(adev->flags & AMD_IS_APU))
2219 gfx_v9_0_enable_gui_idle_interrupt(adev, false);
2220
2221 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
2222 /* legacy firmware loading */
2223 r = gfx_v9_0_cp_gfx_load_microcode(adev);
2224 if (r)
2225 return r;
2226
2227 r = gfx_v9_0_cp_compute_load_microcode(adev);
2228 if (r)
2229 return r;
2230 }
2231
2232 r = gfx_v9_0_cp_gfx_resume(adev);
2233 if (r)
2234 return r;
2235
464826d6
XY		 2236 if (amdgpu_sriov_vf(adev))
2237 r = gfx_v9_0_kiq_resume(adev);
2238 else
2239 r = gfx_v9_0_cp_compute_resume(adev);
b1023571
KW		 2240 if (r)
2241 return r;
2242
2243 ring = &adev->gfx.gfx_ring[0];
2244 r = amdgpu_ring_test_ring(ring);
2245 if (r) {
2246 ring->ready = false;
2247 return r;
2248 }
2249 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
2250 ring = &adev->gfx.compute_ring[i];
2251
2252 ring->ready = true;
2253 r = amdgpu_ring_test_ring(ring);
2254 if (r)
2255 ring->ready = false;
2256 }
2257
464826d6
XY		 2258 if (amdgpu_sriov_vf(adev)) {
2259 ring = &adev->gfx.kiq.ring;
2260 ring->ready = true;
2261 r = amdgpu_ring_test_ring(ring);
2262 if (r)
2263 ring->ready = false;
2264 }
2265
b1023571
KW		 2266 gfx_v9_0_enable_gui_idle_interrupt(adev, true);
2267
2268 return 0;
2269}
2270
2271static void gfx_v9_0_cp_enable(struct amdgpu_device *adev, bool enable)
2272{
2273 gfx_v9_0_cp_gfx_enable(adev, enable);
2274 gfx_v9_0_cp_compute_enable(adev, enable);
2275}
2276
2277static int gfx_v9_0_hw_init(void *handle)
2278{
2279 int r;
2280 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2281
2282 gfx_v9_0_init_golden_registers(adev);
2283
2284 gfx_v9_0_gpu_init(adev);
2285
2286 r = gfx_v9_0_rlc_resume(adev);
2287 if (r)
2288 return r;
2289
2290 r = gfx_v9_0_cp_resume(adev);
2291 if (r)
2292 return r;
2293
2294 r = gfx_v9_0_ngg_en(adev);
2295 if (r)
2296 return r;
2297
2298 return r;
2299}
2300
2301static int gfx_v9_0_hw_fini(void *handle)
2302{
2303 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2304
2305 amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0);
2306 amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0);
464826d6
XY		 2307 if (amdgpu_sriov_vf(adev)) {
2308 pr_debug("For SRIOV client, shouldn't do anything.\n");
2309 return 0;
2310 }
b1023571
KW		 2311 gfx_v9_0_cp_enable(adev, false);
2312 gfx_v9_0_rlc_stop(adev);
2313 gfx_v9_0_cp_compute_fini(adev);
2314
2315 return 0;
2316}
2317
2318static int gfx_v9_0_suspend(void *handle)
2319{
2320 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2321
2322 return gfx_v9_0_hw_fini(adev);
2323}
2324
2325static int gfx_v9_0_resume(void *handle)
2326{
2327 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2328
2329 return gfx_v9_0_hw_init(adev);
2330}
2331
2332static bool gfx_v9_0_is_idle(void *handle)
2333{
2334 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2335
2336 if (REG_GET_FIELD(RREG32(SOC15_REG_OFFSET(GC, 0, mmGRBM_STATUS)),
2337 GRBM_STATUS, GUI_ACTIVE))
2338 return false;
2339 else
2340 return true;
2341}
2342
2343static int gfx_v9_0_wait_for_idle(void *handle)
2344{
2345 unsigned i;
2346 u32 tmp;
2347 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2348
2349 for (i = 0; i < adev->usec_timeout; i++) {
2350 /* read MC_STATUS */
2351 tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmGRBM_STATUS)) &
2352 GRBM_STATUS__GUI_ACTIVE_MASK;
2353
2354 if (!REG_GET_FIELD(tmp, GRBM_STATUS, GUI_ACTIVE))
2355 return 0;
2356 udelay(1);
2357 }
2358 return -ETIMEDOUT;
2359}
2360
2361static void gfx_v9_0_print_status(void *handle)
2362{
2363 int i;
2364 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2365
2366 dev_info(adev->dev, "GFX 9.x registers\n");
2367 dev_info(adev->dev, " GRBM_STATUS=0x%08X\n",
2368 RREG32(SOC15_REG_OFFSET(GC, 0, mmGRBM_STATUS)));
2369 dev_info(adev->dev, " GRBM_STATUS2=0x%08X\n",
2370 RREG32(SOC15_REG_OFFSET(GC, 0, mmGRBM_STATUS2)));
2371 dev_info(adev->dev, " GRBM_STATUS_SE0=0x%08X\n",
2372 RREG32(SOC15_REG_OFFSET(GC, 0, mmGRBM_STATUS_SE0)));
2373 dev_info(adev->dev, " GRBM_STATUS_SE1=0x%08X\n",
2374 RREG32(SOC15_REG_OFFSET(GC, 0, mmGRBM_STATUS_SE1)));
2375 dev_info(adev->dev, " GRBM_STATUS_SE2=0x%08X\n",
2376 RREG32(SOC15_REG_OFFSET(GC, 0, mmGRBM_STATUS_SE2)));
2377 dev_info(adev->dev, " GRBM_STATUS_SE3=0x%08X\n",
2378 RREG32(SOC15_REG_OFFSET(GC, 0, mmGRBM_STATUS_SE3)));
2379 dev_info(adev->dev, " CP_STAT = 0x%08x\n", RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_STAT)));
2380 dev_info(adev->dev, " CP_STALLED_STAT1 = 0x%08x\n",
2381 RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_STALLED_STAT1)));
2382 dev_info(adev->dev, " CP_STALLED_STAT2 = 0x%08x\n",
2383 RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_STALLED_STAT2)));
2384 dev_info(adev->dev, " CP_STALLED_STAT3 = 0x%08x\n",
2385 RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_STALLED_STAT3)));
2386 dev_info(adev->dev, " CP_CPF_BUSY_STAT = 0x%08x\n",
2387 RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_CPF_BUSY_STAT)));
2388 dev_info(adev->dev, " CP_CPF_STALLED_STAT1 = 0x%08x\n",
2389 RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_CPF_STALLED_STAT1)));
2390 dev_info(adev->dev, " CP_CPF_STATUS = 0x%08x\n", RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_CPF_STATUS)));
2391 dev_info(adev->dev, " CP_CPC_BUSY_STAT = 0x%08x\n", RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_CPC_BUSY_STAT)));
2392 dev_info(adev->dev, " CP_CPC_STALLED_STAT1 = 0x%08x\n",
2393 RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_CPC_STALLED_STAT1)));
2394 dev_info(adev->dev, " CP_CPC_STATUS = 0x%08x\n", RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_CPC_STATUS)));
2395
2396 for (i = 0; i < 32; i++) {
2397 dev_info(adev->dev, " GB_TILE_MODE%d=0x%08X\n",
2398 i, RREG32(SOC15_REG_OFFSET(GC, 0, mmGB_TILE_MODE0 ) + i*4));
2399 }
2400 for (i = 0; i < 16; i++) {
2401 dev_info(adev->dev, " GB_MACROTILE_MODE%d=0x%08X\n",
2402 i, RREG32(SOC15_REG_OFFSET(GC, 0, mmGB_MACROTILE_MODE0) + i*4));
2403 }
2404 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
2405 dev_info(adev->dev, " se: %d\n", i);
2406 gfx_v9_0_select_se_sh(adev, i, 0xffffffff, 0xffffffff);
2407 dev_info(adev->dev, " PA_SC_RASTER_CONFIG=0x%08X\n",
2408 RREG32(SOC15_REG_OFFSET(GC, 0, mmPA_SC_RASTER_CONFIG)));
2409 dev_info(adev->dev, " PA_SC_RASTER_CONFIG_1=0x%08X\n",
2410 RREG32(SOC15_REG_OFFSET(GC, 0, mmPA_SC_RASTER_CONFIG_1)));
2411 }
2412 gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
2413
2414 dev_info(adev->dev, " GB_ADDR_CONFIG=0x%08X\n",
2415 RREG32(SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG)));
2416
2417 dev_info(adev->dev, " CP_MEQ_THRESHOLDS=0x%08X\n",
2418 RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_MEQ_THRESHOLDS)));
2419 dev_info(adev->dev, " SX_DEBUG_1=0x%08X\n",
2420 RREG32(SOC15_REG_OFFSET(GC, 0, mmSX_DEBUG_1)));
2421 dev_info(adev->dev, " TA_CNTL_AUX=0x%08X\n",
2422 RREG32(SOC15_REG_OFFSET(GC, 0, mmTA_CNTL_AUX)));
2423 dev_info(adev->dev, " SPI_CONFIG_CNTL=0x%08X\n",
2424 RREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL)));
2425 dev_info(adev->dev, " SQ_CONFIG=0x%08X\n",
2426 RREG32(SOC15_REG_OFFSET(GC, 0, mmSQ_CONFIG)));
2427 dev_info(adev->dev, " DB_DEBUG=0x%08X\n",
2428 RREG32(SOC15_REG_OFFSET(GC, 0, mmDB_DEBUG)));
2429 dev_info(adev->dev, " DB_DEBUG2=0x%08X\n",
2430 RREG32(SOC15_REG_OFFSET(GC, 0, mmDB_DEBUG2)));
2431 dev_info(adev->dev, " DB_DEBUG3=0x%08X\n",
2432 RREG32(SOC15_REG_OFFSET(GC, 0, mmDB_DEBUG3)));
2433 dev_info(adev->dev, " CB_HW_CONTROL=0x%08X\n",
2434 RREG32(SOC15_REG_OFFSET(GC, 0, mmCB_HW_CONTROL)));
2435 dev_info(adev->dev, " SPI_CONFIG_CNTL_1=0x%08X\n",
2436 RREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_1)));
2437 dev_info(adev->dev, " PA_SC_FIFO_SIZE=0x%08X\n",
2438 RREG32(SOC15_REG_OFFSET(GC, 0, mmPA_SC_FIFO_SIZE)));
2439 dev_info(adev->dev, " VGT_NUM_INSTANCES=0x%08X\n",
2440 RREG32(SOC15_REG_OFFSET(GC, 0, mmVGT_NUM_INSTANCES)));
2441 dev_info(adev->dev, " CP_PERFMON_CNTL=0x%08X\n",
2442 RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_PERFMON_CNTL)));
2443 dev_info(adev->dev, " PA_SC_FORCE_EOV_MAX_CNTS=0x%08X\n",
2444 RREG32(SOC15_REG_OFFSET(GC, 0, mmPA_SC_FORCE_EOV_MAX_CNTS)));
2445 dev_info(adev->dev, " VGT_CACHE_INVALIDATION=0x%08X\n",
2446 RREG32(SOC15_REG_OFFSET(GC, 0, mmVGT_CACHE_INVALIDATION)));
2447 dev_info(adev->dev, " VGT_GS_VERTEX_REUSE=0x%08X\n",
2448 RREG32(SOC15_REG_OFFSET(GC, 0, mmVGT_GS_VERTEX_REUSE)));
2449 dev_info(adev->dev, " PA_SC_LINE_STIPPLE_STATE=0x%08X\n",
2450 RREG32(SOC15_REG_OFFSET(GC, 0, mmPA_SC_LINE_STIPPLE_STATE)));
2451 dev_info(adev->dev, " PA_CL_ENHANCE=0x%08X\n",
2452 RREG32(SOC15_REG_OFFSET(GC, 0, mmPA_CL_ENHANCE)));
2453 dev_info(adev->dev, " PA_SC_ENHANCE=0x%08X\n",
2454 RREG32(SOC15_REG_OFFSET(GC, 0, mmPA_SC_ENHANCE)));
2455
2456 dev_info(adev->dev, " CP_ME_CNTL=0x%08X\n",
2457 RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_ME_CNTL)));
2458 dev_info(adev->dev, " CP_MAX_CONTEXT=0x%08X\n",
2459 RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_MAX_CONTEXT)));
2460 dev_info(adev->dev, " CP_DEVICE_ID=0x%08X\n",
2461 RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_DEVICE_ID)));
2462
2463 dev_info(adev->dev, " CP_SEM_WAIT_TIMER=0x%08X\n",
2464 RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_SEM_WAIT_TIMER)));
2465
2466 dev_info(adev->dev, " CP_RB_WPTR_DELAY=0x%08X\n",
2467 RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB_WPTR_DELAY)));
2468 dev_info(adev->dev, " CP_RB_VMID=0x%08X\n",
2469 RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB_VMID)));
2470 dev_info(adev->dev, " CP_RB0_CNTL=0x%08X\n",
2471 RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB0_CNTL)));
2472 dev_info(adev->dev, " CP_RB0_WPTR=0x%08X\n",
2473 RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB0_WPTR)));
2474 dev_info(adev->dev, " CP_RB0_RPTR_ADDR=0x%08X\n",
2475 RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB0_RPTR_ADDR)));
2476 dev_info(adev->dev, " CP_RB0_RPTR_ADDR_HI=0x%08X\n",
2477 RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB0_RPTR_ADDR_HI)));
2478 dev_info(adev->dev, " CP_RB0_CNTL=0x%08X\n",
2479 RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB0_CNTL)));
2480 dev_info(adev->dev, " CP_RB0_BASE=0x%08X\n",
2481 RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB0_BASE)));
2482 dev_info(adev->dev, " CP_RB0_BASE_HI=0x%08X\n",
2483 RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB0_BASE_HI)));
2484 dev_info(adev->dev, " CP_MEC_CNTL=0x%08X\n",
2485 RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_MEC_CNTL)));
2486
2487 dev_info(adev->dev, " SCRATCH_ADDR=0x%08X\n",
2488 RREG32(SOC15_REG_OFFSET(GC, 0, mmSCRATCH_ADDR)));
2489 dev_info(adev->dev, " SCRATCH_UMSK=0x%08X\n",
2490 RREG32(SOC15_REG_OFFSET(GC, 0, mmSCRATCH_UMSK)));
2491
2492 dev_info(adev->dev, " CP_INT_CNTL_RING0=0x%08X\n",
2493 RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING0)));
2494 dev_info(adev->dev, " RLC_LB_CNTL=0x%08X\n",
2495 RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_LB_CNTL)));
2496 dev_info(adev->dev, " RLC_CNTL=0x%08X\n",
2497 RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CNTL)));
2498 dev_info(adev->dev, " RLC_CGCG_CGLS_CTRL=0x%08X\n",
2499 RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CGCG_CGLS_CTRL)));
2500 dev_info(adev->dev, " RLC_LB_CNTR_INIT=0x%08X\n",
2501 RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_LB_CNTR_INIT)));
2502 dev_info(adev->dev, " RLC_LB_CNTR_MAX=0x%08X\n",
2503 RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_LB_CNTR_MAX)));
2504 dev_info(adev->dev, " RLC_LB_INIT_CU_MASK=0x%08X\n",
2505 RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_LB_INIT_CU_MASK)));
2506 dev_info(adev->dev, " RLC_LB_PARAMS=0x%08X\n",
2507 RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_LB_PARAMS)));
2508 dev_info(adev->dev, " RLC_LB_CNTL=0x%08X\n",
2509 RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_LB_CNTL)));
2510 dev_info(adev->dev, " RLC_UCODE_CNTL=0x%08X\n",
2511 RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_UCODE_CNTL)));
2512
2513 dev_info(adev->dev, " RLC_GPM_GENERAL_6=0x%08X\n",
2514 RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_GENERAL_6)));
2515 dev_info(adev->dev, " RLC_GPM_GENERAL_12=0x%08X\n",
2516 RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_GENERAL_12)));
2517 dev_info(adev->dev, " RLC_GPM_TIMER_INT_3=0x%08X\n",
2518 RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_TIMER_INT_3)));
2519 mutex_lock(&adev->srbm_mutex);
2520 for (i = 0; i < 16; i++) {
2521 soc15_grbm_select(adev, 0, 0, 0, i);
2522 dev_info(adev->dev, " VM %d:\n", i);
2523 dev_info(adev->dev, " SH_MEM_CONFIG=0x%08X\n",
2524 RREG32(SOC15_REG_OFFSET(GC, 0, mmSH_MEM_CONFIG)));
2525 dev_info(adev->dev, " SH_MEM_BASES=0x%08X\n",
2526 RREG32(SOC15_REG_OFFSET(GC, 0, mmSH_MEM_BASES)));
2527 }
2528 soc15_grbm_select(adev, 0, 0, 0, 0);
2529 mutex_unlock(&adev->srbm_mutex);
2530}
2531
2532static int gfx_v9_0_soft_reset(void *handle)
2533{
2534 u32 grbm_soft_reset = 0;
2535 u32 tmp;
2536 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2537
2538 /* GRBM_STATUS */
2539 tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmGRBM_STATUS));
2540 if (tmp & (GRBM_STATUS__PA_BUSY_MASK | GRBM_STATUS__SC_BUSY_MASK |
2541 GRBM_STATUS__BCI_BUSY_MASK | GRBM_STATUS__SX_BUSY_MASK |
2542 GRBM_STATUS__TA_BUSY_MASK | GRBM_STATUS__VGT_BUSY_MASK |
2543 GRBM_STATUS__DB_BUSY_MASK | GRBM_STATUS__CB_BUSY_MASK |
2544 GRBM_STATUS__GDS_BUSY_MASK | GRBM_STATUS__SPI_BUSY_MASK |
2545 GRBM_STATUS__IA_BUSY_MASK | GRBM_STATUS__IA_BUSY_NO_DMA_MASK)) {
2546 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
2547 GRBM_SOFT_RESET, SOFT_RESET_CP, 1);
2548 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
2549 GRBM_SOFT_RESET, SOFT_RESET_GFX, 1);
2550 }
2551
2552 if (tmp & (GRBM_STATUS__CP_BUSY_MASK | GRBM_STATUS__CP_COHERENCY_BUSY_MASK)) {
2553 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
2554 GRBM_SOFT_RESET, SOFT_RESET_CP, 1);
2555 }
2556
2557 /* GRBM_STATUS2 */
2558 tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmGRBM_STATUS2));
2559 if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY))
2560 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
2561 GRBM_SOFT_RESET, SOFT_RESET_RLC, 1);
2562
2563
2564 if (grbm_soft_reset ) {
2565 gfx_v9_0_print_status((void *)adev);
2566 /* stop the rlc */
2567 gfx_v9_0_rlc_stop(adev);
2568
2569 /* Disable GFX parsing/prefetching */
2570 gfx_v9_0_cp_gfx_enable(adev, false);
2571
2572 /* Disable MEC parsing/prefetching */
2573 gfx_v9_0_cp_compute_enable(adev, false);
2574
2575 if (grbm_soft_reset) {
2576 tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmGRBM_SOFT_RESET));
2577 tmp |= grbm_soft_reset;
2578 dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp);
2579 WREG32(SOC15_REG_OFFSET(GC, 0, mmGRBM_SOFT_RESET), tmp);
2580 tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmGRBM_SOFT_RESET));
2581
2582 udelay(50);
2583
2584 tmp &= ~grbm_soft_reset;
2585 WREG32(SOC15_REG_OFFSET(GC, 0, mmGRBM_SOFT_RESET), tmp);
2586 tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmGRBM_SOFT_RESET));
2587 }
2588
2589 /* Wait a little for things to settle down */
2590 udelay(50);
2591 gfx_v9_0_print_status((void *)adev);
2592 }
2593 return 0;
2594}
2595
2596static uint64_t gfx_v9_0_get_gpu_clock_counter(struct amdgpu_device *adev)
2597{
2598 uint64_t clock;
2599
2600 mutex_lock(&adev->gfx.gpu_clock_mutex);
2601 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CAPTURE_GPU_CLOCK_COUNT), 1);
2602 clock = (uint64_t)RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPU_CLOCK_COUNT_LSB)) |
2603 ((uint64_t)RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPU_CLOCK_COUNT_MSB)) << 32ULL);
2604 mutex_unlock(&adev->gfx.gpu_clock_mutex);
2605 return clock;
2606}
2607
2608static void gfx_v9_0_ring_emit_gds_switch(struct amdgpu_ring *ring,
2609 uint32_t vmid,
2610 uint32_t gds_base, uint32_t gds_size,
2611 uint32_t gws_base, uint32_t gws_size,
2612 uint32_t oa_base, uint32_t oa_size)
2613{
2614 gds_base = gds_base >> AMDGPU_GDS_SHIFT;
2615 gds_size = gds_size >> AMDGPU_GDS_SHIFT;
2616
2617 gws_base = gws_base >> AMDGPU_GWS_SHIFT;
2618 gws_size = gws_size >> AMDGPU_GWS_SHIFT;
2619
2620 oa_base = oa_base >> AMDGPU_OA_SHIFT;
2621 oa_size = oa_size >> AMDGPU_OA_SHIFT;
2622
2623 /* GDS Base */
2624 gfx_v9_0_write_data_to_reg(ring, 0, false,
2625 amdgpu_gds_reg_offset[vmid].mem_base,
2626 gds_base);
2627
2628 /* GDS Size */
2629 gfx_v9_0_write_data_to_reg(ring, 0, false,
2630 amdgpu_gds_reg_offset[vmid].mem_size,
2631 gds_size);
2632
2633 /* GWS */
2634 gfx_v9_0_write_data_to_reg(ring, 0, false,
2635 amdgpu_gds_reg_offset[vmid].gws,
2636 gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base);
2637
2638 /* OA */
2639 gfx_v9_0_write_data_to_reg(ring, 0, false,
2640 amdgpu_gds_reg_offset[vmid].oa,
2641 (1 << (oa_size + oa_base)) - (1 << oa_base));
2642}
2643
2644static int gfx_v9_0_early_init(void *handle)
2645{
2646 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2647
2648 adev->gfx.num_gfx_rings = GFX9_NUM_GFX_RINGS;
2649 adev->gfx.num_compute_rings = GFX9_NUM_COMPUTE_RINGS;
2650 gfx_v9_0_set_ring_funcs(adev);
2651 gfx_v9_0_set_irq_funcs(adev);
2652 gfx_v9_0_set_gds_init(adev);
2653 gfx_v9_0_set_rlc_funcs(adev);
2654
2655 return 0;
2656}
2657
2658static int gfx_v9_0_late_init(void *handle)
2659{
2660 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2661 int r;
2662
2663 r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0);
2664 if (r)
2665 return r;
2666
2667 r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0);
2668 if (r)
2669 return r;
2670
2671 return 0;
2672}
2673
2674static void gfx_v9_0_enter_rlc_safe_mode(struct amdgpu_device *adev)
2675{
2676 uint32_t rlc_setting, data;
2677 unsigned i;
2678
2679 if (adev->gfx.rlc.in_safe_mode)
2680 return;
2681
2682 /* if RLC is not enabled, do nothing */
2683 rlc_setting = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CNTL));
2684 if (!(rlc_setting & RLC_CNTL__RLC_ENABLE_F32_MASK))
2685 return;
2686
2687 if (adev->cg_flags &
2688 (AMD_CG_SUPPORT_GFX_CGCG | AMD_CG_SUPPORT_GFX_MGCG |
2689 AMD_CG_SUPPORT_GFX_3D_CGCG)) {
2690 data = RLC_SAFE_MODE__CMD_MASK;
2691 data |= (1 << RLC_SAFE_MODE__MESSAGE__SHIFT);
2692 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SAFE_MODE), data);
2693
2694 /* wait for RLC_SAFE_MODE */
2695 for (i = 0; i < adev->usec_timeout; i++) {
2696 if (!REG_GET_FIELD(SOC15_REG_OFFSET(GC, 0, mmRLC_SAFE_MODE), RLC_SAFE_MODE, CMD))
2697 break;
2698 udelay(1);
2699 }
2700 adev->gfx.rlc.in_safe_mode = true;
2701 }
2702}
2703
2704static void gfx_v9_0_exit_rlc_safe_mode(struct amdgpu_device *adev)
2705{
2706 uint32_t rlc_setting, data;
2707
2708 if (!adev->gfx.rlc.in_safe_mode)
2709 return;
2710
2711 /* if RLC is not enabled, do nothing */
2712 rlc_setting = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CNTL));
2713 if (!(rlc_setting & RLC_CNTL__RLC_ENABLE_F32_MASK))
2714 return;
2715
2716 if (adev->cg_flags &
2717 (AMD_CG_SUPPORT_GFX_CGCG | AMD_CG_SUPPORT_GFX_MGCG)) {
2718 /*
2719 * Try to exit safe mode only if it is already in safe
2720 * mode.
2721 */
2722 data = RLC_SAFE_MODE__CMD_MASK;
2723 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SAFE_MODE), data);
2724 adev->gfx.rlc.in_safe_mode = false;
2725 }
2726}
2727
2728static void gfx_v9_0_update_medium_grain_clock_gating(struct amdgpu_device *adev,
2729 bool enable)
2730{
2731 uint32_t data, def;
2732
2733 /* It is disabled by HW by default */
2734 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) {
2735 /* 1 - RLC_CGTT_MGCG_OVERRIDE */
2736 def = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE));
2737 data &= ~(RLC_CGTT_MGCG_OVERRIDE__CPF_CGTT_SCLK_OVERRIDE_MASK |
2738 RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK |
2739 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK |
2740 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK);
2741
2742 /* only for Vega10 & Raven1 */
2743 data |= RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK;
2744
2745 if (def != data)
2746 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE), data);
2747
2748 /* MGLS is a global flag to control all MGLS in GFX */
2749 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) {
2750 /* 2 - RLC memory Light sleep */
2751 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_RLC_LS) {
2752 def = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_MEM_SLP_CNTL));
2753 data |= RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK;
2754 if (def != data)
2755 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_MEM_SLP_CNTL), data);
2756 }
2757 /* 3 - CP memory Light sleep */
2758 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS) {
2759 def = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_MEM_SLP_CNTL));
2760 data |= CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
2761 if (def != data)
2762 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_MEM_SLP_CNTL), data);
2763 }
2764 }
2765 } else {
2766 /* 1 - MGCG_OVERRIDE */
2767 def = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE));
2768 data |= (RLC_CGTT_MGCG_OVERRIDE__CPF_CGTT_SCLK_OVERRIDE_MASK |
2769 RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK |
2770 RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK |
2771 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK |
2772 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK);
2773 if (def != data)
2774 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE), data);
2775
2776 /* 2 - disable MGLS in RLC */
2777 data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_MEM_SLP_CNTL));
2778 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) {
2779 data &= ~RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK;
2780 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_MEM_SLP_CNTL), data);
2781 }
2782
2783 /* 3 - disable MGLS in CP */
2784 data = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_MEM_SLP_CNTL));
2785 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) {
2786 data &= ~CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
2787 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_MEM_SLP_CNTL), data);
2788 }
2789 }
2790}
2791
2792static void gfx_v9_0_update_3d_clock_gating(struct amdgpu_device *adev,
2793 bool enable)
2794{
2795 uint32_t data, def;
2796
2797 adev->gfx.rlc.funcs->enter_safe_mode(adev);
2798
2799 /* Enable 3D CGCG/CGLS */
2800 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG)) {
2801 /* write cmd to clear cgcg/cgls ov */
2802 def = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE));
2803 /* unset CGCG override */
2804 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_GFX3D_CG_OVERRIDE_MASK;
2805 /* update CGCG and CGLS override bits */
2806 if (def != data)
2807 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE), data);
2808 /* enable 3Dcgcg FSM(0x0020003f) */
2809 def = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D));
2810 data = (0x2000 << RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD__SHIFT) |
2811 RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK;
2812 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS)
2813 data |= (0x000F << RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY__SHIFT) |
2814 RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK;
2815 if (def != data)
2816 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D), data);
2817
2818 /* set IDLE_POLL_COUNT(0x00900100) */
2819 def = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB_WPTR_POLL_CNTL));
2820 data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) |
2821 (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT);
2822 if (def != data)
2823 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB_WPTR_POLL_CNTL), data);
2824 } else {
2825 /* Disable CGCG/CGLS */
2826 def = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D));
2827 /* disable cgcg, cgls should be disabled */
2828 data &= ~(RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK |
2829 RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK);
2830 /* disable cgcg and cgls in FSM */
2831 if (def != data)
2832 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D), data);
2833 }
2834
2835 adev->gfx.rlc.funcs->exit_safe_mode(adev);
2836}
2837
2838static void gfx_v9_0_update_coarse_grain_clock_gating(struct amdgpu_device *adev,
2839 bool enable)
2840{
2841 uint32_t def, data;
2842
2843 adev->gfx.rlc.funcs->enter_safe_mode(adev);
2844
2845 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)) {
2846 def = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE));
2847 /* unset CGCG override */
2848 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE_MASK;
2849 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS)
2850 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK;
2851 else
2852 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK;
2853 /* update CGCG and CGLS override bits */
2854 if (def != data)
2855 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE), data);
2856
2857 /* enable cgcg FSM(0x0020003F) */
2858 def = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CGCG_CGLS_CTRL));
2859 data = (0x2000 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) |
2860 RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK;
2861 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS)
2862 data |= (0x000F << RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT) |
2863 RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK;
2864 if (def != data)
2865 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CGCG_CGLS_CTRL), data);
2866
2867 /* set IDLE_POLL_COUNT(0x00900100) */
2868 def = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB_WPTR_POLL_CNTL));
2869 data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) |
2870 (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT);
2871 if (def != data)
2872 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB_WPTR_POLL_CNTL), data);
2873 } else {
2874 def = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CGCG_CGLS_CTRL));
2875 /* reset CGCG/CGLS bits */
2876 data &= ~(RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK);
2877 /* disable cgcg and cgls in FSM */
2878 if (def != data)
2879 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CGCG_CGLS_CTRL), data);
2880 }
2881
2882 adev->gfx.rlc.funcs->exit_safe_mode(adev);
2883}
2884
2885static int gfx_v9_0_update_gfx_clock_gating(struct amdgpu_device *adev,
2886 bool enable)
2887{
2888 if (enable) {
2889 /* CGCG/CGLS should be enabled after MGCG/MGLS
2890 * === MGCG + MGLS ===
2891 */
2892 gfx_v9_0_update_medium_grain_clock_gating(adev, enable);
2893 /* === CGCG /CGLS for GFX 3D Only === */
2894 gfx_v9_0_update_3d_clock_gating(adev, enable);
2895 /* === CGCG + CGLS === */
2896 gfx_v9_0_update_coarse_grain_clock_gating(adev, enable);
2897 } else {
2898 /* CGCG/CGLS should be disabled before MGCG/MGLS
2899 * === CGCG + CGLS ===
2900 */
2901 gfx_v9_0_update_coarse_grain_clock_gating(adev, enable);
2902 /* === CGCG /CGLS for GFX 3D Only === */
2903 gfx_v9_0_update_3d_clock_gating(adev, enable);
2904 /* === MGCG + MGLS === */
2905 gfx_v9_0_update_medium_grain_clock_gating(adev, enable);
2906 }
2907 return 0;
2908}
2909
2910static const struct amdgpu_rlc_funcs gfx_v9_0_rlc_funcs = {
2911 .enter_safe_mode = gfx_v9_0_enter_rlc_safe_mode,
2912 .exit_safe_mode = gfx_v9_0_exit_rlc_safe_mode
2913};
2914
2915static int gfx_v9_0_set_powergating_state(void *handle,
2916 enum amd_powergating_state state)
2917{
2918 return 0;
2919}
2920
2921static int gfx_v9_0_set_clockgating_state(void *handle,
2922 enum amd_clockgating_state state)
2923{
2924 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2925
2926 switch (adev->asic_type) {
2927 case CHIP_VEGA10:
2928 gfx_v9_0_update_gfx_clock_gating(adev,
2929 state == AMD_CG_STATE_GATE ? true : false);
2930 break;
2931 default:
2932 break;
2933 }
2934 return 0;
2935}
2936
2937static u64 gfx_v9_0_ring_get_rptr_gfx(struct amdgpu_ring *ring)
2938{
2939 return ring->adev->wb.wb[ring->rptr_offs]; /* gfx9 is 32bit rptr*/
2940}
2941
2942static u64 gfx_v9_0_ring_get_wptr_gfx(struct amdgpu_ring *ring)
2943{
2944 struct amdgpu_device *adev = ring->adev;
2945 u64 wptr;
2946
2947 /* XXX check if swapping is necessary on BE */
2948 if (ring->use_doorbell) {
2949 wptr = atomic64_read((atomic64_t *)&adev->wb.wb[ring->wptr_offs]);
2950 } else {
2951 wptr = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB0_WPTR));
2952 wptr += (u64)RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB0_WPTR_HI)) << 32;
2953 }
2954
2955 return wptr;
2956}
2957
2958static void gfx_v9_0_ring_set_wptr_gfx(struct amdgpu_ring *ring)
2959{
2960 struct amdgpu_device *adev = ring->adev;
2961
2962 if (ring->use_doorbell) {
2963 /* XXX check if swapping is necessary on BE */
2964 atomic64_set((atomic64_t*)&adev->wb.wb[ring->wptr_offs], ring->wptr);
2965 WDOORBELL64(ring->doorbell_index, ring->wptr);
2966 } else {
2967 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB0_WPTR), lower_32_bits(ring->wptr));
2968 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB0_WPTR_HI), upper_32_bits(ring->wptr));
2969 }
2970}
2971
2972static void gfx_v9_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
2973{
2974 u32 ref_and_mask, reg_mem_engine;
2975 struct nbio_hdp_flush_reg *nbio_hf_reg;
2976
2977 if (ring->adev->asic_type == CHIP_VEGA10)
2978 nbio_hf_reg = &nbio_v6_1_hdp_flush_reg;
2979
2980 if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) {
2981 switch (ring->me) {
2982 case 1:
2983 ref_and_mask = nbio_hf_reg->ref_and_mask_cp2 << ring->pipe;
2984 break;
2985 case 2:
2986 ref_and_mask = nbio_hf_reg->ref_and_mask_cp6 << ring->pipe;
2987 break;
2988 default:
2989 return;
2990 }
2991 reg_mem_engine = 0;
2992 } else {
2993 ref_and_mask = nbio_hf_reg->ref_and_mask_cp0;
2994 reg_mem_engine = 1; /* pfp */
2995 }
2996
2997 gfx_v9_0_wait_reg_mem(ring, reg_mem_engine, 0, 1,
2998 nbio_hf_reg->hdp_flush_req_offset,
2999 nbio_hf_reg->hdp_flush_done_offset,
3000 ref_and_mask, ref_and_mask, 0x20);
3001}
3002
3003static void gfx_v9_0_ring_emit_hdp_invalidate(struct amdgpu_ring *ring)
3004{
3005 gfx_v9_0_write_data_to_reg(ring, 0, true,
3006 SOC15_REG_OFFSET(HDP, 0, mmHDP_DEBUG0), 1);
3007}
3008
3009static void gfx_v9_0_ring_emit_ib_gfx(struct amdgpu_ring *ring,
3010 struct amdgpu_ib *ib,
3011 unsigned vm_id, bool ctx_switch)
3012{
3013 u32 header, control = 0;
3014
3015 if (ib->flags & AMDGPU_IB_FLAG_CE)
3016 header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2);
3017 else
3018 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);
3019
3020 control |= ib->length_dw | (vm_id << 24);
3021
3022 amdgpu_ring_write(ring, header);
3023 BUG_ON(ib->gpu_addr & 0x3); /* Dword align */
3024 amdgpu_ring_write(ring,
3025#ifdef __BIG_ENDIAN
3026 (2 << 0) |
3027#endif
3028 lower_32_bits(ib->gpu_addr));
3029 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
3030 amdgpu_ring_write(ring, control);
3031}
3032
3033#define INDIRECT_BUFFER_VALID (1 << 23)
3034
3035static void gfx_v9_0_ring_emit_ib_compute(struct amdgpu_ring *ring,
3036 struct amdgpu_ib *ib,
3037 unsigned vm_id, bool ctx_switch)
3038{
3039 u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vm_id << 24);
3040
3041 amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
3042 BUG_ON(ib->gpu_addr & 0x3); /* Dword align */
3043 amdgpu_ring_write(ring,
3044#ifdef __BIG_ENDIAN
3045 (2 << 0) |
3046#endif
3047 lower_32_bits(ib->gpu_addr));
3048 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
3049 amdgpu_ring_write(ring, control);
3050}
3051
3052static void gfx_v9_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr,
3053 u64 seq, unsigned flags)
3054{
3055 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
3056 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT;
3057
3058 /* RELEASE_MEM - flush caches, send int */
3059 amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 6));
3060 amdgpu_ring_write(ring, (EOP_TCL1_ACTION_EN |
3061 EOP_TC_ACTION_EN |
3062 EOP_TC_WB_ACTION_EN |
3063 EOP_TC_MD_ACTION_EN |
3064 EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |
3065 EVENT_INDEX(5)));
3066 amdgpu_ring_write(ring, DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0));
3067
3068 /*
3069 * the address should be Qword aligned if 64bit write, Dword
3070 * aligned if only send 32bit data low (discard data high)
3071 */
3072 if (write64bit)
3073 BUG_ON(addr & 0x7);
3074 else
3075 BUG_ON(addr & 0x3);
3076 amdgpu_ring_write(ring, lower_32_bits(addr));
3077 amdgpu_ring_write(ring, upper_32_bits(addr));
3078 amdgpu_ring_write(ring, lower_32_bits(seq));
3079 amdgpu_ring_write(ring, upper_32_bits(seq));
3080 amdgpu_ring_write(ring, 0);
3081}
3082
3083static void gfx_v9_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
3084{
3085 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
3086 uint32_t seq = ring->fence_drv.sync_seq;
3087 uint64_t addr = ring->fence_drv.gpu_addr;
3088
3089 gfx_v9_0_wait_reg_mem(ring, usepfp, 1, 0,
3090 lower_32_bits(addr), upper_32_bits(addr),
3091 seq, 0xffffffff, 4);
3092}
3093
3094static void gfx_v9_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
3095 unsigned vm_id, uint64_t pd_addr)
3096{
3097 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
3098 unsigned eng = ring->idx;
3099 unsigned i;
3100
3101 pd_addr = pd_addr | 0x1; /* valid bit */
3102 /* now only use physical base address of PDE and valid */
3103 BUG_ON(pd_addr & 0xFFFF00000000003EULL);
3104
3105 for (i = 0; i < AMDGPU_MAX_VMHUBS; ++i) {
3106 struct amdgpu_vmhub *hub = &ring->adev->vmhub[i];
3107 uint32_t req = hub->get_invalidate_req(vm_id);
3108
3109 gfx_v9_0_write_data_to_reg(ring, usepfp, true,
3110 hub->ctx0_ptb_addr_lo32
3111 + (2 * vm_id),
3112 lower_32_bits(pd_addr));
3113
3114 gfx_v9_0_write_data_to_reg(ring, usepfp, true,
3115 hub->ctx0_ptb_addr_hi32
3116 + (2 * vm_id),
3117 upper_32_bits(pd_addr));
3118
3119 gfx_v9_0_write_data_to_reg(ring, usepfp, true,
3120 hub->vm_inv_eng0_req + eng, req);
3121
3122 /* wait for the invalidate to complete */
3123 gfx_v9_0_wait_reg_mem(ring, 0, 0, 0, hub->vm_inv_eng0_ack +
3124 eng, 0, 1 << vm_id, 1 << vm_id, 0x20);
3125 }
3126
3127 /* compute doesn't have PFP */
3128 if (usepfp) {
3129 /* sync PFP to ME, otherwise we might get invalid PFP reads */
3130 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));
3131 amdgpu_ring_write(ring, 0x0);
3132 /* Emits 128 dw nop to prevent CE access VM before vm_flush finish */
3133 amdgpu_ring_insert_nop(ring, 128);
3134 }
3135}
3136
3137static u64 gfx_v9_0_ring_get_rptr_compute(struct amdgpu_ring *ring)
3138{
3139 return ring->adev->wb.wb[ring->rptr_offs]; /* gfx9 hardware is 32bit rptr */
3140}
3141
3142static u64 gfx_v9_0_ring_get_wptr_compute(struct amdgpu_ring *ring)
3143{
3144 u64 wptr;
3145
3146 /* XXX check if swapping is necessary on BE */
3147 if (ring->use_doorbell)
3148 wptr = atomic64_read((atomic64_t *)&ring->adev->wb.wb[ring->wptr_offs]);
3149 else
3150 BUG();
3151 return wptr;
3152}
3153
3154static void gfx_v9_0_ring_set_wptr_compute(struct amdgpu_ring *ring)
3155{
3156 struct amdgpu_device *adev = ring->adev;
3157
3158 /* XXX check if swapping is necessary on BE */
3159 if (ring->use_doorbell) {
3160 atomic64_set((atomic64_t*)&adev->wb.wb[ring->wptr_offs], ring->wptr);
3161 WDOORBELL64(ring->doorbell_index, ring->wptr);
3162 } else{
3163 BUG(); /* only DOORBELL method supported on gfx9 now */
3164 }
3165}
3166
aa6faa44
XY		 3167static void gfx_v9_0_ring_emit_fence_kiq(struct amdgpu_ring *ring, u64 addr,
3168 u64 seq, unsigned int flags)
3169{
3170 /* we only allocate 32bit for each seq wb address */
3171 BUG_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
3172
3173 /* write fence seq to the "addr" */
3174 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
3175 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
3176 WRITE_DATA_DST_SEL(5) | WR_CONFIRM));
3177 amdgpu_ring_write(ring, lower_32_bits(addr));
3178 amdgpu_ring_write(ring, upper_32_bits(addr));
3179 amdgpu_ring_write(ring, lower_32_bits(seq));
3180
3181 if (flags & AMDGPU_FENCE_FLAG_INT) {
3182 /* set register to trigger INT */
3183 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
3184 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
3185 WRITE_DATA_DST_SEL(0) | WR_CONFIRM));
3186 amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, 0, mmCPC_INT_STATUS));
3187 amdgpu_ring_write(ring, 0);
3188 amdgpu_ring_write(ring, 0x20000000); /* src_id is 178 */
3189 }
3190}
3191
b1023571
KW		 3192static void gfx_v9_ring_emit_sb(struct amdgpu_ring *ring)
3193{
3194 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
3195 amdgpu_ring_write(ring, 0);
3196}
3197
cca02cd3
XY		 3198static void gfx_v9_0_ring_emit_ce_meta(struct amdgpu_ring *ring)
3199{
3200 static struct v9_ce_ib_state ce_payload = {0};
3201 uint64_t csa_addr;
3202 int cnt;
3203
3204 cnt = (sizeof(ce_payload) >> 2) + 4 - 2;
3205 csa_addr = AMDGPU_VA_RESERVED_SIZE - 2 * 4096;
3206
3207 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt));
3208 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(2) |
3209 WRITE_DATA_DST_SEL(8) |
3210 WR_CONFIRM) |
3211 WRITE_DATA_CACHE_POLICY(0));
3212 amdgpu_ring_write(ring, lower_32_bits(csa_addr + offsetof(struct v9_gfx_meta_data, ce_payload)));
3213 amdgpu_ring_write(ring, upper_32_bits(csa_addr + offsetof(struct v9_gfx_meta_data, ce_payload)));
3214 amdgpu_ring_write_multiple(ring, (void *)&ce_payload, sizeof(ce_payload) >> 2);
3215}
3216
3217static void gfx_v9_0_ring_emit_de_meta(struct amdgpu_ring *ring)
3218{
3219 static struct v9_de_ib_state de_payload = {0};
3220 uint64_t csa_addr, gds_addr;
3221 int cnt;
3222
3223 csa_addr = AMDGPU_VA_RESERVED_SIZE - 2 * 4096;
3224 gds_addr = csa_addr + 4096;
3225 de_payload.gds_backup_addrlo = lower_32_bits(gds_addr);
3226 de_payload.gds_backup_addrhi = upper_32_bits(gds_addr);
3227
3228 cnt = (sizeof(de_payload) >> 2) + 4 - 2;
3229 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt));
3230 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) |
3231 WRITE_DATA_DST_SEL(8) |
3232 WR_CONFIRM) |
3233 WRITE_DATA_CACHE_POLICY(0));
3234 amdgpu_ring_write(ring, lower_32_bits(csa_addr + offsetof(struct v9_gfx_meta_data, de_payload)));
3235 amdgpu_ring_write(ring, upper_32_bits(csa_addr + offsetof(struct v9_gfx_meta_data, de_payload)));
3236 amdgpu_ring_write_multiple(ring, (void *)&de_payload, sizeof(de_payload) >> 2);
3237}
3238
b1023571
KW		 3239static void gfx_v9_ring_emit_cntxcntl(struct amdgpu_ring *ring, uint32_t flags)
3240{
3241 uint32_t dw2 = 0;
3242
cca02cd3
XY		 3243 if (amdgpu_sriov_vf(ring->adev))
3244 gfx_v9_0_ring_emit_ce_meta(ring);
3245
b1023571
KW		 3246 dw2 |= 0x80000000; /* set load_enable otherwise this package is just NOPs */
3247 if (flags & AMDGPU_HAVE_CTX_SWITCH) {
3248 /* set load_global_config & load_global_uconfig */
3249 dw2 |= 0x8001;
3250 /* set load_cs_sh_regs */
3251 dw2 |= 0x01000000;
3252 /* set load_per_context_state & load_gfx_sh_regs for GFX */
3253 dw2 |= 0x10002;
3254
3255 /* set load_ce_ram if preamble presented */
3256 if (AMDGPU_PREAMBLE_IB_PRESENT & flags)
3257 dw2 |= 0x10000000;
3258 } else {
3259 /* still load_ce_ram if this is the first time preamble presented
3260 * although there is no context switch happens.
3261 */
3262 if (AMDGPU_PREAMBLE_IB_PRESENT_FIRST & flags)
3263 dw2 |= 0x10000000;
3264 }
3265
3266 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
3267 amdgpu_ring_write(ring, dw2);
3268 amdgpu_ring_write(ring, 0);
cca02cd3
XY		 3269
3270 if (amdgpu_sriov_vf(ring->adev))
3271 gfx_v9_0_ring_emit_de_meta(ring);
b1023571
KW		 3272}
3273
9a5e02b5
ML		 3274static unsigned gfx_v9_0_ring_emit_init_cond_exec(struct amdgpu_ring *ring)
3275{
3276 unsigned ret;
3277 amdgpu_ring_write(ring, PACKET3(PACKET3_COND_EXEC, 3));
3278 amdgpu_ring_write(ring, lower_32_bits(ring->cond_exe_gpu_addr));
3279 amdgpu_ring_write(ring, upper_32_bits(ring->cond_exe_gpu_addr));
3280 amdgpu_ring_write(ring, 0); /* discard following DWs if *cond_exec_gpu_addr==0 */
3281 ret = ring->wptr & ring->buf_mask;
3282 amdgpu_ring_write(ring, 0x55aa55aa); /* patch dummy value later */
3283 return ret;
3284}
3285
3286static void gfx_v9_0_ring_emit_patch_cond_exec(struct amdgpu_ring *ring, unsigned offset)
3287{
3288 unsigned cur;
3289 BUG_ON(offset > ring->buf_mask);
3290 BUG_ON(ring->ring[offset] != 0x55aa55aa);
3291
3292 cur = (ring->wptr & ring->buf_mask) - 1;
3293 if (likely(cur > offset))
3294 ring->ring[offset] = cur - offset;
3295 else
3296 ring->ring[offset] = (ring->ring_size>>2) - offset + cur;
3297}
3298
aa6faa44
XY		 3299static void gfx_v9_0_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg)
3300{
3301 struct amdgpu_device *adev = ring->adev;
3302
3303 amdgpu_ring_write(ring, PACKET3(PACKET3_COPY_DATA, 4));
3304 amdgpu_ring_write(ring, 0 | /* src: register*/
3305 (5 << 8) | /* dst: memory */
3306 (1 << 20)); /* write confirm */
3307 amdgpu_ring_write(ring, reg);
3308 amdgpu_ring_write(ring, 0);
3309 amdgpu_ring_write(ring, lower_32_bits(adev->wb.gpu_addr +
3310 adev->virt.reg_val_offs * 4));
3311 amdgpu_ring_write(ring, upper_32_bits(adev->wb.gpu_addr +
3312 adev->virt.reg_val_offs * 4));
3313}
3314
3315static void gfx_v9_0_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg,
3316 uint32_t val)
3317{
3318 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
3319 amdgpu_ring_write(ring, (1 << 16)); /* no inc addr */
3320 amdgpu_ring_write(ring, reg);
3321 amdgpu_ring_write(ring, 0);
3322 amdgpu_ring_write(ring, val);
3323}
3324
b1023571
KW		 3325static void gfx_v9_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev,
3326 enum amdgpu_interrupt_state state)
3327{
3328 u32 cp_int_cntl;
3329
3330 switch (state) {
3331 case AMDGPU_IRQ_STATE_DISABLE:
3332 cp_int_cntl = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING0));
3333 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
3334 TIME_STAMP_INT_ENABLE, 0);
3335 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING0), cp_int_cntl);
3336 break;
3337 case AMDGPU_IRQ_STATE_ENABLE:
3338 cp_int_cntl = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING0));
3339 cp_int_cntl =
3340 REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
3341 TIME_STAMP_INT_ENABLE, 1);
3342 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING0), cp_int_cntl);
3343 break;
3344 default:
3345 break;
3346 }
3347}
3348
3349static void gfx_v9_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev,
3350 int me, int pipe,
3351 enum amdgpu_interrupt_state state)
3352{
3353 u32 mec_int_cntl, mec_int_cntl_reg;
3354
3355 /*
3356 * amdgpu controls only pipe 0 of MEC1. That's why this function only
3357 * handles the setting of interrupts for this specific pipe. All other
3358 * pipes' interrupts are set by amdkfd.
3359 */
3360
3361 if (me == 1) {
3362 switch (pipe) {
3363 case 0:
3364 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL);
3365 break;
3366 default:
3367 DRM_DEBUG("invalid pipe %d\n", pipe);
3368 return;
3369 }
3370 } else {
3371 DRM_DEBUG("invalid me %d\n", me);
3372 return;
3373 }
3374
3375 switch (state) {
3376 case AMDGPU_IRQ_STATE_DISABLE:
3377 mec_int_cntl = RREG32(mec_int_cntl_reg);
3378 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
3379 TIME_STAMP_INT_ENABLE, 0);
3380 WREG32(mec_int_cntl_reg, mec_int_cntl);
3381 break;
3382 case AMDGPU_IRQ_STATE_ENABLE:
3383 mec_int_cntl = RREG32(mec_int_cntl_reg);
3384 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
3385 TIME_STAMP_INT_ENABLE, 1);
3386 WREG32(mec_int_cntl_reg, mec_int_cntl);
3387 break;
3388 default:
3389 break;
3390 }
3391}
3392
3393static int gfx_v9_0_set_priv_reg_fault_state(struct amdgpu_device *adev,
3394 struct amdgpu_irq_src *source,
3395 unsigned type,
3396 enum amdgpu_interrupt_state state)
3397{
3398 u32 cp_int_cntl;
3399
3400 switch (state) {
3401 case AMDGPU_IRQ_STATE_DISABLE:
3402 cp_int_cntl = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING0));
3403 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
3404 PRIV_REG_INT_ENABLE, 0);
3405 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING0), cp_int_cntl);
3406 break;
3407 case AMDGPU_IRQ_STATE_ENABLE:
3408 cp_int_cntl = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING0));
3409 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
3410 PRIV_REG_INT_ENABLE, 1);
3411 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING0), cp_int_cntl);
3412 break;
3413 default:
3414 break;
3415 }
3416
3417 return 0;
3418}
3419
3420static int gfx_v9_0_set_priv_inst_fault_state(struct amdgpu_device *adev,
3421 struct amdgpu_irq_src *source,
3422 unsigned type,
3423 enum amdgpu_interrupt_state state)
3424{
3425 u32 cp_int_cntl;
3426
3427 switch (state) {
3428 case AMDGPU_IRQ_STATE_DISABLE:
3429 cp_int_cntl = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING0));
3430 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
3431 PRIV_INSTR_INT_ENABLE, 0);
3432 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING0), cp_int_cntl);
3433 break;
3434 case AMDGPU_IRQ_STATE_ENABLE:
3435 cp_int_cntl = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING0));
3436 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
3437 PRIV_INSTR_INT_ENABLE, 1);
3438 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING0), cp_int_cntl);
3439 break;
3440 default:
3441 break;
3442 }
3443
3444 return 0;
3445}
3446
3447static int gfx_v9_0_set_eop_interrupt_state(struct amdgpu_device *adev,
3448 struct amdgpu_irq_src *src,
3449 unsigned type,
3450 enum amdgpu_interrupt_state state)
3451{
3452 switch (type) {
3453 case AMDGPU_CP_IRQ_GFX_EOP:
3454 gfx_v9_0_set_gfx_eop_interrupt_state(adev, state);
3455 break;
3456 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP:
3457 gfx_v9_0_set_compute_eop_interrupt_state(adev, 1, 0, state);
3458 break;
3459 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP:
3460 gfx_v9_0_set_compute_eop_interrupt_state(adev, 1, 1, state);
3461 break;
3462 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP:
3463 gfx_v9_0_set_compute_eop_interrupt_state(adev, 1, 2, state);
3464 break;
3465 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP:
3466 gfx_v9_0_set_compute_eop_interrupt_state(adev, 1, 3, state);
3467 break;
3468 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP:
3469 gfx_v9_0_set_compute_eop_interrupt_state(adev, 2, 0, state);
3470 break;
3471 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP:
3472 gfx_v9_0_set_compute_eop_interrupt_state(adev, 2, 1, state);
3473 break;
3474 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP:
3475 gfx_v9_0_set_compute_eop_interrupt_state(adev, 2, 2, state);
3476 break;
3477 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP:
3478 gfx_v9_0_set_compute_eop_interrupt_state(adev, 2, 3, state);
3479 break;
3480 default:
3481 break;
3482 }
3483 return 0;
3484}
3485
3486static int gfx_v9_0_eop_irq(struct amdgpu_device *adev,
3487 struct amdgpu_irq_src *source,
3488 struct amdgpu_iv_entry *entry)
3489{
3490 int i;
3491 u8 me_id, pipe_id, queue_id;
3492 struct amdgpu_ring *ring;
3493
3494 DRM_DEBUG("IH: CP EOP\n");
3495 me_id = (entry->ring_id & 0x0c) >> 2;
3496 pipe_id = (entry->ring_id & 0x03) >> 0;
3497 queue_id = (entry->ring_id & 0x70) >> 4;
3498
3499 switch (me_id) {
3500 case 0:
3501 amdgpu_fence_process(&adev->gfx.gfx_ring[0]);
3502 break;
3503 case 1:
3504 case 2:
3505 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
3506 ring = &adev->gfx.compute_ring[i];
3507 /* Per-queue interrupt is supported for MEC starting from VI.
3508 * The interrupt can only be enabled/disabled per pipe instead of per queue.
3509 */
3510 if ((ring->me == me_id) && (ring->pipe == pipe_id) && (ring->queue == queue_id))
3511 amdgpu_fence_process(ring);
3512 }
3513 break;
3514 }
3515 return 0;
3516}
3517
3518static int gfx_v9_0_priv_reg_irq(struct amdgpu_device *adev,
3519 struct amdgpu_irq_src *source,
3520 struct amdgpu_iv_entry *entry)
3521{
3522 DRM_ERROR("Illegal register access in command stream\n");
3523 schedule_work(&adev->reset_work);
3524 return 0;
3525}
3526
3527static int gfx_v9_0_priv_inst_irq(struct amdgpu_device *adev,
3528 struct amdgpu_irq_src *source,
3529 struct amdgpu_iv_entry *entry)
3530{
3531 DRM_ERROR("Illegal instruction in command stream\n");
3532 schedule_work(&adev->reset_work);
3533 return 0;
3534}
3535
97031e25
XY		 3536static int gfx_v9_0_kiq_set_interrupt_state(struct amdgpu_device *adev,
3537 struct amdgpu_irq_src *src,
3538 unsigned int type,
3539 enum amdgpu_interrupt_state state)
3540{
3541 uint32_t tmp, target;
3542 struct amdgpu_ring *ring = (struct amdgpu_ring *)src->data;
3543
3544 BUG_ON(!ring || (ring->funcs->type != AMDGPU_RING_TYPE_KIQ));
3545
3546 if (ring->me == 1)
3547 target = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL);
3548 else
3549 target = SOC15_REG_OFFSET(GC, 0, mmCP_ME2_PIPE0_INT_CNTL);
3550 target += ring->pipe;
3551
3552 switch (type) {
3553 case AMDGPU_CP_KIQ_IRQ_DRIVER0:
3554 if (state == AMDGPU_IRQ_STATE_DISABLE) {
3555 tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmCPC_INT_CNTL));
3556 tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL,
3557 GENERIC2_INT_ENABLE, 0);
3558 WREG32(SOC15_REG_OFFSET(GC, 0, mmCPC_INT_CNTL), tmp);
3559
3560 tmp = RREG32(target);
3561 tmp = REG_SET_FIELD(tmp, CP_ME2_PIPE0_INT_CNTL,
3562 GENERIC2_INT_ENABLE, 0);
3563 WREG32(target, tmp);
3564 } else {
3565 tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmCPC_INT_CNTL));
3566 tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL,
3567 GENERIC2_INT_ENABLE, 1);
3568 WREG32(SOC15_REG_OFFSET(GC, 0, mmCPC_INT_CNTL), tmp);
3569
3570 tmp = RREG32(target);
3571 tmp = REG_SET_FIELD(tmp, CP_ME2_PIPE0_INT_CNTL,
3572 GENERIC2_INT_ENABLE, 1);
3573 WREG32(target, tmp);
3574 }
3575 break;
3576 default:
3577 BUG(); /* kiq only support GENERIC2_INT now */
3578 break;
3579 }
3580 return 0;
3581}
3582
3583static int gfx_v9_0_kiq_irq(struct amdgpu_device *adev,
3584 struct amdgpu_irq_src *source,
3585 struct amdgpu_iv_entry *entry)
3586{
3587 u8 me_id, pipe_id, queue_id;
3588 struct amdgpu_ring *ring = (struct amdgpu_ring *)source->data;
3589
3590 BUG_ON(!ring || (ring->funcs->type != AMDGPU_RING_TYPE_KIQ));
3591
3592 me_id = (entry->ring_id & 0x0c) >> 2;
3593 pipe_id = (entry->ring_id & 0x03) >> 0;
3594 queue_id = (entry->ring_id & 0x70) >> 4;
3595 DRM_DEBUG("IH: CPC GENERIC2_INT, me:%d, pipe:%d, queue:%d\n",
3596 me_id, pipe_id, queue_id);
3597
3598 amdgpu_fence_process(ring);
3599 return 0;
3600}
3601
b1023571
KW		 3602const struct amd_ip_funcs gfx_v9_0_ip_funcs = {
3603 .name = "gfx_v9_0",
3604 .early_init = gfx_v9_0_early_init,
3605 .late_init = gfx_v9_0_late_init,
3606 .sw_init = gfx_v9_0_sw_init,
3607 .sw_fini = gfx_v9_0_sw_fini,
3608 .hw_init = gfx_v9_0_hw_init,
3609 .hw_fini = gfx_v9_0_hw_fini,
3610 .suspend = gfx_v9_0_suspend,
3611 .resume = gfx_v9_0_resume,
3612 .is_idle = gfx_v9_0_is_idle,
3613 .wait_for_idle = gfx_v9_0_wait_for_idle,
3614 .soft_reset = gfx_v9_0_soft_reset,
3615 .set_clockgating_state = gfx_v9_0_set_clockgating_state,
3616 .set_powergating_state = gfx_v9_0_set_powergating_state,
3617};
3618
3619static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_gfx = {
3620 .type = AMDGPU_RING_TYPE_GFX,
3621 .align_mask = 0xff,
3622 .nop = PACKET3(PACKET3_NOP, 0x3FFF),
3623 .support_64bit_ptrs = true,
3624 .get_rptr = gfx_v9_0_ring_get_rptr_gfx,
3625 .get_wptr = gfx_v9_0_ring_get_wptr_gfx,
3626 .set_wptr = gfx_v9_0_ring_set_wptr_gfx,
3627 .emit_frame_size =
3628 20 + /* gfx_v9_0_ring_emit_gds_switch */
3629 7 + /* gfx_v9_0_ring_emit_hdp_flush */
3630 5 + /* gfx_v9_0_ring_emit_hdp_invalidate */
3631 8 + 8 + 8 +/* gfx_v9_0_ring_emit_fence x3 for user fence, vm fence */
3632 7 + /* gfx_v9_0_ring_emit_pipeline_sync */
3633 128 + 66 + /* gfx_v9_0_ring_emit_vm_flush */
3634 2 + /* gfx_v9_ring_emit_sb */
3635 3, /* gfx_v9_ring_emit_cntxcntl */
3636 .emit_ib_size = 4, /* gfx_v9_0_ring_emit_ib_gfx */
3637 .emit_ib = gfx_v9_0_ring_emit_ib_gfx,
3638 .emit_fence = gfx_v9_0_ring_emit_fence,
3639 .emit_pipeline_sync = gfx_v9_0_ring_emit_pipeline_sync,
3640 .emit_vm_flush = gfx_v9_0_ring_emit_vm_flush,
3641 .emit_gds_switch = gfx_v9_0_ring_emit_gds_switch,
3642 .emit_hdp_flush = gfx_v9_0_ring_emit_hdp_flush,
3643 .emit_hdp_invalidate = gfx_v9_0_ring_emit_hdp_invalidate,
3644 .test_ring = gfx_v9_0_ring_test_ring,
3645 .test_ib = gfx_v9_0_ring_test_ib,
3646 .insert_nop = amdgpu_ring_insert_nop,
3647 .pad_ib = amdgpu_ring_generic_pad_ib,
3648 .emit_switch_buffer = gfx_v9_ring_emit_sb,
3649 .emit_cntxcntl = gfx_v9_ring_emit_cntxcntl,
9a5e02b5
ML		 3650 .init_cond_exec = gfx_v9_0_ring_emit_init_cond_exec,
3651 .patch_cond_exec = gfx_v9_0_ring_emit_patch_cond_exec,
b1023571
KW		 3652};
3653
3654static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_compute = {
3655 .type = AMDGPU_RING_TYPE_COMPUTE,
3656 .align_mask = 0xff,
3657 .nop = PACKET3(PACKET3_NOP, 0x3FFF),
3658 .support_64bit_ptrs = true,
3659 .get_rptr = gfx_v9_0_ring_get_rptr_compute,
3660 .get_wptr = gfx_v9_0_ring_get_wptr_compute,
3661 .set_wptr = gfx_v9_0_ring_set_wptr_compute,
3662 .emit_frame_size =
3663 20 + /* gfx_v9_0_ring_emit_gds_switch */
3664 7 + /* gfx_v9_0_ring_emit_hdp_flush */
3665 5 + /* gfx_v9_0_ring_emit_hdp_invalidate */
3666 7 + /* gfx_v9_0_ring_emit_pipeline_sync */
3667 64 + /* gfx_v9_0_ring_emit_vm_flush */
3668 8 + 8 + 8, /* gfx_v9_0_ring_emit_fence x3 for user fence, vm fence */
3669 .emit_ib_size = 4, /* gfx_v9_0_ring_emit_ib_compute */
3670 .emit_ib = gfx_v9_0_ring_emit_ib_compute,
3671 .emit_fence = gfx_v9_0_ring_emit_fence,
3672 .emit_pipeline_sync = gfx_v9_0_ring_emit_pipeline_sync,
3673 .emit_vm_flush = gfx_v9_0_ring_emit_vm_flush,
3674 .emit_gds_switch = gfx_v9_0_ring_emit_gds_switch,
3675 .emit_hdp_flush = gfx_v9_0_ring_emit_hdp_flush,
3676 .emit_hdp_invalidate = gfx_v9_0_ring_emit_hdp_invalidate,
3677 .test_ring = gfx_v9_0_ring_test_ring,
3678 .test_ib = gfx_v9_0_ring_test_ib,
3679 .insert_nop = amdgpu_ring_insert_nop,
3680 .pad_ib = amdgpu_ring_generic_pad_ib,
3681};
3682
aa6faa44
XY		 3683static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_kiq = {
3684 .type = AMDGPU_RING_TYPE_KIQ,
3685 .align_mask = 0xff,
3686 .nop = PACKET3(PACKET3_NOP, 0x3FFF),
3687 .support_64bit_ptrs = true,
3688 .get_rptr = gfx_v9_0_ring_get_rptr_compute,
3689 .get_wptr = gfx_v9_0_ring_get_wptr_compute,
3690 .set_wptr = gfx_v9_0_ring_set_wptr_compute,
3691 .emit_frame_size =
3692 20 + /* gfx_v9_0_ring_emit_gds_switch */
3693 7 + /* gfx_v9_0_ring_emit_hdp_flush */
3694 5 + /* gfx_v9_0_ring_emit_hdp_invalidate */
3695 7 + /* gfx_v9_0_ring_emit_pipeline_sync */
3696 64 + /* gfx_v9_0_ring_emit_vm_flush */
3697 8 + 8 + 8, /* gfx_v9_0_ring_emit_fence_kiq x3 for user fence, vm fence */
3698 .emit_ib_size = 4, /* gfx_v9_0_ring_emit_ib_compute */
3699 .emit_ib = gfx_v9_0_ring_emit_ib_compute,
3700 .emit_fence = gfx_v9_0_ring_emit_fence_kiq,
3701 .emit_hdp_flush = gfx_v9_0_ring_emit_hdp_flush,
3702 .emit_hdp_invalidate = gfx_v9_0_ring_emit_hdp_invalidate,
3703 .test_ring = gfx_v9_0_ring_test_ring,
3704 .test_ib = gfx_v9_0_ring_test_ib,
3705 .insert_nop = amdgpu_ring_insert_nop,
3706 .pad_ib = amdgpu_ring_generic_pad_ib,
3707 .emit_rreg = gfx_v9_0_ring_emit_rreg,
3708 .emit_wreg = gfx_v9_0_ring_emit_wreg,
3709};
b1023571
KW		 3710
3711static void gfx_v9_0_set_ring_funcs(struct amdgpu_device *adev)
3712{
3713 int i;
3714
aa6faa44
XY		 3715 adev->gfx.kiq.ring.funcs = &gfx_v9_0_ring_funcs_kiq;
3716
b1023571
KW		 3717 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
3718 adev->gfx.gfx_ring[i].funcs = &gfx_v9_0_ring_funcs_gfx;
3719
3720 for (i = 0; i < adev->gfx.num_compute_rings; i++)
3721 adev->gfx.compute_ring[i].funcs = &gfx_v9_0_ring_funcs_compute;
3722}
3723
97031e25
XY		 3724static const struct amdgpu_irq_src_funcs gfx_v9_0_kiq_irq_funcs = {
3725 .set = gfx_v9_0_kiq_set_interrupt_state,
3726 .process = gfx_v9_0_kiq_irq,
3727};
3728
b1023571
KW		 3729static const struct amdgpu_irq_src_funcs gfx_v9_0_eop_irq_funcs = {
3730 .set = gfx_v9_0_set_eop_interrupt_state,
3731 .process = gfx_v9_0_eop_irq,
3732};
3733
3734static const struct amdgpu_irq_src_funcs gfx_v9_0_priv_reg_irq_funcs = {
3735 .set = gfx_v9_0_set_priv_reg_fault_state,
3736 .process = gfx_v9_0_priv_reg_irq,
3737};
3738
3739static const struct amdgpu_irq_src_funcs gfx_v9_0_priv_inst_irq_funcs = {
3740 .set = gfx_v9_0_set_priv_inst_fault_state,
3741 .process = gfx_v9_0_priv_inst_irq,
3742};
3743
3744static void gfx_v9_0_set_irq_funcs(struct amdgpu_device *adev)
3745{
3746 adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST;
3747 adev->gfx.eop_irq.funcs = &gfx_v9_0_eop_irq_funcs;
3748
3749 adev->gfx.priv_reg_irq.num_types = 1;
3750 adev->gfx.priv_reg_irq.funcs = &gfx_v9_0_priv_reg_irq_funcs;
3751
3752 adev->gfx.priv_inst_irq.num_types = 1;
3753 adev->gfx.priv_inst_irq.funcs = &gfx_v9_0_priv_inst_irq_funcs;
97031e25
XY		 3754
3755 adev->gfx.kiq.irq.num_types = AMDGPU_CP_KIQ_IRQ_LAST;
3756 adev->gfx.kiq.irq.funcs = &gfx_v9_0_kiq_irq_funcs;
b1023571
KW		 3757}
3758
3759static void gfx_v9_0_set_rlc_funcs(struct amdgpu_device *adev)
3760{
3761 switch (adev->asic_type) {
3762 case CHIP_VEGA10:
3763 adev->gfx.rlc.funcs = &gfx_v9_0_rlc_funcs;
3764 break;
3765 default:
3766 break;
3767 }
3768}
3769
3770static void gfx_v9_0_set_gds_init(struct amdgpu_device *adev)
3771{
3772 /* init asci gds info */
3773 adev->gds.mem.total_size = RREG32(SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_SIZE));
3774 adev->gds.gws.total_size = 64;
3775 adev->gds.oa.total_size = 16;
3776
3777 if (adev->gds.mem.total_size == 64 * 1024) {
3778 adev->gds.mem.gfx_partition_size = 4096;
3779 adev->gds.mem.cs_partition_size = 4096;
3780
3781 adev->gds.gws.gfx_partition_size = 4;
3782 adev->gds.gws.cs_partition_size = 4;
3783
3784 adev->gds.oa.gfx_partition_size = 4;
3785 adev->gds.oa.cs_partition_size = 1;
3786 } else {
3787 adev->gds.mem.gfx_partition_size = 1024;
3788 adev->gds.mem.cs_partition_size = 1024;
3789
3790 adev->gds.gws.gfx_partition_size = 16;
3791 adev->gds.gws.cs_partition_size = 16;
3792
3793 adev->gds.oa.gfx_partition_size = 4;
3794 adev->gds.oa.cs_partition_size = 4;
3795 }
3796}
3797
3798static u32 gfx_v9_0_get_cu_active_bitmap(struct amdgpu_device *adev)
3799{
3800 u32 data, mask;
3801
3802 data = RREG32(SOC15_REG_OFFSET(GC, 0, mmCC_GC_SHADER_ARRAY_CONFIG));
3803 data |= RREG32(SOC15_REG_OFFSET(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG));
3804
3805 data &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK;
3806 data >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT;
3807
3808 mask = gfx_v9_0_create_bitmask(adev->gfx.config.max_cu_per_sh);
3809
3810 return (~data) & mask;
3811}
3812
3813static int gfx_v9_0_get_cu_info(struct amdgpu_device *adev,
3814 struct amdgpu_cu_info *cu_info)
3815{
3816 int i, j, k, counter, active_cu_number = 0;
3817 u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0;
3818
3819 if (!adev || !cu_info)
3820 return -EINVAL;
3821
3822 memset(cu_info, 0, sizeof(*cu_info));
3823
3824 mutex_lock(&adev->grbm_idx_mutex);
3825 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
3826 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
3827 mask = 1;
3828 ao_bitmap = 0;
3829 counter = 0;
3830 gfx_v9_0_select_se_sh(adev, i, j, 0xffffffff);
3831 bitmap = gfx_v9_0_get_cu_active_bitmap(adev);
3832 cu_info->bitmap[i][j] = bitmap;
3833
3834 for (k = 0; k < 16; k ++) {
3835 if (bitmap & mask) {
3836 if (counter < 2)
3837 ao_bitmap |= mask;
3838 counter ++;
3839 }
3840 mask <<= 1;
3841 }
3842 active_cu_number += counter;
3843 ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8));
3844 }
3845 }
3846 gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
3847 mutex_unlock(&adev->grbm_idx_mutex);
3848
3849 cu_info->number = active_cu_number;
3850 cu_info->ao_cu_mask = ao_cu_mask;
3851
3852 return 0;
3853}
3854
3855static int gfx_v9_0_init_queue(struct amdgpu_ring *ring)
3856{
3857 int r, j;
3858 u32 tmp;
3859 bool use_doorbell = true;
3860 u64 hqd_gpu_addr;
3861 u64 mqd_gpu_addr;
3862 u64 eop_gpu_addr;
3863 u64 wb_gpu_addr;
3864 u32 *buf;
3865 struct v9_mqd *mqd;
3866 struct amdgpu_device *adev;
3867
3868 adev = ring->adev;
3869 if (ring->mqd_obj == NULL) {
3870 r = amdgpu_bo_create(adev,
3871 sizeof(struct v9_mqd),
3872 PAGE_SIZE,true,
3873 AMDGPU_GEM_DOMAIN_GTT, 0, NULL,
3874 NULL, &ring->mqd_obj);
3875 if (r) {
3876 dev_warn(adev->dev, "(%d) create MQD bo failed\n", r);
3877 return r;
3878 }
3879 }
3880
3881 r = amdgpu_bo_reserve(ring->mqd_obj, false);
3882 if (unlikely(r != 0)) {
3883 gfx_v9_0_cp_compute_fini(adev);
3884 return r;
3885 }
3886
3887 r = amdgpu_bo_pin(ring->mqd_obj, AMDGPU_GEM_DOMAIN_GTT,
3888 &mqd_gpu_addr);
3889 if (r) {
3890 dev_warn(adev->dev, "(%d) pin MQD bo failed\n", r);
3891 gfx_v9_0_cp_compute_fini(adev);
3892 return r;
3893 }
3894 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&buf);
3895 if (r) {
3896 dev_warn(adev->dev, "(%d) map MQD bo failed\n", r);
3897 gfx_v9_0_cp_compute_fini(adev);
3898 return r;
3899 }
3900
3901 /* init the mqd struct */
3902 memset(buf, 0, sizeof(struct v9_mqd));
3903
3904 mqd = (struct v9_mqd *)buf;
3905 mqd->header = 0xC0310800;
3906 mqd->compute_pipelinestat_enable = 0x00000001;
3907 mqd->compute_static_thread_mgmt_se0 = 0xffffffff;
3908 mqd->compute_static_thread_mgmt_se1 = 0xffffffff;
3909 mqd->compute_static_thread_mgmt_se2 = 0xffffffff;
3910 mqd->compute_static_thread_mgmt_se3 = 0xffffffff;
3911 mqd->compute_misc_reserved = 0x00000003;
3912 mutex_lock(&adev->srbm_mutex);
3913 soc15_grbm_select(adev, ring->me,
3914 ring->pipe,
3915 ring->queue, 0);
3916 /* disable wptr polling */
3917 tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_PQ_WPTR_POLL_CNTL));
3918 tmp = REG_SET_FIELD(tmp, CP_PQ_WPTR_POLL_CNTL, EN, 0);
3919 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_PQ_WPTR_POLL_CNTL), tmp);
3920
3921 /* write the EOP addr */
3922 BUG_ON(ring->me != 1 || ring->pipe != 0); /* can't handle other cases eop address */
3923 eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr + (ring->queue * MEC_HPD_SIZE);
3924 eop_gpu_addr >>= 8;
3925
3926 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_EOP_BASE_ADDR), lower_32_bits(eop_gpu_addr));
3927 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_EOP_BASE_ADDR_HI), upper_32_bits(eop_gpu_addr));
3928 mqd->cp_hqd_eop_base_addr_lo = lower_32_bits(eop_gpu_addr);
3929 mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_gpu_addr);
3930
3931 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
3932 tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_EOP_CONTROL));
3933 tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE,
3934 (order_base_2(MEC_HPD_SIZE / 4) - 1));
3935 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_EOP_CONTROL), tmp);
3936
3937 /* enable doorbell? */
3938 tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL));
3939 if (use_doorbell)
3940 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, DOORBELL_EN, 1);
3941 else
3942 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, DOORBELL_EN, 0);
3943
3944 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL), tmp);
3945 mqd->cp_hqd_pq_doorbell_control = tmp;
3946
3947 /* disable the queue if it's active */
3948 ring->wptr = 0;
3949 mqd->cp_hqd_dequeue_request = 0;
3950 mqd->cp_hqd_pq_rptr = 0;
3951 mqd->cp_hqd_pq_wptr_lo = 0;
3952 mqd->cp_hqd_pq_wptr_hi = 0;
3953 if (RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_ACTIVE)) & 1) {
3954 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_DEQUEUE_REQUEST), 1);
3955 for (j = 0; j < adev->usec_timeout; j++) {
3956 if (!(RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_ACTIVE)) & 1))
3957 break;
3958 udelay(1);
3959 }
3960 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_DEQUEUE_REQUEST), mqd->cp_hqd_dequeue_request);
3961 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_RPTR), mqd->cp_hqd_pq_rptr);
3962 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_LO), mqd->cp_hqd_pq_wptr_lo);
3963 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_HI), mqd->cp_hqd_pq_wptr_hi);
3964 }
3965
3966 /* set the pointer to the MQD */
3967 mqd->cp_mqd_base_addr_lo = mqd_gpu_addr & 0xfffffffc;
3968 mqd->cp_mqd_base_addr_hi = upper_32_bits(mqd_gpu_addr);
3969 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_MQD_BASE_ADDR), mqd->cp_mqd_base_addr_lo);
3970 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_MQD_BASE_ADDR_HI), mqd->cp_mqd_base_addr_hi);
3971
3972 /* set MQD vmid to 0 */
3973 tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_MQD_CONTROL));
3974 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0);
3975 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_MQD_CONTROL), tmp);
3976 mqd->cp_mqd_control = tmp;
3977
3978 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
3979 hqd_gpu_addr = ring->gpu_addr >> 8;
3980 mqd->cp_hqd_pq_base_lo = hqd_gpu_addr;
3981 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr);
3982 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_BASE), mqd->cp_hqd_pq_base_lo);
3983 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_BASE_HI), mqd->cp_hqd_pq_base_hi);
3984
3985 /* set up the HQD, this is similar to CP_RB0_CNTL */
3986 tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_CONTROL));
3987 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE,
3988 (order_base_2(ring->ring_size / 4) - 1));
3989 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE,
3990 ((order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1) << 8));
3991#ifdef __BIG_ENDIAN
3992 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1);
3993#endif
3994 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0);
3995 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ROQ_PQ_IB_FLIP, 0);
3996 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1);
3997 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1);
3998 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_CONTROL), tmp);
3999 mqd->cp_hqd_pq_control = tmp;
4000
4001 /* set the wb address wether it's enabled or not */
4002 wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
4003 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc;
4004 mqd->cp_hqd_pq_rptr_report_addr_hi =
4005 upper_32_bits(wb_gpu_addr) & 0xffff;
4006 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR),
4007 mqd->cp_hqd_pq_rptr_report_addr_lo);
4008 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI),
4009 mqd->cp_hqd_pq_rptr_report_addr_hi);
4010
4011 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
4012 wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
4013 mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc;
4014 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;
4015 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR),
4016 mqd->cp_hqd_pq_wptr_poll_addr_lo);
4017 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI),
4018 mqd->cp_hqd_pq_wptr_poll_addr_hi);
4019
4020 /* enable the doorbell if requested */
4021 if (use_doorbell) {
4022 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_MEC_DOORBELL_RANGE_LOWER),
4023 (AMDGPU_DOORBELL64_KIQ * 2) << 2);
4024 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_MEC_DOORBELL_RANGE_UPPER),
4025 (AMDGPU_DOORBELL64_MEC_RING7 * 2) << 2);
4026 tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL));
4027 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
4028 DOORBELL_OFFSET, ring->doorbell_index);
4029 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, DOORBELL_EN, 1);
4030 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, DOORBELL_SOURCE, 0);
4031 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, DOORBELL_HIT, 0);
4032 mqd->cp_hqd_pq_doorbell_control = tmp;
4033
4034 } else {
4035 mqd->cp_hqd_pq_doorbell_control = 0;
4036 }
4037 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL),
4038 mqd->cp_hqd_pq_doorbell_control);
4039
4040 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
4041 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_LO), mqd->cp_hqd_pq_wptr_lo);
4042 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_HI), mqd->cp_hqd_pq_wptr_hi);
4043
4044 /* set the vmid for the queue */
4045 mqd->cp_hqd_vmid = 0;
4046 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_VMID), mqd->cp_hqd_vmid);
4047
4048 tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PERSISTENT_STATE));
4049 tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x53);
4050 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PERSISTENT_STATE), tmp);
4051 mqd->cp_hqd_persistent_state = tmp;
4052
4053 /* activate the queue */
4054 mqd->cp_hqd_active = 1;
4055 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_ACTIVE), mqd->cp_hqd_active);
4056
4057 soc15_grbm_select(adev, 0, 0, 0, 0);
4058 mutex_unlock(&adev->srbm_mutex);
4059
4060 amdgpu_bo_kunmap(ring->mqd_obj);
4061 amdgpu_bo_unreserve(ring->mqd_obj);
4062
4063 if (use_doorbell) {
4064 tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_PQ_STATUS));
4065 tmp = REG_SET_FIELD(tmp, CP_PQ_STATUS, DOORBELL_ENABLE, 1);
4066 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_PQ_STATUS), tmp);
4067 }
4068
4069 return 0;
4070}
4071
4072const struct amdgpu_ip_block_version gfx_v9_0_ip_block =
4073{
4074 .type = AMD_IP_BLOCK_TYPE_GFX,
4075 .major = 9,
4076 .minor = 0,
4077 .rev = 0,
4078 .funcs = &gfx_v9_0_ip_funcs,
4079};
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