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drm/amdgpu: add support for athub v2.1
[mirror_ubuntu-jammy-kernel.git] / drivers / gpu / drm / amd / amdgpu / gmc_v10_0.c
CommitLineData
f9df67e9
HZ		 1/*
2 * Copyright 2019 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23#include <linux/firmware.h>
d7929c1e 24#include <linux/pci.h>
f9df67e9
HZ		 25#include "amdgpu.h"
26#include "amdgpu_atomfirmware.h"
27#include "gmc_v10_0.h"
28
29#include "hdp/hdp_5_0_0_offset.h"
30#include "hdp/hdp_5_0_0_sh_mask.h"
31#include "gc/gc_10_1_0_sh_mask.h"
32#include "mmhub/mmhub_2_0_0_sh_mask.h"
ea930000
AS		 33#include "athub/athub_2_0_0_sh_mask.h"
34#include "athub/athub_2_0_0_offset.h"
f9df67e9
HZ		 35#include "dcn/dcn_2_0_0_offset.h"
36#include "dcn/dcn_2_0_0_sh_mask.h"
37#include "oss/osssys_5_0_0_offset.h"
38#include "ivsrcid/vmc/irqsrcs_vmc_1_0.h"
39#include "navi10_enum.h"
40
41#include "soc15.h"
ea930000 42#include "soc15d.h"
f9df67e9
HZ		 43#include "soc15_common.h"
44
45#include "nbio_v2_3.h"
46
47#include "gfxhub_v2_0.h"
0b3df16b 48#include "gfxhub_v2_1.h"
f9df67e9
HZ		 49#include "mmhub_v2_0.h"
50#include "athub_v2_0.h"
51/* XXX Move this macro to navi10 header file, which is like vid.h for VI.*/
52#define AMDGPU_NUM_OF_VMIDS 8
53
54#if 0
55static const struct soc15_reg_golden golden_settings_navi10_hdp[] =
56{
57 /* TODO add golden setting for hdp */
58};
59#endif
60
61static int
62gmc_v10_0_vm_fault_interrupt_state(struct amdgpu_device *adev,
63 struct amdgpu_irq_src *src, unsigned type,
64 enum amdgpu_interrupt_state state)
65{
66 struct amdgpu_vmhub *hub;
67 u32 tmp, reg, bits[AMDGPU_MAX_VMHUBS], i;
68
a2d15ed7 69 bits[AMDGPU_GFXHUB_0] = GCVM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
f9df67e9
HZ		 70 GCVM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
71 GCVM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
72 GCVM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
73 GCVM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
74 GCVM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
75 GCVM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK;
76
a2d15ed7 77 bits[AMDGPU_MMHUB_0] = MMVM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
f9df67e9
HZ		 78 MMVM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
79 MMVM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
80 MMVM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
81 MMVM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
82 MMVM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
83 MMVM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK;
84
85 switch (state) {
86 case AMDGPU_IRQ_STATE_DISABLE:
87 /* MM HUB */
a2d15ed7 88 hub = &adev->vmhub[AMDGPU_MMHUB_0];
f9df67e9
HZ		 89 for (i = 0; i < 16; i++) {
90 reg = hub->vm_context0_cntl + i;
91 tmp = RREG32(reg);
a2d15ed7 92 tmp &= ~bits[AMDGPU_MMHUB_0];
f9df67e9
HZ		 93 WREG32(reg, tmp);
94 }
95
96 /* GFX HUB */
a2d15ed7 97 hub = &adev->vmhub[AMDGPU_GFXHUB_0];
f9df67e9
HZ		 98 for (i = 0; i < 16; i++) {
99 reg = hub->vm_context0_cntl + i;
100 tmp = RREG32(reg);
a2d15ed7 101 tmp &= ~bits[AMDGPU_GFXHUB_0];
f9df67e9
HZ		 102 WREG32(reg, tmp);
103 }
104 break;
105 case AMDGPU_IRQ_STATE_ENABLE:
106 /* MM HUB */
a2d15ed7 107 hub = &adev->vmhub[AMDGPU_MMHUB_0];
f9df67e9
HZ		 108 for (i = 0; i < 16; i++) {
109 reg = hub->vm_context0_cntl + i;
110 tmp = RREG32(reg);
a2d15ed7 111 tmp |= bits[AMDGPU_MMHUB_0];
f9df67e9
HZ		 112 WREG32(reg, tmp);
113 }
114
115 /* GFX HUB */
a2d15ed7 116 hub = &adev->vmhub[AMDGPU_GFXHUB_0];
f9df67e9
HZ		 117 for (i = 0; i < 16; i++) {
118 reg = hub->vm_context0_cntl + i;
119 tmp = RREG32(reg);
a2d15ed7 120 tmp |= bits[AMDGPU_GFXHUB_0];
f9df67e9
HZ		 121 WREG32(reg, tmp);
122 }
123 break;
124 default:
125 break;
126 }
127
128 return 0;
129}
130
131static int gmc_v10_0_process_interrupt(struct amdgpu_device *adev,
132 struct amdgpu_irq_src *source,
133 struct amdgpu_iv_entry *entry)
134{
135 struct amdgpu_vmhub *hub = &adev->vmhub[entry->vmid_src];
136 uint32_t status = 0;
137 u64 addr;
138
139 addr = (u64)entry->src_data[0] << 12;
140 addr |= ((u64)entry->src_data[1] & 0xf) << 44;
141
142 if (!amdgpu_sriov_vf(adev)) {
53499173
XY		 143 /*
144 * Issue a dummy read to wait for the status register to
145 * be updated to avoid reading an incorrect value due to
146 * the new fast GRBM interface.
147 */
148 if (entry->vmid_src == AMDGPU_GFXHUB_0)
149 RREG32(hub->vm_l2_pro_fault_status);
150
f9df67e9
HZ		 151 status = RREG32(hub->vm_l2_pro_fault_status);
152 WREG32_P(hub->vm_l2_pro_fault_cntl, 1, ~1);
153 }
154
155 if (printk_ratelimit()) {
5d36d4c9
YZ		 156 struct amdgpu_task_info task_info;
157
158 memset(&task_info, 0, sizeof(struct amdgpu_task_info));
159 amdgpu_vm_get_task_info(adev, entry->pasid, &task_info);
160
f9df67e9 161 dev_err(adev->dev,
5d36d4c9
YZ		 162 "[%s] page fault (src_id:%u ring:%u vmid:%u pasid:%u, "
163 "for process %s pid %d thread %s pid %d)\n",
f9df67e9
HZ		 164 entry->vmid_src ? "mmhub" : "gfxhub",
165 entry->src_id, entry->ring_id, entry->vmid,
5d36d4c9
YZ		 166 entry->pasid, task_info.process_name, task_info.tgid,
167 task_info.task_name, task_info.pid);
168 dev_err(adev->dev, " in page starting at address 0x%016llx from client %d\n",
f9df67e9 169 addr, entry->client_id);
5d36d4c9 170 if (!amdgpu_sriov_vf(adev)) {
f9df67e9 171 dev_err(adev->dev,
5d36d4c9 172 "GCVM_L2_PROTECTION_FAULT_STATUS:0x%08X\n",
f9df67e9 173 status);
d2155a71
OZ		 174 dev_err(adev->dev, "\t Faulty UTCL2 client ID: 0x%lx\n",
175 REG_GET_FIELD(status,
176 GCVM_L2_PROTECTION_FAULT_STATUS, CID));
5d36d4c9
YZ		 177 dev_err(adev->dev, "\t MORE_FAULTS: 0x%lx\n",
178 REG_GET_FIELD(status,
179 GCVM_L2_PROTECTION_FAULT_STATUS, MORE_FAULTS));
180 dev_err(adev->dev, "\t WALKER_ERROR: 0x%lx\n",
181 REG_GET_FIELD(status,
182 GCVM_L2_PROTECTION_FAULT_STATUS, WALKER_ERROR));
183 dev_err(adev->dev, "\t PERMISSION_FAULTS: 0x%lx\n",
184 REG_GET_FIELD(status,
185 GCVM_L2_PROTECTION_FAULT_STATUS, PERMISSION_FAULTS));
186 dev_err(adev->dev, "\t MAPPING_ERROR: 0x%lx\n",
187 REG_GET_FIELD(status,
188 GCVM_L2_PROTECTION_FAULT_STATUS, MAPPING_ERROR));
189 dev_err(adev->dev, "\t RW: 0x%lx\n",
190 REG_GET_FIELD(status,
191 GCVM_L2_PROTECTION_FAULT_STATUS, RW));
192 }
f9df67e9
HZ		 193 }
194
195 return 0;
196}
197
198static const struct amdgpu_irq_src_funcs gmc_v10_0_irq_funcs = {
199 .set = gmc_v10_0_vm_fault_interrupt_state,
200 .process = gmc_v10_0_process_interrupt,
201};
202
203static void gmc_v10_0_set_irq_funcs(struct amdgpu_device *adev)
204{
205 adev->gmc.vm_fault.num_types = 1;
206 adev->gmc.vm_fault.funcs = &gmc_v10_0_irq_funcs;
207}
208
209static uint32_t gmc_v10_0_get_invalidate_req(unsigned int vmid,
210 uint32_t flush_type)
211{
212 u32 req = 0;
213
214 /* invalidate using legacy mode on vmid*/
215 req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ,
216 PER_VMID_INVALIDATE_REQ, 1 << vmid);
217 req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, FLUSH_TYPE, flush_type);
218 req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PTES, 1);
219 req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE0, 1);
220 req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE1, 1);
221 req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE2, 1);
222 req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L1_PTES, 1);
223 req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ,
224 CLEAR_PROTECTION_FAULT_STATUS_ADDR, 0);
225
226 return req;
227}
228
f271fe18 229/**
230 * gmc_v10_0_use_invalidate_semaphore - judge whether to use semaphore
231 *
232 * @adev: amdgpu_device pointer
233 * @vmhub: vmhub type
234 *
235 */
236static bool gmc_v10_0_use_invalidate_semaphore(struct amdgpu_device *adev,
237 uint32_t vmhub)
238{
239 return ((vmhub == AMDGPU_MMHUB_0 ||
240 vmhub == AMDGPU_MMHUB_1) &&
241 (!amdgpu_sriov_vf(adev)));
242}
243
ea930000
AS		 244static bool gmc_v10_0_get_atc_vmid_pasid_mapping_info(
245 struct amdgpu_device *adev,
246 uint8_t vmid, uint16_t *p_pasid)
247{
248 uint32_t value;
249
250 value = RREG32(SOC15_REG_OFFSET(ATHUB, 0, mmATC_VMID0_PASID_MAPPING)
251 + vmid);
252 *p_pasid = value & ATC_VMID0_PASID_MAPPING__PASID_MASK;
253
254 return !!(value & ATC_VMID0_PASID_MAPPING__VALID_MASK);
255}
256
f9df67e9
HZ		 257/*
258 * GART
259 * VMID 0 is the physical GPU addresses as used by the kernel.
260 * VMIDs 1-15 are used for userspace clients and are handled
261 * by the amdgpu vm/hsa code.
262 */
263
264static void gmc_v10_0_flush_vm_hub(struct amdgpu_device *adev, uint32_t vmid,
265 unsigned int vmhub, uint32_t flush_type)
266{
f271fe18 267 bool use_semaphore = gmc_v10_0_use_invalidate_semaphore(adev, vmhub);
f9df67e9 268 struct amdgpu_vmhub *hub = &adev->vmhub[vmhub];
37c58ddf
FK		 269 u32 inv_req = gmc_v10_0_get_invalidate_req(vmid, flush_type);
270 u32 tmp;
f9df67e9
HZ		 271 /* Use register 17 for GART */
272 const unsigned eng = 17;
273 unsigned int i;
274
f920d1bb 275 spin_lock(&adev->gmc.invalidate_lock);
276 /*
277 * It may lose gpuvm invalidate acknowldege state across power-gating
278 * off cycle, add semaphore acquire before invalidation and semaphore
279 * release after invalidation to avoid entering power gated state
280 * to WA the Issue
281 */
282
283 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */
f271fe18 284 if (use_semaphore) {
f920d1bb 285 for (i = 0; i < adev->usec_timeout; i++) {
286 /* a read return value of 1 means semaphore acuqire */
287 tmp = RREG32_NO_KIQ(hub->vm_inv_eng0_sem + eng);
288 if (tmp & 0x1)
289 break;
290 udelay(1);
291 }
292
293 if (i >= adev->usec_timeout)
294 DRM_ERROR("Timeout waiting for sem acquire in VM flush!\n");
295 }
296
37c58ddf 297 WREG32_NO_KIQ(hub->vm_inv_eng0_req + eng, inv_req);
f9df67e9 298
53499173
XY		 299 /*
300 * Issue a dummy read to wait for the ACK register to be cleared
301 * to avoid a false ACK due to the new fast GRBM interface.
302 */
303 if (vmhub == AMDGPU_GFXHUB_0)
304 RREG32_NO_KIQ(hub->vm_inv_eng0_req + eng);
305
f9df67e9
HZ		 306 /* Wait for ACK with a delay.*/
307 for (i = 0; i < adev->usec_timeout; i++) {
308 tmp = RREG32_NO_KIQ(hub->vm_inv_eng0_ack + eng);
309 tmp &= 1 << vmid;
310 if (tmp)
311 break;
312
313 udelay(1);
314 }
315
f920d1bb 316 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */
f271fe18 317 if (use_semaphore)
f920d1bb 318 /*
319 * add semaphore release after invalidation,
320 * write with 0 means semaphore release
321 */
322 WREG32_NO_KIQ(hub->vm_inv_eng0_sem + eng, 0);
323
324 spin_unlock(&adev->gmc.invalidate_lock);
325
f9df67e9
HZ		 326 if (i < adev->usec_timeout)
327 return;
328
329 DRM_ERROR("Timeout waiting for VM flush ACK!\n");
330}
331
332/**
333 * gmc_v10_0_flush_gpu_tlb - gart tlb flush callback
334 *
335 * @adev: amdgpu_device pointer
336 * @vmid: vm instance to flush
337 *
338 * Flush the TLB for the requested page table.
339 */
3ff98548
OZ		 340static void gmc_v10_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid,
341 uint32_t vmhub, uint32_t flush_type)
f9df67e9
HZ		 342{
343 struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring;
344 struct dma_fence *fence;
345 struct amdgpu_job *job;
346
347 int r;
348
349 /* flush hdp cache */
bebc0762 350 adev->nbio.funcs->hdp_flush(adev, NULL);
f9df67e9
HZ		 351
352 mutex_lock(&adev->mman.gtt_window_lock);
353
3ff98548
OZ		 354 if (vmhub == AMDGPU_MMHUB_0) {
355 gmc_v10_0_flush_vm_hub(adev, vmid, AMDGPU_MMHUB_0, 0);
356 mutex_unlock(&adev->mman.gtt_window_lock);
357 return;
358 }
359
360 BUG_ON(vmhub != AMDGPU_GFXHUB_0);
361
767acabd
KW		 362 if (!adev->mman.buffer_funcs_enabled ||
363 !adev->ib_pool_ready ||
e2195f7d
ML		 364 adev->in_gpu_reset ||
365 ring->sched.ready == false) {
a2d15ed7 366 gmc_v10_0_flush_vm_hub(adev, vmid, AMDGPU_GFXHUB_0, 0);
f9df67e9
HZ		 367 mutex_unlock(&adev->mman.gtt_window_lock);
368 return;
369 }
370
371 /* The SDMA on Navi has a bug which can theoretically result in memory
372 * corruption if an invalidation happens at the same time as an VA
373 * translation. Avoid this by doing the invalidation from the SDMA
374 * itself.
375 */
9ecefb19
CK		 376 r = amdgpu_job_alloc_with_ib(adev, 16 * 4, AMDGPU_IB_POOL_IMMEDIATE,
377 &job);
f9df67e9
HZ		 378 if (r)
379 goto error_alloc;
380
381 job->vm_pd_addr = amdgpu_gmc_pd_addr(adev->gart.bo);
382 job->vm_needs_flush = true;
3f378758 383 job->ibs->ptr[job->ibs->length_dw++] = ring->funcs->nop;
f9df67e9
HZ		 384 amdgpu_ring_pad_ib(ring, &job->ibs[0]);
385 r = amdgpu_job_submit(job, &adev->mman.entity,
386 AMDGPU_FENCE_OWNER_UNDEFINED, &fence);
387 if (r)
388 goto error_submit;
389
390 mutex_unlock(&adev->mman.gtt_window_lock);
391
392 dma_fence_wait(fence, false);
393 dma_fence_put(fence);
394
395 return;
396
397error_submit:
398 amdgpu_job_free(job);
399
400error_alloc:
401 mutex_unlock(&adev->mman.gtt_window_lock);
402 DRM_ERROR("Error flushing GPU TLB using the SDMA (%d)!\n", r);
403}
404
ea930000
AS		 405/**
406 * gmc_v10_0_flush_gpu_tlb_pasid - tlb flush via pasid
407 *
408 * @adev: amdgpu_device pointer
409 * @pasid: pasid to be flush
410 *
411 * Flush the TLB for the requested pasid.
412 */
413static int gmc_v10_0_flush_gpu_tlb_pasid(struct amdgpu_device *adev,
414 uint16_t pasid, uint32_t flush_type,
415 bool all_hub)
416{
417 int vmid, i;
418 signed long r;
419 uint32_t seq;
420 uint16_t queried_pasid;
421 bool ret;
422 struct amdgpu_ring *ring = &adev->gfx.kiq.ring;
423 struct amdgpu_kiq *kiq = &adev->gfx.kiq;
424
425 if (amdgpu_emu_mode == 0 && ring->sched.ready) {
426 spin_lock(&adev->gfx.kiq.ring_lock);
36a1707a
AS		 427 /* 2 dwords flush + 8 dwords fence */
428 amdgpu_ring_alloc(ring, kiq->pmf->invalidate_tlbs_size + 8);
ea930000
AS		 429 kiq->pmf->kiq_invalidate_tlbs(ring,
430 pasid, flush_type, all_hub);
04e4e2e9
YT		 431 r = amdgpu_fence_emit_polling(ring, &seq, MAX_KIQ_REG_WAIT);
432 if (r) {
433 amdgpu_ring_undo(ring);
abb17b1e 434 spin_unlock(&adev->gfx.kiq.ring_lock);
04e4e2e9
YT		 435 return -ETIME;
436 }
437
ea930000
AS		 438 amdgpu_ring_commit(ring);
439 spin_unlock(&adev->gfx.kiq.ring_lock);
440 r = amdgpu_fence_wait_polling(ring, seq, adev->usec_timeout);
441 if (r < 1) {
442 DRM_ERROR("wait for kiq fence error: %ld.\n", r);
443 return -ETIME;
444 }
445
446 return 0;
447 }
448
449 for (vmid = 1; vmid < 16; vmid++) {
450
451 ret = gmc_v10_0_get_atc_vmid_pasid_mapping_info(adev, vmid,
452 &queried_pasid);
453 if (ret && queried_pasid == pasid) {
454 if (all_hub) {
455 for (i = 0; i < adev->num_vmhubs; i++)
456 gmc_v10_0_flush_gpu_tlb(adev, vmid,
fa34edbe 457 i, flush_type);
ea930000
AS		 458 } else {
459 gmc_v10_0_flush_gpu_tlb(adev, vmid,
fa34edbe 460 AMDGPU_GFXHUB_0, flush_type);
ea930000
AS		 461 }
462 break;
463 }
464 }
465
466 return 0;
467}
468
f9df67e9
HZ		 469static uint64_t gmc_v10_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring,
470 unsigned vmid, uint64_t pd_addr)
471{
f271fe18 472 bool use_semaphore = gmc_v10_0_use_invalidate_semaphore(ring->adev, ring->funcs->vmhub);
f9df67e9
HZ		 473 struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub];
474 uint32_t req = gmc_v10_0_get_invalidate_req(vmid, 0);
475 unsigned eng = ring->vm_inv_eng;
476
f920d1bb 477 /*
478 * It may lose gpuvm invalidate acknowldege state across power-gating
479 * off cycle, add semaphore acquire before invalidation and semaphore
480 * release after invalidation to avoid entering power gated state
481 * to WA the Issue
482 */
483
484 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */
f271fe18 485 if (use_semaphore)
f920d1bb 486 /* a read return value of 1 means semaphore acuqire */
487 amdgpu_ring_emit_reg_wait(ring,
488 hub->vm_inv_eng0_sem + eng, 0x1, 0x1);
489
f9df67e9
HZ		 490 amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_lo32 + (2 * vmid),
491 lower_32_bits(pd_addr));
492
493 amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_hi32 + (2 * vmid),
494 upper_32_bits(pd_addr));
495
589b64a7 496 amdgpu_ring_emit_reg_write_reg_wait(ring, hub->vm_inv_eng0_req + eng,
497 hub->vm_inv_eng0_ack + eng,
498 req, 1 << vmid);
f9df67e9 499
f920d1bb 500 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */
f271fe18 501 if (use_semaphore)
f920d1bb 502 /*
503 * add semaphore release after invalidation,
504 * write with 0 means semaphore release
505 */
506 amdgpu_ring_emit_wreg(ring, hub->vm_inv_eng0_sem + eng, 0);
507
f9df67e9
HZ		 508 return pd_addr;
509}
510
511static void gmc_v10_0_emit_pasid_mapping(struct amdgpu_ring *ring, unsigned vmid,
512 unsigned pasid)
513{
514 struct amdgpu_device *adev = ring->adev;
515 uint32_t reg;
516
a2d15ed7 517 if (ring->funcs->vmhub == AMDGPU_GFXHUB_0)
f9df67e9
HZ		 518 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT) + vmid;
519 else
520 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT_MM) + vmid;
521
522 amdgpu_ring_emit_wreg(ring, reg, pasid);
523}
524
525/*
526 * PTE format on NAVI 10:
527 * 63:59 reserved
528 * 58:57 reserved
529 * 56 F
530 * 55 L
531 * 54 reserved
532 * 53:52 SW
533 * 51 T
534 * 50:48 mtype
535 * 47:12 4k physical page base address
536 * 11:7 fragment
537 * 6 write
538 * 5 read
539 * 4 exe
540 * 3 Z
541 * 2 snooped
542 * 1 system
543 * 0 valid
544 *
545 * PDE format on NAVI 10:
546 * 63:59 block fragment size
547 * 58:55 reserved
548 * 54 P
549 * 53:48 reserved
550 * 47:6 physical base address of PD or PTE
551 * 5:3 reserved
552 * 2 C
553 * 1 system
554 * 0 valid
555 */
f9df67e9 556
71776b6d
CK		 557static uint64_t gmc_v10_0_map_mtype(struct amdgpu_device *adev, uint32_t flags)
558{
559 switch (flags) {
f9df67e9 560 case AMDGPU_VM_MTYPE_DEFAULT:
71776b6d 561 return AMDGPU_PTE_MTYPE_NV10(MTYPE_NC);
f9df67e9 562 case AMDGPU_VM_MTYPE_NC:
71776b6d 563 return AMDGPU_PTE_MTYPE_NV10(MTYPE_NC);
f9df67e9 564 case AMDGPU_VM_MTYPE_WC:
71776b6d 565 return AMDGPU_PTE_MTYPE_NV10(MTYPE_WC);
f9df67e9 566 case AMDGPU_VM_MTYPE_CC:
71776b6d 567 return AMDGPU_PTE_MTYPE_NV10(MTYPE_CC);
f9df67e9 568 case AMDGPU_VM_MTYPE_UC:
71776b6d 569 return AMDGPU_PTE_MTYPE_NV10(MTYPE_UC);
f9df67e9 570 default:
71776b6d 571 return AMDGPU_PTE_MTYPE_NV10(MTYPE_NC);
f9df67e9 572 }
f9df67e9
HZ		 573}
574
575static void gmc_v10_0_get_vm_pde(struct amdgpu_device *adev, int level,
576 uint64_t *addr, uint64_t *flags)
577{
578 if (!(*flags & AMDGPU_PDE_PTE) && !(*flags & AMDGPU_PTE_SYSTEM))
579 *addr = adev->vm_manager.vram_base_offset + *addr -
580 adev->gmc.vram_start;
581 BUG_ON(*addr & 0xFFFF00000000003FULL);
582
583 if (!adev->gmc.translate_further)
584 return;
585
586 if (level == AMDGPU_VM_PDB1) {
587 /* Set the block fragment size */
588 if (!(*flags & AMDGPU_PDE_PTE))
589 *flags |= AMDGPU_PDE_BFS(0x9);
590
591 } else if (level == AMDGPU_VM_PDB0) {
592 if (*flags & AMDGPU_PDE_PTE)
593 *flags &= ~AMDGPU_PDE_PTE;
594 else
595 *flags |= AMDGPU_PTE_TF;
596 }
597}
598
cbfae36c
CK		 599static void gmc_v10_0_get_vm_pte(struct amdgpu_device *adev,
600 struct amdgpu_bo_va_mapping *mapping,
601 uint64_t *flags)
602{
603 *flags &= ~AMDGPU_PTE_EXECUTABLE;
604 *flags |= mapping->flags & AMDGPU_PTE_EXECUTABLE;
605
606 *flags &= ~AMDGPU_PTE_MTYPE_NV10_MASK;
607 *flags |= (mapping->flags & AMDGPU_PTE_MTYPE_NV10_MASK);
608
609 if (mapping->flags & AMDGPU_PTE_PRT) {
610 *flags |= AMDGPU_PTE_PRT;
611 *flags |= AMDGPU_PTE_SNOOPED;
612 *flags |= AMDGPU_PTE_LOG;
613 *flags |= AMDGPU_PTE_SYSTEM;
614 *flags &= ~AMDGPU_PTE_VALID;
615 }
616}
617
f9df67e9
HZ		 618static const struct amdgpu_gmc_funcs gmc_v10_0_gmc_funcs = {
619 .flush_gpu_tlb = gmc_v10_0_flush_gpu_tlb,
ea930000 620 .flush_gpu_tlb_pasid = gmc_v10_0_flush_gpu_tlb_pasid,
f9df67e9
HZ		 621 .emit_flush_gpu_tlb = gmc_v10_0_emit_flush_gpu_tlb,
622 .emit_pasid_mapping = gmc_v10_0_emit_pasid_mapping,
71776b6d 623 .map_mtype = gmc_v10_0_map_mtype,
cbfae36c
CK		 624 .get_vm_pde = gmc_v10_0_get_vm_pde,
625 .get_vm_pte = gmc_v10_0_get_vm_pte
f9df67e9
HZ		 626};
627
628static void gmc_v10_0_set_gmc_funcs(struct amdgpu_device *adev)
629{
630 if (adev->gmc.gmc_funcs == NULL)
631 adev->gmc.gmc_funcs = &gmc_v10_0_gmc_funcs;
632}
633
634static int gmc_v10_0_early_init(void *handle)
635{
636 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
637
638 gmc_v10_0_set_gmc_funcs(adev);
639 gmc_v10_0_set_irq_funcs(adev);
640
641 adev->gmc.shared_aperture_start = 0x2000000000000000ULL;
642 adev->gmc.shared_aperture_end =
643 adev->gmc.shared_aperture_start + (4ULL << 30) - 1;
644 adev->gmc.private_aperture_start = 0x1000000000000000ULL;
645 adev->gmc.private_aperture_end =
646 adev->gmc.private_aperture_start + (4ULL << 30) - 1;
647
648 return 0;
649}
650
651static int gmc_v10_0_late_init(void *handle)
652{
653 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
5677c520 654 int r;
f9df67e9 655
7db1d560 656 amdgpu_bo_late_init(adev);
1499bcc7 657
5677c520
AD		 658 r = amdgpu_gmc_allocate_vm_inv_eng(adev);
659 if (r)
660 return r;
f9df67e9
HZ		 661
662 return amdgpu_irq_get(adev, &adev->gmc.vm_fault, 0);
663}
664
665static void gmc_v10_0_vram_gtt_location(struct amdgpu_device *adev,
666 struct amdgpu_gmc *mc)
667{
668 u64 base = 0;
669
0b3df16b
LG		 670 if (adev->asic_type == CHIP_SIENNA_CICHLID)
671 base = gfxhub_v2_1_get_fb_location(adev);
672 else
673 base = gfxhub_v2_0_get_fb_location(adev);
f9df67e9
HZ		 674
675 amdgpu_gmc_vram_location(adev, &adev->gmc, base);
676 amdgpu_gmc_gart_location(adev, mc);
677
678 /* base offset of vram pages */
0b3df16b
LG		 679 if (adev->asic_type == CHIP_SIENNA_CICHLID)
680 adev->vm_manager.vram_base_offset = gfxhub_v2_1_get_mc_fb_offset(adev);
681 else
682 adev->vm_manager.vram_base_offset = gfxhub_v2_0_get_mc_fb_offset(adev);
f9df67e9
HZ		 683}
684
685/**
686 * gmc_v10_0_mc_init - initialize the memory controller driver params
687 *
688 * @adev: amdgpu_device pointer
689 *
690 * Look up the amount of vram, vram width, and decide how to place
691 * vram and gart within the GPU's physical address space.
692 * Returns 0 for success.
693 */
694static int gmc_v10_0_mc_init(struct amdgpu_device *adev)
695{
78b7dfd9 696 int r;
f9df67e9
HZ		 697
698 /* size in MB on si */
699 adev->gmc.mc_vram_size =
bebc0762 700 adev->nbio.funcs->get_memsize(adev) * 1024ULL * 1024ULL;
f9df67e9 701 adev->gmc.real_vram_size = adev->gmc.mc_vram_size;
78b7dfd9
AS		 702
703 if (!(adev->flags & AMD_IS_APU)) {
704 r = amdgpu_device_resize_fb_bar(adev);
705 if (r)
706 return r;
707 }
708 adev->gmc.aper_base = pci_resource_start(adev->pdev, 0);
709 adev->gmc.aper_size = pci_resource_len(adev->pdev, 0);
f9df67e9
HZ		 710
711 /* In case the PCI BAR is larger than the actual amount of vram */
78b7dfd9 712 adev->gmc.visible_vram_size = adev->gmc.aper_size;
f9df67e9
HZ		 713 if (adev->gmc.visible_vram_size > adev->gmc.real_vram_size)
714 adev->gmc.visible_vram_size = adev->gmc.real_vram_size;
715
716 /* set the gart size */
717 if (amdgpu_gart_size == -1) {
718 switch (adev->asic_type) {
719 case CHIP_NAVI10:
05d72b8d 720 case CHIP_NAVI14:
4a0e815f 721 case CHIP_NAVI12:
57d70602 722 case CHIP_SIENNA_CICHLID:
f9df67e9
HZ		 723 default:
724 adev->gmc.gart_size = 512ULL << 20;
725 break;
726 }
727 } else
728 adev->gmc.gart_size = (u64)amdgpu_gart_size << 20;
729
730 gmc_v10_0_vram_gtt_location(adev, &adev->gmc);
731
732 return 0;
733}
734
735static int gmc_v10_0_gart_init(struct amdgpu_device *adev)
736{
737 int r;
738
739 if (adev->gart.bo) {
740 WARN(1, "NAVI10 PCIE GART already initialized\n");
741 return 0;
742 }
743
744 /* Initialize common gart structure */
745 r = amdgpu_gart_init(adev);
746 if (r)
747 return r;
748
749 adev->gart.table_size = adev->gart.num_gpu_pages * 8;
750 adev->gart.gart_pte_flags = AMDGPU_PTE_MTYPE_NV10(MTYPE_UC) |
751 AMDGPU_PTE_EXECUTABLE;
752
753 return amdgpu_gart_table_vram_alloc(adev);
754}
755
756static unsigned gmc_v10_0_get_vbios_fb_size(struct amdgpu_device *adev)
757{
758 u32 d1vga_control = RREG32_SOC15(DCE, 0, mmD1VGA_CONTROL);
759 unsigned size;
760
761 if (REG_GET_FIELD(d1vga_control, D1VGA_CONTROL, D1VGA_MODE_ENABLE)) {
762 size = 9 * 1024 * 1024; /* reserve 8MB for vga emulator and 1 MB for FB */
763 } else {
764 u32 viewport;
765 u32 pitch;
766
767 viewport = RREG32_SOC15(DCE, 0, mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION);
768 pitch = RREG32_SOC15(DCE, 0, mmHUBPREQ0_DCSURF_SURFACE_PITCH);
769 size = (REG_GET_FIELD(viewport,
770 HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_HEIGHT) *
771 REG_GET_FIELD(pitch, HUBPREQ0_DCSURF_SURFACE_PITCH, PITCH) *
772 4);
773 }
774 /* return 0 if the pre-OS buffer uses up most of vram */
775 if ((adev->gmc.real_vram_size - size) < (8 * 1024 * 1024)) {
776 DRM_ERROR("Warning: pre-OS buffer uses most of vram, \
777 be aware of gart table overwrite\n");
778 return 0;
779 }
780
781 return size;
782}
783
784
785
786static int gmc_v10_0_sw_init(void *handle)
787{
ad02e08e 788 int r, vram_width = 0, vram_type = 0, vram_vendor = 0;
f9df67e9
HZ		 789 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
790
0b3df16b
LG		 791 if (adev->asic_type == CHIP_SIENNA_CICHLID)
792 gfxhub_v2_1_init(adev);
793 else
794 gfxhub_v2_0_init(adev);
795
f9df67e9
HZ		 796 mmhub_v2_0_init(adev);
797
798 spin_lock_init(&adev->gmc.invalidate_lock);
799
0b3df16b
LG		 800 if (adev->asic_type == CHIP_SIENNA_CICHLID && amdgpu_emu_mode == 1) {
801 adev->gmc.vram_type = AMDGPU_VRAM_TYPE_GDDR6;
631cdbd2 802 adev->gmc.vram_width = 1 * 128; /* numchan * chansize */
0b3df16b
LG		 803 } else {
804 r = amdgpu_atomfirmware_get_vram_info(adev,
805 &vram_width, &vram_type, &vram_vendor);
806 adev->gmc.vram_width = vram_width;
807
808 adev->gmc.vram_type = vram_type;
809 adev->gmc.vram_vendor = vram_vendor;
810 }
631cdbd2 811
f9df67e9
HZ		 812 switch (adev->asic_type) {
813 case CHIP_NAVI10:
05d72b8d 814 case CHIP_NAVI14:
4a0e815f 815 case CHIP_NAVI12:
57d70602 816 case CHIP_SIENNA_CICHLID:
1daa2bfa 817 adev->num_vmhubs = 2;
f9df67e9
HZ		 818 /*
819 * To fulfill 4-level page support,
4a0e815f 820 * vm size is 256TB (48bit), maximum size of Navi10/Navi14/Navi12,
f9df67e9
HZ		 821 * block size 512 (9bit)
822 */
823 amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48);
824 break;
825 default:
826 break;
827 }
828
829 /* This interrupt is VMC page fault.*/
830 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VMC,
831 VMC_1_0__SRCID__VM_FAULT,
832 &adev->gmc.vm_fault);
5021e9a8
ND		 833
834 if (r)
835 return r;
836
f9df67e9
HZ		 837 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_UTCL2,
838 UTCL2_1_0__SRCID__FAULT,
839 &adev->gmc.vm_fault);
840 if (r)
841 return r;
842
843 /*
844 * Set the internal MC address mask This is the max address of the GPU's
845 * internal address space.
846 */
847 adev->gmc.mc_mask = 0xffffffffffffULL; /* 48 bit MC */
848
244511f3 849 r = dma_set_mask_and_coherent(adev->dev, DMA_BIT_MASK(44));
f9df67e9 850 if (r) {
f9df67e9 851 printk(KERN_WARNING "amdgpu: No suitable DMA available.\n");
244511f3 852 return r;
f9df67e9
HZ		 853 }
854
855 r = gmc_v10_0_mc_init(adev);
856 if (r)
857 return r;
858
859 adev->gmc.stolen_size = gmc_v10_0_get_vbios_fb_size(adev);
860
861 /* Memory manager */
862 r = amdgpu_bo_init(adev);
863 if (r)
864 return r;
865
866 r = gmc_v10_0_gart_init(adev);
867 if (r)
868 return r;
869
870 /*
871 * number of VMs
872 * VMID 0 is reserved for System
873 * amdgpu graphics/compute will use VMIDs 1-7
874 * amdkfd will use VMIDs 8-15
875 */
a2d15ed7
LM		 876 adev->vm_manager.id_mgr[AMDGPU_GFXHUB_0].num_ids = AMDGPU_NUM_OF_VMIDS;
877 adev->vm_manager.id_mgr[AMDGPU_MMHUB_0].num_ids = AMDGPU_NUM_OF_VMIDS;
f9df67e9
HZ		 878
879 amdgpu_vm_manager_init(adev);
880
881 return 0;
882}
883
884/**
885 * gmc_v8_0_gart_fini - vm fini callback
886 *
887 * @adev: amdgpu_device pointer
888 *
889 * Tears down the driver GART/VM setup (CIK).
890 */
891static void gmc_v10_0_gart_fini(struct amdgpu_device *adev)
892{
893 amdgpu_gart_table_vram_free(adev);
894 amdgpu_gart_fini(adev);
895}
896
897static int gmc_v10_0_sw_fini(void *handle)
898{
899 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
900
901 amdgpu_vm_manager_fini(adev);
902 gmc_v10_0_gart_fini(adev);
903 amdgpu_gem_force_release(adev);
904 amdgpu_bo_fini(adev);
905
906 return 0;
907}
908
909static void gmc_v10_0_init_golden_registers(struct amdgpu_device *adev)
910{
911 switch (adev->asic_type) {
912 case CHIP_NAVI10:
05d72b8d 913 case CHIP_NAVI14:
4a0e815f 914 case CHIP_NAVI12:
57d70602 915 case CHIP_SIENNA_CICHLID:
f9df67e9
HZ		 916 break;
917 default:
918 break;
919 }
920}
921
922/**
923 * gmc_v10_0_gart_enable - gart enable
924 *
925 * @adev: amdgpu_device pointer
926 */
927static int gmc_v10_0_gart_enable(struct amdgpu_device *adev)
928{
929 int r;
930 bool value;
931 u32 tmp;
932
933 if (adev->gart.bo == NULL) {
934 dev_err(adev->dev, "No VRAM object for PCIE GART.\n");
935 return -EINVAL;
936 }
937
938 r = amdgpu_gart_table_vram_pin(adev);
939 if (r)
940 return r;
941
0b3df16b
LG		 942 if (adev->asic_type == CHIP_SIENNA_CICHLID)
943 r = gfxhub_v2_1_gart_enable(adev);
944 else
945 r = gfxhub_v2_0_gart_enable(adev);
f9df67e9
HZ		 946 if (r)
947 return r;
948
949 r = mmhub_v2_0_gart_enable(adev);
950 if (r)
951 return r;
952
953 tmp = RREG32_SOC15(HDP, 0, mmHDP_MISC_CNTL);
954 tmp |= HDP_MISC_CNTL__FLUSH_INVALIDATE_CACHE_MASK;
955 WREG32_SOC15(HDP, 0, mmHDP_MISC_CNTL, tmp);
956
957 tmp = RREG32_SOC15(HDP, 0, mmHDP_HOST_PATH_CNTL);
958 WREG32_SOC15(HDP, 0, mmHDP_HOST_PATH_CNTL, tmp);
959
960 /* Flush HDP after it is initialized */
bebc0762 961 adev->nbio.funcs->hdp_flush(adev, NULL);
f9df67e9
HZ		 962
963 value = (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS) ?
964 false : true;
965
0b3df16b
LG		 966 if (adev->asic_type == CHIP_SIENNA_CICHLID)
967 gfxhub_v2_1_set_fault_enable_default(adev, value);
968 else
969 gfxhub_v2_0_set_fault_enable_default(adev, value);
f9df67e9 970 mmhub_v2_0_set_fault_enable_default(adev, value);
3ff98548
OZ		 971 gmc_v10_0_flush_gpu_tlb(adev, 0, AMDGPU_MMHUB_0, 0);
972 gmc_v10_0_flush_gpu_tlb(adev, 0, AMDGPU_GFXHUB_0, 0);
f9df67e9
HZ		 973
974 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
975 (unsigned)(adev->gmc.gart_size >> 20),
976 (unsigned long long)amdgpu_bo_gpu_offset(adev->gart.bo));
977
978 adev->gart.ready = true;
979
980 return 0;
981}
982
983static int gmc_v10_0_hw_init(void *handle)
984{
985 int r;
986 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
987
988 /* The sequence of these two function calls matters.*/
989 gmc_v10_0_init_golden_registers(adev);
990
991 r = gmc_v10_0_gart_enable(adev);
992 if (r)
993 return r;
994
995 return 0;
996}
997
998/**
999 * gmc_v10_0_gart_disable - gart disable
1000 *
1001 * @adev: amdgpu_device pointer
1002 *
1003 * This disables all VM page table.
1004 */
1005static void gmc_v10_0_gart_disable(struct amdgpu_device *adev)
1006{
0b3df16b
LG		 1007 if (adev->asic_type == CHIP_SIENNA_CICHLID)
1008 gfxhub_v2_1_gart_disable(adev);
1009 else
1010 gfxhub_v2_0_gart_disable(adev);
f9df67e9
HZ		 1011 mmhub_v2_0_gart_disable(adev);
1012 amdgpu_gart_table_vram_unpin(adev);
1013}
1014
1015static int gmc_v10_0_hw_fini(void *handle)
1016{
1017 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1018
1019 if (amdgpu_sriov_vf(adev)) {
1020 /* full access mode, so don't touch any GMC register */
1021 DRM_DEBUG("For SRIOV client, shouldn't do anything.\n");
1022 return 0;
1023 }
1024
1025 amdgpu_irq_put(adev, &adev->gmc.vm_fault, 0);
1026 gmc_v10_0_gart_disable(adev);
1027
1028 return 0;
1029}
1030
1031static int gmc_v10_0_suspend(void *handle)
1032{
1033 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1034
1035 gmc_v10_0_hw_fini(adev);
1036
1037 return 0;
1038}
1039
1040static int gmc_v10_0_resume(void *handle)
1041{
1042 int r;
1043 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1044
1045 r = gmc_v10_0_hw_init(adev);
1046 if (r)
1047 return r;
1048
1049 amdgpu_vmid_reset_all(adev);
1050
1051 return 0;
1052}
1053
1054static bool gmc_v10_0_is_idle(void *handle)
1055{
1056 /* MC is always ready in GMC v10.*/
1057 return true;
1058}
1059
1060static int gmc_v10_0_wait_for_idle(void *handle)
1061{
1062 /* There is no need to wait for MC idle in GMC v10.*/
1063 return 0;
1064}
1065
1066static int gmc_v10_0_soft_reset(void *handle)
1067{
1068 return 0;
1069}
1070
1071static int gmc_v10_0_set_clockgating_state(void *handle,
1072 enum amd_clockgating_state state)
1073{
1074 int r;
1075 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1076
1077 r = mmhub_v2_0_set_clockgating(adev, state);
1078 if (r)
1079 return r;
1080
1081 return athub_v2_0_set_clockgating(adev, state);
1082}
1083
1084static void gmc_v10_0_get_clockgating_state(void *handle, u32 *flags)
1085{
1086 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1087
1088 mmhub_v2_0_get_clockgating(adev, flags);
1089
1090 athub_v2_0_get_clockgating(adev, flags);
1091}
1092
1093static int gmc_v10_0_set_powergating_state(void *handle,
1094 enum amd_powergating_state state)
1095{
1096 return 0;
1097}
1098
1099const struct amd_ip_funcs gmc_v10_0_ip_funcs = {
1100 .name = "gmc_v10_0",
1101 .early_init = gmc_v10_0_early_init,
1102 .late_init = gmc_v10_0_late_init,
1103 .sw_init = gmc_v10_0_sw_init,
1104 .sw_fini = gmc_v10_0_sw_fini,
1105 .hw_init = gmc_v10_0_hw_init,
1106 .hw_fini = gmc_v10_0_hw_fini,
1107 .suspend = gmc_v10_0_suspend,
1108 .resume = gmc_v10_0_resume,
1109 .is_idle = gmc_v10_0_is_idle,
1110 .wait_for_idle = gmc_v10_0_wait_for_idle,
1111 .soft_reset = gmc_v10_0_soft_reset,
1112 .set_clockgating_state = gmc_v10_0_set_clockgating_state,
1113 .set_powergating_state = gmc_v10_0_set_powergating_state,
1114 .get_clockgating_state = gmc_v10_0_get_clockgating_state,
1115};
1116
1117const struct amdgpu_ip_block_version gmc_v10_0_ip_block =
1118{
1119 .type = AMD_IP_BLOCK_TYPE_GMC,
1120 .major = 10,
1121 .minor = 0,
1122 .rev = 0,
1123 .funcs = &gmc_v10_0_ip_funcs,
1124};
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