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f9df67e9 HZ |
1 | /* |
2 | * Copyright 2019 Advanced Micro Devices, Inc. | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice shall be included in | |
12 | * all copies or substantial portions of the Software. | |
13 | * | |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
20 | * OTHER DEALINGS IN THE SOFTWARE. | |
21 | * | |
22 | */ | |
23 | #include <linux/firmware.h> | |
d7929c1e | 24 | #include <linux/pci.h> |
f9df67e9 HZ |
25 | #include "amdgpu.h" |
26 | #include "amdgpu_atomfirmware.h" | |
27 | #include "gmc_v10_0.h" | |
01eee24f | 28 | #include "umc_v8_7.h" |
f9df67e9 | 29 | |
ea930000 AS |
30 | #include "athub/athub_2_0_0_sh_mask.h" |
31 | #include "athub/athub_2_0_0_offset.h" | |
f9df67e9 HZ |
32 | #include "dcn/dcn_2_0_0_offset.h" |
33 | #include "dcn/dcn_2_0_0_sh_mask.h" | |
34 | #include "oss/osssys_5_0_0_offset.h" | |
35 | #include "ivsrcid/vmc/irqsrcs_vmc_1_0.h" | |
36 | #include "navi10_enum.h" | |
37 | ||
38 | #include "soc15.h" | |
ea930000 | 39 | #include "soc15d.h" |
f9df67e9 HZ |
40 | #include "soc15_common.h" |
41 | ||
42 | #include "nbio_v2_3.h" | |
43 | ||
44 | #include "gfxhub_v2_0.h" | |
0b3df16b | 45 | #include "gfxhub_v2_1.h" |
f9df67e9 | 46 | #include "mmhub_v2_0.h" |
4d8d75a4 | 47 | #include "mmhub_v2_3.h" |
f9df67e9 | 48 | #include "athub_v2_0.h" |
920a4cd3 | 49 | #include "athub_v2_1.h" |
f9df67e9 HZ |
50 | |
51 | #if 0 | |
52 | static const struct soc15_reg_golden golden_settings_navi10_hdp[] = | |
53 | { | |
54 | /* TODO add golden setting for hdp */ | |
55 | }; | |
56 | #endif | |
57 | ||
01eee24f JC |
58 | static int gmc_v10_0_ecc_interrupt_state(struct amdgpu_device *adev, |
59 | struct amdgpu_irq_src *src, | |
60 | unsigned type, | |
61 | enum amdgpu_interrupt_state state) | |
62 | { | |
63 | return 0; | |
64 | } | |
65 | ||
f9df67e9 HZ |
66 | static int |
67 | gmc_v10_0_vm_fault_interrupt_state(struct amdgpu_device *adev, | |
68 | struct amdgpu_irq_src *src, unsigned type, | |
69 | enum amdgpu_interrupt_state state) | |
70 | { | |
f9df67e9 HZ |
71 | switch (state) { |
72 | case AMDGPU_IRQ_STATE_DISABLE: | |
73 | /* MM HUB */ | |
f2c1b5c1 | 74 | amdgpu_gmc_set_vm_fault_masks(adev, AMDGPU_MMHUB_0, false); |
f9df67e9 | 75 | /* GFX HUB */ |
f2c1b5c1 | 76 | amdgpu_gmc_set_vm_fault_masks(adev, AMDGPU_GFXHUB_0, false); |
f9df67e9 HZ |
77 | break; |
78 | case AMDGPU_IRQ_STATE_ENABLE: | |
79 | /* MM HUB */ | |
f2c1b5c1 | 80 | amdgpu_gmc_set_vm_fault_masks(adev, AMDGPU_MMHUB_0, true); |
f9df67e9 | 81 | /* GFX HUB */ |
f2c1b5c1 | 82 | amdgpu_gmc_set_vm_fault_masks(adev, AMDGPU_GFXHUB_0, true); |
f9df67e9 HZ |
83 | break; |
84 | default: | |
85 | break; | |
86 | } | |
87 | ||
88 | return 0; | |
89 | } | |
90 | ||
91 | static int gmc_v10_0_process_interrupt(struct amdgpu_device *adev, | |
92 | struct amdgpu_irq_src *source, | |
93 | struct amdgpu_iv_entry *entry) | |
94 | { | |
a2a8857c | 95 | bool retry_fault = !!(entry->src_data[1] & 0x80); |
ff891a2e | 96 | bool write_fault = !!(entry->src_data[1] & 0x20); |
f9df67e9 | 97 | struct amdgpu_vmhub *hub = &adev->vmhub[entry->vmid_src]; |
45d87b85 | 98 | struct amdgpu_task_info task_info; |
f9df67e9 HZ |
99 | uint32_t status = 0; |
100 | u64 addr; | |
101 | ||
102 | addr = (u64)entry->src_data[0] << 12; | |
103 | addr |= ((u64)entry->src_data[1] & 0xf) << 44; | |
104 | ||
a2a8857c CK |
105 | if (retry_fault) { |
106 | /* Returning 1 here also prevents sending the IV to the KFD */ | |
107 | ||
108 | /* Process it onyl if it's the first fault for this address */ | |
109 | if (entry->ih != &adev->irq.ih_soft && | |
110 | amdgpu_gmc_filter_faults(adev, addr, entry->pasid, | |
111 | entry->timestamp)) | |
112 | return 1; | |
113 | ||
114 | /* Delegate it to a different ring if the hardware hasn't | |
115 | * already done it. | |
116 | */ | |
58df0d71 | 117 | if (entry->ih == &adev->irq.ih) { |
a2a8857c CK |
118 | amdgpu_irq_delegate(adev, entry, 8); |
119 | return 1; | |
120 | } | |
121 | ||
122 | /* Try to handle the recoverable page faults by filling page | |
123 | * tables | |
124 | */ | |
ff891a2e | 125 | if (amdgpu_vm_handle_fault(adev, entry->pasid, addr, write_fault)) |
a2a8857c CK |
126 | return 1; |
127 | } | |
128 | ||
f9df67e9 | 129 | if (!amdgpu_sriov_vf(adev)) { |
53499173 XY |
130 | /* |
131 | * Issue a dummy read to wait for the status register to | |
132 | * be updated to avoid reading an incorrect value due to | |
133 | * the new fast GRBM interface. | |
134 | */ | |
5c46c492 AD |
135 | if ((entry->vmid_src == AMDGPU_GFXHUB_0) && |
136 | (adev->asic_type < CHIP_SIENNA_CICHLID)) | |
53499173 XY |
137 | RREG32(hub->vm_l2_pro_fault_status); |
138 | ||
f9df67e9 HZ |
139 | status = RREG32(hub->vm_l2_pro_fault_status); |
140 | WREG32_P(hub->vm_l2_pro_fault_cntl, 1, ~1); | |
141 | } | |
142 | ||
45d87b85 CK |
143 | if (!printk_ratelimit()) |
144 | return 0; | |
145 | ||
146 | memset(&task_info, 0, sizeof(struct amdgpu_task_info)); | |
147 | amdgpu_vm_get_task_info(adev, entry->pasid, &task_info); | |
148 | ||
149 | dev_err(adev->dev, | |
150 | "[%s] page fault (src_id:%u ring:%u vmid:%u pasid:%u, " | |
151 | "for process %s pid %d thread %s pid %d)\n", | |
152 | entry->vmid_src ? "mmhub" : "gfxhub", | |
153 | entry->src_id, entry->ring_id, entry->vmid, | |
154 | entry->pasid, task_info.process_name, task_info.tgid, | |
155 | task_info.task_name, task_info.pid); | |
be14729a YZ |
156 | dev_err(adev->dev, " in page starting at address 0x%016llx from client 0x%x (%s)\n", |
157 | addr, entry->client_id, | |
158 | soc15_ih_clientid_name[entry->client_id]); | |
45d87b85 CK |
159 | |
160 | if (!amdgpu_sriov_vf(adev)) | |
161 | hub->vmhub_funcs->print_l2_protection_fault_status(adev, | |
162 | status); | |
f9df67e9 HZ |
163 | |
164 | return 0; | |
165 | } | |
166 | ||
167 | static const struct amdgpu_irq_src_funcs gmc_v10_0_irq_funcs = { | |
168 | .set = gmc_v10_0_vm_fault_interrupt_state, | |
169 | .process = gmc_v10_0_process_interrupt, | |
170 | }; | |
171 | ||
01eee24f JC |
172 | static const struct amdgpu_irq_src_funcs gmc_v10_0_ecc_funcs = { |
173 | .set = gmc_v10_0_ecc_interrupt_state, | |
174 | .process = amdgpu_umc_process_ecc_irq, | |
175 | }; | |
176 | ||
94ba290d | 177 | static void gmc_v10_0_set_irq_funcs(struct amdgpu_device *adev) |
f9df67e9 HZ |
178 | { |
179 | adev->gmc.vm_fault.num_types = 1; | |
180 | adev->gmc.vm_fault.funcs = &gmc_v10_0_irq_funcs; | |
01eee24f JC |
181 | |
182 | if (!amdgpu_sriov_vf(adev)) { | |
183 | adev->gmc.ecc_irq.num_types = 1; | |
184 | adev->gmc.ecc_irq.funcs = &gmc_v10_0_ecc_funcs; | |
185 | } | |
f9df67e9 HZ |
186 | } |
187 | ||
f271fe18 | 188 | /** |
189 | * gmc_v10_0_use_invalidate_semaphore - judge whether to use semaphore | |
190 | * | |
191 | * @adev: amdgpu_device pointer | |
192 | * @vmhub: vmhub type | |
193 | * | |
194 | */ | |
195 | static bool gmc_v10_0_use_invalidate_semaphore(struct amdgpu_device *adev, | |
196 | uint32_t vmhub) | |
197 | { | |
198 | return ((vmhub == AMDGPU_MMHUB_0 || | |
199 | vmhub == AMDGPU_MMHUB_1) && | |
200 | (!amdgpu_sriov_vf(adev))); | |
201 | } | |
202 | ||
ea930000 AS |
203 | static bool gmc_v10_0_get_atc_vmid_pasid_mapping_info( |
204 | struct amdgpu_device *adev, | |
205 | uint8_t vmid, uint16_t *p_pasid) | |
206 | { | |
207 | uint32_t value; | |
208 | ||
209 | value = RREG32(SOC15_REG_OFFSET(ATHUB, 0, mmATC_VMID0_PASID_MAPPING) | |
210 | + vmid); | |
211 | *p_pasid = value & ATC_VMID0_PASID_MAPPING__PASID_MASK; | |
212 | ||
213 | return !!(value & ATC_VMID0_PASID_MAPPING__VALID_MASK); | |
214 | } | |
215 | ||
f9df67e9 HZ |
216 | /* |
217 | * GART | |
218 | * VMID 0 is the physical GPU addresses as used by the kernel. | |
219 | * VMIDs 1-15 are used for userspace clients and are handled | |
220 | * by the amdgpu vm/hsa code. | |
221 | */ | |
222 | ||
223 | static void gmc_v10_0_flush_vm_hub(struct amdgpu_device *adev, uint32_t vmid, | |
224 | unsigned int vmhub, uint32_t flush_type) | |
225 | { | |
f271fe18 | 226 | bool use_semaphore = gmc_v10_0_use_invalidate_semaphore(adev, vmhub); |
f9df67e9 | 227 | struct amdgpu_vmhub *hub = &adev->vmhub[vmhub]; |
caa9f483 | 228 | u32 inv_req = hub->vmhub_funcs->get_invalidate_req(vmid, flush_type); |
37c58ddf | 229 | u32 tmp; |
f9df67e9 HZ |
230 | /* Use register 17 for GART */ |
231 | const unsigned eng = 17; | |
232 | unsigned int i; | |
6ba3f59e PJZ |
233 | unsigned char hub_ip = 0; |
234 | ||
235 | hub_ip = (vmhub == AMDGPU_GFXHUB_0) ? | |
236 | GC_HWIP : MMHUB_HWIP; | |
f9df67e9 | 237 | |
f920d1bb | 238 | spin_lock(&adev->gmc.invalidate_lock); |
239 | /* | |
240 | * It may lose gpuvm invalidate acknowldege state across power-gating | |
241 | * off cycle, add semaphore acquire before invalidation and semaphore | |
242 | * release after invalidation to avoid entering power gated state | |
243 | * to WA the Issue | |
244 | */ | |
245 | ||
246 | /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */ | |
f271fe18 | 247 | if (use_semaphore) { |
f920d1bb | 248 | for (i = 0; i < adev->usec_timeout; i++) { |
249 | /* a read return value of 1 means semaphore acuqire */ | |
6ba3f59e PJZ |
250 | tmp = RREG32_RLC_NO_KIQ(hub->vm_inv_eng0_sem + |
251 | hub->eng_distance * eng, hub_ip); | |
252 | ||
f920d1bb | 253 | if (tmp & 0x1) |
254 | break; | |
255 | udelay(1); | |
256 | } | |
257 | ||
258 | if (i >= adev->usec_timeout) | |
259 | DRM_ERROR("Timeout waiting for sem acquire in VM flush!\n"); | |
260 | } | |
261 | ||
6ba3f59e PJZ |
262 | WREG32_RLC_NO_KIQ(hub->vm_inv_eng0_req + |
263 | hub->eng_distance * eng, | |
264 | inv_req, hub_ip); | |
f9df67e9 | 265 | |
53499173 XY |
266 | /* |
267 | * Issue a dummy read to wait for the ACK register to be cleared | |
268 | * to avoid a false ACK due to the new fast GRBM interface. | |
269 | */ | |
5c46c492 AD |
270 | if ((vmhub == AMDGPU_GFXHUB_0) && |
271 | (adev->asic_type < CHIP_SIENNA_CICHLID)) | |
6ba3f59e PJZ |
272 | RREG32_RLC_NO_KIQ(hub->vm_inv_eng0_req + |
273 | hub->eng_distance * eng, hub_ip); | |
53499173 | 274 | |
f9df67e9 HZ |
275 | /* Wait for ACK with a delay.*/ |
276 | for (i = 0; i < adev->usec_timeout; i++) { | |
6ba3f59e PJZ |
277 | tmp = RREG32_RLC_NO_KIQ(hub->vm_inv_eng0_ack + |
278 | hub->eng_distance * eng, hub_ip); | |
279 | ||
f9df67e9 HZ |
280 | tmp &= 1 << vmid; |
281 | if (tmp) | |
282 | break; | |
283 | ||
284 | udelay(1); | |
285 | } | |
286 | ||
f920d1bb | 287 | /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */ |
f271fe18 | 288 | if (use_semaphore) |
f920d1bb | 289 | /* |
290 | * add semaphore release after invalidation, | |
291 | * write with 0 means semaphore release | |
292 | */ | |
6ba3f59e PJZ |
293 | WREG32_RLC_NO_KIQ(hub->vm_inv_eng0_sem + |
294 | hub->eng_distance * eng, 0, hub_ip); | |
f920d1bb | 295 | |
296 | spin_unlock(&adev->gmc.invalidate_lock); | |
297 | ||
f9df67e9 HZ |
298 | if (i < adev->usec_timeout) |
299 | return; | |
300 | ||
d9c7f753 | 301 | DRM_ERROR("Timeout waiting for VM flush hub: %d!\n", vmhub); |
f9df67e9 HZ |
302 | } |
303 | ||
304 | /** | |
305 | * gmc_v10_0_flush_gpu_tlb - gart tlb flush callback | |
306 | * | |
307 | * @adev: amdgpu_device pointer | |
308 | * @vmid: vm instance to flush | |
185ef9ef LJ |
309 | * @vmhub: vmhub type |
310 | * @flush_type: the flush type | |
f9df67e9 HZ |
311 | * |
312 | * Flush the TLB for the requested page table. | |
313 | */ | |
3ff98548 OZ |
314 | static void gmc_v10_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid, |
315 | uint32_t vmhub, uint32_t flush_type) | |
f9df67e9 HZ |
316 | { |
317 | struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring; | |
318 | struct dma_fence *fence; | |
319 | struct amdgpu_job *job; | |
320 | ||
321 | int r; | |
322 | ||
323 | /* flush hdp cache */ | |
bf087285 | 324 | adev->hdp.funcs->flush_hdp(adev, NULL); |
f9df67e9 | 325 | |
8db1015b | 326 | /* For SRIOV run time, driver shouldn't access the register through MMIO |
327 | * Directly use kiq to do the vm invalidation instead | |
328 | */ | |
329 | if (adev->gfx.kiq.ring.sched.ready && | |
330 | (amdgpu_sriov_runtime(adev) || !amdgpu_sriov_vf(adev)) && | |
81202807 | 331 | down_read_trylock(&adev->reset_sem)) { |
8db1015b | 332 | struct amdgpu_vmhub *hub = &adev->vmhub[vmhub]; |
333 | const unsigned eng = 17; | |
caa9f483 | 334 | u32 inv_req = hub->vmhub_funcs->get_invalidate_req(vmid, flush_type); |
af6c5c4f HR |
335 | u32 req = hub->vm_inv_eng0_req + hub->eng_distance * eng; |
336 | u32 ack = hub->vm_inv_eng0_ack + hub->eng_distance * eng; | |
8db1015b | 337 | |
338 | amdgpu_virt_kiq_reg_write_reg_wait(adev, req, ack, inv_req, | |
339 | 1 << vmid); | |
81202807 DL |
340 | |
341 | up_read(&adev->reset_sem); | |
8db1015b | 342 | return; |
343 | } | |
344 | ||
f9df67e9 HZ |
345 | mutex_lock(&adev->mman.gtt_window_lock); |
346 | ||
3ff98548 OZ |
347 | if (vmhub == AMDGPU_MMHUB_0) { |
348 | gmc_v10_0_flush_vm_hub(adev, vmid, AMDGPU_MMHUB_0, 0); | |
349 | mutex_unlock(&adev->mman.gtt_window_lock); | |
350 | return; | |
351 | } | |
352 | ||
353 | BUG_ON(vmhub != AMDGPU_GFXHUB_0); | |
354 | ||
767acabd KW |
355 | if (!adev->mman.buffer_funcs_enabled || |
356 | !adev->ib_pool_ready || | |
53b3f8f4 | 357 | amdgpu_in_reset(adev) || |
e2195f7d | 358 | ring->sched.ready == false) { |
a2d15ed7 | 359 | gmc_v10_0_flush_vm_hub(adev, vmid, AMDGPU_GFXHUB_0, 0); |
f9df67e9 HZ |
360 | mutex_unlock(&adev->mman.gtt_window_lock); |
361 | return; | |
362 | } | |
363 | ||
364 | /* The SDMA on Navi has a bug which can theoretically result in memory | |
365 | * corruption if an invalidation happens at the same time as an VA | |
366 | * translation. Avoid this by doing the invalidation from the SDMA | |
367 | * itself. | |
368 | */ | |
9ecefb19 CK |
369 | r = amdgpu_job_alloc_with_ib(adev, 16 * 4, AMDGPU_IB_POOL_IMMEDIATE, |
370 | &job); | |
f9df67e9 HZ |
371 | if (r) |
372 | goto error_alloc; | |
373 | ||
374 | job->vm_pd_addr = amdgpu_gmc_pd_addr(adev->gart.bo); | |
375 | job->vm_needs_flush = true; | |
3f378758 | 376 | job->ibs->ptr[job->ibs->length_dw++] = ring->funcs->nop; |
f9df67e9 HZ |
377 | amdgpu_ring_pad_ib(ring, &job->ibs[0]); |
378 | r = amdgpu_job_submit(job, &adev->mman.entity, | |
379 | AMDGPU_FENCE_OWNER_UNDEFINED, &fence); | |
380 | if (r) | |
381 | goto error_submit; | |
382 | ||
383 | mutex_unlock(&adev->mman.gtt_window_lock); | |
384 | ||
385 | dma_fence_wait(fence, false); | |
386 | dma_fence_put(fence); | |
387 | ||
388 | return; | |
389 | ||
390 | error_submit: | |
391 | amdgpu_job_free(job); | |
392 | ||
393 | error_alloc: | |
394 | mutex_unlock(&adev->mman.gtt_window_lock); | |
395 | DRM_ERROR("Error flushing GPU TLB using the SDMA (%d)!\n", r); | |
396 | } | |
397 | ||
ea930000 AS |
398 | /** |
399 | * gmc_v10_0_flush_gpu_tlb_pasid - tlb flush via pasid | |
400 | * | |
401 | * @adev: amdgpu_device pointer | |
402 | * @pasid: pasid to be flush | |
185ef9ef LJ |
403 | * @flush_type: the flush type |
404 | * @all_hub: Used with PACKET3_INVALIDATE_TLBS_ALL_HUB() | |
ea930000 AS |
405 | * |
406 | * Flush the TLB for the requested pasid. | |
407 | */ | |
408 | static int gmc_v10_0_flush_gpu_tlb_pasid(struct amdgpu_device *adev, | |
409 | uint16_t pasid, uint32_t flush_type, | |
410 | bool all_hub) | |
411 | { | |
412 | int vmid, i; | |
413 | signed long r; | |
414 | uint32_t seq; | |
415 | uint16_t queried_pasid; | |
416 | bool ret; | |
417 | struct amdgpu_ring *ring = &adev->gfx.kiq.ring; | |
418 | struct amdgpu_kiq *kiq = &adev->gfx.kiq; | |
419 | ||
420 | if (amdgpu_emu_mode == 0 && ring->sched.ready) { | |
421 | spin_lock(&adev->gfx.kiq.ring_lock); | |
36a1707a AS |
422 | /* 2 dwords flush + 8 dwords fence */ |
423 | amdgpu_ring_alloc(ring, kiq->pmf->invalidate_tlbs_size + 8); | |
ea930000 AS |
424 | kiq->pmf->kiq_invalidate_tlbs(ring, |
425 | pasid, flush_type, all_hub); | |
04e4e2e9 YT |
426 | r = amdgpu_fence_emit_polling(ring, &seq, MAX_KIQ_REG_WAIT); |
427 | if (r) { | |
428 | amdgpu_ring_undo(ring); | |
abb17b1e | 429 | spin_unlock(&adev->gfx.kiq.ring_lock); |
04e4e2e9 YT |
430 | return -ETIME; |
431 | } | |
432 | ||
ea930000 AS |
433 | amdgpu_ring_commit(ring); |
434 | spin_unlock(&adev->gfx.kiq.ring_lock); | |
435 | r = amdgpu_fence_wait_polling(ring, seq, adev->usec_timeout); | |
436 | if (r < 1) { | |
aac89168 | 437 | dev_err(adev->dev, "wait for kiq fence error: %ld.\n", r); |
ea930000 AS |
438 | return -ETIME; |
439 | } | |
440 | ||
441 | return 0; | |
442 | } | |
443 | ||
68fce5f0 | 444 | for (vmid = 1; vmid < AMDGPU_NUM_VMID; vmid++) { |
ea930000 AS |
445 | |
446 | ret = gmc_v10_0_get_atc_vmid_pasid_mapping_info(adev, vmid, | |
447 | &queried_pasid); | |
448 | if (ret && queried_pasid == pasid) { | |
449 | if (all_hub) { | |
450 | for (i = 0; i < adev->num_vmhubs; i++) | |
451 | gmc_v10_0_flush_gpu_tlb(adev, vmid, | |
fa34edbe | 452 | i, flush_type); |
ea930000 AS |
453 | } else { |
454 | gmc_v10_0_flush_gpu_tlb(adev, vmid, | |
fa34edbe | 455 | AMDGPU_GFXHUB_0, flush_type); |
ea930000 AS |
456 | } |
457 | break; | |
458 | } | |
459 | } | |
460 | ||
461 | return 0; | |
462 | } | |
463 | ||
f9df67e9 HZ |
464 | static uint64_t gmc_v10_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring, |
465 | unsigned vmid, uint64_t pd_addr) | |
466 | { | |
f271fe18 | 467 | bool use_semaphore = gmc_v10_0_use_invalidate_semaphore(ring->adev, ring->funcs->vmhub); |
f9df67e9 | 468 | struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub]; |
caa9f483 | 469 | uint32_t req = hub->vmhub_funcs->get_invalidate_req(vmid, 0); |
f9df67e9 HZ |
470 | unsigned eng = ring->vm_inv_eng; |
471 | ||
f920d1bb | 472 | /* |
473 | * It may lose gpuvm invalidate acknowldege state across power-gating | |
474 | * off cycle, add semaphore acquire before invalidation and semaphore | |
475 | * release after invalidation to avoid entering power gated state | |
476 | * to WA the Issue | |
477 | */ | |
478 | ||
479 | /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */ | |
f271fe18 | 480 | if (use_semaphore) |
f920d1bb | 481 | /* a read return value of 1 means semaphore acuqire */ |
482 | amdgpu_ring_emit_reg_wait(ring, | |
af6c5c4f HR |
483 | hub->vm_inv_eng0_sem + |
484 | hub->eng_distance * eng, 0x1, 0x1); | |
f920d1bb | 485 | |
af6c5c4f HR |
486 | amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_lo32 + |
487 | (hub->ctx_addr_distance * vmid), | |
f9df67e9 HZ |
488 | lower_32_bits(pd_addr)); |
489 | ||
af6c5c4f HR |
490 | amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_hi32 + |
491 | (hub->ctx_addr_distance * vmid), | |
f9df67e9 HZ |
492 | upper_32_bits(pd_addr)); |
493 | ||
af6c5c4f HR |
494 | amdgpu_ring_emit_reg_write_reg_wait(ring, hub->vm_inv_eng0_req + |
495 | hub->eng_distance * eng, | |
496 | hub->vm_inv_eng0_ack + | |
497 | hub->eng_distance * eng, | |
589b64a7 | 498 | req, 1 << vmid); |
f9df67e9 | 499 | |
f920d1bb | 500 | /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */ |
f271fe18 | 501 | if (use_semaphore) |
f920d1bb | 502 | /* |
503 | * add semaphore release after invalidation, | |
504 | * write with 0 means semaphore release | |
505 | */ | |
af6c5c4f HR |
506 | amdgpu_ring_emit_wreg(ring, hub->vm_inv_eng0_sem + |
507 | hub->eng_distance * eng, 0); | |
f920d1bb | 508 | |
f9df67e9 HZ |
509 | return pd_addr; |
510 | } | |
511 | ||
512 | static void gmc_v10_0_emit_pasid_mapping(struct amdgpu_ring *ring, unsigned vmid, | |
513 | unsigned pasid) | |
514 | { | |
515 | struct amdgpu_device *adev = ring->adev; | |
516 | uint32_t reg; | |
517 | ||
a2d15ed7 | 518 | if (ring->funcs->vmhub == AMDGPU_GFXHUB_0) |
f9df67e9 HZ |
519 | reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT) + vmid; |
520 | else | |
521 | reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT_MM) + vmid; | |
522 | ||
523 | amdgpu_ring_emit_wreg(ring, reg, pasid); | |
524 | } | |
525 | ||
526 | /* | |
527 | * PTE format on NAVI 10: | |
528 | * 63:59 reserved | |
4005809b LG |
529 | * 58 reserved and for sienna_cichlid is used for MALL noalloc |
530 | * 57 reserved | |
f9df67e9 HZ |
531 | * 56 F |
532 | * 55 L | |
533 | * 54 reserved | |
534 | * 53:52 SW | |
535 | * 51 T | |
536 | * 50:48 mtype | |
537 | * 47:12 4k physical page base address | |
538 | * 11:7 fragment | |
539 | * 6 write | |
540 | * 5 read | |
541 | * 4 exe | |
542 | * 3 Z | |
543 | * 2 snooped | |
544 | * 1 system | |
545 | * 0 valid | |
546 | * | |
547 | * PDE format on NAVI 10: | |
548 | * 63:59 block fragment size | |
549 | * 58:55 reserved | |
550 | * 54 P | |
551 | * 53:48 reserved | |
552 | * 47:6 physical base address of PD or PTE | |
553 | * 5:3 reserved | |
554 | * 2 C | |
555 | * 1 system | |
556 | * 0 valid | |
557 | */ | |
f9df67e9 | 558 | |
71776b6d CK |
559 | static uint64_t gmc_v10_0_map_mtype(struct amdgpu_device *adev, uint32_t flags) |
560 | { | |
561 | switch (flags) { | |
f9df67e9 | 562 | case AMDGPU_VM_MTYPE_DEFAULT: |
71776b6d | 563 | return AMDGPU_PTE_MTYPE_NV10(MTYPE_NC); |
f9df67e9 | 564 | case AMDGPU_VM_MTYPE_NC: |
71776b6d | 565 | return AMDGPU_PTE_MTYPE_NV10(MTYPE_NC); |
f9df67e9 | 566 | case AMDGPU_VM_MTYPE_WC: |
71776b6d | 567 | return AMDGPU_PTE_MTYPE_NV10(MTYPE_WC); |
f9df67e9 | 568 | case AMDGPU_VM_MTYPE_CC: |
71776b6d | 569 | return AMDGPU_PTE_MTYPE_NV10(MTYPE_CC); |
f9df67e9 | 570 | case AMDGPU_VM_MTYPE_UC: |
71776b6d | 571 | return AMDGPU_PTE_MTYPE_NV10(MTYPE_UC); |
f9df67e9 | 572 | default: |
71776b6d | 573 | return AMDGPU_PTE_MTYPE_NV10(MTYPE_NC); |
f9df67e9 | 574 | } |
f9df67e9 HZ |
575 | } |
576 | ||
577 | static void gmc_v10_0_get_vm_pde(struct amdgpu_device *adev, int level, | |
578 | uint64_t *addr, uint64_t *flags) | |
579 | { | |
580 | if (!(*flags & AMDGPU_PDE_PTE) && !(*flags & AMDGPU_PTE_SYSTEM)) | |
0ca565ab | 581 | *addr = amdgpu_gmc_vram_mc2pa(adev, *addr); |
f9df67e9 HZ |
582 | BUG_ON(*addr & 0xFFFF00000000003FULL); |
583 | ||
584 | if (!adev->gmc.translate_further) | |
585 | return; | |
586 | ||
587 | if (level == AMDGPU_VM_PDB1) { | |
588 | /* Set the block fragment size */ | |
589 | if (!(*flags & AMDGPU_PDE_PTE)) | |
590 | *flags |= AMDGPU_PDE_BFS(0x9); | |
591 | ||
592 | } else if (level == AMDGPU_VM_PDB0) { | |
593 | if (*flags & AMDGPU_PDE_PTE) | |
594 | *flags &= ~AMDGPU_PDE_PTE; | |
595 | else | |
596 | *flags |= AMDGPU_PTE_TF; | |
597 | } | |
598 | } | |
599 | ||
cbfae36c CK |
600 | static void gmc_v10_0_get_vm_pte(struct amdgpu_device *adev, |
601 | struct amdgpu_bo_va_mapping *mapping, | |
602 | uint64_t *flags) | |
603 | { | |
604 | *flags &= ~AMDGPU_PTE_EXECUTABLE; | |
605 | *flags |= mapping->flags & AMDGPU_PTE_EXECUTABLE; | |
606 | ||
607 | *flags &= ~AMDGPU_PTE_MTYPE_NV10_MASK; | |
608 | *flags |= (mapping->flags & AMDGPU_PTE_MTYPE_NV10_MASK); | |
609 | ||
610 | if (mapping->flags & AMDGPU_PTE_PRT) { | |
611 | *flags |= AMDGPU_PTE_PRT; | |
612 | *flags |= AMDGPU_PTE_SNOOPED; | |
613 | *flags |= AMDGPU_PTE_LOG; | |
614 | *flags |= AMDGPU_PTE_SYSTEM; | |
615 | *flags &= ~AMDGPU_PTE_VALID; | |
616 | } | |
617 | } | |
618 | ||
7348c20a AD |
619 | static unsigned gmc_v10_0_get_vbios_fb_size(struct amdgpu_device *adev) |
620 | { | |
621 | u32 d1vga_control = RREG32_SOC15(DCE, 0, mmD1VGA_CONTROL); | |
622 | unsigned size; | |
623 | ||
624 | if (REG_GET_FIELD(d1vga_control, D1VGA_CONTROL, D1VGA_MODE_ENABLE)) { | |
625 | size = AMDGPU_VBIOS_VGA_ALLOCATION; | |
626 | } else { | |
627 | u32 viewport; | |
628 | u32 pitch; | |
629 | ||
630 | viewport = RREG32_SOC15(DCE, 0, mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION); | |
631 | pitch = RREG32_SOC15(DCE, 0, mmHUBPREQ0_DCSURF_SURFACE_PITCH); | |
632 | size = (REG_GET_FIELD(viewport, | |
633 | HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_HEIGHT) * | |
634 | REG_GET_FIELD(pitch, HUBPREQ0_DCSURF_SURFACE_PITCH, PITCH) * | |
635 | 4); | |
636 | } | |
637 | ||
638 | return size; | |
639 | } | |
640 | ||
f9df67e9 HZ |
641 | static const struct amdgpu_gmc_funcs gmc_v10_0_gmc_funcs = { |
642 | .flush_gpu_tlb = gmc_v10_0_flush_gpu_tlb, | |
ea930000 | 643 | .flush_gpu_tlb_pasid = gmc_v10_0_flush_gpu_tlb_pasid, |
f9df67e9 HZ |
644 | .emit_flush_gpu_tlb = gmc_v10_0_emit_flush_gpu_tlb, |
645 | .emit_pasid_mapping = gmc_v10_0_emit_pasid_mapping, | |
71776b6d | 646 | .map_mtype = gmc_v10_0_map_mtype, |
cbfae36c | 647 | .get_vm_pde = gmc_v10_0_get_vm_pde, |
7348c20a AD |
648 | .get_vm_pte = gmc_v10_0_get_vm_pte, |
649 | .get_vbios_fb_size = gmc_v10_0_get_vbios_fb_size, | |
f9df67e9 HZ |
650 | }; |
651 | ||
652 | static void gmc_v10_0_set_gmc_funcs(struct amdgpu_device *adev) | |
653 | { | |
654 | if (adev->gmc.gmc_funcs == NULL) | |
655 | adev->gmc.gmc_funcs = &gmc_v10_0_gmc_funcs; | |
656 | } | |
657 | ||
01eee24f JC |
658 | static void gmc_v10_0_set_umc_funcs(struct amdgpu_device *adev) |
659 | { | |
660 | switch (adev->asic_type) { | |
661 | case CHIP_SIENNA_CICHLID: | |
662 | adev->umc.max_ras_err_cnt_per_query = UMC_V8_7_TOTAL_CHANNEL_NUM; | |
663 | adev->umc.channel_inst_num = UMC_V8_7_CHANNEL_INSTANCE_NUM; | |
664 | adev->umc.umc_inst_num = UMC_V8_7_UMC_INSTANCE_NUM; | |
665 | adev->umc.channel_offs = UMC_V8_7_PER_CHANNEL_OFFSET_SIENNA; | |
666 | adev->umc.channel_idx_tbl = &umc_v8_7_channel_idx_tbl[0][0]; | |
49070c4e | 667 | adev->umc.ras_funcs = &umc_v8_7_ras_funcs; |
01eee24f JC |
668 | break; |
669 | default: | |
670 | break; | |
671 | } | |
672 | } | |
673 | ||
9fb1506e OZ |
674 | |
675 | static void gmc_v10_0_set_mmhub_funcs(struct amdgpu_device *adev) | |
676 | { | |
4d8d75a4 HR |
677 | switch (adev->asic_type) { |
678 | case CHIP_VANGOGH: | |
c817cfa3 | 679 | case CHIP_YELLOW_CARP: |
4d8d75a4 HR |
680 | adev->mmhub.funcs = &mmhub_v2_3_funcs; |
681 | break; | |
682 | default: | |
683 | adev->mmhub.funcs = &mmhub_v2_0_funcs; | |
684 | break; | |
685 | } | |
9fb1506e OZ |
686 | } |
687 | ||
8ffff9b4 OZ |
688 | static void gmc_v10_0_set_gfxhub_funcs(struct amdgpu_device *adev) |
689 | { | |
690 | switch (adev->asic_type) { | |
691 | case CHIP_SIENNA_CICHLID: | |
692 | case CHIP_NAVY_FLOUNDER: | |
6405e627 | 693 | case CHIP_VANGOGH: |
3e02ad44 | 694 | case CHIP_DIMGREY_CAVEFISH: |
2d527ea6 | 695 | case CHIP_BEIGE_GOBY: |
c817cfa3 | 696 | case CHIP_YELLOW_CARP: |
8ffff9b4 OZ |
697 | adev->gfxhub.funcs = &gfxhub_v2_1_funcs; |
698 | break; | |
699 | default: | |
700 | adev->gfxhub.funcs = &gfxhub_v2_0_funcs; | |
701 | break; | |
702 | } | |
703 | } | |
704 | ||
705 | ||
f9df67e9 HZ |
706 | static int gmc_v10_0_early_init(void *handle) |
707 | { | |
708 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; | |
709 | ||
9fb1506e | 710 | gmc_v10_0_set_mmhub_funcs(adev); |
8ffff9b4 | 711 | gmc_v10_0_set_gfxhub_funcs(adev); |
f9df67e9 HZ |
712 | gmc_v10_0_set_gmc_funcs(adev); |
713 | gmc_v10_0_set_irq_funcs(adev); | |
01eee24f | 714 | gmc_v10_0_set_umc_funcs(adev); |
f9df67e9 HZ |
715 | |
716 | adev->gmc.shared_aperture_start = 0x2000000000000000ULL; | |
717 | adev->gmc.shared_aperture_end = | |
718 | adev->gmc.shared_aperture_start + (4ULL << 30) - 1; | |
719 | adev->gmc.private_aperture_start = 0x1000000000000000ULL; | |
720 | adev->gmc.private_aperture_end = | |
721 | adev->gmc.private_aperture_start + (4ULL << 30) - 1; | |
722 | ||
723 | return 0; | |
724 | } | |
725 | ||
726 | static int gmc_v10_0_late_init(void *handle) | |
727 | { | |
728 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; | |
5677c520 | 729 | int r; |
f9df67e9 | 730 | |
5677c520 AD |
731 | r = amdgpu_gmc_allocate_vm_inv_eng(adev); |
732 | if (r) | |
733 | return r; | |
f9df67e9 | 734 | |
0ad7a64d JC |
735 | r = amdgpu_gmc_ras_late_init(adev); |
736 | if (r) | |
737 | return r; | |
738 | ||
f9df67e9 HZ |
739 | return amdgpu_irq_get(adev, &adev->gmc.vm_fault, 0); |
740 | } | |
741 | ||
742 | static void gmc_v10_0_vram_gtt_location(struct amdgpu_device *adev, | |
743 | struct amdgpu_gmc *mc) | |
744 | { | |
745 | u64 base = 0; | |
746 | ||
8ffff9b4 | 747 | base = adev->gfxhub.funcs->get_fb_location(adev); |
f9df67e9 | 748 | |
fdb8483b JC |
749 | /* add the xgmi offset of the physical node */ |
750 | base += adev->gmc.xgmi.physical_node_id * adev->gmc.xgmi.node_segment_size; | |
751 | ||
f9df67e9 HZ |
752 | amdgpu_gmc_vram_location(adev, &adev->gmc, base); |
753 | amdgpu_gmc_gart_location(adev, mc); | |
99698b51 | 754 | amdgpu_gmc_agp_location(adev, mc); |
f9df67e9 HZ |
755 | |
756 | /* base offset of vram pages */ | |
8ffff9b4 | 757 | adev->vm_manager.vram_base_offset = adev->gfxhub.funcs->get_mc_fb_offset(adev); |
fdb8483b JC |
758 | |
759 | /* add the xgmi offset of the physical node */ | |
760 | adev->vm_manager.vram_base_offset += | |
761 | adev->gmc.xgmi.physical_node_id * adev->gmc.xgmi.node_segment_size; | |
f9df67e9 HZ |
762 | } |
763 | ||
764 | /** | |
765 | * gmc_v10_0_mc_init - initialize the memory controller driver params | |
766 | * | |
767 | * @adev: amdgpu_device pointer | |
768 | * | |
769 | * Look up the amount of vram, vram width, and decide how to place | |
770 | * vram and gart within the GPU's physical address space. | |
771 | * Returns 0 for success. | |
772 | */ | |
773 | static int gmc_v10_0_mc_init(struct amdgpu_device *adev) | |
774 | { | |
78b7dfd9 | 775 | int r; |
f9df67e9 HZ |
776 | |
777 | /* size in MB on si */ | |
778 | adev->gmc.mc_vram_size = | |
bebc0762 | 779 | adev->nbio.funcs->get_memsize(adev) * 1024ULL * 1024ULL; |
f9df67e9 | 780 | adev->gmc.real_vram_size = adev->gmc.mc_vram_size; |
78b7dfd9 AS |
781 | |
782 | if (!(adev->flags & AMD_IS_APU)) { | |
783 | r = amdgpu_device_resize_fb_bar(adev); | |
784 | if (r) | |
785 | return r; | |
786 | } | |
787 | adev->gmc.aper_base = pci_resource_start(adev->pdev, 0); | |
788 | adev->gmc.aper_size = pci_resource_len(adev->pdev, 0); | |
f9df67e9 | 789 | |
6405e627 HR |
790 | #ifdef CONFIG_X86_64 |
791 | if (adev->flags & AMD_IS_APU) { | |
792 | adev->gmc.aper_base = adev->gfxhub.funcs->get_mc_fb_offset(adev); | |
793 | adev->gmc.aper_size = adev->gmc.real_vram_size; | |
794 | } | |
795 | #endif | |
796 | ||
f9df67e9 | 797 | /* In case the PCI BAR is larger than the actual amount of vram */ |
78b7dfd9 | 798 | adev->gmc.visible_vram_size = adev->gmc.aper_size; |
f9df67e9 HZ |
799 | if (adev->gmc.visible_vram_size > adev->gmc.real_vram_size) |
800 | adev->gmc.visible_vram_size = adev->gmc.real_vram_size; | |
801 | ||
802 | /* set the gart size */ | |
803 | if (amdgpu_gart_size == -1) { | |
804 | switch (adev->asic_type) { | |
805 | case CHIP_NAVI10: | |
05d72b8d | 806 | case CHIP_NAVI14: |
4a0e815f | 807 | case CHIP_NAVI12: |
57d70602 | 808 | case CHIP_SIENNA_CICHLID: |
0287ac57 | 809 | case CHIP_NAVY_FLOUNDER: |
6405e627 | 810 | case CHIP_VANGOGH: |
a1435469 | 811 | case CHIP_DIMGREY_CAVEFISH: |
d2bfc50d | 812 | case CHIP_BEIGE_GOBY: |
c817cfa3 | 813 | case CHIP_YELLOW_CARP: |
9dbd8a12 | 814 | case CHIP_CYAN_SKILLFISH: |
f9df67e9 HZ |
815 | default: |
816 | adev->gmc.gart_size = 512ULL << 20; | |
817 | break; | |
818 | } | |
819 | } else | |
820 | adev->gmc.gart_size = (u64)amdgpu_gart_size << 20; | |
821 | ||
822 | gmc_v10_0_vram_gtt_location(adev, &adev->gmc); | |
823 | ||
824 | return 0; | |
825 | } | |
826 | ||
827 | static int gmc_v10_0_gart_init(struct amdgpu_device *adev) | |
828 | { | |
829 | int r; | |
830 | ||
831 | if (adev->gart.bo) { | |
832 | WARN(1, "NAVI10 PCIE GART already initialized\n"); | |
833 | return 0; | |
834 | } | |
835 | ||
836 | /* Initialize common gart structure */ | |
837 | r = amdgpu_gart_init(adev); | |
838 | if (r) | |
839 | return r; | |
840 | ||
841 | adev->gart.table_size = adev->gart.num_gpu_pages * 8; | |
842 | adev->gart.gart_pte_flags = AMDGPU_PTE_MTYPE_NV10(MTYPE_UC) | | |
843 | AMDGPU_PTE_EXECUTABLE; | |
844 | ||
845 | return amdgpu_gart_table_vram_alloc(adev); | |
846 | } | |
847 | ||
f9df67e9 HZ |
848 | static int gmc_v10_0_sw_init(void *handle) |
849 | { | |
ad02e08e | 850 | int r, vram_width = 0, vram_type = 0, vram_vendor = 0; |
f9df67e9 HZ |
851 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
852 | ||
8ffff9b4 | 853 | adev->gfxhub.funcs->init(adev); |
0b3df16b | 854 | |
9fb1506e | 855 | adev->mmhub.funcs->init(adev); |
f9df67e9 HZ |
856 | |
857 | spin_lock_init(&adev->gmc.invalidate_lock); | |
858 | ||
6405e627 HR |
859 | if ((adev->flags & AMD_IS_APU) && amdgpu_emu_mode == 1) { |
860 | adev->gmc.vram_type = AMDGPU_VRAM_TYPE_DDR4; | |
861 | adev->gmc.vram_width = 64; | |
862 | } else if (amdgpu_emu_mode == 1) { | |
0b3df16b | 863 | adev->gmc.vram_type = AMDGPU_VRAM_TYPE_GDDR6; |
631cdbd2 | 864 | adev->gmc.vram_width = 1 * 128; /* numchan * chansize */ |
0b3df16b LG |
865 | } else { |
866 | r = amdgpu_atomfirmware_get_vram_info(adev, | |
867 | &vram_width, &vram_type, &vram_vendor); | |
868 | adev->gmc.vram_width = vram_width; | |
869 | ||
870 | adev->gmc.vram_type = vram_type; | |
871 | adev->gmc.vram_vendor = vram_vendor; | |
872 | } | |
631cdbd2 | 873 | |
f9df67e9 HZ |
874 | switch (adev->asic_type) { |
875 | case CHIP_NAVI10: | |
05d72b8d | 876 | case CHIP_NAVI14: |
4a0e815f | 877 | case CHIP_NAVI12: |
57d70602 | 878 | case CHIP_SIENNA_CICHLID: |
0287ac57 | 879 | case CHIP_NAVY_FLOUNDER: |
6405e627 | 880 | case CHIP_VANGOGH: |
a1435469 | 881 | case CHIP_DIMGREY_CAVEFISH: |
d2bfc50d | 882 | case CHIP_BEIGE_GOBY: |
c817cfa3 | 883 | case CHIP_YELLOW_CARP: |
9dbd8a12 | 884 | case CHIP_CYAN_SKILLFISH: |
1daa2bfa | 885 | adev->num_vmhubs = 2; |
f9df67e9 HZ |
886 | /* |
887 | * To fulfill 4-level page support, | |
4a0e815f | 888 | * vm size is 256TB (48bit), maximum size of Navi10/Navi14/Navi12, |
f9df67e9 HZ |
889 | * block size 512 (9bit) |
890 | */ | |
891 | amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48); | |
892 | break; | |
893 | default: | |
894 | break; | |
895 | } | |
896 | ||
897 | /* This interrupt is VMC page fault.*/ | |
898 | r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VMC, | |
899 | VMC_1_0__SRCID__VM_FAULT, | |
900 | &adev->gmc.vm_fault); | |
5021e9a8 ND |
901 | |
902 | if (r) | |
903 | return r; | |
904 | ||
f9df67e9 HZ |
905 | r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_UTCL2, |
906 | UTCL2_1_0__SRCID__FAULT, | |
907 | &adev->gmc.vm_fault); | |
908 | if (r) | |
909 | return r; | |
910 | ||
01eee24f JC |
911 | if (!amdgpu_sriov_vf(adev)) { |
912 | /* interrupt sent to DF. */ | |
913 | r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DF, 0, | |
914 | &adev->gmc.ecc_irq); | |
915 | if (r) | |
916 | return r; | |
917 | } | |
918 | ||
f9df67e9 HZ |
919 | /* |
920 | * Set the internal MC address mask This is the max address of the GPU's | |
921 | * internal address space. | |
922 | */ | |
923 | adev->gmc.mc_mask = 0xffffffffffffULL; /* 48 bit MC */ | |
924 | ||
244511f3 | 925 | r = dma_set_mask_and_coherent(adev->dev, DMA_BIT_MASK(44)); |
f9df67e9 | 926 | if (r) { |
f9df67e9 | 927 | printk(KERN_WARNING "amdgpu: No suitable DMA available.\n"); |
244511f3 | 928 | return r; |
f9df67e9 HZ |
929 | } |
930 | ||
fdb8483b | 931 | if (adev->gmc.xgmi.supported) { |
8ffff9b4 | 932 | r = adev->gfxhub.funcs->get_xgmi_info(adev); |
fdb8483b JC |
933 | if (r) |
934 | return r; | |
935 | } | |
936 | ||
f9df67e9 HZ |
937 | r = gmc_v10_0_mc_init(adev); |
938 | if (r) | |
939 | return r; | |
940 | ||
7348c20a | 941 | amdgpu_gmc_get_vbios_allocations(adev); |
e15a5fb9 | 942 | amdgpu_gmc_get_reserved_allocation(adev); |
f9df67e9 HZ |
943 | |
944 | /* Memory manager */ | |
945 | r = amdgpu_bo_init(adev); | |
946 | if (r) | |
947 | return r; | |
948 | ||
949 | r = gmc_v10_0_gart_init(adev); | |
950 | if (r) | |
951 | return r; | |
952 | ||
953 | /* | |
954 | * number of VMs | |
955 | * VMID 0 is reserved for System | |
956 | * amdgpu graphics/compute will use VMIDs 1-7 | |
957 | * amdkfd will use VMIDs 8-15 | |
958 | */ | |
40111ec2 | 959 | adev->vm_manager.first_kfd_vmid = 8; |
f9df67e9 HZ |
960 | |
961 | amdgpu_vm_manager_init(adev); | |
962 | ||
963 | return 0; | |
964 | } | |
965 | ||
966 | /** | |
2cce318c | 967 | * gmc_v10_0_gart_fini - vm fini callback |
f9df67e9 HZ |
968 | * |
969 | * @adev: amdgpu_device pointer | |
970 | * | |
971 | * Tears down the driver GART/VM setup (CIK). | |
972 | */ | |
973 | static void gmc_v10_0_gart_fini(struct amdgpu_device *adev) | |
974 | { | |
975 | amdgpu_gart_table_vram_free(adev); | |
f9df67e9 HZ |
976 | } |
977 | ||
978 | static int gmc_v10_0_sw_fini(void *handle) | |
979 | { | |
980 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; | |
981 | ||
982 | amdgpu_vm_manager_fini(adev); | |
983 | gmc_v10_0_gart_fini(adev); | |
984 | amdgpu_gem_force_release(adev); | |
985 | amdgpu_bo_fini(adev); | |
986 | ||
987 | return 0; | |
988 | } | |
989 | ||
990 | static void gmc_v10_0_init_golden_registers(struct amdgpu_device *adev) | |
991 | { | |
992 | switch (adev->asic_type) { | |
993 | case CHIP_NAVI10: | |
05d72b8d | 994 | case CHIP_NAVI14: |
4a0e815f | 995 | case CHIP_NAVI12: |
57d70602 | 996 | case CHIP_SIENNA_CICHLID: |
0287ac57 | 997 | case CHIP_NAVY_FLOUNDER: |
6405e627 | 998 | case CHIP_VANGOGH: |
a1435469 | 999 | case CHIP_DIMGREY_CAVEFISH: |
d2bfc50d | 1000 | case CHIP_BEIGE_GOBY: |
c817cfa3 | 1001 | case CHIP_YELLOW_CARP: |
9dbd8a12 | 1002 | case CHIP_CYAN_SKILLFISH: |
f9df67e9 HZ |
1003 | break; |
1004 | default: | |
1005 | break; | |
1006 | } | |
1007 | } | |
1008 | ||
1009 | /** | |
1010 | * gmc_v10_0_gart_enable - gart enable | |
1011 | * | |
1012 | * @adev: amdgpu_device pointer | |
1013 | */ | |
1014 | static int gmc_v10_0_gart_enable(struct amdgpu_device *adev) | |
1015 | { | |
1016 | int r; | |
1017 | bool value; | |
f9df67e9 HZ |
1018 | |
1019 | if (adev->gart.bo == NULL) { | |
1020 | dev_err(adev->dev, "No VRAM object for PCIE GART.\n"); | |
1021 | return -EINVAL; | |
1022 | } | |
1023 | ||
1024 | r = amdgpu_gart_table_vram_pin(adev); | |
1025 | if (r) | |
1026 | return r; | |
1027 | ||
8ffff9b4 | 1028 | r = adev->gfxhub.funcs->gart_enable(adev); |
f9df67e9 HZ |
1029 | if (r) |
1030 | return r; | |
1031 | ||
9fb1506e | 1032 | r = adev->mmhub.funcs->gart_enable(adev); |
f9df67e9 HZ |
1033 | if (r) |
1034 | return r; | |
1035 | ||
bf087285 | 1036 | adev->hdp.funcs->init_registers(adev); |
f9df67e9 HZ |
1037 | |
1038 | /* Flush HDP after it is initialized */ | |
bf087285 | 1039 | adev->hdp.funcs->flush_hdp(adev, NULL); |
f9df67e9 HZ |
1040 | |
1041 | value = (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS) ? | |
1042 | false : true; | |
1043 | ||
8ffff9b4 | 1044 | adev->gfxhub.funcs->set_fault_enable_default(adev, value); |
9fb1506e | 1045 | adev->mmhub.funcs->set_fault_enable_default(adev, value); |
3ff98548 OZ |
1046 | gmc_v10_0_flush_gpu_tlb(adev, 0, AMDGPU_MMHUB_0, 0); |
1047 | gmc_v10_0_flush_gpu_tlb(adev, 0, AMDGPU_GFXHUB_0, 0); | |
f9df67e9 HZ |
1048 | |
1049 | DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n", | |
1050 | (unsigned)(adev->gmc.gart_size >> 20), | |
1051 | (unsigned long long)amdgpu_bo_gpu_offset(adev->gart.bo)); | |
1052 | ||
1053 | adev->gart.ready = true; | |
1054 | ||
1055 | return 0; | |
1056 | } | |
1057 | ||
1058 | static int gmc_v10_0_hw_init(void *handle) | |
1059 | { | |
1060 | int r; | |
1061 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; | |
1062 | ||
1063 | /* The sequence of these two function calls matters.*/ | |
1064 | gmc_v10_0_init_golden_registers(adev); | |
1065 | ||
b3accd6f XH |
1066 | /* |
1067 | * harvestable groups in gc_utcl2 need to be programmed before any GFX block | |
1068 | * register setup within GMC, or else system hang when harvesting SA. | |
1069 | */ | |
1070 | if (adev->gfxhub.funcs && adev->gfxhub.funcs->utcl2_harvest) | |
1071 | adev->gfxhub.funcs->utcl2_harvest(adev); | |
1072 | ||
f9df67e9 HZ |
1073 | r = gmc_v10_0_gart_enable(adev); |
1074 | if (r) | |
1075 | return r; | |
1076 | ||
01eee24f JC |
1077 | if (adev->umc.funcs && adev->umc.funcs->init_registers) |
1078 | adev->umc.funcs->init_registers(adev); | |
1079 | ||
f9df67e9 HZ |
1080 | return 0; |
1081 | } | |
1082 | ||
1083 | /** | |
1084 | * gmc_v10_0_gart_disable - gart disable | |
1085 | * | |
1086 | * @adev: amdgpu_device pointer | |
1087 | * | |
1088 | * This disables all VM page table. | |
1089 | */ | |
1090 | static void gmc_v10_0_gart_disable(struct amdgpu_device *adev) | |
1091 | { | |
8ffff9b4 | 1092 | adev->gfxhub.funcs->gart_disable(adev); |
9fb1506e | 1093 | adev->mmhub.funcs->gart_disable(adev); |
f9df67e9 HZ |
1094 | amdgpu_gart_table_vram_unpin(adev); |
1095 | } | |
1096 | ||
1097 | static int gmc_v10_0_hw_fini(void *handle) | |
1098 | { | |
1099 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; | |
1100 | ||
66805763 LS |
1101 | gmc_v10_0_gart_disable(adev); |
1102 | ||
f9df67e9 HZ |
1103 | if (amdgpu_sriov_vf(adev)) { |
1104 | /* full access mode, so don't touch any GMC register */ | |
1105 | DRM_DEBUG("For SRIOV client, shouldn't do anything.\n"); | |
1106 | return 0; | |
1107 | } | |
1108 | ||
01eee24f | 1109 | amdgpu_irq_put(adev, &adev->gmc.ecc_irq, 0); |
f9df67e9 | 1110 | amdgpu_irq_put(adev, &adev->gmc.vm_fault, 0); |
f9df67e9 HZ |
1111 | |
1112 | return 0; | |
1113 | } | |
1114 | ||
1115 | static int gmc_v10_0_suspend(void *handle) | |
1116 | { | |
1117 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; | |
1118 | ||
1119 | gmc_v10_0_hw_fini(adev); | |
1120 | ||
1121 | return 0; | |
1122 | } | |
1123 | ||
1124 | static int gmc_v10_0_resume(void *handle) | |
1125 | { | |
1126 | int r; | |
1127 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; | |
1128 | ||
1129 | r = gmc_v10_0_hw_init(adev); | |
1130 | if (r) | |
1131 | return r; | |
1132 | ||
1133 | amdgpu_vmid_reset_all(adev); | |
1134 | ||
1135 | return 0; | |
1136 | } | |
1137 | ||
1138 | static bool gmc_v10_0_is_idle(void *handle) | |
1139 | { | |
1140 | /* MC is always ready in GMC v10.*/ | |
1141 | return true; | |
1142 | } | |
1143 | ||
1144 | static int gmc_v10_0_wait_for_idle(void *handle) | |
1145 | { | |
1146 | /* There is no need to wait for MC idle in GMC v10.*/ | |
1147 | return 0; | |
1148 | } | |
1149 | ||
1150 | static int gmc_v10_0_soft_reset(void *handle) | |
1151 | { | |
1152 | return 0; | |
1153 | } | |
1154 | ||
1155 | static int gmc_v10_0_set_clockgating_state(void *handle, | |
1156 | enum amd_clockgating_state state) | |
1157 | { | |
1158 | int r; | |
1159 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; | |
1160 | ||
9fb1506e | 1161 | r = adev->mmhub.funcs->set_clockgating(adev, state); |
f9df67e9 HZ |
1162 | if (r) |
1163 | return r; | |
1164 | ||
f267242e | 1165 | if (adev->asic_type >= CHIP_SIENNA_CICHLID && |
c817cfa3 | 1166 | adev->asic_type <= CHIP_YELLOW_CARP) |
920a4cd3 LG |
1167 | return athub_v2_1_set_clockgating(adev, state); |
1168 | else | |
1169 | return athub_v2_0_set_clockgating(adev, state); | |
f9df67e9 HZ |
1170 | } |
1171 | ||
1172 | static void gmc_v10_0_get_clockgating_state(void *handle, u32 *flags) | |
1173 | { | |
1174 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; | |
1175 | ||
9fb1506e | 1176 | adev->mmhub.funcs->get_clockgating(adev, flags); |
f9df67e9 | 1177 | |
f267242e | 1178 | if (adev->asic_type >= CHIP_SIENNA_CICHLID && |
c817cfa3 | 1179 | adev->asic_type <= CHIP_YELLOW_CARP) |
920a4cd3 LG |
1180 | athub_v2_1_get_clockgating(adev, flags); |
1181 | else | |
1182 | athub_v2_0_get_clockgating(adev, flags); | |
f9df67e9 HZ |
1183 | } |
1184 | ||
1185 | static int gmc_v10_0_set_powergating_state(void *handle, | |
1186 | enum amd_powergating_state state) | |
1187 | { | |
1188 | return 0; | |
1189 | } | |
1190 | ||
1191 | const struct amd_ip_funcs gmc_v10_0_ip_funcs = { | |
1192 | .name = "gmc_v10_0", | |
1193 | .early_init = gmc_v10_0_early_init, | |
1194 | .late_init = gmc_v10_0_late_init, | |
1195 | .sw_init = gmc_v10_0_sw_init, | |
1196 | .sw_fini = gmc_v10_0_sw_fini, | |
1197 | .hw_init = gmc_v10_0_hw_init, | |
1198 | .hw_fini = gmc_v10_0_hw_fini, | |
1199 | .suspend = gmc_v10_0_suspend, | |
1200 | .resume = gmc_v10_0_resume, | |
1201 | .is_idle = gmc_v10_0_is_idle, | |
1202 | .wait_for_idle = gmc_v10_0_wait_for_idle, | |
1203 | .soft_reset = gmc_v10_0_soft_reset, | |
1204 | .set_clockgating_state = gmc_v10_0_set_clockgating_state, | |
1205 | .set_powergating_state = gmc_v10_0_set_powergating_state, | |
1206 | .get_clockgating_state = gmc_v10_0_get_clockgating_state, | |
1207 | }; | |
1208 | ||
1209 | const struct amdgpu_ip_block_version gmc_v10_0_ip_block = | |
1210 | { | |
1211 | .type = AMD_IP_BLOCK_TYPE_GMC, | |
1212 | .major = 10, | |
1213 | .minor = 0, | |
1214 | .rev = 0, | |
1215 | .funcs = &gmc_v10_0_ip_funcs, | |
1216 | }; |