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drm/amd/display: Fix regression in dce110_apply_ctx_for_surfaces
[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / amd / display / amdgpu_dm / amdgpu_dm.c
CommitLineData
4562236b
HW		 1/*
2 * Copyright 2015 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26#include "dm_services_types.h"
27#include "dc.h"
28
29#include "vid.h"
30#include "amdgpu.h"
a49dcb88 31#include "amdgpu_display.h"
4562236b
HW		 32#include "atom.h"
33#include "amdgpu_dm.h"
e7b07cee 34#include "amdgpu_pm.h"
4562236b
HW		 35
36#include "amd_shared.h"
37#include "amdgpu_dm_irq.h"
38#include "dm_helpers.h"
e7b07cee
HW		 39#include "dm_services_types.h"
40#include "amdgpu_dm_mst_types.h"
4562236b
HW		 41
42#include "ivsrcid/ivsrcid_vislands30.h"
43
44#include <linux/module.h>
45#include <linux/moduleparam.h>
46#include <linux/version.h>
e7b07cee 47#include <linux/types.h>
4562236b 48
e7b07cee 49#include <drm/drmP.h>
4562236b
HW		 50#include <drm/drm_atomic.h>
51#include <drm/drm_atomic_helper.h>
52#include <drm/drm_dp_mst_helper.h>
e7b07cee
HW		 53#include <drm/drm_fb_helper.h>
54#include <drm/drm_edid.h>
4562236b
HW		 55
56#include "modules/inc/mod_freesync.h"
57
ff5ef992
AD		 58#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
59#include "ivsrcid/irqsrcs_dcn_1_0.h"
60
61#include "raven1/DCN/dcn_1_0_offset.h"
62#include "raven1/DCN/dcn_1_0_sh_mask.h"
63#include "vega10/soc15ip.h"
64
65#include "soc15_common.h"
66#endif
67
e7b07cee
HW		 68#include "modules/inc/mod_freesync.h"
69
70#include "i2caux_interface.h"
71
72
3be5262e 73static enum drm_plane_type dm_plane_type_default[AMDGPU_MAX_PLANES] = {
d4e13b0d
AD		 74 DRM_PLANE_TYPE_PRIMARY,
75 DRM_PLANE_TYPE_PRIMARY,
76 DRM_PLANE_TYPE_PRIMARY,
77 DRM_PLANE_TYPE_PRIMARY,
78 DRM_PLANE_TYPE_PRIMARY,
79 DRM_PLANE_TYPE_PRIMARY,
80};
81
3be5262e 82static enum drm_plane_type dm_plane_type_carizzo[AMDGPU_MAX_PLANES] = {
d4e13b0d
AD		 83 DRM_PLANE_TYPE_PRIMARY,
84 DRM_PLANE_TYPE_PRIMARY,
85 DRM_PLANE_TYPE_PRIMARY,
86 DRM_PLANE_TYPE_OVERLAY,/* YUV Capable Underlay */
87};
88
3be5262e 89static enum drm_plane_type dm_plane_type_stoney[AMDGPU_MAX_PLANES] = {
d4e13b0d
AD		 90 DRM_PLANE_TYPE_PRIMARY,
91 DRM_PLANE_TYPE_PRIMARY,
92 DRM_PLANE_TYPE_OVERLAY, /* YUV Capable Underlay */
93};
94
4562236b
HW		 95/*
96 * dm_vblank_get_counter
97 *
98 * @brief
99 * Get counter for number of vertical blanks
100 *
101 * @param
102 * struct amdgpu_device *adev - [in] desired amdgpu device
103 * int disp_idx - [in] which CRTC to get the counter from
104 *
105 * @return
106 * Counter for vertical blanks
107 */
108static u32 dm_vblank_get_counter(struct amdgpu_device *adev, int crtc)
109{
110 if (crtc >= adev->mode_info.num_crtc)
111 return 0;
112 else {
113 struct amdgpu_crtc *acrtc = adev->mode_info.crtcs[crtc];
da5c47f6
AG		 114 struct dm_crtc_state *acrtc_state = to_dm_crtc_state(
115 acrtc->base.state);
4562236b 116
da5c47f6
AG		 117
118 if (acrtc_state->stream == NULL) {
0971c40e
HW		 119 DRM_ERROR("dc_stream_state is NULL for crtc '%d'!\n",
120 crtc);
4562236b
HW		 121 return 0;
122 }
123
da5c47f6 124 return dc_stream_get_vblank_counter(acrtc_state->stream);
4562236b
HW		 125 }
126}
127
128static int dm_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc,
129 u32 *vbl, u32 *position)
130{
81c50963
ST		 131 uint32_t v_blank_start, v_blank_end, h_position, v_position;
132
4562236b
HW		 133 if ((crtc < 0) || (crtc >= adev->mode_info.num_crtc))
134 return -EINVAL;
135 else {
136 struct amdgpu_crtc *acrtc = adev->mode_info.crtcs[crtc];
da5c47f6
AG		 137 struct dm_crtc_state *acrtc_state = to_dm_crtc_state(
138 acrtc->base.state);
4562236b 139
da5c47f6 140 if (acrtc_state->stream == NULL) {
0971c40e
HW		 141 DRM_ERROR("dc_stream_state is NULL for crtc '%d'!\n",
142 crtc);
4562236b
HW		 143 return 0;
144 }
145
81c50963
ST		 146 /*
147 * TODO rework base driver to use values directly.
148 * for now parse it back into reg-format
149 */
da5c47f6 150 dc_stream_get_scanoutpos(acrtc_state->stream,
81c50963
ST		 151 &v_blank_start,
152 &v_blank_end,
153 &h_position,
154 &v_position);
155
e806208d
AG		 156 *position = v_position | (h_position << 16);
157 *vbl = v_blank_start | (v_blank_end << 16);
4562236b
HW		 158 }
159
160 return 0;
161}
162
163static bool dm_is_idle(void *handle)
164{
165 /* XXX todo */
166 return true;
167}
168
169static int dm_wait_for_idle(void *handle)
170{
171 /* XXX todo */
172 return 0;
173}
174
175static bool dm_check_soft_reset(void *handle)
176{
177 return false;
178}
179
180static int dm_soft_reset(void *handle)
181{
182 /* XXX todo */
183 return 0;
184}
185
186static struct amdgpu_crtc *get_crtc_by_otg_inst(
187 struct amdgpu_device *adev,
188 int otg_inst)
189{
190 struct drm_device *dev = adev->ddev;
191 struct drm_crtc *crtc;
192 struct amdgpu_crtc *amdgpu_crtc;
193
194 /*
195 * following if is check inherited from both functions where this one is
196 * used now. Need to be checked why it could happen.
197 */
198 if (otg_inst == -1) {
199 WARN_ON(1);
200 return adev->mode_info.crtcs[0];
201 }
202
203 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
204 amdgpu_crtc = to_amdgpu_crtc(crtc);
205
206 if (amdgpu_crtc->otg_inst == otg_inst)
207 return amdgpu_crtc;
208 }
209
210 return NULL;
211}
212
213static void dm_pflip_high_irq(void *interrupt_params)
214{
4562236b
HW		 215 struct amdgpu_crtc *amdgpu_crtc;
216 struct common_irq_params *irq_params = interrupt_params;
217 struct amdgpu_device *adev = irq_params->adev;
218 unsigned long flags;
219
220 amdgpu_crtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_PFLIP);
221
222 /* IRQ could occur when in initial stage */
223 /*TODO work and BO cleanup */
224 if (amdgpu_crtc == NULL) {
225 DRM_DEBUG_DRIVER("CRTC is null, returning.\n");
226 return;
227 }
228
229 spin_lock_irqsave(&adev->ddev->event_lock, flags);
4562236b
HW		 230
231 if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED){
232 DRM_DEBUG_DRIVER("amdgpu_crtc->pflip_status = %d !=AMDGPU_FLIP_SUBMITTED(%d) on crtc:%d[%p] \n",
233 amdgpu_crtc->pflip_status,
234 AMDGPU_FLIP_SUBMITTED,
235 amdgpu_crtc->crtc_id,
236 amdgpu_crtc);
237 spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
238 return;
239 }
240
4562236b
HW		 241
242 /* wakeup usersapce */
1159898a 243 if (amdgpu_crtc->event) {
753c66c9
MK		 244 /* Update to correct count/ts if racing with vblank irq */
245 drm_crtc_accurate_vblank_count(&amdgpu_crtc->base);
246
54f5499a 247 drm_crtc_send_vblank_event(&amdgpu_crtc->base, amdgpu_crtc->event);
1159898a 248
54f5499a
AG		 249 /* page flip completed. clean up */
250 amdgpu_crtc->event = NULL;
1159898a 251
54f5499a
AG		 252 } else
253 WARN_ON(1);
4562236b 254
54f5499a 255 amdgpu_crtc->pflip_status = AMDGPU_FLIP_NONE;
4562236b
HW		 256 spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
257
54f5499a
AG		 258 DRM_DEBUG_DRIVER("%s - crtc :%d[%p], pflip_stat:AMDGPU_FLIP_NONE\n",
259 __func__, amdgpu_crtc->crtc_id, amdgpu_crtc);
4562236b
HW		 260
261 drm_crtc_vblank_put(&amdgpu_crtc->base);
4562236b
HW		 262}
263
264static void dm_crtc_high_irq(void *interrupt_params)
265{
266 struct common_irq_params *irq_params = interrupt_params;
267 struct amdgpu_device *adev = irq_params->adev;
268 uint8_t crtc_index = 0;
269 struct amdgpu_crtc *acrtc;
270
b57de80a 271 acrtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_VBLANK);
4562236b
HW		 272
273 if (acrtc)
274 crtc_index = acrtc->crtc_id;
275
276 drm_handle_vblank(adev->ddev, crtc_index);
277}
278
279static int dm_set_clockgating_state(void *handle,
280 enum amd_clockgating_state state)
281{
282 return 0;
283}
284
285static int dm_set_powergating_state(void *handle,
286 enum amd_powergating_state state)
287{
288 return 0;
289}
290
291/* Prototypes of private functions */
292static int dm_early_init(void* handle);
293
294static void hotplug_notify_work_func(struct work_struct *work)
295{
296 struct amdgpu_display_manager *dm = container_of(work, struct amdgpu_display_manager, mst_hotplug_work);
297 struct drm_device *dev = dm->ddev;
298
299 drm_kms_helper_hotplug_event(dev);
300}
301
a32e24b4
RL		 302#ifdef ENABLE_FBC
303#include "dal_asic_id.h"
304/* Allocate memory for FBC compressed data */
305/* TODO: Dynamic allocation */
306#define AMDGPU_FBC_SIZE (3840 * 2160 * 4)
307
308void amdgpu_dm_initialize_fbc(struct amdgpu_device *adev)
309{
310 int r;
311 struct dm_comressor_info *compressor = &adev->dm.compressor;
312
313 if (!compressor->bo_ptr) {
314 r = amdgpu_bo_create_kernel(adev, AMDGPU_FBC_SIZE, PAGE_SIZE,
315 AMDGPU_GEM_DOMAIN_VRAM, &compressor->bo_ptr,
316 &compressor->gpu_addr, &compressor->cpu_addr);
317
318 if (r)
319 DRM_ERROR("DM: Failed to initialize fbc\n");
320 }
321
322}
323#endif
324
325
4562236b
HW		 326/* Init display KMS
327 *
328 * Returns 0 on success
329 */
330int amdgpu_dm_init(struct amdgpu_device *adev)
331{
332 struct dc_init_data init_data;
333 adev->dm.ddev = adev->ddev;
334 adev->dm.adev = adev;
335
336 DRM_INFO("DAL is enabled\n");
337 /* Zero all the fields */
338 memset(&init_data, 0, sizeof(init_data));
339
340 /* initialize DAL's lock (for SYNC context use) */
341 spin_lock_init(&adev->dm.dal_lock);
342
343 /* initialize DAL's mutex */
344 mutex_init(&adev->dm.dal_mutex);
345
346 if(amdgpu_dm_irq_init(adev)) {
347 DRM_ERROR("amdgpu: failed to initialize DM IRQ support.\n");
348 goto error;
349 }
350
351 init_data.asic_id.chip_family = adev->family;
352
353 init_data.asic_id.pci_revision_id = adev->rev_id;
354 init_data.asic_id.hw_internal_rev = adev->external_rev_id;
355
356 init_data.asic_id.vram_width = adev->mc.vram_width;
357 /* TODO: initialize init_data.asic_id.vram_type here!!!! */
358 init_data.asic_id.atombios_base_address =
359 adev->mode_info.atom_context->bios;
360
361 init_data.driver = adev;
362
363 adev->dm.cgs_device = amdgpu_cgs_create_device(adev);
364
365 if (!adev->dm.cgs_device) {
366 DRM_ERROR("amdgpu: failed to create cgs device.\n");
367 goto error;
368 }
369
370 init_data.cgs_device = adev->dm.cgs_device;
371
372 adev->dm.dal = NULL;
373
374 init_data.dce_environment = DCE_ENV_PRODUCTION_DRV;
375
a32e24b4
RL		 376#ifdef ENABLE_FBC
377 if (adev->family == FAMILY_CZ)
378 amdgpu_dm_initialize_fbc(adev);
379 init_data.fbc_gpu_addr = adev->dm.compressor.gpu_addr;
380#endif
4562236b
HW		 381 /* Display Core create. */
382 adev->dm.dc = dc_create(&init_data);
383
384 if (!adev->dm.dc)
385 DRM_INFO("Display Core failed to initialize!\n");
386
387 INIT_WORK(&adev->dm.mst_hotplug_work, hotplug_notify_work_func);
388
389 adev->dm.freesync_module = mod_freesync_create(adev->dm.dc);
390 if (!adev->dm.freesync_module) {
391 DRM_ERROR(
392 "amdgpu: failed to initialize freesync_module.\n");
393 } else
394 DRM_INFO("amdgpu: freesync_module init done %p.\n",
395 adev->dm.freesync_module);
396
397 if (amdgpu_dm_initialize_drm_device(adev)) {
398 DRM_ERROR(
399 "amdgpu: failed to initialize sw for display support.\n");
400 goto error;
401 }
402
403 /* Update the actual used number of crtc */
404 adev->mode_info.num_crtc = adev->dm.display_indexes_num;
405
406 /* TODO: Add_display_info? */
407
408 /* TODO use dynamic cursor width */
ce75805e
AG		 409 adev->ddev->mode_config.cursor_width = adev->dm.dc->caps.max_cursor_size;
410 adev->ddev->mode_config.cursor_height = adev->dm.dc->caps.max_cursor_size;
4562236b
HW		 411
412 if (drm_vblank_init(adev->ddev, adev->dm.display_indexes_num)) {
413 DRM_ERROR(
414 "amdgpu: failed to initialize sw for display support.\n");
415 goto error;
416 }
417
418 DRM_INFO("KMS initialized.\n");
419
420 return 0;
421error:
422 amdgpu_dm_fini(adev);
423
424 return -1;
425}
426
427void amdgpu_dm_fini(struct amdgpu_device *adev)
428{
429 amdgpu_dm_destroy_drm_device(&adev->dm);
430 /*
431 * TODO: pageflip, vlank interrupt
432 *
433 * amdgpu_dm_irq_fini(adev);
434 */
435
436 if (adev->dm.cgs_device) {
437 amdgpu_cgs_destroy_device(adev->dm.cgs_device);
438 adev->dm.cgs_device = NULL;
439 }
440 if (adev->dm.freesync_module) {
441 mod_freesync_destroy(adev->dm.freesync_module);
442 adev->dm.freesync_module = NULL;
443 }
444 /* DC Destroy TODO: Replace destroy DAL */
21de3396 445 if (adev->dm.dc)
4562236b 446 dc_destroy(&adev->dm.dc);
4562236b
HW		 447 return;
448}
449
450/* moved from amdgpu_dm_kms.c */
451void amdgpu_dm_destroy()
452{
453}
454
455static int dm_sw_init(void *handle)
456{
457 return 0;
458}
459
460static int dm_sw_fini(void *handle)
461{
462 return 0;
463}
464
7abcf6b5 465static int detect_mst_link_for_all_connectors(struct drm_device *dev)
4562236b
HW		 466{
467 struct amdgpu_connector *aconnector;
468 struct drm_connector *connector;
7abcf6b5 469 int ret = 0;
4562236b
HW		 470
471 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
472
473 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
474 aconnector = to_amdgpu_connector(connector);
7abcf6b5
AG		 475 if (aconnector->dc_link->type == dc_connection_mst_branch) {
476 DRM_INFO("DM_MST: starting TM on aconnector: %p [id: %d]\n",
477 aconnector, aconnector->base.base.id);
478
479 ret = drm_dp_mst_topology_mgr_set_mst(&aconnector->mst_mgr, true);
480 if (ret < 0) {
481 DRM_ERROR("DM_MST: Failed to start MST\n");
482 ((struct dc_link *)aconnector->dc_link)->type = dc_connection_single;
483 return ret;
4562236b 484 }
7abcf6b5 485 }
4562236b
HW		 486 }
487
488 drm_modeset_unlock(&dev->mode_config.connection_mutex);
7abcf6b5
AG		 489 return ret;
490}
491
492static int dm_late_init(void *handle)
493{
494 struct drm_device *dev = ((struct amdgpu_device *)handle)->ddev;
495 int r = detect_mst_link_for_all_connectors(dev);
496
497 return r;
4562236b
HW		 498}
499
500static void s3_handle_mst(struct drm_device *dev, bool suspend)
501{
502 struct amdgpu_connector *aconnector;
503 struct drm_connector *connector;
504
505 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
506
507 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
508 aconnector = to_amdgpu_connector(connector);
509 if (aconnector->dc_link->type == dc_connection_mst_branch &&
510 !aconnector->mst_port) {
511
512 if (suspend)
513 drm_dp_mst_topology_mgr_suspend(&aconnector->mst_mgr);
514 else
515 drm_dp_mst_topology_mgr_resume(&aconnector->mst_mgr);
516 }
517 }
518
519 drm_modeset_unlock(&dev->mode_config.connection_mutex);
520}
521
522static int dm_hw_init(void *handle)
523{
524 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
525 /* Create DAL display manager */
526 amdgpu_dm_init(adev);
4562236b
HW		 527 amdgpu_dm_hpd_init(adev);
528
4562236b
HW		 529 return 0;
530}
531
532static int dm_hw_fini(void *handle)
533{
534 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
535
536 amdgpu_dm_hpd_fini(adev);
537
538 amdgpu_dm_irq_fini(adev);
21de3396 539 amdgpu_dm_fini(adev);
4562236b
HW		 540 return 0;
541}
542
543static int dm_suspend(void *handle)
544{
545 struct amdgpu_device *adev = handle;
546 struct amdgpu_display_manager *dm = &adev->dm;
547 int ret = 0;
4562236b
HW		 548
549 s3_handle_mst(adev->ddev, true);
550
4562236b
HW		 551 amdgpu_dm_irq_suspend(adev);
552
0a214e2f 553 WARN_ON(adev->dm.cached_state);
a3621485
AG		 554 adev->dm.cached_state = drm_atomic_helper_suspend(adev->ddev);
555
4562236b
HW		 556 dc_set_power_state(
557 dm->dc,
a3621485
AG		 558 DC_ACPI_CM_POWER_STATE_D3
559 );
4562236b
HW		 560
561 return ret;
562}
563
564struct amdgpu_connector *amdgpu_dm_find_first_crct_matching_connector(
565 struct drm_atomic_state *state,
566 struct drm_crtc *crtc,
567 bool from_state_var)
568{
569 uint32_t i;
570 struct drm_connector_state *conn_state;
571 struct drm_connector *connector;
572 struct drm_crtc *crtc_from_state;
573
574 for_each_connector_in_state(
575 state,
576 connector,
577 conn_state,
578 i) {
579 crtc_from_state =
580 from_state_var ?
581 conn_state->crtc :
582 connector->state->crtc;
583
584 if (crtc_from_state == crtc)
585 return to_amdgpu_connector(connector);
586 }
587
588 return NULL;
589}
590
4562236b
HW		 591static int dm_resume(void *handle)
592{
593 struct amdgpu_device *adev = handle;
594 struct amdgpu_display_manager *dm = &adev->dm;
595
596 /* power on hardware */
597 dc_set_power_state(
598 dm->dc,
a3621485
AG		 599 DC_ACPI_CM_POWER_STATE_D0
600 );
4562236b
HW		 601
602 return 0;
603}
604
605int amdgpu_dm_display_resume(struct amdgpu_device *adev )
606{
607 struct drm_device *ddev = adev->ddev;
608 struct amdgpu_display_manager *dm = &adev->dm;
609 struct amdgpu_connector *aconnector;
610 struct drm_connector *connector;
4562236b 611 struct drm_crtc *crtc;
a3621485
AG		 612 struct drm_crtc_state *crtc_state;
613 int ret = 0;
614 int i;
4562236b
HW		 615
616 /* program HPD filter */
617 dc_resume(dm->dc);
618
619 /* On resume we need to rewrite the MSTM control bits to enamble MST*/
620 s3_handle_mst(ddev, false);
621
622 /*
623 * early enable HPD Rx IRQ, should be done before set mode as short
624 * pulse interrupts are used for MST
625 */
626 amdgpu_dm_irq_resume_early(adev);
627
4562236b
HW		 628 /* Do detection*/
629 list_for_each_entry(connector,
630 &ddev->mode_config.connector_list, head) {
631 aconnector = to_amdgpu_connector(connector);
632
633 /*
634 * this is the case when traversing through already created
635 * MST connectors, should be skipped
636 */
637 if (aconnector->mst_port)
638 continue;
639
03ea364c 640 mutex_lock(&aconnector->hpd_lock);
4562236b
HW		 641 dc_link_detect(aconnector->dc_link, false);
642 aconnector->dc_sink = NULL;
643 amdgpu_dm_update_connector_after_detect(aconnector);
03ea364c 644 mutex_unlock(&aconnector->hpd_lock);
4562236b
HW		 645 }
646
a3621485
AG		 647 /* Force mode set in atomic comit */
648 for_each_crtc_in_state(adev->dm.cached_state, crtc, crtc_state, i)
649 crtc_state->active_changed = true;
650
651 ret = drm_atomic_helper_resume(ddev, adev->dm.cached_state);
4562236b 652
0a214e2f
AG		 653 drm_atomic_state_put(adev->dm.cached_state);
654 adev->dm.cached_state = NULL;
655
9faa4237 656 amdgpu_dm_irq_resume_late(adev);
4562236b
HW		 657
658 return ret;
659}
660
661static const struct amd_ip_funcs amdgpu_dm_funcs = {
662 .name = "dm",
663 .early_init = dm_early_init,
7abcf6b5 664 .late_init = dm_late_init,
4562236b
HW		 665 .sw_init = dm_sw_init,
666 .sw_fini = dm_sw_fini,
667 .hw_init = dm_hw_init,
668 .hw_fini = dm_hw_fini,
669 .suspend = dm_suspend,
670 .resume = dm_resume,
671 .is_idle = dm_is_idle,
672 .wait_for_idle = dm_wait_for_idle,
673 .check_soft_reset = dm_check_soft_reset,
674 .soft_reset = dm_soft_reset,
675 .set_clockgating_state = dm_set_clockgating_state,
676 .set_powergating_state = dm_set_powergating_state,
677};
678
679const struct amdgpu_ip_block_version dm_ip_block =
680{
681 .type = AMD_IP_BLOCK_TYPE_DCE,
682 .major = 1,
683 .minor = 0,
684 .rev = 0,
685 .funcs = &amdgpu_dm_funcs,
686};
687
ca3268c4
HW		 688
689struct drm_atomic_state *
690dm_atomic_state_alloc(struct drm_device *dev)
691{
692 struct dm_atomic_state *state = kzalloc(sizeof(*state), GFP_KERNEL);
693
694 if (!state || drm_atomic_state_init(dev, &state->base) < 0) {
695 kfree(state);
696 return NULL;
697 }
698
699 return &state->base;
700}
701
0a323b84
AG		 702static void
703dm_atomic_state_clear(struct drm_atomic_state *state)
704{
705 struct dm_atomic_state *dm_state = to_dm_atomic_state(state);
706
707 if (dm_state->context) {
708 dc_release_validate_context(dm_state->context);
709 dm_state->context = NULL;
710 }
711
712 drm_atomic_state_default_clear(state);
713}
714
715static void
716dm_atomic_state_alloc_free(struct drm_atomic_state *state)
717{
718 struct dm_atomic_state *dm_state = to_dm_atomic_state(state);
719 drm_atomic_state_default_release(state);
720 kfree(dm_state);
721}
722
b3663f70 723static const struct drm_mode_config_funcs amdgpu_dm_mode_funcs = {
a49dcb88
HW		 724 .fb_create = amdgpu_user_framebuffer_create,
725 .output_poll_changed = amdgpu_output_poll_changed,
4562236b 726 .atomic_check = amdgpu_dm_atomic_check,
da5c47f6 727 .atomic_commit = amdgpu_dm_atomic_commit,
ca3268c4 728 .atomic_state_alloc = dm_atomic_state_alloc,
0a323b84
AG		 729 .atomic_state_clear = dm_atomic_state_clear,
730 .atomic_state_free = dm_atomic_state_alloc_free
54f5499a
AG		 731};
732
733static struct drm_mode_config_helper_funcs amdgpu_dm_mode_config_helperfuncs = {
734 .atomic_commit_tail = amdgpu_dm_atomic_commit_tail
4562236b
HW		 735};
736
737void amdgpu_dm_update_connector_after_detect(
738 struct amdgpu_connector *aconnector)
739{
740 struct drm_connector *connector = &aconnector->base;
741 struct drm_device *dev = connector->dev;
b73a22d3 742 struct dc_sink *sink;
4562236b
HW		 743
744 /* MST handled by drm_mst framework */
745 if (aconnector->mst_mgr.mst_state == true)
746 return;
747
748
749 sink = aconnector->dc_link->local_sink;
750
751 /* Edid mgmt connector gets first update only in mode_valid hook and then
752 * the connector sink is set to either fake or physical sink depends on link status.
753 * don't do it here if u are during boot
754 */
755 if (aconnector->base.force != DRM_FORCE_UNSPECIFIED
756 && aconnector->dc_em_sink) {
757
ab2541b6 758 /* For S3 resume with headless use eml_sink to fake stream
4562236b
HW		 759 * because on resume connecotr->sink is set ti NULL
760 */
761 mutex_lock(&dev->mode_config.mutex);
762
763 if (sink) {
922aa1e1 764 if (aconnector->dc_sink) {
4562236b
HW		 765 amdgpu_dm_remove_sink_from_freesync_module(
766 connector);
922aa1e1
AG		 767 /* retain and release bellow are used for
768 * bump up refcount for sink because the link don't point
769 * to it anymore after disconnect so on next crtc to connector
770 * reshuffle by UMD we will get into unwanted dc_sink release
771 */
772 if (aconnector->dc_sink != aconnector->dc_em_sink)
773 dc_sink_release(aconnector->dc_sink);
774 }
4562236b
HW		 775 aconnector->dc_sink = sink;
776 amdgpu_dm_add_sink_to_freesync_module(
777 connector, aconnector->edid);
778 } else {
779 amdgpu_dm_remove_sink_from_freesync_module(connector);
780 if (!aconnector->dc_sink)
781 aconnector->dc_sink = aconnector->dc_em_sink;
922aa1e1
AG		 782 else if (aconnector->dc_sink != aconnector->dc_em_sink)
783 dc_sink_retain(aconnector->dc_sink);
4562236b
HW		 784 }
785
786 mutex_unlock(&dev->mode_config.mutex);
787 return;
788 }
789
790 /*
791 * TODO: temporary guard to look for proper fix
792 * if this sink is MST sink, we should not do anything
793 */
794 if (sink && sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT_MST)
795 return;
796
797 if (aconnector->dc_sink == sink) {
798 /* We got a DP short pulse (Link Loss, DP CTS, etc...).
799 * Do nothing!! */
800 DRM_INFO("DCHPD: connector_id=%d: dc_sink didn't change.\n",
801 aconnector->connector_id);
802 return;
803 }
804
805 DRM_INFO("DCHPD: connector_id=%d: Old sink=%p New sink=%p\n",
806 aconnector->connector_id, aconnector->dc_sink, sink);
807
808 mutex_lock(&dev->mode_config.mutex);
809
810 /* 1. Update status of the drm connector
811 * 2. Send an event and let userspace tell us what to do */
812 if (sink) {
813 /* TODO: check if we still need the S3 mode update workaround.
814 * If yes, put it here. */
815 if (aconnector->dc_sink)
816 amdgpu_dm_remove_sink_from_freesync_module(
817 connector);
818
819 aconnector->dc_sink = sink;
820 if (sink->dc_edid.length == 0)
821 aconnector->edid = NULL;
822 else {
823 aconnector->edid =
824 (struct edid *) sink->dc_edid.raw_edid;
825
826
827 drm_mode_connector_update_edid_property(connector,
828 aconnector->edid);
829 }
830 amdgpu_dm_add_sink_to_freesync_module(connector, aconnector->edid);
831
832 } else {
833 amdgpu_dm_remove_sink_from_freesync_module(connector);
834 drm_mode_connector_update_edid_property(connector, NULL);
835 aconnector->num_modes = 0;
836 aconnector->dc_sink = NULL;
837 }
838
839 mutex_unlock(&dev->mode_config.mutex);
840}
841
842static void handle_hpd_irq(void *param)
843{
844 struct amdgpu_connector *aconnector = (struct amdgpu_connector *)param;
845 struct drm_connector *connector = &aconnector->base;
846 struct drm_device *dev = connector->dev;
847
848 /* In case of failure or MST no need to update connector status or notify the OS
849 * since (for MST case) MST does this in it's own context.
850 */
851 mutex_lock(&aconnector->hpd_lock);
852 if (dc_link_detect(aconnector->dc_link, false)) {
853 amdgpu_dm_update_connector_after_detect(aconnector);
854
855
856 drm_modeset_lock_all(dev);
857 dm_restore_drm_connector_state(dev, connector);
858 drm_modeset_unlock_all(dev);
859
860 if (aconnector->base.force == DRM_FORCE_UNSPECIFIED)
861 drm_kms_helper_hotplug_event(dev);
862 }
863 mutex_unlock(&aconnector->hpd_lock);
864
865}
866
867static void dm_handle_hpd_rx_irq(struct amdgpu_connector *aconnector)
868{
869 uint8_t esi[DP_PSR_ERROR_STATUS - DP_SINK_COUNT_ESI] = { 0 };
870 uint8_t dret;
871 bool new_irq_handled = false;
872 int dpcd_addr;
873 int dpcd_bytes_to_read;
874
875 const int max_process_count = 30;
876 int process_count = 0;
877
878 const struct dc_link_status *link_status = dc_link_get_status(aconnector->dc_link);
879
880 if (link_status->dpcd_caps->dpcd_rev.raw < 0x12) {
881 dpcd_bytes_to_read = DP_LANE0_1_STATUS - DP_SINK_COUNT;
882 /* DPCD 0x200 - 0x201 for downstream IRQ */
883 dpcd_addr = DP_SINK_COUNT;
884 } else {
885 dpcd_bytes_to_read = DP_PSR_ERROR_STATUS - DP_SINK_COUNT_ESI;
886 /* DPCD 0x2002 - 0x2005 for downstream IRQ */
887 dpcd_addr = DP_SINK_COUNT_ESI;
888 }
889
890 dret = drm_dp_dpcd_read(
891 &aconnector->dm_dp_aux.aux,
892 dpcd_addr,
893 esi,
894 dpcd_bytes_to_read);
895
896 while (dret == dpcd_bytes_to_read &&
897 process_count < max_process_count) {
898 uint8_t retry;
899 dret = 0;
900
901 process_count++;
902
903 DRM_DEBUG_KMS("ESI %02x %02x %02x\n", esi[0], esi[1], esi[2]);
4562236b
HW		 904 /* handle HPD short pulse irq */
905 if (aconnector->mst_mgr.mst_state)
906 drm_dp_mst_hpd_irq(
907 &aconnector->mst_mgr,
908 esi,
909 &new_irq_handled);
4562236b
HW		 910
911 if (new_irq_handled) {
912 /* ACK at DPCD to notify down stream */
913 const int ack_dpcd_bytes_to_write =
914 dpcd_bytes_to_read - 1;
915
916 for (retry = 0; retry < 3; retry++) {
917 uint8_t wret;
918
919 wret = drm_dp_dpcd_write(
920 &aconnector->dm_dp_aux.aux,
921 dpcd_addr + 1,
922 &esi[1],
923 ack_dpcd_bytes_to_write);
924 if (wret == ack_dpcd_bytes_to_write)
925 break;
926 }
927
928 /* check if there is new irq to be handle */
929 dret = drm_dp_dpcd_read(
930 &aconnector->dm_dp_aux.aux,
931 dpcd_addr,
932 esi,
933 dpcd_bytes_to_read);
934
935 new_irq_handled = false;
936 } else
937 break;
938 }
939
940 if (process_count == max_process_count)
941 DRM_DEBUG_KMS("Loop exceeded max iterations\n");
942}
943
944static void handle_hpd_rx_irq(void *param)
945{
946 struct amdgpu_connector *aconnector = (struct amdgpu_connector *)param;
947 struct drm_connector *connector = &aconnector->base;
948 struct drm_device *dev = connector->dev;
949 const struct dc_link *dc_link = aconnector->dc_link;
950 bool is_mst_root_connector = aconnector->mst_mgr.mst_state;
951
952 /* TODO:Temporary add mutex to protect hpd interrupt not have a gpio
953 * conflict, after implement i2c helper, this mutex should be
954 * retired.
955 */
956 if (aconnector->dc_link->type != dc_connection_mst_branch)
957 mutex_lock(&aconnector->hpd_lock);
958
8ee65d7c 959 if (dc_link_handle_hpd_rx_irq(aconnector->dc_link, NULL) &&
4562236b
HW		 960 !is_mst_root_connector) {
961 /* Downstream Port status changed. */
962 if (dc_link_detect(aconnector->dc_link, false)) {
963 amdgpu_dm_update_connector_after_detect(aconnector);
964
965
966 drm_modeset_lock_all(dev);
967 dm_restore_drm_connector_state(dev, connector);
968 drm_modeset_unlock_all(dev);
969
970 drm_kms_helper_hotplug_event(dev);
971 }
972 }
973 if ((dc_link->cur_link_settings.lane_count != LANE_COUNT_UNKNOWN) ||
974 (dc_link->type == dc_connection_mst_branch))
975 dm_handle_hpd_rx_irq(aconnector);
976
977 if (aconnector->dc_link->type != dc_connection_mst_branch)
978 mutex_unlock(&aconnector->hpd_lock);
979}
980
981static void register_hpd_handlers(struct amdgpu_device *adev)
982{
983 struct drm_device *dev = adev->ddev;
984 struct drm_connector *connector;
985 struct amdgpu_connector *aconnector;
986 const struct dc_link *dc_link;
987 struct dc_interrupt_params int_params = {0};
988
989 int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
990 int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
991
992 list_for_each_entry(connector,
993 &dev->mode_config.connector_list, head) {
994
995 aconnector = to_amdgpu_connector(connector);
996 dc_link = aconnector->dc_link;
997
998 if (DC_IRQ_SOURCE_INVALID != dc_link->irq_source_hpd) {
999 int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT;
1000 int_params.irq_source = dc_link->irq_source_hpd;
1001
1002 amdgpu_dm_irq_register_interrupt(adev, &int_params,
1003 handle_hpd_irq,
1004 (void *) aconnector);
1005 }
1006
1007 if (DC_IRQ_SOURCE_INVALID != dc_link->irq_source_hpd_rx) {
1008
1009 /* Also register for DP short pulse (hpd_rx). */
1010 int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT;
1011 int_params.irq_source = dc_link->irq_source_hpd_rx;
1012
1013 amdgpu_dm_irq_register_interrupt(adev, &int_params,
1014 handle_hpd_rx_irq,
1015 (void *) aconnector);
1016 }
1017 }
1018}
1019
1020/* Register IRQ sources and initialize IRQ callbacks */
1021static int dce110_register_irq_handlers(struct amdgpu_device *adev)
1022{
1023 struct dc *dc = adev->dm.dc;
1024 struct common_irq_params *c_irq_params;
1025 struct dc_interrupt_params int_params = {0};
1026 int r;
1027 int i;
2c8ad2d5
AD		 1028 unsigned client_id = AMDGPU_IH_CLIENTID_LEGACY;
1029
ff5ef992
AD		 1030 if (adev->asic_type == CHIP_VEGA10 ||
1031 adev->asic_type == CHIP_RAVEN)
2c8ad2d5 1032 client_id = AMDGPU_IH_CLIENTID_DCE;
4562236b
HW		 1033
1034 int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
1035 int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
1036
1037 /* Actions of amdgpu_irq_add_id():
1038 * 1. Register a set() function with base driver.
1039 * Base driver will call set() function to enable/disable an
1040 * interrupt in DC hardware.
1041 * 2. Register amdgpu_dm_irq_handler().
1042 * Base driver will call amdgpu_dm_irq_handler() for ALL interrupts
1043 * coming from DC hardware.
1044 * amdgpu_dm_irq_handler() will re-direct the interrupt to DC
1045 * for acknowledging and handling. */
1046
b57de80a 1047 /* Use VBLANK interrupt */
e9029155 1048 for (i = VISLANDS30_IV_SRCID_D1_VERTICAL_INTERRUPT0; i <= VISLANDS30_IV_SRCID_D6_VERTICAL_INTERRUPT0; i++) {
2c8ad2d5 1049 r = amdgpu_irq_add_id(adev, client_id, i, &adev->crtc_irq);
4562236b
HW		 1050 if (r) {
1051 DRM_ERROR("Failed to add crtc irq id!\n");
1052 return r;
1053 }
1054
1055 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
1056 int_params.irq_source =
3d761e79 1057 dc_interrupt_to_irq_source(dc, i, 0);
4562236b 1058
b57de80a 1059 c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1];
4562236b
HW		 1060
1061 c_irq_params->adev = adev;
1062 c_irq_params->irq_src = int_params.irq_source;
1063
1064 amdgpu_dm_irq_register_interrupt(adev, &int_params,
1065 dm_crtc_high_irq, c_irq_params);
1066 }
1067
3d761e79 1068 /* Use GRPH_PFLIP interrupt */
4562236b
HW		 1069 for (i = VISLANDS30_IV_SRCID_D1_GRPH_PFLIP;
1070 i <= VISLANDS30_IV_SRCID_D6_GRPH_PFLIP; i += 2) {
2c8ad2d5 1071 r = amdgpu_irq_add_id(adev, client_id, i, &adev->pageflip_irq);
4562236b
HW		 1072 if (r) {
1073 DRM_ERROR("Failed to add page flip irq id!\n");
1074 return r;
1075 }
1076
1077 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
1078 int_params.irq_source =
1079 dc_interrupt_to_irq_source(dc, i, 0);
1080
1081 c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST];
1082
1083 c_irq_params->adev = adev;
1084 c_irq_params->irq_src = int_params.irq_source;
1085
1086 amdgpu_dm_irq_register_interrupt(adev, &int_params,
1087 dm_pflip_high_irq, c_irq_params);
1088
1089 }
1090
1091 /* HPD */
2c8ad2d5
AD		 1092 r = amdgpu_irq_add_id(adev, client_id,
1093 VISLANDS30_IV_SRCID_HOTPLUG_DETECT_A, &adev->hpd_irq);
4562236b
HW		 1094 if (r) {
1095 DRM_ERROR("Failed to add hpd irq id!\n");
1096 return r;
1097 }
1098
1099 register_hpd_handlers(adev);
1100
1101 return 0;
1102}
1103
ff5ef992
AD		 1104#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
1105/* Register IRQ sources and initialize IRQ callbacks */
1106static int dcn10_register_irq_handlers(struct amdgpu_device *adev)
1107{
1108 struct dc *dc = adev->dm.dc;
1109 struct common_irq_params *c_irq_params;
1110 struct dc_interrupt_params int_params = {0};
1111 int r;
1112 int i;
1113
1114 int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
1115 int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
1116
1117 /* Actions of amdgpu_irq_add_id():
1118 * 1. Register a set() function with base driver.
1119 * Base driver will call set() function to enable/disable an
1120 * interrupt in DC hardware.
1121 * 2. Register amdgpu_dm_irq_handler().
1122 * Base driver will call amdgpu_dm_irq_handler() for ALL interrupts
1123 * coming from DC hardware.
1124 * amdgpu_dm_irq_handler() will re-direct the interrupt to DC
1125 * for acknowledging and handling.
1126 * */
1127
1128 /* Use VSTARTUP interrupt */
1129 for (i = DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP;
1130 i <= DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP + adev->mode_info.num_crtc - 1;
1131 i++) {
1132 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_DCE, i, &adev->crtc_irq);
1133
1134 if (r) {
1135 DRM_ERROR("Failed to add crtc irq id!\n");
1136 return r;
1137 }
1138
1139 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
1140 int_params.irq_source =
1141 dc_interrupt_to_irq_source(dc, i, 0);
1142
1143 c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1];
1144
1145 c_irq_params->adev = adev;
1146 c_irq_params->irq_src = int_params.irq_source;
1147
1148 amdgpu_dm_irq_register_interrupt(adev, &int_params,
1149 dm_crtc_high_irq, c_irq_params);
1150 }
1151
1152 /* Use GRPH_PFLIP interrupt */
1153 for (i = DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT;
1154 i <= DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT + adev->mode_info.num_crtc - 1;
1155 i++) {
1156 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_DCE, i, &adev->pageflip_irq);
1157 if (r) {
1158 DRM_ERROR("Failed to add page flip irq id!\n");
1159 return r;
1160 }
1161
1162 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
1163 int_params.irq_source =
1164 dc_interrupt_to_irq_source(dc, i, 0);
1165
1166 c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST];
1167
1168 c_irq_params->adev = adev;
1169 c_irq_params->irq_src = int_params.irq_source;
1170
1171 amdgpu_dm_irq_register_interrupt(adev, &int_params,
1172 dm_pflip_high_irq, c_irq_params);
1173
1174 }
1175
1176 /* HPD */
1177 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_DCE, DCN_1_0__SRCID__DC_HPD1_INT,
1178 &adev->hpd_irq);
1179 if (r) {
1180 DRM_ERROR("Failed to add hpd irq id!\n");
1181 return r;
1182 }
1183
1184 register_hpd_handlers(adev);
1185
1186 return 0;
1187}
1188#endif
1189
4562236b
HW		 1190static int amdgpu_dm_mode_config_init(struct amdgpu_device *adev)
1191{
1192 int r;
1193
1194 adev->mode_info.mode_config_initialized = true;
1195
4562236b 1196 adev->ddev->mode_config.funcs = (void *)&amdgpu_dm_mode_funcs;
54f5499a 1197 adev->ddev->mode_config.helper_private = &amdgpu_dm_mode_config_helperfuncs;
4562236b
HW		 1198
1199 adev->ddev->mode_config.max_width = 16384;
1200 adev->ddev->mode_config.max_height = 16384;
1201
1202 adev->ddev->mode_config.preferred_depth = 24;
1203 adev->ddev->mode_config.prefer_shadow = 1;
1204 /* indicate support of immediate flip */
1205 adev->ddev->mode_config.async_page_flip = true;
1206
1207 adev->ddev->mode_config.fb_base = adev->mc.aper_base;
1208
1209 r = amdgpu_modeset_create_props(adev);
1210 if (r)
1211 return r;
1212
1213 return 0;
1214}
1215
1216#if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) ||\
1217 defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
1218
1219static int amdgpu_dm_backlight_update_status(struct backlight_device *bd)
1220{
1221 struct amdgpu_display_manager *dm = bl_get_data(bd);
1222
1223 if (dc_link_set_backlight_level(dm->backlight_link,
1224 bd->props.brightness, 0, 0))
1225 return 0;
1226 else
1227 return 1;
1228}
1229
1230static int amdgpu_dm_backlight_get_brightness(struct backlight_device *bd)
1231{
1232 return bd->props.brightness;
1233}
1234
1235static const struct backlight_ops amdgpu_dm_backlight_ops = {
1236 .get_brightness = amdgpu_dm_backlight_get_brightness,
1237 .update_status = amdgpu_dm_backlight_update_status,
1238};
1239
1240void amdgpu_dm_register_backlight_device(struct amdgpu_display_manager *dm)
1241{
1242 char bl_name[16];
1243 struct backlight_properties props = { 0 };
1244
1245 props.max_brightness = AMDGPU_MAX_BL_LEVEL;
1246 props.type = BACKLIGHT_RAW;
1247
1248 snprintf(bl_name, sizeof(bl_name), "amdgpu_bl%d",
1249 dm->adev->ddev->primary->index);
1250
1251 dm->backlight_dev = backlight_device_register(bl_name,
1252 dm->adev->ddev->dev,
1253 dm,
1254 &amdgpu_dm_backlight_ops,
1255 &props);
1256
1257 if (NULL == dm->backlight_dev)
1258 DRM_ERROR("DM: Backlight registration failed!\n");
1259 else
1260 DRM_INFO("DM: Registered Backlight device: %s\n", bl_name);
1261}
1262
1263#endif
1264
1265/* In this architecture, the association
1266 * connector -> encoder -> crtc
1267 * id not really requried. The crtc and connector will hold the
1268 * display_index as an abstraction to use with DAL component
1269 *
1270 * Returns 0 on success
1271 */
1272int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev)
1273{
1274 struct amdgpu_display_manager *dm = &adev->dm;
1275 uint32_t i;
f2a0f5e6
HW		 1276 struct amdgpu_connector *aconnector = NULL;
1277 struct amdgpu_encoder *aencoder = NULL;
d4e13b0d 1278 struct amdgpu_mode_info *mode_info = &adev->mode_info;
4562236b 1279 uint32_t link_cnt;
92f3ac40 1280 unsigned long possible_crtcs;
4562236b
HW		 1281
1282 link_cnt = dm->dc->caps.max_links;
4562236b
HW		 1283 if (amdgpu_dm_mode_config_init(dm->adev)) {
1284 DRM_ERROR("DM: Failed to initialize mode config\n");
f2a0f5e6 1285 return -1;
4562236b
HW		 1286 }
1287
3be5262e 1288 for (i = 0; i < dm->dc->caps.max_planes; i++) {
d4e13b0d
AD		 1289 mode_info->planes[i] = kzalloc(sizeof(struct amdgpu_plane),
1290 GFP_KERNEL);
1291 if (!mode_info->planes[i]) {
3be5262e 1292 DRM_ERROR("KMS: Failed to allocate plane\n");
d4e13b0d
AD		 1293 goto fail_free_planes;
1294 }
1605b3be 1295 mode_info->planes[i]->base.type = mode_info->plane_type[i];
92f3ac40
LSL		 1296
1297 /*
1298 * HACK: IGT tests expect that each plane can only have one
1299 * one possible CRTC. For now, set one CRTC for each
1300 * plane that is not an underlay, but still allow multiple
1301 * CRTCs for underlay planes.
1302 */
1303 possible_crtcs = 1 << i;
1304 if (i >= dm->dc->caps.max_streams)
1305 possible_crtcs = 0xff;
1306
1307 if (amdgpu_dm_plane_init(dm, mode_info->planes[i], possible_crtcs)) {
d4e13b0d
AD		 1308 DRM_ERROR("KMS: Failed to initialize plane\n");
1309 goto fail_free_planes;
1310 }
1311 }
4562236b 1312
d4e13b0d
AD		 1313 for (i = 0; i < dm->dc->caps.max_streams; i++)
1314 if (amdgpu_dm_crtc_init(dm, &mode_info->planes[i]->base, i)) {
4562236b 1315 DRM_ERROR("KMS: Failed to initialize crtc\n");
d4e13b0d 1316 goto fail_free_planes;
4562236b 1317 }
4562236b 1318
ab2541b6 1319 dm->display_indexes_num = dm->dc->caps.max_streams;
4562236b
HW		 1320
1321 /* loops over all connectors on the board */
1322 for (i = 0; i < link_cnt; i++) {
1323
1324 if (i > AMDGPU_DM_MAX_DISPLAY_INDEX) {
1325 DRM_ERROR(
1326 "KMS: Cannot support more than %d display indexes\n",
1327 AMDGPU_DM_MAX_DISPLAY_INDEX);
1328 continue;
1329 }
1330
1331 aconnector = kzalloc(sizeof(*aconnector), GFP_KERNEL);
1332 if (!aconnector)
f2a0f5e6 1333 goto fail_free_planes;
4562236b
HW		 1334
1335 aencoder = kzalloc(sizeof(*aencoder), GFP_KERNEL);
1336 if (!aencoder) {
1337 goto fail_free_connector;
1338 }
1339
1340 if (amdgpu_dm_encoder_init(dm->ddev, aencoder, i)) {
1341 DRM_ERROR("KMS: Failed to initialize encoder\n");
1342 goto fail_free_encoder;
1343 }
1344
1345 if (amdgpu_dm_connector_init(dm, aconnector, i, aencoder)) {
1346 DRM_ERROR("KMS: Failed to initialize connector\n");
f2a0f5e6 1347 goto fail_free_encoder;
4562236b
HW		 1348 }
1349
1350 if (dc_link_detect(dc_get_link_at_index(dm->dc, i), true))
1351 amdgpu_dm_update_connector_after_detect(aconnector);
1352 }
1353
1354 /* Software is initialized. Now we can register interrupt handlers. */
1355 switch (adev->asic_type) {
1356 case CHIP_BONAIRE:
1357 case CHIP_HAWAII:
1358 case CHIP_TONGA:
1359 case CHIP_FIJI:
1360 case CHIP_CARRIZO:
1361 case CHIP_STONEY:
1362 case CHIP_POLARIS11:
1363 case CHIP_POLARIS10:
b264d345 1364 case CHIP_POLARIS12:
2c8ad2d5 1365 case CHIP_VEGA10:
4562236b
HW		 1366 if (dce110_register_irq_handlers(dm->adev)) {
1367 DRM_ERROR("DM: Failed to initialize IRQ\n");
d4e13b0d 1368 goto fail_free_encoder;
4562236b
HW		 1369 }
1370 break;
ff5ef992
AD		 1371#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
1372 case CHIP_RAVEN:
1373 if (dcn10_register_irq_handlers(dm->adev)) {
1374 DRM_ERROR("DM: Failed to initialize IRQ\n");
1375 goto fail_free_encoder;
1376 }
1377 break;
1378#endif
4562236b
HW		 1379 default:
1380 DRM_ERROR("Usupported ASIC type: 0x%X\n", adev->asic_type);
d4e13b0d 1381 goto fail_free_encoder;
4562236b
HW		 1382 }
1383
1384 drm_mode_config_reset(dm->ddev);
1385
1386 return 0;
1387fail_free_encoder:
1388 kfree(aencoder);
1389fail_free_connector:
1390 kfree(aconnector);
d4e13b0d 1391fail_free_planes:
3be5262e 1392 for (i = 0; i < dm->dc->caps.max_planes; i++)
d4e13b0d 1393 kfree(mode_info->planes[i]);
4562236b
HW		 1394 return -1;
1395}
1396
1397void amdgpu_dm_destroy_drm_device(struct amdgpu_display_manager *dm)
1398{
1399 drm_mode_config_cleanup(dm->ddev);
1400 return;
1401}
1402
1403/******************************************************************************
1404 * amdgpu_display_funcs functions
1405 *****************************************************************************/
1406
1407/**
1408 * dm_bandwidth_update - program display watermarks
1409 *
1410 * @adev: amdgpu_device pointer
1411 *
1412 * Calculate and program the display watermarks and line buffer allocation.
1413 */
1414static void dm_bandwidth_update(struct amdgpu_device *adev)
1415{
49c07a99 1416 /* TODO: implement later */
4562236b
HW		 1417}
1418
1419static void dm_set_backlight_level(struct amdgpu_encoder *amdgpu_encoder,
1420 u8 level)
1421{
1422 /* TODO: translate amdgpu_encoder to display_index and call DAL */
4562236b
HW		 1423}
1424
1425static u8 dm_get_backlight_level(struct amdgpu_encoder *amdgpu_encoder)
1426{
1427 /* TODO: translate amdgpu_encoder to display_index and call DAL */
4562236b
HW		 1428 return 0;
1429}
1430
4562236b
HW		 1431static int amdgpu_notify_freesync(struct drm_device *dev, void *data,
1432 struct drm_file *filp)
1433{
1434 struct mod_freesync_params freesync_params;
ab2541b6 1435 uint8_t num_streams;
4562236b 1436 uint8_t i;
4562236b
HW		 1437
1438 struct amdgpu_device *adev = dev->dev_private;
1439 int r = 0;
1440
1441 /* Get freesync enable flag from DRM */
1442
ab2541b6 1443 num_streams = dc_get_current_stream_count(adev->dm.dc);
4562236b 1444
ab2541b6 1445 for (i = 0; i < num_streams; i++) {
0971c40e 1446 struct dc_stream_state *stream;
ab2541b6 1447 stream = dc_get_stream_at_index(adev->dm.dc, i);
4562236b
HW		 1448
1449 mod_freesync_update_state(adev->dm.freesync_module,
ab2541b6 1450 &stream, 1, &freesync_params);
4562236b
HW		 1451 }
1452
1453 return r;
1454}
1455
39cc5be2 1456static const struct amdgpu_display_funcs dm_display_funcs = {
4562236b
HW		 1457 .bandwidth_update = dm_bandwidth_update, /* called unconditionally */
1458 .vblank_get_counter = dm_vblank_get_counter,/* called unconditionally */
1459 .vblank_wait = NULL,
1460 .backlight_set_level =
1461 dm_set_backlight_level,/* called unconditionally */
1462 .backlight_get_level =
1463 dm_get_backlight_level,/* called unconditionally */
1464 .hpd_sense = NULL,/* called unconditionally */
1465 .hpd_set_polarity = NULL, /* called unconditionally */
1466 .hpd_get_gpio_reg = NULL, /* VBIOS parsing. DAL does it. */
4562236b
HW		 1467 .page_flip_get_scanoutpos =
1468 dm_crtc_get_scanoutpos,/* called unconditionally */
1469 .add_encoder = NULL, /* VBIOS parsing. DAL does it. */
1470 .add_connector = NULL, /* VBIOS parsing. DAL does it. */
1471 .notify_freesync = amdgpu_notify_freesync,
1472
1473};
1474
1475#if defined(CONFIG_DEBUG_KERNEL_DC)
1476
1477static ssize_t s3_debug_store(
1478 struct device *device,
1479 struct device_attribute *attr,
1480 const char *buf,
1481 size_t count)
1482{
1483 int ret;
1484 int s3_state;
1485 struct pci_dev *pdev = to_pci_dev(device);
1486 struct drm_device *drm_dev = pci_get_drvdata(pdev);
1487 struct amdgpu_device *adev = drm_dev->dev_private;
1488
1489 ret = kstrtoint(buf, 0, &s3_state);
1490
1491 if (ret == 0) {
1492 if (s3_state) {
1493 dm_resume(adev);
1494 amdgpu_dm_display_resume(adev);
1495 drm_kms_helper_hotplug_event(adev->ddev);
1496 } else
1497 dm_suspend(adev);
1498 }
1499
1500 return ret == 0 ? count : 0;
1501}
1502
1503DEVICE_ATTR_WO(s3_debug);
1504
1505#endif
1506
1507static int dm_early_init(void *handle)
1508{
1509 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1510
d7ec53d9 1511 adev->ddev->driver->driver_features |= DRIVER_ATOMIC;
4562236b
HW		 1512 amdgpu_dm_set_irq_funcs(adev);
1513
1514 switch (adev->asic_type) {
1515 case CHIP_BONAIRE:
1516 case CHIP_HAWAII:
1517 adev->mode_info.num_crtc = 6;
1518 adev->mode_info.num_hpd = 6;
1519 adev->mode_info.num_dig = 6;
3be5262e 1520 adev->mode_info.plane_type = dm_plane_type_default;
4562236b
HW		 1521 break;
1522 case CHIP_FIJI:
1523 case CHIP_TONGA:
1524 adev->mode_info.num_crtc = 6;
1525 adev->mode_info.num_hpd = 6;
1526 adev->mode_info.num_dig = 7;
3be5262e 1527 adev->mode_info.plane_type = dm_plane_type_default;
4562236b
HW		 1528 break;
1529 case CHIP_CARRIZO:
1530 adev->mode_info.num_crtc = 3;
1531 adev->mode_info.num_hpd = 6;
1532 adev->mode_info.num_dig = 9;
3be5262e 1533 adev->mode_info.plane_type = dm_plane_type_carizzo;
4562236b
HW		 1534 break;
1535 case CHIP_STONEY:
1536 adev->mode_info.num_crtc = 2;
1537 adev->mode_info.num_hpd = 6;
1538 adev->mode_info.num_dig = 9;
3be5262e 1539 adev->mode_info.plane_type = dm_plane_type_stoney;
4562236b
HW		 1540 break;
1541 case CHIP_POLARIS11:
b264d345 1542 case CHIP_POLARIS12:
4562236b
HW		 1543 adev->mode_info.num_crtc = 5;
1544 adev->mode_info.num_hpd = 5;
1545 adev->mode_info.num_dig = 5;
3be5262e 1546 adev->mode_info.plane_type = dm_plane_type_default;
4562236b
HW		 1547 break;
1548 case CHIP_POLARIS10:
1549 adev->mode_info.num_crtc = 6;
1550 adev->mode_info.num_hpd = 6;
1551 adev->mode_info.num_dig = 6;
3be5262e 1552 adev->mode_info.plane_type = dm_plane_type_default;
4562236b 1553 break;
2c8ad2d5
AD		 1554 case CHIP_VEGA10:
1555 adev->mode_info.num_crtc = 6;
1556 adev->mode_info.num_hpd = 6;
1557 adev->mode_info.num_dig = 6;
3be5262e 1558 adev->mode_info.plane_type = dm_plane_type_default;
2c8ad2d5 1559 break;
ff5ef992
AD		 1560#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
1561 case CHIP_RAVEN:
1562 adev->mode_info.num_crtc = 4;
1563 adev->mode_info.num_hpd = 4;
1564 adev->mode_info.num_dig = 4;
3be5262e 1565 adev->mode_info.plane_type = dm_plane_type_default;
ff5ef992
AD		 1566 break;
1567#endif
4562236b
HW		 1568 default:
1569 DRM_ERROR("Usupported ASIC type: 0x%X\n", adev->asic_type);
1570 return -EINVAL;
1571 }
1572
39cc5be2
AD		 1573 if (adev->mode_info.funcs == NULL)
1574 adev->mode_info.funcs = &dm_display_funcs;
1575
4562236b
HW		 1576 /* Note: Do NOT change adev->audio_endpt_rreg and
1577 * adev->audio_endpt_wreg because they are initialised in
1578 * amdgpu_device_init() */
1579#if defined(CONFIG_DEBUG_KERNEL_DC)
1580 device_create_file(
1581 adev->ddev->dev,
1582 &dev_attr_s3_debug);
1583#endif
1584
1585 return 0;
1586}
1587
1588bool amdgpu_dm_acquire_dal_lock(struct amdgpu_display_manager *dm)
1589{
1590 /* TODO */
1591 return true;
1592}
1593
1594bool amdgpu_dm_release_dal_lock(struct amdgpu_display_manager *dm)
1595{
e1403629
HW		 1596 /* TODO */
1597 return true;
e7b07cee
HW		 1598}
1599
1600
1601struct dm_connector_state {
1602 struct drm_connector_state base;
1603
1604 enum amdgpu_rmx_type scaling;
1605 uint8_t underscan_vborder;
1606 uint8_t underscan_hborder;
1607 bool underscan_enable;
1608};
1609
1610#define to_dm_connector_state(x)\
1611 container_of((x), struct dm_connector_state, base)
1612
9b690ef3 1613static bool modeset_required(struct drm_crtc_state *crtc_state,
0971c40e
HW		 1614 struct dc_stream_state *new_stream,
1615 struct dc_stream_state *old_stream)
9b690ef3
BL		 1616{
1617 if (dc_is_stream_unchanged(new_stream, old_stream)) {
1618 crtc_state->mode_changed = false;
1619 DRM_DEBUG_KMS("Mode change not required, setting mode_changed to %d",
1620 crtc_state->mode_changed);
1621 }
1622
e7b07cee
HW		 1623 if (!drm_atomic_crtc_needs_modeset(crtc_state))
1624 return false;
1625
1626 if (!crtc_state->enable)
1627 return false;
1628
1629 return crtc_state->active;
1630}
1631
1632static bool modereset_required(struct drm_crtc_state *crtc_state)
1633{
1634 if (!drm_atomic_crtc_needs_modeset(crtc_state))
1635 return false;
1636
1637 return !crtc_state->enable || !crtc_state->active;
1638}
1639
1640void amdgpu_dm_encoder_destroy(struct drm_encoder *encoder)
1641{
1642 drm_encoder_cleanup(encoder);
1643 kfree(encoder);
1644}
1645
1646static const struct drm_encoder_funcs amdgpu_dm_encoder_funcs = {
1647 .destroy = amdgpu_dm_encoder_destroy,
1648};
1649
e7b07cee
HW		 1650static bool fill_rects_from_plane_state(
1651 const struct drm_plane_state *state,
3be5262e 1652 struct dc_plane_state *plane_state)
e7b07cee 1653{
3be5262e
HW		 1654 plane_state->src_rect.x = state->src_x >> 16;
1655 plane_state->src_rect.y = state->src_y >> 16;
e7b07cee 1656 /*we ignore for now mantissa and do not to deal with floating pixels :(*/
3be5262e 1657 plane_state->src_rect.width = state->src_w >> 16;
e7b07cee 1658
3be5262e 1659 if (plane_state->src_rect.width == 0)
e7b07cee
HW		 1660 return false;
1661
3be5262e
HW		 1662 plane_state->src_rect.height = state->src_h >> 16;
1663 if (plane_state->src_rect.height == 0)
e7b07cee
HW		 1664 return false;
1665
3be5262e
HW		 1666 plane_state->dst_rect.x = state->crtc_x;
1667 plane_state->dst_rect.y = state->crtc_y;
e7b07cee
HW		 1668
1669 if (state->crtc_w == 0)
1670 return false;
1671
3be5262e 1672 plane_state->dst_rect.width = state->crtc_w;
e7b07cee
HW		 1673
1674 if (state->crtc_h == 0)
1675 return false;
1676
3be5262e 1677 plane_state->dst_rect.height = state->crtc_h;
e7b07cee 1678
3be5262e 1679 plane_state->clip_rect = plane_state->dst_rect;
e7b07cee
HW		 1680
1681 switch (state->rotation & DRM_MODE_ROTATE_MASK) {
1682 case DRM_MODE_ROTATE_0:
3be5262e 1683 plane_state->rotation = ROTATION_ANGLE_0;
e7b07cee
HW		 1684 break;
1685 case DRM_MODE_ROTATE_90:
3be5262e 1686 plane_state->rotation = ROTATION_ANGLE_90;
e7b07cee
HW		 1687 break;
1688 case DRM_MODE_ROTATE_180:
3be5262e 1689 plane_state->rotation = ROTATION_ANGLE_180;
e7b07cee
HW		 1690 break;
1691 case DRM_MODE_ROTATE_270:
3be5262e 1692 plane_state->rotation = ROTATION_ANGLE_270;
e7b07cee
HW		 1693 break;
1694 default:
3be5262e 1695 plane_state->rotation = ROTATION_ANGLE_0;
e7b07cee
HW		 1696 break;
1697 }
1698
4562236b
HW		 1699 return true;
1700}
e7b07cee
HW		 1701static int get_fb_info(
1702 const struct amdgpu_framebuffer *amdgpu_fb,
1703 uint64_t *tiling_flags,
1704 uint64_t *fb_location)
1705{
1706 struct amdgpu_bo *rbo = gem_to_amdgpu_bo(amdgpu_fb->obj);
1707 int r = amdgpu_bo_reserve(rbo, false);
b830ebc9 1708
e7b07cee
HW		 1709 if (unlikely(r)) {
1710 DRM_ERROR("Unable to reserve buffer\n");
1711 return r;
1712 }
1713
1714 if (fb_location)
1715 *fb_location = amdgpu_bo_gpu_offset(rbo);
1716
1717 if (tiling_flags)
1718 amdgpu_bo_get_tiling_flags(rbo, tiling_flags);
1719
1720 amdgpu_bo_unreserve(rbo);
1721
1722 return r;
1723}
1724
1725static int fill_plane_attributes_from_fb(
1726 struct amdgpu_device *adev,
3be5262e 1727 struct dc_plane_state *plane_state,
e7b07cee
HW		 1728 const struct amdgpu_framebuffer *amdgpu_fb, bool addReq)
1729{
1730 uint64_t tiling_flags;
1731 uint64_t fb_location = 0;
1732 unsigned int awidth;
1733 const struct drm_framebuffer *fb = &amdgpu_fb->base;
1734 int ret = 0;
1735 struct drm_format_name_buf format_name;
1736
1737 ret = get_fb_info(
1738 amdgpu_fb,
1739 &tiling_flags,
1740 addReq == true ? &fb_location:NULL);
1741
1742 if (ret)
1743 return ret;
1744
1745 switch (fb->format->format) {
1746 case DRM_FORMAT_C8:
3be5262e 1747 plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS;
e7b07cee
HW		 1748 break;
1749 case DRM_FORMAT_RGB565:
3be5262e 1750 plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_RGB565;
e7b07cee
HW		 1751 break;
1752 case DRM_FORMAT_XRGB8888:
1753 case DRM_FORMAT_ARGB8888:
3be5262e 1754 plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB8888;
e7b07cee
HW		 1755 break;
1756 case DRM_FORMAT_XRGB2101010:
1757 case DRM_FORMAT_ARGB2101010:
3be5262e 1758 plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010;
e7b07cee
HW		 1759 break;
1760 case DRM_FORMAT_XBGR2101010:
1761 case DRM_FORMAT_ABGR2101010:
3be5262e 1762 plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010;
e7b07cee
HW		 1763 break;
1764 case DRM_FORMAT_NV21:
3be5262e 1765 plane_state->format = SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr;
e7b07cee
HW		 1766 break;
1767 case DRM_FORMAT_NV12:
3be5262e 1768 plane_state->format = SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb;
e7b07cee
HW		 1769 break;
1770 default:
1771 DRM_ERROR("Unsupported screen format %s\n",
1772 drm_get_format_name(fb->format->format, &format_name));
1773 return -EINVAL;
1774 }
1775
3be5262e
HW		 1776 if (plane_state->format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) {
1777 plane_state->address.type = PLN_ADDR_TYPE_GRAPHICS;
1778 plane_state->address.grph.addr.low_part = lower_32_bits(fb_location);
1779 plane_state->address.grph.addr.high_part = upper_32_bits(fb_location);
1780 plane_state->plane_size.grph.surface_size.x = 0;
1781 plane_state->plane_size.grph.surface_size.y = 0;
1782 plane_state->plane_size.grph.surface_size.width = fb->width;
1783 plane_state->plane_size.grph.surface_size.height = fb->height;
1784 plane_state->plane_size.grph.surface_pitch =
e7b07cee
HW		 1785 fb->pitches[0] / fb->format->cpp[0];
1786 /* TODO: unhardcode */
3be5262e 1787 plane_state->color_space = COLOR_SPACE_SRGB;
e7b07cee
HW		 1788
1789 } else {
1790 awidth = ALIGN(fb->width, 64);
3be5262e
HW		 1791 plane_state->address.type = PLN_ADDR_TYPE_VIDEO_PROGRESSIVE;
1792 plane_state->address.video_progressive.luma_addr.low_part
e7b07cee 1793 = lower_32_bits(fb_location);
3be5262e 1794 plane_state->address.video_progressive.chroma_addr.low_part
e7b07cee
HW		 1795 = lower_32_bits(fb_location) +
1796 (awidth * fb->height);
3be5262e
HW		 1797 plane_state->plane_size.video.luma_size.x = 0;
1798 plane_state->plane_size.video.luma_size.y = 0;
1799 plane_state->plane_size.video.luma_size.width = awidth;
1800 plane_state->plane_size.video.luma_size.height = fb->height;
e7b07cee 1801 /* TODO: unhardcode */
3be5262e 1802 plane_state->plane_size.video.luma_pitch = awidth;
e7b07cee 1803
3be5262e
HW		 1804 plane_state->plane_size.video.chroma_size.x = 0;
1805 plane_state->plane_size.video.chroma_size.y = 0;
1806 plane_state->plane_size.video.chroma_size.width = awidth;
1807 plane_state->plane_size.video.chroma_size.height = fb->height;
1808 plane_state->plane_size.video.chroma_pitch = awidth / 2;
e7b07cee
HW		 1809
1810 /* TODO: unhardcode */
3be5262e 1811 plane_state->color_space = COLOR_SPACE_YCBCR709;
e7b07cee
HW		 1812 }
1813
3be5262e 1814 memset(&plane_state->tiling_info, 0, sizeof(plane_state->tiling_info));
e7b07cee 1815
b830ebc9
HW		 1816 /* Fill GFX8 params */
1817 if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == DC_ARRAY_2D_TILED_THIN1) {
1818 unsigned int bankw, bankh, mtaspect, tile_split, num_banks;
e7b07cee
HW		 1819
1820 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH);
1821 bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT);
1822 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT);
1823 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT);
1824 num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS);
1825
1826 /* XXX fix me for VI */
3be5262e
HW		 1827 plane_state->tiling_info.gfx8.num_banks = num_banks;
1828 plane_state->tiling_info.gfx8.array_mode =
e7b07cee 1829 DC_ARRAY_2D_TILED_THIN1;
3be5262e
HW		 1830 plane_state->tiling_info.gfx8.tile_split = tile_split;
1831 plane_state->tiling_info.gfx8.bank_width = bankw;
1832 plane_state->tiling_info.gfx8.bank_height = bankh;
1833 plane_state->tiling_info.gfx8.tile_aspect = mtaspect;
1834 plane_state->tiling_info.gfx8.tile_mode =
e7b07cee
HW		 1835 DC_ADDR_SURF_MICRO_TILING_DISPLAY;
1836 } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE)
1837 == DC_ARRAY_1D_TILED_THIN1) {
3be5262e 1838 plane_state->tiling_info.gfx8.array_mode = DC_ARRAY_1D_TILED_THIN1;
e7b07cee
HW		 1839 }
1840
3be5262e 1841 plane_state->tiling_info.gfx8.pipe_config =
e7b07cee
HW		 1842 AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG);
1843
1844 if (adev->asic_type == CHIP_VEGA10 ||
1845 adev->asic_type == CHIP_RAVEN) {
1846 /* Fill GFX9 params */
3be5262e 1847 plane_state->tiling_info.gfx9.num_pipes =
e7b07cee 1848 adev->gfx.config.gb_addr_config_fields.num_pipes;
3be5262e 1849 plane_state->tiling_info.gfx9.num_banks =
e7b07cee 1850 adev->gfx.config.gb_addr_config_fields.num_banks;
3be5262e 1851 plane_state->tiling_info.gfx9.pipe_interleave =
e7b07cee 1852 adev->gfx.config.gb_addr_config_fields.pipe_interleave_size;
3be5262e 1853 plane_state->tiling_info.gfx9.num_shader_engines =
e7b07cee 1854 adev->gfx.config.gb_addr_config_fields.num_se;
3be5262e 1855 plane_state->tiling_info.gfx9.max_compressed_frags =
e7b07cee 1856 adev->gfx.config.gb_addr_config_fields.max_compress_frags;
3be5262e 1857 plane_state->tiling_info.gfx9.num_rb_per_se =
e7b07cee 1858 adev->gfx.config.gb_addr_config_fields.num_rb_per_se;
3be5262e 1859 plane_state->tiling_info.gfx9.swizzle =
e7b07cee 1860 AMDGPU_TILING_GET(tiling_flags, SWIZZLE_MODE);
3be5262e 1861 plane_state->tiling_info.gfx9.shaderEnable = 1;
e7b07cee
HW		 1862 }
1863
3be5262e
HW		 1864 plane_state->visible = true;
1865 plane_state->scaling_quality.h_taps_c = 0;
1866 plane_state->scaling_quality.v_taps_c = 0;
e7b07cee 1867
3be5262e
HW		 1868 /* is this needed? is plane_state zeroed at allocation? */
1869 plane_state->scaling_quality.h_taps = 0;
1870 plane_state->scaling_quality.v_taps = 0;
1871 plane_state->stereo_format = PLANE_STEREO_FORMAT_NONE;
e7b07cee
HW		 1872
1873 return ret;
1874
1875}
1876
e7b07cee
HW		 1877static void fill_gamma_from_crtc_state(
1878 const struct drm_crtc_state *crtc_state,
3be5262e 1879 struct dc_plane_state *plane_state)
e7b07cee
HW		 1880{
1881 int i;
1882 struct dc_gamma *gamma;
d66cf5f5
AK		 1883 struct drm_color_lut *lut =
1884 (struct drm_color_lut *) crtc_state->gamma_lut->data;
e7b07cee
HW		 1885
1886 gamma = dc_create_gamma();
1887
1888 if (gamma == NULL) {
1889 WARN_ON(1);
1890 return;
1891 }
1892
d66cf5f5
AK		 1893 gamma->type = GAMMA_RGB_256_ENTRIES;
1894 for (i = 0; i < GAMMA_RGB_256_ENTRIES; i++) {
1895 gamma->entries.red[i] = dal_fixed31_32_from_int(lut[i].red);
1896 gamma->entries.green[i] = dal_fixed31_32_from_int(lut[i].green);
1897 gamma->entries.blue[i] = dal_fixed31_32_from_int(lut[i].blue);
e7b07cee
HW		 1898 }
1899
3be5262e 1900 plane_state->gamma_correction = gamma;
e7b07cee
HW		 1901}
1902
1903static int fill_plane_attributes(
1904 struct amdgpu_device *adev,
3be5262e 1905 struct dc_plane_state *dc_plane_state,
e7b07cee
HW		 1906 struct drm_plane_state *plane_state,
1907 struct drm_crtc_state *crtc_state,
1908 bool addrReq)
1909{
1910 const struct amdgpu_framebuffer *amdgpu_fb =
1911 to_amdgpu_framebuffer(plane_state->fb);
1912 const struct drm_crtc *crtc = plane_state->crtc;
1913 struct dc_transfer_func *input_tf;
1914 int ret = 0;
1915
3be5262e 1916 if (!fill_rects_from_plane_state(plane_state, dc_plane_state))
e7b07cee
HW		 1917 return -EINVAL;
1918
1919 ret = fill_plane_attributes_from_fb(
1920 crtc->dev->dev_private,
3be5262e 1921 dc_plane_state,
e7b07cee
HW		 1922 amdgpu_fb,
1923 addrReq);
1924
1925 if (ret)
1926 return ret;
1927
1928 input_tf = dc_create_transfer_func();
1929
1930 if (input_tf == NULL)
1931 return -ENOMEM;
1932
1933 input_tf->type = TF_TYPE_PREDEFINED;
1934 input_tf->tf = TRANSFER_FUNCTION_SRGB;
1935
3be5262e 1936 dc_plane_state->in_transfer_func = input_tf;
e7b07cee
HW		 1937
1938 /* In case of gamma set, update gamma value */
1939 if (crtc_state->gamma_lut)
3be5262e 1940 fill_gamma_from_crtc_state(crtc_state, dc_plane_state);
e7b07cee
HW		 1941
1942 return ret;
1943}
1944
1945/*****************************************************************************/
1946
1947struct amdgpu_connector *aconnector_from_drm_crtc_id(
1948 const struct drm_crtc *crtc)
1949{
1950 struct drm_device *dev = crtc->dev;
1951 struct drm_connector *connector;
1952 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
1953 struct amdgpu_connector *aconnector;
1954
1955 list_for_each_entry(connector,
1956 &dev->mode_config.connector_list, head) {
1957
1958 aconnector = to_amdgpu_connector(connector);
1959
1960 if (aconnector->base.state->crtc != &acrtc->base)
1961 continue;
1962
1963 /* Found the connector */
1964 return aconnector;
1965 }
1966
1967 /* If we get here, not found. */
1968 return NULL;
1969}
1970
1971static void update_stream_scaling_settings(
1972 const struct drm_display_mode *mode,
1973 const struct dm_connector_state *dm_state,
0971c40e 1974 struct dc_stream_state *stream)
e7b07cee
HW		 1975{
1976 enum amdgpu_rmx_type rmx_type;
1977
1978 struct rect src = { 0 }; /* viewport in composition space*/
1979 struct rect dst = { 0 }; /* stream addressable area */
1980
1981 /* no mode. nothing to be done */
1982 if (!mode)
1983 return;
1984
1985 /* Full screen scaling by default */
1986 src.width = mode->hdisplay;
1987 src.height = mode->vdisplay;
1988 dst.width = stream->timing.h_addressable;
1989 dst.height = stream->timing.v_addressable;
1990
1991 rmx_type = dm_state->scaling;
1992 if (rmx_type == RMX_ASPECT || rmx_type == RMX_OFF) {
1993 if (src.width * dst.height <
1994 src.height * dst.width) {
1995 /* height needs less upscaling/more downscaling */
1996 dst.width = src.width *
1997 dst.height / src.height;
1998 } else {
1999 /* width needs less upscaling/more downscaling */
2000 dst.height = src.height *
2001 dst.width / src.width;
2002 }
2003 } else if (rmx_type == RMX_CENTER) {
2004 dst = src;
2005 }
2006
2007 dst.x = (stream->timing.h_addressable - dst.width) / 2;
2008 dst.y = (stream->timing.v_addressable - dst.height) / 2;
2009
2010 if (dm_state->underscan_enable) {
2011 dst.x += dm_state->underscan_hborder / 2;
2012 dst.y += dm_state->underscan_vborder / 2;
2013 dst.width -= dm_state->underscan_hborder;
2014 dst.height -= dm_state->underscan_vborder;
2015 }
2016
2017 stream->src = src;
2018 stream->dst = dst;
2019
2020 DRM_DEBUG_KMS("Destination Rectangle x:%d y:%d width:%d height:%d\n",
2021 dst.x, dst.y, dst.width, dst.height);
2022
2023}
2024
2025static enum dc_color_depth convert_color_depth_from_display_info(
2026 const struct drm_connector *connector)
2027{
2028 uint32_t bpc = connector->display_info.bpc;
2029
2030 /* Limited color depth to 8bit
b830ebc9
HW		 2031 * TODO: Still need to handle deep color
2032 */
e7b07cee
HW		 2033 if (bpc > 8)
2034 bpc = 8;
2035
2036 switch (bpc) {
2037 case 0:
2038 /* Temporary Work around, DRM don't parse color depth for
2039 * EDID revision before 1.4
2040 * TODO: Fix edid parsing
2041 */
2042 return COLOR_DEPTH_888;
2043 case 6:
2044 return COLOR_DEPTH_666;
2045 case 8:
2046 return COLOR_DEPTH_888;
2047 case 10:
2048 return COLOR_DEPTH_101010;
2049 case 12:
2050 return COLOR_DEPTH_121212;
2051 case 14:
2052 return COLOR_DEPTH_141414;
2053 case 16:
2054 return COLOR_DEPTH_161616;
2055 default:
2056 return COLOR_DEPTH_UNDEFINED;
2057 }
2058}
2059
2060static enum dc_aspect_ratio get_aspect_ratio(
2061 const struct drm_display_mode *mode_in)
2062{
2063 int32_t width = mode_in->crtc_hdisplay * 9;
2064 int32_t height = mode_in->crtc_vdisplay * 16;
b830ebc9 2065
e7b07cee
HW		 2066 if ((width - height) < 10 && (width - height) > -10)
2067 return ASPECT_RATIO_16_9;
2068 else
2069 return ASPECT_RATIO_4_3;
2070}
2071
2072static enum dc_color_space get_output_color_space(
2073 const struct dc_crtc_timing *dc_crtc_timing)
2074{
2075 enum dc_color_space color_space = COLOR_SPACE_SRGB;
2076
2077 switch (dc_crtc_timing->pixel_encoding) {
2078 case PIXEL_ENCODING_YCBCR422:
2079 case PIXEL_ENCODING_YCBCR444:
2080 case PIXEL_ENCODING_YCBCR420:
2081 {
2082 /*
2083 * 27030khz is the separation point between HDTV and SDTV
2084 * according to HDMI spec, we use YCbCr709 and YCbCr601
2085 * respectively
2086 */
2087 if (dc_crtc_timing->pix_clk_khz > 27030) {
2088 if (dc_crtc_timing->flags.Y_ONLY)
2089 color_space =
2090 COLOR_SPACE_YCBCR709_LIMITED;
2091 else
2092 color_space = COLOR_SPACE_YCBCR709;
2093 } else {
2094 if (dc_crtc_timing->flags.Y_ONLY)
2095 color_space =
2096 COLOR_SPACE_YCBCR601_LIMITED;
2097 else
2098 color_space = COLOR_SPACE_YCBCR601;
2099 }
2100
2101 }
2102 break;
2103 case PIXEL_ENCODING_RGB:
2104 color_space = COLOR_SPACE_SRGB;
2105 break;
2106
2107 default:
2108 WARN_ON(1);
2109 break;
2110 }
2111
2112 return color_space;
2113}
2114
2115/*****************************************************************************/
2116
2117static void fill_stream_properties_from_drm_display_mode(
0971c40e 2118 struct dc_stream_state *stream,
e7b07cee
HW		 2119 const struct drm_display_mode *mode_in,
2120 const struct drm_connector *connector)
2121{
2122 struct dc_crtc_timing *timing_out = &stream->timing;
b830ebc9 2123
e7b07cee
HW		 2124 memset(timing_out, 0, sizeof(struct dc_crtc_timing));
2125
2126 timing_out->h_border_left = 0;
2127 timing_out->h_border_right = 0;
2128 timing_out->v_border_top = 0;
2129 timing_out->v_border_bottom = 0;
2130 /* TODO: un-hardcode */
2131
2132 if ((connector->display_info.color_formats & DRM_COLOR_FORMAT_YCRCB444)
2133 && stream->sink->sink_signal == SIGNAL_TYPE_HDMI_TYPE_A)
2134 timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR444;
2135 else
2136 timing_out->pixel_encoding = PIXEL_ENCODING_RGB;
2137
2138 timing_out->timing_3d_format = TIMING_3D_FORMAT_NONE;
2139 timing_out->display_color_depth = convert_color_depth_from_display_info(
2140 connector);
2141 timing_out->scan_type = SCANNING_TYPE_NODATA;
2142 timing_out->hdmi_vic = 0;
2143 timing_out->vic = drm_match_cea_mode(mode_in);
2144
2145 timing_out->h_addressable = mode_in->crtc_hdisplay;
2146 timing_out->h_total = mode_in->crtc_htotal;
2147 timing_out->h_sync_width =
2148 mode_in->crtc_hsync_end - mode_in->crtc_hsync_start;
2149 timing_out->h_front_porch =
2150 mode_in->crtc_hsync_start - mode_in->crtc_hdisplay;
2151 timing_out->v_total = mode_in->crtc_vtotal;
2152 timing_out->v_addressable = mode_in->crtc_vdisplay;
2153 timing_out->v_front_porch =
2154 mode_in->crtc_vsync_start - mode_in->crtc_vdisplay;
2155 timing_out->v_sync_width =
2156 mode_in->crtc_vsync_end - mode_in->crtc_vsync_start;
2157 timing_out->pix_clk_khz = mode_in->crtc_clock;
2158 timing_out->aspect_ratio = get_aspect_ratio(mode_in);
2159 if (mode_in->flags & DRM_MODE_FLAG_PHSYNC)
2160 timing_out->flags.HSYNC_POSITIVE_POLARITY = 1;
2161 if (mode_in->flags & DRM_MODE_FLAG_PVSYNC)
2162 timing_out->flags.VSYNC_POSITIVE_POLARITY = 1;
2163
2164 stream->output_color_space = get_output_color_space(timing_out);
2165
2166 {
2167 struct dc_transfer_func *tf = dc_create_transfer_func();
b830ebc9 2168
e7b07cee
HW		 2169 tf->type = TF_TYPE_PREDEFINED;
2170 tf->tf = TRANSFER_FUNCTION_SRGB;
2171 stream->out_transfer_func = tf;
2172 }
2173}
2174
2175static void fill_audio_info(
2176 struct audio_info *audio_info,
2177 const struct drm_connector *drm_connector,
2178 const struct dc_sink *dc_sink)
2179{
2180 int i = 0;
2181 int cea_revision = 0;
2182 const struct dc_edid_caps *edid_caps = &dc_sink->edid_caps;
2183
2184 audio_info->manufacture_id = edid_caps->manufacturer_id;
2185 audio_info->product_id = edid_caps->product_id;
2186
2187 cea_revision = drm_connector->display_info.cea_rev;
2188
2189 while (i < AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS &&
2190 edid_caps->display_name[i]) {
2191 audio_info->display_name[i] = edid_caps->display_name[i];
2192 i++;
2193 }
2194
b830ebc9 2195 if (cea_revision >= 3) {
e7b07cee
HW		 2196 audio_info->mode_count = edid_caps->audio_mode_count;
2197
2198 for (i = 0; i < audio_info->mode_count; ++i) {
2199 audio_info->modes[i].format_code =
2200 (enum audio_format_code)
2201 (edid_caps->audio_modes[i].format_code);
2202 audio_info->modes[i].channel_count =
2203 edid_caps->audio_modes[i].channel_count;
2204 audio_info->modes[i].sample_rates.all =
2205 edid_caps->audio_modes[i].sample_rate;
2206 audio_info->modes[i].sample_size =
2207 edid_caps->audio_modes[i].sample_size;
2208 }
2209 }
2210
2211 audio_info->flags.all = edid_caps->speaker_flags;
2212
2213 /* TODO: We only check for the progressive mode, check for interlace mode too */
b830ebc9 2214 if (drm_connector->latency_present[0]) {
e7b07cee
HW		 2215 audio_info->video_latency = drm_connector->video_latency[0];
2216 audio_info->audio_latency = drm_connector->audio_latency[0];
2217 }
2218
2219 /* TODO: For DP, video and audio latency should be calculated from DPCD caps */
2220
2221}
2222
2223static void copy_crtc_timing_for_drm_display_mode(
2224 const struct drm_display_mode *src_mode,
2225 struct drm_display_mode *dst_mode)
2226{
2227 dst_mode->crtc_hdisplay = src_mode->crtc_hdisplay;
2228 dst_mode->crtc_vdisplay = src_mode->crtc_vdisplay;
2229 dst_mode->crtc_clock = src_mode->crtc_clock;
2230 dst_mode->crtc_hblank_start = src_mode->crtc_hblank_start;
2231 dst_mode->crtc_hblank_end = src_mode->crtc_hblank_end;
b830ebc9 2232 dst_mode->crtc_hsync_start = src_mode->crtc_hsync_start;
e7b07cee
HW		 2233 dst_mode->crtc_hsync_end = src_mode->crtc_hsync_end;
2234 dst_mode->crtc_htotal = src_mode->crtc_htotal;
2235 dst_mode->crtc_hskew = src_mode->crtc_hskew;
2236 dst_mode->crtc_vblank_start = src_mode->crtc_vblank_start;
2237 dst_mode->crtc_vblank_end = src_mode->crtc_vblank_end;
2238 dst_mode->crtc_vsync_start = src_mode->crtc_vsync_start;
2239 dst_mode->crtc_vsync_end = src_mode->crtc_vsync_end;
2240 dst_mode->crtc_vtotal = src_mode->crtc_vtotal;
2241}
2242
2243static void decide_crtc_timing_for_drm_display_mode(
2244 struct drm_display_mode *drm_mode,
2245 const struct drm_display_mode *native_mode,
2246 bool scale_enabled)
2247{
2248 if (scale_enabled) {
2249 copy_crtc_timing_for_drm_display_mode(native_mode, drm_mode);
2250 } else if (native_mode->clock == drm_mode->clock &&
2251 native_mode->htotal == drm_mode->htotal &&
2252 native_mode->vtotal == drm_mode->vtotal) {
2253 copy_crtc_timing_for_drm_display_mode(native_mode, drm_mode);
2254 } else {
2255 /* no scaling nor amdgpu inserted, no need to patch */
2256 }
2257}
2258
0971c40e 2259static struct dc_stream_state *create_stream_for_sink(
e7b07cee
HW		 2260 struct amdgpu_connector *aconnector,
2261 const struct drm_display_mode *drm_mode,
2262 const struct dm_connector_state *dm_state)
2263{
2264 struct drm_display_mode *preferred_mode = NULL;
2265 const struct drm_connector *drm_connector;
0971c40e 2266 struct dc_stream_state *stream = NULL;
e7b07cee
HW		 2267 struct drm_display_mode mode = *drm_mode;
2268 bool native_mode_found = false;
2269
b830ebc9 2270 if (aconnector == NULL) {
e7b07cee
HW		 2271 DRM_ERROR("aconnector is NULL!\n");
2272 goto drm_connector_null;
2273 }
2274
b830ebc9 2275 if (dm_state == NULL) {
e7b07cee
HW		 2276 DRM_ERROR("dm_state is NULL!\n");
2277 goto dm_state_null;
2278 }
4562236b 2279
e7b07cee
HW		 2280 drm_connector = &aconnector->base;
2281 stream = dc_create_stream_for_sink(aconnector->dc_sink);
4562236b 2282
b830ebc9 2283 if (stream == NULL) {
e7b07cee
HW		 2284 DRM_ERROR("Failed to create stream for sink!\n");
2285 goto stream_create_fail;
2286 }
2287
2288 list_for_each_entry(preferred_mode, &aconnector->base.modes, head) {
2289 /* Search for preferred mode */
2290 if (preferred_mode->type & DRM_MODE_TYPE_PREFERRED) {
2291 native_mode_found = true;
2292 break;
2293 }
2294 }
2295 if (!native_mode_found)
2296 preferred_mode = list_first_entry_or_null(
2297 &aconnector->base.modes,
2298 struct drm_display_mode,
2299 head);
2300
b830ebc9 2301 if (preferred_mode == NULL) {
e7b07cee
HW		 2302 /* This may not be an error, the use case is when we we have no
2303 * usermode calls to reset and set mode upon hotplug. In this
2304 * case, we call set mode ourselves to restore the previous mode
2305 * and the modelist may not be filled in in time.
2306 */
2307 DRM_INFO("No preferred mode found\n");
2308 } else {
2309 decide_crtc_timing_for_drm_display_mode(
2310 &mode, preferred_mode,
2311 dm_state->scaling != RMX_OFF);
2312 }
2313
2314 fill_stream_properties_from_drm_display_mode(stream,
2315 &mode, &aconnector->base);
2316 update_stream_scaling_settings(&mode, dm_state, stream);
2317
2318 fill_audio_info(
2319 &stream->audio_info,
2320 drm_connector,
2321 aconnector->dc_sink);
2322
2323stream_create_fail:
2324dm_state_null:
2325drm_connector_null:
2326 return stream;
2327}
2328
2329void amdgpu_dm_crtc_destroy(struct drm_crtc *crtc)
2330{
2331 drm_crtc_cleanup(crtc);
2332 kfree(crtc);
2333}
2334
2335static void dm_crtc_destroy_state(struct drm_crtc *crtc,
2336 struct drm_crtc_state *state)
2337{
2338 struct dm_crtc_state *cur = to_dm_crtc_state(state);
2339
2340 /* TODO Destroy dc_stream objects are stream object is flattened */
2341 if (cur->stream)
2342 dc_stream_release(cur->stream);
2343
2344
2345 __drm_atomic_helper_crtc_destroy_state(state);
2346
2347
2348 kfree(state);
2349}
2350
2351static void dm_crtc_reset_state(struct drm_crtc *crtc)
2352{
2353 struct dm_crtc_state *state;
2354
2355 if (crtc->state)
2356 dm_crtc_destroy_state(crtc, crtc->state);
2357
2358 state = kzalloc(sizeof(*state), GFP_KERNEL);
2359 if (WARN_ON(!state))
2360 return;
2361
2362 crtc->state = &state->base;
2363 crtc->state->crtc = crtc;
2364
2365}
2366
2367static struct drm_crtc_state *
2368dm_crtc_duplicate_state(struct drm_crtc *crtc)
2369{
2370 struct dm_crtc_state *state, *cur;
2371
2372 cur = to_dm_crtc_state(crtc->state);
2373
2374 if (WARN_ON(!crtc->state))
2375 return NULL;
2376
2377 state = dm_alloc(sizeof(*state));
2378
2379 __drm_atomic_helper_crtc_duplicate_state(crtc, &state->base);
2380
2381 if (cur->stream) {
2382 state->stream = cur->stream;
2383 dc_stream_retain(state->stream);
2384 }
2385
2386 /* TODO Duplicate dc_stream after objects are stream object is flattened */
2387
2388 return &state->base;
2389}
2390
2391/* Implemented only the options currently availible for the driver */
2392static const struct drm_crtc_funcs amdgpu_dm_crtc_funcs = {
2393 .reset = dm_crtc_reset_state,
2394 .destroy = amdgpu_dm_crtc_destroy,
2395 .gamma_set = drm_atomic_helper_legacy_gamma_set,
2396 .set_config = drm_atomic_helper_set_config,
2397 .page_flip = drm_atomic_helper_page_flip,
2398 .atomic_duplicate_state = dm_crtc_duplicate_state,
2399 .atomic_destroy_state = dm_crtc_destroy_state,
2400};
2401
2402static enum drm_connector_status
2403amdgpu_dm_connector_detect(struct drm_connector *connector, bool force)
2404{
2405 bool connected;
2406 struct amdgpu_connector *aconnector = to_amdgpu_connector(connector);
2407
2408 /* Notes:
2409 * 1. This interface is NOT called in context of HPD irq.
2410 * 2. This interface *is called* in context of user-mode ioctl. Which
2411 * makes it a bad place for *any* MST-related activit. */
2412
2413 if (aconnector->base.force == DRM_FORCE_UNSPECIFIED)
2414 connected = (aconnector->dc_sink != NULL);
2415 else
2416 connected = (aconnector->base.force == DRM_FORCE_ON);
2417
2418 return (connected ? connector_status_connected :
2419 connector_status_disconnected);
2420}
2421
2422int amdgpu_dm_connector_atomic_set_property(
2423 struct drm_connector *connector,
2424 struct drm_connector_state *connector_state,
2425 struct drm_property *property,
2426 uint64_t val)
2427{
2428 struct drm_device *dev = connector->dev;
2429 struct amdgpu_device *adev = dev->dev_private;
2430 struct dm_connector_state *dm_old_state =
2431 to_dm_connector_state(connector->state);
2432 struct dm_connector_state *dm_new_state =
2433 to_dm_connector_state(connector_state);
2434
2435 int ret = -EINVAL;
2436
2437 if (property == dev->mode_config.scaling_mode_property) {
2438 enum amdgpu_rmx_type rmx_type;
2439
2440 switch (val) {
2441 case DRM_MODE_SCALE_CENTER:
2442 rmx_type = RMX_CENTER;
2443 break;
2444 case DRM_MODE_SCALE_ASPECT:
2445 rmx_type = RMX_ASPECT;
2446 break;
2447 case DRM_MODE_SCALE_FULLSCREEN:
2448 rmx_type = RMX_FULL;
2449 break;
2450 case DRM_MODE_SCALE_NONE:
2451 default:
2452 rmx_type = RMX_OFF;
2453 break;
2454 }
2455
2456 if (dm_old_state->scaling == rmx_type)
2457 return 0;
2458
2459 dm_new_state->scaling = rmx_type;
2460 ret = 0;
2461 } else if (property == adev->mode_info.underscan_hborder_property) {
2462 dm_new_state->underscan_hborder = val;
2463 ret = 0;
2464 } else if (property == adev->mode_info.underscan_vborder_property) {
2465 dm_new_state->underscan_vborder = val;
2466 ret = 0;
2467 } else if (property == adev->mode_info.underscan_property) {
2468 dm_new_state->underscan_enable = val;
2469 ret = 0;
2470 }
2471
2472 return ret;
2473}
2474
2475int amdgpu_dm_connector_atomic_get_property(
2476 struct drm_connector *connector,
2477 const struct drm_connector_state *state,
2478 struct drm_property *property,
2479 uint64_t *val)
2480{
2481 struct drm_device *dev = connector->dev;
2482 struct amdgpu_device *adev = dev->dev_private;
2483 struct dm_connector_state *dm_state =
2484 to_dm_connector_state(state);
2485 int ret = -EINVAL;
2486
2487 if (property == dev->mode_config.scaling_mode_property) {
2488 switch (dm_state->scaling) {
2489 case RMX_CENTER:
2490 *val = DRM_MODE_SCALE_CENTER;
2491 break;
2492 case RMX_ASPECT:
2493 *val = DRM_MODE_SCALE_ASPECT;
2494 break;
2495 case RMX_FULL:
2496 *val = DRM_MODE_SCALE_FULLSCREEN;
2497 break;
2498 case RMX_OFF:
2499 default:
2500 *val = DRM_MODE_SCALE_NONE;
2501 break;
2502 }
2503 ret = 0;
2504 } else if (property == adev->mode_info.underscan_hborder_property) {
2505 *val = dm_state->underscan_hborder;
2506 ret = 0;
2507 } else if (property == adev->mode_info.underscan_vborder_property) {
2508 *val = dm_state->underscan_vborder;
2509 ret = 0;
2510 } else if (property == adev->mode_info.underscan_property) {
2511 *val = dm_state->underscan_enable;
2512 ret = 0;
2513 }
2514 return ret;
2515}
2516
2517void amdgpu_dm_connector_destroy(struct drm_connector *connector)
2518{
2519 struct amdgpu_connector *aconnector = to_amdgpu_connector(connector);
2520 const struct dc_link *link = aconnector->dc_link;
2521 struct amdgpu_device *adev = connector->dev->dev_private;
2522 struct amdgpu_display_manager *dm = &adev->dm;
2523#if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) ||\
2524 defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
2525
2526 if (link->connector_signal & (SIGNAL_TYPE_EDP | SIGNAL_TYPE_LVDS)) {
2527 amdgpu_dm_register_backlight_device(dm);
2528
2529 if (dm->backlight_dev) {
2530 backlight_device_unregister(dm->backlight_dev);
2531 dm->backlight_dev = NULL;
2532 }
2533
2534 }
2535#endif
2536 drm_connector_unregister(connector);
2537 drm_connector_cleanup(connector);
2538 kfree(connector);
2539}
2540
2541void amdgpu_dm_connector_funcs_reset(struct drm_connector *connector)
2542{
2543 struct dm_connector_state *state =
2544 to_dm_connector_state(connector->state);
2545
2546 kfree(state);
2547
2548 state = kzalloc(sizeof(*state), GFP_KERNEL);
2549
2550 if (state) {
2551 state->scaling = RMX_OFF;
2552 state->underscan_enable = false;
2553 state->underscan_hborder = 0;
2554 state->underscan_vborder = 0;
2555
2556 connector->state = &state->base;
2557 connector->state->connector = connector;
2558 }
2559}
2560
2561struct drm_connector_state *amdgpu_dm_connector_atomic_duplicate_state(
2562 struct drm_connector *connector)
2563{
2564 struct dm_connector_state *state =
2565 to_dm_connector_state(connector->state);
2566
2567 struct dm_connector_state *new_state =
2568 kmemdup(state, sizeof(*state), GFP_KERNEL);
2569
2570 if (new_state) {
2571 __drm_atomic_helper_connector_duplicate_state(connector,
2572 &new_state->base);
2573 return &new_state->base;
2574 }
2575
2576 return NULL;
2577}
2578
2579static const struct drm_connector_funcs amdgpu_dm_connector_funcs = {
2580 .reset = amdgpu_dm_connector_funcs_reset,
2581 .detect = amdgpu_dm_connector_detect,
2582 .fill_modes = drm_helper_probe_single_connector_modes,
2583 .destroy = amdgpu_dm_connector_destroy,
2584 .atomic_duplicate_state = amdgpu_dm_connector_atomic_duplicate_state,
2585 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
2586 .atomic_set_property = amdgpu_dm_connector_atomic_set_property,
2587 .atomic_get_property = amdgpu_dm_connector_atomic_get_property
2588};
2589
2590static struct drm_encoder *best_encoder(struct drm_connector *connector)
2591{
2592 int enc_id = connector->encoder_ids[0];
2593 struct drm_mode_object *obj;
2594 struct drm_encoder *encoder;
2595
2596 DRM_DEBUG_KMS("Finding the best encoder\n");
2597
2598 /* pick the encoder ids */
2599 if (enc_id) {
2600 obj = drm_mode_object_find(connector->dev, enc_id, DRM_MODE_OBJECT_ENCODER);
2601 if (!obj) {
2602 DRM_ERROR("Couldn't find a matching encoder for our connector\n");
2603 return NULL;
2604 }
2605 encoder = obj_to_encoder(obj);
2606 return encoder;
2607 }
2608 DRM_ERROR("No encoder id\n");
2609 return NULL;
2610}
2611
2612static int get_modes(struct drm_connector *connector)
2613{
2614 return amdgpu_dm_connector_get_modes(connector);
2615}
2616
2617static void create_eml_sink(struct amdgpu_connector *aconnector)
2618{
2619 struct dc_sink_init_data init_params = {
2620 .link = aconnector->dc_link,
2621 .sink_signal = SIGNAL_TYPE_VIRTUAL
2622 };
2623 struct edid *edid = (struct edid *) aconnector->base.edid_blob_ptr->data;
2624
2625 if (!aconnector->base.edid_blob_ptr ||
2626 !aconnector->base.edid_blob_ptr->data) {
2627 DRM_ERROR("No EDID firmware found on connector: %s ,forcing to OFF!\n",
2628 aconnector->base.name);
2629
2630 aconnector->base.force = DRM_FORCE_OFF;
2631 aconnector->base.override_edid = false;
2632 return;
2633 }
2634
2635 aconnector->edid = edid;
2636
2637 aconnector->dc_em_sink = dc_link_add_remote_sink(
2638 aconnector->dc_link,
2639 (uint8_t *)edid,
2640 (edid->extensions + 1) * EDID_LENGTH,
2641 &init_params);
2642
2643 if (aconnector->base.force
2644 == DRM_FORCE_ON)
2645 aconnector->dc_sink = aconnector->dc_link->local_sink ?
2646 aconnector->dc_link->local_sink :
2647 aconnector->dc_em_sink;
2648}
2649
2650static void handle_edid_mgmt(struct amdgpu_connector *aconnector)
2651{
2652 struct dc_link *link = (struct dc_link *)aconnector->dc_link;
2653
2654 /* In case of headless boot with force on for DP managed connector
2655 * Those settings have to be != 0 to get initial modeset
2656 */
2657 if (link->connector_signal == SIGNAL_TYPE_DISPLAY_PORT) {
2658 link->verified_link_cap.lane_count = LANE_COUNT_FOUR;
2659 link->verified_link_cap.link_rate = LINK_RATE_HIGH2;
2660 }
2661
2662
2663 aconnector->base.override_edid = true;
2664 create_eml_sink(aconnector);
2665}
2666
2667int amdgpu_dm_connector_mode_valid(
2668 struct drm_connector *connector,
2669 struct drm_display_mode *mode)
2670{
2671 int result = MODE_ERROR;
2672 struct dc_sink *dc_sink;
2673 struct amdgpu_device *adev = connector->dev->dev_private;
2674 /* TODO: Unhardcode stream count */
0971c40e 2675 struct dc_stream_state *stream;
e7b07cee
HW		 2676 struct amdgpu_connector *aconnector = to_amdgpu_connector(connector);
2677
2678 if ((mode->flags & DRM_MODE_FLAG_INTERLACE) ||
2679 (mode->flags & DRM_MODE_FLAG_DBLSCAN))
2680 return result;
2681
2682 /* Only run this the first time mode_valid is called to initilialize
2683 * EDID mgmt
2684 */
2685 if (aconnector->base.force != DRM_FORCE_UNSPECIFIED &&
2686 !aconnector->dc_em_sink)
2687 handle_edid_mgmt(aconnector);
2688
2689 dc_sink = to_amdgpu_connector(connector)->dc_sink;
2690
b830ebc9 2691 if (dc_sink == NULL) {
e7b07cee
HW		 2692 DRM_ERROR("dc_sink is NULL!\n");
2693 goto fail;
2694 }
2695
2696 stream = dc_create_stream_for_sink(dc_sink);
b830ebc9 2697 if (stream == NULL) {
e7b07cee
HW		 2698 DRM_ERROR("Failed to create stream for sink!\n");
2699 goto fail;
2700 }
2701
2702 drm_mode_set_crtcinfo(mode, 0);
2703 fill_stream_properties_from_drm_display_mode(stream, mode, connector);
2704
2705 stream->src.width = mode->hdisplay;
2706 stream->src.height = mode->vdisplay;
2707 stream->dst = stream->src;
2708
2709 if (dc_validate_stream(adev->dm.dc, stream))
2710 result = MODE_OK;
2711
2712 dc_stream_release(stream);
2713
2714fail:
2715 /* TODO: error handling*/
2716 return result;
2717}
2718
2719static const struct drm_connector_helper_funcs
2720amdgpu_dm_connector_helper_funcs = {
2721 /*
b830ebc9
HW		 2722 * If hotplug a second bigger display in FB Con mode, bigger resolution
2723 * modes will be filtered by drm_mode_validate_size(), and those modes
2724 * is missing after user start lightdm. So we need to renew modes list.
2725 * in get_modes call back, not just return the modes count
2726 */
e7b07cee
HW		 2727 .get_modes = get_modes,
2728 .mode_valid = amdgpu_dm_connector_mode_valid,
2729 .best_encoder = best_encoder
2730};
2731
2732static void dm_crtc_helper_disable(struct drm_crtc *crtc)
2733{
2734}
2735
2736static int dm_crtc_helper_atomic_check(
2737 struct drm_crtc *crtc,
2738 struct drm_crtc_state *state)
2739{
2740 struct amdgpu_device *adev = crtc->dev->dev_private;
2741 struct dc *dc = adev->dm.dc;
2742 struct dm_crtc_state *dm_crtc_state = to_dm_crtc_state(state);
2743 int ret = -EINVAL;
2744
9b690ef3
BL		 2745 if (unlikely(!dm_crtc_state->stream &&
2746 modeset_required(state, NULL, dm_crtc_state->stream))) {
e7b07cee
HW		 2747 WARN_ON(1);
2748 return ret;
2749 }
2750
2751 /* In some use cases, like reset, no stream is attached */
2752 if (!dm_crtc_state->stream)
2753 return 0;
2754
2755 if (dc_validate_stream(dc, dm_crtc_state->stream))
2756 return 0;
2757
2758 return ret;
2759}
2760
2761static bool dm_crtc_helper_mode_fixup(
2762 struct drm_crtc *crtc,
2763 const struct drm_display_mode *mode,
2764 struct drm_display_mode *adjusted_mode)
2765{
2766 return true;
2767}
2768
2769static const struct drm_crtc_helper_funcs amdgpu_dm_crtc_helper_funcs = {
2770 .disable = dm_crtc_helper_disable,
2771 .atomic_check = dm_crtc_helper_atomic_check,
2772 .mode_fixup = dm_crtc_helper_mode_fixup
2773};
2774
2775static void dm_encoder_helper_disable(struct drm_encoder *encoder)
2776{
2777
2778}
2779
2780static int dm_encoder_helper_atomic_check(
2781 struct drm_encoder *encoder,
2782 struct drm_crtc_state *crtc_state,
2783 struct drm_connector_state *conn_state)
2784{
2785 return 0;
2786}
2787
2788const struct drm_encoder_helper_funcs amdgpu_dm_encoder_helper_funcs = {
2789 .disable = dm_encoder_helper_disable,
2790 .atomic_check = dm_encoder_helper_atomic_check
2791};
2792
2793static void dm_drm_plane_reset(struct drm_plane *plane)
2794{
2795 struct dm_plane_state *amdgpu_state = NULL;
2796
2797 if (plane->state)
2798 plane->funcs->atomic_destroy_state(plane, plane->state);
2799
2800 amdgpu_state = kzalloc(sizeof(*amdgpu_state), GFP_KERNEL);
2801
2802 if (amdgpu_state) {
2803 plane->state = &amdgpu_state->base;
2804 plane->state->plane = plane;
2805 plane->state->rotation = DRM_MODE_ROTATE_0;
2806 } else
2807 WARN_ON(1);
2808}
2809
2810static struct drm_plane_state *
2811dm_drm_plane_duplicate_state(struct drm_plane *plane)
2812{
2813 struct dm_plane_state *dm_plane_state, *old_dm_plane_state;
2814
2815 old_dm_plane_state = to_dm_plane_state(plane->state);
2816 dm_plane_state = kzalloc(sizeof(*dm_plane_state), GFP_KERNEL);
2817 if (!dm_plane_state)
2818 return NULL;
2819
2820 __drm_atomic_helper_plane_duplicate_state(plane, &dm_plane_state->base);
2821
3be5262e
HW		 2822 if (old_dm_plane_state->dc_state) {
2823 dm_plane_state->dc_state = old_dm_plane_state->dc_state;
2824 dc_plane_state_retain(dm_plane_state->dc_state);
e7b07cee
HW		 2825 }
2826
2827 return &dm_plane_state->base;
2828}
2829
2830void dm_drm_plane_destroy_state(struct drm_plane *plane,
2831 struct drm_plane_state *state)
2832{
2833 struct dm_plane_state *dm_plane_state = to_dm_plane_state(state);
2834
3be5262e
HW		 2835 if (dm_plane_state->dc_state)
2836 dc_plane_state_release(dm_plane_state->dc_state);
e7b07cee 2837
0627bbd3 2838 drm_atomic_helper_plane_destroy_state(plane, state);
e7b07cee
HW		 2839}
2840
2841static const struct drm_plane_funcs dm_plane_funcs = {
2842 .update_plane = drm_atomic_helper_update_plane,
2843 .disable_plane = drm_atomic_helper_disable_plane,
2844 .destroy = drm_plane_cleanup,
2845 .reset = dm_drm_plane_reset,
2846 .atomic_duplicate_state = dm_drm_plane_duplicate_state,
2847 .atomic_destroy_state = dm_drm_plane_destroy_state,
2848};
2849
2850static int dm_plane_helper_prepare_fb(
2851 struct drm_plane *plane,
2852 struct drm_plane_state *new_state)
2853{
2854 struct amdgpu_framebuffer *afb;
2855 struct drm_gem_object *obj;
2856 struct amdgpu_bo *rbo;
2857 int r;
2858 struct dm_plane_state *dm_plane_state_new, *dm_plane_state_old;
2859 unsigned int awidth;
2860
2861 dm_plane_state_old = to_dm_plane_state(plane->state);
2862 dm_plane_state_new = to_dm_plane_state(new_state);
2863
2864 if (!new_state->fb) {
2865 DRM_DEBUG_KMS("No FB bound\n");
2866 return 0;
2867 }
2868
2869 afb = to_amdgpu_framebuffer(new_state->fb);
2870
2871 obj = afb->obj;
2872 rbo = gem_to_amdgpu_bo(obj);
2873 r = amdgpu_bo_reserve(rbo, false);
2874 if (unlikely(r != 0))
2875 return r;
2876
2877 r = amdgpu_bo_pin(rbo, AMDGPU_GEM_DOMAIN_VRAM, &afb->address);
2878
2879
2880 amdgpu_bo_unreserve(rbo);
2881
2882 if (unlikely(r != 0)) {
2883 DRM_ERROR("Failed to pin framebuffer\n");
2884 return r;
2885 }
2886
2887 amdgpu_bo_ref(rbo);
2888
3be5262e
HW		 2889 if (dm_plane_state_new->dc_state &&
2890 dm_plane_state_old->dc_state != dm_plane_state_new->dc_state) {
2891 struct dc_plane_state *plane_state = dm_plane_state_new->dc_state;
e7b07cee 2892
3be5262e
HW		 2893 if (plane_state->format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) {
2894 plane_state->address.grph.addr.low_part = lower_32_bits(afb->address);
2895 plane_state->address.grph.addr.high_part = upper_32_bits(afb->address);
e7b07cee
HW		 2896 } else {
2897 awidth = ALIGN(new_state->fb->width, 64);
3be5262e 2898 plane_state->address.video_progressive.luma_addr.low_part
e7b07cee 2899 = lower_32_bits(afb->address);
3be5262e 2900 plane_state->address.video_progressive.chroma_addr.low_part
e7b07cee
HW		 2901 = lower_32_bits(afb->address) +
2902 (awidth * new_state->fb->height);
2903 }
2904 }
2905
2906 /* It's a hack for s3 since in 4.9 kernel filter out cursor buffer
2907 * prepare and cleanup in drm_atomic_helper_prepare_planes
2908 * and drm_atomic_helper_cleanup_planes because fb doens't in s3.
2909 * IN 4.10 kernel this code should be removed and amdgpu_device_suspend
2910 * code touching fram buffers should be avoided for DC.
2911 */
2912 if (plane->type == DRM_PLANE_TYPE_CURSOR) {
2913 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(new_state->crtc);
2914
2915 acrtc->cursor_bo = obj;
2916 }
2917 return 0;
2918}
2919
2920static void dm_plane_helper_cleanup_fb(
2921 struct drm_plane *plane,
2922 struct drm_plane_state *old_state)
2923{
2924 struct amdgpu_bo *rbo;
2925 struct amdgpu_framebuffer *afb;
2926 int r;
2927
2928 if (!old_state->fb)
2929 return;
2930
2931 afb = to_amdgpu_framebuffer(old_state->fb);
2932 rbo = gem_to_amdgpu_bo(afb->obj);
2933 r = amdgpu_bo_reserve(rbo, false);
2934 if (unlikely(r)) {
2935 DRM_ERROR("failed to reserve rbo before unpin\n");
2936 return;
b830ebc9
HW		 2937 }
2938
2939 amdgpu_bo_unpin(rbo);
2940 amdgpu_bo_unreserve(rbo);
2941 amdgpu_bo_unref(&rbo);
e7b07cee
HW		 2942}
2943
2944int dm_create_validation_set_for_connector(struct drm_connector *connector,
2945 struct drm_display_mode *mode, struct dc_validation_set *val_set)
2946{
2947 int result = MODE_ERROR;
2948 struct dc_sink *dc_sink =
2949 to_amdgpu_connector(connector)->dc_sink;
2950 /* TODO: Unhardcode stream count */
0971c40e 2951 struct dc_stream_state *stream;
e7b07cee
HW		 2952
2953 if ((mode->flags & DRM_MODE_FLAG_INTERLACE) ||
2954 (mode->flags & DRM_MODE_FLAG_DBLSCAN))
2955 return result;
2956
b830ebc9 2957 if (dc_sink == NULL) {
e7b07cee
HW		 2958 DRM_ERROR("dc_sink is NULL!\n");
2959 return result;
2960 }
2961
2962 stream = dc_create_stream_for_sink(dc_sink);
2963
b830ebc9 2964 if (stream == NULL) {
e7b07cee
HW		 2965 DRM_ERROR("Failed to create stream for sink!\n");
2966 return result;
2967 }
2968
2969 drm_mode_set_crtcinfo(mode, 0);
2970
2971 fill_stream_properties_from_drm_display_mode(stream, mode, connector);
2972
2973 val_set->stream = stream;
2974
2975 stream->src.width = mode->hdisplay;
2976 stream->src.height = mode->vdisplay;
2977 stream->dst = stream->src;
2978
2979 return MODE_OK;
2980}
2981
cbd19488
AG		 2982int dm_plane_atomic_check(struct drm_plane *plane,
2983 struct drm_plane_state *state)
2984{
2985 struct amdgpu_device *adev = plane->dev->dev_private;
2986 struct dc *dc = adev->dm.dc;
2987 struct dm_plane_state *dm_plane_state = to_dm_plane_state(state);
2988
3be5262e 2989 if (!dm_plane_state->dc_state)
9a3329b1 2990 return 0;
cbd19488 2991
3be5262e 2992 if (dc_validate_plane(dc, dm_plane_state->dc_state))
cbd19488
AG		 2993 return 0;
2994
2995 return -EINVAL;
2996}
2997
e7b07cee
HW		 2998static const struct drm_plane_helper_funcs dm_plane_helper_funcs = {
2999 .prepare_fb = dm_plane_helper_prepare_fb,
3000 .cleanup_fb = dm_plane_helper_cleanup_fb,
cbd19488 3001 .atomic_check = dm_plane_atomic_check,
e7b07cee
HW		 3002};
3003
3004/*
3005 * TODO: these are currently initialized to rgb formats only.
3006 * For future use cases we should either initialize them dynamically based on
3007 * plane capabilities, or initialize this array to all formats, so internal drm
3008 * check will succeed, and let DC to implement proper check
3009 */
3010static uint32_t rgb_formats[] = {
3011 DRM_FORMAT_RGB888,
3012 DRM_FORMAT_XRGB8888,
3013 DRM_FORMAT_ARGB8888,
3014 DRM_FORMAT_RGBA8888,
3015 DRM_FORMAT_XRGB2101010,
3016 DRM_FORMAT_XBGR2101010,
3017 DRM_FORMAT_ARGB2101010,
3018 DRM_FORMAT_ABGR2101010,
3019};
3020
3021static uint32_t yuv_formats[] = {
3022 DRM_FORMAT_NV12,
3023 DRM_FORMAT_NV21,
3024};
3025
3026static const u32 cursor_formats[] = {
3027 DRM_FORMAT_ARGB8888
3028};
3029
3030int amdgpu_dm_plane_init(struct amdgpu_display_manager *dm,
3031 struct amdgpu_plane *aplane,
3032 unsigned long possible_crtcs)
3033{
3034 int res = -EPERM;
3035
3036 switch (aplane->base.type) {
3037 case DRM_PLANE_TYPE_PRIMARY:
3038 aplane->base.format_default = true;
3039
3040 res = drm_universal_plane_init(
3041 dm->adev->ddev,
3042 &aplane->base,
3043 possible_crtcs,
3044 &dm_plane_funcs,
3045 rgb_formats,
3046 ARRAY_SIZE(rgb_formats),
3047 NULL, aplane->base.type, NULL);
3048 break;
3049 case DRM_PLANE_TYPE_OVERLAY:
3050 res = drm_universal_plane_init(
3051 dm->adev->ddev,
3052 &aplane->base,
3053 possible_crtcs,
3054 &dm_plane_funcs,
3055 yuv_formats,
3056 ARRAY_SIZE(yuv_formats),
3057 NULL, aplane->base.type, NULL);
3058 break;
3059 case DRM_PLANE_TYPE_CURSOR:
3060 res = drm_universal_plane_init(
3061 dm->adev->ddev,
3062 &aplane->base,
3063 possible_crtcs,
3064 &dm_plane_funcs,
3065 cursor_formats,
3066 ARRAY_SIZE(cursor_formats),
3067 NULL, aplane->base.type, NULL);
3068 break;
3069 }
3070
3071 drm_plane_helper_add(&aplane->base, &dm_plane_helper_funcs);
3072
3073 return res;
3074}
3075
3076int amdgpu_dm_crtc_init(struct amdgpu_display_manager *dm,
3077 struct drm_plane *plane,
3078 uint32_t crtc_index)
3079{
3080 struct amdgpu_crtc *acrtc = NULL;
3081 struct amdgpu_plane *cursor_plane;
3082
3083 int res = -ENOMEM;
3084
3085 cursor_plane = kzalloc(sizeof(*cursor_plane), GFP_KERNEL);
3086 if (!cursor_plane)
3087 goto fail;
3088
3089 cursor_plane->base.type = DRM_PLANE_TYPE_CURSOR;
3090 res = amdgpu_dm_plane_init(dm, cursor_plane, 0);
3091
3092 acrtc = kzalloc(sizeof(struct amdgpu_crtc), GFP_KERNEL);
3093 if (!acrtc)
3094 goto fail;
3095
3096 res = drm_crtc_init_with_planes(
3097 dm->ddev,
3098 &acrtc->base,
3099 plane,
3100 &cursor_plane->base,
3101 &amdgpu_dm_crtc_funcs, NULL);
3102
3103 if (res)
3104 goto fail;
3105
3106 drm_crtc_helper_add(&acrtc->base, &amdgpu_dm_crtc_helper_funcs);
3107
3108 acrtc->max_cursor_width = dm->adev->dm.dc->caps.max_cursor_size;
3109 acrtc->max_cursor_height = dm->adev->dm.dc->caps.max_cursor_size;
3110
3111 acrtc->crtc_id = crtc_index;
3112 acrtc->base.enabled = false;
3113
3114 dm->adev->mode_info.crtcs[crtc_index] = acrtc;
3115 drm_mode_crtc_set_gamma_size(&acrtc->base, 256);
3116
3117 return 0;
3118
3119fail:
b830ebc9
HW		 3120 kfree(acrtc);
3121 kfree(cursor_plane);
e7b07cee
HW		 3122 acrtc->crtc_id = -1;
3123 return res;
3124}
3125
3126
3127static int to_drm_connector_type(enum signal_type st)
3128{
3129 switch (st) {
3130 case SIGNAL_TYPE_HDMI_TYPE_A:
3131 return DRM_MODE_CONNECTOR_HDMIA;
3132 case SIGNAL_TYPE_EDP:
3133 return DRM_MODE_CONNECTOR_eDP;
3134 case SIGNAL_TYPE_RGB:
3135 return DRM_MODE_CONNECTOR_VGA;
3136 case SIGNAL_TYPE_DISPLAY_PORT:
3137 case SIGNAL_TYPE_DISPLAY_PORT_MST:
3138 return DRM_MODE_CONNECTOR_DisplayPort;
3139 case SIGNAL_TYPE_DVI_DUAL_LINK:
3140 case SIGNAL_TYPE_DVI_SINGLE_LINK:
3141 return DRM_MODE_CONNECTOR_DVID;
3142 case SIGNAL_TYPE_VIRTUAL:
3143 return DRM_MODE_CONNECTOR_VIRTUAL;
3144
3145 default:
3146 return DRM_MODE_CONNECTOR_Unknown;
3147 }
3148}
3149
3150static void amdgpu_dm_get_native_mode(struct drm_connector *connector)
3151{
3152 const struct drm_connector_helper_funcs *helper =
3153 connector->helper_private;
3154 struct drm_encoder *encoder;
3155 struct amdgpu_encoder *amdgpu_encoder;
3156
3157 encoder = helper->best_encoder(connector);
3158
3159 if (encoder == NULL)
3160 return;
3161
3162 amdgpu_encoder = to_amdgpu_encoder(encoder);
3163
3164 amdgpu_encoder->native_mode.clock = 0;
3165
3166 if (!list_empty(&connector->probed_modes)) {
3167 struct drm_display_mode *preferred_mode = NULL;
b830ebc9 3168
e7b07cee 3169 list_for_each_entry(preferred_mode,
b830ebc9
HW		 3170 &connector->probed_modes,
3171 head) {
3172 if (preferred_mode->type & DRM_MODE_TYPE_PREFERRED)
3173 amdgpu_encoder->native_mode = *preferred_mode;
3174
e7b07cee
HW		 3175 break;
3176 }
3177
3178 }
3179}
3180
3181static struct drm_display_mode *amdgpu_dm_create_common_mode(
3182 struct drm_encoder *encoder, char *name,
3183 int hdisplay, int vdisplay)
3184{
3185 struct drm_device *dev = encoder->dev;
3186 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3187 struct drm_display_mode *mode = NULL;
3188 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
3189
3190 mode = drm_mode_duplicate(dev, native_mode);
3191
b830ebc9 3192 if (mode == NULL)
e7b07cee
HW		 3193 return NULL;
3194
3195 mode->hdisplay = hdisplay;
3196 mode->vdisplay = vdisplay;
3197 mode->type &= ~DRM_MODE_TYPE_PREFERRED;
3198 strncpy(mode->name, name, DRM_DISPLAY_MODE_LEN);
3199
3200 return mode;
3201
3202}
3203
3204static void amdgpu_dm_connector_add_common_modes(struct drm_encoder *encoder,
3205 struct drm_connector *connector)
3206{
3207 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3208 struct drm_display_mode *mode = NULL;
3209 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
3210 struct amdgpu_connector *amdgpu_connector =
3211 to_amdgpu_connector(connector);
3212 int i;
3213 int n;
3214 struct mode_size {
3215 char name[DRM_DISPLAY_MODE_LEN];
3216 int w;
3217 int h;
b830ebc9 3218 } common_modes[] = {
e7b07cee
HW		 3219 { "640x480", 640, 480},
3220 { "800x600", 800, 600},
3221 { "1024x768", 1024, 768},
3222 { "1280x720", 1280, 720},
3223 { "1280x800", 1280, 800},
3224 {"1280x1024", 1280, 1024},
3225 { "1440x900", 1440, 900},
3226 {"1680x1050", 1680, 1050},
3227 {"1600x1200", 1600, 1200},
3228 {"1920x1080", 1920, 1080},
3229 {"1920x1200", 1920, 1200}
3230 };
3231
b830ebc9 3232 n = ARRAY_SIZE(common_modes);
e7b07cee
HW		 3233
3234 for (i = 0; i < n; i++) {
3235 struct drm_display_mode *curmode = NULL;
3236 bool mode_existed = false;
3237
3238 if (common_modes[i].w > native_mode->hdisplay ||
b830ebc9
HW		 3239 common_modes[i].h > native_mode->vdisplay ||
3240 (common_modes[i].w == native_mode->hdisplay &&
3241 common_modes[i].h == native_mode->vdisplay))
3242 continue;
e7b07cee
HW		 3243
3244 list_for_each_entry(curmode, &connector->probed_modes, head) {
3245 if (common_modes[i].w == curmode->hdisplay &&
b830ebc9 3246 common_modes[i].h == curmode->vdisplay) {
e7b07cee
HW		 3247 mode_existed = true;
3248 break;
3249 }
3250 }
3251
3252 if (mode_existed)
3253 continue;
3254
3255 mode = amdgpu_dm_create_common_mode(encoder,
3256 common_modes[i].name, common_modes[i].w,
3257 common_modes[i].h);
3258 drm_mode_probed_add(connector, mode);
3259 amdgpu_connector->num_modes++;
3260 }
3261}
3262
3263static void amdgpu_dm_connector_ddc_get_modes(
3264 struct drm_connector *connector,
3265 struct edid *edid)
3266{
3267 struct amdgpu_connector *amdgpu_connector =
3268 to_amdgpu_connector(connector);
3269
3270 if (edid) {
3271 /* empty probed_modes */
3272 INIT_LIST_HEAD(&connector->probed_modes);
3273 amdgpu_connector->num_modes =
3274 drm_add_edid_modes(connector, edid);
3275
3276 drm_edid_to_eld(connector, edid);
3277
3278 amdgpu_dm_get_native_mode(connector);
3279 } else
3280 amdgpu_connector->num_modes = 0;
3281}
3282
3283int amdgpu_dm_connector_get_modes(struct drm_connector *connector)
3284{
3285 const struct drm_connector_helper_funcs *helper =
3286 connector->helper_private;
3287 struct amdgpu_connector *amdgpu_connector =
3288 to_amdgpu_connector(connector);
3289 struct drm_encoder *encoder;
3290 struct edid *edid = amdgpu_connector->edid;
3291
3292 encoder = helper->best_encoder(connector);
3293
3294 amdgpu_dm_connector_ddc_get_modes(connector, edid);
3295 amdgpu_dm_connector_add_common_modes(encoder, connector);
3296 return amdgpu_connector->num_modes;
3297}
3298
3299void amdgpu_dm_connector_init_helper(
3300 struct amdgpu_display_manager *dm,
3301 struct amdgpu_connector *aconnector,
3302 int connector_type,
3303 struct dc_link *link,
3304 int link_index)
3305{
3306 struct amdgpu_device *adev = dm->ddev->dev_private;
3307
3308 aconnector->connector_id = link_index;
3309 aconnector->dc_link = link;
3310 aconnector->base.interlace_allowed = false;
3311 aconnector->base.doublescan_allowed = false;
3312 aconnector->base.stereo_allowed = false;
3313 aconnector->base.dpms = DRM_MODE_DPMS_OFF;
3314 aconnector->hpd.hpd = AMDGPU_HPD_NONE; /* not used */
3315
3316 mutex_init(&aconnector->hpd_lock);
3317
b830ebc9
HW		 3318 /* configure support HPD hot plug connector_>polled default value is 0
3319 * which means HPD hot plug not supported
3320 */
e7b07cee
HW		 3321 switch (connector_type) {
3322 case DRM_MODE_CONNECTOR_HDMIA:
3323 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD;
3324 break;
3325 case DRM_MODE_CONNECTOR_DisplayPort:
3326 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD;
3327 break;
3328 case DRM_MODE_CONNECTOR_DVID:
3329 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD;
3330 break;
3331 default:
3332 break;
3333 }
3334
3335 drm_object_attach_property(&aconnector->base.base,
3336 dm->ddev->mode_config.scaling_mode_property,
3337 DRM_MODE_SCALE_NONE);
3338
3339 drm_object_attach_property(&aconnector->base.base,
3340 adev->mode_info.underscan_property,
3341 UNDERSCAN_OFF);
3342 drm_object_attach_property(&aconnector->base.base,
3343 adev->mode_info.underscan_hborder_property,
3344 0);
3345 drm_object_attach_property(&aconnector->base.base,
3346 adev->mode_info.underscan_vborder_property,
3347 0);
3348
3349}
3350
3351int amdgpu_dm_i2c_xfer(struct i2c_adapter *i2c_adap,
3352 struct i2c_msg *msgs, int num)
3353{
3354 struct amdgpu_i2c_adapter *i2c = i2c_get_adapdata(i2c_adap);
3355 struct ddc_service *ddc_service = i2c->ddc_service;
3356 struct i2c_command cmd;
3357 int i;
3358 int result = -EIO;
3359
b830ebc9 3360 cmd.payloads = kcalloc(num, sizeof(struct i2c_payload), GFP_KERNEL);
e7b07cee
HW		 3361
3362 if (!cmd.payloads)
3363 return result;
3364
3365 cmd.number_of_payloads = num;
3366 cmd.engine = I2C_COMMAND_ENGINE_DEFAULT;
3367 cmd.speed = 100;
3368
3369 for (i = 0; i < num; i++) {
3370 cmd.payloads[i].write = !(msgs[i].flags & I2C_M_RD);
3371 cmd.payloads[i].address = msgs[i].addr;
3372 cmd.payloads[i].length = msgs[i].len;
3373 cmd.payloads[i].data = msgs[i].buf;
3374 }
3375
3376 if (dal_i2caux_submit_i2c_command(
3377 ddc_service->ctx->i2caux,
3378 ddc_service->ddc_pin,
3379 &cmd))
3380 result = num;
3381
3382 kfree(cmd.payloads);
3383 return result;
3384}
3385
3386u32 amdgpu_dm_i2c_func(struct i2c_adapter *adap)
3387{
3388 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
3389}
3390
3391static const struct i2c_algorithm amdgpu_dm_i2c_algo = {
3392 .master_xfer = amdgpu_dm_i2c_xfer,
3393 .functionality = amdgpu_dm_i2c_func,
3394};
3395
3396static struct amdgpu_i2c_adapter *create_i2c(
3397 struct ddc_service *ddc_service,
3398 int link_index,
3399 int *res)
3400{
3401 struct amdgpu_device *adev = ddc_service->ctx->driver_context;
3402 struct amdgpu_i2c_adapter *i2c;
3403
b830ebc9 3404 i2c = kzalloc(sizeof(struct amdgpu_i2c_adapter), GFP_KERNEL);
e7b07cee
HW		 3405 i2c->base.owner = THIS_MODULE;
3406 i2c->base.class = I2C_CLASS_DDC;
3407 i2c->base.dev.parent = &adev->pdev->dev;
3408 i2c->base.algo = &amdgpu_dm_i2c_algo;
b830ebc9 3409 snprintf(i2c->base.name, sizeof(i2c->base.name), "AMDGPU DM i2c hw bus %d", link_index);
e7b07cee
HW		 3410 i2c_set_adapdata(&i2c->base, i2c);
3411 i2c->ddc_service = ddc_service;
3412
3413 return i2c;
3414}
3415
3416/* Note: this function assumes that dc_link_detect() was called for the
b830ebc9
HW		 3417 * dc_link which will be represented by this aconnector.
3418 */
e7b07cee
HW		 3419int amdgpu_dm_connector_init(
3420 struct amdgpu_display_manager *dm,
3421 struct amdgpu_connector *aconnector,
3422 uint32_t link_index,
3423 struct amdgpu_encoder *aencoder)
3424{
3425 int res = 0;
3426 int connector_type;
3427 struct dc *dc = dm->dc;
3428 struct dc_link *link = dc_get_link_at_index(dc, link_index);
3429 struct amdgpu_i2c_adapter *i2c;
3430 ((struct dc_link *)link)->priv = aconnector;
3431
3432 DRM_DEBUG_KMS("%s()\n", __func__);
3433
3434 i2c = create_i2c(link->ddc, link->link_index, &res);
3435 aconnector->i2c = i2c;
3436 res = i2c_add_adapter(&i2c->base);
3437
3438 if (res) {
3439 DRM_ERROR("Failed to register hw i2c %d\n", link->link_index);
3440 goto out_free;
3441 }
3442
3443 connector_type = to_drm_connector_type(link->connector_signal);
3444
3445 res = drm_connector_init(
3446 dm->ddev,
3447 &aconnector->base,
3448 &amdgpu_dm_connector_funcs,
3449 connector_type);
3450
3451 if (res) {
3452 DRM_ERROR("connector_init failed\n");
3453 aconnector->connector_id = -1;
3454 goto out_free;
3455 }
3456
3457 drm_connector_helper_add(
3458 &aconnector->base,
3459 &amdgpu_dm_connector_helper_funcs);
3460
3461 amdgpu_dm_connector_init_helper(
3462 dm,
3463 aconnector,
3464 connector_type,
3465 link,
3466 link_index);
3467
3468 drm_mode_connector_attach_encoder(
3469 &aconnector->base, &aencoder->base);
3470
3471 drm_connector_register(&aconnector->base);
3472
3473 if (connector_type == DRM_MODE_CONNECTOR_DisplayPort
3474 || connector_type == DRM_MODE_CONNECTOR_eDP)
3475 amdgpu_dm_initialize_dp_connector(dm, aconnector);
3476
3477#if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) ||\
3478 defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
3479
3480 /* NOTE: this currently will create backlight device even if a panel
3481 * is not connected to the eDP/LVDS connector.
3482 *
3483 * This is less than ideal but we don't have sink information at this
3484 * stage since detection happens after. We can't do detection earlier
3485 * since MST detection needs connectors to be created first.
3486 */
3487 if (link->connector_signal & (SIGNAL_TYPE_EDP | SIGNAL_TYPE_LVDS)) {
3488 /* Event if registration failed, we should continue with
3489 * DM initialization because not having a backlight control
b830ebc9
HW		 3490 * is better then a black screen.
3491 */
e7b07cee
HW		 3492 amdgpu_dm_register_backlight_device(dm);
3493
3494 if (dm->backlight_dev)
3495 dm->backlight_link = link;
3496 }
3497#endif
3498
3499out_free:
3500 if (res) {
3501 kfree(i2c);
3502 aconnector->i2c = NULL;
3503 }
3504 return res;
3505}
3506
3507int amdgpu_dm_get_encoder_crtc_mask(struct amdgpu_device *adev)
3508{
3509 switch (adev->mode_info.num_crtc) {
3510 case 1:
3511 return 0x1;
3512 case 2:
3513 return 0x3;
3514 case 3:
3515 return 0x7;
3516 case 4:
3517 return 0xf;
3518 case 5:
3519 return 0x1f;
3520 case 6:
3521 default:
3522 return 0x3f;
3523 }
3524}
3525
3526int amdgpu_dm_encoder_init(
3527 struct drm_device *dev,
3528 struct amdgpu_encoder *aencoder,
3529 uint32_t link_index)
3530{
3531 struct amdgpu_device *adev = dev->dev_private;
3532
3533 int res = drm_encoder_init(dev,
3534 &aencoder->base,
3535 &amdgpu_dm_encoder_funcs,
3536 DRM_MODE_ENCODER_TMDS,
3537 NULL);
3538
3539 aencoder->base.possible_crtcs = amdgpu_dm_get_encoder_crtc_mask(adev);
3540
3541 if (!res)
3542 aencoder->encoder_id = link_index;
3543 else
3544 aencoder->encoder_id = -1;
3545
3546 drm_encoder_helper_add(&aencoder->base, &amdgpu_dm_encoder_helper_funcs);
3547
3548 return res;
3549}
3550
3551static void manage_dm_interrupts(
3552 struct amdgpu_device *adev,
3553 struct amdgpu_crtc *acrtc,
3554 bool enable)
3555{
3556 /*
3557 * this is not correct translation but will work as soon as VBLANK
3558 * constant is the same as PFLIP
3559 */
3560 int irq_type =
3561 amdgpu_crtc_idx_to_irq_type(
3562 adev,
3563 acrtc->crtc_id);
3564
3565 if (enable) {
3566 drm_crtc_vblank_on(&acrtc->base);
3567 amdgpu_irq_get(
3568 adev,
3569 &adev->pageflip_irq,
3570 irq_type);
3571 } else {
3572
3573 amdgpu_irq_put(
3574 adev,
3575 &adev->pageflip_irq,
3576 irq_type);
3577 drm_crtc_vblank_off(&acrtc->base);
3578 }
3579}
3580
3581static bool is_scaling_state_different(
3582 const struct dm_connector_state *dm_state,
3583 const struct dm_connector_state *old_dm_state)
3584{
3585 if (dm_state->scaling != old_dm_state->scaling)
3586 return true;
3587 if (!dm_state->underscan_enable && old_dm_state->underscan_enable) {
3588 if (old_dm_state->underscan_hborder != 0 && old_dm_state->underscan_vborder != 0)
3589 return true;
3590 } else if (dm_state->underscan_enable && !old_dm_state->underscan_enable) {
3591 if (dm_state->underscan_hborder != 0 && dm_state->underscan_vborder != 0)
3592 return true;
b830ebc9
HW		 3593 } else if (dm_state->underscan_hborder != old_dm_state->underscan_hborder ||
3594 dm_state->underscan_vborder != old_dm_state->underscan_vborder)
3595 return true;
e7b07cee
HW		 3596 return false;
3597}
3598
3599static void remove_stream(
3600 struct amdgpu_device *adev,
3601 struct amdgpu_crtc *acrtc,
0971c40e 3602 struct dc_stream_state *stream)
e7b07cee
HW		 3603{
3604 /* this is the update mode case */
3605 if (adev->dm.freesync_module)
3606 mod_freesync_remove_stream(adev->dm.freesync_module, stream);
3607
3608 acrtc->otg_inst = -1;
3609 acrtc->enabled = false;
3610}
3611
2a8f6ccb
HW		 3612int get_cursor_position(struct drm_plane *plane, struct drm_crtc *crtc,
3613 struct dc_cursor_position *position)
3614{
3615 struct amdgpu_crtc *amdgpu_crtc = amdgpu_crtc = to_amdgpu_crtc(crtc);
3616 int x, y;
3617 int xorigin = 0, yorigin = 0;
3618
3619 if (!crtc || !plane->state->fb) {
3620 position->enable = false;
3621 position->x = 0;
3622 position->y = 0;
3623 return 0;
3624 }
3625
3626 if ((plane->state->crtc_w > amdgpu_crtc->max_cursor_width) ||
3627 (plane->state->crtc_h > amdgpu_crtc->max_cursor_height)) {
3628 DRM_ERROR("%s: bad cursor width or height %d x %d\n",
3629 __func__,
3630 plane->state->crtc_w,
3631 plane->state->crtc_h);
3632 return -EINVAL;
3633 }
3634
3635 x = plane->state->crtc_x;
3636 y = plane->state->crtc_y;
3637 /* avivo cursor are offset into the total surface */
3638 x += crtc->primary->state->src_x >> 16;
3639 y += crtc->primary->state->src_y >> 16;
3640 if (x < 0) {
3641 xorigin = min(-x, amdgpu_crtc->max_cursor_width - 1);
3642 x = 0;
3643 }
3644 if (y < 0) {
3645 yorigin = min(-y, amdgpu_crtc->max_cursor_height - 1);
3646 y = 0;
3647 }
3648 position->enable = true;
3649 position->x = x;
3650 position->y = y;
3651 position->x_hotspot = xorigin;
3652 position->y_hotspot = yorigin;
3653
3654 return 0;
3655}
3656
e7b07cee
HW		 3657static void handle_cursor_update(
3658 struct drm_plane *plane,
3659 struct drm_plane_state *old_plane_state)
3660{
2a8f6ccb
HW		 3661 struct amdgpu_framebuffer *afb = to_amdgpu_framebuffer(plane->state->fb);
3662 struct drm_crtc *crtc = afb ? plane->state->crtc : old_plane_state->crtc;
3663 struct dm_crtc_state *crtc_state = crtc ? to_dm_crtc_state(crtc->state) : NULL;
3664 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
3665 uint64_t address = afb ? afb->address : 0;
3666 struct dc_cursor_position position;
3667 struct dc_cursor_attributes attributes;
3668 int ret;
3669
e7b07cee
HW		 3670 if (!plane->state->fb && !old_plane_state->fb)
3671 return;
3672
2a8f6ccb
HW		 3673 DRM_DEBUG_KMS("%s: crtc_id=%d with size %d to %d\n",
3674 __func__,
3675 amdgpu_crtc->crtc_id,
3676 plane->state->crtc_w,
3677 plane->state->crtc_h);
3678
3679 ret = get_cursor_position(plane, crtc, &position);
3680 if (ret)
3681 return;
3682
3683 if (!position.enable) {
3684 /* turn off cursor */
3685 if (crtc_state && crtc_state->stream)
3686 dc_stream_set_cursor_position(crtc_state->stream,
3687 &position);
3688 return;
e7b07cee 3689 }
e7b07cee 3690
2a8f6ccb
HW		 3691 amdgpu_crtc->cursor_width = plane->state->crtc_w;
3692 amdgpu_crtc->cursor_height = plane->state->crtc_h;
3693
3694 attributes.address.high_part = upper_32_bits(address);
3695 attributes.address.low_part = lower_32_bits(address);
3696 attributes.width = plane->state->crtc_w;
3697 attributes.height = plane->state->crtc_h;
3698 attributes.color_format = CURSOR_MODE_COLOR_PRE_MULTIPLIED_ALPHA;
3699 attributes.rotation_angle = 0;
3700 attributes.attribute_flags.value = 0;
3701
3702 attributes.pitch = attributes.width;
3703
3704 if (!dc_stream_set_cursor_attributes(crtc_state->stream,
3705 &attributes))
3706 DRM_ERROR("DC failed to set cursor attributes\n");
3707
3708 if (crtc_state->stream)
3709 if (!dc_stream_set_cursor_position(crtc_state->stream,
3710 &position))
3711 DRM_ERROR("DC failed to set cursor position\n");
3712}
e7b07cee
HW		 3713
3714static void prepare_flip_isr(struct amdgpu_crtc *acrtc)
3715{
3716
3717 assert_spin_locked(&acrtc->base.dev->event_lock);
3718 WARN_ON(acrtc->event);
3719
3720 acrtc->event = acrtc->base.state->event;
3721
3722 /* Set the flip status */
3723 acrtc->pflip_status = AMDGPU_FLIP_SUBMITTED;
3724
3725 /* Mark this event as consumed */
3726 acrtc->base.state->event = NULL;
3727
3728 DRM_DEBUG_DRIVER("crtc:%d, pflip_stat:AMDGPU_FLIP_SUBMITTED\n",
3729 acrtc->crtc_id);
3730}
3731
3732/*
3733 * Executes flip
3734 *
3735 * Waits on all BO's fences and for proper vblank count
3736 */
3737static void amdgpu_dm_do_flip(
3738 struct drm_crtc *crtc,
3739 struct drm_framebuffer *fb,
3740 uint32_t target)
3741{
3742 unsigned long flags;
3743 uint32_t target_vblank;
3744 int r, vpos, hpos;
3745 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
3746 struct amdgpu_framebuffer *afb = to_amdgpu_framebuffer(fb);
3747 struct amdgpu_bo *abo = gem_to_amdgpu_bo(afb->obj);
3748 struct amdgpu_device *adev = crtc->dev->dev_private;
3749 bool async_flip = (acrtc->flip_flags & DRM_MODE_PAGE_FLIP_ASYNC) != 0;
3750 struct dc_flip_addrs addr = { {0} };
3be5262e 3751 /* TODO eliminate or rename surface_update */
e7b07cee
HW		 3752 struct dc_surface_update surface_updates[1] = { {0} };
3753 struct dm_crtc_state *acrtc_state = to_dm_crtc_state(crtc->state);
3754
3755
3756 /* Prepare wait for target vblank early - before the fence-waits */
3757 target_vblank = target - drm_crtc_vblank_count(crtc) +
3758 amdgpu_get_vblank_counter_kms(crtc->dev, acrtc->crtc_id);
3759
b830ebc9 3760 /* TODO This might fail and hence better not used, wait
e7b07cee
HW		 3761 * explicitly on fences instead
3762 * and in general should be called for
3763 * blocking commit to as per framework helpers
b830ebc9 3764 */
e7b07cee
HW		 3765 r = amdgpu_bo_reserve(abo, true);
3766 if (unlikely(r != 0)) {
3767 DRM_ERROR("failed to reserve buffer before flip\n");
3768 WARN_ON(1);
3769 }
3770
3771 /* Wait for all fences on this FB */
3772 WARN_ON(reservation_object_wait_timeout_rcu(abo->tbo.resv, true, false,
3773 MAX_SCHEDULE_TIMEOUT) < 0);
3774
3775 amdgpu_bo_unreserve(abo);
3776
3777 /* Wait until we're out of the vertical blank period before the one
3778 * targeted by the flip
3779 */
3780 while ((acrtc->enabled &&
3781 (amdgpu_get_crtc_scanoutpos(adev->ddev, acrtc->crtc_id, 0,
3782 &vpos, &hpos, NULL, NULL,
3783 &crtc->hwmode)
3784 & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK)) ==
3785 (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK) &&
3786 (int)(target_vblank -
3787 amdgpu_get_vblank_counter_kms(adev->ddev, acrtc->crtc_id)) > 0)) {
3788 usleep_range(1000, 1100);
3789 }
3790
3791 /* Flip */
3792 spin_lock_irqsave(&crtc->dev->event_lock, flags);
3793 /* update crtc fb */
3794 crtc->primary->fb = fb;
3795
3796 WARN_ON(acrtc->pflip_status != AMDGPU_FLIP_NONE);
3797 WARN_ON(!acrtc_state->stream);
3798
3799 addr.address.grph.addr.low_part = lower_32_bits(afb->address);
3800 addr.address.grph.addr.high_part = upper_32_bits(afb->address);
3801 addr.flip_immediate = async_flip;
3802
3803
3804 if (acrtc->base.state->event)
3805 prepare_flip_isr(acrtc);
3806
3be5262e 3807 surface_updates->surface = dc_stream_get_status(acrtc_state->stream)->plane_states[0];
e7b07cee
HW		 3808 surface_updates->flip_addr = &addr;
3809
3810
3be5262e 3811 dc_update_planes_and_stream(adev->dm.dc, surface_updates, 1, acrtc_state->stream, NULL);
e7b07cee
HW		 3812
3813 DRM_DEBUG_DRIVER("%s Flipping to hi: 0x%x, low: 0x%x \n",
3814 __func__,
3815 addr.address.grph.addr.high_part,
3816 addr.address.grph.addr.low_part);
3817
3818
3819 spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
3820}
3821
3be5262e 3822static void amdgpu_dm_commit_planes(struct drm_atomic_state *state,
e7b07cee
HW		 3823 struct drm_device *dev,
3824 struct amdgpu_display_manager *dm,
3825 struct drm_crtc *pcrtc,
3826 bool *wait_for_vblank)
3827{
3828 uint32_t i;
3829 struct drm_plane *plane;
3830 struct drm_plane_state *old_plane_state;
0971c40e 3831 struct dc_stream_state *dc_stream_attach;
3be5262e 3832 struct dc_plane_state *plane_states_constructed[MAX_SURFACES];
e7b07cee
HW		 3833 struct amdgpu_crtc *acrtc_attach = to_amdgpu_crtc(pcrtc);
3834 struct dm_crtc_state *acrtc_state = to_dm_crtc_state(pcrtc->state);
3835 int planes_count = 0;
3836 unsigned long flags;
3837
3838 /* update planes when needed */
3839 for_each_plane_in_state(state, plane, old_plane_state, i) {
3840 struct drm_plane_state *plane_state = plane->state;
3841 struct drm_crtc *crtc = plane_state->crtc;
3842 struct drm_framebuffer *fb = plane_state->fb;
3843 bool pflip_needed;
3844 struct dm_plane_state *dm_plane_state = to_dm_plane_state(plane_state);
3845
3846 if (plane->type == DRM_PLANE_TYPE_CURSOR) {
3847 handle_cursor_update(plane, old_plane_state);
3848 continue;
3849 }
3850
3851 if (!fb || !crtc || pcrtc != crtc || !crtc->state->active ||
3852 (!crtc->state->planes_changed &&
3853 !pcrtc->state->color_mgmt_changed))
3854 continue;
3855
3856 pflip_needed = !state->allow_modeset;
3857
3858 spin_lock_irqsave(&crtc->dev->event_lock, flags);
3859 if (acrtc_attach->pflip_status != AMDGPU_FLIP_NONE) {
3be5262e
HW		 3860 DRM_ERROR("%s: acrtc %d, already busy\n",
3861 __func__,
3862 acrtc_attach->crtc_id);
e7b07cee 3863 spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
b830ebc9 3864 /* In commit tail framework this cannot happen */
e7b07cee
HW		 3865 WARN_ON(1);
3866 }
3867 spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
3868
3869 if (!pflip_needed) {
3be5262e 3870 WARN_ON(!dm_plane_state->dc_state);
e7b07cee 3871
3be5262e 3872 plane_states_constructed[planes_count] = dm_plane_state->dc_state;
e7b07cee
HW		 3873
3874 dc_stream_attach = acrtc_state->stream;
3875 planes_count++;
3876
3877 } else if (crtc->state->planes_changed) {
3878 /* Assume even ONE crtc with immediate flip means
3879 * entire can't wait for VBLANK
3880 * TODO Check if it's correct
3881 */
3882 *wait_for_vblank =
3883 acrtc_attach->flip_flags & DRM_MODE_PAGE_FLIP_ASYNC ?
3884 false : true;
3885
3886 /* TODO: Needs rework for multiplane flip */
3887 if (plane->type == DRM_PLANE_TYPE_PRIMARY)
3888 drm_crtc_vblank_get(crtc);
3889
3890 amdgpu_dm_do_flip(
3891 crtc,
3892 fb,
3893 drm_crtc_vblank_count(crtc) + *wait_for_vblank);
3894
3895 /*TODO BUG remove ASAP in 4.12 to avoid race between worker and flip IOCTL */
3896
3897 /*clean up the flags for next usage*/
3898 acrtc_attach->flip_flags = 0;
3899 }
3900
3901 }
3902
3903 if (planes_count) {
3904 unsigned long flags;
3905
3906 if (pcrtc->state->event) {
3907
3908 drm_crtc_vblank_get(pcrtc);
3909
3910 spin_lock_irqsave(&pcrtc->dev->event_lock, flags);
3911 prepare_flip_isr(acrtc_attach);
3912 spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags);
3913 }
3914
3be5262e
HW		 3915 if (false == dc_commit_planes_to_stream(dm->dc,
3916 plane_states_constructed,
3917 planes_count,
3918 dc_stream_attach))
3919 dm_error("%s: Failed to attach plane!\n", __func__);
e7b07cee
HW		 3920 } else {
3921 /*TODO BUG Here should go disable planes on CRTC. */
3922 }
3923}
3924
3925
3926int amdgpu_dm_atomic_commit(
3927 struct drm_device *dev,
3928 struct drm_atomic_state *state,
3929 bool nonblock)
3930{
3931 struct drm_crtc *crtc;
3932 struct drm_crtc_state *new_state;
3933 struct amdgpu_device *adev = dev->dev_private;
3934 int i;
3935
3936 /*
3937 * We evade vblanks and pflips on crtc that
3938 * should be changed. We do it here to flush & disable
3939 * interrupts before drm_swap_state is called in drm_atomic_helper_commit
3940 * it will update crtc->dm_crtc_state->stream pointer which is used in
3941 * the ISRs.
3942 */
3943 for_each_crtc_in_state(state, crtc, new_state, i) {
3944 struct dm_crtc_state *old_acrtc_state = to_dm_crtc_state(crtc->state);
3945 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
3946
3947 if (drm_atomic_crtc_needs_modeset(new_state) && old_acrtc_state->stream)
3948 manage_dm_interrupts(adev, acrtc, false);
3949 }
3950
3951 return drm_atomic_helper_commit(dev, state, nonblock);
3952
3953 /*TODO Handle EINTR, reenable IRQ*/
3954}
3955
3956void amdgpu_dm_atomic_commit_tail(
3957 struct drm_atomic_state *state)
3958{
3959 struct drm_device *dev = state->dev;
3960 struct amdgpu_device *adev = dev->dev_private;
3961 struct amdgpu_display_manager *dm = &adev->dm;
3962 struct dm_atomic_state *dm_state;
3963 uint32_t i, j;
3964 uint32_t new_crtcs_count = 0;
3965 struct drm_crtc *crtc, *pcrtc;
3966 struct drm_crtc_state *old_crtc_state;
3967 struct amdgpu_crtc *new_crtcs[MAX_STREAMS];
0971c40e 3968 struct dc_stream_state *new_stream = NULL;
e7b07cee
HW		 3969 unsigned long flags;
3970 bool wait_for_vblank = true;
3971 struct drm_connector *connector;
3972 struct drm_connector_state *old_conn_state;
3973 struct dm_crtc_state *old_acrtc_state, *new_acrtc_state;
3974
3975 drm_atomic_helper_update_legacy_modeset_state(dev, state);
3976
3977 dm_state = to_dm_atomic_state(state);
3978
3979 /* update changed items */
3980 for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
3981 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
3982 struct drm_crtc_state *new_state = crtc->state;
b830ebc9 3983
e7b07cee
HW		 3984 new_acrtc_state = to_dm_crtc_state(new_state);
3985 old_acrtc_state = to_dm_crtc_state(old_crtc_state);
3986
3987 DRM_DEBUG_KMS(
3988 "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, "
3989 "planes_changed:%d, mode_changed:%d,active_changed:%d,"
3990 "connectors_changed:%d\n",
3991 acrtc->crtc_id,
3992 new_state->enable,
3993 new_state->active,
3994 new_state->planes_changed,
3995 new_state->mode_changed,
3996 new_state->active_changed,
3997 new_state->connectors_changed);
3998
3999 /* handles headless hotplug case, updating new_state and
4000 * aconnector as needed
4001 */
4002
9b690ef3 4003 if (modeset_required(new_state, new_acrtc_state->stream, old_acrtc_state->stream)) {
e7b07cee
HW		 4004
4005 DRM_INFO("Atomic commit: SET crtc id %d: [%p]\n", acrtc->crtc_id, acrtc);
4006
4007 if (!new_acrtc_state->stream) {
4008 /*
b830ebc9
HW		 4009 * this could happen because of issues with
4010 * userspace notifications delivery.
4011 * In this case userspace tries to set mode on
4012 * display which is disconnect in fact.
4013 * dc_sink in NULL in this case on aconnector.
4014 * We expect reset mode will come soon.
4015 *
4016 * This can also happen when unplug is done
4017 * during resume sequence ended
4018 *
4019 * In this case, we want to pretend we still
4020 * have a sink to keep the pipe running so that
4021 * hw state is consistent with the sw state
4022 */
e7b07cee
HW		 4023 DRM_DEBUG_KMS("%s: Failed to create new stream for crtc %d\n",
4024 __func__, acrtc->base.base.id);
4025 continue;
4026 }
4027
4028
4029 if (old_acrtc_state->stream)
4030 remove_stream(adev, acrtc, old_acrtc_state->stream);
4031
4032
4033 /*
4034 * this loop saves set mode crtcs
4035 * we needed to enable vblanks once all
4036 * resources acquired in dc after dc_commit_streams
4037 */
4038
4039 /*TODO move all this into dm_crtc_state, get rid of
4040 * new_crtcs array and use old and new atomic states
4041 * instead
4042 */
4043 new_crtcs[new_crtcs_count] = acrtc;
4044 new_crtcs_count++;
4045
4046 acrtc->enabled = true;
4047 acrtc->hw_mode = crtc->state->mode;
4048 crtc->hwmode = crtc->state->mode;
4049 } else if (modereset_required(new_state)) {
4050 DRM_INFO("Atomic commit: RESET. crtc id %d:[%p]\n", acrtc->crtc_id, acrtc);
4051
4052 /* i.e. reset mode */
4053 if (old_acrtc_state->stream)
4054 remove_stream(adev, acrtc, old_acrtc_state->stream);
4055 }
4056 } /* for_each_crtc_in_state() */
4057
4058 /*
4059 * Add streams after required streams from new and replaced streams
4060 * are removed from freesync module
4061 */
4062 if (adev->dm.freesync_module) {
4063 for (i = 0; i < new_crtcs_count; i++) {
4064 struct amdgpu_connector *aconnector = NULL;
b830ebc9 4065
e7b07cee
HW		 4066 new_acrtc_state = to_dm_crtc_state(new_crtcs[i]->base.state);
4067
4068 new_stream = new_acrtc_state->stream;
4069 aconnector =
4070 amdgpu_dm_find_first_crct_matching_connector(
4071 state,
4072 &new_crtcs[i]->base,
4073 false);
4074 if (!aconnector) {
b830ebc9
HW		 4075 DRM_INFO("Atomic commit: Failed to find connector for acrtc id:%d "
4076 "skipping freesync init\n",
4077 new_crtcs[i]->crtc_id);
e7b07cee
HW		 4078 continue;
4079 }
4080
4081 mod_freesync_add_stream(adev->dm.freesync_module,
4082 new_stream, &aconnector->caps);
4083 }
4084 }
4085
4086 if (dm_state->context)
4087 WARN_ON(!dc_commit_context(dm->dc, dm_state->context));
4088
4089
4090 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
4091 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
b830ebc9 4092
e7b07cee
HW		 4093 new_acrtc_state = to_dm_crtc_state(crtc->state);
4094
4095 if (new_acrtc_state->stream != NULL) {
4096 const struct dc_stream_status *status =
4097 dc_stream_get_status(new_acrtc_state->stream);
4098
4099 if (!status)
4100 DC_ERR("got no status for stream %p on acrtc%p\n", new_acrtc_state->stream, acrtc);
4101 else
4102 acrtc->otg_inst = status->primary_otg_inst;
4103 }
4104 }
4105
4106 /* Handle scaling and undersacn changes*/
4107 for_each_connector_in_state(state, connector, old_conn_state, i) {
4108 struct amdgpu_connector *aconnector = to_amdgpu_connector(connector);
4109 struct dm_connector_state *con_new_state =
4110 to_dm_connector_state(aconnector->base.state);
4111 struct dm_connector_state *con_old_state =
4112 to_dm_connector_state(old_conn_state);
4113 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(con_new_state->base.crtc);
4114 struct dc_stream_status *status = NULL;
4115
4116 /* Skip any modesets/resets */
4117 if (!acrtc || drm_atomic_crtc_needs_modeset(acrtc->base.state))
4118 continue;
4119
4120 /* Skip any thing not scale or underscan changes */
4121 if (!is_scaling_state_different(con_new_state, con_old_state))
4122 continue;
4123
4124 new_acrtc_state = to_dm_crtc_state(acrtc->base.state);
4125
4126 update_stream_scaling_settings(&con_new_state->base.crtc->mode,
0971c40e 4127 con_new_state, (struct dc_stream_state *)new_acrtc_state->stream);
e7b07cee
HW		 4128
4129 status = dc_stream_get_status(new_acrtc_state->stream);
4130 WARN_ON(!status);
3be5262e 4131 WARN_ON(!status->plane_count);
e7b07cee
HW		 4132
4133 if (!new_acrtc_state->stream)
4134 continue;
4135
4136 /*TODO How it works with MPO ?*/
3be5262e 4137 if (!dc_commit_planes_to_stream(
e7b07cee 4138 dm->dc,
3be5262e
HW		 4139 status->plane_states,
4140 status->plane_count,
e7b07cee
HW		 4141 new_acrtc_state->stream))
4142 dm_error("%s: Failed to update stream scaling!\n", __func__);
4143 }
4144
4145 for (i = 0; i < new_crtcs_count; i++) {
4146 /*
4147 * loop to enable interrupts on newly arrived crtc
4148 */
4149 struct amdgpu_crtc *acrtc = new_crtcs[i];
b830ebc9 4150
e7b07cee
HW		 4151 new_acrtc_state = to_dm_crtc_state(acrtc->base.state);
4152
4153 if (adev->dm.freesync_module)
4154 mod_freesync_notify_mode_change(
4155 adev->dm.freesync_module, &new_acrtc_state->stream, 1);
4156
4157 manage_dm_interrupts(adev, acrtc, true);
4158 }
4159
4160 /* update planes when needed per crtc*/
4161 for_each_crtc_in_state(state, pcrtc, old_crtc_state, j) {
4162 new_acrtc_state = to_dm_crtc_state(pcrtc->state);
4163
4164 if (new_acrtc_state->stream)
3be5262e 4165 amdgpu_dm_commit_planes(state, dev, dm, pcrtc, &wait_for_vblank);
e7b07cee
HW		 4166 }
4167
4168
4169 /*
4170 * send vblank event on all events not handled in flip and
4171 * mark consumed event for drm_atomic_helper_commit_hw_done
4172 */
4173 spin_lock_irqsave(&adev->ddev->event_lock, flags);
4174 for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
4175 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
4176
4177 if (acrtc->base.state->event)
4178 drm_send_event_locked(dev, &crtc->state->event->base);
4179
4180 acrtc->base.state->event = NULL;
4181 }
4182 spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
4183
4184 /* Signal HW programming completion */
4185 drm_atomic_helper_commit_hw_done(state);
4186
4187 if (wait_for_vblank)
4188 drm_atomic_helper_wait_for_vblanks(dev, state);
4189
4190 drm_atomic_helper_cleanup_planes(dev, state);
4191}
4192
4193
4194static int dm_force_atomic_commit(struct drm_connector *connector)
4195{
4196 int ret = 0;
4197 struct drm_device *ddev = connector->dev;
4198 struct drm_atomic_state *state = drm_atomic_state_alloc(ddev);
4199 struct amdgpu_crtc *disconnected_acrtc = to_amdgpu_crtc(connector->encoder->crtc);
4200 struct drm_plane *plane = disconnected_acrtc->base.primary;
4201 struct drm_connector_state *conn_state;
4202 struct drm_crtc_state *crtc_state;
4203 struct drm_plane_state *plane_state;
4204
4205 if (!state)
4206 return -ENOMEM;
4207
4208 state->acquire_ctx = ddev->mode_config.acquire_ctx;
4209
4210 /* Construct an atomic state to restore previous display setting */
4211
4212 /*
4213 * Attach connectors to drm_atomic_state
4214 */
4215 conn_state = drm_atomic_get_connector_state(state, connector);
4216
4217 ret = PTR_ERR_OR_ZERO(conn_state);
4218 if (ret)
4219 goto err;
4220
4221 /* Attach crtc to drm_atomic_state*/
4222 crtc_state = drm_atomic_get_crtc_state(state, &disconnected_acrtc->base);
4223
4224 ret = PTR_ERR_OR_ZERO(crtc_state);
4225 if (ret)
4226 goto err;
4227
4228 /* force a restore */
4229 crtc_state->mode_changed = true;
4230
4231 /* Attach plane to drm_atomic_state */
4232 plane_state = drm_atomic_get_plane_state(state, plane);
4233
4234 ret = PTR_ERR_OR_ZERO(plane_state);
4235 if (ret)
4236 goto err;
4237
4238
4239 /* Call commit internally with the state we just constructed */
4240 ret = drm_atomic_commit(state);
4241 if (!ret)
4242 return 0;
4243
4244err:
4245 DRM_ERROR("Restoring old state failed with %i\n", ret);
4246 drm_atomic_state_put(state);
4247
4248 return ret;
4249}
4250
4251/*
4252 * This functions handle all cases when set mode does not come upon hotplug.
4253 * This include when the same display is unplugged then plugged back into the
4254 * same port and when we are running without usermode desktop manager supprot
4255 */
4256void dm_restore_drm_connector_state(struct drm_device *dev, struct drm_connector *connector)
4257{
4258 struct amdgpu_connector *aconnector = to_amdgpu_connector(connector);
4259 struct amdgpu_crtc *disconnected_acrtc;
4260 struct dm_crtc_state *acrtc_state;
4261
4262 if (!aconnector->dc_sink || !connector->state || !connector->encoder)
4263 return;
4264
4265 disconnected_acrtc = to_amdgpu_crtc(connector->encoder->crtc);
4266 acrtc_state = to_dm_crtc_state(disconnected_acrtc->base.state);
4267
4268 if (!disconnected_acrtc || !acrtc_state->stream)
4269 return;
4270
4271 /*
4272 * If the previous sink is not released and different from the current,
4273 * we deduce we are in a state where we can not rely on usermode call
4274 * to turn on the display, so we do it here
4275 */
4276 if (acrtc_state->stream->sink != aconnector->dc_sink)
4277 dm_force_atomic_commit(&aconnector->base);
4278}
4279
3be5262e 4280static uint32_t add_val_sets_plane(
e7b07cee
HW		 4281 struct dc_validation_set *val_sets,
4282 uint32_t set_count,
0971c40e 4283 const struct dc_stream_state *stream,
3be5262e 4284 struct dc_plane_state *plane_state)
e7b07cee
HW		 4285{
4286 uint32_t i = 0, j = 0;
4287
4288 while (i < set_count) {
4289 if (val_sets[i].stream == stream) {
3be5262e 4290 while (val_sets[i].plane_states[j])
e7b07cee
HW		 4291 j++;
4292 break;
4293 }
4294 ++i;
4295 }
4296
3be5262e
HW		 4297 val_sets[i].plane_states[j] = plane_state;
4298 val_sets[i].plane_count++;
e7b07cee 4299
3be5262e 4300 return val_sets[i].plane_count;
e7b07cee
HW		 4301}
4302
4303static uint32_t update_in_val_sets_stream(
4304 struct dc_validation_set *val_sets,
4305 uint32_t set_count,
0971c40e
HW		 4306 struct dc_stream_state *old_stream,
4307 struct dc_stream_state *new_stream,
e7b07cee
HW		 4308 struct drm_crtc *crtc)
4309{
4310 uint32_t i = 0;
4311
4312 while (i < set_count) {
4313 if (val_sets[i].stream == old_stream)
4314 break;
4315 ++i;
4316 }
4317
4318 val_sets[i].stream = new_stream;
4319
4320 if (i == set_count)
4321 /* nothing found. add new one to the end */
4322 return set_count + 1;
4323
4324 return set_count;
4325}
4326
4327static uint32_t remove_from_val_sets(
4328 struct dc_validation_set *val_sets,
4329 uint32_t set_count,
0971c40e 4330 const struct dc_stream_state *stream)
e7b07cee
HW		 4331{
4332 int i;
4333
4334 for (i = 0; i < set_count; i++)
4335 if (val_sets[i].stream == stream)
4336 break;
4337
4338 if (i == set_count) {
4339 /* nothing found */
4340 return set_count;
4341 }
4342
4343 set_count--;
4344
b830ebc9 4345 for (; i < set_count; i++)
e7b07cee 4346 val_sets[i] = val_sets[i + 1];
e7b07cee
HW		 4347
4348 return set_count;
4349}
4350
4351/*`
4352 * Grabs all modesetting locks to serialize against any blocking commits,
4353 * Waits for completion of all non blocking commits.
4354 */
4355static int do_aquire_global_lock(
4356 struct drm_device *dev,
4357 struct drm_atomic_state *state)
4358{
4359 struct drm_crtc *crtc;
4360 struct drm_crtc_commit *commit;
4361 long ret;
4362
4363 /* Adding all modeset locks to aquire_ctx will
4364 * ensure that when the framework release it the
4365 * extra locks we are locking here will get released to
4366 */
4367 ret = drm_modeset_lock_all_ctx(dev, state->acquire_ctx);
4368 if (ret)
4369 return ret;
4370
4371 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
4372 spin_lock(&crtc->commit_lock);
4373 commit = list_first_entry_or_null(&crtc->commit_list,
4374 struct drm_crtc_commit, commit_entry);
4375 if (commit)
4376 drm_crtc_commit_get(commit);
4377 spin_unlock(&crtc->commit_lock);
4378
4379 if (!commit)
4380 continue;
4381
4382 /* Make sure all pending HW programming completed and
4383 * page flips done
4384 */
4385 ret = wait_for_completion_interruptible_timeout(&commit->hw_done, 10*HZ);
4386
4387 if (ret > 0)
4388 ret = wait_for_completion_interruptible_timeout(
4389 &commit->flip_done, 10*HZ);
4390
4391 if (ret == 0)
4392 DRM_ERROR("[CRTC:%d:%s] hw_done or flip_done "
b830ebc9 4393 "timed out\n", crtc->base.id, crtc->name);
e7b07cee
HW		 4394
4395 drm_crtc_commit_put(commit);
4396 }
4397
4398 return ret < 0 ? ret : 0;
4399}
4400
4401int amdgpu_dm_atomic_check(struct drm_device *dev,
4402 struct drm_atomic_state *state)
4403{
4404 struct dm_atomic_state *dm_state;
4405 struct drm_crtc *crtc;
4406 struct drm_crtc_state *crtc_state;
4407 struct drm_plane *plane;
4408 struct drm_plane_state *plane_state;
4409 int i, j;
4410 int ret;
4411 struct amdgpu_device *adev = dev->dev_private;
4412 struct dc *dc = adev->dm.dc;
4413 struct drm_connector *connector;
4414 struct drm_connector_state *conn_state;
4415 int set_count;
4416 struct dc_validation_set set[MAX_STREAMS] = { { 0 } };
4417 struct dm_crtc_state *old_acrtc_state, *new_acrtc_state;
4418
4419 /*
4420 * This bool will be set for true for any modeset/reset
3be5262e 4421 * or plane update which implies non fast surface update.
e7b07cee
HW		 4422 */
4423 bool lock_and_validation_needed = false;
4424
4425 ret = drm_atomic_helper_check_modeset(dev, state);
4426
4427 if (ret) {
4428 DRM_ERROR("Atomic state validation failed with error :%d !\n", ret);
4429 return ret;
4430 }
4431
4432 dm_state = to_dm_atomic_state(state);
4433
4434 /* copy existing configuration */
4435 set_count = 0;
4436 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
4437
4438 old_acrtc_state = to_dm_crtc_state(crtc->state);
4439
4440 if (old_acrtc_state->stream) {
4441 dc_stream_retain(old_acrtc_state->stream);
4442 set[set_count].stream = old_acrtc_state->stream;
4443 ++set_count;
4444 }
4445 }
4446
4447 /*TODO Move this code into dm_crtc_atomic_check once we get rid of dc_validation_set */
4448 /* update changed items */
4449 for_each_crtc_in_state(state, crtc, crtc_state, i) {
4450 struct amdgpu_crtc *acrtc = NULL;
4451 struct amdgpu_connector *aconnector = NULL;
0971c40e 4452 struct dc_stream_state *new_stream = NULL;
9b690ef3
BL		 4453 struct drm_connector_state *conn_state = NULL;
4454 struct dm_connector_state *dm_conn_state = NULL;
b830ebc9 4455
e7b07cee
HW		 4456 old_acrtc_state = to_dm_crtc_state(crtc->state);
4457 new_acrtc_state = to_dm_crtc_state(crtc_state);
4458 acrtc = to_amdgpu_crtc(crtc);
4459
4460 aconnector = amdgpu_dm_find_first_crct_matching_connector(state, crtc, true);
4461
4462 DRM_DEBUG_KMS(
4463 "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, "
4464 "planes_changed:%d, mode_changed:%d,active_changed:%d,"
4465 "connectors_changed:%d\n",
4466 acrtc->crtc_id,
4467 crtc_state->enable,
4468 crtc_state->active,
4469 crtc_state->planes_changed,
4470 crtc_state->mode_changed,
4471 crtc_state->active_changed,
4472 crtc_state->connectors_changed);
4473
9b690ef3 4474 if (modereset_required(crtc_state)) {
e7b07cee 4475
9b690ef3
BL		 4476 /* i.e. reset mode */
4477 if (new_acrtc_state->stream) {
4478 set_count = remove_from_val_sets(
4479 set,
4480 set_count,
4481 new_acrtc_state->stream);
4482
4483 dc_stream_release(new_acrtc_state->stream);
4484 new_acrtc_state->stream = NULL;
4485
4486 lock_and_validation_needed = true;
4487 }
4488
4489 } else {
e7b07cee
HW		 4490
4491 if (aconnector) {
9b690ef3
BL		 4492 conn_state = drm_atomic_get_connector_state(state,
4493 &aconnector->base);
4494
e7b07cee
HW		 4495 if (IS_ERR(conn_state)) {
4496 ret = PTR_ERR_OR_ZERO(conn_state);
4497 goto fail;
4498 }
4499
4500 dm_conn_state = to_dm_connector_state(conn_state);
9b690ef3
BL		 4501
4502 new_stream = create_stream_for_sink(aconnector,
4503 &crtc_state->mode,
4504 dm_conn_state);
4505
a7b06724
BL		 4506 /*
4507 * we can have no stream on ACTION_SET if a display
4508 * was disconnected during S3, in this case it not and
4509 * error, the OS will be updated after detection, and
4510 * do the right thing on next atomic commit
4511 */
4512
9b690ef3
BL		 4513 if (!new_stream) {
4514 DRM_DEBUG_KMS("%s: Failed to create new stream for crtc %d\n",
4515 __func__, acrtc->base.base.id);
4516 break;
4517 }
4518
4519
e7b07cee
HW		 4520 }
4521
9b690ef3
BL		 4522 if (modeset_required(crtc_state, new_stream,
4523 old_acrtc_state->stream)) {
4524
9b690ef3
BL		 4525 if (new_acrtc_state->stream)
4526 dc_stream_release(new_acrtc_state->stream);
e7b07cee 4527
9b690ef3 4528 new_acrtc_state->stream = new_stream;
e7b07cee 4529
9b690ef3 4530 set_count = update_in_val_sets_stream(
e7b07cee
HW		 4531 set,
4532 set_count,
9b690ef3
BL		 4533 old_acrtc_state->stream,
4534 new_acrtc_state->stream,
4535 crtc);
e7b07cee
HW		 4536
4537 lock_and_validation_needed = true;
9b690ef3
BL		 4538 } else {
4539 /*
4540 * The new stream is unused, so we release it
4541 */
4542 if (new_stream)
4543 dc_stream_release(new_stream);
4544
e7b07cee
HW		 4545 }
4546 }
4547
4548
4549 /*
4550 * Hack: Commit needs planes right now, specifically for gamma
4551 * TODO rework commit to check CRTC for gamma change
4552 */
4553 if (crtc_state->color_mgmt_changed) {
4554
4555 ret = drm_atomic_add_affected_planes(state, crtc);
4556 if (ret)
4557 goto fail;
4558 }
4559 }
4560
4561 /* Check scaling and undersacn changes*/
4562 /*TODO Removed scaling changes validation due to inability to commit
4563 * new stream into context w\o causing full reset. Need to
4564 * decide how to handle.
4565 */
4566 for_each_connector_in_state(state, connector, conn_state, i) {
4567 struct amdgpu_connector *aconnector = to_amdgpu_connector(connector);
4568 struct dm_connector_state *con_old_state =
4569 to_dm_connector_state(aconnector->base.state);
4570 struct dm_connector_state *con_new_state =
4571 to_dm_connector_state(conn_state);
4572 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(con_new_state->base.crtc);
4573
4574 /* Skip any modesets/resets */
4575 if (!acrtc || drm_atomic_crtc_needs_modeset(acrtc->base.state))
4576 continue;
4577
b830ebc9 4578 /* Skip any thing not scale or underscan changes */
e7b07cee
HW		 4579 if (!is_scaling_state_different(con_new_state, con_old_state))
4580 continue;
4581
4582 lock_and_validation_needed = true;
4583 }
4584
4585 for_each_crtc_in_state(state, crtc, crtc_state, i) {
4586 new_acrtc_state = to_dm_crtc_state(crtc_state);
4587
4588 for_each_plane_in_state(state, plane, plane_state, j) {
4589 struct drm_crtc *plane_crtc = plane_state->crtc;
4590 struct drm_framebuffer *fb = plane_state->fb;
4591 bool pflip_needed;
4592 struct dm_plane_state *dm_plane_state = to_dm_plane_state(plane_state);
4593
4594 /*TODO Implement atomic check for cursor plane */
4595 if (plane->type == DRM_PLANE_TYPE_CURSOR)
4596 continue;
4597
4598 if (!fb || !plane_crtc || crtc != plane_crtc || !crtc_state->active)
4599 continue;
4600
4601 WARN_ON(!new_acrtc_state->stream);
4602
4603 pflip_needed = !state->allow_modeset;
4604 if (!pflip_needed) {
3be5262e 4605 struct dc_plane_state *dc_plane_state;
e7b07cee 4606
3be5262e 4607 dc_plane_state = dc_create_plane_state(dc);
e7b07cee 4608
4d128c2f
JZ		 4609 if (dm_plane_state->dc_state)
4610 dc_plane_state_release(dm_plane_state->dc_state);
4611
4612 dm_plane_state->dc_state = dc_plane_state;
4613
e7b07cee
HW		 4614 ret = fill_plane_attributes(
4615 plane_crtc->dev->dev_private,
3be5262e 4616 dc_plane_state,
e7b07cee
HW		 4617 plane_state,
4618 crtc_state,
4619 false);
4620 if (ret)
4621 goto fail;
4622
3be5262e 4623 add_val_sets_plane(set,
e7b07cee
HW		 4624 set_count,
4625 new_acrtc_state->stream,
3be5262e 4626 dc_plane_state);
e7b07cee
HW		 4627
4628 lock_and_validation_needed = true;
4629 }
4630 }
4631 }
4632
4633 /* Run this here since we want to validate the streams we created */
4634 ret = drm_atomic_helper_check_planes(dev, state);
4635 if (ret)
4636 goto fail;
4637
4638 /*
4639 * For full updates case when
4640 * removing/adding/updating streams on once CRTC while flipping
4641 * on another CRTC,
4642 * acquiring global lock will guarantee that any such full
4643 * update commit
4644 * will wait for completion of any outstanding flip using DRMs
4645 * synchronization events.
4646 */
4647
4648 if (lock_and_validation_needed) {
4649
4650 ret = do_aquire_global_lock(dev, state);
4651 if (ret)
4652 goto fail;
4653 WARN_ON(dm_state->context);
4654 dm_state->context = dc_get_validate_context(dc, set, set_count);
4655 if (!dm_state->context) {
4656 ret = -EINVAL;
4657 goto fail;
4658 }
4659 }
4660
4661 /* Must be success */
4662 WARN_ON(ret);
4663 return ret;
4664
4665fail:
4666 if (ret == -EDEADLK)
4667 DRM_DEBUG_KMS("Atomic check stopped due to to deadlock.\n");
4668 else if (ret == -EINTR || ret == -EAGAIN || ret == -ERESTARTSYS)
4669 DRM_DEBUG_KMS("Atomic check stopped due to to signal.\n");
4670 else
4671 DRM_ERROR("Atomic check failed with err: %d .\n", ret);
4672
4673 return ret;
4674}
4675
4676static bool is_dp_capable_without_timing_msa(
4677 struct dc *dc,
4678 struct amdgpu_connector *amdgpu_connector)
4679{
4680 uint8_t dpcd_data;
4681 bool capable = false;
4682
4683 if (amdgpu_connector->dc_link &&
4684 dm_helpers_dp_read_dpcd(
4685 NULL,
4686 amdgpu_connector->dc_link,
4687 DP_DOWN_STREAM_PORT_COUNT,
4688 &dpcd_data,
4689 sizeof(dpcd_data))) {
4690 capable = (dpcd_data & DP_MSA_TIMING_PAR_IGNORED) ? true:false;
4691 }
4692
4693 return capable;
4694}
4695void amdgpu_dm_add_sink_to_freesync_module(
4696 struct drm_connector *connector,
4697 struct edid *edid)
4698{
4699 int i;
4700 uint64_t val_capable;
4701 bool edid_check_required;
4702 struct detailed_timing *timing;
4703 struct detailed_non_pixel *data;
4704 struct detailed_data_monitor_range *range;
4705 struct amdgpu_connector *amdgpu_connector =
4706 to_amdgpu_connector(connector);
4707
4708 struct drm_device *dev = connector->dev;
4709 struct amdgpu_device *adev = dev->dev_private;
b830ebc9 4710
e7b07cee
HW		 4711 edid_check_required = false;
4712 if (!amdgpu_connector->dc_sink) {
4713 DRM_ERROR("dc_sink NULL, could not add free_sync module.\n");
4714 return;
4715 }
4716 if (!adev->dm.freesync_module)
4717 return;
4718 /*
4719 * if edid non zero restrict freesync only for dp and edp
4720 */
4721 if (edid) {
4722 if (amdgpu_connector->dc_sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT
4723 || amdgpu_connector->dc_sink->sink_signal == SIGNAL_TYPE_EDP) {
4724 edid_check_required = is_dp_capable_without_timing_msa(
4725 adev->dm.dc,
4726 amdgpu_connector);
4727 }
4728 }
4729 val_capable = 0;
4730 if (edid_check_required == true && (edid->version > 1 ||
4731 (edid->version == 1 && edid->revision > 1))) {
4732 for (i = 0; i < 4; i++) {
4733
4734 timing = &edid->detailed_timings[i];
4735 data = &timing->data.other_data;
4736 range = &data->data.range;
4737 /*
4738 * Check if monitor has continuous frequency mode
4739 */
4740 if (data->type != EDID_DETAIL_MONITOR_RANGE)
4741 continue;
4742 /*
4743 * Check for flag range limits only. If flag == 1 then
4744 * no additional timing information provided.
4745 * Default GTF, GTF Secondary curve and CVT are not
4746 * supported
4747 */
4748 if (range->flags != 1)
4749 continue;
4750
4751 amdgpu_connector->min_vfreq = range->min_vfreq;
4752 amdgpu_connector->max_vfreq = range->max_vfreq;
4753 amdgpu_connector->pixel_clock_mhz =
4754 range->pixel_clock_mhz * 10;
4755 break;
4756 }
4757
4758 if (amdgpu_connector->max_vfreq -
4759 amdgpu_connector->min_vfreq > 10) {
4760 amdgpu_connector->caps.supported = true;
4761 amdgpu_connector->caps.min_refresh_in_micro_hz =
4762 amdgpu_connector->min_vfreq * 1000000;
4763 amdgpu_connector->caps.max_refresh_in_micro_hz =
4764 amdgpu_connector->max_vfreq * 1000000;
4765 val_capable = 1;
4766 }
4767 }
4768
4769 /*
4770 * TODO figure out how to notify user-mode or DRM of freesync caps
4771 * once we figure out how to deal with freesync in an upstreamable
4772 * fashion
4773 */
4774
4775}
4776
4777void amdgpu_dm_remove_sink_from_freesync_module(
4778 struct drm_connector *connector)
4779{
4780 /*
4781 * TODO fill in once we figure out how to deal with freesync in
4782 * an upstreamable fashion
4783 */
4784}
ubuntu-bionic-kernel mirror