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drm/amd/display: Fix gfx9 parameters reading for DC.
[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / amd / display / amdgpu_dm / amdgpu_dm_types.c
CommitLineData
4562236b
HW		 1/*
2 * Copyright 2012-13 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26#include <linux/types.h>
27#include <linux/version.h>
28
29#include <drm/drmP.h>
30#include <drm/drm_atomic_helper.h>
31#include <drm/drm_fb_helper.h>
32#include <drm/drm_atomic.h>
33#include <drm/drm_edid.h>
34
35#include "amdgpu.h"
36#include "amdgpu_pm.h"
37#include "dm_services_types.h"
38
39// We need to #undef FRAME_SIZE and DEPRECATED because they conflict
40// with ptrace-abi.h's #define's of them.
41#undef FRAME_SIZE
42#undef DEPRECATED
43
44#include "dc.h"
45
46#include "amdgpu_dm_types.h"
47#include "amdgpu_dm_mst_types.h"
48
49#include "modules/inc/mod_freesync.h"
50
51struct dm_connector_state {
52 struct drm_connector_state base;
53
54 enum amdgpu_rmx_type scaling;
55 uint8_t underscan_vborder;
56 uint8_t underscan_hborder;
57 bool underscan_enable;
58};
59
60#define to_dm_connector_state(x)\
61 container_of((x), struct dm_connector_state, base)
62
63
64void amdgpu_dm_encoder_destroy(struct drm_encoder *encoder)
65{
66 drm_encoder_cleanup(encoder);
67 kfree(encoder);
68}
69
70static const struct drm_encoder_funcs amdgpu_dm_encoder_funcs = {
71 .destroy = amdgpu_dm_encoder_destroy,
72};
73
74static void dm_set_cursor(
75 struct amdgpu_crtc *amdgpu_crtc,
76 uint64_t gpu_addr,
77 uint32_t width,
78 uint32_t height)
79{
80 struct dc_cursor_attributes attributes;
cf388c0d
AN		 81 struct dc_cursor_position position;
82 struct drm_crtc *crtc = &amdgpu_crtc->base;
83 int x, y;
84 int xorigin = 0, yorigin = 0;
85
4562236b
HW		 86 amdgpu_crtc->cursor_width = width;
87 amdgpu_crtc->cursor_height = height;
88
89 attributes.address.high_part = upper_32_bits(gpu_addr);
90 attributes.address.low_part = lower_32_bits(gpu_addr);
91 attributes.width = width;
92 attributes.height = height;
93 attributes.x_hot = 0;
94 attributes.y_hot = 0;
95 attributes.color_format = CURSOR_MODE_COLOR_PRE_MULTIPLIED_ALPHA;
96 attributes.rotation_angle = 0;
97 attributes.attribute_flags.value = 0;
98
cf388c0d
AN		 99 x = amdgpu_crtc->cursor_x;
100 y = amdgpu_crtc->cursor_y;
101
102 /* avivo cursor are offset into the total surface */
103 x += crtc->primary->state->src_x >> 16;
104 y += crtc->primary->state->src_y >> 16;
105
106 if (x < 0) {
107 xorigin = min(-x, amdgpu_crtc->max_cursor_width - 1);
108 x = 0;
109 }
110 if (y < 0) {
111 yorigin = min(-y, amdgpu_crtc->max_cursor_height - 1);
112 y = 0;
113 }
114
115 position.enable = true;
116 position.x = x;
117 position.y = y;
118
119 position.hot_spot_enable = true;
120 position.x_hotspot = xorigin;
121 position.y_hotspot = yorigin;
122
ab2541b6
AC		 123 if (!dc_stream_set_cursor_attributes(
124 amdgpu_crtc->stream,
4562236b
HW		 125 &attributes)) {
126 DRM_ERROR("DC failed to set cursor attributes\n");
127 }
cf388c0d 128
ab2541b6
AC		 129 if (!dc_stream_set_cursor_position(
130 amdgpu_crtc->stream,
cf388c0d
AN		 131 &position)) {
132 DRM_ERROR("DC failed to set cursor position\n");
133 }
4562236b
HW		 134}
135
136static int dm_crtc_unpin_cursor_bo_old(
137 struct amdgpu_crtc *amdgpu_crtc)
138{
139 struct amdgpu_bo *robj;
140 int ret = 0;
141
142 if (NULL != amdgpu_crtc && NULL != amdgpu_crtc->cursor_bo) {
143 robj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo);
144
145 ret = amdgpu_bo_reserve(robj, false);
146
147 if (likely(ret == 0)) {
148 ret = amdgpu_bo_unpin(robj);
149
150 if (unlikely(ret != 0)) {
151 DRM_ERROR(
152 "%s: unpin failed (ret=%d), bo %p\n",
153 __func__,
154 ret,
155 amdgpu_crtc->cursor_bo);
156 }
157
158 amdgpu_bo_unreserve(robj);
159 } else {
160 DRM_ERROR(
161 "%s: reserve failed (ret=%d), bo %p\n",
162 __func__,
163 ret,
164 amdgpu_crtc->cursor_bo);
165 }
166
167 drm_gem_object_unreference_unlocked(amdgpu_crtc->cursor_bo);
168 amdgpu_crtc->cursor_bo = NULL;
169 }
170
171 return ret;
172}
173
174static int dm_crtc_pin_cursor_bo_new(
175 struct drm_crtc *crtc,
176 struct drm_file *file_priv,
177 uint32_t handle,
178 struct amdgpu_bo **ret_obj)
179{
180 struct amdgpu_crtc *amdgpu_crtc;
181 struct amdgpu_bo *robj;
182 struct drm_gem_object *obj;
183 int ret = -EINVAL;
184
185 if (NULL != crtc) {
186 struct drm_device *dev = crtc->dev;
187 struct amdgpu_device *adev = dev->dev_private;
188 uint64_t gpu_addr;
189
190 amdgpu_crtc = to_amdgpu_crtc(crtc);
191
192 obj = drm_gem_object_lookup(file_priv, handle);
193
194 if (!obj) {
195 DRM_ERROR(
196 "Cannot find cursor object %x for crtc %d\n",
197 handle,
198 amdgpu_crtc->crtc_id);
199 goto release;
200 }
201 robj = gem_to_amdgpu_bo(obj);
202
203 ret = amdgpu_bo_reserve(robj, false);
204
205 if (unlikely(ret != 0)) {
206 drm_gem_object_unreference_unlocked(obj);
207 DRM_ERROR("dm_crtc_pin_cursor_bo_new ret %x, handle %x\n",
208 ret, handle);
209 goto release;
210 }
211
212 ret = amdgpu_bo_pin_restricted(robj, AMDGPU_GEM_DOMAIN_VRAM, 0,
213 adev->mc.visible_vram_size,
214 &gpu_addr);
215
216 if (ret == 0) {
217 amdgpu_crtc->cursor_addr = gpu_addr;
218 *ret_obj = robj;
219 }
220 amdgpu_bo_unreserve(robj);
221 if (ret)
222 drm_gem_object_unreference_unlocked(obj);
223
224 }
225release:
226
227 return ret;
228}
229
230static int dm_crtc_cursor_set(
231 struct drm_crtc *crtc,
232 struct drm_file *file_priv,
233 uint32_t handle,
234 uint32_t width,
235 uint32_t height)
236{
237 struct amdgpu_bo *new_cursor_bo;
238 struct dc_cursor_position position;
239
240 int ret;
241
242 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
243
244 ret = EINVAL;
245 new_cursor_bo = NULL;
246
247 DRM_DEBUG_KMS(
248 "%s: crtc_id=%d with handle %d and size %d to %d, bo_object %p\n",
249 __func__,
250 amdgpu_crtc->crtc_id,
251 handle,
252 width,
253 height,
254 amdgpu_crtc->cursor_bo);
255
256 if (!handle) {
257 /* turn off cursor */
258 position.enable = false;
259 position.x = 0;
260 position.y = 0;
261 position.hot_spot_enable = false;
262
ab2541b6 263 if (amdgpu_crtc->stream) {
4562236b 264 /*set cursor visible false*/
ab2541b6
AC		 265 dc_stream_set_cursor_position(
266 amdgpu_crtc->stream,
4562236b
HW		 267 &position);
268 }
269 /*unpin old cursor buffer and update cache*/
270 ret = dm_crtc_unpin_cursor_bo_old(amdgpu_crtc);
271 goto release;
272
273 }
274
275 if ((width > amdgpu_crtc->max_cursor_width) ||
276 (height > amdgpu_crtc->max_cursor_height)) {
277 DRM_ERROR(
278 "%s: bad cursor width or height %d x %d\n",
279 __func__,
280 width,
281 height);
282 goto release;
283 }
284 /*try to pin new cursor bo*/
285 ret = dm_crtc_pin_cursor_bo_new(crtc, file_priv, handle, &new_cursor_bo);
286 /*if map not successful then return an error*/
287 if (ret)
288 goto release;
289
290 /*program new cursor bo to hardware*/
291 dm_set_cursor(amdgpu_crtc, amdgpu_crtc->cursor_addr, width, height);
292
293 /*un map old, not used anymore cursor bo ,
294 * return memory and mapping back */
295 dm_crtc_unpin_cursor_bo_old(amdgpu_crtc);
296
297 /*assign new cursor bo to our internal cache*/
298 amdgpu_crtc->cursor_bo = &new_cursor_bo->gem_base;
299
300release:
301 return ret;
302
303}
304
305static int dm_crtc_cursor_move(struct drm_crtc *crtc,
306 int x, int y)
307{
308 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
309 int xorigin = 0, yorigin = 0;
310 struct dc_cursor_position position;
311
cf388c0d
AN		 312 amdgpu_crtc->cursor_x = x;
313 amdgpu_crtc->cursor_y = y;
314
4562236b
HW		 315 /* avivo cursor are offset into the total surface */
316 x += crtc->primary->state->src_x >> 16;
317 y += crtc->primary->state->src_y >> 16;
318
319 /*
320 * TODO: for cursor debugging unguard the following
321 */
322#if 0
323 DRM_DEBUG_KMS(
324 "%s: x %d y %d c->x %d c->y %d\n",
325 __func__,
326 x,
327 y,
328 crtc->x,
329 crtc->y);
330#endif
331
332 if (x < 0) {
333 xorigin = min(-x, amdgpu_crtc->max_cursor_width - 1);
334 x = 0;
335 }
336 if (y < 0) {
337 yorigin = min(-y, amdgpu_crtc->max_cursor_height - 1);
338 y = 0;
339 }
340
341 position.enable = true;
342 position.x = x;
343 position.y = y;
344
345 position.hot_spot_enable = true;
346 position.x_hotspot = xorigin;
347 position.y_hotspot = yorigin;
348
ab2541b6
AC		 349 if (amdgpu_crtc->stream) {
350 if (!dc_stream_set_cursor_position(
351 amdgpu_crtc->stream,
4562236b
HW		 352 &position)) {
353 DRM_ERROR("DC failed to set cursor position\n");
354 return -EINVAL;
355 }
356 }
357
358 return 0;
359}
360
361static void dm_crtc_cursor_reset(struct drm_crtc *crtc)
362{
363 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
364
365 DRM_DEBUG_KMS(
366 "%s: with cursor_bo %p\n",
367 __func__,
368 amdgpu_crtc->cursor_bo);
369
ab2541b6 370 if (amdgpu_crtc->cursor_bo && amdgpu_crtc->stream) {
4562236b
HW		 371 dm_set_cursor(
372 amdgpu_crtc,
373 amdgpu_crtc->cursor_addr,
374 amdgpu_crtc->cursor_width,
375 amdgpu_crtc->cursor_height);
376 }
377}
378static bool fill_rects_from_plane_state(
379 const struct drm_plane_state *state,
380 struct dc_surface *surface)
381{
382 surface->src_rect.x = state->src_x >> 16;
383 surface->src_rect.y = state->src_y >> 16;
384 /*we ignore for now mantissa and do not to deal with floating pixels :(*/
385 surface->src_rect.width = state->src_w >> 16;
386
387 if (surface->src_rect.width == 0)
388 return false;
389
390 surface->src_rect.height = state->src_h >> 16;
391 if (surface->src_rect.height == 0)
392 return false;
393
394 surface->dst_rect.x = state->crtc_x;
395 surface->dst_rect.y = state->crtc_y;
396
397 if (state->crtc_w == 0)
398 return false;
399
400 surface->dst_rect.width = state->crtc_w;
401
402 if (state->crtc_h == 0)
403 return false;
404
405 surface->dst_rect.height = state->crtc_h;
406
407 surface->clip_rect = surface->dst_rect;
408
409 switch (state->rotation & DRM_MODE_ROTATE_MASK) {
410 case DRM_MODE_ROTATE_0:
411 surface->rotation = ROTATION_ANGLE_0;
412 break;
413 case DRM_MODE_ROTATE_90:
414 surface->rotation = ROTATION_ANGLE_90;
415 break;
416 case DRM_MODE_ROTATE_180:
417 surface->rotation = ROTATION_ANGLE_180;
418 break;
419 case DRM_MODE_ROTATE_270:
420 surface->rotation = ROTATION_ANGLE_270;
421 break;
422 default:
423 surface->rotation = ROTATION_ANGLE_0;
424 break;
425 }
426
427 return true;
428}
429static bool get_fb_info(
430 const struct amdgpu_framebuffer *amdgpu_fb,
431 uint64_t *tiling_flags,
432 uint64_t *fb_location)
433{
434 struct amdgpu_bo *rbo = gem_to_amdgpu_bo(amdgpu_fb->obj);
435 int r = amdgpu_bo_reserve(rbo, false);
436 if (unlikely(r != 0)){
437 DRM_ERROR("Unable to reserve buffer\n");
438 return false;
439 }
440
441 if (fb_location)
442 *fb_location = amdgpu_bo_gpu_offset(rbo);
443
444 if (tiling_flags)
445 amdgpu_bo_get_tiling_flags(rbo, tiling_flags);
446
447 amdgpu_bo_unreserve(rbo);
448
449 return true;
450}
451static void fill_plane_attributes_from_fb(
6a1f8cab 452 struct amdgpu_device *adev,
4562236b
HW		 453 struct dc_surface *surface,
454 const struct amdgpu_framebuffer *amdgpu_fb, bool addReq)
455{
456 uint64_t tiling_flags;
457 uint64_t fb_location = 0;
458 const struct drm_framebuffer *fb = &amdgpu_fb->base;
459 struct drm_format_name_buf format_name;
460
461 get_fb_info(
462 amdgpu_fb,
463 &tiling_flags,
464 addReq == true ? &fb_location:NULL);
465
466 surface->address.type = PLN_ADDR_TYPE_GRAPHICS;
467 surface->address.grph.addr.low_part = lower_32_bits(fb_location);
468 surface->address.grph.addr.high_part = upper_32_bits(fb_location);
469
470 switch (fb->format->format) {
471 case DRM_FORMAT_C8:
472 surface->format = SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS;
473 break;
474 case DRM_FORMAT_RGB565:
475 surface->format = SURFACE_PIXEL_FORMAT_GRPH_RGB565;
476 break;
477 case DRM_FORMAT_XRGB8888:
478 case DRM_FORMAT_ARGB8888:
479 surface->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB8888;
480 break;
481 case DRM_FORMAT_XRGB2101010:
482 case DRM_FORMAT_ARGB2101010:
483 surface->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010;
484 break;
485 case DRM_FORMAT_XBGR2101010:
486 case DRM_FORMAT_ABGR2101010:
487 surface->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010;
488 break;
489 default:
490 DRM_ERROR("Unsupported screen format %s\n",
491 drm_get_format_name(fb->format->format, &format_name));
492 return;
493 }
494
495 memset(&surface->tiling_info, 0, sizeof(surface->tiling_info));
496
2c8ad2d5 497 /* Fill GFX params */
4562236b
HW		 498 if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == DC_ARRAY_2D_TILED_THIN1)
499 {
500 unsigned bankw, bankh, mtaspect, tile_split, num_banks;
501
502 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH);
503 bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT);
504 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT);
505 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT);
506 num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS);
507
508 /* XXX fix me for VI */
509 surface->tiling_info.gfx8.num_banks = num_banks;
510 surface->tiling_info.gfx8.array_mode =
511 DC_ARRAY_2D_TILED_THIN1;
512 surface->tiling_info.gfx8.tile_split = tile_split;
513 surface->tiling_info.gfx8.bank_width = bankw;
514 surface->tiling_info.gfx8.bank_height = bankh;
515 surface->tiling_info.gfx8.tile_aspect = mtaspect;
516 surface->tiling_info.gfx8.tile_mode =
517 DC_ADDR_SURF_MICRO_TILING_DISPLAY;
518 } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE)
519 == DC_ARRAY_1D_TILED_THIN1) {
520 surface->tiling_info.gfx8.array_mode = DC_ARRAY_1D_TILED_THIN1;
521 }
522
523 surface->tiling_info.gfx8.pipe_config =
524 AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG);
525
2c8ad2d5
AD		 526 if (adev->asic_type == CHIP_VEGA10) {
527 /* Fill GFX9 params */
528 surface->tiling_info.gfx9.num_pipes =
529 adev->gfx.config.gb_addr_config_fields.num_pipes;
530 surface->tiling_info.gfx9.num_banks =
531 adev->gfx.config.gb_addr_config_fields.num_banks;
532 surface->tiling_info.gfx9.pipe_interleave =
533 adev->gfx.config.gb_addr_config_fields.pipe_interleave_size;
534 surface->tiling_info.gfx9.num_shader_engines =
535 adev->gfx.config.gb_addr_config_fields.num_se;
536 surface->tiling_info.gfx9.max_compressed_frags =
537 adev->gfx.config.gb_addr_config_fields.max_compress_frags;
d092bf65
AG		 538 surface->tiling_info.gfx9.num_rb_per_se =
539 adev->gfx.config.gb_addr_config_fields.num_rb_per_se;
2c8ad2d5
AD		 540 surface->tiling_info.gfx9.swizzle =
541 AMDGPU_TILING_GET(tiling_flags, SWIZZLE_MODE);
542 surface->tiling_info.gfx9.shaderEnable = 1;
543 }
2c8ad2d5
AD		 544
545
4562236b
HW		 546 surface->plane_size.grph.surface_size.x = 0;
547 surface->plane_size.grph.surface_size.y = 0;
548 surface->plane_size.grph.surface_size.width = fb->width;
549 surface->plane_size.grph.surface_size.height = fb->height;
550 surface->plane_size.grph.surface_pitch =
551 fb->pitches[0] / fb->format->cpp[0];
552
553 surface->visible = true;
554 surface->scaling_quality.h_taps_c = 0;
555 surface->scaling_quality.v_taps_c = 0;
556
557 /* TODO: unhardcode */
558 surface->color_space = COLOR_SPACE_SRGB;
559 /* is this needed? is surface zeroed at allocation? */
560 surface->scaling_quality.h_taps = 0;
561 surface->scaling_quality.v_taps = 0;
562 surface->stereo_format = PLANE_STEREO_FORMAT_NONE;
563
564}
565
566#define NUM_OF_RAW_GAMMA_RAMP_RGB_256 256
567
568static void fill_gamma_from_crtc(
569 const struct drm_crtc *crtc,
570 struct dc_surface *dc_surface)
571{
572 int i;
573 struct dc_gamma *gamma;
574 struct drm_crtc_state *state = crtc->state;
575 struct drm_color_lut *lut = (struct drm_color_lut *) state->gamma_lut->data;
576
577 gamma = dc_create_gamma();
578
579 if (gamma == NULL)
580 return;
581
582 for (i = 0; i < NUM_OF_RAW_GAMMA_RAMP_RGB_256; i++) {
d7194cf6
AC		 583 gamma->red[i] = lut[i].red;
584 gamma->green[i] = lut[i].green;
585 gamma->blue[i] = lut[i].blue;
4562236b
HW		 586 }
587
4562236b
HW		 588 dc_surface->gamma_correction = gamma;
589}
590
591static void fill_plane_attributes(
6a1f8cab 592 struct amdgpu_device *adev,
4562236b
HW		 593 struct dc_surface *surface,
594 struct drm_plane_state *state, bool addrReq)
595{
596 const struct amdgpu_framebuffer *amdgpu_fb =
597 to_amdgpu_framebuffer(state->fb);
598 const struct drm_crtc *crtc = state->crtc;
18f39f2d 599 struct dc_transfer_func *input_tf;
4562236b
HW		 600
601 fill_rects_from_plane_state(state, surface);
602 fill_plane_attributes_from_fb(
6a1f8cab 603 crtc->dev->dev_private,
4562236b
HW		 604 surface,
605 amdgpu_fb,
606 addrReq);
607
18f39f2d
RL		 608 input_tf = dc_create_transfer_func();
609
610 if (input_tf == NULL)
611 return;
612
613 input_tf->type = TF_TYPE_PREDEFINED;
614 input_tf->tf = TRANSFER_FUNCTION_SRGB;
615
616 surface->in_transfer_func = input_tf;
617
4562236b
HW		 618 /* In case of gamma set, update gamma value */
619 if (state->crtc->state->gamma_lut) {
620 fill_gamma_from_crtc(crtc, surface);
621 }
622}
623
624/*****************************************************************************/
625
626struct amdgpu_connector *aconnector_from_drm_crtc_id(
627 const struct drm_crtc *crtc)
628{
629 struct drm_device *dev = crtc->dev;
630 struct drm_connector *connector;
631 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
632 struct amdgpu_connector *aconnector;
633
634 list_for_each_entry(connector,
635 &dev->mode_config.connector_list, head) {
636
637 aconnector = to_amdgpu_connector(connector);
638
639 if (aconnector->base.state->crtc != &acrtc->base)
640 continue;
641
642 /* Found the connector */
643 return aconnector;
644 }
645
646 /* If we get here, not found. */
647 return NULL;
648}
649
650static void update_stream_scaling_settings(
651 const struct drm_display_mode *mode,
652 const struct dm_connector_state *dm_state,
653 const struct dc_stream *stream)
654{
655 struct amdgpu_device *adev = dm_state->base.crtc->dev->dev_private;
656 enum amdgpu_rmx_type rmx_type;
657
ab2541b6 658 struct rect src = { 0 }; /* viewport in composition space*/
4562236b
HW		 659 struct rect dst = { 0 }; /* stream addressable area */
660
f7f3cfee
HW		 661 /* no mode. nothing to be done */
662 if (!mode)
663 return;
664
4562236b
HW		 665 /* Full screen scaling by default */
666 src.width = mode->hdisplay;
667 src.height = mode->vdisplay;
668 dst.width = stream->timing.h_addressable;
669 dst.height = stream->timing.v_addressable;
670
671 rmx_type = dm_state->scaling;
672 if (rmx_type == RMX_ASPECT || rmx_type == RMX_OFF) {
673 if (src.width * dst.height <
674 src.height * dst.width) {
675 /* height needs less upscaling/more downscaling */
676 dst.width = src.width *
677 dst.height / src.height;
678 } else {
679 /* width needs less upscaling/more downscaling */
680 dst.height = src.height *
681 dst.width / src.width;
682 }
683 } else if (rmx_type == RMX_CENTER) {
684 dst = src;
685 }
686
687 dst.x = (stream->timing.h_addressable - dst.width) / 2;
688 dst.y = (stream->timing.v_addressable - dst.height) / 2;
689
690 if (dm_state->underscan_enable) {
691 dst.x += dm_state->underscan_hborder / 2;
692 dst.y += dm_state->underscan_vborder / 2;
693 dst.width -= dm_state->underscan_hborder;
694 dst.height -= dm_state->underscan_vborder;
695 }
696
697 adev->dm.dc->stream_funcs.stream_update_scaling(adev->dm.dc, stream, &src, &dst);
698
699 DRM_DEBUG_KMS("Destination Rectangle x:%d y:%d width:%d height:%d\n",
700 dst.x, dst.y, dst.width, dst.height);
701
702}
703
704static void dm_dc_surface_commit(
705 struct dc *dc,
706 struct drm_crtc *crtc)
707{
708 struct dc_surface *dc_surface;
709 const struct dc_surface *dc_surfaces[1];
54f5499a 710 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
ab2541b6 711 const struct dc_stream *dc_stream = acrtc->stream;
54f5499a
AG		 712 unsigned long flags;
713
714 spin_lock_irqsave(&crtc->dev->event_lock, flags);
715 if (acrtc->pflip_status != AMDGPU_FLIP_NONE) {
716 DRM_ERROR("dm_dc_surface_commit: acrtc %d, already busy\n", acrtc->crtc_id);
717 spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
718 /* In comit tail framework this cannot happen */
719 BUG_ON(0);
720 }
721 spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
4562236b 722
ab2541b6 723 if (!dc_stream) {
4562236b 724 dm_error(
ab2541b6 725 "%s: Failed to obtain stream on crtc (%d)!\n",
4562236b
HW		 726 __func__,
727 acrtc->crtc_id);
728 goto fail;
729 }
730
731 dc_surface = dc_create_surface(dc);
732
733 if (!dc_surface) {
734 dm_error(
735 "%s: Failed to create a surface!\n",
736 __func__);
737 goto fail;
738 }
739
740 /* Surface programming */
6a1f8cab
AG		 741 fill_plane_attributes(
742 crtc->dev->dev_private,
743 dc_surface,
744 crtc->primary->state,
745 true);
4562236b
HW		 746
747 dc_surfaces[0] = dc_surface;
748
ab2541b6 749 if (false == dc_commit_surfaces_to_stream(
4562236b
HW		 750 dc,
751 dc_surfaces,
752 1,
ab2541b6 753 dc_stream)) {
4562236b
HW		 754 dm_error(
755 "%s: Failed to attach surface!\n",
756 __func__);
757 }
758
759 dc_surface_release(dc_surface);
760fail:
761 return;
762}
763
764static enum dc_color_depth convert_color_depth_from_display_info(
765 const struct drm_connector *connector)
766{
767 uint32_t bpc = connector->display_info.bpc;
768
769 /* Limited color depth to 8bit
770 * TODO: Still need to handle deep color*/
771 if (bpc > 8)
772 bpc = 8;
773
774 switch (bpc) {
775 case 0:
776 /* Temporary Work around, DRM don't parse color depth for
777 * EDID revision before 1.4
778 * TODO: Fix edid parsing
779 */
780 return COLOR_DEPTH_888;
781 case 6:
782 return COLOR_DEPTH_666;
783 case 8:
784 return COLOR_DEPTH_888;
785 case 10:
786 return COLOR_DEPTH_101010;
787 case 12:
788 return COLOR_DEPTH_121212;
789 case 14:
790 return COLOR_DEPTH_141414;
791 case 16:
792 return COLOR_DEPTH_161616;
793 default:
794 return COLOR_DEPTH_UNDEFINED;
795 }
796}
797
798static enum dc_aspect_ratio get_aspect_ratio(
799 const struct drm_display_mode *mode_in)
800{
801 int32_t width = mode_in->crtc_hdisplay * 9;
802 int32_t height = mode_in->crtc_vdisplay * 16;
803 if ((width - height) < 10 && (width - height) > -10)
804 return ASPECT_RATIO_16_9;
805 else
806 return ASPECT_RATIO_4_3;
807}
808
809static enum dc_color_space get_output_color_space(
810 const struct dc_crtc_timing *dc_crtc_timing)
811{
812 enum dc_color_space color_space = COLOR_SPACE_SRGB;
813
814 switch (dc_crtc_timing->pixel_encoding) {
815 case PIXEL_ENCODING_YCBCR422:
816 case PIXEL_ENCODING_YCBCR444:
817 case PIXEL_ENCODING_YCBCR420:
818 {
819 /*
820 * 27030khz is the separation point between HDTV and SDTV
821 * according to HDMI spec, we use YCbCr709 and YCbCr601
822 * respectively
823 */
824 if (dc_crtc_timing->pix_clk_khz > 27030) {
825 if (dc_crtc_timing->flags.Y_ONLY)
826 color_space =
827 COLOR_SPACE_YCBCR709_LIMITED;
828 else
829 color_space = COLOR_SPACE_YCBCR709;
830 } else {
831 if (dc_crtc_timing->flags.Y_ONLY)
832 color_space =
833 COLOR_SPACE_YCBCR601_LIMITED;
834 else
835 color_space = COLOR_SPACE_YCBCR601;
836 }
837
838 }
839 break;
840 case PIXEL_ENCODING_RGB:
841 color_space = COLOR_SPACE_SRGB;
842 break;
843
844 default:
845 WARN_ON(1);
846 break;
847 }
848
849 return color_space;
850}
851
852/*****************************************************************************/
853
854static void fill_stream_properties_from_drm_display_mode(
855 struct dc_stream *stream,
856 const struct drm_display_mode *mode_in,
857 const struct drm_connector *connector)
858{
859 struct dc_crtc_timing *timing_out = &stream->timing;
860 memset(timing_out, 0, sizeof(struct dc_crtc_timing));
861
862 timing_out->h_border_left = 0;
863 timing_out->h_border_right = 0;
864 timing_out->v_border_top = 0;
865 timing_out->v_border_bottom = 0;
866 /* TODO: un-hardcode */
867
868 if ((connector->display_info.color_formats & DRM_COLOR_FORMAT_YCRCB444)
869 && stream->sink->sink_signal == SIGNAL_TYPE_HDMI_TYPE_A)
870 timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR444;
871 else
872 timing_out->pixel_encoding = PIXEL_ENCODING_RGB;
873
874 timing_out->timing_3d_format = TIMING_3D_FORMAT_NONE;
875 timing_out->display_color_depth = convert_color_depth_from_display_info(
876 connector);
877 timing_out->scan_type = SCANNING_TYPE_NODATA;
878 timing_out->hdmi_vic = 0;
879 timing_out->vic = drm_match_cea_mode(mode_in);
880
881 timing_out->h_addressable = mode_in->crtc_hdisplay;
882 timing_out->h_total = mode_in->crtc_htotal;
883 timing_out->h_sync_width =
884 mode_in->crtc_hsync_end - mode_in->crtc_hsync_start;
885 timing_out->h_front_porch =
886 mode_in->crtc_hsync_start - mode_in->crtc_hdisplay;
887 timing_out->v_total = mode_in->crtc_vtotal;
888 timing_out->v_addressable = mode_in->crtc_vdisplay;
889 timing_out->v_front_porch =
890 mode_in->crtc_vsync_start - mode_in->crtc_vdisplay;
891 timing_out->v_sync_width =
892 mode_in->crtc_vsync_end - mode_in->crtc_vsync_start;
893 timing_out->pix_clk_khz = mode_in->crtc_clock;
894 timing_out->aspect_ratio = get_aspect_ratio(mode_in);
895 if (mode_in->flags & DRM_MODE_FLAG_PHSYNC)
896 timing_out->flags.HSYNC_POSITIVE_POLARITY = 1;
897 if (mode_in->flags & DRM_MODE_FLAG_PVSYNC)
898 timing_out->flags.VSYNC_POSITIVE_POLARITY = 1;
899
900 stream->output_color_space = get_output_color_space(timing_out);
901
d7194cf6
AC		 902 {
903 struct dc_transfer_func *tf = dc_create_transfer_func();
904 tf->type = TF_TYPE_PREDEFINED;
905 tf->tf = TRANSFER_FUNCTION_SRGB;
906 stream->out_transfer_func = tf;
907 }
4562236b
HW		 908}
909
910static void fill_audio_info(
911 struct audio_info *audio_info,
912 const struct drm_connector *drm_connector,
913 const struct dc_sink *dc_sink)
914{
915 int i = 0;
916 int cea_revision = 0;
917 const struct dc_edid_caps *edid_caps = &dc_sink->edid_caps;
918
919 audio_info->manufacture_id = edid_caps->manufacturer_id;
920 audio_info->product_id = edid_caps->product_id;
921
922 cea_revision = drm_connector->display_info.cea_rev;
923
924 while (i < AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS &&
925 edid_caps->display_name[i]) {
926 audio_info->display_name[i] = edid_caps->display_name[i];
927 i++;
928 }
929
930 if(cea_revision >= 3) {
931 audio_info->mode_count = edid_caps->audio_mode_count;
932
933 for (i = 0; i < audio_info->mode_count; ++i) {
934 audio_info->modes[i].format_code =
935 (enum audio_format_code)
936 (edid_caps->audio_modes[i].format_code);
937 audio_info->modes[i].channel_count =
938 edid_caps->audio_modes[i].channel_count;
939 audio_info->modes[i].sample_rates.all =
940 edid_caps->audio_modes[i].sample_rate;
941 audio_info->modes[i].sample_size =
942 edid_caps->audio_modes[i].sample_size;
943 }
944 }
945
946 audio_info->flags.all = edid_caps->speaker_flags;
947
948 /* TODO: We only check for the progressive mode, check for interlace mode too */
949 if(drm_connector->latency_present[0]) {
950 audio_info->video_latency = drm_connector->video_latency[0];
951 audio_info->audio_latency = drm_connector->audio_latency[0];
952 }
953
954 /* TODO: For DP, video and audio latency should be calculated from DPCD caps */
955
956}
957
958static void copy_crtc_timing_for_drm_display_mode(
959 const struct drm_display_mode *src_mode,
960 struct drm_display_mode *dst_mode)
961{
962 dst_mode->crtc_hdisplay = src_mode->crtc_hdisplay;
963 dst_mode->crtc_vdisplay = src_mode->crtc_vdisplay;
964 dst_mode->crtc_clock = src_mode->crtc_clock;
965 dst_mode->crtc_hblank_start = src_mode->crtc_hblank_start;
966 dst_mode->crtc_hblank_end = src_mode->crtc_hblank_end;
967 dst_mode->crtc_hsync_start= src_mode->crtc_hsync_start;
968 dst_mode->crtc_hsync_end = src_mode->crtc_hsync_end;
969 dst_mode->crtc_htotal = src_mode->crtc_htotal;
970 dst_mode->crtc_hskew = src_mode->crtc_hskew;
5866e7cf
JL		 971 dst_mode->crtc_vblank_start = src_mode->crtc_vblank_start;
972 dst_mode->crtc_vblank_end = src_mode->crtc_vblank_end;
973 dst_mode->crtc_vsync_start = src_mode->crtc_vsync_start;
974 dst_mode->crtc_vsync_end = src_mode->crtc_vsync_end;
975 dst_mode->crtc_vtotal = src_mode->crtc_vtotal;
4562236b
HW		 976}
977
978static void decide_crtc_timing_for_drm_display_mode(
979 struct drm_display_mode *drm_mode,
980 const struct drm_display_mode *native_mode,
981 bool scale_enabled)
982{
983 if (scale_enabled) {
984 copy_crtc_timing_for_drm_display_mode(native_mode, drm_mode);
985 } else if (native_mode->clock == drm_mode->clock &&
986 native_mode->htotal == drm_mode->htotal &&
987 native_mode->vtotal == drm_mode->vtotal) {
988 copy_crtc_timing_for_drm_display_mode(native_mode, drm_mode);
989 } else {
990 /* no scaling nor amdgpu inserted, no need to patch */
991 }
992}
993
ab2541b6 994static struct dc_stream *create_stream_for_sink(
0d70570f 995 struct amdgpu_connector *aconnector,
4562236b
HW		 996 const struct drm_display_mode *drm_mode,
997 const struct dm_connector_state *dm_state)
998{
999 struct drm_display_mode *preferred_mode = NULL;
1000 const struct drm_connector *drm_connector;
ab2541b6 1001 struct dc_stream *stream = NULL;
4562236b
HW		 1002 struct drm_display_mode mode = *drm_mode;
1003 bool native_mode_found = false;
1004
1005 if (NULL == aconnector) {
1006 DRM_ERROR("aconnector is NULL!\n");
1007 goto drm_connector_null;
1008 }
1009
1010 if (NULL == dm_state) {
1011 DRM_ERROR("dm_state is NULL!\n");
1012 goto dm_state_null;
1013 }
1014
1015 drm_connector = &aconnector->base;
1016 stream = dc_create_stream_for_sink(aconnector->dc_sink);
1017
1018 if (NULL == stream) {
1019 DRM_ERROR("Failed to create stream for sink!\n");
1020 goto stream_create_fail;
1021 }
1022
1023 list_for_each_entry(preferred_mode, &aconnector->base.modes, head) {
1024 /* Search for preferred mode */
1025 if (preferred_mode->type & DRM_MODE_TYPE_PREFERRED) {
1026 native_mode_found = true;
1027 break;
1028 }
1029 }
1030 if (!native_mode_found)
1031 preferred_mode = list_first_entry_or_null(
1032 &aconnector->base.modes,
1033 struct drm_display_mode,
1034 head);
1035
1036 if (NULL == preferred_mode) {
1037 /* This may not be an error, the use case is when we we have no
1038 * usermode calls to reset and set mode upon hotplug. In this
1039 * case, we call set mode ourselves to restore the previous mode
1040 * and the modelist may not be filled in in time.
1041 */
1042 DRM_INFO("No preferred mode found\n");
1043 } else {
1044 decide_crtc_timing_for_drm_display_mode(
1045 &mode, preferred_mode,
1046 dm_state->scaling != RMX_OFF);
1047 }
1048
1049 fill_stream_properties_from_drm_display_mode(stream,
1050 &mode, &aconnector->base);
1051 update_stream_scaling_settings(&mode, dm_state, stream);
1052
1053 fill_audio_info(
1054 &stream->audio_info,
1055 drm_connector,
1056 aconnector->dc_sink);
1057
ab2541b6 1058stream_create_fail:
4562236b
HW		 1059dm_state_null:
1060drm_connector_null:
ab2541b6 1061 return stream;
4562236b
HW		 1062}
1063
1064void amdgpu_dm_crtc_destroy(struct drm_crtc *crtc)
1065{
1066 drm_crtc_cleanup(crtc);
1067 kfree(crtc);
1068}
1069
1070/* Implemented only the options currently availible for the driver */
1071static const struct drm_crtc_funcs amdgpu_dm_crtc_funcs = {
1072 .reset = drm_atomic_helper_crtc_reset,
1073 .cursor_set = dm_crtc_cursor_set,
1074 .cursor_move = dm_crtc_cursor_move,
1075 .destroy = amdgpu_dm_crtc_destroy,
1076 .gamma_set = drm_atomic_helper_legacy_gamma_set,
1077 .set_config = drm_atomic_helper_set_config,
1078 .page_flip = drm_atomic_helper_page_flip,
1079 .atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state,
1080 .atomic_destroy_state = drm_atomic_helper_crtc_destroy_state,
1081};
1082
1083static enum drm_connector_status
1084amdgpu_dm_connector_detect(struct drm_connector *connector, bool force)
1085{
1086 bool connected;
1087 struct amdgpu_connector *aconnector = to_amdgpu_connector(connector);
1088
1089 /* Notes:
1090 * 1. This interface is NOT called in context of HPD irq.
1091 * 2. This interface *is called* in context of user-mode ioctl. Which
1092 * makes it a bad place for *any* MST-related activit. */
1093
1094 if (aconnector->base.force == DRM_FORCE_UNSPECIFIED)
1095 connected = (aconnector->dc_sink != NULL);
1096 else
1097 connected = (aconnector->base.force == DRM_FORCE_ON);
1098
1099 return (connected ? connector_status_connected :
1100 connector_status_disconnected);
1101}
1102
1103int amdgpu_dm_connector_atomic_set_property(
1104 struct drm_connector *connector,
1105 struct drm_connector_state *connector_state,
1106 struct drm_property *property,
1107 uint64_t val)
1108{
1109 struct drm_device *dev = connector->dev;
1110 struct amdgpu_device *adev = dev->dev_private;
1111 struct dm_connector_state *dm_old_state =
1112 to_dm_connector_state(connector->state);
1113 struct dm_connector_state *dm_new_state =
1114 to_dm_connector_state(connector_state);
1115
1116 struct drm_crtc_state *new_crtc_state;
1117 struct drm_crtc *crtc;
1118 int i;
1119 int ret = -EINVAL;
1120
1121 if (property == dev->mode_config.scaling_mode_property) {
1122 enum amdgpu_rmx_type rmx_type;
1123
1124 switch (val) {
1125 case DRM_MODE_SCALE_CENTER:
1126 rmx_type = RMX_CENTER;
1127 break;
1128 case DRM_MODE_SCALE_ASPECT:
1129 rmx_type = RMX_ASPECT;
1130 break;
1131 case DRM_MODE_SCALE_FULLSCREEN:
1132 rmx_type = RMX_FULL;
1133 break;
1134 case DRM_MODE_SCALE_NONE:
1135 default:
1136 rmx_type = RMX_OFF;
1137 break;
1138 }
1139
1140 if (dm_old_state->scaling == rmx_type)
1141 return 0;
1142
1143 dm_new_state->scaling = rmx_type;
1144 ret = 0;
1145 } else if (property == adev->mode_info.underscan_hborder_property) {
1146 dm_new_state->underscan_hborder = val;
1147 ret = 0;
1148 } else if (property == adev->mode_info.underscan_vborder_property) {
1149 dm_new_state->underscan_vborder = val;
1150 ret = 0;
1151 } else if (property == adev->mode_info.underscan_property) {
1152 dm_new_state->underscan_enable = val;
1153 ret = 0;
1154 }
1155
1156 for_each_crtc_in_state(
1157 connector_state->state,
1158 crtc,
1159 new_crtc_state,
1160 i) {
1161
1162 if (crtc == connector_state->crtc) {
1163 struct drm_plane_state *plane_state;
1164
1165 /*
1166 * Bit of magic done here. We need to ensure
1167 * that planes get update after mode is set.
1168 * So, we need to add primary plane to state,
1169 * and this way atomic_update would be called
1170 * for it
1171 */
1172 plane_state =
1173 drm_atomic_get_plane_state(
1174 connector_state->state,
1175 crtc->primary);
1176
1177 if (!plane_state)
1178 return -EINVAL;
1179 }
1180 }
1181
1182 return ret;
1183}
1184
1185void amdgpu_dm_connector_destroy(struct drm_connector *connector)
1186{
1187 struct amdgpu_connector *aconnector = to_amdgpu_connector(connector);
1188 const struct dc_link *link = aconnector->dc_link;
1189 struct amdgpu_device *adev = connector->dev->dev_private;
1190 struct amdgpu_display_manager *dm = &adev->dm;
1191#if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) ||\
1192 defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
1193
1194 if (link->connector_signal & (SIGNAL_TYPE_EDP | SIGNAL_TYPE_LVDS)) {
1195 amdgpu_dm_register_backlight_device(dm);
1196
1197 if (dm->backlight_dev) {
1198 backlight_device_unregister(dm->backlight_dev);
1199 dm->backlight_dev = NULL;
1200 }
1201
1202 }
1203#endif
1204 drm_connector_unregister(connector);
1205 drm_connector_cleanup(connector);
1206 kfree(connector);
1207}
1208
1209void amdgpu_dm_connector_funcs_reset(struct drm_connector *connector)
1210{
1211 struct dm_connector_state *state =
1212 to_dm_connector_state(connector->state);
1213
1214 kfree(state);
1215
1216 state = kzalloc(sizeof(*state), GFP_KERNEL);
1217
1218 if (state) {
1219 state->scaling = RMX_OFF;
1220 state->underscan_enable = false;
1221 state->underscan_hborder = 0;
1222 state->underscan_vborder = 0;
1223
1224 connector->state = &state->base;
1225 connector->state->connector = connector;
1226 }
1227}
1228
1229struct drm_connector_state *amdgpu_dm_connector_atomic_duplicate_state(
1230 struct drm_connector *connector)
1231{
1232 struct dm_connector_state *state =
1233 to_dm_connector_state(connector->state);
1234
1235 struct dm_connector_state *new_state =
1236 kmemdup(state, sizeof(*state), GFP_KERNEL);
1237
1238 if (new_state) {
1239 __drm_atomic_helper_connector_duplicate_state(connector,
1240 &new_state->base);
1241 return &new_state->base;
1242 }
1243
1244 return NULL;
1245}
1246
1247static const struct drm_connector_funcs amdgpu_dm_connector_funcs = {
1248 .reset = amdgpu_dm_connector_funcs_reset,
1249 .detect = amdgpu_dm_connector_detect,
1250 .fill_modes = drm_helper_probe_single_connector_modes,
1251 .destroy = amdgpu_dm_connector_destroy,
1252 .atomic_duplicate_state = amdgpu_dm_connector_atomic_duplicate_state,
1253 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
1254 .atomic_set_property = amdgpu_dm_connector_atomic_set_property
1255};
1256
1257static struct drm_encoder *best_encoder(struct drm_connector *connector)
1258{
1259 int enc_id = connector->encoder_ids[0];
1260 struct drm_mode_object *obj;
1261 struct drm_encoder *encoder;
1262
1263 DRM_DEBUG_KMS("Finding the best encoder\n");
1264
1265 /* pick the encoder ids */
1266 if (enc_id) {
1267 obj = drm_mode_object_find(connector->dev, enc_id, DRM_MODE_OBJECT_ENCODER);
1268 if (!obj) {
1269 DRM_ERROR("Couldn't find a matching encoder for our connector\n");
1270 return NULL;
1271 }
1272 encoder = obj_to_encoder(obj);
1273 return encoder;
1274 }
1275 DRM_ERROR("No encoder id\n");
1276 return NULL;
1277}
1278
1279static int get_modes(struct drm_connector *connector)
1280{
1281 return amdgpu_dm_connector_get_modes(connector);
1282}
1283
1284static void create_eml_sink(struct amdgpu_connector *aconnector)
1285{
1286 struct dc_sink_init_data init_params = {
1287 .link = aconnector->dc_link,
1288 .sink_signal = SIGNAL_TYPE_VIRTUAL
1289 };
1290 struct edid *edid = (struct edid *) aconnector->base.edid_blob_ptr->data;
1291
1292 if (!aconnector->base.edid_blob_ptr ||
1293 !aconnector->base.edid_blob_ptr->data) {
1294 DRM_ERROR("No EDID firmware found on connector: %s ,forcing to OFF!\n",
1295 aconnector->base.name);
1296
1297 aconnector->base.force = DRM_FORCE_OFF;
1298 aconnector->base.override_edid = false;
1299 return;
1300 }
1301
1302 aconnector->edid = edid;
1303
1304 aconnector->dc_em_sink = dc_link_add_remote_sink(
1305 aconnector->dc_link,
1306 (uint8_t *)edid,
1307 (edid->extensions + 1) * EDID_LENGTH,
1308 &init_params);
1309
1310 if (aconnector->base.force
1311 == DRM_FORCE_ON)
1312 aconnector->dc_sink = aconnector->dc_link->local_sink ?
1313 aconnector->dc_link->local_sink :
1314 aconnector->dc_em_sink;
1315}
1316
1317static void handle_edid_mgmt(struct amdgpu_connector *aconnector)
1318{
1319 struct dc_link *link = (struct dc_link *)aconnector->dc_link;
1320
1321 /* In case of headless boot with force on for DP managed connector
1322 * Those settings have to be != 0 to get initial modeset
1323 */
1324 if (link->connector_signal == SIGNAL_TYPE_DISPLAY_PORT) {
1325 link->verified_link_cap.lane_count = LANE_COUNT_FOUR;
1326 link->verified_link_cap.link_rate = LINK_RATE_HIGH2;
1327 }
1328
1329
1330 aconnector->base.override_edid = true;
1331 create_eml_sink(aconnector);
1332}
1333
1334int amdgpu_dm_connector_mode_valid(
1335 struct drm_connector *connector,
1336 struct drm_display_mode *mode)
1337{
1338 int result = MODE_ERROR;
1339 const struct dc_sink *dc_sink;
1340 struct amdgpu_device *adev = connector->dev->dev_private;
1341 struct dc_validation_set val_set = { 0 };
1342 /* TODO: Unhardcode stream count */
ab2541b6 1343 struct dc_stream *stream;
4562236b
HW		 1344 struct amdgpu_connector *aconnector = to_amdgpu_connector(connector);
1345
1346 if ((mode->flags & DRM_MODE_FLAG_INTERLACE) ||
1347 (mode->flags & DRM_MODE_FLAG_DBLSCAN))
1348 return result;
1349
1350 /* Only run this the first time mode_valid is called to initilialize
1351 * EDID mgmt
1352 */
1353 if (aconnector->base.force != DRM_FORCE_UNSPECIFIED &&
1354 !aconnector->dc_em_sink)
1355 handle_edid_mgmt(aconnector);
1356
1357 dc_sink = to_amdgpu_connector(connector)->dc_sink;
1358
1359 if (NULL == dc_sink) {
1360 DRM_ERROR("dc_sink is NULL!\n");
ab2541b6 1361 goto null_sink;
4562236b
HW		 1362 }
1363
ab2541b6
AC		 1364 stream = dc_create_stream_for_sink(dc_sink);
1365 if (NULL == stream) {
4562236b
HW		 1366 DRM_ERROR("Failed to create stream for sink!\n");
1367 goto stream_create_fail;
1368 }
1369
1370 drm_mode_set_crtcinfo(mode, 0);
ab2541b6 1371 fill_stream_properties_from_drm_display_mode(stream, mode, connector);
4562236b 1372
ab2541b6 1373 val_set.stream = stream;
4562236b 1374 val_set.surface_count = 0;
ab2541b6
AC		 1375 stream->src.width = mode->hdisplay;
1376 stream->src.height = mode->vdisplay;
1377 stream->dst = stream->src;
4562236b
HW		 1378
1379 if (dc_validate_resources(adev->dm.dc, &val_set, 1))
1380 result = MODE_OK;
1381
ab2541b6
AC		 1382 dc_stream_release(stream);
1383
4562236b 1384stream_create_fail:
ab2541b6 1385null_sink:
4562236b
HW		 1386 /* TODO: error handling*/
1387 return result;
1388}
1389
1390static const struct drm_connector_helper_funcs
1391amdgpu_dm_connector_helper_funcs = {
1392 /*
1393 * If hotplug a second bigger display in FB Con mode, bigger resolution
1394 * modes will be filtered by drm_mode_validate_size(), and those modes
1395 * is missing after user start lightdm. So we need to renew modes list.
1396 * in get_modes call back, not just return the modes count
1397 */
1398 .get_modes = get_modes,
1399 .mode_valid = amdgpu_dm_connector_mode_valid,
1400 .best_encoder = best_encoder
1401};
1402
1403static void dm_crtc_helper_disable(struct drm_crtc *crtc)
1404{
1405}
1406
1407static int dm_crtc_helper_atomic_check(
1408 struct drm_crtc *crtc,
1409 struct drm_crtc_state *state)
1410{
1411 return 0;
1412}
1413
1414static bool dm_crtc_helper_mode_fixup(
1415 struct drm_crtc *crtc,
1416 const struct drm_display_mode *mode,
1417 struct drm_display_mode *adjusted_mode)
1418{
1419 return true;
1420}
1421
1422static const struct drm_crtc_helper_funcs amdgpu_dm_crtc_helper_funcs = {
1423 .disable = dm_crtc_helper_disable,
1424 .atomic_check = dm_crtc_helper_atomic_check,
1425 .mode_fixup = dm_crtc_helper_mode_fixup
1426};
1427
1428static void dm_encoder_helper_disable(struct drm_encoder *encoder)
1429{
1430
1431}
1432
1433static int dm_encoder_helper_atomic_check(
1434 struct drm_encoder *encoder,
1435 struct drm_crtc_state *crtc_state,
1436 struct drm_connector_state *conn_state)
1437{
1438 return 0;
1439}
1440
1441const struct drm_encoder_helper_funcs amdgpu_dm_encoder_helper_funcs = {
1442 .disable = dm_encoder_helper_disable,
1443 .atomic_check = dm_encoder_helper_atomic_check
1444};
1445
1446static const struct drm_plane_funcs dm_plane_funcs = {
1447 .reset = drm_atomic_helper_plane_reset,
1448 .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state,
1449 .atomic_destroy_state = drm_atomic_helper_plane_destroy_state
1450};
1451
4562236b
HW		 1452static int dm_plane_helper_prepare_fb(
1453 struct drm_plane *plane,
1454 struct drm_plane_state *new_state)
1455{
1456 struct amdgpu_framebuffer *afb;
1457 struct drm_gem_object *obj;
1458 struct amdgpu_bo *rbo;
1459 int r;
1460
1461 if (!new_state->fb) {
1462 DRM_DEBUG_KMS("No FB bound\n");
1463 return 0;
1464 }
1465
1466 afb = to_amdgpu_framebuffer(new_state->fb);
1467
1468 obj = afb->obj;
1469 rbo = gem_to_amdgpu_bo(obj);
1470 r = amdgpu_bo_reserve(rbo, false);
1471 if (unlikely(r != 0))
1472 return r;
1473
54f5499a 1474 r = amdgpu_bo_pin(rbo, AMDGPU_GEM_DOMAIN_VRAM, &afb->address);
4562236b
HW		 1475
1476 amdgpu_bo_unreserve(rbo);
1477
1478 if (unlikely(r != 0)) {
1479 DRM_ERROR("Failed to pin framebuffer\n");
1480 return r;
1481 }
1482
54f5499a 1483 amdgpu_bo_ref(rbo);
4562236b
HW		 1484 return 0;
1485}
1486
1487static void dm_plane_helper_cleanup_fb(
1488 struct drm_plane *plane,
1489 struct drm_plane_state *old_state)
1490{
1491 struct amdgpu_bo *rbo;
1492 struct amdgpu_framebuffer *afb;
1493 int r;
1494
1495 if (!old_state->fb)
1496 return;
1497
1498 afb = to_amdgpu_framebuffer(old_state->fb);
1499 rbo = gem_to_amdgpu_bo(afb->obj);
1500 r = amdgpu_bo_reserve(rbo, false);
1501 if (unlikely(r)) {
1502 DRM_ERROR("failed to reserve rbo before unpin\n");
1503 return;
1504 } else {
1505 amdgpu_bo_unpin(rbo);
1506 amdgpu_bo_unreserve(rbo);
54f5499a 1507 amdgpu_bo_unref(&rbo);
4562236b 1508 }
54f5499a
AG		 1509
1510 afb->address = 0;
4562236b
HW		 1511}
1512
ab2541b6 1513int dm_create_validation_set_for_connector(struct drm_connector *connector,
4562236b
HW		 1514 struct drm_display_mode *mode, struct dc_validation_set *val_set)
1515{
1516 int result = MODE_ERROR;
1517 const struct dc_sink *dc_sink =
1518 to_amdgpu_connector(connector)->dc_sink;
1519 /* TODO: Unhardcode stream count */
ab2541b6 1520 struct dc_stream *stream;
4562236b
HW		 1521
1522 if ((mode->flags & DRM_MODE_FLAG_INTERLACE) ||
1523 (mode->flags & DRM_MODE_FLAG_DBLSCAN))
1524 return result;
1525
1526 if (NULL == dc_sink) {
1527 DRM_ERROR("dc_sink is NULL!\n");
1528 return result;
1529 }
1530
ab2541b6 1531 stream = dc_create_stream_for_sink(dc_sink);
4562236b 1532
ab2541b6 1533 if (NULL == stream) {
4562236b
HW		 1534 DRM_ERROR("Failed to create stream for sink!\n");
1535 return result;
1536 }
1537
1538 drm_mode_set_crtcinfo(mode, 0);
1539
ab2541b6 1540 fill_stream_properties_from_drm_display_mode(stream, mode, connector);
4562236b 1541
ab2541b6 1542 val_set->stream = stream;
4562236b 1543
ab2541b6
AC		 1544 stream->src.width = mode->hdisplay;
1545 stream->src.height = mode->vdisplay;
1546 stream->dst = stream->src;
4562236b
HW		 1547
1548 return MODE_OK;
4562236b
HW		 1549}
1550
1551static const struct drm_plane_helper_funcs dm_plane_helper_funcs = {
1552 .prepare_fb = dm_plane_helper_prepare_fb,
1553 .cleanup_fb = dm_plane_helper_cleanup_fb,
1554};
1555
1556/*
1557 * TODO: these are currently initialized to rgb formats only.
1558 * For future use cases we should either initialize them dynamically based on
1559 * plane capabilities, or initialize this array to all formats, so internal drm
1560 * check will succeed, and let DC to implement proper check
1561 */
1562static uint32_t rgb_formats[] = {
1563 DRM_FORMAT_XRGB4444,
1564 DRM_FORMAT_ARGB4444,
1565 DRM_FORMAT_RGBA4444,
1566 DRM_FORMAT_ARGB1555,
1567 DRM_FORMAT_RGB565,
1568 DRM_FORMAT_RGB888,
1569 DRM_FORMAT_XRGB8888,
1570 DRM_FORMAT_ARGB8888,
1571 DRM_FORMAT_RGBA8888,
1572 DRM_FORMAT_XRGB2101010,
1573 DRM_FORMAT_XBGR2101010,
1574 DRM_FORMAT_ARGB2101010,
1575 DRM_FORMAT_ABGR2101010,
1576};
1577
1578int amdgpu_dm_crtc_init(struct amdgpu_display_manager *dm,
1579 struct amdgpu_crtc *acrtc,
1580 uint32_t crtc_index)
1581{
1582 int res = -ENOMEM;
1583
1584 struct drm_plane *primary_plane =
1585 kzalloc(sizeof(*primary_plane), GFP_KERNEL);
1586
1587 if (!primary_plane)
1588 goto fail_plane;
1589
1590 primary_plane->format_default = true;
1591
1592 res = drm_universal_plane_init(
1593 dm->adev->ddev,
1594 primary_plane,
1595 0,
1596 &dm_plane_funcs,
1597 rgb_formats,
1598 ARRAY_SIZE(rgb_formats),
1599 NULL,
1600 DRM_PLANE_TYPE_PRIMARY, NULL);
1601
1602 primary_plane->crtc = &acrtc->base;
1603
1604 drm_plane_helper_add(primary_plane, &dm_plane_helper_funcs);
1605
1606 res = drm_crtc_init_with_planes(
1607 dm->ddev,
1608 &acrtc->base,
1609 primary_plane,
1610 NULL,
1611 &amdgpu_dm_crtc_funcs, NULL);
1612
1613 if (res)
1614 goto fail;
1615
1616 drm_crtc_helper_add(&acrtc->base, &amdgpu_dm_crtc_helper_funcs);
1617
1618 acrtc->max_cursor_width = 128;
1619 acrtc->max_cursor_height = 128;
1620
1621 acrtc->crtc_id = crtc_index;
1622 acrtc->base.enabled = false;
1623
1624 dm->adev->mode_info.crtcs[crtc_index] = acrtc;
1625 drm_mode_crtc_set_gamma_size(&acrtc->base, 256);
1626
1627 return 0;
1628fail:
1629 kfree(primary_plane);
1630fail_plane:
1631 acrtc->crtc_id = -1;
1632 return res;
1633}
1634
1635static int to_drm_connector_type(enum signal_type st)
1636{
1637 switch (st) {
1638 case SIGNAL_TYPE_HDMI_TYPE_A:
1639 return DRM_MODE_CONNECTOR_HDMIA;
1640 case SIGNAL_TYPE_EDP:
1641 return DRM_MODE_CONNECTOR_eDP;
1642 case SIGNAL_TYPE_RGB:
1643 return DRM_MODE_CONNECTOR_VGA;
1644 case SIGNAL_TYPE_DISPLAY_PORT:
1645 case SIGNAL_TYPE_DISPLAY_PORT_MST:
1646 return DRM_MODE_CONNECTOR_DisplayPort;
1647 case SIGNAL_TYPE_DVI_DUAL_LINK:
1648 case SIGNAL_TYPE_DVI_SINGLE_LINK:
1649 return DRM_MODE_CONNECTOR_DVID;
1650 case SIGNAL_TYPE_VIRTUAL:
1651 return DRM_MODE_CONNECTOR_VIRTUAL;
1652
1653 default:
1654 return DRM_MODE_CONNECTOR_Unknown;
1655 }
1656}
1657
1658static void amdgpu_dm_get_native_mode(struct drm_connector *connector)
1659{
1660 const struct drm_connector_helper_funcs *helper =
1661 connector->helper_private;
1662 struct drm_encoder *encoder;
1663 struct amdgpu_encoder *amdgpu_encoder;
1664
1665 encoder = helper->best_encoder(connector);
1666
1667 if (encoder == NULL)
1668 return;
1669
1670 amdgpu_encoder = to_amdgpu_encoder(encoder);
1671
1672 amdgpu_encoder->native_mode.clock = 0;
1673
1674 if (!list_empty(&connector->probed_modes)) {
1675 struct drm_display_mode *preferred_mode = NULL;
1676 list_for_each_entry(preferred_mode,
1677 &connector->probed_modes,
1678 head) {
1679 if (preferred_mode->type & DRM_MODE_TYPE_PREFERRED) {
1680 amdgpu_encoder->native_mode = *preferred_mode;
1681 }
1682 break;
1683 }
1684
1685 }
1686}
1687
1688static struct drm_display_mode *amdgpu_dm_create_common_mode(
1689 struct drm_encoder *encoder, char *name,
1690 int hdisplay, int vdisplay)
1691{
1692 struct drm_device *dev = encoder->dev;
1693 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1694 struct drm_display_mode *mode = NULL;
1695 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
1696
1697 mode = drm_mode_duplicate(dev, native_mode);
1698
1699 if(mode == NULL)
1700 return NULL;
1701
1702 mode->hdisplay = hdisplay;
1703 mode->vdisplay = vdisplay;
1704 mode->type &= ~DRM_MODE_TYPE_PREFERRED;
1705 strncpy(mode->name, name, DRM_DISPLAY_MODE_LEN);
1706
1707 return mode;
1708
1709}
1710
1711static void amdgpu_dm_connector_add_common_modes(struct drm_encoder *encoder,
1712 struct drm_connector *connector)
1713{
1714 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1715 struct drm_display_mode *mode = NULL;
1716 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
1717 struct amdgpu_connector *amdgpu_connector =
1718 to_amdgpu_connector(connector);
1719 int i;
1720 int n;
1721 struct mode_size {
1722 char name[DRM_DISPLAY_MODE_LEN];
1723 int w;
1724 int h;
1725 }common_modes[] = {
1726 { "640x480", 640, 480},
1727 { "800x600", 800, 600},
1728 { "1024x768", 1024, 768},
1729 { "1280x720", 1280, 720},
1730 { "1280x800", 1280, 800},
1731 {"1280x1024", 1280, 1024},
1732 { "1440x900", 1440, 900},
1733 {"1680x1050", 1680, 1050},
1734 {"1600x1200", 1600, 1200},
1735 {"1920x1080", 1920, 1080},
1736 {"1920x1200", 1920, 1200}
1737 };
1738
1739 n = sizeof(common_modes) / sizeof(common_modes[0]);
1740
1741 for (i = 0; i < n; i++) {
1742 struct drm_display_mode *curmode = NULL;
1743 bool mode_existed = false;
1744
1745 if (common_modes[i].w > native_mode->hdisplay ||
1746 common_modes[i].h > native_mode->vdisplay ||
1747 (common_modes[i].w == native_mode->hdisplay &&
1748 common_modes[i].h == native_mode->vdisplay))
1749 continue;
1750
1751 list_for_each_entry(curmode, &connector->probed_modes, head) {
1752 if (common_modes[i].w == curmode->hdisplay &&
1753 common_modes[i].h == curmode->vdisplay) {
1754 mode_existed = true;
1755 break;
1756 }
1757 }
1758
1759 if (mode_existed)
1760 continue;
1761
1762 mode = amdgpu_dm_create_common_mode(encoder,
1763 common_modes[i].name, common_modes[i].w,
1764 common_modes[i].h);
1765 drm_mode_probed_add(connector, mode);
1766 amdgpu_connector->num_modes++;
1767 }
1768}
1769
1770static void amdgpu_dm_connector_ddc_get_modes(
1771 struct drm_connector *connector,
1772 struct edid *edid)
1773{
1774 struct amdgpu_connector *amdgpu_connector =
1775 to_amdgpu_connector(connector);
1776
1777 if (edid) {
1778 /* empty probed_modes */
1779 INIT_LIST_HEAD(&connector->probed_modes);
1780 amdgpu_connector->num_modes =
1781 drm_add_edid_modes(connector, edid);
1782
1783 drm_edid_to_eld(connector, edid);
1784
1785 amdgpu_dm_get_native_mode(connector);
1786 } else
1787 amdgpu_connector->num_modes = 0;
1788}
1789
1790int amdgpu_dm_connector_get_modes(struct drm_connector *connector)
1791{
1792 const struct drm_connector_helper_funcs *helper =
1793 connector->helper_private;
1794 struct amdgpu_connector *amdgpu_connector =
1795 to_amdgpu_connector(connector);
1796 struct drm_encoder *encoder;
1797 struct edid *edid = amdgpu_connector->edid;
1798
1799 encoder = helper->best_encoder(connector);
1800
1801 amdgpu_dm_connector_ddc_get_modes(connector, edid);
1802 amdgpu_dm_connector_add_common_modes(encoder, connector);
1803 return amdgpu_connector->num_modes;
1804}
1805
1806void amdgpu_dm_connector_init_helper(
1807 struct amdgpu_display_manager *dm,
1808 struct amdgpu_connector *aconnector,
1809 int connector_type,
1810 const struct dc_link *link,
1811 int link_index)
1812{
1813 struct amdgpu_device *adev = dm->ddev->dev_private;
1814
1815 aconnector->connector_id = link_index;
1816 aconnector->dc_link = link;
67a27705
HW		 1817 aconnector->base.interlace_allowed = false;
1818 aconnector->base.doublescan_allowed = false;
1819 aconnector->base.stereo_allowed = false;
4562236b
HW		 1820 aconnector->base.dpms = DRM_MODE_DPMS_OFF;
1821 aconnector->hpd.hpd = AMDGPU_HPD_NONE; /* not used */
1822
1823 mutex_init(&aconnector->hpd_lock);
1824
1825 /*configure suport HPD hot plug connector_>polled default value is 0
1826 * which means HPD hot plug not supported*/
1827 switch (connector_type) {
1828 case DRM_MODE_CONNECTOR_HDMIA:
1829 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD;
1830 break;
1831 case DRM_MODE_CONNECTOR_DisplayPort:
1832 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD;
1833 break;
1834 case DRM_MODE_CONNECTOR_DVID:
1835 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD;
1836 break;
1837 default:
1838 break;
1839 }
1840
1841 drm_object_attach_property(&aconnector->base.base,
1842 dm->ddev->mode_config.scaling_mode_property,
1843 DRM_MODE_SCALE_NONE);
1844
1845 drm_object_attach_property(&aconnector->base.base,
1846 adev->mode_info.underscan_property,
1847 UNDERSCAN_OFF);
1848 drm_object_attach_property(&aconnector->base.base,
1849 adev->mode_info.underscan_hborder_property,
1850 0);
1851 drm_object_attach_property(&aconnector->base.base,
1852 adev->mode_info.underscan_vborder_property,
1853 0);
1854
1855}
1856
1857int amdgpu_dm_i2c_xfer(struct i2c_adapter *i2c_adap,
1858 struct i2c_msg *msgs, int num)
1859{
1860 struct amdgpu_i2c_adapter *i2c = i2c_get_adapdata(i2c_adap);
1861 struct i2c_command cmd;
1862 int i;
1863 int result = -EIO;
1864
1865 cmd.payloads = kzalloc(num * sizeof(struct i2c_payload), GFP_KERNEL);
1866
1867 if (!cmd.payloads)
1868 return result;
1869
1870 cmd.number_of_payloads = num;
1871 cmd.engine = I2C_COMMAND_ENGINE_DEFAULT;
1872 cmd.speed = 100;
1873
1874 for (i = 0; i < num; i++) {
1875 cmd.payloads[i].write = (msgs[i].flags & I2C_M_RD);
1876 cmd.payloads[i].address = msgs[i].addr;
1877 cmd.payloads[i].length = msgs[i].len;
1878 cmd.payloads[i].data = msgs[i].buf;
1879 }
1880
1881 if (dc_submit_i2c(i2c->dm->dc, i2c->link_index, &cmd))
1882 result = num;
1883
1884 kfree(cmd.payloads);
1885
1886 return result;
1887}
1888
1889u32 amdgpu_dm_i2c_func(struct i2c_adapter *adap)
1890{
1891 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
1892}
1893
1894static const struct i2c_algorithm amdgpu_dm_i2c_algo = {
1895 .master_xfer = amdgpu_dm_i2c_xfer,
1896 .functionality = amdgpu_dm_i2c_func,
1897};
1898
1899struct amdgpu_i2c_adapter *create_i2c(unsigned int link_index, struct amdgpu_display_manager *dm, int *res)
1900{
1901 struct amdgpu_i2c_adapter *i2c;
1902
1903 i2c = kzalloc(sizeof (struct amdgpu_i2c_adapter), GFP_KERNEL);
1904 i2c->dm = dm;
1905 i2c->base.owner = THIS_MODULE;
1906 i2c->base.class = I2C_CLASS_DDC;
1907 i2c->base.dev.parent = &dm->adev->pdev->dev;
1908 i2c->base.algo = &amdgpu_dm_i2c_algo;
1909 snprintf(i2c->base.name, sizeof (i2c->base.name), "AMDGPU DM i2c hw bus %d", link_index);
1910 i2c->link_index = link_index;
1911 i2c_set_adapdata(&i2c->base, i2c);
1912
1913 return i2c;
1914}
1915
1916/* Note: this function assumes that dc_link_detect() was called for the
1917 * dc_link which will be represented by this aconnector. */
1918int amdgpu_dm_connector_init(
1919 struct amdgpu_display_manager *dm,
1920 struct amdgpu_connector *aconnector,
1921 uint32_t link_index,
1922 struct amdgpu_encoder *aencoder)
1923{
1924 int res = 0;
1925 int connector_type;
1926 struct dc *dc = dm->dc;
1927 const struct dc_link *link = dc_get_link_at_index(dc, link_index);
1928 struct amdgpu_i2c_adapter *i2c;
1929
1930 DRM_DEBUG_KMS("%s()\n", __func__);
1931
1932 i2c = create_i2c(link->link_index, dm, &res);
1933 aconnector->i2c = i2c;
1934 res = i2c_add_adapter(&i2c->base);
1935
1936 if (res) {
1937 DRM_ERROR("Failed to register hw i2c %d\n", link->link_index);
1938 goto out_free;
1939 }
1940
1941 connector_type = to_drm_connector_type(link->connector_signal);
1942
1943 res = drm_connector_init(
1944 dm->ddev,
1945 &aconnector->base,
1946 &amdgpu_dm_connector_funcs,
1947 connector_type);
1948
1949 if (res) {
1950 DRM_ERROR("connector_init failed\n");
1951 aconnector->connector_id = -1;
1952 goto out_free;
1953 }
1954
1955 drm_connector_helper_add(
1956 &aconnector->base,
1957 &amdgpu_dm_connector_helper_funcs);
1958
1959 amdgpu_dm_connector_init_helper(
1960 dm,
1961 aconnector,
1962 connector_type,
1963 link,
1964 link_index);
1965
1966 drm_mode_connector_attach_encoder(
1967 &aconnector->base, &aencoder->base);
1968
1969 drm_connector_register(&aconnector->base);
1970
1971 if (connector_type == DRM_MODE_CONNECTOR_DisplayPort
1972 || connector_type == DRM_MODE_CONNECTOR_eDP)
1973 amdgpu_dm_initialize_mst_connector(dm, aconnector);
1974
1975#if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) ||\
1976 defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
1977
1978 /* NOTE: this currently will create backlight device even if a panel
1979 * is not connected to the eDP/LVDS connector.
1980 *
1981 * This is less than ideal but we don't have sink information at this
1982 * stage since detection happens after. We can't do detection earlier
1983 * since MST detection needs connectors to be created first.
1984 */
1985 if (link->connector_signal & (SIGNAL_TYPE_EDP | SIGNAL_TYPE_LVDS)) {
1986 /* Event if registration failed, we should continue with
1987 * DM initialization because not having a backlight control
1988 * is better then a black screen. */
1989 amdgpu_dm_register_backlight_device(dm);
1990
1991 if (dm->backlight_dev)
1992 dm->backlight_link = link;
1993 }
1994#endif
1995
1996out_free:
1997 if (res) {
1998 kfree(i2c);
1999 aconnector->i2c = NULL;
2000 }
2001 return res;
2002}
2003
2004int amdgpu_dm_get_encoder_crtc_mask(struct amdgpu_device *adev)
2005{
2006 switch (adev->mode_info.num_crtc) {
2007 case 1:
2008 return 0x1;
2009 case 2:
2010 return 0x3;
2011 case 3:
2012 return 0x7;
2013 case 4:
2014 return 0xf;
2015 case 5:
2016 return 0x1f;
2017 case 6:
2018 default:
2019 return 0x3f;
2020 }
2021}
2022
2023int amdgpu_dm_encoder_init(
2024 struct drm_device *dev,
2025 struct amdgpu_encoder *aencoder,
2026 uint32_t link_index)
2027{
2028 struct amdgpu_device *adev = dev->dev_private;
2029
2030 int res = drm_encoder_init(dev,
2031 &aencoder->base,
2032 &amdgpu_dm_encoder_funcs,
2033 DRM_MODE_ENCODER_TMDS,
2034 NULL);
2035
2036 aencoder->base.possible_crtcs = amdgpu_dm_get_encoder_crtc_mask(adev);
2037
2038 if (!res)
2039 aencoder->encoder_id = link_index;
2040 else
2041 aencoder->encoder_id = -1;
2042
2043 drm_encoder_helper_add(&aencoder->base, &amdgpu_dm_encoder_helper_funcs);
2044
2045 return res;
2046}
2047
2048enum dm_commit_action {
2049 DM_COMMIT_ACTION_NOTHING,
2050 DM_COMMIT_ACTION_RESET,
2051 DM_COMMIT_ACTION_DPMS_ON,
2052 DM_COMMIT_ACTION_DPMS_OFF,
2053 DM_COMMIT_ACTION_SET
2054};
2055
2056static enum dm_commit_action get_dm_commit_action(struct drm_crtc_state *state)
2057{
2058 /* mode changed means either actually mode changed or enabled changed */
2059 /* active changed means dpms changed */
2060
2061 DRM_DEBUG_KMS("crtc_state_flags: enable:%d, active:%d, planes_changed:%d, mode_changed:%d,active_changed:%d,connectors_changed:%d\n",
2062 state->enable,
2063 state->active,
2064 state->planes_changed,
2065 state->mode_changed,
2066 state->active_changed,
2067 state->connectors_changed);
2068
2069 if (state->mode_changed) {
2070 /* if it is got disabled - call reset mode */
2071 if (!state->enable)
2072 return DM_COMMIT_ACTION_RESET;
2073
2074 if (state->active)
2075 return DM_COMMIT_ACTION_SET;
2076 else
2077 return DM_COMMIT_ACTION_RESET;
2078 } else {
2079 /* ! mode_changed */
2080
2081 /* if it is remain disable - skip it */
2082 if (!state->enable)
2083 return DM_COMMIT_ACTION_NOTHING;
2084
2085 if (state->active && state->connectors_changed)
2086 return DM_COMMIT_ACTION_SET;
2087
2088 if (state->active_changed) {
2089 if (state->active) {
2090 return DM_COMMIT_ACTION_DPMS_ON;
2091 } else {
2092 return DM_COMMIT_ACTION_DPMS_OFF;
2093 }
2094 } else {
2095 /* ! active_changed */
2096 return DM_COMMIT_ACTION_NOTHING;
2097 }
2098 }
2099}
2100
4562236b
HW		 2101static void manage_dm_interrupts(
2102 struct amdgpu_device *adev,
2103 struct amdgpu_crtc *acrtc,
2104 bool enable)
2105{
2106 /*
2107 * this is not correct translation but will work as soon as VBLANK
2108 * constant is the same as PFLIP
2109 */
2110 int irq_type =
2111 amdgpu_crtc_idx_to_irq_type(
2112 adev,
2113 acrtc->crtc_id);
2114
2115 if (enable) {
2116 drm_crtc_vblank_on(&acrtc->base);
2117 amdgpu_irq_get(
2118 adev,
2119 &adev->pageflip_irq,
2120 irq_type);
2121 } else {
4562236b
HW		 2122
2123 amdgpu_irq_put(
2124 adev,
2125 &adev->pageflip_irq,
2126 irq_type);
2127 drm_crtc_vblank_off(&acrtc->base);
2128 }
2129}
2130
4562236b
HW		 2131static bool is_scaling_state_different(
2132 const struct dm_connector_state *dm_state,
2133 const struct dm_connector_state *old_dm_state)
2134{
2135 if (dm_state->scaling != old_dm_state->scaling)
2136 return true;
2137 if (!dm_state->underscan_enable && old_dm_state->underscan_enable) {
2138 if (old_dm_state->underscan_hborder != 0 && old_dm_state->underscan_vborder != 0)
2139 return true;
2140 } else if (dm_state->underscan_enable && !old_dm_state->underscan_enable) {
2141 if (dm_state->underscan_hborder != 0 && dm_state->underscan_vborder != 0)
2142 return true;
2143 } else if (dm_state->underscan_hborder != old_dm_state->underscan_hborder
2144 || dm_state->underscan_vborder != old_dm_state->underscan_vborder)
2145 return true;
2146 return false;
2147}
2148
ab2541b6 2149static void remove_stream(struct amdgpu_device *adev, struct amdgpu_crtc *acrtc)
4562236b 2150{
4562236b
HW		 2151 /*
2152 * we evade vblanks and pflips on crtc that
2153 * should be changed
2154 */
2155 manage_dm_interrupts(adev, acrtc, false);
ab2541b6 2156
4562236b
HW		 2157 /* this is the update mode case */
2158 if (adev->dm.freesync_module)
ab2541b6
AC		 2159 mod_freesync_remove_stream(adev->dm.freesync_module,
2160 acrtc->stream);
2161
2162 dc_stream_release(acrtc->stream);
2163 acrtc->stream = NULL;
4562236b
HW		 2164 acrtc->otg_inst = -1;
2165 acrtc->enabled = false;
2166}
2167
54f5499a
AG		 2168
2169/*
2170 * Executes flip
2171 *
2172 * Waits on all BO's fences and for proper vblank count
2173 */
2174static void amdgpu_dm_do_flip(
2175 struct drm_crtc *crtc,
2176 struct drm_framebuffer *fb,
2177 uint32_t target)
2178{
2179 unsigned long flags;
2180 uint32_t target_vblank;
2181 int r, vpos, hpos;
2182 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
2183 struct amdgpu_framebuffer *afb = to_amdgpu_framebuffer(fb);
2184 struct amdgpu_bo *abo = gem_to_amdgpu_bo(afb->obj);
2185 struct amdgpu_device *adev = crtc->dev->dev_private;
2186 bool async_flip = (acrtc->flip_flags & DRM_MODE_PAGE_FLIP_ASYNC) != 0;
2187
2188
2189 /*TODO This might fail and hence better not used, wait
2190 * explicitly on fences instead
2191 * and in general should be called for
2192 * blocking commit to as per framework helpers
2193 * */
2194 r = amdgpu_bo_reserve(abo, true);
2195 if (unlikely(r != 0)) {
2196 DRM_ERROR("failed to reserve buffer before flip\n");
2197 BUG_ON(0);
2198 }
2199
2200 /* Wait for all fences on this FB */
2201 WARN_ON(reservation_object_wait_timeout_rcu(abo->tbo.resv, true, false,
2202 MAX_SCHEDULE_TIMEOUT) < 0);
2203
2204 amdgpu_bo_unreserve(abo);
2205
2206 /* Wait for target vblank */
2207 /* Wait until we're out of the vertical blank period before the one
2208 * targeted by the flip
2209 */
2210 target_vblank = target - drm_crtc_vblank_count(crtc) +
2211 amdgpu_get_vblank_counter_kms(crtc->dev, acrtc->crtc_id);
2212
2213 while ((acrtc->enabled &&
2214 (amdgpu_get_crtc_scanoutpos(adev->ddev, acrtc->crtc_id, 0,
2215 &vpos, &hpos, NULL, NULL,
2216 &crtc->hwmode)
2217 & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK)) ==
2218 (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK) &&
2219 (int)(target_vblank -
2220 amdgpu_get_vblank_counter_kms(adev->ddev, acrtc->crtc_id)) > 0)) {
2221 usleep_range(1000, 1100);
2222 }
2223
2224 /* Flip */
2225 spin_lock_irqsave(&crtc->dev->event_lock, flags);
2226 /* update crtc fb */
2227 crtc->primary->fb = fb;
2228
2229 /* Do the flip (mmio) */
2230 adev->mode_info.funcs->page_flip(adev, acrtc->crtc_id, afb->address, async_flip);
2231
2232 spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
2233 DRM_DEBUG_DRIVER("crtc:%d, pflip_stat:AMDGPU_FLIP_SUBMITTED\n",
2234 acrtc->crtc_id);
2235}
2236
2237void amdgpu_dm_atomic_commit_tail(
2238 struct drm_atomic_state *state)
4562236b 2239{
54f5499a 2240 struct drm_device *dev = state->dev;
4562236b
HW		 2241 struct amdgpu_device *adev = dev->dev_private;
2242 struct amdgpu_display_manager *dm = &adev->dm;
2243 struct drm_plane *plane;
4562236b 2244 struct drm_plane_state *old_plane_state;
ab2541b6 2245 uint32_t i;
ab2541b6 2246 uint32_t commit_streams_count = 0;
4562236b 2247 uint32_t new_crtcs_count = 0;
4562236b
HW		 2248 struct drm_crtc *crtc;
2249 struct drm_crtc_state *old_crtc_state;
ab2541b6
AC		 2250 const struct dc_stream *commit_streams[MAX_STREAMS];
2251 struct amdgpu_crtc *new_crtcs[MAX_STREAMS];
2252 const struct dc_stream *new_stream;
54f5499a
AG		 2253 unsigned long flags;
2254 bool wait_for_vblank = true;
4562236b 2255
4562236b
HW		 2256
2257 drm_atomic_helper_update_legacy_modeset_state(dev, state);
2258
2259 /* update changed items */
2260 for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
2261 struct amdgpu_crtc *acrtc;
2262 struct amdgpu_connector *aconnector = NULL;
2263 enum dm_commit_action action;
2264 struct drm_crtc_state *new_state = crtc->state;
2265
2266 acrtc = to_amdgpu_crtc(crtc);
2267
2268 aconnector =
2269 amdgpu_dm_find_first_crct_matching_connector(
2270 state,
2271 crtc,
2272 false);
2273
2274 /* handles headless hotplug case, updating new_state and
2275 * aconnector as needed
2276 */
2277
2278 action = get_dm_commit_action(new_state);
2279
2280 switch (action) {
2281 case DM_COMMIT_ACTION_DPMS_ON:
2282 case DM_COMMIT_ACTION_SET: {
2283 struct dm_connector_state *dm_state = NULL;
ab2541b6 2284 new_stream = NULL;
4562236b
HW		 2285
2286 if (aconnector)
2287 dm_state = to_dm_connector_state(aconnector->base.state);
2288
ab2541b6 2289 new_stream = create_stream_for_sink(
4562236b
HW		 2290 aconnector,
2291 &crtc->state->mode,
2292 dm_state);
2293
2294 DRM_INFO("Atomic commit: SET crtc id %d: [%p]\n", acrtc->crtc_id, acrtc);
2295
ab2541b6 2296 if (!new_stream) {
4562236b
HW		 2297 /*
2298 * this could happen because of issues with
2299 * userspace notifications delivery.
2300 * In this case userspace tries to set mode on
2301 * display which is disconnect in fact.
2302 * dc_sink in NULL in this case on aconnector.
2303 * We expect reset mode will come soon.
2304 *
2305 * This can also happen when unplug is done
2306 * during resume sequence ended
2307 *
2308 * In this case, we want to pretend we still
2309 * have a sink to keep the pipe running so that
2310 * hw state is consistent with the sw state
2311 */
ab2541b6 2312 DRM_DEBUG_KMS("%s: Failed to create new stream for crtc %d\n",
4562236b
HW		 2313 __func__, acrtc->base.base.id);
2314 break;
2315 }
2316
ab2541b6
AC		 2317 if (acrtc->stream)
2318 remove_stream(adev, acrtc);
4562236b
HW		 2319
2320 /*
2321 * this loop saves set mode crtcs
2322 * we needed to enable vblanks once all
ab2541b6 2323 * resources acquired in dc after dc_commit_streams
4562236b
HW		 2324 */
2325 new_crtcs[new_crtcs_count] = acrtc;
2326 new_crtcs_count++;
2327
ab2541b6 2328 acrtc->stream = new_stream;
4562236b
HW		 2329 acrtc->enabled = true;
2330 acrtc->hw_mode = crtc->state->mode;
2331 crtc->hwmode = crtc->state->mode;
2332
2333 break;
2334 }
2335
2336 case DM_COMMIT_ACTION_NOTHING: {
2337 struct dm_connector_state *dm_state = NULL;
2338
2339 if (!aconnector)
2340 break;
2341
2342 dm_state = to_dm_connector_state(aconnector->base.state);
2343
2344 /* Scaling update */
ab2541b6
AC		 2345 update_stream_scaling_settings(&crtc->state->mode,
2346 dm_state, acrtc->stream);
4562236b
HW		 2347
2348 break;
2349 }
2350 case DM_COMMIT_ACTION_DPMS_OFF:
2351 case DM_COMMIT_ACTION_RESET:
2352 DRM_INFO("Atomic commit: RESET. crtc id %d:[%p]\n", acrtc->crtc_id, acrtc);
2353 /* i.e. reset mode */
ab2541b6
AC		 2354 if (acrtc->stream)
2355 remove_stream(adev, acrtc);
4562236b
HW		 2356 break;
2357 } /* switch() */
2358 } /* for_each_crtc_in_state() */
2359
2360 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2361
2362 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
2363
ab2541b6
AC		 2364 if (acrtc->stream) {
2365 commit_streams[commit_streams_count] = acrtc->stream;
2366 ++commit_streams_count;
4562236b
HW		 2367 }
2368 }
2369
2370 /*
ab2541b6 2371 * Add streams after required streams from new and replaced streams
4562236b
HW		 2372 * are removed from freesync module
2373 */
2374 if (adev->dm.freesync_module) {
2375 for (i = 0; i < new_crtcs_count; i++) {
2376 struct amdgpu_connector *aconnector = NULL;
ab2541b6 2377 new_stream = new_crtcs[i]->stream;
4562236b
HW		 2378 aconnector =
2379 amdgpu_dm_find_first_crct_matching_connector(
2380 state,
2381 &new_crtcs[i]->base,
2382 false);
2383 if (!aconnector) {
2384 DRM_INFO(
2385 "Atomic commit: Failed to find connector for acrtc id:%d "
2386 "skipping freesync init\n",
2387 new_crtcs[i]->crtc_id);
2388 continue;
2389 }
2390
ab2541b6
AC		 2391 mod_freesync_add_stream(adev->dm.freesync_module,
2392 new_stream, &aconnector->caps);
4562236b
HW		 2393 }
2394 }
2395
ab2541b6 2396 /* DC is optimized not to do anything if 'streams' didn't change. */
53d35dc6 2397 WARN_ON(!dc_commit_streams(dm->dc, commit_streams, commit_streams_count));
4562236b
HW		 2398
2399 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2400 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
2401
ab2541b6 2402 if (acrtc->stream != NULL)
4562236b 2403 acrtc->otg_inst =
ab2541b6 2404 dc_stream_get_status(acrtc->stream)->primary_otg_inst;
4562236b
HW		 2405 }
2406
2407 /* update planes when needed */
2408 for_each_plane_in_state(state, plane, old_plane_state, i) {
2409 struct drm_plane_state *plane_state = plane->state;
2410 struct drm_crtc *crtc = plane_state->crtc;
4562236b
HW		 2411 struct drm_framebuffer *fb = plane_state->fb;
2412 struct drm_connector *connector;
2413 struct dm_connector_state *dm_state = NULL;
2414 enum dm_commit_action action;
54f5499a 2415 bool pflip_needed;
4562236b
HW		 2416
2417 if (!fb || !crtc || !crtc->state->active)
2418 continue;
2419
2420 action = get_dm_commit_action(crtc->state);
2421
2422 /* Surfaces are created under two scenarios:
2423 * 1. This commit is not a page flip.
ab2541b6 2424 * 2. This commit is a page flip, and streams are created.
4562236b 2425 */
2d60ded1 2426 pflip_needed = !state->allow_modeset;
54f5499a
AG		 2427 if (!pflip_needed ||
2428 action == DM_COMMIT_ACTION_DPMS_ON ||
2429 action == DM_COMMIT_ACTION_SET) {
4562236b
HW		 2430 list_for_each_entry(connector,
2431 &dev->mode_config.connector_list, head) {
2432 if (connector->state->crtc == crtc) {
2433 dm_state = to_dm_connector_state(
2434 connector->state);
2435 break;
2436 }
2437 }
2438
2439 /*
2440 * This situation happens in the following case:
2441 * we are about to get set mode for connector who's only
2442 * possible crtc (in encoder crtc mask) is used by
2443 * another connector, that is why it will try to
2444 * re-assing crtcs in order to make configuration
2445 * supported. For our implementation we need to make all
2446 * encoders support all crtcs, then this issue will
2447 * never arise again. But to guard code from this issue
2448 * check is left.
2449 *
2450 * Also it should be needed when used with actual
2451 * drm_atomic_commit ioctl in future
2452 */
2453 if (!dm_state)
2454 continue;
2455
4562236b
HW		 2456 dm_dc_surface_commit(dm->dc, crtc);
2457 }
2458 }
2459
2460 for (i = 0; i < new_crtcs_count; i++) {
2461 /*
2462 * loop to enable interrupts on newly arrived crtc
2463 */
2464 struct amdgpu_crtc *acrtc = new_crtcs[i];
2465
ab2541b6
AC		 2466 if (adev->dm.freesync_module)
2467 mod_freesync_notify_mode_change(
2468 adev->dm.freesync_module, &acrtc->stream, 1);
4562236b
HW		 2469
2470 manage_dm_interrupts(adev, acrtc, true);
2471 dm_crtc_cursor_reset(&acrtc->base);
2472
2473 }
2474
4562236b
HW		 2475 for_each_plane_in_state(state, plane, old_plane_state, i) {
2476 struct drm_plane_state *plane_state = plane->state;
2477 struct drm_crtc *crtc = plane_state->crtc;
2478 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
2479 struct drm_framebuffer *fb = plane_state->fb;
54f5499a 2480 bool pflip_needed;
4562236b
HW		 2481
2482 if (!fb || !crtc || !crtc->state->planes_changed ||
2483 !crtc->state->active)
2484 continue;
2d60ded1 2485 pflip_needed = !state->allow_modeset;
54f5499a
AG		 2486
2487 if (pflip_needed) {
2488 amdgpu_dm_do_flip(
2489 crtc,
2490 fb,
2491 drm_crtc_vblank_count(crtc));
2492
2493 wait_for_vblank =
2494 acrtc->flip_flags & DRM_MODE_PAGE_FLIP_ASYNC ?
2495 false : true;
4562236b
HW		 2496 /*clean up the flags for next usage*/
2497 acrtc->flip_flags = 0;
2498 }
2499 }
2500
4562236b 2501
54f5499a
AG		 2502 /*TODO mark consumed event on all crtc assigned event
2503 * in drm_atomic_helper_setup_commit just to signal completion
2504 */
2505 spin_lock_irqsave(&adev->ddev->event_lock, flags);
2506 for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
2507 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
2508
2509 if (acrtc->base.state->event &&
2510 acrtc->base.state->event->event.base.type != DRM_EVENT_FLIP_COMPLETE) {
2511 acrtc->event = acrtc->base.state->event;
2512 acrtc->base.state->event = NULL;
2513 }
2514 }
2515 spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
2516
2517 /* Signal HW programming completion */
2518 drm_atomic_helper_commit_hw_done(state);
2519
2520 if (wait_for_vblank)
2521 drm_atomic_helper_wait_for_vblanks(dev, state);
2522
2523 /*TODO send vblank event on all crtc assigned event
2524 * in drm_atomic_helper_setup_commit just to signal completion
2525 */
2526 spin_lock_irqsave(&adev->ddev->event_lock, flags);
2527 for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
2528 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
4562236b 2529
54f5499a
AG		 2530 if (acrtc->event &&
2531 acrtc->event->event.base.type != DRM_EVENT_FLIP_COMPLETE) {
2532 drm_send_event_locked(dev, &acrtc->event->base);
2533 acrtc->event = NULL;
2534 }
2535 }
2536 spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
4562236b 2537
54f5499a
AG		 2538 /*TODO Is it to early if actual flip haven't happened yet ?*/
2539 /* Release old FB */
2540 drm_atomic_helper_cleanup_planes(dev, state);
4562236b 2541}
92cc37fb
AG		 2542
2543
2544static int dm_force_atomic_commit(struct drm_connector *connector)
2545{
2546 int ret = 0;
2547 struct drm_device *ddev = connector->dev;
2548 struct drm_atomic_state *state = drm_atomic_state_alloc(ddev);
2549 struct amdgpu_crtc *disconnected_acrtc = to_amdgpu_crtc(connector->encoder->crtc);
2550 struct drm_plane *plane = disconnected_acrtc->base.primary;
2551 struct drm_connector_state *conn_state;
2552 struct drm_crtc_state *crtc_state;
2553 struct drm_plane_state *plane_state;
2554
2555 if (!state)
2556 return -ENOMEM;
2557
2558 state->acquire_ctx = ddev->mode_config.acquire_ctx;
2559
2560 /* Construct an atomic state to restore previous display setting */
2561
2562 /*
2563 * Attach connectors to drm_atomic_state
2564 */
2565 conn_state = drm_atomic_get_connector_state(state, connector);
2566
2567 ret = PTR_ERR_OR_ZERO(conn_state);
2568 if (ret)
2569 goto err;
2570
2571 /* Attach crtc to drm_atomic_state*/
2572 crtc_state = drm_atomic_get_crtc_state(state, &disconnected_acrtc->base);
2573
2574 ret = PTR_ERR_OR_ZERO(crtc_state);
2575 if (ret)
2576 goto err;
2577
2578 /* force a restore */
2579 crtc_state->mode_changed = true;
2580
2581 /* Attach plane to drm_atomic_state */
2582 plane_state = drm_atomic_get_plane_state(state, plane);
2583
2584 ret = PTR_ERR_OR_ZERO(plane_state);
2585 if (ret)
2586 goto err;
2587
2588
2589 /* Call commit internally with the state we just constructed */
2590 ret = drm_atomic_commit(state);
2591 if (!ret)
2592 return 0;
2593
2594err:
2595 DRM_ERROR("Restoring old state failed with %i\n", ret);
2596 drm_atomic_state_put(state);
2597
2598 return ret;
2599}
2600
4562236b
HW		 2601/*
2602 * This functions handle all cases when set mode does not come upon hotplug.
2603 * This include when the same display is unplugged then plugged back into the
2604 * same port and when we are running without usermode desktop manager supprot
2605 */
2606void dm_restore_drm_connector_state(struct drm_device *dev, struct drm_connector *connector)
2607{
4562236b
HW		 2608 struct amdgpu_connector *aconnector = to_amdgpu_connector(connector);
2609 struct amdgpu_crtc *disconnected_acrtc;
4562236b
HW		 2610
2611 if (!aconnector->dc_sink || !connector->state || !connector->encoder)
2612 return;
2613
2614 disconnected_acrtc = to_amdgpu_crtc(connector->encoder->crtc);
2615
ab2541b6 2616 if (!disconnected_acrtc || !disconnected_acrtc->stream)
4562236b
HW		 2617 return;
2618
4562236b
HW		 2619 /*
2620 * If the previous sink is not released and different from the current,
2621 * we deduce we are in a state where we can not rely on usermode call
2622 * to turn on the display, so we do it here
2623 */
92cc37fb
AG		 2624 if (disconnected_acrtc->stream->sink != aconnector->dc_sink)
2625 dm_force_atomic_commit(&aconnector->base);
4562236b
HW		 2626}
2627
2628static uint32_t add_val_sets_surface(
2629 struct dc_validation_set *val_sets,
2630 uint32_t set_count,
ab2541b6 2631 const struct dc_stream *stream,
4562236b
HW		 2632 const struct dc_surface *surface)
2633{
2634 uint32_t i = 0;
2635
2636 while (i < set_count) {
ab2541b6 2637 if (val_sets[i].stream == stream)
4562236b
HW		 2638 break;
2639 ++i;
2640 }
2641
2642 val_sets[i].surfaces[val_sets[i].surface_count] = surface;
2643 val_sets[i].surface_count++;
2644
2645 return val_sets[i].surface_count;
2646}
2647
ab2541b6 2648static uint32_t update_in_val_sets_stream(
4562236b
HW		 2649 struct dc_validation_set *val_sets,
2650 struct drm_crtc **crtcs,
2651 uint32_t set_count,
ab2541b6
AC		 2652 const struct dc_stream *old_stream,
2653 const struct dc_stream *new_stream,
4562236b
HW		 2654 struct drm_crtc *crtc)
2655{
2656 uint32_t i = 0;
2657
2658 while (i < set_count) {
ab2541b6 2659 if (val_sets[i].stream == old_stream)
4562236b
HW		 2660 break;
2661 ++i;
2662 }
2663
ab2541b6 2664 val_sets[i].stream = new_stream;
4562236b
HW		 2665 crtcs[i] = crtc;
2666
2667 if (i == set_count) {
2668 /* nothing found. add new one to the end */
2669 return set_count + 1;
2670 }
2671
2672 return set_count;
2673}
2674
2675static uint32_t remove_from_val_sets(
2676 struct dc_validation_set *val_sets,
2677 uint32_t set_count,
ab2541b6 2678 const struct dc_stream *stream)
4562236b
HW		 2679{
2680 int i;
2681
2682 for (i = 0; i < set_count; i++)
ab2541b6 2683 if (val_sets[i].stream == stream)
4562236b
HW		 2684 break;
2685
2686 if (i == set_count) {
2687 /* nothing found */
2688 return set_count;
2689 }
2690
2691 set_count--;
2692
2693 for (; i < set_count; i++) {
2694 val_sets[i] = val_sets[i + 1];
2695 }
2696
2697 return set_count;
2698}
2699
2700int amdgpu_dm_atomic_check(struct drm_device *dev,
2701 struct drm_atomic_state *state)
2702{
2703 struct drm_crtc *crtc;
2704 struct drm_crtc_state *crtc_state;
2705 struct drm_plane *plane;
2706 struct drm_plane_state *plane_state;
2707 int i, j;
2708 int ret;
2709 int set_count;
ab2541b6
AC		 2710 int new_stream_count;
2711 struct dc_validation_set set[MAX_STREAMS] = {{ 0 }};
2712 struct dc_stream *new_streams[MAX_STREAMS] = { 0 };
2713 struct drm_crtc *crtc_set[MAX_STREAMS] = { 0 };
4562236b
HW		 2714 struct amdgpu_device *adev = dev->dev_private;
2715 struct dc *dc = adev->dm.dc;
2716 bool need_to_validate = false;
2717
2718 ret = drm_atomic_helper_check(dev, state);
2719
2720 if (ret) {
2721 DRM_ERROR("Atomic state validation failed with error :%d !\n",
2722 ret);
2723 return ret;
2724 }
2725
2726 ret = -EINVAL;
2727
2728 /* copy existing configuration */
ab2541b6 2729 new_stream_count = 0;
4562236b
HW		 2730 set_count = 0;
2731 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2732
2733 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
2734
ab2541b6
AC		 2735 if (acrtc->stream) {
2736 set[set_count].stream = acrtc->stream;
4562236b
HW		 2737 crtc_set[set_count] = crtc;
2738 ++set_count;
2739 }
2740 }
2741
2742 /* update changed items */
2743 for_each_crtc_in_state(state, crtc, crtc_state, i) {
2744 struct amdgpu_crtc *acrtc = NULL;
2745 struct amdgpu_connector *aconnector = NULL;
2746 enum dm_commit_action action;
2747
2748 acrtc = to_amdgpu_crtc(crtc);
2749
2750 aconnector = amdgpu_dm_find_first_crct_matching_connector(state, crtc, true);
2751
2752 action = get_dm_commit_action(crtc_state);
2753
2754 switch (action) {
2755 case DM_COMMIT_ACTION_DPMS_ON:
2756 case DM_COMMIT_ACTION_SET: {
ab2541b6 2757 struct dc_stream *new_stream = NULL;
4562236b
HW		 2758 struct drm_connector_state *conn_state = NULL;
2759 struct dm_connector_state *dm_state = NULL;
2760
2761 if (aconnector) {
2762 conn_state = drm_atomic_get_connector_state(state, &aconnector->base);
2763 if (IS_ERR(conn_state))
2764 return ret;
2765 dm_state = to_dm_connector_state(conn_state);
2766 }
2767
ab2541b6 2768 new_stream = create_stream_for_sink(aconnector, &crtc_state->mode, dm_state);
4562236b
HW		 2769
2770 /*
ab2541b6 2771 * we can have no stream on ACTION_SET if a display
4562236b
HW		 2772 * was disconnected during S3, in this case it not and
2773 * error, the OS will be updated after detection, and
2774 * do the right thing on next atomic commit
2775 */
ab2541b6
AC		 2776 if (!new_stream) {
2777 DRM_DEBUG_KMS("%s: Failed to create new stream for crtc %d\n",
4562236b
HW		 2778 __func__, acrtc->base.base.id);
2779 break;
2780 }
2781
ab2541b6
AC		 2782 new_streams[new_stream_count] = new_stream;
2783 set_count = update_in_val_sets_stream(
4562236b
HW		 2784 set,
2785 crtc_set,
2786 set_count,
ab2541b6
AC		 2787 acrtc->stream,
2788 new_stream,
4562236b
HW		 2789 crtc);
2790
ab2541b6 2791 new_stream_count++;
4562236b
HW		 2792 need_to_validate = true;
2793 break;
2794 }
2795
2796 case DM_COMMIT_ACTION_NOTHING: {
2797 const struct drm_connector *drm_connector = NULL;
2798 struct drm_connector_state *conn_state = NULL;
2799 struct dm_connector_state *dm_state = NULL;
2800 struct dm_connector_state *old_dm_state = NULL;
ab2541b6 2801 struct dc_stream *new_stream;
4562236b
HW		 2802
2803 if (!aconnector)
2804 break;
2805
2806 for_each_connector_in_state(
2807 state, drm_connector, conn_state, j) {
2808 if (&aconnector->base == drm_connector)
2809 break;
2810 }
2811
2812 old_dm_state = to_dm_connector_state(drm_connector->state);
2813 dm_state = to_dm_connector_state(conn_state);
2814
2815 /* Support underscan adjustment*/
2816 if (!is_scaling_state_different(dm_state, old_dm_state))
2817 break;
2818
ab2541b6 2819 new_stream = create_stream_for_sink(aconnector, &crtc_state->mode, dm_state);
4562236b 2820
ab2541b6
AC		 2821 if (!new_stream) {
2822 DRM_ERROR("%s: Failed to create new stream for crtc %d\n",
4562236b
HW		 2823 __func__, acrtc->base.base.id);
2824 break;
2825 }
2826
ab2541b6
AC		 2827 new_streams[new_stream_count] = new_stream;
2828 set_count = update_in_val_sets_stream(
4562236b
HW		 2829 set,
2830 crtc_set,
2831 set_count,
ab2541b6
AC		 2832 acrtc->stream,
2833 new_stream,
4562236b
HW		 2834 crtc);
2835
ab2541b6 2836 new_stream_count++;
4562236b
HW		 2837 need_to_validate = true;
2838
2839 break;
2840 }
2841 case DM_COMMIT_ACTION_DPMS_OFF:
2842 case DM_COMMIT_ACTION_RESET:
2843 /* i.e. reset mode */
ab2541b6 2844 if (acrtc->stream) {
4562236b
HW		 2845 set_count = remove_from_val_sets(
2846 set,
2847 set_count,
ab2541b6 2848 acrtc->stream);
4562236b
HW		 2849 }
2850 break;
2851 }
2852
2853 /*
2854 * TODO revisit when removing commit action
2855 * and looking at atomic flags directly
2856 */
2857
2858 /* commit needs planes right now (for gamma, eg.) */
2859 /* TODO rework commit to chack crtc for gamma change */
2860 ret = drm_atomic_add_affected_planes(state, crtc);
2861 if (ret)
2862 return ret;
53d35dc6
AG		 2863
2864 ret = -EINVAL;
4562236b
HW		 2865 }
2866
2867 for (i = 0; i < set_count; i++) {
2868 for_each_plane_in_state(state, plane, plane_state, j) {
4562236b
HW		 2869 struct drm_crtc *crtc = plane_state->crtc;
2870 struct drm_framebuffer *fb = plane_state->fb;
2871 struct drm_connector *connector;
2872 struct dm_connector_state *dm_state = NULL;
2873 enum dm_commit_action action;
2874 struct drm_crtc_state *crtc_state;
54f5499a 2875 bool pflip_needed;
4562236b
HW		 2876
2877
2878 if (!fb || !crtc || crtc_set[i] != crtc ||
2879 !crtc->state->planes_changed || !crtc->state->active)
2880 continue;
2881
2882 action = get_dm_commit_action(crtc->state);
2883
2884 /* Surfaces are created under two scenarios:
2885 * 1. This commit is not a page flip.
ab2541b6 2886 * 2. This commit is a page flip, and streams are created.
4562236b
HW		 2887 */
2888 crtc_state = drm_atomic_get_crtc_state(state, crtc);
2d60ded1 2889 pflip_needed = !state->allow_modeset;
54f5499a
AG		 2890 if (!pflip_needed ||
2891 action == DM_COMMIT_ACTION_DPMS_ON ||
2892 action == DM_COMMIT_ACTION_SET) {
4562236b
HW		 2893 struct dc_surface *surface;
2894
2895 list_for_each_entry(connector,
2896 &dev->mode_config.connector_list, head) {
2897 if (connector->state->crtc == crtc) {
2898 dm_state = to_dm_connector_state(
2899 connector->state);
2900 break;
2901 }
2902 }
2903
2904 /*
2905 * This situation happens in the following case:
2906 * we are about to get set mode for connector who's only
2907 * possible crtc (in encoder crtc mask) is used by
2908 * another connector, that is why it will try to
2909 * re-assing crtcs in order to make configuration
2910 * supported. For our implementation we need to make all
2911 * encoders support all crtcs, then this issue will
2912 * never arise again. But to guard code from this issue
2913 * check is left.
2914 *
2915 * Also it should be needed when used with actual
2916 * drm_atomic_commit ioctl in future
2917 */
2918 if (!dm_state)
2919 continue;
2920
2921 surface = dc_create_surface(dc);
2922 fill_plane_attributes(
6a1f8cab 2923 crtc->dev->dev_private,
4562236b
HW		 2924 surface,
2925 plane_state,
2926 false);
2927
2928 add_val_sets_surface(
2929 set,
2930 set_count,
ab2541b6 2931 set[i].stream,
4562236b
HW		 2932 surface);
2933
2934 need_to_validate = true;
2935 }
2936 }
2937 }
2938
2939 if (need_to_validate == false || set_count == 0 ||
2940 dc_validate_resources(dc, set, set_count))
2941 ret = 0;
2942
2943 for (i = 0; i < set_count; i++) {
2944 for (j = 0; j < set[i].surface_count; j++) {
2945 dc_surface_release(set[i].surfaces[j]);
2946 }
2947 }
ab2541b6
AC		 2948 for (i = 0; i < new_stream_count; i++)
2949 dc_stream_release(new_streams[i]);
4562236b
HW		 2950
2951 if (ret != 0)
2952 DRM_ERROR("Atomic check failed.\n");
2953
2954 return ret;
2955}
2956
2957static bool is_dp_capable_without_timing_msa(
2958 struct dc *dc,
2959 struct amdgpu_connector *amdgpu_connector)
2960{
2961 uint8_t dpcd_data;
2962 bool capable = false;
2963 if (amdgpu_connector->dc_link &&
2964 dc_read_dpcd(dc, amdgpu_connector->dc_link->link_index,
2965 DP_DOWN_STREAM_PORT_COUNT,
2966 &dpcd_data, sizeof(dpcd_data)) )
d7194cf6 2967 capable = (dpcd_data & DP_MSA_TIMING_PAR_IGNORED) ? true:false;
4562236b
HW		 2968
2969 return capable;
2970}
2971void amdgpu_dm_add_sink_to_freesync_module(
2972 struct drm_connector *connector,
2973 struct edid *edid)
2974{
2975 int i;
2976 uint64_t val_capable;
2977 bool edid_check_required;
2978 struct detailed_timing *timing;
2979 struct detailed_non_pixel *data;
2980 struct detailed_data_monitor_range *range;
2981 struct amdgpu_connector *amdgpu_connector =
2982 to_amdgpu_connector(connector);
2983
2984 struct drm_device *dev = connector->dev;
2985 struct amdgpu_device *adev = dev->dev_private;
2986 edid_check_required = false;
2987 if (!amdgpu_connector->dc_sink) {
2988 DRM_ERROR("dc_sink NULL, could not add free_sync module.\n");
2989 return;
2990 }
2991 if (!adev->dm.freesync_module)
2992 return;
2993 /*
2994 * if edid non zero restrict freesync only for dp and edp
2995 */
2996 if (edid) {
2997 if (amdgpu_connector->dc_sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT
2998 || amdgpu_connector->dc_sink->sink_signal == SIGNAL_TYPE_EDP) {
2999 edid_check_required = is_dp_capable_without_timing_msa(
3000 adev->dm.dc,
3001 amdgpu_connector);
3002 }
3003 }
3004 val_capable = 0;
3005 if (edid_check_required == true && (edid->version > 1 ||
3006 (edid->version == 1 && edid->revision > 1))) {
3007 for (i = 0; i < 4; i++) {
3008
3009 timing = &edid->detailed_timings[i];
3010 data = &timing->data.other_data;
3011 range = &data->data.range;
3012 /*
3013 * Check if monitor has continuous frequency mode
3014 */
3015 if (data->type != EDID_DETAIL_MONITOR_RANGE)
3016 continue;
3017 /*
3018 * Check for flag range limits only. If flag == 1 then
3019 * no additional timing information provided.
3020 * Default GTF, GTF Secondary curve and CVT are not
3021 * supported
3022 */
3023 if (range->flags != 1)
3024 continue;
3025
3026 amdgpu_connector->min_vfreq = range->min_vfreq;
3027 amdgpu_connector->max_vfreq = range->max_vfreq;
3028 amdgpu_connector->pixel_clock_mhz =
3029 range->pixel_clock_mhz * 10;
3030 break;
3031 }
3032
3033 if (amdgpu_connector->max_vfreq -
3034 amdgpu_connector->min_vfreq > 10) {
3035 amdgpu_connector->caps.supported = true;
3036 amdgpu_connector->caps.min_refresh_in_micro_hz =
3037 amdgpu_connector->min_vfreq * 1000000;
3038 amdgpu_connector->caps.max_refresh_in_micro_hz =
3039 amdgpu_connector->max_vfreq * 1000000;
3040 val_capable = 1;
3041 }
3042 }
3043
3044 /*
3045 * TODO figure out how to notify user-mode or DRM of freesync caps
3046 * once we figure out how to deal with freesync in an upstreamable
3047 * fashion
3048 */
3049
3050}
3051
3052void amdgpu_dm_remove_sink_from_freesync_module(
3053 struct drm_connector *connector)
3054{
3055 /*
3056 * TODO fill in once we figure out how to deal with freesync in
3057 * an upstreamable fashion
3058 */
3059}
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