]> git.proxmox.com Git - mirror_ubuntu-bionic-kernel.git/blame - drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
projects / mirror_ubuntu-bionic-kernel.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
drm/amd/display: Rename dc_stream to dc_stream_state
[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / amd / display / dc / core / dc_link_dp.c
CommitLineData
4562236b
HW		 1/* Copyright 2015 Advanced Micro Devices, Inc. */
2#include "dm_services.h"
3#include "dc.h"
4#include "dc_link_dp.h"
5#include "dm_helpers.h"
6
7#include "inc/core_types.h"
8#include "link_hwss.h"
9#include "dc_link_ddc.h"
10#include "core_status.h"
11#include "dpcd_defs.h"
12
13#include "core_dc.h"
529cad0f 14#include "resource.h"
4562236b
HW		 15
16/* maximum pre emphasis level allowed for each voltage swing level*/
17static const enum dc_pre_emphasis voltage_swing_to_pre_emphasis[] = {
18 PRE_EMPHASIS_LEVEL3,
19 PRE_EMPHASIS_LEVEL2,
20 PRE_EMPHASIS_LEVEL1,
21 PRE_EMPHASIS_DISABLED };
22
23enum {
24 POST_LT_ADJ_REQ_LIMIT = 6,
25 POST_LT_ADJ_REQ_TIMEOUT = 200
26};
27
28enum {
29 LINK_TRAINING_MAX_RETRY_COUNT = 5,
30 /* to avoid infinite loop where-in the receiver
31 * switches between different VS
32 */
33 LINK_TRAINING_MAX_CR_RETRY = 100
34};
35
4562236b 36static void wait_for_training_aux_rd_interval(
d0778ebf 37 struct dc_link *link,
4562236b
HW		 38 uint32_t default_wait_in_micro_secs)
39{
40 union training_aux_rd_interval training_rd_interval;
41
42 /* overwrite the delay if rev > 1.1*/
43 if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_12) {
44 /* DP 1.2 or later - retrieve delay through
45 * "DPCD_ADDR_TRAINING_AUX_RD_INTERVAL" register */
46 core_link_read_dpcd(
47 link,
3a340294 48 DP_TRAINING_AUX_RD_INTERVAL,
4562236b
HW		 49 (uint8_t *)&training_rd_interval,
50 sizeof(training_rd_interval));
51
52 if (training_rd_interval.bits.TRAINIG_AUX_RD_INTERVAL)
53 default_wait_in_micro_secs =
54 training_rd_interval.bits.TRAINIG_AUX_RD_INTERVAL * 4000;
55 }
56
57 udelay(default_wait_in_micro_secs);
58
59 dm_logger_write(link->ctx->logger, LOG_HW_LINK_TRAINING,
60 "%s:\n wait = %d\n",
61 __func__,
62 default_wait_in_micro_secs);
63}
64
65static void dpcd_set_training_pattern(
d0778ebf 66 struct dc_link *link,
4562236b
HW		 67 union dpcd_training_pattern dpcd_pattern)
68{
69 core_link_write_dpcd(
70 link,
3a340294 71 DP_TRAINING_PATTERN_SET,
4562236b
HW		 72 &dpcd_pattern.raw,
73 1);
74
75 dm_logger_write(link->ctx->logger, LOG_HW_LINK_TRAINING,
76 "%s\n %x pattern = %x\n",
77 __func__,
3a340294 78 DP_TRAINING_PATTERN_SET,
4562236b
HW		 79 dpcd_pattern.v1_4.TRAINING_PATTERN_SET);
80}
81
82static void dpcd_set_link_settings(
d0778ebf 83 struct dc_link *link,
4562236b
HW		 84 const struct link_training_settings *lt_settings)
85{
86 uint8_t rate = (uint8_t)
87 (lt_settings->link_settings.link_rate);
88
89 union down_spread_ctrl downspread = {{0}};
90 union lane_count_set lane_count_set = {{0}};
91 uint8_t link_set_buffer[2];
92
93 downspread.raw = (uint8_t)
94 (lt_settings->link_settings.link_spread);
95
96 lane_count_set.bits.LANE_COUNT_SET =
97 lt_settings->link_settings.lane_count;
98
99 lane_count_set.bits.ENHANCED_FRAMING = 1;
100
101 lane_count_set.bits.POST_LT_ADJ_REQ_GRANTED =
102 link->dpcd_caps.max_ln_count.bits.POST_LT_ADJ_REQ_SUPPORTED;
103
104 link_set_buffer[0] = rate;
105 link_set_buffer[1] = lane_count_set.raw;
106
3a340294 107 core_link_write_dpcd(link, DP_LINK_BW_SET,
4562236b 108 link_set_buffer, 2);
3a340294 109 core_link_write_dpcd(link, DP_DOWNSPREAD_CTRL,
4562236b
HW		 110 &downspread.raw, sizeof(downspread));
111
112 dm_logger_write(link->ctx->logger, LOG_HW_LINK_TRAINING,
113 "%s\n %x rate = %x\n %x lane = %x\n %x spread = %x\n",
114 __func__,
3a340294 115 DP_LINK_BW_SET,
4562236b 116 lt_settings->link_settings.link_rate,
3a340294 117 DP_LANE_COUNT_SET,
4562236b 118 lt_settings->link_settings.lane_count,
3a340294 119 DP_DOWNSPREAD_CTRL,
4562236b
HW		 120 lt_settings->link_settings.link_spread);
121
122}
123
124static enum dpcd_training_patterns
125 hw_training_pattern_to_dpcd_training_pattern(
d0778ebf 126 struct dc_link *link,
4562236b
HW		 127 enum hw_dp_training_pattern pattern)
128{
129 enum dpcd_training_patterns dpcd_tr_pattern =
130 DPCD_TRAINING_PATTERN_VIDEOIDLE;
131
132 switch (pattern) {
133 case HW_DP_TRAINING_PATTERN_1:
134 dpcd_tr_pattern = DPCD_TRAINING_PATTERN_1;
135 break;
136 case HW_DP_TRAINING_PATTERN_2:
137 dpcd_tr_pattern = DPCD_TRAINING_PATTERN_2;
138 break;
139 case HW_DP_TRAINING_PATTERN_3:
140 dpcd_tr_pattern = DPCD_TRAINING_PATTERN_3;
141 break;
142 case HW_DP_TRAINING_PATTERN_4:
143 dpcd_tr_pattern = DPCD_TRAINING_PATTERN_4;
144 break;
145 default:
146 ASSERT(0);
147 dm_logger_write(link->ctx->logger, LOG_HW_LINK_TRAINING,
148 "%s: Invalid HW Training pattern: %d\n",
149 __func__, pattern);
150 break;
151 }
152
153 return dpcd_tr_pattern;
154
155}
156
157static void dpcd_set_lt_pattern_and_lane_settings(
d0778ebf 158 struct dc_link *link,
4562236b
HW		 159 const struct link_training_settings *lt_settings,
160 enum hw_dp_training_pattern pattern)
161{
162 union dpcd_training_lane dpcd_lane[LANE_COUNT_DP_MAX] = {{{0}}};
163 const uint32_t dpcd_base_lt_offset =
3a340294 164 DP_TRAINING_PATTERN_SET;
4562236b
HW		 165 uint8_t dpcd_lt_buffer[5] = {0};
166 union dpcd_training_pattern dpcd_pattern = {{0}};
167 uint32_t lane;
168 uint32_t size_in_bytes;
169 bool edp_workaround = false; /* TODO link_prop.INTERNAL */
170
171 /*****************************************************************
172 * DpcdAddress_TrainingPatternSet
173 *****************************************************************/
174 dpcd_pattern.v1_4.TRAINING_PATTERN_SET =
175 hw_training_pattern_to_dpcd_training_pattern(link, pattern);
176
3a340294 177 dpcd_lt_buffer[DP_TRAINING_PATTERN_SET - dpcd_base_lt_offset]
4562236b
HW		 178 = dpcd_pattern.raw;
179
180 dm_logger_write(link->ctx->logger, LOG_HW_LINK_TRAINING,
181 "%s\n %x pattern = %x\n",
182 __func__,
3a340294 183 DP_TRAINING_PATTERN_SET,
4562236b
HW		 184 dpcd_pattern.v1_4.TRAINING_PATTERN_SET);
185
186 /*****************************************************************
187 * DpcdAddress_Lane0Set -> DpcdAddress_Lane3Set
188 *****************************************************************/
189 for (lane = 0; lane <
190 (uint32_t)(lt_settings->link_settings.lane_count); lane++) {
191
192 dpcd_lane[lane].bits.VOLTAGE_SWING_SET =
193 (uint8_t)(lt_settings->lane_settings[lane].VOLTAGE_SWING);
194 dpcd_lane[lane].bits.PRE_EMPHASIS_SET =
195 (uint8_t)(lt_settings->lane_settings[lane].PRE_EMPHASIS);
196
197 dpcd_lane[lane].bits.MAX_SWING_REACHED =
198 (lt_settings->lane_settings[lane].VOLTAGE_SWING ==
199 VOLTAGE_SWING_MAX_LEVEL ? 1 : 0);
200 dpcd_lane[lane].bits.MAX_PRE_EMPHASIS_REACHED =
201 (lt_settings->lane_settings[lane].PRE_EMPHASIS ==
202 PRE_EMPHASIS_MAX_LEVEL ? 1 : 0);
203 }
204
205 /* concatinate everything into one buffer*/
206
207 size_in_bytes = lt_settings->link_settings.lane_count * sizeof(dpcd_lane[0]);
208
209 // 0x00103 - 0x00102
210 memmove(
3a340294 211 &dpcd_lt_buffer[DP_TRAINING_LANE0_SET - dpcd_base_lt_offset],
4562236b
HW		 212 dpcd_lane,
213 size_in_bytes);
214
215 dm_logger_write(link->ctx->logger, LOG_HW_LINK_TRAINING,
216 "%s:\n %x VS set = %x PE set = %x \
217 max VS Reached = %x max PE Reached = %x\n",
218 __func__,
3a340294 219 DP_TRAINING_LANE0_SET,
4562236b
HW		 220 dpcd_lane[0].bits.VOLTAGE_SWING_SET,
221 dpcd_lane[0].bits.PRE_EMPHASIS_SET,
222 dpcd_lane[0].bits.MAX_SWING_REACHED,
223 dpcd_lane[0].bits.MAX_PRE_EMPHASIS_REACHED);
224
225 if (edp_workaround) {
226 /* for eDP write in 2 parts because the 5-byte burst is
227 * causing issues on some eDP panels (EPR#366724)
228 */
229 core_link_write_dpcd(
230 link,
3a340294 231 DP_TRAINING_PATTERN_SET,
4562236b
HW		 232 &dpcd_pattern.raw,
233 sizeof(dpcd_pattern.raw) );
234
235 core_link_write_dpcd(
236 link,
3a340294 237 DP_TRAINING_LANE0_SET,
4562236b
HW		 238 (uint8_t *)(dpcd_lane),
239 size_in_bytes);
240
241 } else
242 /* write it all in (1 + number-of-lanes)-byte burst*/
243 core_link_write_dpcd(
244 link,
245 dpcd_base_lt_offset,
246 dpcd_lt_buffer,
247 size_in_bytes + sizeof(dpcd_pattern.raw) );
248
d0778ebf 249 link->cur_lane_setting = lt_settings->lane_settings[0];
4562236b
HW		 250}
251
252static bool is_cr_done(enum dc_lane_count ln_count,
253 union lane_status *dpcd_lane_status)
254{
255 bool done = true;
256 uint32_t lane;
257 /*LANEx_CR_DONE bits All 1's?*/
258 for (lane = 0; lane < (uint32_t)(ln_count); lane++) {
259 if (!dpcd_lane_status[lane].bits.CR_DONE_0)
260 done = false;
261 }
262 return done;
263
264}
265
266static bool is_ch_eq_done(enum dc_lane_count ln_count,
267 union lane_status *dpcd_lane_status,
268 union lane_align_status_updated *lane_status_updated)
269{
270 bool done = true;
271 uint32_t lane;
272 if (!lane_status_updated->bits.INTERLANE_ALIGN_DONE)
273 done = false;
274 else {
275 for (lane = 0; lane < (uint32_t)(ln_count); lane++) {
276 if (!dpcd_lane_status[lane].bits.SYMBOL_LOCKED_0 ||
277 !dpcd_lane_status[lane].bits.CHANNEL_EQ_DONE_0)
278 done = false;
279 }
280 }
281 return done;
282
283}
284
285static void update_drive_settings(
286 struct link_training_settings *dest,
287 struct link_training_settings src)
288{
289 uint32_t lane;
290 for (lane = 0; lane < src.link_settings.lane_count; lane++) {
291 dest->lane_settings[lane].VOLTAGE_SWING =
292 src.lane_settings[lane].VOLTAGE_SWING;
293 dest->lane_settings[lane].PRE_EMPHASIS =
294 src.lane_settings[lane].PRE_EMPHASIS;
295 dest->lane_settings[lane].POST_CURSOR2 =
296 src.lane_settings[lane].POST_CURSOR2;
297 }
298}
299
300static uint8_t get_nibble_at_index(const uint8_t *buf,
301 uint32_t index)
302{
303 uint8_t nibble;
304 nibble = buf[index / 2];
305
306 if (index % 2)
307 nibble >>= 4;
308 else
309 nibble &= 0x0F;
310
311 return nibble;
312}
313
314static enum dc_pre_emphasis get_max_pre_emphasis_for_voltage_swing(
315 enum dc_voltage_swing voltage)
316{
317 enum dc_pre_emphasis pre_emphasis;
318 pre_emphasis = PRE_EMPHASIS_MAX_LEVEL;
319
320 if (voltage <= VOLTAGE_SWING_MAX_LEVEL)
321 pre_emphasis = voltage_swing_to_pre_emphasis[voltage];
322
323 return pre_emphasis;
324
325}
326
327static void find_max_drive_settings(
328 const struct link_training_settings *link_training_setting,
329 struct link_training_settings *max_lt_setting)
330{
331 uint32_t lane;
332 struct dc_lane_settings max_requested;
333
334 max_requested.VOLTAGE_SWING =
335 link_training_setting->
336 lane_settings[0].VOLTAGE_SWING;
337 max_requested.PRE_EMPHASIS =
338 link_training_setting->
339 lane_settings[0].PRE_EMPHASIS;
340 /*max_requested.postCursor2 =
341 * link_training_setting->laneSettings[0].postCursor2;*/
342
343 /* Determine what the maximum of the requested settings are*/
344 for (lane = 1; lane < link_training_setting->link_settings.lane_count;
345 lane++) {
346 if (link_training_setting->lane_settings[lane].VOLTAGE_SWING >
347 max_requested.VOLTAGE_SWING)
348
349 max_requested.VOLTAGE_SWING =
350 link_training_setting->
351 lane_settings[lane].VOLTAGE_SWING;
352
353 if (link_training_setting->lane_settings[lane].PRE_EMPHASIS >
354 max_requested.PRE_EMPHASIS)
355 max_requested.PRE_EMPHASIS =
356 link_training_setting->
357 lane_settings[lane].PRE_EMPHASIS;
358
359 /*
360 if (link_training_setting->laneSettings[lane].postCursor2 >
361 max_requested.postCursor2)
362 {
363 max_requested.postCursor2 =
364 link_training_setting->laneSettings[lane].postCursor2;
365 }
366 */
367 }
368
369 /* make sure the requested settings are
370 * not higher than maximum settings*/
371 if (max_requested.VOLTAGE_SWING > VOLTAGE_SWING_MAX_LEVEL)
372 max_requested.VOLTAGE_SWING = VOLTAGE_SWING_MAX_LEVEL;
373
374 if (max_requested.PRE_EMPHASIS > PRE_EMPHASIS_MAX_LEVEL)
375 max_requested.PRE_EMPHASIS = PRE_EMPHASIS_MAX_LEVEL;
376 /*
377 if (max_requested.postCursor2 > PostCursor2_MaxLevel)
378 max_requested.postCursor2 = PostCursor2_MaxLevel;
379 */
380
381 /* make sure the pre-emphasis matches the voltage swing*/
382 if (max_requested.PRE_EMPHASIS >
383 get_max_pre_emphasis_for_voltage_swing(
384 max_requested.VOLTAGE_SWING))
385 max_requested.PRE_EMPHASIS =
386 get_max_pre_emphasis_for_voltage_swing(
387 max_requested.VOLTAGE_SWING);
388
389 /*
390 * Post Cursor2 levels are completely independent from
391 * pre-emphasis (Post Cursor1) levels. But Post Cursor2 levels
392 * can only be applied to each allowable combination of voltage
393 * swing and pre-emphasis levels */
394 /* if ( max_requested.postCursor2 >
395 * getMaxPostCursor2ForVoltageSwing(max_requested.voltageSwing))
396 * max_requested.postCursor2 =
397 * getMaxPostCursor2ForVoltageSwing(max_requested.voltageSwing);
398 */
399
400 max_lt_setting->link_settings.link_rate =
401 link_training_setting->link_settings.link_rate;
402 max_lt_setting->link_settings.lane_count =
403 link_training_setting->link_settings.lane_count;
404 max_lt_setting->link_settings.link_spread =
405 link_training_setting->link_settings.link_spread;
406
407 for (lane = 0; lane <
408 link_training_setting->link_settings.lane_count;
409 lane++) {
410 max_lt_setting->lane_settings[lane].VOLTAGE_SWING =
411 max_requested.VOLTAGE_SWING;
412 max_lt_setting->lane_settings[lane].PRE_EMPHASIS =
413 max_requested.PRE_EMPHASIS;
414 /*max_lt_setting->laneSettings[lane].postCursor2 =
415 * max_requested.postCursor2;
416 */
417 }
418
419}
420
421static void get_lane_status_and_drive_settings(
d0778ebf 422 struct dc_link *link,
4562236b
HW		 423 const struct link_training_settings *link_training_setting,
424 union lane_status *ln_status,
425 union lane_align_status_updated *ln_status_updated,
426 struct link_training_settings *req_settings)
427{
428 uint8_t dpcd_buf[6] = {0};
429 union lane_adjust dpcd_lane_adjust[LANE_COUNT_DP_MAX] = {{{0}}};
430 struct link_training_settings request_settings = {{0}};
431 uint32_t lane;
432
433 memset(req_settings, '\0', sizeof(struct link_training_settings));
434
435 core_link_read_dpcd(
436 link,
3a340294 437 DP_LANE0_1_STATUS,
4562236b
HW		 438 (uint8_t *)(dpcd_buf),
439 sizeof(dpcd_buf));
440
441 for (lane = 0; lane <
442 (uint32_t)(link_training_setting->link_settings.lane_count);
443 lane++) {
444
445 ln_status[lane].raw =
446 get_nibble_at_index(&dpcd_buf[0], lane);
447 dpcd_lane_adjust[lane].raw =
448 get_nibble_at_index(&dpcd_buf[4], lane);
449 }
450
451 ln_status_updated->raw = dpcd_buf[2];
452
453 dm_logger_write(link->ctx->logger, LOG_HW_LINK_TRAINING,
454 "%s:\n%x Lane01Status = %x\n %x Lane23Status = %x\n ",
455 __func__,
3a340294
DA		 456 DP_LANE0_1_STATUS, dpcd_buf[0],
457 DP_LANE2_3_STATUS, dpcd_buf[1]);
4562236b
HW		 458
459 dm_logger_write(link->ctx->logger, LOG_HW_LINK_TRAINING,
460 "%s:\n %x Lane01AdjustRequest = %x\n %x Lane23AdjustRequest = %x\n",
461 __func__,
3a340294 462 DP_ADJUST_REQUEST_LANE0_1,
4562236b 463 dpcd_buf[4],
3a340294 464 DP_ADJUST_REQUEST_LANE2_3,
4562236b
HW		 465 dpcd_buf[5]);
466
467 /*copy to req_settings*/
468 request_settings.link_settings.lane_count =
469 link_training_setting->link_settings.lane_count;
470 request_settings.link_settings.link_rate =
471 link_training_setting->link_settings.link_rate;
472 request_settings.link_settings.link_spread =
473 link_training_setting->link_settings.link_spread;
474
475 for (lane = 0; lane <
476 (uint32_t)(link_training_setting->link_settings.lane_count);
477 lane++) {
478
479 request_settings.lane_settings[lane].VOLTAGE_SWING =
480 (enum dc_voltage_swing)(dpcd_lane_adjust[lane].bits.
481 VOLTAGE_SWING_LANE);
482 request_settings.lane_settings[lane].PRE_EMPHASIS =
483 (enum dc_pre_emphasis)(dpcd_lane_adjust[lane].bits.
484 PRE_EMPHASIS_LANE);
485 }
486
487 /*Note: for postcursor2, read adjusted
488 * postcursor2 settings from*/
489 /*DpcdAddress_AdjustRequestPostCursor2 =
490 *0x020C (not implemented yet)*/
491
492 /* we find the maximum of the requested settings across all lanes*/
493 /* and set this maximum for all lanes*/
494 find_max_drive_settings(&request_settings, req_settings);
495
496 /* if post cursor 2 is needed in the future,
497 * read DpcdAddress_AdjustRequestPostCursor2 = 0x020C
498 */
499
500}
501
502static void dpcd_set_lane_settings(
d0778ebf 503 struct dc_link *link,
4562236b
HW		 504 const struct link_training_settings *link_training_setting)
505{
506 union dpcd_training_lane dpcd_lane[LANE_COUNT_DP_MAX] = {{{0}}};
507 uint32_t lane;
508
509 for (lane = 0; lane <
510 (uint32_t)(link_training_setting->
511 link_settings.lane_count);
512 lane++) {
513 dpcd_lane[lane].bits.VOLTAGE_SWING_SET =
514 (uint8_t)(link_training_setting->
515 lane_settings[lane].VOLTAGE_SWING);
516 dpcd_lane[lane].bits.PRE_EMPHASIS_SET =
517 (uint8_t)(link_training_setting->
518 lane_settings[lane].PRE_EMPHASIS);
519 dpcd_lane[lane].bits.MAX_SWING_REACHED =
520 (link_training_setting->
521 lane_settings[lane].VOLTAGE_SWING ==
522 VOLTAGE_SWING_MAX_LEVEL ? 1 : 0);
523 dpcd_lane[lane].bits.MAX_PRE_EMPHASIS_REACHED =
524 (link_training_setting->
525 lane_settings[lane].PRE_EMPHASIS ==
526 PRE_EMPHASIS_MAX_LEVEL ? 1 : 0);
527 }
528
529 core_link_write_dpcd(link,
3a340294 530 DP_TRAINING_LANE0_SET,
4562236b
HW		 531 (uint8_t *)(dpcd_lane),
532 link_training_setting->link_settings.lane_count);
533
534 /*
535 if (LTSettings.link.rate == LinkRate_High2)
536 {
537 DpcdTrainingLaneSet2 dpcd_lane2[lane_count_DPMax] = {0};
538 for ( uint32_t lane = 0;
539 lane < lane_count_DPMax; lane++)
540 {
541 dpcd_lane2[lane].bits.post_cursor2_set =
542 static_cast<unsigned char>(
543 LTSettings.laneSettings[lane].postCursor2);
544 dpcd_lane2[lane].bits.max_post_cursor2_reached = 0;
545 }
546 m_pDpcdAccessSrv->WriteDpcdData(
547 DpcdAddress_Lane0Set2,
548 reinterpret_cast<unsigned char*>(dpcd_lane2),
549 LTSettings.link.lanes);
550 }
551 */
552
553 dm_logger_write(link->ctx->logger, LOG_HW_LINK_TRAINING,
554 "%s\n %x VS set = %x PE set = %x \
555 max VS Reached = %x max PE Reached = %x\n",
556 __func__,
3a340294 557 DP_TRAINING_LANE0_SET,
4562236b
HW		 558 dpcd_lane[0].bits.VOLTAGE_SWING_SET,
559 dpcd_lane[0].bits.PRE_EMPHASIS_SET,
560 dpcd_lane[0].bits.MAX_SWING_REACHED,
561 dpcd_lane[0].bits.MAX_PRE_EMPHASIS_REACHED);
562
d0778ebf 563 link->cur_lane_setting = link_training_setting->lane_settings[0];
4562236b
HW		 564
565}
566
567static bool is_max_vs_reached(
568 const struct link_training_settings *lt_settings)
569{
570 uint32_t lane;
571 for (lane = 0; lane <
572 (uint32_t)(lt_settings->link_settings.lane_count);
573 lane++) {
574 if (lt_settings->lane_settings[lane].VOLTAGE_SWING
575 == VOLTAGE_SWING_MAX_LEVEL)
576 return true;
577 }
578 return false;
579
580}
581
582void dc_link_dp_set_drive_settings(
d0778ebf 583 struct dc_link *link,
4562236b
HW		 584 struct link_training_settings *lt_settings)
585{
4562236b 586 /* program ASIC PHY settings*/
d0778ebf 587 dp_set_hw_lane_settings(link, lt_settings);
4562236b
HW		 588
589 /* Notify DP sink the PHY settings from source */
d0778ebf 590 dpcd_set_lane_settings(link, lt_settings);
4562236b
HW		 591}
592
593static bool perform_post_lt_adj_req_sequence(
d0778ebf 594 struct dc_link *link,
4562236b
HW		 595 struct link_training_settings *lt_settings)
596{
597 enum dc_lane_count lane_count =
598 lt_settings->link_settings.lane_count;
599
600 uint32_t adj_req_count;
601 uint32_t adj_req_timer;
602 bool req_drv_setting_changed;
603 uint32_t lane;
604
605 req_drv_setting_changed = false;
606 for (adj_req_count = 0; adj_req_count < POST_LT_ADJ_REQ_LIMIT;
607 adj_req_count++) {
608
609 req_drv_setting_changed = false;
610
611 for (adj_req_timer = 0;
612 adj_req_timer < POST_LT_ADJ_REQ_TIMEOUT;
613 adj_req_timer++) {
614
615 struct link_training_settings req_settings;
616 union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX];
617 union lane_align_status_updated
618 dpcd_lane_status_updated;
619
620 get_lane_status_and_drive_settings(
621 link,
622 lt_settings,
623 dpcd_lane_status,
624 &dpcd_lane_status_updated,
625 &req_settings);
626
627 if (dpcd_lane_status_updated.bits.
628 POST_LT_ADJ_REQ_IN_PROGRESS == 0)
629 return true;
630
631 if (!is_cr_done(lane_count, dpcd_lane_status))
632 return false;
633
634 if (!is_ch_eq_done(
635 lane_count,
636 dpcd_lane_status,
637 &dpcd_lane_status_updated))
638 return false;
639
640 for (lane = 0; lane < (uint32_t)(lane_count); lane++) {
641
642 if (lt_settings->
643 lane_settings[lane].VOLTAGE_SWING !=
644 req_settings.lane_settings[lane].
645 VOLTAGE_SWING ||
646 lt_settings->lane_settings[lane].PRE_EMPHASIS !=
647 req_settings.lane_settings[lane].PRE_EMPHASIS) {
648
649 req_drv_setting_changed = true;
650 break;
651 }
652 }
653
654 if (req_drv_setting_changed) {
655 update_drive_settings(
656 lt_settings,req_settings);
657
d0778ebf 658 dc_link_dp_set_drive_settings(link,
4562236b
HW		 659 lt_settings);
660 break;
661 }
662
663 msleep(1);
664 }
665
666 if (!req_drv_setting_changed) {
667 dm_logger_write(link->ctx->logger, LOG_WARNING,
668 "%s: Post Link Training Adjust Request Timed out\n",
669 __func__);
670
671 ASSERT(0);
672 return true;
673 }
674 }
675 dm_logger_write(link->ctx->logger, LOG_WARNING,
676 "%s: Post Link Training Adjust Request limit reached\n",
677 __func__);
678
679 ASSERT(0);
680 return true;
681
682}
683
d0778ebf 684static enum hw_dp_training_pattern get_supported_tp(struct dc_link *link)
4562236b
HW		 685{
686 enum hw_dp_training_pattern highest_tp = HW_DP_TRAINING_PATTERN_2;
687 struct encoder_feature_support *features = &link->link_enc->features;
688 struct dpcd_caps *dpcd_caps = &link->dpcd_caps;
689
690 if (features->flags.bits.IS_TPS3_CAPABLE)
691 highest_tp = HW_DP_TRAINING_PATTERN_3;
692
693 if (features->flags.bits.IS_TPS4_CAPABLE)
694 highest_tp = HW_DP_TRAINING_PATTERN_4;
695
696 if (dpcd_caps->max_down_spread.bits.TPS4_SUPPORTED &&
697 highest_tp >= HW_DP_TRAINING_PATTERN_4)
698 return HW_DP_TRAINING_PATTERN_4;
699
700 if (dpcd_caps->max_ln_count.bits.TPS3_SUPPORTED &&
701 highest_tp >= HW_DP_TRAINING_PATTERN_3)
702 return HW_DP_TRAINING_PATTERN_3;
703
704 return HW_DP_TRAINING_PATTERN_2;
705}
706
820e3935 707static enum link_training_result perform_channel_equalization_sequence(
d0778ebf 708 struct dc_link *link,
4562236b
HW		 709 struct link_training_settings *lt_settings)
710{
711 struct link_training_settings req_settings;
712 enum hw_dp_training_pattern hw_tr_pattern;
713 uint32_t retries_ch_eq;
714 enum dc_lane_count lane_count = lt_settings->link_settings.lane_count;
715 union lane_align_status_updated dpcd_lane_status_updated = {{0}};
716 union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX] = {{{0}}};;
717
718 hw_tr_pattern = get_supported_tp(link);
719
720 dp_set_hw_training_pattern(link, hw_tr_pattern);
721
722 for (retries_ch_eq = 0; retries_ch_eq <= LINK_TRAINING_MAX_RETRY_COUNT;
723 retries_ch_eq++) {
724
725 dp_set_hw_lane_settings(link, lt_settings);
726
727 /* 2. update DPCD*/
728 if (!retries_ch_eq)
729 /* EPR #361076 - write as a 5-byte burst,
730 * but only for the 1-st iteration*/
731 dpcd_set_lt_pattern_and_lane_settings(
732 link,
733 lt_settings,
734 hw_tr_pattern);
735 else
736 dpcd_set_lane_settings(link, lt_settings);
737
738 /* 3. wait for receiver to lock-on*/
739 wait_for_training_aux_rd_interval(link, 400);
740
741 /* 4. Read lane status and requested
742 * drive settings as set by the sink*/
743
744 get_lane_status_and_drive_settings(
745 link,
746 lt_settings,
747 dpcd_lane_status,
748 &dpcd_lane_status_updated,
749 &req_settings);
750
751 /* 5. check CR done*/
752 if (!is_cr_done(lane_count, dpcd_lane_status))
820e3935 753 return LINK_TRAINING_EQ_FAIL_CR;
4562236b
HW		 754
755 /* 6. check CHEQ done*/
756 if (is_ch_eq_done(lane_count,
757 dpcd_lane_status,
758 &dpcd_lane_status_updated))
820e3935 759 return LINK_TRAINING_SUCCESS;
4562236b
HW		 760
761 /* 7. update VS/PE/PC2 in lt_settings*/
762 update_drive_settings(lt_settings, req_settings);
763 }
764
820e3935 765 return LINK_TRAINING_EQ_FAIL_EQ;
4562236b
HW		 766
767}
768
769static bool perform_clock_recovery_sequence(
d0778ebf 770 struct dc_link *link,
4562236b
HW		 771 struct link_training_settings *lt_settings)
772{
773 uint32_t retries_cr;
774 uint32_t retry_count;
775 uint32_t lane;
776 struct link_training_settings req_settings;
777 enum dc_lane_count lane_count =
778 lt_settings->link_settings.lane_count;
779 enum hw_dp_training_pattern hw_tr_pattern = HW_DP_TRAINING_PATTERN_1;
780 union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX];
781 union lane_align_status_updated dpcd_lane_status_updated;
782
783 retries_cr = 0;
784 retry_count = 0;
785 /* initial drive setting (VS/PE/PC2)*/
786 for (lane = 0; lane < LANE_COUNT_DP_MAX; lane++) {
787 lt_settings->lane_settings[lane].VOLTAGE_SWING =
788 VOLTAGE_SWING_LEVEL0;
789 lt_settings->lane_settings[lane].PRE_EMPHASIS =
790 PRE_EMPHASIS_DISABLED;
791 lt_settings->lane_settings[lane].POST_CURSOR2 =
792 POST_CURSOR2_DISABLED;
793 }
794
795 dp_set_hw_training_pattern(link, hw_tr_pattern);
796
797 /* najeeb - The synaptics MST hub can put the LT in
798 * infinite loop by switching the VS
799 */
800 /* between level 0 and level 1 continuously, here
801 * we try for CR lock for LinkTrainingMaxCRRetry count*/
802 while ((retries_cr < LINK_TRAINING_MAX_RETRY_COUNT) &&
803 (retry_count < LINK_TRAINING_MAX_CR_RETRY)) {
804
805 memset(&dpcd_lane_status, '\0', sizeof(dpcd_lane_status));
806 memset(&dpcd_lane_status_updated, '\0',
807 sizeof(dpcd_lane_status_updated));
808
809 /* 1. call HWSS to set lane settings*/
810 dp_set_hw_lane_settings(
811 link,
812 lt_settings);
813
814 /* 2. update DPCD of the receiver*/
815 if (!retries_cr)
816 /* EPR #361076 - write as a 5-byte burst,
817 * but only for the 1-st iteration.*/
818 dpcd_set_lt_pattern_and_lane_settings(
819 link,
820 lt_settings,
821 hw_tr_pattern);
822 else
823 dpcd_set_lane_settings(
824 link,
825 lt_settings);
826
827 /* 3. wait receiver to lock-on*/
828 wait_for_training_aux_rd_interval(
829 link,
830 100);
831
832 /* 4. Read lane status and requested drive
833 * settings as set by the sink
834 */
835 get_lane_status_and_drive_settings(
836 link,
837 lt_settings,
838 dpcd_lane_status,
839 &dpcd_lane_status_updated,
840 &req_settings);
841
842 /* 5. check CR done*/
843 if (is_cr_done(lane_count, dpcd_lane_status))
844 return true;
845
846 /* 6. max VS reached*/
847 if (is_max_vs_reached(lt_settings))
848 return false;
849
850 /* 7. same voltage*/
851 /* Note: VS same for all lanes,
852 * so comparing first lane is sufficient*/
853 if (lt_settings->lane_settings[0].VOLTAGE_SWING ==
854 req_settings.lane_settings[0].VOLTAGE_SWING)
855 retries_cr++;
856 else
857 retries_cr = 0;
858
859 /* 8. update VS/PE/PC2 in lt_settings*/
860 update_drive_settings(lt_settings, req_settings);
861
862 retry_count++;
863 }
864
865 if (retry_count >= LINK_TRAINING_MAX_CR_RETRY) {
866 ASSERT(0);
867 dm_logger_write(link->ctx->logger, LOG_ERROR,
868 "%s: Link Training Error, could not \
869 get CR after %d tries. \
870 Possibly voltage swing issue", __func__,
871 LINK_TRAINING_MAX_CR_RETRY);
872
873 }
874
875 return false;
876}
877
878static inline bool perform_link_training_int(
d0778ebf 879 struct dc_link *link,
4562236b
HW		 880 struct link_training_settings *lt_settings,
881 bool status)
882{
883 union lane_count_set lane_count_set = { {0} };
884 union dpcd_training_pattern dpcd_pattern = { {0} };
885
886 /* 3. set training not in progress*/
887 dpcd_pattern.v1_4.TRAINING_PATTERN_SET = DPCD_TRAINING_PATTERN_VIDEOIDLE;
888 dpcd_set_training_pattern(link, dpcd_pattern);
889
890 /* 4. mainlink output idle pattern*/
891 dp_set_hw_test_pattern(link, DP_TEST_PATTERN_VIDEO_MODE, NULL, 0);
892
893 /*
894 * 5. post training adjust if required
895 * If the upstream DPTX and downstream DPRX both support TPS4,
896 * TPS4 must be used instead of POST_LT_ADJ_REQ.
897 */
c30267f5
CL		 898 if (link->dpcd_caps.max_ln_count.bits.POST_LT_ADJ_REQ_SUPPORTED != 1 ||
899 get_supported_tp(link) == HW_DP_TRAINING_PATTERN_4)
4562236b
HW		 900 return status;
901
902 if (status &&
903 perform_post_lt_adj_req_sequence(link, lt_settings) == false)
904 status = false;
905
906 lane_count_set.bits.LANE_COUNT_SET = lt_settings->link_settings.lane_count;
907 lane_count_set.bits.ENHANCED_FRAMING = 1;
908 lane_count_set.bits.POST_LT_ADJ_REQ_GRANTED = 0;
909
910 core_link_write_dpcd(
911 link,
3a340294 912 DP_LANE_COUNT_SET,
4562236b
HW		 913 &lane_count_set.raw,
914 sizeof(lane_count_set));
915
916 return status;
917}
918
820e3935 919enum link_training_result dc_link_dp_perform_link_training(
4562236b
HW		 920 struct dc_link *link,
921 const struct dc_link_settings *link_setting,
922 bool skip_video_pattern)
923{
820e3935 924 enum link_training_result status = LINK_TRAINING_SUCCESS;
4562236b
HW		 925
926 char *link_rate = "Unknown";
927 struct link_training_settings lt_settings;
928
4562236b
HW		 929 memset(&lt_settings, '\0', sizeof(lt_settings));
930
931 lt_settings.link_settings.link_rate = link_setting->link_rate;
932 lt_settings.link_settings.lane_count = link_setting->lane_count;
933
934 /*@todo[vdevulap] move SS to LS, should not be handled by displaypath*/
935
936 /* TODO hard coded to SS for now
937 * lt_settings.link_settings.link_spread =
938 * dal_display_path_is_ss_supported(
939 * path_mode->display_path) ?
940 * LINK_SPREAD_05_DOWNSPREAD_30KHZ :
941 * LINK_SPREAD_DISABLED;
942 */
943 lt_settings.link_settings.link_spread = LINK_SPREAD_05_DOWNSPREAD_30KHZ;
944
945 /* 1. set link rate, lane count and spread*/
d0778ebf 946 dpcd_set_link_settings(link, &lt_settings);
4562236b
HW		 947
948 /* 2. perform link training (set link training done
949 * to false is done as well)*/
d0778ebf 950 if (!perform_clock_recovery_sequence(link, &lt_settings)) {
820e3935
DW		 951 status = LINK_TRAINING_CR_FAIL;
952 } else {
d0778ebf 953 status = perform_channel_equalization_sequence(link,
820e3935 954 &lt_settings);
4562236b
HW		 955 }
956
820e3935 957 if ((status == LINK_TRAINING_SUCCESS) || !skip_video_pattern) {
d0778ebf 958 if (!perform_link_training_int(link,
820e3935
DW		 959 &lt_settings,
960 status == LINK_TRAINING_SUCCESS)) {
961 /* the next link training setting in this case
962 * would be the same as CR failure case.
963 */
964 status = LINK_TRAINING_CR_FAIL;
965 }
966 }
4562236b
HW		 967
968 /* 6. print status message*/
969 switch (lt_settings.link_settings.link_rate) {
970
971 case LINK_RATE_LOW:
972 link_rate = "RBR";
973 break;
974 case LINK_RATE_HIGH:
975 link_rate = "HBR";
976 break;
977 case LINK_RATE_HIGH2:
978 link_rate = "HBR2";
979 break;
980 case LINK_RATE_RBR2:
981 link_rate = "RBR2";
982 break;
983 case LINK_RATE_HIGH3:
984 link_rate = "HBR3";
985 break;
986 default:
987 break;
988 }
989
990 /* Connectivity log: link training */
d0778ebf 991 CONN_MSG_LT(link, "%sx%d %s VS=%d, PE=%d",
4562236b
HW		 992 link_rate,
993 lt_settings.link_settings.lane_count,
820e3935
DW		 994 (status == LINK_TRAINING_SUCCESS) ? "pass" :
995 ((status == LINK_TRAINING_CR_FAIL) ? "CR failed" :
996 "EQ failed"),
4562236b
HW		 997 lt_settings.lane_settings[0].VOLTAGE_SWING,
998 lt_settings.lane_settings[0].PRE_EMPHASIS);
999
1000 return status;
1001}
1002
1003
1004bool perform_link_training_with_retries(
d0778ebf 1005 struct dc_link *link,
4562236b
HW		 1006 const struct dc_link_settings *link_setting,
1007 bool skip_video_pattern,
1008 int attempts)
1009{
1010 uint8_t j;
1011 uint8_t delay_between_attempts = LINK_TRAINING_RETRY_DELAY;
1012
1013 for (j = 0; j < attempts; ++j) {
1014
1015 if (dc_link_dp_perform_link_training(
d0778ebf 1016 link,
4562236b 1017 link_setting,
820e3935 1018 skip_video_pattern) == LINK_TRAINING_SUCCESS)
4562236b
HW		 1019 return true;
1020
1021 msleep(delay_between_attempts);
1022 delay_between_attempts += LINK_TRAINING_RETRY_DELAY;
1023 }
1024
1025 return false;
1026}
1027
d0778ebf 1028static struct dc_link_settings get_max_link_cap(struct dc_link *link)
4562236b
HW		 1029{
1030 /* Set Default link settings */
1031 struct dc_link_settings max_link_cap = {LANE_COUNT_FOUR, LINK_RATE_HIGH,
1032 LINK_SPREAD_05_DOWNSPREAD_30KHZ};
1033
1034 /* Higher link settings based on feature supported */
1035 if (link->link_enc->features.flags.bits.IS_HBR2_CAPABLE)
1036 max_link_cap.link_rate = LINK_RATE_HIGH2;
1037
1038 if (link->link_enc->features.flags.bits.IS_HBR3_CAPABLE)
1039 max_link_cap.link_rate = LINK_RATE_HIGH3;
1040
1041 /* Lower link settings based on sink's link cap */
d0778ebf 1042 if (link->reported_link_cap.lane_count < max_link_cap.lane_count)
4562236b 1043 max_link_cap.lane_count =
d0778ebf
HW		 1044 link->reported_link_cap.lane_count;
1045 if (link->reported_link_cap.link_rate < max_link_cap.link_rate)
4562236b 1046 max_link_cap.link_rate =
d0778ebf
HW		 1047 link->reported_link_cap.link_rate;
1048 if (link->reported_link_cap.link_spread <
4562236b
HW		 1049 max_link_cap.link_spread)
1050 max_link_cap.link_spread =
d0778ebf 1051 link->reported_link_cap.link_spread;
4562236b
HW		 1052 return max_link_cap;
1053}
1054
1055bool dp_hbr_verify_link_cap(
d0778ebf 1056 struct dc_link *link,
4562236b
HW		 1057 struct dc_link_settings *known_limit_link_setting)
1058{
1059 struct dc_link_settings max_link_cap = {0};
820e3935
DW		 1060 struct dc_link_settings cur_link_setting = {0};
1061 struct dc_link_settings *cur = &cur_link_setting;
1062 struct dc_link_settings initial_link_settings = {0};
4562236b
HW		 1063 bool success;
1064 bool skip_link_training;
4562236b 1065 bool skip_video_pattern;
4562236b
HW		 1066 struct clock_source *dp_cs;
1067 enum clock_source_id dp_cs_id = CLOCK_SOURCE_ID_EXTERNAL;
820e3935 1068 enum link_training_result status;
4562236b
HW		 1069
1070 success = false;
1071 skip_link_training = false;
1072
1073 max_link_cap = get_max_link_cap(link);
1074
1075 /* TODO implement override and monitor patch later */
1076
1077 /* try to train the link from high to low to
1078 * find the physical link capability
1079 */
1080 /* disable PHY done possible by BIOS, will be done by driver itself */
d0778ebf 1081 dp_disable_link_phy(link, link->connector_signal);
4562236b
HW		 1082
1083 dp_cs = link->dc->res_pool->dp_clock_source;
1084
1085 if (dp_cs)
1086 dp_cs_id = dp_cs->id;
1087 else {
1088 /*
1089 * dp clock source is not initialized for some reason.
1090 * Should not happen, CLOCK_SOURCE_ID_EXTERNAL will be used
1091 */
1092 ASSERT(dp_cs);
1093 }
1094
820e3935
DW		 1095 /* link training starts with the maximum common settings
1096 * supported by both sink and ASIC.
1097 */
1098 initial_link_settings = get_common_supported_link_settings(
1099 *known_limit_link_setting,
1100 max_link_cap);
1101 cur_link_setting = initial_link_settings;
1102 do {
4562236b 1103 skip_video_pattern = true;
820e3935 1104
4562236b
HW		 1105 if (cur->link_rate == LINK_RATE_LOW)
1106 skip_video_pattern = false;
1107
1108 dp_enable_link_phy(
1109 link,
d0778ebf 1110 link->connector_signal,
4562236b
HW		 1111 dp_cs_id,
1112 cur);
1113
1114 if (skip_link_training)
1115 success = true;
1116 else {
820e3935 1117 status = dc_link_dp_perform_link_training(
d0778ebf 1118 link,
4562236b
HW		 1119 cur,
1120 skip_video_pattern);
820e3935
DW		 1121 if (status == LINK_TRAINING_SUCCESS)
1122 success = true;
4562236b
HW		 1123 }
1124
1125 if (success)
d0778ebf 1126 link->verified_link_cap = *cur;
4562236b
HW		 1127
1128 /* always disable the link before trying another
1129 * setting or before returning we'll enable it later
1130 * based on the actual mode we're driving
1131 */
d0778ebf 1132 dp_disable_link_phy(link, link->connector_signal);
820e3935
DW		 1133 } while (!success && decide_fallback_link_setting(
1134 initial_link_settings, cur, status));
4562236b
HW		 1135
1136 /* Link Training failed for all Link Settings
1137 * (Lane Count is still unknown)
1138 */
1139 if (!success) {
1140 /* If all LT fails for all settings,
1141 * set verified = failed safe (1 lane low)
1142 */
d0778ebf
HW		 1143 link->verified_link_cap.lane_count = LANE_COUNT_ONE;
1144 link->verified_link_cap.link_rate = LINK_RATE_LOW;
4562236b 1145
d0778ebf 1146 link->verified_link_cap.link_spread =
4562236b
HW		 1147 LINK_SPREAD_DISABLED;
1148 }
1149
4562236b
HW		 1150
1151 return success;
1152}
1153
820e3935
DW		 1154struct dc_link_settings get_common_supported_link_settings (
1155 struct dc_link_settings link_setting_a,
1156 struct dc_link_settings link_setting_b)
1157{
1158 struct dc_link_settings link_settings = {0};
1159
1160 link_settings.lane_count =
1161 (link_setting_a.lane_count <=
1162 link_setting_b.lane_count) ?
1163 link_setting_a.lane_count :
1164 link_setting_b.lane_count;
1165 link_settings.link_rate =
1166 (link_setting_a.link_rate <=
1167 link_setting_b.link_rate) ?
1168 link_setting_a.link_rate :
1169 link_setting_b.link_rate;
1170 link_settings.link_spread = LINK_SPREAD_DISABLED;
1171
1172 /* in DP compliance test, DPR-120 may have
1173 * a random value in its MAX_LINK_BW dpcd field.
1174 * We map it to the maximum supported link rate that
1175 * is smaller than MAX_LINK_BW in this case.
1176 */
1177 if (link_settings.link_rate > LINK_RATE_HIGH3) {
1178 link_settings.link_rate = LINK_RATE_HIGH3;
1179 } else if (link_settings.link_rate < LINK_RATE_HIGH3
1180 && link_settings.link_rate > LINK_RATE_HIGH2) {
1181 link_settings.link_rate = LINK_RATE_HIGH2;
1182 } else if (link_settings.link_rate < LINK_RATE_HIGH2
1183 && link_settings.link_rate > LINK_RATE_HIGH) {
1184 link_settings.link_rate = LINK_RATE_HIGH;
1185 } else if (link_settings.link_rate < LINK_RATE_HIGH
1186 && link_settings.link_rate > LINK_RATE_LOW) {
1187 link_settings.link_rate = LINK_RATE_LOW;
1188 } else if (link_settings.link_rate < LINK_RATE_LOW) {
1189 link_settings.link_rate = LINK_RATE_UNKNOWN;
1190 }
1191
1192 return link_settings;
1193}
1194
1195bool reached_minimum_lane_count(enum dc_lane_count lane_count)
1196{
1197 return lane_count <= LANE_COUNT_ONE;
1198}
1199
1200bool reached_minimum_link_rate(enum dc_link_rate link_rate)
1201{
1202 return link_rate <= LINK_RATE_LOW;
1203}
1204
1205enum dc_lane_count reduce_lane_count(enum dc_lane_count lane_count)
1206{
1207 switch (lane_count) {
1208 case LANE_COUNT_FOUR:
1209 return LANE_COUNT_TWO;
1210 case LANE_COUNT_TWO:
1211 return LANE_COUNT_ONE;
1212 case LANE_COUNT_ONE:
1213 return LANE_COUNT_UNKNOWN;
1214 default:
1215 return LANE_COUNT_UNKNOWN;
1216 }
1217}
1218
1219enum dc_link_rate reduce_link_rate(enum dc_link_rate link_rate)
1220{
1221 switch (link_rate) {
1222 case LINK_RATE_HIGH3:
1223 return LINK_RATE_HIGH2;
1224 case LINK_RATE_HIGH2:
1225 return LINK_RATE_HIGH;
1226 case LINK_RATE_HIGH:
1227 return LINK_RATE_LOW;
1228 case LINK_RATE_LOW:
1229 return LINK_RATE_UNKNOWN;
1230 default:
1231 return LINK_RATE_UNKNOWN;
1232 }
1233}
1234
8c4abe0b
DW		 1235enum dc_lane_count increase_lane_count(enum dc_lane_count lane_count)
1236{
1237 switch (lane_count) {
1238 case LANE_COUNT_ONE:
1239 return LANE_COUNT_TWO;
1240 case LANE_COUNT_TWO:
1241 return LANE_COUNT_FOUR;
1242 default:
1243 return LANE_COUNT_UNKNOWN;
1244 }
1245}
1246
1247enum dc_link_rate increase_link_rate(enum dc_link_rate link_rate)
1248{
1249 switch (link_rate) {
1250 case LINK_RATE_LOW:
1251 return LINK_RATE_HIGH;
1252 case LINK_RATE_HIGH:
1253 return LINK_RATE_HIGH2;
1254 case LINK_RATE_HIGH2:
1255 return LINK_RATE_HIGH3;
1256 default:
1257 return LINK_RATE_UNKNOWN;
1258 }
1259}
1260
820e3935
DW		 1261/*
1262 * function: set link rate and lane count fallback based
1263 * on current link setting and last link training result
1264 * return value:
1265 * true - link setting could be set
1266 * false - has reached minimum setting
1267 * and no further fallback could be done
1268 */
1269bool decide_fallback_link_setting(
1270 struct dc_link_settings initial_link_settings,
1271 struct dc_link_settings *current_link_setting,
1272 enum link_training_result training_result)
1273{
1274 if (!current_link_setting)
1275 return false;
1276
1277 switch (training_result) {
1278 case LINK_TRAINING_CR_FAIL:
1279 {
1280 if (!reached_minimum_link_rate
1281 (current_link_setting->link_rate)) {
1282 current_link_setting->link_rate =
1283 reduce_link_rate(
1284 current_link_setting->link_rate);
1285 } else if (!reached_minimum_lane_count
1286 (current_link_setting->lane_count)) {
1287 current_link_setting->link_rate =
1288 initial_link_settings.link_rate;
1289 current_link_setting->lane_count =
1290 reduce_lane_count(
1291 current_link_setting->lane_count);
1292 } else {
1293 return false;
1294 }
1295 break;
1296 }
1297 case LINK_TRAINING_EQ_FAIL_EQ:
1298 {
1299 if (!reached_minimum_lane_count
1300 (current_link_setting->lane_count)) {
1301 current_link_setting->lane_count =
1302 reduce_lane_count(
1303 current_link_setting->lane_count);
1304 } else if (!reached_minimum_link_rate
1305 (current_link_setting->link_rate)) {
1306 current_link_setting->lane_count =
1307 initial_link_settings.lane_count;
1308 current_link_setting->link_rate =
1309 reduce_link_rate(
1310 current_link_setting->link_rate);
1311 } else {
1312 return false;
1313 }
1314 break;
1315 }
1316 case LINK_TRAINING_EQ_FAIL_CR:
1317 {
1318 if (!reached_minimum_link_rate
1319 (current_link_setting->link_rate)) {
1320 current_link_setting->link_rate =
1321 reduce_link_rate(
1322 current_link_setting->link_rate);
1323 } else {
1324 return false;
1325 }
1326 break;
1327 }
1328 default:
1329 return false;
1330 }
1331 return true;
1332}
1333
4562236b
HW		 1334static uint32_t bandwidth_in_kbps_from_timing(
1335 const struct dc_crtc_timing *timing)
1336{
1337 uint32_t bits_per_channel = 0;
1338 uint32_t kbps;
1339 switch (timing->display_color_depth) {
1340
1341 case COLOR_DEPTH_666:
1342 bits_per_channel = 6;
1343 break;
1344 case COLOR_DEPTH_888:
1345 bits_per_channel = 8;
1346 break;
1347 case COLOR_DEPTH_101010:
1348 bits_per_channel = 10;
1349 break;
1350 case COLOR_DEPTH_121212:
1351 bits_per_channel = 12;
1352 break;
1353 case COLOR_DEPTH_141414:
1354 bits_per_channel = 14;
1355 break;
1356 case COLOR_DEPTH_161616:
1357 bits_per_channel = 16;
1358 break;
1359 default:
1360 break;
1361 }
1362 ASSERT(bits_per_channel != 0);
1363
1364 kbps = timing->pix_clk_khz;
1365 kbps *= bits_per_channel;
1366
1367 if (timing->flags.Y_ONLY != 1)
1368 /*Only YOnly make reduce bandwidth by 1/3 compares to RGB*/
1369 kbps *= 3;
1370
1371 return kbps;
1372
1373}
1374
1375static uint32_t bandwidth_in_kbps_from_link_settings(
1376 const struct dc_link_settings *link_setting)
1377{
1378 uint32_t link_rate_in_kbps = link_setting->link_rate *
1379 LINK_RATE_REF_FREQ_IN_KHZ;
1380
1381 uint32_t lane_count = link_setting->lane_count;
1382 uint32_t kbps = link_rate_in_kbps;
1383 kbps *= lane_count;
1384 kbps *= 8; /* 8 bits per byte*/
1385
1386 return kbps;
1387
1388}
1389
1390bool dp_validate_mode_timing(
d0778ebf 1391 struct dc_link *link,
4562236b
HW		 1392 const struct dc_crtc_timing *timing)
1393{
1394 uint32_t req_bw;
1395 uint32_t max_bw;
1396
1397 const struct dc_link_settings *link_setting;
1398
1399 /*always DP fail safe mode*/
1400 if (timing->pix_clk_khz == (uint32_t)25175 &&
1401 timing->h_addressable == (uint32_t)640 &&
1402 timing->v_addressable == (uint32_t)480)
1403 return true;
1404
1405 /* We always use verified link settings */
d0778ebf 1406 link_setting = &link->verified_link_cap;
4562236b
HW		 1407
1408 /* TODO: DYNAMIC_VALIDATION needs to be implemented */
1409 /*if (flags.DYNAMIC_VALIDATION == 1 &&
d0778ebf
HW		 1410 link->verified_link_cap.lane_count != LANE_COUNT_UNKNOWN)
1411 link_setting = &link->verified_link_cap;
4562236b
HW		 1412 */
1413
1414 req_bw = bandwidth_in_kbps_from_timing(timing);
1415 max_bw = bandwidth_in_kbps_from_link_settings(link_setting);
1416
1417 if (req_bw <= max_bw) {
1418 /* remember the biggest mode here, during
1419 * initial link training (to get
1420 * verified_link_cap), LS sends event about
1421 * cannot train at reported cap to upper
1422 * layer and upper layer will re-enumerate modes.
1423 * this is not necessary if the lower
1424 * verified_link_cap is enough to drive
1425 * all the modes */
1426
1427 /* TODO: DYNAMIC_VALIDATION needs to be implemented */
1428 /* if (flags.DYNAMIC_VALIDATION == 1)
1429 dpsst->max_req_bw_for_verified_linkcap = dal_max(
1430 dpsst->max_req_bw_for_verified_linkcap, req_bw); */
1431 return true;
1432 } else
1433 return false;
1434}
1435
0971c40e 1436void decide_link_settings(struct dc_stream_state *stream,
4562236b
HW		 1437 struct dc_link_settings *link_setting)
1438{
1439
8c4abe0b
DW		 1440 struct dc_link_settings initial_link_setting = {
1441 LANE_COUNT_ONE, LINK_RATE_LOW, LINK_SPREAD_DISABLED};
1442 struct dc_link_settings current_link_setting =
1443 initial_link_setting;
d0778ebf 1444 struct dc_link *link;
4562236b
HW		 1445 uint32_t req_bw;
1446 uint32_t link_bw;
4562236b 1447
4fa086b9 1448 req_bw = bandwidth_in_kbps_from_timing(&stream->timing);
4562236b 1449
8c4abe0b
DW		 1450 link = stream->sink->link;
1451
4562236b
HW		 1452 /* if preferred is specified through AMDDP, use it, if it's enough
1453 * to drive the mode
1454 */
d0778ebf 1455 if (link->preferred_link_setting.lane_count !=
8c4abe0b 1456 LANE_COUNT_UNKNOWN &&
d0778ebf 1457 link->preferred_link_setting.link_rate !=
8c4abe0b 1458 LINK_RATE_UNKNOWN) {
d0778ebf 1459 *link_setting = link->preferred_link_setting;
8c4abe0b
DW		 1460 return;
1461 }
4562236b 1462
8c4abe0b
DW		 1463 /* search for the minimum link setting that:
1464 * 1. is supported according to the link training result
1465 * 2. could support the b/w requested by the timing
1466 */
1467 while (current_link_setting.link_rate <=
4654a2f7 1468 link->verified_link_cap.link_rate) {
4562236b 1469 link_bw = bandwidth_in_kbps_from_link_settings(
8c4abe0b
DW		 1470 &current_link_setting);
1471 if (req_bw <= link_bw) {
1472 *link_setting = current_link_setting;
4562236b
HW		 1473 return;
1474 }
4562236b 1475
8c4abe0b 1476 if (current_link_setting.lane_count <
4654a2f7 1477 link->verified_link_cap.lane_count) {
8c4abe0b
DW		 1478 current_link_setting.lane_count =
1479 increase_lane_count(
1480 current_link_setting.lane_count);
1481 } else {
1482 current_link_setting.link_rate =
1483 increase_link_rate(
1484 current_link_setting.link_rate);
1485 current_link_setting.lane_count =
1486 initial_link_setting.lane_count;
4562236b
HW		 1487 }
1488 }
1489
1490 BREAK_TO_DEBUGGER();
d0778ebf 1491 ASSERT(link->verified_link_cap.lane_count != LANE_COUNT_UNKNOWN);
4562236b 1492
d0778ebf 1493 *link_setting = link->verified_link_cap;
4562236b
HW		 1494}
1495
1496/*************************Short Pulse IRQ***************************/
1497
1498static bool hpd_rx_irq_check_link_loss_status(
d0778ebf 1499 struct dc_link *link,
4562236b
HW		 1500 union hpd_irq_data *hpd_irq_dpcd_data)
1501{
1502 uint8_t irq_reg_rx_power_state;
1503 enum dc_status dpcd_result = DC_ERROR_UNEXPECTED;
1504 union lane_status lane_status;
1505 uint32_t lane;
1506 bool sink_status_changed;
1507 bool return_code;
1508
1509 sink_status_changed = false;
1510 return_code = false;
1511
d0778ebf 1512 if (link->cur_link_settings.lane_count == 0)
4562236b
HW		 1513 return return_code;
1514 /*1. Check that we can handle interrupt: Not in FS DOS,
1515 * Not in "Display Timeout" state, Link is trained.
1516 */
1517
1518 dpcd_result = core_link_read_dpcd(link,
3a340294 1519 DP_SET_POWER,
4562236b
HW		 1520 &irq_reg_rx_power_state,
1521 sizeof(irq_reg_rx_power_state));
1522
1523 if (dpcd_result != DC_OK) {
3a340294 1524 irq_reg_rx_power_state = DP_SET_POWER_D0;
4562236b
HW		 1525 dm_logger_write(link->ctx->logger, LOG_HW_HPD_IRQ,
1526 "%s: DPCD read failed to obtain power state.\n",
1527 __func__);
1528 }
1529
3a340294 1530 if (irq_reg_rx_power_state == DP_SET_POWER_D0) {
4562236b
HW		 1531
1532 /*2. Check that Link Status changed, before re-training.*/
1533
1534 /*parse lane status*/
1535 for (lane = 0;
d0778ebf 1536 lane < link->cur_link_settings.lane_count;
4562236b
HW		 1537 lane++) {
1538
1539 /* check status of lanes 0,1
1540 * changed DpcdAddress_Lane01Status (0x202)*/
1541 lane_status.raw = get_nibble_at_index(
1542 &hpd_irq_dpcd_data->bytes.lane01_status.raw,
1543 lane);
1544
1545 if (!lane_status.bits.CHANNEL_EQ_DONE_0 ||
1546 !lane_status.bits.CR_DONE_0 ||
1547 !lane_status.bits.SYMBOL_LOCKED_0) {
1548 /* if one of the channel equalization, clock
1549 * recovery or symbol lock is dropped
1550 * consider it as (link has been
1551 * dropped) dp sink status has changed*/
1552 sink_status_changed = true;
1553 break;
1554 }
1555
1556 }
1557
1558 /* Check interlane align.*/
1559 if (sink_status_changed ||
1560 !hpd_irq_dpcd_data->bytes.lane_status_updated.bits.
1561 INTERLANE_ALIGN_DONE) {
1562
1563 dm_logger_write(link->ctx->logger, LOG_HW_HPD_IRQ,
1564 "%s: Link Status changed.\n",
1565 __func__);
1566
1567 return_code = true;
1568 }
1569 }
1570
1571 return return_code;
1572}
1573
1574static enum dc_status read_hpd_rx_irq_data(
d0778ebf 1575 struct dc_link *link,
4562236b
HW		 1576 union hpd_irq_data *irq_data)
1577{
1578 /* The HW reads 16 bytes from 200h on HPD,
1579 * but if we get an AUX_DEFER, the HW cannot retry
1580 * and this causes the CTS tests 4.3.2.1 - 3.2.4 to
1581 * fail, so we now explicitly read 6 bytes which is
1582 * the req from the above mentioned test cases.
1583 */
1584 return core_link_read_dpcd(
1585 link,
3a340294 1586 DP_SINK_COUNT,
4562236b
HW		 1587 irq_data->raw,
1588 sizeof(union hpd_irq_data));
1589}
1590
d0778ebf 1591static bool allow_hpd_rx_irq(const struct dc_link *link)
4562236b
HW		 1592{
1593 /*
1594 * Don't handle RX IRQ unless one of following is met:
1595 * 1) The link is established (cur_link_settings != unknown)
1596 * 2) We kicked off MST detection
1597 * 3) We know we're dealing with an active dongle
1598 */
1599
d0778ebf
HW		 1600 if ((link->cur_link_settings.lane_count != LANE_COUNT_UNKNOWN) ||
1601 (link->type == dc_connection_mst_branch) ||
4562236b
HW		 1602 is_dp_active_dongle(link))
1603 return true;
1604
1605 return false;
1606}
1607
d0778ebf 1608static bool handle_hpd_irq_psr_sink(const struct dc_link *link)
4562236b
HW		 1609{
1610 union dpcd_psr_configuration psr_configuration;
1611
94267b3d 1612 if (!link->psr_enabled)
4562236b
HW		 1613 return false;
1614
7c7f5b15
AG		 1615 dm_helpers_dp_read_dpcd(
1616 link->ctx,
d0778ebf 1617 link,
7c7f5b15
AG		 1618 368,/*DpcdAddress_PSR_Enable_Cfg*/
1619 &psr_configuration.raw,
1620 sizeof(psr_configuration.raw));
1621
4562236b
HW		 1622
1623 if (psr_configuration.bits.ENABLE) {
1624 unsigned char dpcdbuf[3] = {0};
1625 union psr_error_status psr_error_status;
1626 union psr_sink_psr_status psr_sink_psr_status;
1627
7c7f5b15
AG		 1628 dm_helpers_dp_read_dpcd(
1629 link->ctx,
d0778ebf 1630 link,
7c7f5b15
AG		 1631 0x2006, /*DpcdAddress_PSR_Error_Status*/
1632 (unsigned char *) dpcdbuf,
1633 sizeof(dpcdbuf));
4562236b
HW		 1634
1635 /*DPCD 2006h ERROR STATUS*/
1636 psr_error_status.raw = dpcdbuf[0];
1637 /*DPCD 2008h SINK PANEL SELF REFRESH STATUS*/
1638 psr_sink_psr_status.raw = dpcdbuf[2];
1639
1640 if (psr_error_status.bits.LINK_CRC_ERROR ||
1641 psr_error_status.bits.RFB_STORAGE_ERROR) {
1642 /* Acknowledge and clear error bits */
7c7f5b15
AG		 1643 dm_helpers_dp_write_dpcd(
1644 link->ctx,
d0778ebf 1645 link,
7c7f5b15 1646 8198,/*DpcdAddress_PSR_Error_Status*/
4562236b
HW		 1647 &psr_error_status.raw,
1648 sizeof(psr_error_status.raw));
1649
1650 /* PSR error, disable and re-enable PSR */
d0778ebf
HW		 1651 dc_link_set_psr_enable(link, false);
1652 dc_link_set_psr_enable(link, true);
4562236b
HW		 1653
1654 return true;
1655 } else if (psr_sink_psr_status.bits.SINK_SELF_REFRESH_STATUS ==
1656 PSR_SINK_STATE_ACTIVE_DISPLAY_FROM_SINK_RFB){
1657 /* No error is detect, PSR is active.
1658 * We should return with IRQ_HPD handled without
1659 * checking for loss of sync since PSR would have
1660 * powered down main link.
1661 */
1662 return true;
1663 }
1664 }
1665 return false;
1666}
1667
d0778ebf 1668static void dp_test_send_link_training(struct dc_link *link)
4562236b 1669{
73c72602 1670 struct dc_link_settings link_settings = {0};
4562236b
HW		 1671
1672 core_link_read_dpcd(
1673 link,
3a340294 1674 DP_TEST_LANE_COUNT,
4562236b
HW		 1675 (unsigned char *)(&link_settings.lane_count),
1676 1);
1677 core_link_read_dpcd(
1678 link,
3a340294 1679 DP_TEST_LINK_RATE,
4562236b
HW		 1680 (unsigned char *)(&link_settings.link_rate),
1681 1);
1682
1683 /* Set preferred link settings */
d0778ebf
HW		 1684 link->verified_link_cap.lane_count = link_settings.lane_count;
1685 link->verified_link_cap.link_rate = link_settings.link_rate;
4562236b 1686
73c72602 1687 dp_retrain_link_dp_test(link, &link_settings, false);
4562236b
HW		 1688}
1689
d0778ebf 1690static void dp_test_send_phy_test_pattern(struct dc_link *link)
4562236b
HW		 1691{
1692 union phy_test_pattern dpcd_test_pattern;
1693 union lane_adjust dpcd_lane_adjustment[2];
1694 unsigned char dpcd_post_cursor_2_adjustment = 0;
1695 unsigned char test_80_bit_pattern[
3a340294
DA		 1696 (DP_TEST_80BIT_CUSTOM_PATTERN_79_72 -
1697 DP_TEST_80BIT_CUSTOM_PATTERN_7_0)+1] = {0};
4562236b
HW		 1698 enum dp_test_pattern test_pattern;
1699 struct dc_link_training_settings link_settings;
1700 union lane_adjust dpcd_lane_adjust;
1701 unsigned int lane;
1702 struct link_training_settings link_training_settings;
1703 int i = 0;
1704
1705 dpcd_test_pattern.raw = 0;
1706 memset(dpcd_lane_adjustment, 0, sizeof(dpcd_lane_adjustment));
1707 memset(&link_settings, 0, sizeof(link_settings));
1708
1709 /* get phy test pattern and pattern parameters from DP receiver */
1710 core_link_read_dpcd(
1711 link,
3a340294 1712 DP_TEST_PHY_PATTERN,
4562236b
HW		 1713 &dpcd_test_pattern.raw,
1714 sizeof(dpcd_test_pattern));
1715 core_link_read_dpcd(
1716 link,
3a340294 1717 DP_ADJUST_REQUEST_LANE0_1,
4562236b
HW		 1718 &dpcd_lane_adjustment[0].raw,
1719 sizeof(dpcd_lane_adjustment));
1720
1721 /*get post cursor 2 parameters
1722 * For DP 1.1a or eariler, this DPCD register's value is 0
1723 * For DP 1.2 or later:
1724 * Bits 1:0 = POST_CURSOR2_LANE0; Bits 3:2 = POST_CURSOR2_LANE1
1725 * Bits 5:4 = POST_CURSOR2_LANE2; Bits 7:6 = POST_CURSOR2_LANE3
1726 */
1727 core_link_read_dpcd(
1728 link,
3a340294 1729 DP_ADJUST_REQUEST_POST_CURSOR2,
4562236b
HW		 1730 &dpcd_post_cursor_2_adjustment,
1731 sizeof(dpcd_post_cursor_2_adjustment));
1732
1733 /* translate request */
1734 switch (dpcd_test_pattern.bits.PATTERN) {
1735 case PHY_TEST_PATTERN_D10_2:
1736 test_pattern = DP_TEST_PATTERN_D102;
0e19401f 1737 break;
4562236b
HW		 1738 case PHY_TEST_PATTERN_SYMBOL_ERROR:
1739 test_pattern = DP_TEST_PATTERN_SYMBOL_ERROR;
0e19401f 1740 break;
4562236b
HW		 1741 case PHY_TEST_PATTERN_PRBS7:
1742 test_pattern = DP_TEST_PATTERN_PRBS7;
0e19401f 1743 break;
4562236b
HW		 1744 case PHY_TEST_PATTERN_80BIT_CUSTOM:
1745 test_pattern = DP_TEST_PATTERN_80BIT_CUSTOM;
0e19401f
TC		 1746 break;
1747 case PHY_TEST_PATTERN_CP2520_1:
1748 test_pattern = DP_TEST_PATTERN_CP2520_1;
1749 break;
1750 case PHY_TEST_PATTERN_CP2520_2:
1751 test_pattern = DP_TEST_PATTERN_CP2520_2;
1752 break;
1753 case PHY_TEST_PATTERN_CP2520_3:
1754 test_pattern = DP_TEST_PATTERN_CP2520_3;
1755 break;
4562236b
HW		 1756 default:
1757 test_pattern = DP_TEST_PATTERN_VIDEO_MODE;
1758 break;
1759 }
1760
1761 if (test_pattern == DP_TEST_PATTERN_80BIT_CUSTOM)
1762 core_link_read_dpcd(
1763 link,
3a340294 1764 DP_TEST_80BIT_CUSTOM_PATTERN_7_0,
4562236b
HW		 1765 test_80_bit_pattern,
1766 sizeof(test_80_bit_pattern));
1767
1768 /* prepare link training settings */
d0778ebf 1769 link_settings.link = link->cur_link_settings;
4562236b
HW		 1770
1771 for (lane = 0; lane <
d0778ebf 1772 (unsigned int)(link->cur_link_settings.lane_count);
4562236b
HW		 1773 lane++) {
1774 dpcd_lane_adjust.raw =
1775 get_nibble_at_index(&dpcd_lane_adjustment[0].raw, lane);
1776 link_settings.lane_settings[lane].VOLTAGE_SWING =
1777 (enum dc_voltage_swing)
1778 (dpcd_lane_adjust.bits.VOLTAGE_SWING_LANE);
1779 link_settings.lane_settings[lane].PRE_EMPHASIS =
1780 (enum dc_pre_emphasis)
1781 (dpcd_lane_adjust.bits.PRE_EMPHASIS_LANE);
1782 link_settings.lane_settings[lane].POST_CURSOR2 =
1783 (enum dc_post_cursor2)
1784 ((dpcd_post_cursor_2_adjustment >> (lane * 2)) & 0x03);
1785 }
1786
1787 for (i = 0; i < 4; i++)
1788 link_training_settings.lane_settings[i] =
1789 link_settings.lane_settings[i];
1790 link_training_settings.link_settings = link_settings.link;
1791 link_training_settings.allow_invalid_msa_timing_param = false;
1792 /*Usage: Measure DP physical lane signal
1793 * by DP SI test equipment automatically.
1794 * PHY test pattern request is generated by equipment via HPD interrupt.
1795 * HPD needs to be active all the time. HPD should be active
1796 * all the time. Do not touch it.
1797 * forward request to DS
1798 */
1799 dc_link_dp_set_test_pattern(
d0778ebf 1800 link,
4562236b
HW		 1801 test_pattern,
1802 &link_training_settings,
1803 test_80_bit_pattern,
3a340294
DA		 1804 (DP_TEST_80BIT_CUSTOM_PATTERN_79_72 -
1805 DP_TEST_80BIT_CUSTOM_PATTERN_7_0)+1);
4562236b
HW		 1806}
1807
d0778ebf 1808static void dp_test_send_link_test_pattern(struct dc_link *link)
4562236b
HW		 1809{
1810 union link_test_pattern dpcd_test_pattern;
1811 union test_misc dpcd_test_params;
1812 enum dp_test_pattern test_pattern;
1813
1814 memset(&dpcd_test_pattern, 0, sizeof(dpcd_test_pattern));
1815 memset(&dpcd_test_params, 0, sizeof(dpcd_test_params));
1816
1817 /* get link test pattern and pattern parameters */
1818 core_link_read_dpcd(
1819 link,
3a340294 1820 DP_TEST_PATTERN,
4562236b
HW		 1821 &dpcd_test_pattern.raw,
1822 sizeof(dpcd_test_pattern));
1823 core_link_read_dpcd(
1824 link,
3a340294 1825 DP_TEST_MISC0,
4562236b
HW		 1826 &dpcd_test_params.raw,
1827 sizeof(dpcd_test_params));
1828
1829 switch (dpcd_test_pattern.bits.PATTERN) {
1830 case LINK_TEST_PATTERN_COLOR_RAMP:
1831 test_pattern = DP_TEST_PATTERN_COLOR_RAMP;
1832 break;
1833 case LINK_TEST_PATTERN_VERTICAL_BARS:
1834 test_pattern = DP_TEST_PATTERN_VERTICAL_BARS;
1835 break; /* black and white */
1836 case LINK_TEST_PATTERN_COLOR_SQUARES:
1837 test_pattern = (dpcd_test_params.bits.DYN_RANGE ==
1838 TEST_DYN_RANGE_VESA ?
1839 DP_TEST_PATTERN_COLOR_SQUARES :
1840 DP_TEST_PATTERN_COLOR_SQUARES_CEA);
1841 break;
1842 default:
1843 test_pattern = DP_TEST_PATTERN_VIDEO_MODE;
1844 break;
1845 }
1846
1847 dc_link_dp_set_test_pattern(
d0778ebf 1848 link,
4562236b
HW		 1849 test_pattern,
1850 NULL,
1851 NULL,
1852 0);
1853}
1854
d0778ebf 1855static void handle_automated_test(struct dc_link *link)
4562236b
HW		 1856{
1857 union test_request test_request;
1858 union test_response test_response;
1859
1860 memset(&test_request, 0, sizeof(test_request));
1861 memset(&test_response, 0, sizeof(test_response));
1862
1863 core_link_read_dpcd(
1864 link,
3a340294 1865 DP_TEST_REQUEST,
4562236b
HW		 1866 &test_request.raw,
1867 sizeof(union test_request));
1868 if (test_request.bits.LINK_TRAINING) {
1869 /* ACK first to let DP RX test box monitor LT sequence */
1870 test_response.bits.ACK = 1;
1871 core_link_write_dpcd(
1872 link,
3a340294 1873 DP_TEST_RESPONSE,
4562236b
HW		 1874 &test_response.raw,
1875 sizeof(test_response));
1876 dp_test_send_link_training(link);
1877 /* no acknowledge request is needed again */
1878 test_response.bits.ACK = 0;
1879 }
1880 if (test_request.bits.LINK_TEST_PATTRN) {
1881 dp_test_send_link_test_pattern(link);
75a74755 1882 test_response.bits.ACK = 1;
4562236b
HW		 1883 }
1884 if (test_request.bits.PHY_TEST_PATTERN) {
1885 dp_test_send_phy_test_pattern(link);
1886 test_response.bits.ACK = 1;
1887 }
1888 if (!test_request.raw)
1889 /* no requests, revert all test signals
1890 * TODO: revert all test signals
1891 */
1892 test_response.bits.ACK = 1;
1893 /* send request acknowledgment */
1894 if (test_response.bits.ACK)
1895 core_link_write_dpcd(
1896 link,
3a340294 1897 DP_TEST_RESPONSE,
4562236b
HW		 1898 &test_response.raw,
1899 sizeof(test_response));
1900}
1901
d0778ebf 1902bool dc_link_handle_hpd_rx_irq(struct dc_link *link, union hpd_irq_data *out_hpd_irq_dpcd_data)
4562236b 1903{
4562236b 1904 union hpd_irq_data hpd_irq_dpcd_data = {{{{0}}}};
c2e218dd 1905 union device_service_irq device_service_clear = { { 0 } };
4562236b
HW		 1906 enum dc_status result = DDC_RESULT_UNKNOWN;
1907 bool status = false;
1908 /* For use cases related to down stream connection status change,
1909 * PSR and device auto test, refer to function handle_sst_hpd_irq
1910 * in DAL2.1*/
1911
1912 dm_logger_write(link->ctx->logger, LOG_HW_HPD_IRQ,
1913 "%s: Got short pulse HPD on link %d\n",
d0778ebf 1914 __func__, link->link_index);
4562236b 1915
8ee65d7c 1916
4562236b
HW		 1917 /* All the "handle_hpd_irq_xxx()" methods
1918 * should be called only after
1919 * dal_dpsst_ls_read_hpd_irq_data
1920 * Order of calls is important too
1921 */
1922 result = read_hpd_rx_irq_data(link, &hpd_irq_dpcd_data);
8ee65d7c
WL		 1923 if (out_hpd_irq_dpcd_data)
1924 *out_hpd_irq_dpcd_data = hpd_irq_dpcd_data;
4562236b
HW		 1925
1926 if (result != DC_OK) {
1927 dm_logger_write(link->ctx->logger, LOG_HW_HPD_IRQ,
1928 "%s: DPCD read failed to obtain irq data\n",
1929 __func__);
1930 return false;
1931 }
1932
1933 if (hpd_irq_dpcd_data.bytes.device_service_irq.bits.AUTOMATED_TEST) {
1934 device_service_clear.bits.AUTOMATED_TEST = 1;
1935 core_link_write_dpcd(
1936 link,
3a340294 1937 DP_DEVICE_SERVICE_IRQ_VECTOR,
4562236b
HW		 1938 &device_service_clear.raw,
1939 sizeof(device_service_clear.raw));
1940 device_service_clear.raw = 0;
1941 handle_automated_test(link);
1942 return false;
1943 }
1944
1945 if (!allow_hpd_rx_irq(link)) {
1946 dm_logger_write(link->ctx->logger, LOG_HW_HPD_IRQ,
1947 "%s: skipping HPD handling on %d\n",
d0778ebf 1948 __func__, link->link_index);
4562236b
HW		 1949 return false;
1950 }
1951
1952 if (handle_hpd_irq_psr_sink(link))
1953 /* PSR-related error was detected and handled */
1954 return true;
1955
1956 /* If PSR-related error handled, Main link may be off,
1957 * so do not handle as a normal sink status change interrupt.
1958 */
1959
1960 /* check if we have MST msg and return since we poll for it */
1961 if (hpd_irq_dpcd_data.bytes.device_service_irq.
1962 bits.DOWN_REP_MSG_RDY ||
1963 hpd_irq_dpcd_data.bytes.device_service_irq.
1964 bits.UP_REQ_MSG_RDY)
1965 return false;
1966
1967 /* For now we only handle 'Downstream port status' case.
1968 * If we got sink count changed it means
1969 * Downstream port status changed,
1970 * then DM should call DC to do the detection. */
1971 if (hpd_rx_irq_check_link_loss_status(
1972 link,
1973 &hpd_irq_dpcd_data)) {
1974 /* Connectivity log: link loss */
1975 CONN_DATA_LINK_LOSS(link,
1976 hpd_irq_dpcd_data.raw,
1977 sizeof(hpd_irq_dpcd_data),
1978 "Status: ");
1979
1980 perform_link_training_with_retries(link,
d0778ebf 1981 &link->cur_link_settings,
4562236b
HW		 1982 true, LINK_TRAINING_ATTEMPTS);
1983
1984 status = false;
1985 }
1986
d0778ebf 1987 if (link->type == dc_connection_active_dongle &&
4562236b
HW		 1988 hpd_irq_dpcd_data.bytes.sink_cnt.bits.SINK_COUNT
1989 != link->dpcd_sink_count)
1990 status = true;
1991
1992 /* reasons for HPD RX:
1993 * 1. Link Loss - ie Re-train the Link
1994 * 2. MST sideband message
1995 * 3. Automated Test - ie. Internal Commit
1996 * 4. CP (copy protection) - (not interesting for DM???)
1997 * 5. DRR
1998 * 6. Downstream Port status changed
1999 * -ie. Detect - this the only one
2000 * which is interesting for DM because
2001 * it must call dc_link_detect.
2002 */
2003 return status;
2004}
2005
2006/*query dpcd for version and mst cap addresses*/
d0778ebf 2007bool is_mst_supported(struct dc_link *link)
4562236b
HW		 2008{
2009 bool mst = false;
2010 enum dc_status st = DC_OK;
2011 union dpcd_rev rev;
2012 union mstm_cap cap;
2013
2014 rev.raw = 0;
2015 cap.raw = 0;
2016
3a340294 2017 st = core_link_read_dpcd(link, DP_DPCD_REV, &rev.raw,
4562236b
HW		 2018 sizeof(rev));
2019
2020 if (st == DC_OK && rev.raw >= DPCD_REV_12) {
2021
3a340294 2022 st = core_link_read_dpcd(link, DP_MSTM_CAP,
4562236b
HW		 2023 &cap.raw, sizeof(cap));
2024 if (st == DC_OK && cap.bits.MST_CAP == 1)
2025 mst = true;
2026 }
2027 return mst;
2028
2029}
2030
d0778ebf 2031bool is_dp_active_dongle(const struct dc_link *link)
4562236b
HW		 2032{
2033 enum display_dongle_type dongle_type = link->dpcd_caps.dongle_type;
2034
2035 return (dongle_type == DISPLAY_DONGLE_DP_VGA_CONVERTER) ||
2036 (dongle_type == DISPLAY_DONGLE_DP_DVI_CONVERTER) ||
2037 (dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER);
2038}
2039
2040static void get_active_converter_info(
d0778ebf 2041 uint8_t data, struct dc_link *link)
4562236b
HW		 2042{
2043 union dp_downstream_port_present ds_port = { .byte = data };
2044
2045 /* decode converter info*/
2046 if (!ds_port.fields.PORT_PRESENT) {
2047 link->dpcd_caps.dongle_type = DISPLAY_DONGLE_NONE;
d0778ebf 2048 ddc_service_set_dongle_type(link->ddc,
4562236b
HW		 2049 link->dpcd_caps.dongle_type);
2050 return;
2051 }
2052
2053 switch (ds_port.fields.PORT_TYPE) {
2054 case DOWNSTREAM_VGA:
2055 link->dpcd_caps.dongle_type = DISPLAY_DONGLE_DP_VGA_CONVERTER;
2056 break;
2057 case DOWNSTREAM_DVI_HDMI:
2058 /* At this point we don't know is it DVI or HDMI,
2059 * assume DVI.*/
2060 link->dpcd_caps.dongle_type = DISPLAY_DONGLE_DP_DVI_CONVERTER;
2061 break;
2062 default:
2063 link->dpcd_caps.dongle_type = DISPLAY_DONGLE_NONE;
2064 break;
2065 }
2066
ac0e562c 2067 if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_11) {
4562236b
HW		 2068 uint8_t det_caps[4];
2069 union dwnstream_port_caps_byte0 *port_caps =
2070 (union dwnstream_port_caps_byte0 *)det_caps;
3a340294 2071 core_link_read_dpcd(link, DP_DOWNSTREAM_PORT_0,
4562236b
HW		 2072 det_caps, sizeof(det_caps));
2073
2074 switch (port_caps->bits.DWN_STRM_PORTX_TYPE) {
2075 case DOWN_STREAM_DETAILED_VGA:
2076 link->dpcd_caps.dongle_type =
2077 DISPLAY_DONGLE_DP_VGA_CONVERTER;
2078 break;
2079 case DOWN_STREAM_DETAILED_DVI:
2080 link->dpcd_caps.dongle_type =
2081 DISPLAY_DONGLE_DP_DVI_CONVERTER;
2082 break;
2083 case DOWN_STREAM_DETAILED_HDMI:
2084 link->dpcd_caps.dongle_type =
2085 DISPLAY_DONGLE_DP_HDMI_CONVERTER;
2086
03f5c686 2087 link->dpcd_caps.dongle_caps.dongle_type = link->dpcd_caps.dongle_type;
4562236b
HW		 2088 if (ds_port.fields.DETAILED_CAPS) {
2089
2090 union dwnstream_port_caps_byte3_hdmi
2091 hdmi_caps = {.raw = det_caps[3] };
03f5c686
CL		 2092 union dwnstream_port_caps_byte1
2093 hdmi_color_caps = {.raw = det_caps[2] };
2094 link->dpcd_caps.dongle_caps.dp_hdmi_max_pixel_clk =
2095 det_caps[1] * 25000;
4562236b 2096
03f5c686 2097 link->dpcd_caps.dongle_caps.is_dp_hdmi_s3d_converter =
4562236b 2098 hdmi_caps.bits.FRAME_SEQ_TO_FRAME_PACK;
03f5c686
CL		 2099 link->dpcd_caps.dongle_caps.is_dp_hdmi_ycbcr422_pass_through =
2100 hdmi_caps.bits.YCrCr422_PASS_THROUGH;
2101 link->dpcd_caps.dongle_caps.is_dp_hdmi_ycbcr420_pass_through =
2102 hdmi_caps.bits.YCrCr420_PASS_THROUGH;
2103 link->dpcd_caps.dongle_caps.is_dp_hdmi_ycbcr422_converter =
2104 hdmi_caps.bits.YCrCr422_CONVERSION;
2105 link->dpcd_caps.dongle_caps.is_dp_hdmi_ycbcr420_converter =
2106 hdmi_caps.bits.YCrCr420_CONVERSION;
2107
2108 link->dpcd_caps.dongle_caps.dp_hdmi_max_bpc =
2109 hdmi_color_caps.bits.MAX_BITS_PER_COLOR_COMPONENT;
2110
2111 link->dpcd_caps.dongle_caps.extendedCapValid = true;
4562236b 2112 }
03f5c686 2113
4562236b
HW		 2114 break;
2115 }
2116 }
2117
d0778ebf 2118 ddc_service_set_dongle_type(link->ddc, link->dpcd_caps.dongle_type);
4562236b
HW		 2119
2120 {
2121 struct dp_device_vendor_id dp_id;
2122
2123 /* read IEEE branch device id */
2124 core_link_read_dpcd(
2125 link,
3a340294 2126 DP_BRANCH_OUI,
4562236b
HW		 2127 (uint8_t *)&dp_id,
2128 sizeof(dp_id));
2129
2130 link->dpcd_caps.branch_dev_id =
2131 (dp_id.ieee_oui[0] << 16) +
2132 (dp_id.ieee_oui[1] << 8) +
2133 dp_id.ieee_oui[2];
2134
2135 memmove(
2136 link->dpcd_caps.branch_dev_name,
2137 dp_id.ieee_device_id,
2138 sizeof(dp_id.ieee_device_id));
2139 }
2140
2141 {
2142 struct dp_sink_hw_fw_revision dp_hw_fw_revision;
2143
2144 core_link_read_dpcd(
2145 link,
3a340294 2146 DP_BRANCH_REVISION_START,
4562236b
HW		 2147 (uint8_t *)&dp_hw_fw_revision,
2148 sizeof(dp_hw_fw_revision));
2149
2150 link->dpcd_caps.branch_hw_revision =
2151 dp_hw_fw_revision.ieee_hw_rev;
2152 }
2153}
2154
d0778ebf 2155static void dp_wa_power_up_0010FA(struct dc_link *link, uint8_t *dpcd_data,
4562236b
HW		 2156 int length)
2157{
2158 int retry = 0;
2159 union dp_downstream_port_present ds_port = { 0 };
2160
2161 if (!link->dpcd_caps.dpcd_rev.raw) {
2162 do {
2163 dp_receiver_power_ctrl(link, true);
3a340294 2164 core_link_read_dpcd(link, DP_DPCD_REV,
4562236b
HW		 2165 dpcd_data, length);
2166 link->dpcd_caps.dpcd_rev.raw = dpcd_data[
3a340294
DA		 2167 DP_DPCD_REV -
2168 DP_DPCD_REV];
4562236b
HW		 2169 } while (retry++ < 4 && !link->dpcd_caps.dpcd_rev.raw);
2170 }
2171
3a340294
DA		 2172 ds_port.byte = dpcd_data[DP_DOWNSTREAMPORT_PRESENT -
2173 DP_DPCD_REV];
4562236b
HW		 2174
2175 if (link->dpcd_caps.dongle_type == DISPLAY_DONGLE_DP_VGA_CONVERTER) {
2176 switch (link->dpcd_caps.branch_dev_id) {
2177 /* Some active dongles (DP-VGA, DP-DLDVI converters) power down
2178 * all internal circuits including AUX communication preventing
2179 * reading DPCD table and EDID (spec violation).
2180 * Encoder will skip DP RX power down on disable_output to
2181 * keep receiver powered all the time.*/
2182 case DP_BRANCH_DEVICE_ID_1:
2183 case DP_BRANCH_DEVICE_ID_4:
2184 link->wa_flags.dp_keep_receiver_powered = true;
2185 break;
2186
2187 /* TODO: May need work around for other dongles. */
2188 default:
2189 link->wa_flags.dp_keep_receiver_powered = false;
2190 break;
2191 }
2192 } else
2193 link->wa_flags.dp_keep_receiver_powered = false;
2194}
2195
d0778ebf 2196static void retrieve_link_cap(struct dc_link *link)
4562236b 2197{
3a340294 2198 uint8_t dpcd_data[DP_TRAINING_AUX_RD_INTERVAL - DP_DPCD_REV + 1];
4562236b
HW		 2199
2200 union down_stream_port_count down_strm_port_count;
2201 union edp_configuration_cap edp_config_cap;
2202 union dp_downstream_port_present ds_port = { 0 };
2203
2204 memset(dpcd_data, '\0', sizeof(dpcd_data));
2205 memset(&down_strm_port_count,
2206 '\0', sizeof(union down_stream_port_count));
2207 memset(&edp_config_cap, '\0',
2208 sizeof(union edp_configuration_cap));
2209
2210 core_link_read_dpcd(
2211 link,
3a340294 2212 DP_DPCD_REV,
4562236b
HW		 2213 dpcd_data,
2214 sizeof(dpcd_data));
2215
4562236b
HW		 2216 {
2217 union training_aux_rd_interval aux_rd_interval;
2218
2219 aux_rd_interval.raw =
3a340294 2220 dpcd_data[DP_TRAINING_AUX_RD_INTERVAL];
4562236b
HW		 2221
2222 if (aux_rd_interval.bits.EXT_RECIEVER_CAP_FIELD_PRESENT == 1) {
2223 core_link_read_dpcd(
2224 link,
3a340294 2225 DP_DP13_DPCD_REV,
4562236b
HW		 2226 dpcd_data,
2227 sizeof(dpcd_data));
2228 }
2229 }
2230
cc04bf7e
TC		 2231 link->dpcd_caps.dpcd_rev.raw =
2232 dpcd_data[DP_DPCD_REV - DP_DPCD_REV];
2233
3a340294
DA		 2234 ds_port.byte = dpcd_data[DP_DOWNSTREAMPORT_PRESENT -
2235 DP_DPCD_REV];
4562236b
HW		 2236
2237 get_active_converter_info(ds_port.byte, link);
2238
2239 dp_wa_power_up_0010FA(link, dpcd_data, sizeof(dpcd_data));
2240
2241 link->dpcd_caps.allow_invalid_MSA_timing_param =
2242 down_strm_port_count.bits.IGNORE_MSA_TIMING_PARAM;
2243
2244 link->dpcd_caps.max_ln_count.raw = dpcd_data[
3a340294 2245 DP_MAX_LANE_COUNT - DP_DPCD_REV];
4562236b
HW		 2246
2247 link->dpcd_caps.max_down_spread.raw = dpcd_data[
3a340294 2248 DP_MAX_DOWNSPREAD - DP_DPCD_REV];
4562236b 2249
d0778ebf 2250 link->reported_link_cap.lane_count =
4562236b 2251 link->dpcd_caps.max_ln_count.bits.MAX_LANE_COUNT;
d0778ebf 2252 link->reported_link_cap.link_rate = dpcd_data[
3a340294 2253 DP_MAX_LINK_RATE - DP_DPCD_REV];
d0778ebf 2254 link->reported_link_cap.link_spread =
4562236b
HW		 2255 link->dpcd_caps.max_down_spread.bits.MAX_DOWN_SPREAD ?
2256 LINK_SPREAD_05_DOWNSPREAD_30KHZ : LINK_SPREAD_DISABLED;
2257
2258 edp_config_cap.raw = dpcd_data[
3a340294 2259 DP_EDP_CONFIGURATION_CAP - DP_DPCD_REV];
4562236b
HW		 2260 link->dpcd_caps.panel_mode_edp =
2261 edp_config_cap.bits.ALT_SCRAMBLER_RESET;
2262
d0778ebf
HW		 2263 link->test_pattern_enabled = false;
2264 link->compliance_test_state.raw = 0;
4562236b 2265
4562236b
HW		 2266 /* read sink count */
2267 core_link_read_dpcd(link,
3a340294 2268 DP_SINK_COUNT,
4562236b
HW		 2269 &link->dpcd_caps.sink_count.raw,
2270 sizeof(link->dpcd_caps.sink_count.raw));
2271
4562236b
HW		 2272 /* Connectivity log: detection */
2273 CONN_DATA_DETECT(link, dpcd_data, sizeof(dpcd_data), "Rx Caps: ");
4562236b
HW		 2274}
2275
d0778ebf 2276void detect_dp_sink_caps(struct dc_link *link)
4562236b
HW		 2277{
2278 retrieve_link_cap(link);
2279
2280 /* dc init_hw has power encoder using default
2281 * signal for connector. For native DP, no
2282 * need to power up encoder again. If not native
2283 * DP, hw_init may need check signal or power up
2284 * encoder here.
2285 */
2286
2287 if (is_mst_supported(link)) {
d0778ebf 2288 link->verified_link_cap = link->reported_link_cap;
4562236b
HW		 2289 } else {
2290 dp_hbr_verify_link_cap(link,
d0778ebf 2291 &link->reported_link_cap);
4562236b
HW		 2292 }
2293 /* TODO save sink caps in link->sink */
2294}
2295
4654a2f7
RL		 2296void detect_edp_sink_caps(struct dc_link *link)
2297{
2298 retrieve_link_cap(link);
2299 link->verified_link_cap = link->reported_link_cap;
2300}
2301
4562236b
HW		 2302void dc_link_dp_enable_hpd(const struct dc_link *link)
2303{
d0778ebf 2304 struct link_encoder *encoder = link->link_enc;
4562236b
HW		 2305
2306 if (encoder != NULL && encoder->funcs->enable_hpd != NULL)
2307 encoder->funcs->enable_hpd(encoder);
2308}
2309
2310void dc_link_dp_disable_hpd(const struct dc_link *link)
2311{
d0778ebf 2312 struct link_encoder *encoder = link->link_enc;
4562236b
HW		 2313
2314 if (encoder != NULL && encoder->funcs->enable_hpd != NULL)
2315 encoder->funcs->disable_hpd(encoder);
2316}
2317
2318static bool is_dp_phy_pattern(enum dp_test_pattern test_pattern)
2319{
0e19401f
TC		 2320 if ((DP_TEST_PATTERN_PHY_PATTERN_BEGIN <= test_pattern &&
2321 test_pattern <= DP_TEST_PATTERN_PHY_PATTERN_END) ||
2322 test_pattern == DP_TEST_PATTERN_VIDEO_MODE)
4562236b
HW		 2323 return true;
2324 else
2325 return false;
2326}
2327
d0778ebf 2328static void set_crtc_test_pattern(struct dc_link *link,
4562236b
HW		 2329 struct pipe_ctx *pipe_ctx,
2330 enum dp_test_pattern test_pattern)
2331{
2332 enum controller_dp_test_pattern controller_test_pattern;
2333 enum dc_color_depth color_depth = pipe_ctx->
4fa086b9 2334 stream->timing.display_color_depth;
4562236b
HW		 2335 struct bit_depth_reduction_params params;
2336
2337 memset(&params, 0, sizeof(params));
2338
2339 switch (test_pattern) {
2340 case DP_TEST_PATTERN_COLOR_SQUARES:
2341 controller_test_pattern =
2342 CONTROLLER_DP_TEST_PATTERN_COLORSQUARES;
2343 break;
2344 case DP_TEST_PATTERN_COLOR_SQUARES_CEA:
2345 controller_test_pattern =
2346 CONTROLLER_DP_TEST_PATTERN_COLORSQUARES_CEA;
2347 break;
2348 case DP_TEST_PATTERN_VERTICAL_BARS:
2349 controller_test_pattern =
2350 CONTROLLER_DP_TEST_PATTERN_VERTICALBARS;
2351 break;
2352 case DP_TEST_PATTERN_HORIZONTAL_BARS:
2353 controller_test_pattern =
2354 CONTROLLER_DP_TEST_PATTERN_HORIZONTALBARS;
2355 break;
2356 case DP_TEST_PATTERN_COLOR_RAMP:
2357 controller_test_pattern =
2358 CONTROLLER_DP_TEST_PATTERN_COLORRAMP;
2359 break;
2360 default:
2361 controller_test_pattern =
2362 CONTROLLER_DP_TEST_PATTERN_VIDEOMODE;
2363 break;
2364 }
2365
2366 switch (test_pattern) {
2367 case DP_TEST_PATTERN_COLOR_SQUARES:
2368 case DP_TEST_PATTERN_COLOR_SQUARES_CEA:
2369 case DP_TEST_PATTERN_VERTICAL_BARS:
2370 case DP_TEST_PATTERN_HORIZONTAL_BARS:
2371 case DP_TEST_PATTERN_COLOR_RAMP:
2372 {
2373 /* disable bit depth reduction */
2374 pipe_ctx->stream->bit_depth_params = params;
2375 pipe_ctx->opp->funcs->
2376 opp_program_bit_depth_reduction(pipe_ctx->opp, &params);
2377
2378 pipe_ctx->tg->funcs->set_test_pattern(pipe_ctx->tg,
2379 controller_test_pattern, color_depth);
2380 }
2381 break;
2382 case DP_TEST_PATTERN_VIDEO_MODE:
2383 {
2384 /* restore bitdepth reduction */
529cad0f 2385 resource_build_bit_depth_reduction_params(pipe_ctx->stream,
4562236b
HW		 2386 &params);
2387 pipe_ctx->stream->bit_depth_params = params;
2388 pipe_ctx->opp->funcs->
2389 opp_program_bit_depth_reduction(pipe_ctx->opp, &params);
2390
2391 pipe_ctx->tg->funcs->set_test_pattern(pipe_ctx->tg,
2392 CONTROLLER_DP_TEST_PATTERN_VIDEOMODE,
2393 color_depth);
2394 }
2395 break;
2396
2397 default:
2398 break;
2399 }
2400}
2401
2402bool dc_link_dp_set_test_pattern(
d0778ebf 2403 struct dc_link *link,
4562236b
HW		 2404 enum dp_test_pattern test_pattern,
2405 const struct link_training_settings *p_link_settings,
2406 const unsigned char *p_custom_pattern,
2407 unsigned int cust_pattern_size)
2408{
d0778ebf 2409 struct pipe_ctx *pipes = link->dc->current_context->res_ctx.pipe_ctx;
4562236b
HW		 2410 struct pipe_ctx pipe_ctx = pipes[0];
2411 unsigned int lane;
2412 unsigned int i;
2413 unsigned char link_qual_pattern[LANE_COUNT_DP_MAX] = {0};
2414 union dpcd_training_pattern training_pattern;
4562236b
HW		 2415 enum dpcd_phy_test_patterns pattern;
2416
2417 memset(&training_pattern, 0, sizeof(training_pattern));
4562236b
HW		 2418
2419 for (i = 0; i < MAX_PIPES; i++) {
d0778ebf 2420 if (pipes[i].stream->sink->link == link) {
4562236b
HW		 2421 pipe_ctx = pipes[i];
2422 break;
2423 }
2424 }
2425
2426 /* Reset CRTC Test Pattern if it is currently running and request
2427 * is VideoMode Reset DP Phy Test Pattern if it is currently running
2428 * and request is VideoMode
2429 */
d0778ebf 2430 if (link->test_pattern_enabled && test_pattern ==
4562236b
HW		 2431 DP_TEST_PATTERN_VIDEO_MODE) {
2432 /* Set CRTC Test Pattern */
d0778ebf
HW		 2433 set_crtc_test_pattern(link, &pipe_ctx, test_pattern);
2434 dp_set_hw_test_pattern(link, test_pattern,
4562236b
HW		 2435 (uint8_t *)p_custom_pattern,
2436 (uint32_t)cust_pattern_size);
2437
2438 /* Unblank Stream */
d0778ebf 2439 link->dc->hwss.unblank_stream(
4562236b 2440 &pipe_ctx,
d0778ebf 2441 &link->verified_link_cap);
4562236b
HW		 2442 /* TODO:m_pHwss->MuteAudioEndpoint
2443 * (pPathMode->pDisplayPath, false);
2444 */
2445
2446 /* Reset Test Pattern state */
d0778ebf 2447 link->test_pattern_enabled = false;
4562236b
HW		 2448
2449 return true;
2450 }
2451
2452 /* Check for PHY Test Patterns */
2453 if (is_dp_phy_pattern(test_pattern)) {
2454 /* Set DPCD Lane Settings before running test pattern */
2455 if (p_link_settings != NULL) {
d0778ebf
HW		 2456 dp_set_hw_lane_settings(link, p_link_settings);
2457 dpcd_set_lane_settings(link, p_link_settings);
4562236b
HW		 2458 }
2459
2460 /* Blank stream if running test pattern */
2461 if (test_pattern != DP_TEST_PATTERN_VIDEO_MODE) {
2462 /*TODO:
2463 * m_pHwss->
2464 * MuteAudioEndpoint(pPathMode->pDisplayPath, true);
2465 */
2466 /* Blank stream */
2467 pipes->stream_enc->funcs->dp_blank(pipe_ctx.stream_enc);
2468 }
2469
d0778ebf 2470 dp_set_hw_test_pattern(link, test_pattern,
4562236b
HW		 2471 (uint8_t *)p_custom_pattern,
2472 (uint32_t)cust_pattern_size);
2473
2474 if (test_pattern != DP_TEST_PATTERN_VIDEO_MODE) {
2475 /* Set Test Pattern state */
d0778ebf 2476 link->test_pattern_enabled = true;
4562236b 2477 if (p_link_settings != NULL)
d0778ebf 2478 dpcd_set_link_settings(link,
4562236b
HW		 2479 p_link_settings);
2480 }
2481
2482 switch (test_pattern) {
2483 case DP_TEST_PATTERN_VIDEO_MODE:
2484 pattern = PHY_TEST_PATTERN_NONE;
0e19401f 2485 break;
4562236b
HW		 2486 case DP_TEST_PATTERN_D102:
2487 pattern = PHY_TEST_PATTERN_D10_2;
0e19401f 2488 break;
4562236b
HW		 2489 case DP_TEST_PATTERN_SYMBOL_ERROR:
2490 pattern = PHY_TEST_PATTERN_SYMBOL_ERROR;
0e19401f 2491 break;
4562236b
HW		 2492 case DP_TEST_PATTERN_PRBS7:
2493 pattern = PHY_TEST_PATTERN_PRBS7;
0e19401f 2494 break;
4562236b
HW		 2495 case DP_TEST_PATTERN_80BIT_CUSTOM:
2496 pattern = PHY_TEST_PATTERN_80BIT_CUSTOM;
0e19401f
TC		 2497 break;
2498 case DP_TEST_PATTERN_CP2520_1:
2499 pattern = PHY_TEST_PATTERN_CP2520_1;
2500 break;
2501 case DP_TEST_PATTERN_CP2520_2:
2502 pattern = PHY_TEST_PATTERN_CP2520_2;
2503 break;
2504 case DP_TEST_PATTERN_CP2520_3:
2505 pattern = PHY_TEST_PATTERN_CP2520_3;
2506 break;
4562236b
HW		 2507 default:
2508 return false;
2509 }
2510
2511 if (test_pattern == DP_TEST_PATTERN_VIDEO_MODE
2512 /*TODO:&& !pPathMode->pDisplayPath->IsTargetPoweredOn()*/)
2513 return false;
2514
d0778ebf 2515 if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_12) {
4562236b
HW		 2516 /* tell receiver that we are sending qualification
2517 * pattern DP 1.2 or later - DP receiver's link quality
2518 * pattern is set using DPCD LINK_QUAL_LANEx_SET
2519 * register (0x10B~0x10E)\
2520 */
2521 for (lane = 0; lane < LANE_COUNT_DP_MAX; lane++)
2522 link_qual_pattern[lane] =
2523 (unsigned char)(pattern);
2524
d0778ebf 2525 core_link_write_dpcd(link,
3a340294 2526 DP_LINK_QUAL_LANE0_SET,
4562236b
HW		 2527 link_qual_pattern,
2528 sizeof(link_qual_pattern));
d0778ebf
HW		 2529 } else if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_10 ||
2530 link->dpcd_caps.dpcd_rev.raw == 0) {
4562236b
HW		 2531 /* tell receiver that we are sending qualification
2532 * pattern DP 1.1a or earlier - DP receiver's link
2533 * quality pattern is set using
2534 * DPCD TRAINING_PATTERN_SET -> LINK_QUAL_PATTERN_SET
2535 * register (0x102). We will use v_1.3 when we are
2536 * setting test pattern for DP 1.1.
2537 */
d0778ebf
HW		 2538 core_link_read_dpcd(link, DP_TRAINING_PATTERN_SET,
2539 &training_pattern.raw,
2540 sizeof(training_pattern));
4562236b 2541 training_pattern.v1_3.LINK_QUAL_PATTERN_SET = pattern;
d0778ebf
HW		 2542 core_link_write_dpcd(link, DP_TRAINING_PATTERN_SET,
2543 &training_pattern.raw,
2544 sizeof(training_pattern));
4562236b
HW		 2545 }
2546 } else {
2547 /* CRTC Patterns */
d0778ebf 2548 set_crtc_test_pattern(link, &pipe_ctx, test_pattern);
4562236b 2549 /* Set Test Pattern state */
d0778ebf 2550 link->test_pattern_enabled = true;
4562236b
HW		 2551 }
2552
2553 return true;
2554}
07c84c7a 2555
d0778ebf 2556void dp_enable_mst_on_sink(struct dc_link *link, bool enable)
07c84c7a
DW		 2557{
2558 unsigned char mstmCntl;
2559
2560 core_link_read_dpcd(link, DP_MSTM_CTRL, &mstmCntl, 1);
2561 if (enable)
2562 mstmCntl |= DP_MST_EN;
2563 else
2564 mstmCntl &= (~DP_MST_EN);
2565
2566 core_link_write_dpcd(link, DP_MSTM_CTRL, &mstmCntl, 1);
2567}
ubuntu-bionic-kernel mirror