[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / amd / display / dc / inc / hw_sequencer.h

/*
 * Copyright 2015 Advanced Micro Devices, Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 * Authors: AMD
 *
 */

#ifndef __DC_HW_SEQUENCER_H__
#define __DC_HW_SEQUENCER_H__
#include "core_types.h"
#include "timing_generator.h"

enum pipe_gating_control {
	PIPE_GATING_CONTROL_DISABLE = 0,
	PIPE_GATING_CONTROL_ENABLE,
	PIPE_GATING_CONTROL_INIT
};

struct dce_hwseq_wa {
	bool blnd_crtc_trigger;
};

struct dce_hwseq {
	struct dc_context *ctx;
	const struct dce_hwseq_registers *regs;
	const struct dce_hwseq_shift *shifts;
	const struct dce_hwseq_mask *masks;
	struct dce_hwseq_wa wa;
};


struct hw_sequencer_funcs {

	void (*init_hw)(struct core_dc *dc);

	enum dc_status (*apply_ctx_to_hw)(
			struct core_dc *dc, struct validate_context *context);

	void (*reset_hw_ctx_wrap)(
			struct core_dc *dc, struct validate_context *context);

	void (*apply_ctx_for_surface)(
			struct core_dc *dc,
			const struct dc_stream_state *stream,
			int num_planes,
			struct validate_context *context);

	void (*set_plane_config)(
			const struct core_dc *dc,
			struct pipe_ctx *pipe_ctx,
			struct resource_context *res_ctx);

	void (*program_gamut_remap)(
			struct pipe_ctx *pipe_ctx);

	void (*program_csc_matrix)(
			struct pipe_ctx *pipe_ctx,
			enum dc_color_space colorspace,
			uint16_t *matrix);

	void (*update_plane_addr)(
		const struct core_dc *dc,
		struct pipe_ctx *pipe_ctx);

	void (*update_dchub)(
		struct dce_hwseq *hws,
		struct dchub_init_data *dh_data);

	void (*update_pending_status)(
			struct pipe_ctx *pipe_ctx);

	bool (*set_input_transfer_func)(
				struct pipe_ctx *pipe_ctx,
				const struct dc_plane_state *plane_state);

	bool (*set_output_transfer_func)(
				struct pipe_ctx *pipe_ctx,
				const struct dc_stream_state *stream);

	void (*power_down)(struct core_dc *dc);

	void (*enable_accelerated_mode)(struct core_dc *dc);

	void (*enable_timing_synchronization)(
			struct core_dc *dc,
			int group_index,
			int group_size,
			struct pipe_ctx *grouped_pipes[]);

	void (*enable_display_pipe_clock_gating)(
					struct dc_context *ctx,
					bool clock_gating);

	bool (*enable_display_power_gating)(
					struct core_dc *dc,
					uint8_t controller_id,
					struct dc_bios *dcb,
					enum pipe_gating_control power_gating);

	void (*power_down_front_end)(struct core_dc *dc, int fe_idx);

	void (*power_on_front_end)(struct core_dc *dc,
			struct pipe_ctx *pipe,
			struct validate_context *context);

	void (*update_info_frame)(struct pipe_ctx *pipe_ctx);

	void (*enable_stream)(struct pipe_ctx *pipe_ctx);

	void (*disable_stream)(struct pipe_ctx *pipe_ctx);

	void (*unblank_stream)(struct pipe_ctx *pipe_ctx,
			struct dc_link_settings *link_settings);

	void (*pipe_control_lock)(
				struct core_dc *dc,
				struct pipe_ctx *pipe,
				bool lock);

	void (*set_bandwidth)(
			struct core_dc *dc,
			struct validate_context *context,
			bool decrease_allowed);

	void (*set_drr)(struct pipe_ctx **pipe_ctx, int num_pipes,
			int vmin, int vmax);

	void (*get_position)(struct pipe_ctx **pipe_ctx, int num_pipes,
			struct crtc_position *position);

	void (*set_static_screen_control)(struct pipe_ctx **pipe_ctx,
			int num_pipes, const struct dc_static_screen_events *events);

	enum dc_status (*prog_pixclk_crtc_otg)(
			struct pipe_ctx *pipe_ctx,
			struct validate_context *context,
			struct core_dc *dc);

	void (*setup_stereo)(
			struct pipe_ctx *pipe_ctx,
			struct core_dc *dc);

	void (*set_avmute)(struct pipe_ctx *pipe_ctx, bool enable);

	void (*log_hw_state)(struct core_dc *dc);

	void (*wait_for_mpcc_disconnect)(struct core_dc *dc,
			struct resource_pool *res_pool,
			struct pipe_ctx *pipe_ctx);
};

void color_space_to_black_color(
	const struct core_dc *dc,
	enum dc_color_space colorspace,
	struct tg_color *black_color);

bool hwss_wait_for_blank_complete(
		struct timing_generator *tg);

#endif /* __DC_HW_SEQUENCER_H__ */
Commit	Line	Data
4562236b HW	1	/*
	2	* Copyright 2015 Advanced Micro Devices, Inc.
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice shall be included in
	12	* all copies or substantial portions of the Software.
	13	*
	14	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	15	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	16	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	17	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
	18	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	19	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	20	* OTHER DEALINGS IN THE SOFTWARE.
	21	*
	22	* Authors: AMD
	23	*
	24	*/
	25
	26	#ifndef __DC_HW_SEQUENCER_H__
	27	#define __DC_HW_SEQUENCER_H__
	28	#include "core_types.h"
	29	#include "timing_generator.h"
	30
4562236b HW	31	enum pipe_gating_control {
	32	PIPE_GATING_CONTROL_DISABLE = 0,
	33	PIPE_GATING_CONTROL_ENABLE,
	34	PIPE_GATING_CONTROL_INIT
	35	};
	36
f0828115 CL	37	struct dce_hwseq_wa {
	38	bool blnd_crtc_trigger;
	39	};
	40
	41	struct dce_hwseq {
	42	struct dc_context *ctx;
	43	const struct dce_hwseq_registers *regs;
	44	const struct dce_hwseq_shift *shifts;
	45	const struct dce_hwseq_mask *masks;
	46	struct dce_hwseq_wa wa;
4562236b HW	47	};
4562236b HW	48
4562236b HW	49
	50	struct hw_sequencer_funcs {
	51
	52	void (init_hw)(struct core_dc dc);
	53
	54	enum dc_status (*apply_ctx_to_hw)(
	55	struct core_dc dc, struct validate_context context);
	56
	57	void (*reset_hw_ctx_wrap)(
	58	struct core_dc dc, struct validate_context context);
	59
4562236b HW	60	void (*apply_ctx_for_surface)(
4562236b HW	61	struct core_dc *dc,
3e9ad616 EY	62	const struct dc_stream_state *stream,
3e9ad616 EY	63	int num_planes,
4562236b HW	64	struct validate_context *context);
	65
	66	void (*set_plane_config)(
	67	const struct core_dc *dc,
	68	struct pipe_ctx *pipe_ctx,
	69	struct resource_context *res_ctx);
	70
1bf56e62 ZF	71	void (*program_gamut_remap)(
	72	struct pipe_ctx *pipe_ctx);
	73
abe07e80 YHL	74	void (*program_csc_matrix)(
	75	struct pipe_ctx *pipe_ctx,
	76	enum dc_color_space colorspace,
	77	uint16_t *matrix);
	78
4562236b HW	79	void (*update_plane_addr)(
	80	const struct core_dc *dc,
	81	struct pipe_ctx *pipe_ctx);
	82
08b16886 ZF	83	void (*update_dchub)(
	84	struct dce_hwseq *hws,
	85	struct dchub_init_data *dh_data);
	86
4562236b HW	87	void (*update_pending_status)(
	88	struct pipe_ctx *pipe_ctx);
	89
90e508ba	90	bool (*set_input_transfer_func)(
fb735a9f	91	struct pipe_ctx *pipe_ctx,
3be5262e	92	const struct dc_plane_state *plane_state);
4562236b	93
90e508ba AK	94	bool (*set_output_transfer_func)(
90e508ba AK	95	struct pipe_ctx *pipe_ctx,
0971c40e	96	const struct dc_stream_state *stream);
90e508ba	97
4562236b HW	98	void (power_down)(struct core_dc dc);
	99
	100	void (enable_accelerated_mode)(struct core_dc dc);
	101
	102	void (*enable_timing_synchronization)(
	103	struct core_dc *dc,
	104	int group_index,
	105	int group_size,
	106	struct pipe_ctx *grouped_pipes[]);
	107
4562236b HW	108	void (*enable_display_pipe_clock_gating)(
	109	struct dc_context *ctx,
	110	bool clock_gating);
	111
	112	bool (*enable_display_power_gating)(
	113	struct core_dc *dc,
	114	uint8_t controller_id,
	115	struct dc_bios *dcb,
	116	enum pipe_gating_control power_gating);
	117
cfe4645e	118	void (power_down_front_end)(struct core_dc dc, int fe_idx);
18f7a1e4 YS	119
	120	void (power_on_front_end)(struct core_dc dc,
	121	struct pipe_ctx *pipe,
	122	struct validate_context *context);
	123
4562236b HW	124	void (update_info_frame)(struct pipe_ctx pipe_ctx);
	125
	126	void (enable_stream)(struct pipe_ctx pipe_ctx);
	127
	128	void (disable_stream)(struct pipe_ctx pipe_ctx);
	129
	130	void (unblank_stream)(struct pipe_ctx pipe_ctx,
	131	struct dc_link_settings *link_settings);
	132
	133	void (*pipe_control_lock)(
f0828115 CL	134	struct core_dc *dc,
f0828115 CL	135	struct pipe_ctx *pipe,
4562236b HW	136	bool lock);
4562236b HW	137
cf437593 DL	138	void (*set_bandwidth)(
	139	struct core_dc *dc,
	140	struct validate_context *context,
	141	bool decrease_allowed);
4562236b HW	142
	143	void (set_drr)(struct pipe_ctx *pipe_ctx, int num_pipes,
	144	int vmin, int vmax);
	145
72ada5f7 EC	146	void (get_position)(struct pipe_ctx *pipe_ctx, int num_pipes,
	147	struct crtc_position *position);
	148
4562236b	149	void (set_static_screen_control)(struct pipe_ctx *pipe_ctx,
94267b3d	150	int num_pipes, const struct dc_static_screen_events *events);
4562236b HW	151
	152	enum dc_status (*prog_pixclk_crtc_otg)(
	153	struct pipe_ctx *pipe_ctx,
	154	struct validate_context *context,
	155	struct core_dc *dc);
9edba557 VP	156
	157	void (*setup_stereo)(
	158	struct pipe_ctx *pipe_ctx,
	159	struct core_dc *dc);
15e17335 CL	160
15e17335 CL	161	void (set_avmute)(struct pipe_ctx pipe_ctx, bool enable);
6d244be8 TC	162
6d244be8 TC	163	void (log_hw_state)(struct core_dc dc);
87480687	164
6be425f3 EY	165	void (wait_for_mpcc_disconnect)(struct core_dc dc,
	166	struct resource_pool *res_pool,
	167	struct pipe_ctx *pipe_ctx);
4562236b HW	168	};
	169
	170	void color_space_to_black_color(
	171	const struct core_dc *dc,
	172	enum dc_color_space colorspace,
	173	struct tg_color *black_color);
	174
4b5e7d62 HW	175	bool hwss_wait_for_blank_complete(
	176	struct timing_generator *tg);
	177
4562236b	178	#endif /* __DC_HW_SEQUENCER_H__ */