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Commit | Line | Data |
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96f60e37 RK |
1 | /* |
2 | * Copyright (C) 2012 Russell King | |
3 | * Rewritten from the dovefb driver, and Armada510 manuals. | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License version 2 as | |
7 | * published by the Free Software Foundation. | |
8 | */ | |
9 | #include <linux/clk.h> | |
10 | #include <drm/drmP.h> | |
11 | #include <drm/drm_crtc_helper.h> | |
12 | #include "armada_crtc.h" | |
13 | #include "armada_drm.h" | |
14 | #include "armada_fb.h" | |
15 | #include "armada_gem.h" | |
16 | #include "armada_hw.h" | |
17 | ||
18 | struct armada_frame_work { | |
19 | struct drm_pending_vblank_event *event; | |
20 | struct armada_regs regs[4]; | |
21 | struct drm_framebuffer *old_fb; | |
22 | }; | |
23 | ||
24 | enum csc_mode { | |
25 | CSC_AUTO = 0, | |
26 | CSC_YUV_CCIR601 = 1, | |
27 | CSC_YUV_CCIR709 = 2, | |
28 | CSC_RGB_COMPUTER = 1, | |
29 | CSC_RGB_STUDIO = 2, | |
30 | }; | |
31 | ||
32 | /* | |
33 | * A note about interlacing. Let's consider HDMI 1920x1080i. | |
34 | * The timing parameters we have from X are: | |
35 | * Hact HsyA HsyI Htot Vact VsyA VsyI Vtot | |
36 | * 1920 2448 2492 2640 1080 1084 1094 1125 | |
37 | * Which get translated to: | |
38 | * Hact HsyA HsyI Htot Vact VsyA VsyI Vtot | |
39 | * 1920 2448 2492 2640 540 542 547 562 | |
40 | * | |
41 | * This is how it is defined by CEA-861-D - line and pixel numbers are | |
42 | * referenced to the rising edge of VSYNC and HSYNC. Total clocks per | |
43 | * line: 2640. The odd frame, the first active line is at line 21, and | |
44 | * the even frame, the first active line is 584. | |
45 | * | |
46 | * LN: 560 561 562 563 567 568 569 | |
47 | * DE: ~~~|____________________________//__________________________ | |
48 | * HSYNC: ____|~|_____|~|_____|~|_____|~|_//__|~|_____|~|_____|~|_____ | |
49 | * VSYNC: _________________________|~~~~~~//~~~~~~~~~~~~~~~|__________ | |
50 | * 22 blanking lines. VSYNC at 1320 (referenced to the HSYNC rising edge). | |
51 | * | |
52 | * LN: 1123 1124 1125 1 5 6 7 | |
53 | * DE: ~~~|____________________________//__________________________ | |
54 | * HSYNC: ____|~|_____|~|_____|~|_____|~|_//__|~|_____|~|_____|~|_____ | |
55 | * VSYNC: ____________________|~~~~~~~~~~~//~~~~~~~~~~|_______________ | |
56 | * 23 blanking lines | |
57 | * | |
58 | * The Armada LCD Controller line and pixel numbers are, like X timings, | |
59 | * referenced to the top left of the active frame. | |
60 | * | |
61 | * So, translating these to our LCD controller: | |
62 | * Odd frame, 563 total lines, VSYNC at line 543-548, pixel 1128. | |
63 | * Even frame, 562 total lines, VSYNC at line 542-547, pixel 2448. | |
64 | * Note: Vsync front porch remains constant! | |
65 | * | |
66 | * if (odd_frame) { | |
67 | * vtotal = mode->crtc_vtotal + 1; | |
68 | * vbackporch = mode->crtc_vsync_start - mode->crtc_vdisplay + 1; | |
69 | * vhorizpos = mode->crtc_hsync_start - mode->crtc_htotal / 2 | |
70 | * } else { | |
71 | * vtotal = mode->crtc_vtotal; | |
72 | * vbackporch = mode->crtc_vsync_start - mode->crtc_vdisplay; | |
73 | * vhorizpos = mode->crtc_hsync_start; | |
74 | * } | |
75 | * vfrontporch = mode->crtc_vtotal - mode->crtc_vsync_end; | |
76 | * | |
77 | * So, we need to reprogram these registers on each vsync event: | |
78 | * LCD_SPU_V_PORCH, LCD_SPU_ADV_REG, LCD_SPUT_V_H_TOTAL | |
79 | * | |
80 | * Note: we do not use the frame done interrupts because these appear | |
81 | * to happen too early, and lead to jitter on the display (presumably | |
82 | * they occur at the end of the last active line, before the vsync back | |
83 | * porch, which we're reprogramming.) | |
84 | */ | |
85 | ||
86 | void | |
87 | armada_drm_crtc_update_regs(struct armada_crtc *dcrtc, struct armada_regs *regs) | |
88 | { | |
89 | while (regs->offset != ~0) { | |
90 | void __iomem *reg = dcrtc->base + regs->offset; | |
91 | uint32_t val; | |
92 | ||
93 | val = regs->mask; | |
94 | if (val != 0) | |
95 | val &= readl_relaxed(reg); | |
96 | writel_relaxed(val | regs->val, reg); | |
97 | ++regs; | |
98 | } | |
99 | } | |
100 | ||
101 | #define dpms_blanked(dpms) ((dpms) != DRM_MODE_DPMS_ON) | |
102 | ||
103 | static void armada_drm_crtc_update(struct armada_crtc *dcrtc) | |
104 | { | |
105 | uint32_t dumb_ctrl; | |
106 | ||
107 | dumb_ctrl = dcrtc->cfg_dumb_ctrl; | |
108 | ||
109 | if (!dpms_blanked(dcrtc->dpms)) | |
110 | dumb_ctrl |= CFG_DUMB_ENA; | |
111 | ||
112 | /* | |
113 | * When the dumb interface isn't in DUMB24_RGB888_0 mode, it might | |
114 | * be using SPI or GPIO. If we set this to DUMB_BLANK, we will | |
115 | * force LCD_D[23:0] to output blank color, overriding the GPIO or | |
116 | * SPI usage. So leave it as-is unless in DUMB24_RGB888_0 mode. | |
117 | */ | |
118 | if (dpms_blanked(dcrtc->dpms) && | |
119 | (dumb_ctrl & DUMB_MASK) == DUMB24_RGB888_0) { | |
120 | dumb_ctrl &= ~DUMB_MASK; | |
121 | dumb_ctrl |= DUMB_BLANK; | |
122 | } | |
123 | ||
124 | /* | |
125 | * The documentation doesn't indicate what the normal state of | |
126 | * the sync signals are. Sebastian Hesselbart kindly probed | |
127 | * these signals on his board to determine their state. | |
128 | * | |
129 | * The non-inverted state of the sync signals is active high. | |
130 | * Setting these bits makes the appropriate signal active low. | |
131 | */ | |
132 | if (dcrtc->crtc.mode.flags & DRM_MODE_FLAG_NCSYNC) | |
133 | dumb_ctrl |= CFG_INV_CSYNC; | |
134 | if (dcrtc->crtc.mode.flags & DRM_MODE_FLAG_NHSYNC) | |
135 | dumb_ctrl |= CFG_INV_HSYNC; | |
136 | if (dcrtc->crtc.mode.flags & DRM_MODE_FLAG_NVSYNC) | |
137 | dumb_ctrl |= CFG_INV_VSYNC; | |
138 | ||
139 | if (dcrtc->dumb_ctrl != dumb_ctrl) { | |
140 | dcrtc->dumb_ctrl = dumb_ctrl; | |
141 | writel_relaxed(dumb_ctrl, dcrtc->base + LCD_SPU_DUMB_CTRL); | |
142 | } | |
143 | } | |
144 | ||
145 | static unsigned armada_drm_crtc_calc_fb(struct drm_framebuffer *fb, | |
146 | int x, int y, struct armada_regs *regs, bool interlaced) | |
147 | { | |
148 | struct armada_gem_object *obj = drm_fb_obj(fb); | |
149 | unsigned pitch = fb->pitches[0]; | |
150 | unsigned offset = y * pitch + x * fb->bits_per_pixel / 8; | |
151 | uint32_t addr_odd, addr_even; | |
152 | unsigned i = 0; | |
153 | ||
154 | DRM_DEBUG_DRIVER("pitch %u x %d y %d bpp %d\n", | |
155 | pitch, x, y, fb->bits_per_pixel); | |
156 | ||
157 | addr_odd = addr_even = obj->dev_addr + offset; | |
158 | ||
159 | if (interlaced) { | |
160 | addr_even += pitch; | |
161 | pitch *= 2; | |
162 | } | |
163 | ||
164 | /* write offset, base, and pitch */ | |
165 | armada_reg_queue_set(regs, i, addr_odd, LCD_CFG_GRA_START_ADDR0); | |
166 | armada_reg_queue_set(regs, i, addr_even, LCD_CFG_GRA_START_ADDR1); | |
167 | armada_reg_queue_mod(regs, i, pitch, 0xffff, LCD_CFG_GRA_PITCH); | |
168 | ||
169 | return i; | |
170 | } | |
171 | ||
172 | static int armada_drm_crtc_queue_frame_work(struct armada_crtc *dcrtc, | |
173 | struct armada_frame_work *work) | |
174 | { | |
175 | struct drm_device *dev = dcrtc->crtc.dev; | |
176 | unsigned long flags; | |
177 | int ret; | |
178 | ||
179 | ret = drm_vblank_get(dev, dcrtc->num); | |
180 | if (ret) { | |
181 | DRM_ERROR("failed to acquire vblank counter\n"); | |
182 | return ret; | |
183 | } | |
184 | ||
185 | spin_lock_irqsave(&dev->event_lock, flags); | |
186 | if (!dcrtc->frame_work) | |
187 | dcrtc->frame_work = work; | |
188 | else | |
189 | ret = -EBUSY; | |
190 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
191 | ||
192 | if (ret) | |
193 | drm_vblank_put(dev, dcrtc->num); | |
194 | ||
195 | return ret; | |
196 | } | |
197 | ||
198 | static void armada_drm_crtc_complete_frame_work(struct armada_crtc *dcrtc) | |
199 | { | |
200 | struct drm_device *dev = dcrtc->crtc.dev; | |
201 | struct armada_frame_work *work = dcrtc->frame_work; | |
202 | ||
203 | dcrtc->frame_work = NULL; | |
204 | ||
205 | armada_drm_crtc_update_regs(dcrtc, work->regs); | |
206 | ||
207 | if (work->event) | |
208 | drm_send_vblank_event(dev, dcrtc->num, work->event); | |
209 | ||
210 | drm_vblank_put(dev, dcrtc->num); | |
211 | ||
212 | /* Finally, queue the process-half of the cleanup. */ | |
213 | __armada_drm_queue_unref_work(dcrtc->crtc.dev, work->old_fb); | |
214 | kfree(work); | |
215 | } | |
216 | ||
217 | static void armada_drm_crtc_finish_fb(struct armada_crtc *dcrtc, | |
218 | struct drm_framebuffer *fb, bool force) | |
219 | { | |
220 | struct armada_frame_work *work; | |
221 | ||
222 | if (!fb) | |
223 | return; | |
224 | ||
225 | if (force) { | |
226 | /* Display is disabled, so just drop the old fb */ | |
227 | drm_framebuffer_unreference(fb); | |
228 | return; | |
229 | } | |
230 | ||
231 | work = kmalloc(sizeof(*work), GFP_KERNEL); | |
232 | if (work) { | |
233 | int i = 0; | |
234 | work->event = NULL; | |
235 | work->old_fb = fb; | |
236 | armada_reg_queue_end(work->regs, i); | |
237 | ||
238 | if (armada_drm_crtc_queue_frame_work(dcrtc, work) == 0) | |
239 | return; | |
240 | ||
241 | kfree(work); | |
242 | } | |
243 | ||
244 | /* | |
245 | * Oops - just drop the reference immediately and hope for | |
246 | * the best. The worst that will happen is the buffer gets | |
247 | * reused before it has finished being displayed. | |
248 | */ | |
249 | drm_framebuffer_unreference(fb); | |
250 | } | |
251 | ||
252 | static void armada_drm_vblank_off(struct armada_crtc *dcrtc) | |
253 | { | |
254 | struct drm_device *dev = dcrtc->crtc.dev; | |
255 | ||
256 | /* | |
257 | * Tell the DRM core that vblank IRQs aren't going to happen for | |
258 | * a while. This cleans up any pending vblank events for us. | |
259 | */ | |
260 | drm_vblank_off(dev, dcrtc->num); | |
261 | ||
262 | /* Handle any pending flip event. */ | |
263 | spin_lock_irq(&dev->event_lock); | |
264 | if (dcrtc->frame_work) | |
265 | armada_drm_crtc_complete_frame_work(dcrtc); | |
266 | spin_unlock_irq(&dev->event_lock); | |
267 | } | |
268 | ||
269 | void armada_drm_crtc_gamma_set(struct drm_crtc *crtc, u16 r, u16 g, u16 b, | |
270 | int idx) | |
271 | { | |
272 | } | |
273 | ||
274 | void armada_drm_crtc_gamma_get(struct drm_crtc *crtc, u16 *r, u16 *g, u16 *b, | |
275 | int idx) | |
276 | { | |
277 | } | |
278 | ||
279 | /* The mode_config.mutex will be held for this call */ | |
280 | static void armada_drm_crtc_dpms(struct drm_crtc *crtc, int dpms) | |
281 | { | |
282 | struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc); | |
283 | ||
284 | if (dcrtc->dpms != dpms) { | |
285 | dcrtc->dpms = dpms; | |
286 | armada_drm_crtc_update(dcrtc); | |
287 | if (dpms_blanked(dpms)) | |
288 | armada_drm_vblank_off(dcrtc); | |
289 | } | |
290 | } | |
291 | ||
292 | /* | |
293 | * Prepare for a mode set. Turn off overlay to ensure that we don't end | |
294 | * up with the overlay size being bigger than the active screen size. | |
295 | * We rely upon X refreshing this state after the mode set has completed. | |
296 | * | |
297 | * The mode_config.mutex will be held for this call | |
298 | */ | |
299 | static void armada_drm_crtc_prepare(struct drm_crtc *crtc) | |
300 | { | |
301 | struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc); | |
302 | struct drm_plane *plane; | |
303 | ||
304 | /* | |
305 | * If we have an overlay plane associated with this CRTC, disable | |
306 | * it before the modeset to avoid its coordinates being outside | |
307 | * the new mode parameters. DRM doesn't provide help with this. | |
308 | */ | |
309 | plane = dcrtc->plane; | |
310 | if (plane) { | |
311 | struct drm_framebuffer *fb = plane->fb; | |
312 | ||
313 | plane->funcs->disable_plane(plane); | |
314 | plane->fb = NULL; | |
315 | plane->crtc = NULL; | |
316 | drm_framebuffer_unreference(fb); | |
317 | } | |
318 | } | |
319 | ||
320 | /* The mode_config.mutex will be held for this call */ | |
321 | static void armada_drm_crtc_commit(struct drm_crtc *crtc) | |
322 | { | |
323 | struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc); | |
324 | ||
325 | if (dcrtc->dpms != DRM_MODE_DPMS_ON) { | |
326 | dcrtc->dpms = DRM_MODE_DPMS_ON; | |
327 | armada_drm_crtc_update(dcrtc); | |
328 | } | |
329 | } | |
330 | ||
331 | /* The mode_config.mutex will be held for this call */ | |
332 | static bool armada_drm_crtc_mode_fixup(struct drm_crtc *crtc, | |
333 | const struct drm_display_mode *mode, struct drm_display_mode *adj) | |
334 | { | |
96f60e37 RK |
335 | struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc); |
336 | int ret; | |
337 | ||
338 | /* We can't do interlaced modes if we don't have the SPU_ADV_REG */ | |
42e62ba7 | 339 | if (!dcrtc->variant->has_spu_adv_reg && |
96f60e37 RK |
340 | adj->flags & DRM_MODE_FLAG_INTERLACE) |
341 | return false; | |
342 | ||
343 | /* Check whether the display mode is possible */ | |
42e62ba7 | 344 | ret = dcrtc->variant->compute_clock(dcrtc, adj, NULL); |
96f60e37 RK |
345 | if (ret) |
346 | return false; | |
347 | ||
348 | return true; | |
349 | } | |
350 | ||
e5d9ddfb | 351 | static void armada_drm_crtc_irq(struct armada_crtc *dcrtc, u32 stat) |
96f60e37 RK |
352 | { |
353 | struct armada_vbl_event *e, *n; | |
354 | void __iomem *base = dcrtc->base; | |
355 | ||
356 | if (stat & DMA_FF_UNDERFLOW) | |
357 | DRM_ERROR("video underflow on crtc %u\n", dcrtc->num); | |
358 | if (stat & GRA_FF_UNDERFLOW) | |
359 | DRM_ERROR("graphics underflow on crtc %u\n", dcrtc->num); | |
360 | ||
361 | if (stat & VSYNC_IRQ) | |
362 | drm_handle_vblank(dcrtc->crtc.dev, dcrtc->num); | |
363 | ||
364 | spin_lock(&dcrtc->irq_lock); | |
365 | ||
366 | list_for_each_entry_safe(e, n, &dcrtc->vbl_list, node) { | |
367 | list_del_init(&e->node); | |
368 | drm_vblank_put(dcrtc->crtc.dev, dcrtc->num); | |
369 | e->fn(dcrtc, e->data); | |
370 | } | |
371 | ||
372 | if (stat & GRA_FRAME_IRQ && dcrtc->interlaced) { | |
373 | int i = stat & GRA_FRAME_IRQ0 ? 0 : 1; | |
374 | uint32_t val; | |
375 | ||
376 | writel_relaxed(dcrtc->v[i].spu_v_porch, base + LCD_SPU_V_PORCH); | |
377 | writel_relaxed(dcrtc->v[i].spu_v_h_total, | |
378 | base + LCD_SPUT_V_H_TOTAL); | |
379 | ||
380 | val = readl_relaxed(base + LCD_SPU_ADV_REG); | |
381 | val &= ~(ADV_VSYNC_L_OFF | ADV_VSYNC_H_OFF | ADV_VSYNCOFFEN); | |
382 | val |= dcrtc->v[i].spu_adv_reg; | |
662af0d8 | 383 | writel_relaxed(val, base + LCD_SPU_ADV_REG); |
96f60e37 | 384 | } |
662af0d8 RK |
385 | |
386 | if (stat & DUMB_FRAMEDONE && dcrtc->cursor_update) { | |
387 | writel_relaxed(dcrtc->cursor_hw_pos, | |
388 | base + LCD_SPU_HWC_OVSA_HPXL_VLN); | |
389 | writel_relaxed(dcrtc->cursor_hw_sz, | |
390 | base + LCD_SPU_HWC_HPXL_VLN); | |
391 | armada_updatel(CFG_HWC_ENA, | |
392 | CFG_HWC_ENA | CFG_HWC_1BITMOD | CFG_HWC_1BITENA, | |
393 | base + LCD_SPU_DMA_CTRL0); | |
394 | dcrtc->cursor_update = false; | |
395 | armada_drm_crtc_disable_irq(dcrtc, DUMB_FRAMEDONE_ENA); | |
396 | } | |
397 | ||
96f60e37 RK |
398 | spin_unlock(&dcrtc->irq_lock); |
399 | ||
400 | if (stat & GRA_FRAME_IRQ) { | |
401 | struct drm_device *dev = dcrtc->crtc.dev; | |
402 | ||
403 | spin_lock(&dev->event_lock); | |
404 | if (dcrtc->frame_work) | |
405 | armada_drm_crtc_complete_frame_work(dcrtc); | |
406 | spin_unlock(&dev->event_lock); | |
407 | ||
408 | wake_up(&dcrtc->frame_wait); | |
409 | } | |
410 | } | |
411 | ||
e5d9ddfb RK |
412 | static irqreturn_t armada_drm_irq(int irq, void *arg) |
413 | { | |
414 | struct armada_crtc *dcrtc = arg; | |
415 | u32 v, stat = readl_relaxed(dcrtc->base + LCD_SPU_IRQ_ISR); | |
416 | ||
417 | /* | |
418 | * This is rediculous - rather than writing bits to clear, we | |
419 | * have to set the actual status register value. This is racy. | |
420 | */ | |
421 | writel_relaxed(0, dcrtc->base + LCD_SPU_IRQ_ISR); | |
422 | ||
423 | /* Mask out those interrupts we haven't enabled */ | |
424 | v = stat & dcrtc->irq_ena; | |
425 | ||
426 | if (v & (VSYNC_IRQ|GRA_FRAME_IRQ|DUMB_FRAMEDONE)) { | |
427 | armada_drm_crtc_irq(dcrtc, stat); | |
428 | return IRQ_HANDLED; | |
429 | } | |
430 | return IRQ_NONE; | |
431 | } | |
432 | ||
96f60e37 RK |
433 | /* These are locked by dev->vbl_lock */ |
434 | void armada_drm_crtc_disable_irq(struct armada_crtc *dcrtc, u32 mask) | |
435 | { | |
436 | if (dcrtc->irq_ena & mask) { | |
437 | dcrtc->irq_ena &= ~mask; | |
438 | writel(dcrtc->irq_ena, dcrtc->base + LCD_SPU_IRQ_ENA); | |
439 | } | |
440 | } | |
441 | ||
442 | void armada_drm_crtc_enable_irq(struct armada_crtc *dcrtc, u32 mask) | |
443 | { | |
444 | if ((dcrtc->irq_ena & mask) != mask) { | |
445 | dcrtc->irq_ena |= mask; | |
446 | writel(dcrtc->irq_ena, dcrtc->base + LCD_SPU_IRQ_ENA); | |
447 | if (readl_relaxed(dcrtc->base + LCD_SPU_IRQ_ISR) & mask) | |
448 | writel(0, dcrtc->base + LCD_SPU_IRQ_ISR); | |
449 | } | |
450 | } | |
451 | ||
452 | static uint32_t armada_drm_crtc_calculate_csc(struct armada_crtc *dcrtc) | |
453 | { | |
454 | struct drm_display_mode *adj = &dcrtc->crtc.mode; | |
455 | uint32_t val = 0; | |
456 | ||
457 | if (dcrtc->csc_yuv_mode == CSC_YUV_CCIR709) | |
458 | val |= CFG_CSC_YUV_CCIR709; | |
459 | if (dcrtc->csc_rgb_mode == CSC_RGB_STUDIO) | |
460 | val |= CFG_CSC_RGB_STUDIO; | |
461 | ||
462 | /* | |
463 | * In auto mode, set the colorimetry, based upon the HDMI spec. | |
464 | * 1280x720p, 1920x1080p and 1920x1080i use ITU709, others use | |
465 | * ITU601. It may be more appropriate to set this depending on | |
466 | * the source - but what if the graphic frame is YUV and the | |
467 | * video frame is RGB? | |
468 | */ | |
469 | if ((adj->hdisplay == 1280 && adj->vdisplay == 720 && | |
470 | !(adj->flags & DRM_MODE_FLAG_INTERLACE)) || | |
471 | (adj->hdisplay == 1920 && adj->vdisplay == 1080)) { | |
472 | if (dcrtc->csc_yuv_mode == CSC_AUTO) | |
473 | val |= CFG_CSC_YUV_CCIR709; | |
474 | } | |
475 | ||
476 | /* | |
477 | * We assume we're connected to a TV-like device, so the YUV->RGB | |
478 | * conversion should produce a limited range. We should set this | |
479 | * depending on the connectors attached to this CRTC, and what | |
480 | * kind of device they report being connected. | |
481 | */ | |
482 | if (dcrtc->csc_rgb_mode == CSC_AUTO) | |
483 | val |= CFG_CSC_RGB_STUDIO; | |
484 | ||
485 | return val; | |
486 | } | |
487 | ||
488 | /* The mode_config.mutex will be held for this call */ | |
489 | static int armada_drm_crtc_mode_set(struct drm_crtc *crtc, | |
490 | struct drm_display_mode *mode, struct drm_display_mode *adj, | |
491 | int x, int y, struct drm_framebuffer *old_fb) | |
492 | { | |
96f60e37 RK |
493 | struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc); |
494 | struct armada_regs regs[17]; | |
495 | uint32_t lm, rm, tm, bm, val, sclk; | |
496 | unsigned long flags; | |
497 | unsigned i; | |
498 | bool interlaced; | |
499 | ||
f4510a27 | 500 | drm_framebuffer_reference(crtc->primary->fb); |
96f60e37 RK |
501 | |
502 | interlaced = !!(adj->flags & DRM_MODE_FLAG_INTERLACE); | |
503 | ||
f4510a27 MR |
504 | i = armada_drm_crtc_calc_fb(dcrtc->crtc.primary->fb, |
505 | x, y, regs, interlaced); | |
96f60e37 RK |
506 | |
507 | rm = adj->crtc_hsync_start - adj->crtc_hdisplay; | |
508 | lm = adj->crtc_htotal - adj->crtc_hsync_end; | |
509 | bm = adj->crtc_vsync_start - adj->crtc_vdisplay; | |
510 | tm = adj->crtc_vtotal - adj->crtc_vsync_end; | |
511 | ||
512 | DRM_DEBUG_DRIVER("H: %d %d %d %d lm %d rm %d\n", | |
513 | adj->crtc_hdisplay, | |
514 | adj->crtc_hsync_start, | |
515 | adj->crtc_hsync_end, | |
516 | adj->crtc_htotal, lm, rm); | |
517 | DRM_DEBUG_DRIVER("V: %d %d %d %d tm %d bm %d\n", | |
518 | adj->crtc_vdisplay, | |
519 | adj->crtc_vsync_start, | |
520 | adj->crtc_vsync_end, | |
521 | adj->crtc_vtotal, tm, bm); | |
522 | ||
523 | /* Wait for pending flips to complete */ | |
524 | wait_event(dcrtc->frame_wait, !dcrtc->frame_work); | |
525 | ||
526 | drm_vblank_pre_modeset(crtc->dev, dcrtc->num); | |
527 | ||
528 | crtc->mode = *adj; | |
529 | ||
530 | val = dcrtc->dumb_ctrl & ~CFG_DUMB_ENA; | |
531 | if (val != dcrtc->dumb_ctrl) { | |
532 | dcrtc->dumb_ctrl = val; | |
533 | writel_relaxed(val, dcrtc->base + LCD_SPU_DUMB_CTRL); | |
534 | } | |
535 | ||
536 | /* Now compute the divider for real */ | |
42e62ba7 | 537 | dcrtc->variant->compute_clock(dcrtc, adj, &sclk); |
96f60e37 RK |
538 | |
539 | /* Ensure graphic fifo is enabled */ | |
540 | armada_reg_queue_mod(regs, i, 0, CFG_PDWN64x66, LCD_SPU_SRAM_PARA1); | |
541 | armada_reg_queue_set(regs, i, sclk, LCD_CFG_SCLK_DIV); | |
542 | ||
543 | if (interlaced ^ dcrtc->interlaced) { | |
544 | if (adj->flags & DRM_MODE_FLAG_INTERLACE) | |
545 | drm_vblank_get(dcrtc->crtc.dev, dcrtc->num); | |
546 | else | |
547 | drm_vblank_put(dcrtc->crtc.dev, dcrtc->num); | |
548 | dcrtc->interlaced = interlaced; | |
549 | } | |
550 | ||
551 | spin_lock_irqsave(&dcrtc->irq_lock, flags); | |
552 | ||
553 | /* Even interlaced/progressive frame */ | |
554 | dcrtc->v[1].spu_v_h_total = adj->crtc_vtotal << 16 | | |
555 | adj->crtc_htotal; | |
556 | dcrtc->v[1].spu_v_porch = tm << 16 | bm; | |
557 | val = adj->crtc_hsync_start; | |
662af0d8 | 558 | dcrtc->v[1].spu_adv_reg = val << 20 | val | ADV_VSYNCOFFEN | |
42e62ba7 | 559 | dcrtc->variant->spu_adv_reg; |
96f60e37 RK |
560 | |
561 | if (interlaced) { | |
562 | /* Odd interlaced frame */ | |
563 | dcrtc->v[0].spu_v_h_total = dcrtc->v[1].spu_v_h_total + | |
564 | (1 << 16); | |
565 | dcrtc->v[0].spu_v_porch = dcrtc->v[1].spu_v_porch + 1; | |
566 | val = adj->crtc_hsync_start - adj->crtc_htotal / 2; | |
662af0d8 | 567 | dcrtc->v[0].spu_adv_reg = val << 20 | val | ADV_VSYNCOFFEN | |
42e62ba7 | 568 | dcrtc->variant->spu_adv_reg; |
96f60e37 RK |
569 | } else { |
570 | dcrtc->v[0] = dcrtc->v[1]; | |
571 | } | |
572 | ||
573 | val = adj->crtc_vdisplay << 16 | adj->crtc_hdisplay; | |
574 | ||
575 | armada_reg_queue_set(regs, i, val, LCD_SPU_V_H_ACTIVE); | |
576 | armada_reg_queue_set(regs, i, val, LCD_SPU_GRA_HPXL_VLN); | |
577 | armada_reg_queue_set(regs, i, val, LCD_SPU_GZM_HPXL_VLN); | |
578 | armada_reg_queue_set(regs, i, (lm << 16) | rm, LCD_SPU_H_PORCH); | |
579 | armada_reg_queue_set(regs, i, dcrtc->v[0].spu_v_porch, LCD_SPU_V_PORCH); | |
580 | armada_reg_queue_set(regs, i, dcrtc->v[0].spu_v_h_total, | |
581 | LCD_SPUT_V_H_TOTAL); | |
582 | ||
42e62ba7 | 583 | if (dcrtc->variant->has_spu_adv_reg) { |
96f60e37 RK |
584 | armada_reg_queue_mod(regs, i, dcrtc->v[0].spu_adv_reg, |
585 | ADV_VSYNC_L_OFF | ADV_VSYNC_H_OFF | | |
586 | ADV_VSYNCOFFEN, LCD_SPU_ADV_REG); | |
662af0d8 | 587 | } |
96f60e37 RK |
588 | |
589 | val = CFG_GRA_ENA | CFG_GRA_HSMOOTH; | |
f4510a27 MR |
590 | val |= CFG_GRA_FMT(drm_fb_to_armada_fb(dcrtc->crtc.primary->fb)->fmt); |
591 | val |= CFG_GRA_MOD(drm_fb_to_armada_fb(dcrtc->crtc.primary->fb)->mod); | |
96f60e37 | 592 | |
f4510a27 | 593 | if (drm_fb_to_armada_fb(dcrtc->crtc.primary->fb)->fmt > CFG_420) |
96f60e37 RK |
594 | val |= CFG_PALETTE_ENA; |
595 | ||
596 | if (interlaced) | |
597 | val |= CFG_GRA_FTOGGLE; | |
598 | ||
599 | armada_reg_queue_mod(regs, i, val, CFG_GRAFORMAT | | |
600 | CFG_GRA_MOD(CFG_SWAPRB | CFG_SWAPUV | | |
601 | CFG_SWAPYU | CFG_YUV2RGB) | | |
602 | CFG_PALETTE_ENA | CFG_GRA_FTOGGLE, | |
603 | LCD_SPU_DMA_CTRL0); | |
604 | ||
605 | val = adj->flags & DRM_MODE_FLAG_NVSYNC ? CFG_VSYNC_INV : 0; | |
606 | armada_reg_queue_mod(regs, i, val, CFG_VSYNC_INV, LCD_SPU_DMA_CTRL1); | |
607 | ||
608 | val = dcrtc->spu_iopad_ctrl | armada_drm_crtc_calculate_csc(dcrtc); | |
609 | armada_reg_queue_set(regs, i, val, LCD_SPU_IOPAD_CONTROL); | |
610 | armada_reg_queue_end(regs, i); | |
611 | ||
612 | armada_drm_crtc_update_regs(dcrtc, regs); | |
613 | spin_unlock_irqrestore(&dcrtc->irq_lock, flags); | |
614 | ||
615 | armada_drm_crtc_update(dcrtc); | |
616 | ||
617 | drm_vblank_post_modeset(crtc->dev, dcrtc->num); | |
618 | armada_drm_crtc_finish_fb(dcrtc, old_fb, dpms_blanked(dcrtc->dpms)); | |
619 | ||
620 | return 0; | |
621 | } | |
622 | ||
623 | /* The mode_config.mutex will be held for this call */ | |
624 | static int armada_drm_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y, | |
625 | struct drm_framebuffer *old_fb) | |
626 | { | |
627 | struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc); | |
628 | struct armada_regs regs[4]; | |
629 | unsigned i; | |
630 | ||
f4510a27 | 631 | i = armada_drm_crtc_calc_fb(crtc->primary->fb, crtc->x, crtc->y, regs, |
96f60e37 RK |
632 | dcrtc->interlaced); |
633 | armada_reg_queue_end(regs, i); | |
634 | ||
635 | /* Wait for pending flips to complete */ | |
636 | wait_event(dcrtc->frame_wait, !dcrtc->frame_work); | |
637 | ||
638 | /* Take a reference to the new fb as we're using it */ | |
f4510a27 | 639 | drm_framebuffer_reference(crtc->primary->fb); |
96f60e37 RK |
640 | |
641 | /* Update the base in the CRTC */ | |
642 | armada_drm_crtc_update_regs(dcrtc, regs); | |
643 | ||
644 | /* Drop our previously held reference */ | |
645 | armada_drm_crtc_finish_fb(dcrtc, old_fb, dpms_blanked(dcrtc->dpms)); | |
646 | ||
647 | return 0; | |
648 | } | |
649 | ||
650 | static void armada_drm_crtc_load_lut(struct drm_crtc *crtc) | |
651 | { | |
652 | } | |
653 | ||
654 | /* The mode_config.mutex will be held for this call */ | |
655 | static void armada_drm_crtc_disable(struct drm_crtc *crtc) | |
656 | { | |
657 | struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc); | |
658 | ||
659 | armada_drm_crtc_dpms(crtc, DRM_MODE_DPMS_OFF); | |
f4510a27 | 660 | armada_drm_crtc_finish_fb(dcrtc, crtc->primary->fb, true); |
96f60e37 RK |
661 | |
662 | /* Power down most RAMs and FIFOs */ | |
663 | writel_relaxed(CFG_PDWN256x32 | CFG_PDWN256x24 | CFG_PDWN256x8 | | |
664 | CFG_PDWN32x32 | CFG_PDWN16x66 | CFG_PDWN32x66 | | |
665 | CFG_PDWN64x66, dcrtc->base + LCD_SPU_SRAM_PARA1); | |
666 | } | |
667 | ||
668 | static const struct drm_crtc_helper_funcs armada_crtc_helper_funcs = { | |
669 | .dpms = armada_drm_crtc_dpms, | |
670 | .prepare = armada_drm_crtc_prepare, | |
671 | .commit = armada_drm_crtc_commit, | |
672 | .mode_fixup = armada_drm_crtc_mode_fixup, | |
673 | .mode_set = armada_drm_crtc_mode_set, | |
674 | .mode_set_base = armada_drm_crtc_mode_set_base, | |
675 | .load_lut = armada_drm_crtc_load_lut, | |
676 | .disable = armada_drm_crtc_disable, | |
677 | }; | |
678 | ||
662af0d8 RK |
679 | static void armada_load_cursor_argb(void __iomem *base, uint32_t *pix, |
680 | unsigned stride, unsigned width, unsigned height) | |
681 | { | |
682 | uint32_t addr; | |
683 | unsigned y; | |
684 | ||
685 | addr = SRAM_HWC32_RAM1; | |
686 | for (y = 0; y < height; y++) { | |
687 | uint32_t *p = &pix[y * stride]; | |
688 | unsigned x; | |
689 | ||
690 | for (x = 0; x < width; x++, p++) { | |
691 | uint32_t val = *p; | |
692 | ||
693 | val = (val & 0xff00ff00) | | |
694 | (val & 0x000000ff) << 16 | | |
695 | (val & 0x00ff0000) >> 16; | |
696 | ||
697 | writel_relaxed(val, | |
698 | base + LCD_SPU_SRAM_WRDAT); | |
699 | writel_relaxed(addr | SRAM_WRITE, | |
700 | base + LCD_SPU_SRAM_CTRL); | |
c39b0695 | 701 | readl_relaxed(base + LCD_SPU_HWC_OVSA_HPXL_VLN); |
662af0d8 RK |
702 | addr += 1; |
703 | if ((addr & 0x00ff) == 0) | |
704 | addr += 0xf00; | |
705 | if ((addr & 0x30ff) == 0) | |
706 | addr = SRAM_HWC32_RAM2; | |
707 | } | |
708 | } | |
709 | } | |
710 | ||
711 | static void armada_drm_crtc_cursor_tran(void __iomem *base) | |
712 | { | |
713 | unsigned addr; | |
714 | ||
715 | for (addr = 0; addr < 256; addr++) { | |
716 | /* write the default value */ | |
717 | writel_relaxed(0x55555555, base + LCD_SPU_SRAM_WRDAT); | |
718 | writel_relaxed(addr | SRAM_WRITE | SRAM_HWC32_TRAN, | |
719 | base + LCD_SPU_SRAM_CTRL); | |
720 | } | |
721 | } | |
722 | ||
723 | static int armada_drm_crtc_cursor_update(struct armada_crtc *dcrtc, bool reload) | |
724 | { | |
725 | uint32_t xoff, xscr, w = dcrtc->cursor_w, s; | |
726 | uint32_t yoff, yscr, h = dcrtc->cursor_h; | |
727 | uint32_t para1; | |
728 | ||
729 | /* | |
730 | * Calculate the visible width and height of the cursor, | |
731 | * screen position, and the position in the cursor bitmap. | |
732 | */ | |
733 | if (dcrtc->cursor_x < 0) { | |
734 | xoff = -dcrtc->cursor_x; | |
735 | xscr = 0; | |
736 | w -= min(xoff, w); | |
737 | } else if (dcrtc->cursor_x + w > dcrtc->crtc.mode.hdisplay) { | |
738 | xoff = 0; | |
739 | xscr = dcrtc->cursor_x; | |
740 | w = max_t(int, dcrtc->crtc.mode.hdisplay - dcrtc->cursor_x, 0); | |
741 | } else { | |
742 | xoff = 0; | |
743 | xscr = dcrtc->cursor_x; | |
744 | } | |
745 | ||
746 | if (dcrtc->cursor_y < 0) { | |
747 | yoff = -dcrtc->cursor_y; | |
748 | yscr = 0; | |
749 | h -= min(yoff, h); | |
750 | } else if (dcrtc->cursor_y + h > dcrtc->crtc.mode.vdisplay) { | |
751 | yoff = 0; | |
752 | yscr = dcrtc->cursor_y; | |
753 | h = max_t(int, dcrtc->crtc.mode.vdisplay - dcrtc->cursor_y, 0); | |
754 | } else { | |
755 | yoff = 0; | |
756 | yscr = dcrtc->cursor_y; | |
757 | } | |
758 | ||
759 | /* On interlaced modes, the vertical cursor size must be halved */ | |
760 | s = dcrtc->cursor_w; | |
761 | if (dcrtc->interlaced) { | |
762 | s *= 2; | |
763 | yscr /= 2; | |
764 | h /= 2; | |
765 | } | |
766 | ||
767 | if (!dcrtc->cursor_obj || !h || !w) { | |
768 | spin_lock_irq(&dcrtc->irq_lock); | |
769 | armada_drm_crtc_disable_irq(dcrtc, DUMB_FRAMEDONE_ENA); | |
770 | dcrtc->cursor_update = false; | |
771 | armada_updatel(0, CFG_HWC_ENA, dcrtc->base + LCD_SPU_DMA_CTRL0); | |
772 | spin_unlock_irq(&dcrtc->irq_lock); | |
773 | return 0; | |
774 | } | |
775 | ||
776 | para1 = readl_relaxed(dcrtc->base + LCD_SPU_SRAM_PARA1); | |
777 | armada_updatel(CFG_CSB_256x32, CFG_CSB_256x32 | CFG_PDWN256x32, | |
778 | dcrtc->base + LCD_SPU_SRAM_PARA1); | |
779 | ||
780 | /* | |
781 | * Initialize the transparency if the SRAM was powered down. | |
782 | * We must also reload the cursor data as well. | |
783 | */ | |
784 | if (!(para1 & CFG_CSB_256x32)) { | |
785 | armada_drm_crtc_cursor_tran(dcrtc->base); | |
786 | reload = true; | |
787 | } | |
788 | ||
789 | if (dcrtc->cursor_hw_sz != (h << 16 | w)) { | |
790 | spin_lock_irq(&dcrtc->irq_lock); | |
791 | armada_drm_crtc_disable_irq(dcrtc, DUMB_FRAMEDONE_ENA); | |
792 | dcrtc->cursor_update = false; | |
793 | armada_updatel(0, CFG_HWC_ENA, dcrtc->base + LCD_SPU_DMA_CTRL0); | |
794 | spin_unlock_irq(&dcrtc->irq_lock); | |
795 | reload = true; | |
796 | } | |
797 | if (reload) { | |
798 | struct armada_gem_object *obj = dcrtc->cursor_obj; | |
799 | uint32_t *pix; | |
800 | /* Set the top-left corner of the cursor image */ | |
801 | pix = obj->addr; | |
802 | pix += yoff * s + xoff; | |
803 | armada_load_cursor_argb(dcrtc->base, pix, s, w, h); | |
804 | } | |
805 | ||
806 | /* Reload the cursor position, size and enable in the IRQ handler */ | |
807 | spin_lock_irq(&dcrtc->irq_lock); | |
808 | dcrtc->cursor_hw_pos = yscr << 16 | xscr; | |
809 | dcrtc->cursor_hw_sz = h << 16 | w; | |
810 | dcrtc->cursor_update = true; | |
811 | armada_drm_crtc_enable_irq(dcrtc, DUMB_FRAMEDONE_ENA); | |
812 | spin_unlock_irq(&dcrtc->irq_lock); | |
813 | ||
814 | return 0; | |
815 | } | |
816 | ||
817 | static void cursor_update(void *data) | |
818 | { | |
819 | armada_drm_crtc_cursor_update(data, true); | |
820 | } | |
821 | ||
822 | static int armada_drm_crtc_cursor_set(struct drm_crtc *crtc, | |
823 | struct drm_file *file, uint32_t handle, uint32_t w, uint32_t h) | |
824 | { | |
825 | struct drm_device *dev = crtc->dev; | |
826 | struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc); | |
662af0d8 RK |
827 | struct armada_gem_object *obj = NULL; |
828 | int ret; | |
829 | ||
830 | /* If no cursor support, replicate drm's return value */ | |
42e62ba7 | 831 | if (!dcrtc->variant->has_spu_adv_reg) |
662af0d8 RK |
832 | return -ENXIO; |
833 | ||
834 | if (handle && w > 0 && h > 0) { | |
835 | /* maximum size is 64x32 or 32x64 */ | |
836 | if (w > 64 || h > 64 || (w > 32 && h > 32)) | |
837 | return -ENOMEM; | |
838 | ||
839 | obj = armada_gem_object_lookup(dev, file, handle); | |
840 | if (!obj) | |
841 | return -ENOENT; | |
842 | ||
843 | /* Must be a kernel-mapped object */ | |
844 | if (!obj->addr) { | |
845 | drm_gem_object_unreference_unlocked(&obj->obj); | |
846 | return -EINVAL; | |
847 | } | |
848 | ||
849 | if (obj->obj.size < w * h * 4) { | |
850 | DRM_ERROR("buffer is too small\n"); | |
851 | drm_gem_object_unreference_unlocked(&obj->obj); | |
852 | return -ENOMEM; | |
853 | } | |
854 | } | |
855 | ||
856 | mutex_lock(&dev->struct_mutex); | |
857 | if (dcrtc->cursor_obj) { | |
858 | dcrtc->cursor_obj->update = NULL; | |
859 | dcrtc->cursor_obj->update_data = NULL; | |
860 | drm_gem_object_unreference(&dcrtc->cursor_obj->obj); | |
861 | } | |
862 | dcrtc->cursor_obj = obj; | |
863 | dcrtc->cursor_w = w; | |
864 | dcrtc->cursor_h = h; | |
865 | ret = armada_drm_crtc_cursor_update(dcrtc, true); | |
866 | if (obj) { | |
867 | obj->update_data = dcrtc; | |
868 | obj->update = cursor_update; | |
869 | } | |
870 | mutex_unlock(&dev->struct_mutex); | |
871 | ||
872 | return ret; | |
873 | } | |
874 | ||
875 | static int armada_drm_crtc_cursor_move(struct drm_crtc *crtc, int x, int y) | |
876 | { | |
877 | struct drm_device *dev = crtc->dev; | |
878 | struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc); | |
662af0d8 RK |
879 | int ret; |
880 | ||
881 | /* If no cursor support, replicate drm's return value */ | |
42e62ba7 | 882 | if (!dcrtc->variant->has_spu_adv_reg) |
662af0d8 RK |
883 | return -EFAULT; |
884 | ||
885 | mutex_lock(&dev->struct_mutex); | |
886 | dcrtc->cursor_x = x; | |
887 | dcrtc->cursor_y = y; | |
888 | ret = armada_drm_crtc_cursor_update(dcrtc, false); | |
889 | mutex_unlock(&dev->struct_mutex); | |
890 | ||
891 | return ret; | |
892 | } | |
893 | ||
96f60e37 RK |
894 | static void armada_drm_crtc_destroy(struct drm_crtc *crtc) |
895 | { | |
896 | struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc); | |
897 | struct armada_private *priv = crtc->dev->dev_private; | |
898 | ||
662af0d8 RK |
899 | if (dcrtc->cursor_obj) |
900 | drm_gem_object_unreference(&dcrtc->cursor_obj->obj); | |
901 | ||
96f60e37 RK |
902 | priv->dcrtc[dcrtc->num] = NULL; |
903 | drm_crtc_cleanup(&dcrtc->crtc); | |
904 | ||
905 | if (!IS_ERR(dcrtc->clk)) | |
906 | clk_disable_unprepare(dcrtc->clk); | |
907 | ||
e5d9ddfb RK |
908 | writel_relaxed(0, dcrtc->base + LCD_SPU_IRQ_ENA); |
909 | ||
96f60e37 RK |
910 | kfree(dcrtc); |
911 | } | |
912 | ||
913 | /* | |
914 | * The mode_config lock is held here, to prevent races between this | |
915 | * and a mode_set. | |
916 | */ | |
917 | static int armada_drm_crtc_page_flip(struct drm_crtc *crtc, | |
5e4e3ba9 | 918 | struct drm_framebuffer *fb, struct drm_pending_vblank_event *event, uint32_t page_flip_flags) |
96f60e37 RK |
919 | { |
920 | struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc); | |
921 | struct armada_frame_work *work; | |
922 | struct drm_device *dev = crtc->dev; | |
923 | unsigned long flags; | |
924 | unsigned i; | |
925 | int ret; | |
926 | ||
927 | /* We don't support changing the pixel format */ | |
f4510a27 | 928 | if (fb->pixel_format != crtc->primary->fb->pixel_format) |
96f60e37 RK |
929 | return -EINVAL; |
930 | ||
931 | work = kmalloc(sizeof(*work), GFP_KERNEL); | |
932 | if (!work) | |
933 | return -ENOMEM; | |
934 | ||
935 | work->event = event; | |
f4510a27 | 936 | work->old_fb = dcrtc->crtc.primary->fb; |
96f60e37 RK |
937 | |
938 | i = armada_drm_crtc_calc_fb(fb, crtc->x, crtc->y, work->regs, | |
939 | dcrtc->interlaced); | |
940 | armada_reg_queue_end(work->regs, i); | |
941 | ||
942 | /* | |
943 | * Hold the old framebuffer for the work - DRM appears to drop our | |
944 | * reference to the old framebuffer in drm_mode_page_flip_ioctl(). | |
945 | */ | |
946 | drm_framebuffer_reference(work->old_fb); | |
947 | ||
948 | ret = armada_drm_crtc_queue_frame_work(dcrtc, work); | |
949 | if (ret) { | |
950 | /* | |
951 | * Undo our reference above; DRM does not drop the reference | |
952 | * to this object on error, so that's okay. | |
953 | */ | |
954 | drm_framebuffer_unreference(work->old_fb); | |
955 | kfree(work); | |
956 | return ret; | |
957 | } | |
958 | ||
959 | /* | |
960 | * Don't take a reference on the new framebuffer; | |
961 | * drm_mode_page_flip_ioctl() has already grabbed a reference and | |
962 | * will _not_ drop that reference on successful return from this | |
963 | * function. Simply mark this new framebuffer as the current one. | |
964 | */ | |
f4510a27 | 965 | dcrtc->crtc.primary->fb = fb; |
96f60e37 RK |
966 | |
967 | /* | |
968 | * Finally, if the display is blanked, we won't receive an | |
969 | * interrupt, so complete it now. | |
970 | */ | |
971 | if (dpms_blanked(dcrtc->dpms)) { | |
972 | spin_lock_irqsave(&dev->event_lock, flags); | |
973 | if (dcrtc->frame_work) | |
974 | armada_drm_crtc_complete_frame_work(dcrtc); | |
975 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
976 | } | |
977 | ||
978 | return 0; | |
979 | } | |
980 | ||
981 | static int | |
982 | armada_drm_crtc_set_property(struct drm_crtc *crtc, | |
983 | struct drm_property *property, uint64_t val) | |
984 | { | |
985 | struct armada_private *priv = crtc->dev->dev_private; | |
986 | struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc); | |
987 | bool update_csc = false; | |
988 | ||
989 | if (property == priv->csc_yuv_prop) { | |
990 | dcrtc->csc_yuv_mode = val; | |
991 | update_csc = true; | |
992 | } else if (property == priv->csc_rgb_prop) { | |
993 | dcrtc->csc_rgb_mode = val; | |
994 | update_csc = true; | |
995 | } | |
996 | ||
997 | if (update_csc) { | |
998 | uint32_t val; | |
999 | ||
1000 | val = dcrtc->spu_iopad_ctrl | | |
1001 | armada_drm_crtc_calculate_csc(dcrtc); | |
1002 | writel_relaxed(val, dcrtc->base + LCD_SPU_IOPAD_CONTROL); | |
1003 | } | |
1004 | ||
1005 | return 0; | |
1006 | } | |
1007 | ||
1008 | static struct drm_crtc_funcs armada_crtc_funcs = { | |
662af0d8 RK |
1009 | .cursor_set = armada_drm_crtc_cursor_set, |
1010 | .cursor_move = armada_drm_crtc_cursor_move, | |
96f60e37 RK |
1011 | .destroy = armada_drm_crtc_destroy, |
1012 | .set_config = drm_crtc_helper_set_config, | |
1013 | .page_flip = armada_drm_crtc_page_flip, | |
1014 | .set_property = armada_drm_crtc_set_property, | |
1015 | }; | |
1016 | ||
1017 | static struct drm_prop_enum_list armada_drm_csc_yuv_enum_list[] = { | |
1018 | { CSC_AUTO, "Auto" }, | |
1019 | { CSC_YUV_CCIR601, "CCIR601" }, | |
1020 | { CSC_YUV_CCIR709, "CCIR709" }, | |
1021 | }; | |
1022 | ||
1023 | static struct drm_prop_enum_list armada_drm_csc_rgb_enum_list[] = { | |
1024 | { CSC_AUTO, "Auto" }, | |
1025 | { CSC_RGB_COMPUTER, "Computer system" }, | |
1026 | { CSC_RGB_STUDIO, "Studio" }, | |
1027 | }; | |
1028 | ||
1029 | static int armada_drm_crtc_create_properties(struct drm_device *dev) | |
1030 | { | |
1031 | struct armada_private *priv = dev->dev_private; | |
1032 | ||
1033 | if (priv->csc_yuv_prop) | |
1034 | return 0; | |
1035 | ||
1036 | priv->csc_yuv_prop = drm_property_create_enum(dev, 0, | |
1037 | "CSC_YUV", armada_drm_csc_yuv_enum_list, | |
1038 | ARRAY_SIZE(armada_drm_csc_yuv_enum_list)); | |
1039 | priv->csc_rgb_prop = drm_property_create_enum(dev, 0, | |
1040 | "CSC_RGB", armada_drm_csc_rgb_enum_list, | |
1041 | ARRAY_SIZE(armada_drm_csc_rgb_enum_list)); | |
1042 | ||
1043 | if (!priv->csc_yuv_prop || !priv->csc_rgb_prop) | |
1044 | return -ENOMEM; | |
1045 | ||
1046 | return 0; | |
1047 | } | |
1048 | ||
d0165407 | 1049 | int armada_drm_crtc_create(struct drm_device *dev, struct resource *res, |
42e62ba7 | 1050 | int irq, const struct armada_variant *variant) |
96f60e37 RK |
1051 | { |
1052 | struct armada_private *priv = dev->dev_private; | |
1053 | struct armada_crtc *dcrtc; | |
1054 | void __iomem *base; | |
1055 | int ret; | |
1056 | ||
1057 | ret = armada_drm_crtc_create_properties(dev); | |
1058 | if (ret) | |
1059 | return ret; | |
1060 | ||
1061 | base = devm_request_and_ioremap(dev->dev, res); | |
1062 | if (!base) { | |
1063 | DRM_ERROR("failed to ioremap register\n"); | |
1064 | return -ENOMEM; | |
1065 | } | |
1066 | ||
1067 | dcrtc = kzalloc(sizeof(*dcrtc), GFP_KERNEL); | |
1068 | if (!dcrtc) { | |
1069 | DRM_ERROR("failed to allocate Armada crtc\n"); | |
1070 | return -ENOMEM; | |
1071 | } | |
1072 | ||
42e62ba7 | 1073 | dcrtc->variant = variant; |
96f60e37 | 1074 | dcrtc->base = base; |
d0165407 | 1075 | dcrtc->num = dev->mode_config.num_crtc; |
96f60e37 RK |
1076 | dcrtc->clk = ERR_PTR(-EINVAL); |
1077 | dcrtc->csc_yuv_mode = CSC_AUTO; | |
1078 | dcrtc->csc_rgb_mode = CSC_AUTO; | |
1079 | dcrtc->cfg_dumb_ctrl = DUMB24_RGB888_0; | |
1080 | dcrtc->spu_iopad_ctrl = CFG_VSCALE_LN_EN | CFG_IOPAD_DUMB24; | |
1081 | spin_lock_init(&dcrtc->irq_lock); | |
1082 | dcrtc->irq_ena = CLEAN_SPU_IRQ_ISR; | |
1083 | INIT_LIST_HEAD(&dcrtc->vbl_list); | |
1084 | init_waitqueue_head(&dcrtc->frame_wait); | |
1085 | ||
1086 | /* Initialize some registers which we don't otherwise set */ | |
1087 | writel_relaxed(0x00000001, dcrtc->base + LCD_CFG_SCLK_DIV); | |
1088 | writel_relaxed(0x00000000, dcrtc->base + LCD_SPU_BLANKCOLOR); | |
1089 | writel_relaxed(dcrtc->spu_iopad_ctrl, | |
1090 | dcrtc->base + LCD_SPU_IOPAD_CONTROL); | |
1091 | writel_relaxed(0x00000000, dcrtc->base + LCD_SPU_SRAM_PARA0); | |
1092 | writel_relaxed(CFG_PDWN256x32 | CFG_PDWN256x24 | CFG_PDWN256x8 | | |
1093 | CFG_PDWN32x32 | CFG_PDWN16x66 | CFG_PDWN32x66 | | |
1094 | CFG_PDWN64x66, dcrtc->base + LCD_SPU_SRAM_PARA1); | |
1095 | writel_relaxed(0x2032ff81, dcrtc->base + LCD_SPU_DMA_CTRL1); | |
1096 | writel_relaxed(0x00000000, dcrtc->base + LCD_SPU_GRA_OVSA_HPXL_VLN); | |
e5d9ddfb RK |
1097 | writel_relaxed(dcrtc->irq_ena, dcrtc->base + LCD_SPU_IRQ_ENA); |
1098 | writel_relaxed(0, dcrtc->base + LCD_SPU_IRQ_ISR); | |
1099 | ||
1100 | ret = devm_request_irq(dev, irq, armada_drm_irq, 0, "armada_drm_crtc", | |
1101 | dcrtc); | |
1102 | if (ret < 0) { | |
1103 | kfree(dcrtc); | |
1104 | return ret; | |
1105 | } | |
96f60e37 | 1106 | |
42e62ba7 RK |
1107 | if (dcrtc->variant->init) { |
1108 | ret = dcrtc->variant->init(dcrtc, dev->dev); | |
96f60e37 RK |
1109 | if (ret) { |
1110 | kfree(dcrtc); | |
1111 | return ret; | |
1112 | } | |
1113 | } | |
1114 | ||
1115 | /* Ensure AXI pipeline is enabled */ | |
1116 | armada_updatel(CFG_ARBFAST_ENA, 0, dcrtc->base + LCD_SPU_DMA_CTRL0); | |
1117 | ||
1118 | priv->dcrtc[dcrtc->num] = dcrtc; | |
1119 | ||
1120 | drm_crtc_init(dev, &dcrtc->crtc, &armada_crtc_funcs); | |
1121 | drm_crtc_helper_add(&dcrtc->crtc, &armada_crtc_helper_funcs); | |
1122 | ||
1123 | drm_object_attach_property(&dcrtc->crtc.base, priv->csc_yuv_prop, | |
1124 | dcrtc->csc_yuv_mode); | |
1125 | drm_object_attach_property(&dcrtc->crtc.base, priv->csc_rgb_prop, | |
1126 | dcrtc->csc_rgb_mode); | |
1127 | ||
1128 | return armada_overlay_plane_create(dev, 1 << dcrtc->num); | |
1129 | } |