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673a394b EA |
1 | /************************************************************************** |
2 | * | |
3 | * Copyright (c) 2006-2007 Tungsten Graphics, Inc., Cedar Park, TX., USA | |
4 | * All Rights Reserved. | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | |
7 | * copy of this software and associated documentation files (the | |
8 | * "Software"), to deal in the Software without restriction, including | |
9 | * without limitation the rights to use, copy, modify, merge, publish, | |
10 | * distribute, sub license, and/or sell copies of the Software, and to | |
11 | * permit persons to whom the Software is furnished to do so, subject to | |
12 | * the following conditions: | |
13 | * | |
14 | * The above copyright notice and this permission notice (including the | |
15 | * next paragraph) shall be included in all copies or substantial portions | |
16 | * of the Software. | |
17 | * | |
18 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
19 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
20 | * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL | |
21 | * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, | |
22 | * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR | |
23 | * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE | |
24 | * USE OR OTHER DEALINGS IN THE SOFTWARE. | |
25 | * | |
26 | **************************************************************************/ | |
27 | /* | |
28 | * Authors: Thomas Hellström <thomas-at-tungstengraphics-dot-com> | |
29 | */ | |
30 | ||
b7e32bef | 31 | #include <linux/dma-buf-map.h> |
2d1a8a48 | 32 | #include <linux/export.h> |
b46b54a5 | 33 | #include <linux/highmem.h> |
68104581 | 34 | #include <linux/mem_encrypt.h> |
3abc6670 | 35 | #include <xen/xen.h> |
b46b54a5 CW |
36 | |
37 | #include <drm/drm_cache.h> | |
673a394b | 38 | |
b7e32bef TH |
39 | /* A small bounce buffer that fits on the stack. */ |
40 | #define MEMCPY_BOUNCE_SIZE 128 | |
41 | ||
673a394b | 42 | #if defined(CONFIG_X86) |
b04d4a38 | 43 | #include <asm/smp.h> |
2a0c772f RZ |
44 | |
45 | /* | |
46 | * clflushopt is an unordered instruction which needs fencing with mfence or | |
47 | * sfence to avoid ordering issues. For drm_clflush_page this fencing happens | |
48 | * in the caller. | |
49 | */ | |
673a394b EA |
50 | static void |
51 | drm_clflush_page(struct page *page) | |
52 | { | |
53 | uint8_t *page_virtual; | |
54 | unsigned int i; | |
87229ad9 | 55 | const int size = boot_cpu_data.x86_clflush_size; |
673a394b EA |
56 | |
57 | if (unlikely(page == NULL)) | |
58 | return; | |
59 | ||
1c9c20f6 | 60 | page_virtual = kmap_atomic(page); |
87229ad9 | 61 | for (i = 0; i < PAGE_SIZE; i += size) |
2a0c772f | 62 | clflushopt(page_virtual + i); |
1c9c20f6 | 63 | kunmap_atomic(page_virtual); |
673a394b | 64 | } |
673a394b | 65 | |
c9c97b8c DA |
66 | static void drm_cache_flush_clflush(struct page *pages[], |
67 | unsigned long num_pages) | |
68 | { | |
69 | unsigned long i; | |
70 | ||
606be047 | 71 | mb(); /*Full memory barrier used before so that CLFLUSH is ordered*/ |
c9c97b8c DA |
72 | for (i = 0; i < num_pages; i++) |
73 | drm_clflush_page(*pages++); | |
606be047 | 74 | mb(); /*Also used after CLFLUSH so that all cache is flushed*/ |
c9c97b8c | 75 | } |
c9c97b8c | 76 | #endif |
ed017d9f | 77 | |
f0e36723 GKB |
78 | /** |
79 | * drm_clflush_pages - Flush dcache lines of a set of pages. | |
80 | * @pages: List of pages to be flushed. | |
81 | * @num_pages: Number of pages in the array. | |
82 | * | |
83 | * Flush every data cache line entry that points to an address belonging | |
84 | * to a page in the array. | |
85 | */ | |
673a394b EA |
86 | void |
87 | drm_clflush_pages(struct page *pages[], unsigned long num_pages) | |
88 | { | |
89 | ||
90 | #if defined(CONFIG_X86) | |
906bf7fd | 91 | if (static_cpu_has(X86_FEATURE_CLFLUSH)) { |
c9c97b8c | 92 | drm_cache_flush_clflush(pages, num_pages); |
673a394b EA |
93 | return; |
94 | } | |
673a394b | 95 | |
b04d4a38 | 96 | if (wbinvd_on_all_cpus()) |
499447db | 97 | pr_err("Timed out waiting for cache flush\n"); |
c9c97b8c DA |
98 | |
99 | #elif defined(__powerpc__) | |
100 | unsigned long i; | |
e109c6db | 101 | |
c9c97b8c DA |
102 | for (i = 0; i < num_pages; i++) { |
103 | struct page *page = pages[i]; | |
104 | void *page_virtual; | |
105 | ||
106 | if (unlikely(page == NULL)) | |
107 | continue; | |
108 | ||
1c9c20f6 | 109 | page_virtual = kmap_atomic(page); |
c9c97b8c DA |
110 | flush_dcache_range((unsigned long)page_virtual, |
111 | (unsigned long)page_virtual + PAGE_SIZE); | |
1c9c20f6 | 112 | kunmap_atomic(page_virtual); |
c9c97b8c DA |
113 | } |
114 | #else | |
499447db | 115 | pr_err("Architecture has no drm_cache.c support\n"); |
ed017d9f | 116 | WARN_ON_ONCE(1); |
e0f0754f | 117 | #endif |
673a394b EA |
118 | } |
119 | EXPORT_SYMBOL(drm_clflush_pages); | |
6d5cd9cb | 120 | |
f0e36723 GKB |
121 | /** |
122 | * drm_clflush_sg - Flush dcache lines pointing to a scather-gather. | |
123 | * @st: struct sg_table. | |
124 | * | |
125 | * Flush every data cache line entry that points to an address in the | |
126 | * sg. | |
127 | */ | |
9da3da66 CW |
128 | void |
129 | drm_clflush_sg(struct sg_table *st) | |
130 | { | |
131 | #if defined(CONFIG_X86) | |
906bf7fd | 132 | if (static_cpu_has(X86_FEATURE_CLFLUSH)) { |
f5ddf697 | 133 | struct sg_page_iter sg_iter; |
9da3da66 | 134 | |
c6a5f8da | 135 | mb(); /*CLFLUSH is ordered only by using memory barriers*/ |
6c6fa39c | 136 | for_each_sgtable_page(st, &sg_iter, 0) |
2db76d7c | 137 | drm_clflush_page(sg_page_iter_page(&sg_iter)); |
c6a5f8da | 138 | mb(); /*Make sure that all cache line entry is flushed*/ |
9da3da66 CW |
139 | |
140 | return; | |
141 | } | |
142 | ||
b04d4a38 | 143 | if (wbinvd_on_all_cpus()) |
499447db | 144 | pr_err("Timed out waiting for cache flush\n"); |
9da3da66 | 145 | #else |
499447db | 146 | pr_err("Architecture has no drm_cache.c support\n"); |
9da3da66 CW |
147 | WARN_ON_ONCE(1); |
148 | #endif | |
149 | } | |
150 | EXPORT_SYMBOL(drm_clflush_sg); | |
151 | ||
f0e36723 GKB |
152 | /** |
153 | * drm_clflush_virt_range - Flush dcache lines of a region | |
154 | * @addr: Initial kernel memory address. | |
155 | * @length: Region size. | |
156 | * | |
157 | * Flush every data cache line entry that points to an address in the | |
158 | * region requested. | |
159 | */ | |
6d5cd9cb | 160 | void |
c2d15359 | 161 | drm_clflush_virt_range(void *addr, unsigned long length) |
6d5cd9cb DV |
162 | { |
163 | #if defined(CONFIG_X86) | |
906bf7fd | 164 | if (static_cpu_has(X86_FEATURE_CLFLUSH)) { |
afcd950c | 165 | const int size = boot_cpu_data.x86_clflush_size; |
c2d15359 | 166 | void *end = addr + length; |
e109c6db | 167 | |
afcd950c | 168 | addr = (void *)(((unsigned long)addr) & -size); |
c6a5f8da | 169 | mb(); /*CLFLUSH is only ordered with a full memory barrier*/ |
afcd950c | 170 | for (; addr < end; addr += size) |
79270968 | 171 | clflushopt(addr); |
396f5d62 | 172 | clflushopt(end - 1); /* force serialisation */ |
0ae865ef | 173 | mb(); /*Ensure that every data cache line entry is flushed*/ |
6d5cd9cb DV |
174 | return; |
175 | } | |
176 | ||
b04d4a38 | 177 | if (wbinvd_on_all_cpus()) |
499447db | 178 | pr_err("Timed out waiting for cache flush\n"); |
6d5cd9cb | 179 | #else |
499447db | 180 | pr_err("Architecture has no drm_cache.c support\n"); |
6d5cd9cb DV |
181 | WARN_ON_ONCE(1); |
182 | #endif | |
183 | } | |
184 | EXPORT_SYMBOL(drm_clflush_virt_range); | |
3abc6670 TZ |
185 | |
186 | bool drm_need_swiotlb(int dma_bits) | |
187 | { | |
188 | struct resource *tmp; | |
189 | resource_size_t max_iomem = 0; | |
190 | ||
191 | /* | |
192 | * Xen paravirtual hosts require swiotlb regardless of requested dma | |
193 | * transfer size. | |
194 | * | |
195 | * NOTE: Really, what it requires is use of the dma_alloc_coherent | |
196 | * allocator used in ttm_dma_populate() instead of | |
197 | * ttm_populate_and_map_pages(), which bounce buffers so much in | |
198 | * Xen it leads to swiotlb buffer exhaustion. | |
199 | */ | |
200 | if (xen_pv_domain()) | |
201 | return true; | |
202 | ||
203 | /* | |
204 | * Enforce dma_alloc_coherent when memory encryption is active as well | |
205 | * for the same reasons as for Xen paravirtual hosts. | |
206 | */ | |
207 | if (mem_encrypt_active()) | |
208 | return true; | |
209 | ||
210 | for (tmp = iomem_resource.child; tmp; tmp = tmp->sibling) | |
211 | max_iomem = max(max_iomem, tmp->end); | |
212 | ||
213 | return max_iomem > ((u64)1 << dma_bits); | |
214 | } | |
215 | EXPORT_SYMBOL(drm_need_swiotlb); | |
b7e32bef TH |
216 | |
217 | static void memcpy_fallback(struct dma_buf_map *dst, | |
218 | const struct dma_buf_map *src, | |
219 | unsigned long len) | |
220 | { | |
221 | if (!dst->is_iomem && !src->is_iomem) { | |
222 | memcpy(dst->vaddr, src->vaddr, len); | |
223 | } else if (!src->is_iomem) { | |
224 | dma_buf_map_memcpy_to(dst, src->vaddr, len); | |
225 | } else if (!dst->is_iomem) { | |
226 | memcpy_fromio(dst->vaddr, src->vaddr_iomem, len); | |
227 | } else { | |
228 | /* | |
229 | * Bounce size is not performance tuned, but using a | |
230 | * bounce buffer like this is significantly faster than | |
231 | * resorting to ioreadxx() + iowritexx(). | |
232 | */ | |
233 | char bounce[MEMCPY_BOUNCE_SIZE]; | |
234 | void __iomem *_src = src->vaddr_iomem; | |
235 | void __iomem *_dst = dst->vaddr_iomem; | |
236 | ||
237 | while (len >= MEMCPY_BOUNCE_SIZE) { | |
238 | memcpy_fromio(bounce, _src, MEMCPY_BOUNCE_SIZE); | |
239 | memcpy_toio(_dst, bounce, MEMCPY_BOUNCE_SIZE); | |
240 | _src += MEMCPY_BOUNCE_SIZE; | |
241 | _dst += MEMCPY_BOUNCE_SIZE; | |
242 | len -= MEMCPY_BOUNCE_SIZE; | |
243 | } | |
244 | if (len) { | |
245 | memcpy_fromio(bounce, _src, MEMCPY_BOUNCE_SIZE); | |
246 | memcpy_toio(_dst, bounce, MEMCPY_BOUNCE_SIZE); | |
247 | } | |
248 | } | |
249 | } | |
250 | ||
251 | #ifdef CONFIG_X86 | |
252 | ||
253 | static DEFINE_STATIC_KEY_FALSE(has_movntdqa); | |
254 | ||
255 | static void __memcpy_ntdqa(void *dst, const void *src, unsigned long len) | |
256 | { | |
257 | kernel_fpu_begin(); | |
258 | ||
259 | while (len >= 4) { | |
260 | asm("movntdqa (%0), %%xmm0\n" | |
261 | "movntdqa 16(%0), %%xmm1\n" | |
262 | "movntdqa 32(%0), %%xmm2\n" | |
263 | "movntdqa 48(%0), %%xmm3\n" | |
264 | "movaps %%xmm0, (%1)\n" | |
265 | "movaps %%xmm1, 16(%1)\n" | |
266 | "movaps %%xmm2, 32(%1)\n" | |
267 | "movaps %%xmm3, 48(%1)\n" | |
268 | :: "r" (src), "r" (dst) : "memory"); | |
269 | src += 64; | |
270 | dst += 64; | |
271 | len -= 4; | |
272 | } | |
273 | while (len--) { | |
274 | asm("movntdqa (%0), %%xmm0\n" | |
275 | "movaps %%xmm0, (%1)\n" | |
276 | :: "r" (src), "r" (dst) : "memory"); | |
277 | src += 16; | |
278 | dst += 16; | |
279 | } | |
280 | ||
281 | kernel_fpu_end(); | |
282 | } | |
283 | ||
284 | /* | |
285 | * __drm_memcpy_from_wc copies @len bytes from @src to @dst using | |
286 | * non-temporal instructions where available. Note that all arguments | |
287 | * (@src, @dst) must be aligned to 16 bytes and @len must be a multiple | |
288 | * of 16. | |
289 | */ | |
290 | static void __drm_memcpy_from_wc(void *dst, const void *src, unsigned long len) | |
291 | { | |
292 | if (unlikely(((unsigned long)dst | (unsigned long)src | len) & 15)) | |
293 | memcpy(dst, src, len); | |
294 | else if (likely(len)) | |
295 | __memcpy_ntdqa(dst, src, len >> 4); | |
296 | } | |
297 | ||
298 | /** | |
299 | * drm_memcpy_from_wc - Perform the fastest available memcpy from a source | |
300 | * that may be WC. | |
301 | * @dst: The destination pointer | |
302 | * @src: The source pointer | |
303 | * @len: The size of the area o transfer in bytes | |
304 | * | |
305 | * Tries an arch optimized memcpy for prefetching reading out of a WC region, | |
306 | * and if no such beast is available, falls back to a normal memcpy. | |
307 | */ | |
308 | void drm_memcpy_from_wc(struct dma_buf_map *dst, | |
309 | const struct dma_buf_map *src, | |
310 | unsigned long len) | |
311 | { | |
312 | if (WARN_ON(in_interrupt())) { | |
313 | memcpy_fallback(dst, src, len); | |
314 | return; | |
315 | } | |
316 | ||
317 | if (static_branch_likely(&has_movntdqa)) { | |
318 | __drm_memcpy_from_wc(dst->is_iomem ? | |
319 | (void __force *)dst->vaddr_iomem : | |
320 | dst->vaddr, | |
321 | src->is_iomem ? | |
322 | (void const __force *)src->vaddr_iomem : | |
323 | src->vaddr, | |
324 | len); | |
325 | return; | |
326 | } | |
327 | ||
328 | memcpy_fallback(dst, src, len); | |
329 | } | |
330 | EXPORT_SYMBOL(drm_memcpy_from_wc); | |
331 | ||
332 | /* | |
333 | * drm_memcpy_init_early - One time initialization of the WC memcpy code | |
334 | */ | |
335 | void drm_memcpy_init_early(void) | |
336 | { | |
337 | /* | |
338 | * Some hypervisors (e.g. KVM) don't support VEX-prefix instructions | |
339 | * emulation. So don't enable movntdqa in hypervisor guest. | |
340 | */ | |
341 | if (static_cpu_has(X86_FEATURE_XMM4_1) && | |
342 | !boot_cpu_has(X86_FEATURE_HYPERVISOR)) | |
343 | static_branch_enable(&has_movntdqa); | |
344 | } | |
345 | #else | |
346 | void drm_memcpy_from_wc(struct dma_buf_map *dst, | |
347 | const struct dma_buf_map *src, | |
348 | unsigned long len) | |
349 | { | |
350 | WARN_ON(in_interrupt()); | |
351 | ||
352 | memcpy_fallback(dst, src, len); | |
353 | } | |
354 | EXPORT_SYMBOL(drm_memcpy_from_wc); | |
355 | ||
356 | void drm_memcpy_init_early(void) | |
357 | { | |
358 | } | |
359 | #endif /* CONFIG_X86 */ |