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drm/etnaviv: add lockdep assert to fence allocation
[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / etnaviv / etnaviv_gpu.c
CommitLineData
a8c21a54
T		 1/*
2 * Copyright (C) 2015 Etnaviv Project
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License version 2 as published by
6 * the Free Software Foundation.
7 *
8 * This program is distributed in the hope that it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License along with
14 * this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16
17#include <linux/component.h>
f54d1867 18#include <linux/dma-fence.h>
a8c21a54
T		 19#include <linux/moduleparam.h>
20#include <linux/of_device.h>
ea1f5729
LS		 21
22#include "etnaviv_cmdbuf.h"
a8c21a54
T		 23#include "etnaviv_dump.h"
24#include "etnaviv_gpu.h"
25#include "etnaviv_gem.h"
26#include "etnaviv_mmu.h"
a8c21a54
T		 27#include "common.xml.h"
28#include "state.xml.h"
29#include "state_hi.xml.h"
30#include "cmdstream.xml.h"
31
32static const struct platform_device_id gpu_ids[] = {
33 { .name = "etnaviv-gpu,2d" },
34 { },
35};
36
37static bool etnaviv_dump_core = true;
38module_param_named(dump_core, etnaviv_dump_core, bool, 0600);
39
40/*
41 * Driver functions:
42 */
43
44int etnaviv_gpu_get_param(struct etnaviv_gpu *gpu, u32 param, u64 *value)
45{
46 switch (param) {
47 case ETNAVIV_PARAM_GPU_MODEL:
48 *value = gpu->identity.model;
49 break;
50
51 case ETNAVIV_PARAM_GPU_REVISION:
52 *value = gpu->identity.revision;
53 break;
54
55 case ETNAVIV_PARAM_GPU_FEATURES_0:
56 *value = gpu->identity.features;
57 break;
58
59 case ETNAVIV_PARAM_GPU_FEATURES_1:
60 *value = gpu->identity.minor_features0;
61 break;
62
63 case ETNAVIV_PARAM_GPU_FEATURES_2:
64 *value = gpu->identity.minor_features1;
65 break;
66
67 case ETNAVIV_PARAM_GPU_FEATURES_3:
68 *value = gpu->identity.minor_features2;
69 break;
70
71 case ETNAVIV_PARAM_GPU_FEATURES_4:
72 *value = gpu->identity.minor_features3;
73 break;
74
602eb489
RK		 75 case ETNAVIV_PARAM_GPU_FEATURES_5:
76 *value = gpu->identity.minor_features4;
77 break;
78
79 case ETNAVIV_PARAM_GPU_FEATURES_6:
80 *value = gpu->identity.minor_features5;
81 break;
82
a8c21a54
T		 83 case ETNAVIV_PARAM_GPU_STREAM_COUNT:
84 *value = gpu->identity.stream_count;
85 break;
86
87 case ETNAVIV_PARAM_GPU_REGISTER_MAX:
88 *value = gpu->identity.register_max;
89 break;
90
91 case ETNAVIV_PARAM_GPU_THREAD_COUNT:
92 *value = gpu->identity.thread_count;
93 break;
94
95 case ETNAVIV_PARAM_GPU_VERTEX_CACHE_SIZE:
96 *value = gpu->identity.vertex_cache_size;
97 break;
98
99 case ETNAVIV_PARAM_GPU_SHADER_CORE_COUNT:
100 *value = gpu->identity.shader_core_count;
101 break;
102
103 case ETNAVIV_PARAM_GPU_PIXEL_PIPES:
104 *value = gpu->identity.pixel_pipes;
105 break;
106
107 case ETNAVIV_PARAM_GPU_VERTEX_OUTPUT_BUFFER_SIZE:
108 *value = gpu->identity.vertex_output_buffer_size;
109 break;
110
111 case ETNAVIV_PARAM_GPU_BUFFER_SIZE:
112 *value = gpu->identity.buffer_size;
113 break;
114
115 case ETNAVIV_PARAM_GPU_INSTRUCTION_COUNT:
116 *value = gpu->identity.instruction_count;
117 break;
118
119 case ETNAVIV_PARAM_GPU_NUM_CONSTANTS:
120 *value = gpu->identity.num_constants;
121 break;
122
602eb489
RK		 123 case ETNAVIV_PARAM_GPU_NUM_VARYINGS:
124 *value = gpu->identity.varyings_count;
125 break;
126
a8c21a54
T		 127 default:
128 DBG("%s: invalid param: %u", dev_name(gpu->dev), param);
129 return -EINVAL;
130 }
131
132 return 0;
133}
134
472f79dc
RK		 135
136#define etnaviv_is_model_rev(gpu, mod, rev) \
137 ((gpu)->identity.model == chipModel_##mod && \
138 (gpu)->identity.revision == rev)
52f36ba1
RK		 139#define etnaviv_field(val, field) \
140 (((val) & field##__MASK) >> field##__SHIFT)
141
a8c21a54
T		 142static void etnaviv_hw_specs(struct etnaviv_gpu *gpu)
143{
144 if (gpu->identity.minor_features0 &
145 chipMinorFeatures0_MORE_MINOR_FEATURES) {
602eb489
RK		 146 u32 specs[4];
147 unsigned int streams;
a8c21a54
T		 148
149 specs[0] = gpu_read(gpu, VIVS_HI_CHIP_SPECS);
150 specs[1] = gpu_read(gpu, VIVS_HI_CHIP_SPECS_2);
602eb489
RK		 151 specs[2] = gpu_read(gpu, VIVS_HI_CHIP_SPECS_3);
152 specs[3] = gpu_read(gpu, VIVS_HI_CHIP_SPECS_4);
a8c21a54 153
52f36ba1
RK		 154 gpu->identity.stream_count = etnaviv_field(specs[0],
155 VIVS_HI_CHIP_SPECS_STREAM_COUNT);
156 gpu->identity.register_max = etnaviv_field(specs[0],
157 VIVS_HI_CHIP_SPECS_REGISTER_MAX);
158 gpu->identity.thread_count = etnaviv_field(specs[0],
159 VIVS_HI_CHIP_SPECS_THREAD_COUNT);
160 gpu->identity.vertex_cache_size = etnaviv_field(specs[0],
161 VIVS_HI_CHIP_SPECS_VERTEX_CACHE_SIZE);
162 gpu->identity.shader_core_count = etnaviv_field(specs[0],
163 VIVS_HI_CHIP_SPECS_SHADER_CORE_COUNT);
164 gpu->identity.pixel_pipes = etnaviv_field(specs[0],
165 VIVS_HI_CHIP_SPECS_PIXEL_PIPES);
a8c21a54 166 gpu->identity.vertex_output_buffer_size =
52f36ba1
RK		 167 etnaviv_field(specs[0],
168 VIVS_HI_CHIP_SPECS_VERTEX_OUTPUT_BUFFER_SIZE);
169
170 gpu->identity.buffer_size = etnaviv_field(specs[1],
171 VIVS_HI_CHIP_SPECS_2_BUFFER_SIZE);
172 gpu->identity.instruction_count = etnaviv_field(specs[1],
173 VIVS_HI_CHIP_SPECS_2_INSTRUCTION_COUNT);
174 gpu->identity.num_constants = etnaviv_field(specs[1],
175 VIVS_HI_CHIP_SPECS_2_NUM_CONSTANTS);
602eb489
RK		 176
177 gpu->identity.varyings_count = etnaviv_field(specs[2],
178 VIVS_HI_CHIP_SPECS_3_VARYINGS_COUNT);
179
180 /* This overrides the value from older register if non-zero */
181 streams = etnaviv_field(specs[3],
182 VIVS_HI_CHIP_SPECS_4_STREAM_COUNT);
183 if (streams)
184 gpu->identity.stream_count = streams;
a8c21a54
T		 185 }
186
187 /* Fill in the stream count if not specified */
188 if (gpu->identity.stream_count == 0) {
189 if (gpu->identity.model >= 0x1000)
190 gpu->identity.stream_count = 4;
191 else
192 gpu->identity.stream_count = 1;
193 }
194
195 /* Convert the register max value */
196 if (gpu->identity.register_max)
197 gpu->identity.register_max = 1 << gpu->identity.register_max;
507f8991 198 else if (gpu->identity.model == chipModel_GC400)
a8c21a54
T		 199 gpu->identity.register_max = 32;
200 else
201 gpu->identity.register_max = 64;
202
203 /* Convert thread count */
204 if (gpu->identity.thread_count)
205 gpu->identity.thread_count = 1 << gpu->identity.thread_count;
507f8991 206 else if (gpu->identity.model == chipModel_GC400)
a8c21a54 207 gpu->identity.thread_count = 64;
507f8991
RK		 208 else if (gpu->identity.model == chipModel_GC500 ||
209 gpu->identity.model == chipModel_GC530)
a8c21a54
T		 210 gpu->identity.thread_count = 128;
211 else
212 gpu->identity.thread_count = 256;
213
214 if (gpu->identity.vertex_cache_size == 0)
215 gpu->identity.vertex_cache_size = 8;
216
217 if (gpu->identity.shader_core_count == 0) {
218 if (gpu->identity.model >= 0x1000)
219 gpu->identity.shader_core_count = 2;
220 else
221 gpu->identity.shader_core_count = 1;
222 }
223
224 if (gpu->identity.pixel_pipes == 0)
225 gpu->identity.pixel_pipes = 1;
226
227 /* Convert virtex buffer size */
228 if (gpu->identity.vertex_output_buffer_size) {
229 gpu->identity.vertex_output_buffer_size =
230 1 << gpu->identity.vertex_output_buffer_size;
507f8991 231 } else if (gpu->identity.model == chipModel_GC400) {
a8c21a54
T		 232 if (gpu->identity.revision < 0x4000)
233 gpu->identity.vertex_output_buffer_size = 512;
234 else if (gpu->identity.revision < 0x4200)
235 gpu->identity.vertex_output_buffer_size = 256;
236 else
237 gpu->identity.vertex_output_buffer_size = 128;
238 } else {
239 gpu->identity.vertex_output_buffer_size = 512;
240 }
241
242 switch (gpu->identity.instruction_count) {
243 case 0:
472f79dc 244 if (etnaviv_is_model_rev(gpu, GC2000, 0x5108) ||
507f8991 245 gpu->identity.model == chipModel_GC880)
a8c21a54
T		 246 gpu->identity.instruction_count = 512;
247 else
248 gpu->identity.instruction_count = 256;
249 break;
250
251 case 1:
252 gpu->identity.instruction_count = 1024;
253 break;
254
255 case 2:
256 gpu->identity.instruction_count = 2048;
257 break;
258
259 default:
260 gpu->identity.instruction_count = 256;
261 break;
262 }
263
264 if (gpu->identity.num_constants == 0)
265 gpu->identity.num_constants = 168;
602eb489
RK		 266
267 if (gpu->identity.varyings_count == 0) {
268 if (gpu->identity.minor_features1 & chipMinorFeatures1_HALTI0)
269 gpu->identity.varyings_count = 12;
270 else
271 gpu->identity.varyings_count = 8;
272 }
273
274 /*
275 * For some cores, two varyings are consumed for position, so the
276 * maximum varying count needs to be reduced by one.
277 */
278 if (etnaviv_is_model_rev(gpu, GC5000, 0x5434) ||
279 etnaviv_is_model_rev(gpu, GC4000, 0x5222) ||
280 etnaviv_is_model_rev(gpu, GC4000, 0x5245) ||
281 etnaviv_is_model_rev(gpu, GC4000, 0x5208) ||
282 etnaviv_is_model_rev(gpu, GC3000, 0x5435) ||
283 etnaviv_is_model_rev(gpu, GC2200, 0x5244) ||
284 etnaviv_is_model_rev(gpu, GC2100, 0x5108) ||
285 etnaviv_is_model_rev(gpu, GC2000, 0x5108) ||
286 etnaviv_is_model_rev(gpu, GC1500, 0x5246) ||
287 etnaviv_is_model_rev(gpu, GC880, 0x5107) ||
288 etnaviv_is_model_rev(gpu, GC880, 0x5106))
289 gpu->identity.varyings_count -= 1;
a8c21a54
T		 290}
291
292static void etnaviv_hw_identify(struct etnaviv_gpu *gpu)
293{
294 u32 chipIdentity;
295
296 chipIdentity = gpu_read(gpu, VIVS_HI_CHIP_IDENTITY);
297
298 /* Special case for older graphic cores. */
52f36ba1 299 if (etnaviv_field(chipIdentity, VIVS_HI_CHIP_IDENTITY_FAMILY) == 0x01) {
507f8991 300 gpu->identity.model = chipModel_GC500;
52f36ba1
RK		 301 gpu->identity.revision = etnaviv_field(chipIdentity,
302 VIVS_HI_CHIP_IDENTITY_REVISION);
a8c21a54
T		 303 } else {
304
305 gpu->identity.model = gpu_read(gpu, VIVS_HI_CHIP_MODEL);
306 gpu->identity.revision = gpu_read(gpu, VIVS_HI_CHIP_REV);
307
308 /*
309 * !!!! HACK ALERT !!!!
310 * Because people change device IDs without letting software
311 * know about it - here is the hack to make it all look the
312 * same. Only for GC400 family.
313 */
314 if ((gpu->identity.model & 0xff00) == 0x0400 &&
507f8991 315 gpu->identity.model != chipModel_GC420) {
a8c21a54
T		 316 gpu->identity.model = gpu->identity.model & 0x0400;
317 }
318
319 /* Another special case */
472f79dc 320 if (etnaviv_is_model_rev(gpu, GC300, 0x2201)) {
a8c21a54
T		 321 u32 chipDate = gpu_read(gpu, VIVS_HI_CHIP_DATE);
322 u32 chipTime = gpu_read(gpu, VIVS_HI_CHIP_TIME);
323
324 if (chipDate == 0x20080814 && chipTime == 0x12051100) {
325 /*
326 * This IP has an ECO; put the correct
327 * revision in it.
328 */
329 gpu->identity.revision = 0x1051;
330 }
331 }
12ff4bde
LS		 332
333 /*
334 * NXP likes to call the GPU on the i.MX6QP GC2000+, but in
335 * reality it's just a re-branded GC3000. We can identify this
336 * core by the upper half of the revision register being all 1.
337 * Fix model/rev here, so all other places can refer to this
338 * core by its real identity.
339 */
340 if (etnaviv_is_model_rev(gpu, GC2000, 0xffff5450)) {
341 gpu->identity.model = chipModel_GC3000;
342 gpu->identity.revision &= 0xffff;
343 }
a8c21a54
T		 344 }
345
346 dev_info(gpu->dev, "model: GC%x, revision: %x\n",
347 gpu->identity.model, gpu->identity.revision);
348
349 gpu->identity.features = gpu_read(gpu, VIVS_HI_CHIP_FEATURE);
350
351 /* Disable fast clear on GC700. */
507f8991 352 if (gpu->identity.model == chipModel_GC700)
a8c21a54
T		 353 gpu->identity.features &= ~chipFeatures_FAST_CLEAR;
354
507f8991
RK		 355 if ((gpu->identity.model == chipModel_GC500 &&
356 gpu->identity.revision < 2) ||
357 (gpu->identity.model == chipModel_GC300 &&
358 gpu->identity.revision < 0x2000)) {
a8c21a54
T		 359
360 /*
361 * GC500 rev 1.x and GC300 rev < 2.0 doesn't have these
362 * registers.
363 */
364 gpu->identity.minor_features0 = 0;
365 gpu->identity.minor_features1 = 0;
366 gpu->identity.minor_features2 = 0;
367 gpu->identity.minor_features3 = 0;
602eb489
RK		 368 gpu->identity.minor_features4 = 0;
369 gpu->identity.minor_features5 = 0;
a8c21a54
T		 370 } else
371 gpu->identity.minor_features0 =
372 gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_0);
373
374 if (gpu->identity.minor_features0 &
375 chipMinorFeatures0_MORE_MINOR_FEATURES) {
376 gpu->identity.minor_features1 =
377 gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_1);
378 gpu->identity.minor_features2 =
379 gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_2);
380 gpu->identity.minor_features3 =
381 gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_3);
602eb489
RK		 382 gpu->identity.minor_features4 =
383 gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_4);
384 gpu->identity.minor_features5 =
385 gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_5);
a8c21a54
T		 386 }
387
388 /* GC600 idle register reports zero bits where modules aren't present */
389 if (gpu->identity.model == chipModel_GC600) {
390 gpu->idle_mask = VIVS_HI_IDLE_STATE_TX |
391 VIVS_HI_IDLE_STATE_RA |
392 VIVS_HI_IDLE_STATE_SE |
393 VIVS_HI_IDLE_STATE_PA |
394 VIVS_HI_IDLE_STATE_SH |
395 VIVS_HI_IDLE_STATE_PE |
396 VIVS_HI_IDLE_STATE_DE |
397 VIVS_HI_IDLE_STATE_FE;
398 } else {
399 gpu->idle_mask = ~VIVS_HI_IDLE_STATE_AXI_LP;
400 }
401
402 etnaviv_hw_specs(gpu);
403}
404
405static void etnaviv_gpu_load_clock(struct etnaviv_gpu *gpu, u32 clock)
406{
407 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, clock |
408 VIVS_HI_CLOCK_CONTROL_FSCALE_CMD_LOAD);
409 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, clock);
410}
411
412static int etnaviv_hw_reset(struct etnaviv_gpu *gpu)
413{
414 u32 control, idle;
415 unsigned long timeout;
416 bool failed = true;
417
418 /* TODO
419 *
420 * - clock gating
421 * - puls eater
422 * - what about VG?
423 */
424
425 /* We hope that the GPU resets in under one second */
426 timeout = jiffies + msecs_to_jiffies(1000);
427
428 while (time_is_after_jiffies(timeout)) {
429 control = VIVS_HI_CLOCK_CONTROL_DISABLE_DEBUG_REGISTERS |
430 VIVS_HI_CLOCK_CONTROL_FSCALE_VAL(0x40);
431
432 /* enable clock */
433 etnaviv_gpu_load_clock(gpu, control);
434
435 /* Wait for stable clock. Vivante's code waited for 1ms */
436 usleep_range(1000, 10000);
437
438 /* isolate the GPU. */
439 control |= VIVS_HI_CLOCK_CONTROL_ISOLATE_GPU;
440 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control);
441
442 /* set soft reset. */
443 control |= VIVS_HI_CLOCK_CONTROL_SOFT_RESET;
444 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control);
445
446 /* wait for reset. */
447 msleep(1);
448
449 /* reset soft reset bit. */
450 control &= ~VIVS_HI_CLOCK_CONTROL_SOFT_RESET;
451 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control);
452
453 /* reset GPU isolation. */
454 control &= ~VIVS_HI_CLOCK_CONTROL_ISOLATE_GPU;
455 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control);
456
457 /* read idle register. */
458 idle = gpu_read(gpu, VIVS_HI_IDLE_STATE);
459
460 /* try reseting again if FE it not idle */
461 if ((idle & VIVS_HI_IDLE_STATE_FE) == 0) {
462 dev_dbg(gpu->dev, "FE is not idle\n");
463 continue;
464 }
465
466 /* read reset register. */
467 control = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL);
468
469 /* is the GPU idle? */
470 if (((control & VIVS_HI_CLOCK_CONTROL_IDLE_3D) == 0) ||
471 ((control & VIVS_HI_CLOCK_CONTROL_IDLE_2D) == 0)) {
472 dev_dbg(gpu->dev, "GPU is not idle\n");
473 continue;
474 }
475
476 failed = false;
477 break;
478 }
479
480 if (failed) {
481 idle = gpu_read(gpu, VIVS_HI_IDLE_STATE);
482 control = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL);
483
484 dev_err(gpu->dev, "GPU failed to reset: FE %sidle, 3D %sidle, 2D %sidle\n",
485 idle & VIVS_HI_IDLE_STATE_FE ? "" : "not ",
486 control & VIVS_HI_CLOCK_CONTROL_IDLE_3D ? "" : "not ",
487 control & VIVS_HI_CLOCK_CONTROL_IDLE_2D ? "" : "not ");
488
489 return -EBUSY;
490 }
491
492 /* We rely on the GPU running, so program the clock */
493 control = VIVS_HI_CLOCK_CONTROL_DISABLE_DEBUG_REGISTERS |
494 VIVS_HI_CLOCK_CONTROL_FSCALE_VAL(0x40);
495
496 /* enable clock */
497 etnaviv_gpu_load_clock(gpu, control);
498
499 return 0;
500}
501
7d0c6e71
RK		 502static void etnaviv_gpu_enable_mlcg(struct etnaviv_gpu *gpu)
503{
504 u32 pmc, ppc;
505
506 /* enable clock gating */
507 ppc = gpu_read(gpu, VIVS_PM_POWER_CONTROLS);
508 ppc |= VIVS_PM_POWER_CONTROLS_ENABLE_MODULE_CLOCK_GATING;
509
510 /* Disable stall module clock gating for 4.3.0.1 and 4.3.0.2 revs */
511 if (gpu->identity.revision == 0x4301 ||
512 gpu->identity.revision == 0x4302)
513 ppc |= VIVS_PM_POWER_CONTROLS_DISABLE_STALL_MODULE_CLOCK_GATING;
514
515 gpu_write(gpu, VIVS_PM_POWER_CONTROLS, ppc);
516
517 pmc = gpu_read(gpu, VIVS_PM_MODULE_CONTROLS);
518
519 /* Disable PA clock gating for GC400+ except for GC420 */
520 if (gpu->identity.model >= chipModel_GC400 &&
521 gpu->identity.model != chipModel_GC420)
522 pmc |= VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_PA;
523
524 /*
525 * Disable PE clock gating on revs < 5.0.0.0 when HZ is
526 * present without a bug fix.
527 */
528 if (gpu->identity.revision < 0x5000 &&
529 gpu->identity.minor_features0 & chipMinorFeatures0_HZ &&
530 !(gpu->identity.minor_features1 &
531 chipMinorFeatures1_DISABLE_PE_GATING))
532 pmc |= VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_PE;
533
534 if (gpu->identity.revision < 0x5422)
535 pmc |= BIT(15); /* Unknown bit */
536
537 pmc |= VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_RA_HZ;
538 pmc |= VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_RA_EZ;
539
540 gpu_write(gpu, VIVS_PM_MODULE_CONTROLS, pmc);
541}
542
229855b6
LS		 543void etnaviv_gpu_start_fe(struct etnaviv_gpu *gpu, u32 address, u16 prefetch)
544{
545 gpu_write(gpu, VIVS_FE_COMMAND_ADDRESS, address);
546 gpu_write(gpu, VIVS_FE_COMMAND_CONTROL,
547 VIVS_FE_COMMAND_CONTROL_ENABLE |
548 VIVS_FE_COMMAND_CONTROL_PREFETCH(prefetch));
549}
550
e17a0ded
WL		 551static void etnaviv_gpu_setup_pulse_eater(struct etnaviv_gpu *gpu)
552{
553 /*
554 * Base value for VIVS_PM_PULSE_EATER register on models where it
555 * cannot be read, extracted from vivante kernel driver.
556 */
557 u32 pulse_eater = 0x01590880;
558
559 if (etnaviv_is_model_rev(gpu, GC4000, 0x5208) ||
560 etnaviv_is_model_rev(gpu, GC4000, 0x5222)) {
561 pulse_eater |= BIT(23);
562
563 }
564
565 if (etnaviv_is_model_rev(gpu, GC1000, 0x5039) ||
566 etnaviv_is_model_rev(gpu, GC1000, 0x5040)) {
567 pulse_eater &= ~BIT(16);
568 pulse_eater |= BIT(17);
569 }
570
571 if ((gpu->identity.revision > 0x5420) &&
572 (gpu->identity.features & chipFeatures_PIPE_3D))
573 {
574 /* Performance fix: disable internal DFS */
575 pulse_eater = gpu_read(gpu, VIVS_PM_PULSE_EATER);
576 pulse_eater |= BIT(18);
577 }
578
579 gpu_write(gpu, VIVS_PM_PULSE_EATER, pulse_eater);
580}
581
a8c21a54
T		 582static void etnaviv_gpu_hw_init(struct etnaviv_gpu *gpu)
583{
584 u16 prefetch;
585
472f79dc
RK		 586 if ((etnaviv_is_model_rev(gpu, GC320, 0x5007) ||
587 etnaviv_is_model_rev(gpu, GC320, 0x5220)) &&
588 gpu_read(gpu, VIVS_HI_CHIP_TIME) != 0x2062400) {
a8c21a54
T		 589 u32 mc_memory_debug;
590
591 mc_memory_debug = gpu_read(gpu, VIVS_MC_DEBUG_MEMORY) & ~0xff;
592
593 if (gpu->identity.revision == 0x5007)
594 mc_memory_debug |= 0x0c;
595 else
596 mc_memory_debug |= 0x08;
597
598 gpu_write(gpu, VIVS_MC_DEBUG_MEMORY, mc_memory_debug);
599 }
600
7d0c6e71
RK		 601 /* enable module-level clock gating */
602 etnaviv_gpu_enable_mlcg(gpu);
603
a8c21a54
T		 604 /*
605 * Update GPU AXI cache atttribute to "cacheable, no allocate".
606 * This is necessary to prevent the iMX6 SoC locking up.
607 */
608 gpu_write(gpu, VIVS_HI_AXI_CONFIG,
609 VIVS_HI_AXI_CONFIG_AWCACHE(2) |
610 VIVS_HI_AXI_CONFIG_ARCACHE(2));
611
612 /* GC2000 rev 5108 needs a special bus config */
472f79dc 613 if (etnaviv_is_model_rev(gpu, GC2000, 0x5108)) {
a8c21a54
T		 614 u32 bus_config = gpu_read(gpu, VIVS_MC_BUS_CONFIG);
615 bus_config &= ~(VIVS_MC_BUS_CONFIG_FE_BUS_CONFIG__MASK |
616 VIVS_MC_BUS_CONFIG_TX_BUS_CONFIG__MASK);
617 bus_config |= VIVS_MC_BUS_CONFIG_FE_BUS_CONFIG(1) |
618 VIVS_MC_BUS_CONFIG_TX_BUS_CONFIG(0);
619 gpu_write(gpu, VIVS_MC_BUS_CONFIG, bus_config);
620 }
621
e17a0ded
WL		 622 /* setup the pulse eater */
623 etnaviv_gpu_setup_pulse_eater(gpu);
624
99f861bc 625 /* setup the MMU */
e095c8fe 626 etnaviv_iommu_restore(gpu);
a8c21a54
T		 627
628 /* Start command processor */
629 prefetch = etnaviv_buffer_init(gpu);
630
631 gpu_write(gpu, VIVS_HI_INTR_ENBL, ~0U);
c3ef4b8c 632 etnaviv_gpu_start_fe(gpu, etnaviv_cmdbuf_get_va(gpu->buffer),
229855b6 633 prefetch);
a8c21a54
T		 634}
635
636int etnaviv_gpu_init(struct etnaviv_gpu *gpu)
637{
638 int ret, i;
a8c21a54
T		 639
640 ret = pm_runtime_get_sync(gpu->dev);
1409df04
LS		 641 if (ret < 0) {
642 dev_err(gpu->dev, "Failed to enable GPU power domain\n");
a8c21a54 643 return ret;
1409df04 644 }
a8c21a54
T		 645
646 etnaviv_hw_identify(gpu);
647
648 if (gpu->identity.model == 0) {
649 dev_err(gpu->dev, "Unknown GPU model\n");
f6427760
RK		 650 ret = -ENXIO;
651 goto fail;
a8c21a54
T		 652 }
653
b98c6688
RK		 654 /* Exclude VG cores with FE2.0 */
655 if (gpu->identity.features & chipFeatures_PIPE_VG &&
656 gpu->identity.features & chipFeatures_FE20) {
657 dev_info(gpu->dev, "Ignoring GPU with VG and FE2.0\n");
658 ret = -ENXIO;
659 goto fail;
660 }
661
2144fff7
LS		 662 /*
663 * Set the GPU linear window to be at the end of the DMA window, where
664 * the CMA area is likely to reside. This ensures that we are able to
665 * map the command buffers while having the linear window overlap as
666 * much RAM as possible, so we can optimize mappings for other buffers.
667 *
668 * For 3D cores only do this if MC2.0 is present, as with MC1.0 it leads
669 * to different views of the memory on the individual engines.
670 */
671 if (!(gpu->identity.features & chipFeatures_PIPE_3D) ||
672 (gpu->identity.minor_features0 & chipMinorFeatures0_MC20)) {
673 u32 dma_mask = (u32)dma_get_required_mask(gpu->dev);
674 if (dma_mask < PHYS_OFFSET + SZ_2G)
675 gpu->memory_base = PHYS_OFFSET;
676 else
677 gpu->memory_base = dma_mask - SZ_2G + 1;
1db01279
LS		 678 } else if (PHYS_OFFSET >= SZ_2G) {
679 dev_info(gpu->dev, "Need to move linear window on MC1.0, disabling TS\n");
680 gpu->memory_base = PHYS_OFFSET;
681 gpu->identity.features &= ~chipFeatures_FAST_CLEAR;
2144fff7
LS		 682 }
683
a8c21a54 684 ret = etnaviv_hw_reset(gpu);
1409df04
LS		 685 if (ret) {
686 dev_err(gpu->dev, "GPU reset failed\n");
a8c21a54 687 goto fail;
1409df04 688 }
a8c21a54 689
dd34bb96
LS		 690 gpu->mmu = etnaviv_iommu_new(gpu);
691 if (IS_ERR(gpu->mmu)) {
1409df04 692 dev_err(gpu->dev, "Failed to instantiate GPU IOMMU\n");
dd34bb96 693 ret = PTR_ERR(gpu->mmu);
a8c21a54
T		 694 goto fail;
695 }
696
e66774dd
LS		 697 gpu->cmdbuf_suballoc = etnaviv_cmdbuf_suballoc_new(gpu);
698 if (IS_ERR(gpu->cmdbuf_suballoc)) {
699 dev_err(gpu->dev, "Failed to create cmdbuf suballocator\n");
700 ret = PTR_ERR(gpu->cmdbuf_suballoc);
701 goto fail;
702 }
703
a8c21a54 704 /* Create buffer: */
e66774dd 705 gpu->buffer = etnaviv_cmdbuf_new(gpu->cmdbuf_suballoc, PAGE_SIZE, 0);
a8c21a54
T		 706 if (!gpu->buffer) {
707 ret = -ENOMEM;
708 dev_err(gpu->dev, "could not create command buffer\n");
45d16a6d 709 goto destroy_iommu;
a8c21a54 710 }
acfee0ec
LS		 711
712 if (gpu->mmu->version == ETNAVIV_IOMMU_V1 &&
c3ef4b8c 713 etnaviv_cmdbuf_get_va(gpu->buffer) > 0x80000000) {
a8c21a54
T		 714 ret = -EINVAL;
715 dev_err(gpu->dev,
716 "command buffer outside valid memory window\n");
717 goto free_buffer;
718 }
719
720 /* Setup event management */
721 spin_lock_init(&gpu->event_spinlock);
722 init_completion(&gpu->event_free);
723 for (i = 0; i < ARRAY_SIZE(gpu->event); i++) {
724 gpu->event[i].used = false;
725 complete(&gpu->event_free);
726 }
727
728 /* Now program the hardware */
729 mutex_lock(&gpu->lock);
730 etnaviv_gpu_hw_init(gpu);
f6086311 731 gpu->exec_state = -1;
a8c21a54
T		 732 mutex_unlock(&gpu->lock);
733
734 pm_runtime_mark_last_busy(gpu->dev);
735 pm_runtime_put_autosuspend(gpu->dev);
736
737 return 0;
738
739free_buffer:
ea1f5729 740 etnaviv_cmdbuf_free(gpu->buffer);
a8c21a54 741 gpu->buffer = NULL;
45d16a6d
LS		 742destroy_iommu:
743 etnaviv_iommu_destroy(gpu->mmu);
744 gpu->mmu = NULL;
a8c21a54
T		 745fail:
746 pm_runtime_mark_last_busy(gpu->dev);
747 pm_runtime_put_autosuspend(gpu->dev);
748
749 return ret;
750}
751
752#ifdef CONFIG_DEBUG_FS
753struct dma_debug {
754 u32 address[2];
755 u32 state[2];
756};
757
758static void verify_dma(struct etnaviv_gpu *gpu, struct dma_debug *debug)
759{
760 u32 i;
761
762 debug->address[0] = gpu_read(gpu, VIVS_FE_DMA_ADDRESS);
763 debug->state[0] = gpu_read(gpu, VIVS_FE_DMA_DEBUG_STATE);
764
765 for (i = 0; i < 500; i++) {
766 debug->address[1] = gpu_read(gpu, VIVS_FE_DMA_ADDRESS);
767 debug->state[1] = gpu_read(gpu, VIVS_FE_DMA_DEBUG_STATE);
768
769 if (debug->address[0] != debug->address[1])
770 break;
771
772 if (debug->state[0] != debug->state[1])
773 break;
774 }
775}
776
777int etnaviv_gpu_debugfs(struct etnaviv_gpu *gpu, struct seq_file *m)
778{
779 struct dma_debug debug;
780 u32 dma_lo, dma_hi, axi, idle;
781 int ret;
782
783 seq_printf(m, "%s Status:\n", dev_name(gpu->dev));
784
785 ret = pm_runtime_get_sync(gpu->dev);
786 if (ret < 0)
787 return ret;
788
789 dma_lo = gpu_read(gpu, VIVS_FE_DMA_LOW);
790 dma_hi = gpu_read(gpu, VIVS_FE_DMA_HIGH);
791 axi = gpu_read(gpu, VIVS_HI_AXI_STATUS);
792 idle = gpu_read(gpu, VIVS_HI_IDLE_STATE);
793
794 verify_dma(gpu, &debug);
795
796 seq_puts(m, "\tfeatures\n");
797 seq_printf(m, "\t minor_features0: 0x%08x\n",
798 gpu->identity.minor_features0);
799 seq_printf(m, "\t minor_features1: 0x%08x\n",
800 gpu->identity.minor_features1);
801 seq_printf(m, "\t minor_features2: 0x%08x\n",
802 gpu->identity.minor_features2);
803 seq_printf(m, "\t minor_features3: 0x%08x\n",
804 gpu->identity.minor_features3);
602eb489
RK		 805 seq_printf(m, "\t minor_features4: 0x%08x\n",
806 gpu->identity.minor_features4);
807 seq_printf(m, "\t minor_features5: 0x%08x\n",
808 gpu->identity.minor_features5);
a8c21a54
T		 809
810 seq_puts(m, "\tspecs\n");
811 seq_printf(m, "\t stream_count: %d\n",
812 gpu->identity.stream_count);
813 seq_printf(m, "\t register_max: %d\n",
814 gpu->identity.register_max);
815 seq_printf(m, "\t thread_count: %d\n",
816 gpu->identity.thread_count);
817 seq_printf(m, "\t vertex_cache_size: %d\n",
818 gpu->identity.vertex_cache_size);
819 seq_printf(m, "\t shader_core_count: %d\n",
820 gpu->identity.shader_core_count);
821 seq_printf(m, "\t pixel_pipes: %d\n",
822 gpu->identity.pixel_pipes);
823 seq_printf(m, "\t vertex_output_buffer_size: %d\n",
824 gpu->identity.vertex_output_buffer_size);
825 seq_printf(m, "\t buffer_size: %d\n",
826 gpu->identity.buffer_size);
827 seq_printf(m, "\t instruction_count: %d\n",
828 gpu->identity.instruction_count);
829 seq_printf(m, "\t num_constants: %d\n",
830 gpu->identity.num_constants);
602eb489
RK		 831 seq_printf(m, "\t varyings_count: %d\n",
832 gpu->identity.varyings_count);
a8c21a54
T		 833
834 seq_printf(m, "\taxi: 0x%08x\n", axi);
835 seq_printf(m, "\tidle: 0x%08x\n", idle);
836 idle |= ~gpu->idle_mask & ~VIVS_HI_IDLE_STATE_AXI_LP;
837 if ((idle & VIVS_HI_IDLE_STATE_FE) == 0)
838 seq_puts(m, "\t FE is not idle\n");
839 if ((idle & VIVS_HI_IDLE_STATE_DE) == 0)
840 seq_puts(m, "\t DE is not idle\n");
841 if ((idle & VIVS_HI_IDLE_STATE_PE) == 0)
842 seq_puts(m, "\t PE is not idle\n");
843 if ((idle & VIVS_HI_IDLE_STATE_SH) == 0)
844 seq_puts(m, "\t SH is not idle\n");
845 if ((idle & VIVS_HI_IDLE_STATE_PA) == 0)
846 seq_puts(m, "\t PA is not idle\n");
847 if ((idle & VIVS_HI_IDLE_STATE_SE) == 0)
848 seq_puts(m, "\t SE is not idle\n");
849 if ((idle & VIVS_HI_IDLE_STATE_RA) == 0)
850 seq_puts(m, "\t RA is not idle\n");
851 if ((idle & VIVS_HI_IDLE_STATE_TX) == 0)
852 seq_puts(m, "\t TX is not idle\n");
853 if ((idle & VIVS_HI_IDLE_STATE_VG) == 0)
854 seq_puts(m, "\t VG is not idle\n");
855 if ((idle & VIVS_HI_IDLE_STATE_IM) == 0)
856 seq_puts(m, "\t IM is not idle\n");
857 if ((idle & VIVS_HI_IDLE_STATE_FP) == 0)
858 seq_puts(m, "\t FP is not idle\n");
859 if ((idle & VIVS_HI_IDLE_STATE_TS) == 0)
860 seq_puts(m, "\t TS is not idle\n");
861 if (idle & VIVS_HI_IDLE_STATE_AXI_LP)
862 seq_puts(m, "\t AXI low power mode\n");
863
864 if (gpu->identity.features & chipFeatures_DEBUG_MODE) {
865 u32 read0 = gpu_read(gpu, VIVS_MC_DEBUG_READ0);
866 u32 read1 = gpu_read(gpu, VIVS_MC_DEBUG_READ1);
867 u32 write = gpu_read(gpu, VIVS_MC_DEBUG_WRITE);
868
869 seq_puts(m, "\tMC\n");
870 seq_printf(m, "\t read0: 0x%08x\n", read0);
871 seq_printf(m, "\t read1: 0x%08x\n", read1);
872 seq_printf(m, "\t write: 0x%08x\n", write);
873 }
874
875 seq_puts(m, "\tDMA ");
876
877 if (debug.address[0] == debug.address[1] &&
878 debug.state[0] == debug.state[1]) {
879 seq_puts(m, "seems to be stuck\n");
880 } else if (debug.address[0] == debug.address[1]) {
c01e0159 881 seq_puts(m, "address is constant\n");
a8c21a54 882 } else {
c01e0159 883 seq_puts(m, "is running\n");
a8c21a54
T		 884 }
885
886 seq_printf(m, "\t address 0: 0x%08x\n", debug.address[0]);
887 seq_printf(m, "\t address 1: 0x%08x\n", debug.address[1]);
888 seq_printf(m, "\t state 0: 0x%08x\n", debug.state[0]);
889 seq_printf(m, "\t state 1: 0x%08x\n", debug.state[1]);
890 seq_printf(m, "\t last fetch 64 bit word: 0x%08x 0x%08x\n",
891 dma_lo, dma_hi);
892
893 ret = 0;
894
895 pm_runtime_mark_last_busy(gpu->dev);
896 pm_runtime_put_autosuspend(gpu->dev);
897
898 return ret;
899}
900#endif
901
a8c21a54
T		 902/*
903 * Hangcheck detection for locked gpu:
904 */
905static void recover_worker(struct work_struct *work)
906{
907 struct etnaviv_gpu *gpu = container_of(work, struct etnaviv_gpu,
908 recover_work);
909 unsigned long flags;
910 unsigned int i;
911
912 dev_err(gpu->dev, "hangcheck recover!\n");
913
914 if (pm_runtime_get_sync(gpu->dev) < 0)
915 return;
916
917 mutex_lock(&gpu->lock);
918
919 /* Only catch the first event, or when manually re-armed */
920 if (etnaviv_dump_core) {
921 etnaviv_core_dump(gpu);
922 etnaviv_dump_core = false;
923 }
924
925 etnaviv_hw_reset(gpu);
926
927 /* complete all events, the GPU won't do it after the reset */
928 spin_lock_irqsave(&gpu->event_spinlock, flags);
929 for (i = 0; i < ARRAY_SIZE(gpu->event); i++) {
930 if (!gpu->event[i].used)
931 continue;
f54d1867 932 dma_fence_signal(gpu->event[i].fence);
a8c21a54
T		 933 gpu->event[i].fence = NULL;
934 gpu->event[i].used = false;
935 complete(&gpu->event_free);
a8c21a54
T		 936 }
937 spin_unlock_irqrestore(&gpu->event_spinlock, flags);
938 gpu->completed_fence = gpu->active_fence;
939
940 etnaviv_gpu_hw_init(gpu);
1b94a9b7 941 gpu->lastctx = NULL;
f6086311 942 gpu->exec_state = -1;
a8c21a54
T		 943
944 mutex_unlock(&gpu->lock);
945 pm_runtime_mark_last_busy(gpu->dev);
946 pm_runtime_put_autosuspend(gpu->dev);
947
948 /* Retire the buffer objects in a work */
949 etnaviv_queue_work(gpu->drm, &gpu->retire_work);
950}
951
952static void hangcheck_timer_reset(struct etnaviv_gpu *gpu)
953{
954 DBG("%s", dev_name(gpu->dev));
955 mod_timer(&gpu->hangcheck_timer,
956 round_jiffies_up(jiffies + DRM_ETNAVIV_HANGCHECK_JIFFIES));
957}
958
959static void hangcheck_handler(unsigned long data)
960{
961 struct etnaviv_gpu *gpu = (struct etnaviv_gpu *)data;
962 u32 fence = gpu->completed_fence;
963 bool progress = false;
964
965 if (fence != gpu->hangcheck_fence) {
966 gpu->hangcheck_fence = fence;
967 progress = true;
968 }
969
970 if (!progress) {
971 u32 dma_addr = gpu_read(gpu, VIVS_FE_DMA_ADDRESS);
972 int change = dma_addr - gpu->hangcheck_dma_addr;
973
974 if (change < 0 || change > 16) {
975 gpu->hangcheck_dma_addr = dma_addr;
976 progress = true;
977 }
978 }
979
980 if (!progress && fence_after(gpu->active_fence, fence)) {
981 dev_err(gpu->dev, "hangcheck detected gpu lockup!\n");
982 dev_err(gpu->dev, " completed fence: %u\n", fence);
983 dev_err(gpu->dev, " active fence: %u\n",
984 gpu->active_fence);
985 etnaviv_queue_work(gpu->drm, &gpu->recover_work);
986 }
987
988 /* if still more pending work, reset the hangcheck timer: */
989 if (fence_after(gpu->active_fence, gpu->hangcheck_fence))
990 hangcheck_timer_reset(gpu);
991}
992
993static void hangcheck_disable(struct etnaviv_gpu *gpu)
994{
995 del_timer_sync(&gpu->hangcheck_timer);
996 cancel_work_sync(&gpu->recover_work);
997}
998
999/* fence object management */
1000struct etnaviv_fence {
1001 struct etnaviv_gpu *gpu;
f54d1867 1002 struct dma_fence base;
a8c21a54
T		 1003};
1004
f54d1867 1005static inline struct etnaviv_fence *to_etnaviv_fence(struct dma_fence *fence)
a8c21a54
T		 1006{
1007 return container_of(fence, struct etnaviv_fence, base);
1008}
1009
f54d1867 1010static const char *etnaviv_fence_get_driver_name(struct dma_fence *fence)
a8c21a54
T		 1011{
1012 return "etnaviv";
1013}
1014
f54d1867 1015static const char *etnaviv_fence_get_timeline_name(struct dma_fence *fence)
a8c21a54
T		 1016{
1017 struct etnaviv_fence *f = to_etnaviv_fence(fence);
1018
1019 return dev_name(f->gpu->dev);
1020}
1021
f54d1867 1022static bool etnaviv_fence_enable_signaling(struct dma_fence *fence)
a8c21a54
T		 1023{
1024 return true;
1025}
1026
f54d1867 1027static bool etnaviv_fence_signaled(struct dma_fence *fence)
a8c21a54
T		 1028{
1029 struct etnaviv_fence *f = to_etnaviv_fence(fence);
1030
1031 return fence_completed(f->gpu, f->base.seqno);
1032}
1033
f54d1867 1034static void etnaviv_fence_release(struct dma_fence *fence)
a8c21a54
T		 1035{
1036 struct etnaviv_fence *f = to_etnaviv_fence(fence);
1037
1038 kfree_rcu(f, base.rcu);
1039}
1040
f54d1867 1041static const struct dma_fence_ops etnaviv_fence_ops = {
a8c21a54
T		 1042 .get_driver_name = etnaviv_fence_get_driver_name,
1043 .get_timeline_name = etnaviv_fence_get_timeline_name,
1044 .enable_signaling = etnaviv_fence_enable_signaling,
1045 .signaled = etnaviv_fence_signaled,
f54d1867 1046 .wait = dma_fence_default_wait,
a8c21a54
T		 1047 .release = etnaviv_fence_release,
1048};
1049
f54d1867 1050static struct dma_fence *etnaviv_gpu_fence_alloc(struct etnaviv_gpu *gpu)
a8c21a54
T		 1051{
1052 struct etnaviv_fence *f;
1053
b27734c2
LS		 1054 /*
1055 * GPU lock must already be held, otherwise fence completion order might
1056 * not match the seqno order assigned here.
1057 */
1058 lockdep_assert_held(&gpu->lock);
1059
a8c21a54
T		 1060 f = kzalloc(sizeof(*f), GFP_KERNEL);
1061 if (!f)
1062 return NULL;
1063
1064 f->gpu = gpu;
1065
f54d1867
CW		 1066 dma_fence_init(&f->base, &etnaviv_fence_ops, &gpu->fence_spinlock,
1067 gpu->fence_context, ++gpu->next_fence);
a8c21a54
T		 1068
1069 return &f->base;
1070}
1071
1072int etnaviv_gpu_fence_sync_obj(struct etnaviv_gem_object *etnaviv_obj,
1073 unsigned int context, bool exclusive)
1074{
1075 struct reservation_object *robj = etnaviv_obj->resv;
1076 struct reservation_object_list *fobj;
f54d1867 1077 struct dma_fence *fence;
a8c21a54
T		 1078 int i, ret;
1079
1080 if (!exclusive) {
1081 ret = reservation_object_reserve_shared(robj);
1082 if (ret)
1083 return ret;
1084 }
1085
1086 /*
1087 * If we have any shared fences, then the exclusive fence
1088 * should be ignored as it will already have been signalled.
1089 */
1090 fobj = reservation_object_get_list(robj);
1091 if (!fobj || fobj->shared_count == 0) {
1092 /* Wait on any existing exclusive fence which isn't our own */
1093 fence = reservation_object_get_excl(robj);
1094 if (fence && fence->context != context) {
f54d1867 1095 ret = dma_fence_wait(fence, true);
a8c21a54
T		 1096 if (ret)
1097 return ret;
1098 }
1099 }
1100
1101 if (!exclusive || !fobj)
1102 return 0;
1103
1104 for (i = 0; i < fobj->shared_count; i++) {
1105 fence = rcu_dereference_protected(fobj->shared[i],
1106 reservation_object_held(robj));
1107 if (fence->context != context) {
f54d1867 1108 ret = dma_fence_wait(fence, true);
a8c21a54
T		 1109 if (ret)
1110 return ret;
1111 }
1112 }
1113
1114 return 0;
1115}
1116
1117/*
1118 * event management:
1119 */
1120
1121static unsigned int event_alloc(struct etnaviv_gpu *gpu)
1122{
1123 unsigned long ret, flags;
1124 unsigned int i, event = ~0U;
1125
1126 ret = wait_for_completion_timeout(&gpu->event_free,
1127 msecs_to_jiffies(10 * 10000));
1128 if (!ret)
1129 dev_err(gpu->dev, "wait_for_completion_timeout failed");
1130
1131 spin_lock_irqsave(&gpu->event_spinlock, flags);
1132
1133 /* find first free event */
1134 for (i = 0; i < ARRAY_SIZE(gpu->event); i++) {
1135 if (gpu->event[i].used == false) {
1136 gpu->event[i].used = true;
1137 event = i;
1138 break;
1139 }
1140 }
1141
1142 spin_unlock_irqrestore(&gpu->event_spinlock, flags);
1143
1144 return event;
1145}
1146
1147static void event_free(struct etnaviv_gpu *gpu, unsigned int event)
1148{
1149 unsigned long flags;
1150
1151 spin_lock_irqsave(&gpu->event_spinlock, flags);
1152
1153 if (gpu->event[event].used == false) {
1154 dev_warn(gpu->dev, "event %u is already marked as free",
1155 event);
1156 spin_unlock_irqrestore(&gpu->event_spinlock, flags);
1157 } else {
1158 gpu->event[event].used = false;
1159 spin_unlock_irqrestore(&gpu->event_spinlock, flags);
1160
1161 complete(&gpu->event_free);
1162 }
1163}
1164
1165/*
1166 * Cmdstream submission/retirement:
1167 */
1168
a8c21a54
T		 1169static void retire_worker(struct work_struct *work)
1170{
1171 struct etnaviv_gpu *gpu = container_of(work, struct etnaviv_gpu,
1172 retire_work);
1173 u32 fence = gpu->completed_fence;
1174 struct etnaviv_cmdbuf *cmdbuf, *tmp;
1175 unsigned int i;
1176
1177 mutex_lock(&gpu->lock);
1178 list_for_each_entry_safe(cmdbuf, tmp, &gpu->active_cmd_list, node) {
f54d1867 1179 if (!dma_fence_is_signaled(cmdbuf->fence))
a8c21a54
T		 1180 break;
1181
1182 list_del(&cmdbuf->node);
f54d1867 1183 dma_fence_put(cmdbuf->fence);
a8c21a54
T		 1184
1185 for (i = 0; i < cmdbuf->nr_bos; i++) {
b6325f40
RK		 1186 struct etnaviv_vram_mapping *mapping = cmdbuf->bo_map[i];
1187 struct etnaviv_gem_object *etnaviv_obj = mapping->object;
a8c21a54
T		 1188
1189 atomic_dec(&etnaviv_obj->gpu_active);
1190 /* drop the refcount taken in etnaviv_gpu_submit */
b6325f40 1191 etnaviv_gem_mapping_unreference(mapping);
a8c21a54
T		 1192 }
1193
ea1f5729 1194 etnaviv_cmdbuf_free(cmdbuf);
d9fd0c7d
LS		 1195 /*
1196 * We need to balance the runtime PM count caused by
1197 * each submission. Upon submission, we increment
1198 * the runtime PM counter, and allocate one event.
1199 * So here, we put the runtime PM count for each
1200 * completed event.
1201 */
1202 pm_runtime_put_autosuspend(gpu->dev);
a8c21a54
T		 1203 }
1204
1205 gpu->retired_fence = fence;
1206
1207 mutex_unlock(&gpu->lock);
1208
1209 wake_up_all(&gpu->fence_event);
1210}
1211
1212int etnaviv_gpu_wait_fence_interruptible(struct etnaviv_gpu *gpu,
1213 u32 fence, struct timespec *timeout)
1214{
1215 int ret;
1216
1217 if (fence_after(fence, gpu->next_fence)) {
1218 DRM_ERROR("waiting on invalid fence: %u (of %u)\n",
1219 fence, gpu->next_fence);
1220 return -EINVAL;
1221 }
1222
1223 if (!timeout) {
1224 /* No timeout was requested: just test for completion */
1225 ret = fence_completed(gpu, fence) ? 0 : -EBUSY;
1226 } else {
1227 unsigned long remaining = etnaviv_timeout_to_jiffies(timeout);
1228
1229 ret = wait_event_interruptible_timeout(gpu->fence_event,
1230 fence_completed(gpu, fence),
1231 remaining);
1232 if (ret == 0) {
1233 DBG("timeout waiting for fence: %u (retired: %u completed: %u)",
1234 fence, gpu->retired_fence,
1235 gpu->completed_fence);
1236 ret = -ETIMEDOUT;
1237 } else if (ret != -ERESTARTSYS) {
1238 ret = 0;
1239 }
1240 }
1241
1242 return ret;
1243}
1244
1245/*
1246 * Wait for an object to become inactive. This, on it's own, is not race
1247 * free: the object is moved by the retire worker off the active list, and
1248 * then the iova is put. Moreover, the object could be re-submitted just
1249 * after we notice that it's become inactive.
1250 *
1251 * Although the retirement happens under the gpu lock, we don't want to hold
1252 * that lock in this function while waiting.
1253 */
1254int etnaviv_gpu_wait_obj_inactive(struct etnaviv_gpu *gpu,
1255 struct etnaviv_gem_object *etnaviv_obj, struct timespec *timeout)
1256{
1257 unsigned long remaining;
1258 long ret;
1259
1260 if (!timeout)
1261 return !is_active(etnaviv_obj) ? 0 : -EBUSY;
1262
1263 remaining = etnaviv_timeout_to_jiffies(timeout);
1264
1265 ret = wait_event_interruptible_timeout(gpu->fence_event,
1266 !is_active(etnaviv_obj),
1267 remaining);
1268 if (ret > 0) {
1269 struct etnaviv_drm_private *priv = gpu->drm->dev_private;
1270
1271 /* Synchronise with the retire worker */
1272 flush_workqueue(priv->wq);
1273 return 0;
1274 } else if (ret == -ERESTARTSYS) {
1275 return -ERESTARTSYS;
1276 } else {
1277 return -ETIMEDOUT;
1278 }
1279}
1280
1281int etnaviv_gpu_pm_get_sync(struct etnaviv_gpu *gpu)
1282{
1283 return pm_runtime_get_sync(gpu->dev);
1284}
1285
1286void etnaviv_gpu_pm_put(struct etnaviv_gpu *gpu)
1287{
1288 pm_runtime_mark_last_busy(gpu->dev);
1289 pm_runtime_put_autosuspend(gpu->dev);
1290}
1291
1292/* add bo's to gpu's ring, and kick gpu: */
1293int etnaviv_gpu_submit(struct etnaviv_gpu *gpu,
1294 struct etnaviv_gem_submit *submit, struct etnaviv_cmdbuf *cmdbuf)
1295{
f54d1867 1296 struct dma_fence *fence;
a8c21a54
T		 1297 unsigned int event, i;
1298 int ret;
1299
1300 ret = etnaviv_gpu_pm_get_sync(gpu);
1301 if (ret < 0)
1302 return ret;
1303
a8c21a54
T		 1304 /*
1305 * TODO
1306 *
1307 * - flush
1308 * - data endian
1309 * - prefetch
1310 *
1311 */
1312
1313 event = event_alloc(gpu);
1314 if (unlikely(event == ~0U)) {
1315 DRM_ERROR("no free event\n");
1316 ret = -EBUSY;
d9853490 1317 goto out_pm_put;
a8c21a54
T		 1318 }
1319
1320 fence = etnaviv_gpu_fence_alloc(gpu);
1321 if (!fence) {
1322 event_free(gpu, event);
1323 ret = -ENOMEM;
d9853490 1324 goto out_pm_put;
a8c21a54
T		 1325 }
1326
d9853490
LS		 1327 mutex_lock(&gpu->lock);
1328
a8c21a54
T		 1329 gpu->event[event].fence = fence;
1330 submit->fence = fence->seqno;
1331 gpu->active_fence = submit->fence;
1332
1333 if (gpu->lastctx != cmdbuf->ctx) {
1334 gpu->mmu->need_flush = true;
1335 gpu->switch_context = true;
1336 gpu->lastctx = cmdbuf->ctx;
1337 }
1338
1339 etnaviv_buffer_queue(gpu, event, cmdbuf);
1340
1341 cmdbuf->fence = fence;
1342 list_add_tail(&cmdbuf->node, &gpu->active_cmd_list);
1343
1344 /* We're committed to adding this command buffer, hold a PM reference */
1345 pm_runtime_get_noresume(gpu->dev);
1346
1347 for (i = 0; i < submit->nr_bos; i++) {
1348 struct etnaviv_gem_object *etnaviv_obj = submit->bos[i].obj;
a8c21a54 1349
b6325f40
RK		 1350 /* Each cmdbuf takes a refcount on the mapping */
1351 etnaviv_gem_mapping_reference(submit->bos[i].mapping);
1352 cmdbuf->bo_map[i] = submit->bos[i].mapping;
a8c21a54
T		 1353 atomic_inc(&etnaviv_obj->gpu_active);
1354
1355 if (submit->bos[i].flags & ETNA_SUBMIT_BO_WRITE)
1356 reservation_object_add_excl_fence(etnaviv_obj->resv,
1357 fence);
1358 else
1359 reservation_object_add_shared_fence(etnaviv_obj->resv,
1360 fence);
1361 }
1362 cmdbuf->nr_bos = submit->nr_bos;
1363 hangcheck_timer_reset(gpu);
1364 ret = 0;
1365
a8c21a54
T		 1366 mutex_unlock(&gpu->lock);
1367
d9853490 1368out_pm_put:
a8c21a54
T		 1369 etnaviv_gpu_pm_put(gpu);
1370
1371 return ret;
1372}
1373
1374/*
1375 * Init/Cleanup:
1376 */
1377static irqreturn_t irq_handler(int irq, void *data)
1378{
1379 struct etnaviv_gpu *gpu = data;
1380 irqreturn_t ret = IRQ_NONE;
1381
1382 u32 intr = gpu_read(gpu, VIVS_HI_INTR_ACKNOWLEDGE);
1383
1384 if (intr != 0) {
1385 int event;
1386
1387 pm_runtime_mark_last_busy(gpu->dev);
1388
1389 dev_dbg(gpu->dev, "intr 0x%08x\n", intr);
1390
1391 if (intr & VIVS_HI_INTR_ACKNOWLEDGE_AXI_BUS_ERROR) {
1392 dev_err(gpu->dev, "AXI bus error\n");
1393 intr &= ~VIVS_HI_INTR_ACKNOWLEDGE_AXI_BUS_ERROR;
1394 }
1395
128a9b1d
LS		 1396 if (intr & VIVS_HI_INTR_ACKNOWLEDGE_MMU_EXCEPTION) {
1397 int i;
1398
1399 dev_err_ratelimited(gpu->dev,
1400 "MMU fault status 0x%08x\n",
1401 gpu_read(gpu, VIVS_MMUv2_STATUS));
1402 for (i = 0; i < 4; i++) {
1403 dev_err_ratelimited(gpu->dev,
1404 "MMU %d fault addr 0x%08x\n",
1405 i, gpu_read(gpu,
1406 VIVS_MMUv2_EXCEPTION_ADDR(i)));
1407 }
1408 intr &= ~VIVS_HI_INTR_ACKNOWLEDGE_MMU_EXCEPTION;
1409 }
1410
a8c21a54 1411 while ((event = ffs(intr)) != 0) {
f54d1867 1412 struct dma_fence *fence;
a8c21a54
T		 1413
1414 event -= 1;
1415
1416 intr &= ~(1 << event);
1417
1418 dev_dbg(gpu->dev, "event %u\n", event);
1419
1420 fence = gpu->event[event].fence;
1421 gpu->event[event].fence = NULL;
f54d1867 1422 dma_fence_signal(fence);
a8c21a54
T		 1423
1424 /*
1425 * Events can be processed out of order. Eg,
1426 * - allocate and queue event 0
1427 * - allocate event 1
1428 * - event 0 completes, we process it
1429 * - allocate and queue event 0
1430 * - event 1 and event 0 complete
1431 * we can end up processing event 0 first, then 1.
1432 */
1433 if (fence_after(fence->seqno, gpu->completed_fence))
1434 gpu->completed_fence = fence->seqno;
1435
1436 event_free(gpu, event);
a8c21a54
T		 1437 }
1438
1439 /* Retire the buffer objects in a work */
1440 etnaviv_queue_work(gpu->drm, &gpu->retire_work);
1441
1442 ret = IRQ_HANDLED;
1443 }
1444
1445 return ret;
1446}
1447
1448static int etnaviv_gpu_clk_enable(struct etnaviv_gpu *gpu)
1449{
1450 int ret;
1451
9c7310c0
LS		 1452 if (gpu->clk_bus) {
1453 ret = clk_prepare_enable(gpu->clk_bus);
1454 if (ret)
1455 return ret;
1456 }
a8c21a54 1457
9c7310c0
LS		 1458 if (gpu->clk_core) {
1459 ret = clk_prepare_enable(gpu->clk_core);
1460 if (ret)
1461 goto disable_clk_bus;
1462 }
1463
1464 if (gpu->clk_shader) {
1465 ret = clk_prepare_enable(gpu->clk_shader);
1466 if (ret)
1467 goto disable_clk_core;
a8c21a54
T		 1468 }
1469
1470 return 0;
9c7310c0
LS		 1471
1472disable_clk_core:
1473 if (gpu->clk_core)
1474 clk_disable_unprepare(gpu->clk_core);
1475disable_clk_bus:
1476 if (gpu->clk_bus)
1477 clk_disable_unprepare(gpu->clk_bus);
1478
1479 return ret;
a8c21a54
T		 1480}
1481
1482static int etnaviv_gpu_clk_disable(struct etnaviv_gpu *gpu)
1483{
9c7310c0
LS		 1484 if (gpu->clk_shader)
1485 clk_disable_unprepare(gpu->clk_shader);
1486 if (gpu->clk_core)
1487 clk_disable_unprepare(gpu->clk_core);
1488 if (gpu->clk_bus)
1489 clk_disable_unprepare(gpu->clk_bus);
a8c21a54
T		 1490
1491 return 0;
1492}
1493
b88163e3
LS		 1494int etnaviv_gpu_wait_idle(struct etnaviv_gpu *gpu, unsigned int timeout_ms)
1495{
1496 unsigned long timeout = jiffies + msecs_to_jiffies(timeout_ms);
1497
1498 do {
1499 u32 idle = gpu_read(gpu, VIVS_HI_IDLE_STATE);
1500
1501 if ((idle & gpu->idle_mask) == gpu->idle_mask)
1502 return 0;
1503
1504 if (time_is_before_jiffies(timeout)) {
1505 dev_warn(gpu->dev,
1506 "timed out waiting for idle: idle=0x%x\n",
1507 idle);
1508 return -ETIMEDOUT;
1509 }
1510
1511 udelay(5);
1512 } while (1);
1513}
1514
a8c21a54
T		 1515static int etnaviv_gpu_hw_suspend(struct etnaviv_gpu *gpu)
1516{
1517 if (gpu->buffer) {
a8c21a54
T		 1518 /* Replace the last WAIT with END */
1519 etnaviv_buffer_end(gpu);
1520
1521 /*
1522 * We know that only the FE is busy here, this should
1523 * happen quickly (as the WAIT is only 200 cycles). If
1524 * we fail, just warn and continue.
1525 */
b88163e3 1526 etnaviv_gpu_wait_idle(gpu, 100);
a8c21a54
T		 1527 }
1528
1529 return etnaviv_gpu_clk_disable(gpu);
1530}
1531
1532#ifdef CONFIG_PM
1533static int etnaviv_gpu_hw_resume(struct etnaviv_gpu *gpu)
1534{
1535 u32 clock;
1536 int ret;
1537
1538 ret = mutex_lock_killable(&gpu->lock);
1539 if (ret)
1540 return ret;
1541
1542 clock = VIVS_HI_CLOCK_CONTROL_DISABLE_DEBUG_REGISTERS |
1543 VIVS_HI_CLOCK_CONTROL_FSCALE_VAL(0x40);
1544
1545 etnaviv_gpu_load_clock(gpu, clock);
1546 etnaviv_gpu_hw_init(gpu);
1547
1548 gpu->switch_context = true;
f6086311 1549 gpu->exec_state = -1;
a8c21a54
T		 1550
1551 mutex_unlock(&gpu->lock);
1552
1553 return 0;
1554}
1555#endif
1556
1557static int etnaviv_gpu_bind(struct device *dev, struct device *master,
1558 void *data)
1559{
1560 struct drm_device *drm = data;
1561 struct etnaviv_drm_private *priv = drm->dev_private;
1562 struct etnaviv_gpu *gpu = dev_get_drvdata(dev);
1563 int ret;
1564
1565#ifdef CONFIG_PM
1566 ret = pm_runtime_get_sync(gpu->dev);
1567#else
1568 ret = etnaviv_gpu_clk_enable(gpu);
1569#endif
1570 if (ret < 0)
1571 return ret;
1572
1573 gpu->drm = drm;
f54d1867 1574 gpu->fence_context = dma_fence_context_alloc(1);
a8c21a54
T		 1575 spin_lock_init(&gpu->fence_spinlock);
1576
1577 INIT_LIST_HEAD(&gpu->active_cmd_list);
1578 INIT_WORK(&gpu->retire_work, retire_worker);
1579 INIT_WORK(&gpu->recover_work, recover_worker);
1580 init_waitqueue_head(&gpu->fence_event);
1581
946dd8d5
LS		 1582 setup_deferrable_timer(&gpu->hangcheck_timer, hangcheck_handler,
1583 (unsigned long)gpu);
a8c21a54
T		 1584
1585 priv->gpu[priv->num_gpus++] = gpu;
1586
1587 pm_runtime_mark_last_busy(gpu->dev);
1588 pm_runtime_put_autosuspend(gpu->dev);
1589
1590 return 0;
1591}
1592
1593static void etnaviv_gpu_unbind(struct device *dev, struct device *master,
1594 void *data)
1595{
1596 struct etnaviv_gpu *gpu = dev_get_drvdata(dev);
1597
1598 DBG("%s", dev_name(gpu->dev));
1599
1600 hangcheck_disable(gpu);
1601
1602#ifdef CONFIG_PM
1603 pm_runtime_get_sync(gpu->dev);
1604 pm_runtime_put_sync_suspend(gpu->dev);
1605#else
1606 etnaviv_gpu_hw_suspend(gpu);
1607#endif
1608
1609 if (gpu->buffer) {
ea1f5729 1610 etnaviv_cmdbuf_free(gpu->buffer);
a8c21a54
T		 1611 gpu->buffer = NULL;
1612 }
1613
e66774dd
LS		 1614 if (gpu->cmdbuf_suballoc) {
1615 etnaviv_cmdbuf_suballoc_destroy(gpu->cmdbuf_suballoc);
1616 gpu->cmdbuf_suballoc = NULL;
1617 }
1618
a8c21a54
T		 1619 if (gpu->mmu) {
1620 etnaviv_iommu_destroy(gpu->mmu);
1621 gpu->mmu = NULL;
1622 }
1623
1624 gpu->drm = NULL;
1625}
1626
1627static const struct component_ops gpu_ops = {
1628 .bind = etnaviv_gpu_bind,
1629 .unbind = etnaviv_gpu_unbind,
1630};
1631
1632static const struct of_device_id etnaviv_gpu_match[] = {
1633 {
1634 .compatible = "vivante,gc"
1635 },
1636 { /* sentinel */ }
1637};
1638
1639static int etnaviv_gpu_platform_probe(struct platform_device *pdev)
1640{
1641 struct device *dev = &pdev->dev;
1642 struct etnaviv_gpu *gpu;
dc227890 1643 int err;
a8c21a54
T		 1644
1645 gpu = devm_kzalloc(dev, sizeof(*gpu), GFP_KERNEL);
1646 if (!gpu)
1647 return -ENOMEM;
1648
1649 gpu->dev = &pdev->dev;
1650 mutex_init(&gpu->lock);
1651
a8c21a54
T		 1652 /* Map registers: */
1653 gpu->mmio = etnaviv_ioremap(pdev, NULL, dev_name(gpu->dev));
1654 if (IS_ERR(gpu->mmio))
1655 return PTR_ERR(gpu->mmio);
1656
1657 /* Get Interrupt: */
1658 gpu->irq = platform_get_irq(pdev, 0);
1659 if (gpu->irq < 0) {
db60eda3
FE		 1660 dev_err(dev, "failed to get irq: %d\n", gpu->irq);
1661 return gpu->irq;
a8c21a54
T		 1662 }
1663
1664 err = devm_request_irq(&pdev->dev, gpu->irq, irq_handler, 0,
1665 dev_name(gpu->dev), gpu);
1666 if (err) {
1667 dev_err(dev, "failed to request IRQ%u: %d\n", gpu->irq, err);
db60eda3 1668 return err;
a8c21a54
T		 1669 }
1670
1671 /* Get Clocks: */
1672 gpu->clk_bus = devm_clk_get(&pdev->dev, "bus");
1673 DBG("clk_bus: %p", gpu->clk_bus);
1674 if (IS_ERR(gpu->clk_bus))
1675 gpu->clk_bus = NULL;
1676
1677 gpu->clk_core = devm_clk_get(&pdev->dev, "core");
1678 DBG("clk_core: %p", gpu->clk_core);
1679 if (IS_ERR(gpu->clk_core))
1680 gpu->clk_core = NULL;
1681
1682 gpu->clk_shader = devm_clk_get(&pdev->dev, "shader");
1683 DBG("clk_shader: %p", gpu->clk_shader);
1684 if (IS_ERR(gpu->clk_shader))
1685 gpu->clk_shader = NULL;
1686
1687 /* TODO: figure out max mapped size */
1688 dev_set_drvdata(dev, gpu);
1689
1690 /*
1691 * We treat the device as initially suspended. The runtime PM
1692 * autosuspend delay is rather arbitary: no measurements have
1693 * yet been performed to determine an appropriate value.
1694 */
1695 pm_runtime_use_autosuspend(gpu->dev);
1696 pm_runtime_set_autosuspend_delay(gpu->dev, 200);
1697 pm_runtime_enable(gpu->dev);
1698
1699 err = component_add(&pdev->dev, &gpu_ops);
1700 if (err < 0) {
1701 dev_err(&pdev->dev, "failed to register component: %d\n", err);
db60eda3 1702 return err;
a8c21a54
T		 1703 }
1704
1705 return 0;
a8c21a54
T		 1706}
1707
1708static int etnaviv_gpu_platform_remove(struct platform_device *pdev)
1709{
1710 component_del(&pdev->dev, &gpu_ops);
1711 pm_runtime_disable(&pdev->dev);
1712 return 0;
1713}
1714
1715#ifdef CONFIG_PM
1716static int etnaviv_gpu_rpm_suspend(struct device *dev)
1717{
1718 struct etnaviv_gpu *gpu = dev_get_drvdata(dev);
1719 u32 idle, mask;
1720
1721 /* If we have outstanding fences, we're not idle */
1722 if (gpu->completed_fence != gpu->active_fence)
1723 return -EBUSY;
1724
1725 /* Check whether the hardware (except FE) is idle */
1726 mask = gpu->idle_mask & ~VIVS_HI_IDLE_STATE_FE;
1727 idle = gpu_read(gpu, VIVS_HI_IDLE_STATE) & mask;
1728 if (idle != mask)
1729 return -EBUSY;
1730
1731 return etnaviv_gpu_hw_suspend(gpu);
1732}
1733
1734static int etnaviv_gpu_rpm_resume(struct device *dev)
1735{
1736 struct etnaviv_gpu *gpu = dev_get_drvdata(dev);
1737 int ret;
1738
1739 ret = etnaviv_gpu_clk_enable(gpu);
1740 if (ret)
1741 return ret;
1742
1743 /* Re-initialise the basic hardware state */
1744 if (gpu->drm && gpu->buffer) {
1745 ret = etnaviv_gpu_hw_resume(gpu);
1746 if (ret) {
1747 etnaviv_gpu_clk_disable(gpu);
1748 return ret;
1749 }
1750 }
1751
1752 return 0;
1753}
1754#endif
1755
1756static const struct dev_pm_ops etnaviv_gpu_pm_ops = {
1757 SET_RUNTIME_PM_OPS(etnaviv_gpu_rpm_suspend, etnaviv_gpu_rpm_resume,
1758 NULL)
1759};
1760
1761struct platform_driver etnaviv_gpu_driver = {
1762 .driver = {
1763 .name = "etnaviv-gpu",
1764 .owner = THIS_MODULE,
1765 .pm = &etnaviv_gpu_pm_ops,
1766 .of_match_table = etnaviv_gpu_match,
1767 },
1768 .probe = etnaviv_gpu_platform_probe,
1769 .remove = etnaviv_gpu_platform_remove,
1770 .id_table = gpu_ids,
1771};
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