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1c248b7d ID |
1 | /* exynos_drm_drv.h |
2 | * | |
3 | * Copyright (c) 2011 Samsung Electronics Co., Ltd. | |
4 | * Authors: | |
5 | * Inki Dae <inki.dae@samsung.com> | |
6 | * Joonyoung Shim <jy0922.shim@samsung.com> | |
7 | * Seung-Woo Kim <sw0312.kim@samsung.com> | |
8 | * | |
d81aecb5 ID |
9 | * This program is free software; you can redistribute it and/or modify it |
10 | * under the terms of the GNU General Public License as published by the | |
11 | * Free Software Foundation; either version 2 of the License, or (at your | |
12 | * option) any later version. | |
1c248b7d ID |
13 | */ |
14 | ||
15 | #ifndef _EXYNOS_DRM_DRV_H_ | |
16 | #define _EXYNOS_DRM_DRV_H_ | |
17 | ||
d2c1bba3 | 18 | #include <drm/drmP.h> |
4f9eb94f | 19 | #include <linux/module.h> |
1c248b7d | 20 | |
b73d1230 | 21 | #define MAX_CRTC 3 |
864ee9e6 | 22 | #define MAX_PLANE 5 |
b73d1230 | 23 | #define MAX_FB_BUFFER 4 |
1c248b7d | 24 | |
5d3d0995 GP |
25 | #define DEFAULT_WIN 0 |
26 | ||
357193cd | 27 | #define to_exynos_crtc(x) container_of(x, struct exynos_drm_crtc, base) |
8837deea | 28 | #define to_exynos_plane(x) container_of(x, struct exynos_drm_plane, base) |
ffceaed6 | 29 | |
1c248b7d ID |
30 | /* this enumerates display type. */ |
31 | enum exynos_drm_output_type { | |
32 | EXYNOS_DISPLAY_TYPE_NONE, | |
33 | /* RGB or CPU Interface. */ | |
34 | EXYNOS_DISPLAY_TYPE_LCD, | |
35 | /* HDMI Interface. */ | |
36 | EXYNOS_DISPLAY_TYPE_HDMI, | |
b73d1230 ID |
37 | /* Virtual Display Interface. */ |
38 | EXYNOS_DISPLAY_TYPE_VIDI, | |
1c248b7d ID |
39 | }; |
40 | ||
0114f404 MS |
41 | struct exynos_drm_rect { |
42 | unsigned int x, y; | |
43 | unsigned int w, h; | |
44 | }; | |
45 | ||
1c248b7d | 46 | /* |
0114f404 | 47 | * Exynos drm plane state structure. |
1c248b7d | 48 | * |
0114f404 MS |
49 | * @base: plane_state object (contains drm_framebuffer pointer) |
50 | * @src: rectangle of the source image data to be displayed (clipped to | |
51 | * visible part). | |
52 | * @crtc: rectangle of the target image position on hardware screen | |
53 | * (clipped to visible part). | |
3cabaf7e JS |
54 | * @h_ratio: horizontal scaling ratio, 16.16 fixed point |
55 | * @v_ratio: vertical scaling ratio, 16.16 fixed point | |
0114f404 MS |
56 | * |
57 | * this structure consists plane state data that will be applied to hardware | |
58 | * specific overlay info. | |
59 | */ | |
60 | ||
61 | struct exynos_drm_plane_state { | |
62 | struct drm_plane_state base; | |
63 | struct exynos_drm_rect crtc; | |
64 | struct exynos_drm_rect src; | |
65 | unsigned int h_ratio; | |
66 | unsigned int v_ratio; | |
67 | }; | |
68 | ||
69 | static inline struct exynos_drm_plane_state * | |
70 | to_exynos_plane_state(struct drm_plane_state *state) | |
71 | { | |
72 | return container_of(state, struct exynos_drm_plane_state, base); | |
73 | } | |
74 | ||
75 | /* | |
76 | * Exynos drm common overlay structure. | |
77 | * | |
78 | * @base: plane object | |
40bdfb0a | 79 | * @index: hardware index of the overlay layer |
1c248b7d ID |
80 | * |
81 | * this structure is common to exynos SoC and its contents would be copied | |
82 | * to hardware specific overlay info. | |
83 | */ | |
8837deea GP |
84 | |
85 | struct exynos_drm_plane { | |
86 | struct drm_plane base; | |
fd2d2fc2 | 87 | const struct exynos_drm_plane_config *config; |
40bdfb0a | 88 | unsigned int index; |
1c248b7d ID |
89 | }; |
90 | ||
6178d3d1 MS |
91 | #define EXYNOS_DRM_PLANE_CAP_DOUBLE (1 << 0) |
92 | #define EXYNOS_DRM_PLANE_CAP_SCALE (1 << 1) | |
0ea72405 | 93 | #define EXYNOS_DRM_PLANE_CAP_ZPOS (1 << 2) |
6178d3d1 | 94 | |
fd2d2fc2 MS |
95 | /* |
96 | * Exynos DRM plane configuration structure. | |
97 | * | |
0ea72405 | 98 | * @zpos: initial z-position of the plane. |
fd2d2fc2 MS |
99 | * @type: type of the plane (primary, cursor or overlay). |
100 | * @pixel_formats: supported pixel formats. | |
101 | * @num_pixel_formats: number of elements in 'pixel_formats'. | |
102 | * @capabilities: supported features (see EXYNOS_DRM_PLANE_CAP_*) | |
103 | */ | |
104 | ||
105 | struct exynos_drm_plane_config { | |
106 | unsigned int zpos; | |
107 | enum drm_plane_type type; | |
108 | const uint32_t *pixel_formats; | |
109 | unsigned int num_pixel_formats; | |
110 | unsigned int capabilities; | |
111 | }; | |
112 | ||
1c248b7d | 113 | /* |
93bca243 | 114 | * Exynos drm crtc ops |
1c248b7d | 115 | * |
3cecda03 GP |
116 | * @enable: enable the device |
117 | * @disable: disable the device | |
1c248b7d ID |
118 | * @commit: set current hw specific display mode to hw. |
119 | * @enable_vblank: specific driver callback for enabling vblank interrupt. | |
120 | * @disable_vblank: specific driver callback for disabling vblank interrupt. | |
5625b341 | 121 | * @atomic_check: validate state |
d29c2c14 MS |
122 | * @atomic_begin: prepare device to receive an update |
123 | * @atomic_flush: mark the end of device update | |
9cc7610a GP |
124 | * @update_plane: apply hardware specific overlay data to registers. |
125 | * @disable_plane: disable hardware specific overlay. | |
5595d4d8 YC |
126 | * @te_handler: trigger to transfer video image at the tearing effect |
127 | * synchronization signal if there is a page flip request. | |
1c248b7d | 128 | */ |
93bca243 GP |
129 | struct exynos_drm_crtc; |
130 | struct exynos_drm_crtc_ops { | |
3cecda03 GP |
131 | void (*enable)(struct exynos_drm_crtc *crtc); |
132 | void (*disable)(struct exynos_drm_crtc *crtc); | |
93bca243 GP |
133 | void (*commit)(struct exynos_drm_crtc *crtc); |
134 | int (*enable_vblank)(struct exynos_drm_crtc *crtc); | |
135 | void (*disable_vblank)(struct exynos_drm_crtc *crtc); | |
5625b341 AH |
136 | int (*atomic_check)(struct exynos_drm_crtc *crtc, |
137 | struct drm_crtc_state *state); | |
d29c2c14 | 138 | void (*atomic_begin)(struct exynos_drm_crtc *crtc); |
1e1d1393 GP |
139 | void (*update_plane)(struct exynos_drm_crtc *crtc, |
140 | struct exynos_drm_plane *plane); | |
141 | void (*disable_plane)(struct exynos_drm_crtc *crtc, | |
142 | struct exynos_drm_plane *plane); | |
d29c2c14 | 143 | void (*atomic_flush)(struct exynos_drm_crtc *crtc); |
93bca243 | 144 | void (*te_handler)(struct exynos_drm_crtc *crtc); |
1c248b7d ID |
145 | }; |
146 | ||
f26b9343 AH |
147 | struct exynos_drm_clk { |
148 | void (*enable)(struct exynos_drm_clk *clk, bool enable); | |
149 | }; | |
150 | ||
2bf053eb GP |
151 | /* |
152 | * Exynos specific crtc structure. | |
153 | * | |
357193cd | 154 | * @base: crtc object. |
5d1741ad | 155 | * @type: one of EXYNOS_DISPLAY_TYPE_LCD and HDMI. |
2bf053eb GP |
156 | * @pipe: a crtc index created at load() with a new crtc object creation |
157 | * and the crtc object would be set to private->crtc array | |
158 | * to get a crtc object corresponding to this pipe from private->crtc | |
159 | * array when irq interrupt occurred. the reason of using this pipe is that | |
160 | * drm framework doesn't support multiple irq yet. | |
161 | * we can refer to the crtc to current hardware interrupt occurred through | |
162 | * this pipe value. | |
63498e30 | 163 | * @enabled: if the crtc is enabled or not |
e752747b | 164 | * @event: vblank event that is currently queued for flip |
c4533665 GP |
165 | * @wait_update: wait all pending planes updates to finish |
166 | * @pending_update: number of pending plane updates in this crtc | |
93bca243 GP |
167 | * @ops: pointer to callbacks for exynos drm specific functionality |
168 | * @ctx: A pointer to the crtc's implementation specific context | |
2bf053eb GP |
169 | */ |
170 | struct exynos_drm_crtc { | |
357193cd | 171 | struct drm_crtc base; |
5d1741ad | 172 | enum exynos_drm_output_type type; |
2bf053eb | 173 | unsigned int pipe; |
f3aaf762 | 174 | const struct exynos_drm_crtc_ops *ops; |
93bca243 | 175 | void *ctx; |
f26b9343 | 176 | struct exynos_drm_clk *pipe_clk; |
2bf053eb GP |
177 | }; |
178 | ||
f26b9343 AH |
179 | static inline void exynos_drm_pipe_clk_enable(struct exynos_drm_crtc *crtc, |
180 | bool enable) | |
181 | { | |
182 | if (crtc->pipe_clk) | |
183 | crtc->pipe_clk->enable(crtc->pipe_clk, enable); | |
184 | } | |
185 | ||
d7f1642c JS |
186 | struct exynos_drm_g2d_private { |
187 | struct device *dev; | |
188 | struct list_head inuse_cmdlist; | |
189 | struct list_head event_list; | |
2a3098ff | 190 | struct list_head userptr_list; |
d7f1642c JS |
191 | }; |
192 | ||
193 | struct drm_exynos_file_private { | |
194 | struct exynos_drm_g2d_private *g2d_priv; | |
5c76c5b1 | 195 | struct device *ipp_dev; |
d7f1642c JS |
196 | }; |
197 | ||
1c248b7d ID |
198 | /* |
199 | * Exynos drm private structure. | |
0519f9a1 ID |
200 | * |
201 | * @da_start: start address to device address space. | |
202 | * with iommu, device address space starts from this address | |
203 | * otherwise default one. | |
204 | * @da_space_size: size of device address space. | |
205 | * if 0 then default value is used for it. | |
f37cd5e8 | 206 | * @pipe: the pipe number for this crtc/manager. |
a379df19 GP |
207 | * @pending: the crtcs that have pending updates to finish |
208 | * @lock: protect access to @pending | |
209 | * @wait: wait an atomic commit to finish | |
1c248b7d ID |
210 | */ |
211 | struct exynos_drm_private { | |
212 | struct drm_fb_helper *fb_helper; | |
213 | ||
f43c3596 | 214 | struct device *dma_dev; |
f43c3596 | 215 | void *mapping; |
f37cd5e8 ID |
216 | |
217 | unsigned int pipe; | |
a379df19 GP |
218 | |
219 | /* for atomic commit */ | |
220 | u32 pending; | |
221 | spinlock_t lock; | |
222 | wait_queue_head_t wait; | |
1c248b7d ID |
223 | }; |
224 | ||
f43c3596 MS |
225 | static inline struct device *to_dma_dev(struct drm_device *dev) |
226 | { | |
227 | struct exynos_drm_private *priv = dev->dev_private; | |
228 | ||
229 | return priv->dma_dev; | |
230 | } | |
231 | ||
1c248b7d ID |
232 | /* |
233 | * Exynos drm sub driver structure. | |
234 | * | |
235 | * @list: sub driver has its own list object to register to exynos drm driver. | |
677e84c1 | 236 | * @dev: pointer to device object for subdrv device driver. |
1c248b7d ID |
237 | * @drm_dev: pointer to drm_device and this pointer would be set |
238 | * when sub driver calls exynos_drm_subdrv_register(). | |
239 | * @probe: this callback would be called by exynos drm driver after | |
f37cd5e8 | 240 | * subdrv is registered to it. |
1c248b7d | 241 | * @remove: this callback is used to release resources created |
f37cd5e8 | 242 | * by probe callback. |
9084f7b8 JS |
243 | * @open: this would be called with drm device file open. |
244 | * @close: this would be called with drm device file close. | |
1c248b7d ID |
245 | */ |
246 | struct exynos_drm_subdrv { | |
247 | struct list_head list; | |
677e84c1 | 248 | struct device *dev; |
1c248b7d ID |
249 | struct drm_device *drm_dev; |
250 | ||
41c24346 | 251 | int (*probe)(struct drm_device *drm_dev, struct device *dev); |
29cb6025 | 252 | void (*remove)(struct drm_device *drm_dev, struct device *dev); |
9084f7b8 JS |
253 | int (*open)(struct drm_device *drm_dev, struct device *dev, |
254 | struct drm_file *file); | |
255 | void (*close)(struct drm_device *drm_dev, struct device *dev, | |
256 | struct drm_file *file); | |
1c248b7d ID |
257 | }; |
258 | ||
f37cd5e8 | 259 | /* This function would be called by non kms drivers such as g2d and ipp. */ |
1c248b7d ID |
260 | int exynos_drm_subdrv_register(struct exynos_drm_subdrv *drm_subdrv); |
261 | ||
132a5b91 | 262 | /* this function removes subdrv list from exynos drm driver */ |
1c248b7d ID |
263 | int exynos_drm_subdrv_unregister(struct exynos_drm_subdrv *drm_subdrv); |
264 | ||
f37cd5e8 ID |
265 | int exynos_drm_device_subdrv_probe(struct drm_device *dev); |
266 | int exynos_drm_device_subdrv_remove(struct drm_device *dev); | |
9084f7b8 JS |
267 | int exynos_drm_subdrv_open(struct drm_device *dev, struct drm_file *file); |
268 | void exynos_drm_subdrv_close(struct drm_device *dev, struct drm_file *file); | |
269 | ||
14b6873a | 270 | #ifdef CONFIG_DRM_EXYNOS_DPI |
2b8376c8 GP |
271 | struct drm_encoder *exynos_dpi_probe(struct device *dev); |
272 | int exynos_dpi_remove(struct drm_encoder *encoder); | |
273 | int exynos_dpi_bind(struct drm_device *dev, struct drm_encoder *encoder); | |
14b6873a | 274 | #else |
2b8376c8 | 275 | static inline struct drm_encoder * |
dcdffeda | 276 | exynos_dpi_probe(struct device *dev) { return NULL; } |
2b8376c8 | 277 | static inline int exynos_dpi_remove(struct drm_encoder *encoder) |
1c9ff4ab GP |
278 | { |
279 | return 0; | |
280 | } | |
a2986e80 | 281 | static inline int exynos_dpi_bind(struct drm_device *dev, |
2b8376c8 | 282 | struct drm_encoder *encoder) |
a2986e80 GP |
283 | { |
284 | return 0; | |
285 | } | |
14b6873a AH |
286 | #endif |
287 | ||
a379df19 | 288 | int exynos_atomic_commit(struct drm_device *dev, struct drm_atomic_state *state, |
1b3f09d8 | 289 | bool nonblock); |
38d868e4 | 290 | int exynos_atomic_check(struct drm_device *dev, struct drm_atomic_state *state); |
a379df19 | 291 | |
f37cd5e8 | 292 | |
f37cd5e8 | 293 | extern struct platform_driver fimd_driver; |
c8466a91 | 294 | extern struct platform_driver exynos5433_decon_driver; |
96976c3d | 295 | extern struct platform_driver decon_driver; |
1417f109 | 296 | extern struct platform_driver dp_driver; |
7eb8f069 | 297 | extern struct platform_driver dsi_driver; |
132a5b91 | 298 | extern struct platform_driver mixer_driver; |
f37cd5e8 | 299 | extern struct platform_driver hdmi_driver; |
b73d1230 | 300 | extern struct platform_driver vidi_driver; |
d7f1642c | 301 | extern struct platform_driver g2d_driver; |
16102edb | 302 | extern struct platform_driver fimc_driver; |
bea8a429 | 303 | extern struct platform_driver rotator_driver; |
f2646380 | 304 | extern struct platform_driver gsc_driver; |
cb471f14 | 305 | extern struct platform_driver ipp_driver; |
77bbd891 | 306 | extern struct platform_driver mic_driver; |
1c248b7d | 307 | #endif |