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da52605e RZ |
1 | /* Hisilicon Hibmc SoC drm driver |
2 | * | |
3 | * Based on the bochs drm driver. | |
4 | * | |
5 | * Copyright (c) 2016 Huawei Limited. | |
6 | * | |
7 | * Author: | |
8 | * Rongrong Zou <zourongrong@huawei.com> | |
9 | * Rongrong Zou <zourongrong@gmail.com> | |
10 | * Jianhua Li <lijianhua@huawei.com> | |
11 | * | |
12 | * This program is free software; you can redistribute it and/or modify | |
13 | * it under the terms of the GNU General Public License as published by | |
14 | * the Free Software Foundation; either version 2 of the License, or | |
15 | * (at your option) any later version. | |
16 | * | |
17 | */ | |
18 | ||
19 | #include <drm/drm_atomic.h> | |
20 | #include <drm/drm_atomic_helper.h> | |
21 | #include <drm/drm_crtc_helper.h> | |
22 | #include <drm/drm_plane_helper.h> | |
23 | ||
24 | #include "hibmc_drm_drv.h" | |
25 | #include "hibmc_drm_regs.h" | |
26 | ||
27 | struct hibmc_display_panel_pll { | |
28 | unsigned long M; | |
29 | unsigned long N; | |
30 | unsigned long OD; | |
31 | unsigned long POD; | |
32 | }; | |
33 | ||
34 | struct hibmc_dislay_pll_config { | |
35 | unsigned long hdisplay; | |
36 | unsigned long vdisplay; | |
37 | u32 pll1_config_value; | |
38 | u32 pll2_config_value; | |
39 | }; | |
40 | ||
41 | static const struct hibmc_dislay_pll_config hibmc_pll_table[] = { | |
42 | {800, 600, CRT_PLL1_HS_40MHZ, CRT_PLL2_HS_40MHZ}, | |
43 | {1024, 768, CRT_PLL1_HS_65MHZ, CRT_PLL2_HS_65MHZ}, | |
44 | {1152, 864, CRT_PLL1_HS_80MHZ_1152, CRT_PLL2_HS_80MHZ}, | |
45 | {1280, 768, CRT_PLL1_HS_80MHZ, CRT_PLL2_HS_80MHZ}, | |
46 | {1280, 720, CRT_PLL1_HS_74MHZ, CRT_PLL2_HS_74MHZ}, | |
47 | {1280, 960, CRT_PLL1_HS_108MHZ, CRT_PLL2_HS_108MHZ}, | |
48 | {1280, 1024, CRT_PLL1_HS_108MHZ, CRT_PLL2_HS_108MHZ}, | |
49 | {1600, 1200, CRT_PLL1_HS_162MHZ, CRT_PLL2_HS_162MHZ}, | |
50 | {1920, 1080, CRT_PLL1_HS_148MHZ, CRT_PLL2_HS_148MHZ}, | |
51 | {1920, 1200, CRT_PLL1_HS_193MHZ, CRT_PLL2_HS_193MHZ}, | |
52 | }; | |
53 | ||
54 | #define PADDING(align, data) (((data) + (align) - 1) & (~((align) - 1))) | |
55 | ||
56 | static int hibmc_plane_atomic_check(struct drm_plane *plane, | |
57 | struct drm_plane_state *state) | |
58 | { | |
59 | struct drm_framebuffer *fb = state->fb; | |
60 | struct drm_crtc *crtc = state->crtc; | |
61 | struct drm_crtc_state *crtc_state; | |
62 | u32 src_w = state->src_w >> 16; | |
63 | u32 src_h = state->src_h >> 16; | |
64 | ||
65 | if (!crtc || !fb) | |
66 | return 0; | |
67 | ||
68 | crtc_state = drm_atomic_get_crtc_state(state->state, crtc); | |
69 | if (IS_ERR(crtc_state)) | |
70 | return PTR_ERR(crtc_state); | |
71 | ||
72 | if (src_w != state->crtc_w || src_h != state->crtc_h) { | |
73 | DRM_DEBUG_ATOMIC("scale not support\n"); | |
74 | return -EINVAL; | |
75 | } | |
76 | ||
77 | if (state->crtc_x < 0 || state->crtc_y < 0) { | |
78 | DRM_DEBUG_ATOMIC("crtc_x/y of drm_plane state is invalid\n"); | |
79 | return -EINVAL; | |
80 | } | |
81 | ||
82 | if (state->crtc_x + state->crtc_w > | |
83 | crtc_state->adjusted_mode.hdisplay || | |
84 | state->crtc_y + state->crtc_h > | |
85 | crtc_state->adjusted_mode.vdisplay) { | |
86 | DRM_DEBUG_ATOMIC("visible portion of plane is invalid\n"); | |
87 | return -EINVAL; | |
88 | } | |
89 | ||
90 | return 0; | |
91 | } | |
92 | ||
93 | static void hibmc_plane_atomic_update(struct drm_plane *plane, | |
94 | struct drm_plane_state *old_state) | |
95 | { | |
96 | struct drm_plane_state *state = plane->state; | |
97 | u32 reg; | |
98 | int ret; | |
99 | u64 gpu_addr = 0; | |
100 | unsigned int line_l; | |
101 | struct hibmc_drm_private *priv = plane->dev->dev_private; | |
102 | struct hibmc_framebuffer *hibmc_fb; | |
103 | struct hibmc_bo *bo; | |
104 | ||
105 | if (!state->fb) | |
106 | return; | |
107 | ||
108 | hibmc_fb = to_hibmc_framebuffer(state->fb); | |
109 | bo = gem_to_hibmc_bo(hibmc_fb->obj); | |
110 | ret = ttm_bo_reserve(&bo->bo, true, false, NULL); | |
111 | if (ret) { | |
112 | DRM_ERROR("failed to reserve ttm_bo: %d", ret); | |
113 | return; | |
114 | } | |
115 | ||
116 | ret = hibmc_bo_pin(bo, TTM_PL_FLAG_VRAM, &gpu_addr); | |
117 | ttm_bo_unreserve(&bo->bo); | |
118 | if (ret) { | |
119 | DRM_ERROR("failed to pin hibmc_bo: %d", ret); | |
120 | return; | |
121 | } | |
122 | ||
123 | writel(gpu_addr, priv->mmio + HIBMC_CRT_FB_ADDRESS); | |
124 | ||
272725c7 | 125 | reg = state->fb->width * (state->fb->format->cpp[0]); |
da52605e RZ |
126 | /* now line_pad is 16 */ |
127 | reg = PADDING(16, reg); | |
128 | ||
272725c7 | 129 | line_l = state->fb->width * state->fb->format->cpp[0]; |
da52605e RZ |
130 | line_l = PADDING(16, line_l); |
131 | writel(HIBMC_FIELD(HIBMC_CRT_FB_WIDTH_WIDTH, reg) | | |
132 | HIBMC_FIELD(HIBMC_CRT_FB_WIDTH_OFFS, line_l), | |
133 | priv->mmio + HIBMC_CRT_FB_WIDTH); | |
134 | ||
135 | /* SET PIXEL FORMAT */ | |
136 | reg = readl(priv->mmio + HIBMC_CRT_DISP_CTL); | |
137 | reg &= ~HIBMC_CRT_DISP_CTL_FORMAT_MASK; | |
138 | reg |= HIBMC_FIELD(HIBMC_CRT_DISP_CTL_FORMAT, | |
272725c7 | 139 | state->fb->format->cpp[0] * 8 / 16); |
da52605e RZ |
140 | writel(reg, priv->mmio + HIBMC_CRT_DISP_CTL); |
141 | } | |
142 | ||
143 | static const u32 channel_formats1[] = { | |
144 | DRM_FORMAT_RGB565, DRM_FORMAT_BGR565, DRM_FORMAT_RGB888, | |
145 | DRM_FORMAT_BGR888, DRM_FORMAT_XRGB8888, DRM_FORMAT_XBGR8888, | |
146 | DRM_FORMAT_RGBA8888, DRM_FORMAT_BGRA8888, DRM_FORMAT_ARGB8888, | |
147 | DRM_FORMAT_ABGR8888 | |
148 | }; | |
149 | ||
150 | static struct drm_plane_funcs hibmc_plane_funcs = { | |
151 | .update_plane = drm_atomic_helper_update_plane, | |
152 | .disable_plane = drm_atomic_helper_disable_plane, | |
da52605e RZ |
153 | .destroy = drm_plane_cleanup, |
154 | .reset = drm_atomic_helper_plane_reset, | |
155 | .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state, | |
156 | .atomic_destroy_state = drm_atomic_helper_plane_destroy_state, | |
157 | }; | |
158 | ||
159 | static const struct drm_plane_helper_funcs hibmc_plane_helper_funcs = { | |
160 | .atomic_check = hibmc_plane_atomic_check, | |
161 | .atomic_update = hibmc_plane_atomic_update, | |
162 | }; | |
163 | ||
164 | static struct drm_plane *hibmc_plane_init(struct hibmc_drm_private *priv) | |
165 | { | |
166 | struct drm_device *dev = priv->dev; | |
167 | struct drm_plane *plane; | |
168 | int ret = 0; | |
169 | ||
170 | plane = devm_kzalloc(dev->dev, sizeof(*plane), GFP_KERNEL); | |
171 | if (!plane) { | |
172 | DRM_ERROR("failed to alloc memory when init plane\n"); | |
173 | return ERR_PTR(-ENOMEM); | |
174 | } | |
175 | /* | |
176 | * plane init | |
177 | * TODO: Now only support primary plane, overlay planes | |
178 | * need to do. | |
179 | */ | |
180 | ret = drm_universal_plane_init(dev, plane, 1, &hibmc_plane_funcs, | |
181 | channel_formats1, | |
182 | ARRAY_SIZE(channel_formats1), | |
e6fc3b68 | 183 | NULL, |
da52605e RZ |
184 | DRM_PLANE_TYPE_PRIMARY, |
185 | NULL); | |
186 | if (ret) { | |
187 | DRM_ERROR("failed to init plane: %d\n", ret); | |
188 | return ERR_PTR(ret); | |
189 | } | |
190 | ||
191 | drm_plane_helper_add(plane, &hibmc_plane_helper_funcs); | |
192 | return plane; | |
193 | } | |
194 | ||
0b20a0f8 LP |
195 | static void hibmc_crtc_atomic_enable(struct drm_crtc *crtc, |
196 | struct drm_crtc_state *old_state) | |
da52605e RZ |
197 | { |
198 | unsigned int reg; | |
199 | struct hibmc_drm_private *priv = crtc->dev->dev_private; | |
200 | ||
201 | hibmc_set_power_mode(priv, HIBMC_PW_MODE_CTL_MODE_MODE0); | |
202 | ||
203 | /* Enable display power gate & LOCALMEM power gate*/ | |
204 | reg = readl(priv->mmio + HIBMC_CURRENT_GATE); | |
205 | reg &= ~HIBMC_CURR_GATE_LOCALMEM_MASK; | |
206 | reg &= ~HIBMC_CURR_GATE_DISPLAY_MASK; | |
207 | reg |= HIBMC_CURR_GATE_LOCALMEM(1); | |
208 | reg |= HIBMC_CURR_GATE_DISPLAY(1); | |
209 | hibmc_set_current_gate(priv, reg); | |
210 | drm_crtc_vblank_on(crtc); | |
211 | } | |
212 | ||
64581714 LP |
213 | static void hibmc_crtc_atomic_disable(struct drm_crtc *crtc, |
214 | struct drm_crtc_state *old_state) | |
da52605e RZ |
215 | { |
216 | unsigned int reg; | |
217 | struct hibmc_drm_private *priv = crtc->dev->dev_private; | |
218 | ||
219 | drm_crtc_vblank_off(crtc); | |
220 | ||
221 | hibmc_set_power_mode(priv, HIBMC_PW_MODE_CTL_MODE_SLEEP); | |
222 | ||
223 | /* Enable display power gate & LOCALMEM power gate*/ | |
224 | reg = readl(priv->mmio + HIBMC_CURRENT_GATE); | |
225 | reg &= ~HIBMC_CURR_GATE_LOCALMEM_MASK; | |
226 | reg &= ~HIBMC_CURR_GATE_DISPLAY_MASK; | |
227 | reg |= HIBMC_CURR_GATE_LOCALMEM(0); | |
228 | reg |= HIBMC_CURR_GATE_DISPLAY(0); | |
229 | hibmc_set_current_gate(priv, reg); | |
230 | } | |
231 | ||
232 | static unsigned int format_pll_reg(void) | |
233 | { | |
234 | unsigned int pllreg = 0; | |
235 | struct hibmc_display_panel_pll pll = {0}; | |
236 | ||
237 | /* | |
238 | * Note that all PLL's have the same format. Here, | |
239 | * we just use Panel PLL parameter to work out the bit | |
240 | * fields in the register.On returning a 32 bit number, the value can | |
241 | * be applied to any PLL in the calling function. | |
242 | */ | |
243 | pllreg |= HIBMC_FIELD(HIBMC_PLL_CTRL_BYPASS, 0); | |
244 | pllreg |= HIBMC_FIELD(HIBMC_PLL_CTRL_POWER, 1); | |
245 | pllreg |= HIBMC_FIELD(HIBMC_PLL_CTRL_INPUT, 0); | |
246 | pllreg |= HIBMC_FIELD(HIBMC_PLL_CTRL_POD, pll.POD); | |
247 | pllreg |= HIBMC_FIELD(HIBMC_PLL_CTRL_OD, pll.OD); | |
248 | pllreg |= HIBMC_FIELD(HIBMC_PLL_CTRL_N, pll.N); | |
249 | pllreg |= HIBMC_FIELD(HIBMC_PLL_CTRL_M, pll.M); | |
250 | ||
251 | return pllreg; | |
252 | } | |
253 | ||
254 | static void set_vclock_hisilicon(struct drm_device *dev, unsigned long pll) | |
255 | { | |
256 | u32 val; | |
257 | struct hibmc_drm_private *priv = dev->dev_private; | |
258 | ||
259 | val = readl(priv->mmio + CRT_PLL1_HS); | |
260 | val &= ~(CRT_PLL1_HS_OUTER_BYPASS(1)); | |
261 | writel(val, priv->mmio + CRT_PLL1_HS); | |
262 | ||
263 | val = CRT_PLL1_HS_INTER_BYPASS(1) | CRT_PLL1_HS_POWERON(1); | |
264 | writel(val, priv->mmio + CRT_PLL1_HS); | |
265 | ||
266 | writel(pll, priv->mmio + CRT_PLL1_HS); | |
267 | ||
268 | usleep_range(1000, 2000); | |
269 | ||
270 | val = pll & ~(CRT_PLL1_HS_POWERON(1)); | |
271 | writel(val, priv->mmio + CRT_PLL1_HS); | |
272 | ||
273 | usleep_range(1000, 2000); | |
274 | ||
275 | val &= ~(CRT_PLL1_HS_INTER_BYPASS(1)); | |
276 | writel(val, priv->mmio + CRT_PLL1_HS); | |
277 | ||
278 | usleep_range(1000, 2000); | |
279 | ||
280 | val |= CRT_PLL1_HS_OUTER_BYPASS(1); | |
281 | writel(val, priv->mmio + CRT_PLL1_HS); | |
282 | } | |
283 | ||
284 | static void get_pll_config(unsigned long x, unsigned long y, | |
285 | u32 *pll1, u32 *pll2) | |
286 | { | |
287 | int i; | |
288 | int count = ARRAY_SIZE(hibmc_pll_table); | |
289 | ||
290 | for (i = 0; i < count; i++) { | |
291 | if (hibmc_pll_table[i].hdisplay == x && | |
292 | hibmc_pll_table[i].vdisplay == y) { | |
293 | *pll1 = hibmc_pll_table[i].pll1_config_value; | |
294 | *pll2 = hibmc_pll_table[i].pll2_config_value; | |
295 | return; | |
296 | } | |
297 | } | |
298 | ||
299 | /* if found none, we use default value */ | |
300 | *pll1 = CRT_PLL1_HS_25MHZ; | |
301 | *pll2 = CRT_PLL2_HS_25MHZ; | |
302 | } | |
303 | ||
304 | /* | |
305 | * This function takes care the extra registers and bit fields required to | |
306 | * setup a mode in board. | |
307 | * Explanation about Display Control register: | |
308 | * FPGA only supports 7 predefined pixel clocks, and clock select is | |
309 | * in bit 4:0 of new register 0x802a8. | |
310 | */ | |
311 | static unsigned int display_ctrl_adjust(struct drm_device *dev, | |
312 | struct drm_display_mode *mode, | |
313 | unsigned int ctrl) | |
314 | { | |
315 | unsigned long x, y; | |
316 | u32 pll1; /* bit[31:0] of PLL */ | |
317 | u32 pll2; /* bit[63:32] of PLL */ | |
318 | struct hibmc_drm_private *priv = dev->dev_private; | |
319 | ||
320 | x = mode->hdisplay; | |
321 | y = mode->vdisplay; | |
322 | ||
323 | get_pll_config(x, y, &pll1, &pll2); | |
324 | writel(pll2, priv->mmio + CRT_PLL2_HS); | |
325 | set_vclock_hisilicon(dev, pll1); | |
326 | ||
327 | /* | |
328 | * Hisilicon has to set up the top-left and bottom-right | |
329 | * registers as well. | |
330 | * Note that normal chip only use those two register for | |
331 | * auto-centering mode. | |
332 | */ | |
333 | writel(HIBMC_FIELD(HIBMC_CRT_AUTO_CENTERING_TL_TOP, 0) | | |
334 | HIBMC_FIELD(HIBMC_CRT_AUTO_CENTERING_TL_LEFT, 0), | |
335 | priv->mmio + HIBMC_CRT_AUTO_CENTERING_TL); | |
336 | ||
337 | writel(HIBMC_FIELD(HIBMC_CRT_AUTO_CENTERING_BR_BOTTOM, y - 1) | | |
338 | HIBMC_FIELD(HIBMC_CRT_AUTO_CENTERING_BR_RIGHT, x - 1), | |
339 | priv->mmio + HIBMC_CRT_AUTO_CENTERING_BR); | |
340 | ||
341 | /* | |
342 | * Assume common fields in ctrl have been properly set before | |
343 | * calling this function. | |
344 | * This function only sets the extra fields in ctrl. | |
345 | */ | |
346 | ||
347 | /* Set bit 25 of display controller: Select CRT or VGA clock */ | |
348 | ctrl &= ~HIBMC_CRT_DISP_CTL_CRTSELECT_MASK; | |
349 | ctrl &= ~HIBMC_CRT_DISP_CTL_CLOCK_PHASE_MASK; | |
350 | ||
351 | ctrl |= HIBMC_CRT_DISP_CTL_CRTSELECT(HIBMC_CRTSELECT_CRT); | |
352 | ||
353 | /* clock_phase_polarity is 0 */ | |
354 | ctrl |= HIBMC_CRT_DISP_CTL_CLOCK_PHASE(0); | |
355 | ||
356 | writel(ctrl, priv->mmio + HIBMC_CRT_DISP_CTL); | |
357 | ||
358 | return ctrl; | |
359 | } | |
360 | ||
361 | static void hibmc_crtc_mode_set_nofb(struct drm_crtc *crtc) | |
362 | { | |
363 | unsigned int val; | |
364 | struct drm_display_mode *mode = &crtc->state->mode; | |
365 | struct drm_device *dev = crtc->dev; | |
366 | struct hibmc_drm_private *priv = dev->dev_private; | |
367 | int width = mode->hsync_end - mode->hsync_start; | |
368 | int height = mode->vsync_end - mode->vsync_start; | |
369 | ||
370 | writel(format_pll_reg(), priv->mmio + HIBMC_CRT_PLL_CTRL); | |
371 | writel(HIBMC_FIELD(HIBMC_CRT_HORZ_TOTAL_TOTAL, mode->htotal - 1) | | |
372 | HIBMC_FIELD(HIBMC_CRT_HORZ_TOTAL_DISP_END, mode->hdisplay - 1), | |
373 | priv->mmio + HIBMC_CRT_HORZ_TOTAL); | |
374 | ||
375 | writel(HIBMC_FIELD(HIBMC_CRT_HORZ_SYNC_WIDTH, width) | | |
376 | HIBMC_FIELD(HIBMC_CRT_HORZ_SYNC_START, mode->hsync_start - 1), | |
377 | priv->mmio + HIBMC_CRT_HORZ_SYNC); | |
378 | ||
379 | writel(HIBMC_FIELD(HIBMC_CRT_VERT_TOTAL_TOTAL, mode->vtotal - 1) | | |
380 | HIBMC_FIELD(HIBMC_CRT_VERT_TOTAL_DISP_END, mode->vdisplay - 1), | |
381 | priv->mmio + HIBMC_CRT_VERT_TOTAL); | |
382 | ||
383 | writel(HIBMC_FIELD(HIBMC_CRT_VERT_SYNC_HEIGHT, height) | | |
384 | HIBMC_FIELD(HIBMC_CRT_VERT_SYNC_START, mode->vsync_start - 1), | |
385 | priv->mmio + HIBMC_CRT_VERT_SYNC); | |
386 | ||
387 | val = HIBMC_FIELD(HIBMC_CRT_DISP_CTL_VSYNC_PHASE, 0); | |
388 | val |= HIBMC_FIELD(HIBMC_CRT_DISP_CTL_HSYNC_PHASE, 0); | |
389 | val |= HIBMC_CRT_DISP_CTL_TIMING(1); | |
390 | val |= HIBMC_CRT_DISP_CTL_PLANE(1); | |
391 | ||
392 | display_ctrl_adjust(dev, mode, val); | |
393 | } | |
394 | ||
395 | static void hibmc_crtc_atomic_begin(struct drm_crtc *crtc, | |
396 | struct drm_crtc_state *old_state) | |
397 | { | |
398 | unsigned int reg; | |
399 | struct drm_device *dev = crtc->dev; | |
400 | struct hibmc_drm_private *priv = dev->dev_private; | |
401 | ||
402 | hibmc_set_power_mode(priv, HIBMC_PW_MODE_CTL_MODE_MODE0); | |
403 | ||
404 | /* Enable display power gate & LOCALMEM power gate*/ | |
405 | reg = readl(priv->mmio + HIBMC_CURRENT_GATE); | |
406 | reg &= ~HIBMC_CURR_GATE_DISPLAY_MASK; | |
407 | reg &= ~HIBMC_CURR_GATE_LOCALMEM_MASK; | |
408 | reg |= HIBMC_CURR_GATE_DISPLAY(1); | |
409 | reg |= HIBMC_CURR_GATE_LOCALMEM(1); | |
410 | hibmc_set_current_gate(priv, reg); | |
411 | ||
412 | /* We can add more initialization as needed. */ | |
413 | } | |
414 | ||
415 | static void hibmc_crtc_atomic_flush(struct drm_crtc *crtc, | |
416 | struct drm_crtc_state *old_state) | |
417 | ||
418 | { | |
419 | unsigned long flags; | |
420 | ||
421 | spin_lock_irqsave(&crtc->dev->event_lock, flags); | |
422 | if (crtc->state->event) | |
423 | drm_crtc_send_vblank_event(crtc, crtc->state->event); | |
424 | crtc->state->event = NULL; | |
425 | spin_unlock_irqrestore(&crtc->dev->event_lock, flags); | |
426 | } | |
427 | ||
14de02cd SG |
428 | static int hibmc_crtc_enable_vblank(struct drm_crtc *crtc) |
429 | { | |
430 | struct hibmc_drm_private *priv = crtc->dev->dev_private; | |
431 | ||
432 | writel(HIBMC_RAW_INTERRUPT_EN_VBLANK(1), | |
433 | priv->mmio + HIBMC_RAW_INTERRUPT_EN); | |
434 | ||
435 | return 0; | |
436 | } | |
437 | ||
438 | static void hibmc_crtc_disable_vblank(struct drm_crtc *crtc) | |
439 | { | |
440 | struct hibmc_drm_private *priv = crtc->dev->dev_private; | |
441 | ||
442 | writel(HIBMC_RAW_INTERRUPT_EN_VBLANK(0), | |
443 | priv->mmio + HIBMC_RAW_INTERRUPT_EN); | |
444 | } | |
445 | ||
da52605e RZ |
446 | static const struct drm_crtc_funcs hibmc_crtc_funcs = { |
447 | .page_flip = drm_atomic_helper_page_flip, | |
448 | .set_config = drm_atomic_helper_set_config, | |
449 | .destroy = drm_crtc_cleanup, | |
450 | .reset = drm_atomic_helper_crtc_reset, | |
451 | .atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state, | |
452 | .atomic_destroy_state = drm_atomic_helper_crtc_destroy_state, | |
14de02cd SG |
453 | .enable_vblank = hibmc_crtc_enable_vblank, |
454 | .disable_vblank = hibmc_crtc_disable_vblank, | |
da52605e RZ |
455 | }; |
456 | ||
457 | static const struct drm_crtc_helper_funcs hibmc_crtc_helper_funcs = { | |
da52605e RZ |
458 | .mode_set_nofb = hibmc_crtc_mode_set_nofb, |
459 | .atomic_begin = hibmc_crtc_atomic_begin, | |
460 | .atomic_flush = hibmc_crtc_atomic_flush, | |
0b20a0f8 | 461 | .atomic_enable = hibmc_crtc_atomic_enable, |
64581714 | 462 | .atomic_disable = hibmc_crtc_atomic_disable, |
da52605e RZ |
463 | }; |
464 | ||
465 | int hibmc_de_init(struct hibmc_drm_private *priv) | |
466 | { | |
467 | struct drm_device *dev = priv->dev; | |
468 | struct drm_crtc *crtc; | |
469 | struct drm_plane *plane; | |
470 | int ret; | |
471 | ||
472 | plane = hibmc_plane_init(priv); | |
473 | if (IS_ERR(plane)) { | |
474 | DRM_ERROR("failed to create plane: %ld\n", PTR_ERR(plane)); | |
475 | return PTR_ERR(plane); | |
476 | } | |
477 | ||
478 | crtc = devm_kzalloc(dev->dev, sizeof(*crtc), GFP_KERNEL); | |
479 | if (!crtc) { | |
480 | DRM_ERROR("failed to alloc memory when init crtc\n"); | |
481 | return -ENOMEM; | |
482 | } | |
483 | ||
484 | ret = drm_crtc_init_with_planes(dev, crtc, plane, | |
485 | NULL, &hibmc_crtc_funcs, NULL); | |
486 | if (ret) { | |
487 | DRM_ERROR("failed to init crtc: %d\n", ret); | |
488 | return ret; | |
489 | } | |
490 | ||
491 | ret = drm_mode_crtc_set_gamma_size(crtc, 256); | |
492 | if (ret) { | |
493 | DRM_ERROR("failed to set gamma size: %d\n", ret); | |
494 | return ret; | |
495 | } | |
496 | drm_crtc_helper_add(crtc, &hibmc_crtc_helper_funcs); | |
497 | ||
498 | return 0; | |
499 | } |