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Commit | Line | Data |
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2017263e BG |
1 | /* |
2 | * Copyright © 2008 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | * Keith Packard <keithp@keithp.com> | |
26 | * | |
27 | */ | |
28 | ||
29 | #include <linux/seq_file.h> | |
f3cd474b | 30 | #include <linux/debugfs.h> |
5a0e3ad6 | 31 | #include <linux/slab.h> |
2d1a8a48 | 32 | #include <linux/export.h> |
6d2b8885 | 33 | #include <linux/list_sort.h> |
ec013e7f | 34 | #include <asm/msr-index.h> |
760285e7 | 35 | #include <drm/drmP.h> |
4e5359cd | 36 | #include "intel_drv.h" |
e5c65260 | 37 | #include "intel_ringbuffer.h" |
760285e7 | 38 | #include <drm/i915_drm.h> |
2017263e BG |
39 | #include "i915_drv.h" |
40 | ||
2017263e BG |
41 | #if defined(CONFIG_DEBUG_FS) |
42 | ||
f13d3f73 | 43 | enum { |
69dc4987 | 44 | ACTIVE_LIST, |
f13d3f73 | 45 | INACTIVE_LIST, |
d21d5975 | 46 | PINNED_LIST, |
f13d3f73 | 47 | }; |
2017263e | 48 | |
70d39fe4 CW |
49 | static const char *yesno(int v) |
50 | { | |
51 | return v ? "yes" : "no"; | |
52 | } | |
53 | ||
54 | static int i915_capabilities(struct seq_file *m, void *data) | |
55 | { | |
56 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
57 | struct drm_device *dev = node->minor->dev; | |
58 | const struct intel_device_info *info = INTEL_INFO(dev); | |
59 | ||
60 | seq_printf(m, "gen: %d\n", info->gen); | |
03d00ac5 | 61 | seq_printf(m, "pch: %d\n", INTEL_PCH_TYPE(dev)); |
79fc46df DL |
62 | #define PRINT_FLAG(x) seq_printf(m, #x ": %s\n", yesno(info->x)) |
63 | #define SEP_SEMICOLON ; | |
64 | DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG, SEP_SEMICOLON); | |
65 | #undef PRINT_FLAG | |
66 | #undef SEP_SEMICOLON | |
70d39fe4 CW |
67 | |
68 | return 0; | |
69 | } | |
2017263e | 70 | |
05394f39 | 71 | static const char *get_pin_flag(struct drm_i915_gem_object *obj) |
a6172a80 | 72 | { |
05394f39 | 73 | if (obj->user_pin_count > 0) |
a6172a80 | 74 | return "P"; |
05394f39 | 75 | else if (obj->pin_count > 0) |
a6172a80 CW |
76 | return "p"; |
77 | else | |
78 | return " "; | |
79 | } | |
80 | ||
05394f39 | 81 | static const char *get_tiling_flag(struct drm_i915_gem_object *obj) |
a6172a80 | 82 | { |
0206e353 AJ |
83 | switch (obj->tiling_mode) { |
84 | default: | |
85 | case I915_TILING_NONE: return " "; | |
86 | case I915_TILING_X: return "X"; | |
87 | case I915_TILING_Y: return "Y"; | |
88 | } | |
a6172a80 CW |
89 | } |
90 | ||
1d693bcc BW |
91 | static inline const char *get_global_flag(struct drm_i915_gem_object *obj) |
92 | { | |
93 | return obj->has_global_gtt_mapping ? "g" : " "; | |
94 | } | |
95 | ||
37811fcc CW |
96 | static void |
97 | describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj) | |
98 | { | |
1d693bcc | 99 | struct i915_vma *vma; |
fb1ae911 | 100 | seq_printf(m, "%pK: %s%s%s %8zdKiB %02x %02x %u %u %u%s%s%s", |
37811fcc CW |
101 | &obj->base, |
102 | get_pin_flag(obj), | |
103 | get_tiling_flag(obj), | |
1d693bcc | 104 | get_global_flag(obj), |
a05a5862 | 105 | obj->base.size / 1024, |
37811fcc CW |
106 | obj->base.read_domains, |
107 | obj->base.write_domain, | |
0201f1ec CW |
108 | obj->last_read_seqno, |
109 | obj->last_write_seqno, | |
caea7476 | 110 | obj->last_fenced_seqno, |
84734a04 | 111 | i915_cache_level_str(obj->cache_level), |
37811fcc CW |
112 | obj->dirty ? " dirty" : "", |
113 | obj->madv == I915_MADV_DONTNEED ? " purgeable" : ""); | |
114 | if (obj->base.name) | |
115 | seq_printf(m, " (name: %d)", obj->base.name); | |
c110a6d7 CW |
116 | if (obj->pin_count) |
117 | seq_printf(m, " (pinned x %d)", obj->pin_count); | |
cc98b413 CW |
118 | if (obj->pin_display) |
119 | seq_printf(m, " (display)"); | |
37811fcc CW |
120 | if (obj->fence_reg != I915_FENCE_REG_NONE) |
121 | seq_printf(m, " (fence: %d)", obj->fence_reg); | |
1d693bcc BW |
122 | list_for_each_entry(vma, &obj->vma_list, vma_link) { |
123 | if (!i915_is_ggtt(vma->vm)) | |
124 | seq_puts(m, " (pp"); | |
125 | else | |
126 | seq_puts(m, " (g"); | |
127 | seq_printf(m, "gtt offset: %08lx, size: %08lx)", | |
128 | vma->node.start, vma->node.size); | |
129 | } | |
c1ad11fc CW |
130 | if (obj->stolen) |
131 | seq_printf(m, " (stolen: %08lx)", obj->stolen->start); | |
6299f992 CW |
132 | if (obj->pin_mappable || obj->fault_mappable) { |
133 | char s[3], *t = s; | |
134 | if (obj->pin_mappable) | |
135 | *t++ = 'p'; | |
136 | if (obj->fault_mappable) | |
137 | *t++ = 'f'; | |
138 | *t = '\0'; | |
139 | seq_printf(m, " (%s mappable)", s); | |
140 | } | |
69dc4987 CW |
141 | if (obj->ring != NULL) |
142 | seq_printf(m, " (%s)", obj->ring->name); | |
37811fcc CW |
143 | } |
144 | ||
3ccfd19d BW |
145 | static void describe_ctx(struct seq_file *m, struct i915_hw_context *ctx) |
146 | { | |
147 | seq_putc(m, ctx->is_initialized ? 'I' : 'i'); | |
148 | seq_putc(m, ctx->remap_slice ? 'R' : 'r'); | |
149 | seq_putc(m, ' '); | |
150 | } | |
151 | ||
433e12f7 | 152 | static int i915_gem_object_list_info(struct seq_file *m, void *data) |
2017263e BG |
153 | { |
154 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
433e12f7 BG |
155 | uintptr_t list = (uintptr_t) node->info_ent->data; |
156 | struct list_head *head; | |
2017263e | 157 | struct drm_device *dev = node->minor->dev; |
5cef07e1 BW |
158 | struct drm_i915_private *dev_priv = dev->dev_private; |
159 | struct i915_address_space *vm = &dev_priv->gtt.base; | |
ca191b13 | 160 | struct i915_vma *vma; |
8f2480fb CW |
161 | size_t total_obj_size, total_gtt_size; |
162 | int count, ret; | |
de227ef0 CW |
163 | |
164 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
165 | if (ret) | |
166 | return ret; | |
2017263e | 167 | |
ca191b13 | 168 | /* FIXME: the user of this interface might want more than just GGTT */ |
433e12f7 BG |
169 | switch (list) { |
170 | case ACTIVE_LIST: | |
267f0c90 | 171 | seq_puts(m, "Active:\n"); |
5cef07e1 | 172 | head = &vm->active_list; |
433e12f7 BG |
173 | break; |
174 | case INACTIVE_LIST: | |
267f0c90 | 175 | seq_puts(m, "Inactive:\n"); |
5cef07e1 | 176 | head = &vm->inactive_list; |
433e12f7 | 177 | break; |
433e12f7 | 178 | default: |
de227ef0 CW |
179 | mutex_unlock(&dev->struct_mutex); |
180 | return -EINVAL; | |
2017263e | 181 | } |
2017263e | 182 | |
8f2480fb | 183 | total_obj_size = total_gtt_size = count = 0; |
ca191b13 BW |
184 | list_for_each_entry(vma, head, mm_list) { |
185 | seq_printf(m, " "); | |
186 | describe_obj(m, vma->obj); | |
187 | seq_printf(m, "\n"); | |
188 | total_obj_size += vma->obj->base.size; | |
189 | total_gtt_size += vma->node.size; | |
8f2480fb | 190 | count++; |
2017263e | 191 | } |
de227ef0 | 192 | mutex_unlock(&dev->struct_mutex); |
5e118f41 | 193 | |
8f2480fb CW |
194 | seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n", |
195 | count, total_obj_size, total_gtt_size); | |
2017263e BG |
196 | return 0; |
197 | } | |
198 | ||
6d2b8885 CW |
199 | static int obj_rank_by_stolen(void *priv, |
200 | struct list_head *A, struct list_head *B) | |
201 | { | |
202 | struct drm_i915_gem_object *a = | |
b25cb2f8 | 203 | container_of(A, struct drm_i915_gem_object, obj_exec_link); |
6d2b8885 | 204 | struct drm_i915_gem_object *b = |
b25cb2f8 | 205 | container_of(B, struct drm_i915_gem_object, obj_exec_link); |
6d2b8885 CW |
206 | |
207 | return a->stolen->start - b->stolen->start; | |
208 | } | |
209 | ||
210 | static int i915_gem_stolen_list_info(struct seq_file *m, void *data) | |
211 | { | |
212 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
213 | struct drm_device *dev = node->minor->dev; | |
214 | struct drm_i915_private *dev_priv = dev->dev_private; | |
215 | struct drm_i915_gem_object *obj; | |
216 | size_t total_obj_size, total_gtt_size; | |
217 | LIST_HEAD(stolen); | |
218 | int count, ret; | |
219 | ||
220 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
221 | if (ret) | |
222 | return ret; | |
223 | ||
224 | total_obj_size = total_gtt_size = count = 0; | |
225 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) { | |
226 | if (obj->stolen == NULL) | |
227 | continue; | |
228 | ||
b25cb2f8 | 229 | list_add(&obj->obj_exec_link, &stolen); |
6d2b8885 CW |
230 | |
231 | total_obj_size += obj->base.size; | |
232 | total_gtt_size += i915_gem_obj_ggtt_size(obj); | |
233 | count++; | |
234 | } | |
235 | list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) { | |
236 | if (obj->stolen == NULL) | |
237 | continue; | |
238 | ||
b25cb2f8 | 239 | list_add(&obj->obj_exec_link, &stolen); |
6d2b8885 CW |
240 | |
241 | total_obj_size += obj->base.size; | |
242 | count++; | |
243 | } | |
244 | list_sort(NULL, &stolen, obj_rank_by_stolen); | |
245 | seq_puts(m, "Stolen:\n"); | |
246 | while (!list_empty(&stolen)) { | |
b25cb2f8 | 247 | obj = list_first_entry(&stolen, typeof(*obj), obj_exec_link); |
6d2b8885 CW |
248 | seq_puts(m, " "); |
249 | describe_obj(m, obj); | |
250 | seq_putc(m, '\n'); | |
b25cb2f8 | 251 | list_del_init(&obj->obj_exec_link); |
6d2b8885 CW |
252 | } |
253 | mutex_unlock(&dev->struct_mutex); | |
254 | ||
255 | seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n", | |
256 | count, total_obj_size, total_gtt_size); | |
257 | return 0; | |
258 | } | |
259 | ||
6299f992 CW |
260 | #define count_objects(list, member) do { \ |
261 | list_for_each_entry(obj, list, member) { \ | |
f343c5f6 | 262 | size += i915_gem_obj_ggtt_size(obj); \ |
6299f992 CW |
263 | ++count; \ |
264 | if (obj->map_and_fenceable) { \ | |
f343c5f6 | 265 | mappable_size += i915_gem_obj_ggtt_size(obj); \ |
6299f992 CW |
266 | ++mappable_count; \ |
267 | } \ | |
268 | } \ | |
0206e353 | 269 | } while (0) |
6299f992 | 270 | |
2db8e9d6 CW |
271 | struct file_stats { |
272 | int count; | |
273 | size_t total, active, inactive, unbound; | |
274 | }; | |
275 | ||
276 | static int per_file_stats(int id, void *ptr, void *data) | |
277 | { | |
278 | struct drm_i915_gem_object *obj = ptr; | |
279 | struct file_stats *stats = data; | |
280 | ||
281 | stats->count++; | |
282 | stats->total += obj->base.size; | |
283 | ||
f343c5f6 | 284 | if (i915_gem_obj_ggtt_bound(obj)) { |
2db8e9d6 CW |
285 | if (!list_empty(&obj->ring_list)) |
286 | stats->active += obj->base.size; | |
287 | else | |
288 | stats->inactive += obj->base.size; | |
289 | } else { | |
290 | if (!list_empty(&obj->global_list)) | |
291 | stats->unbound += obj->base.size; | |
292 | } | |
293 | ||
294 | return 0; | |
295 | } | |
296 | ||
ca191b13 BW |
297 | #define count_vmas(list, member) do { \ |
298 | list_for_each_entry(vma, list, member) { \ | |
299 | size += i915_gem_obj_ggtt_size(vma->obj); \ | |
300 | ++count; \ | |
301 | if (vma->obj->map_and_fenceable) { \ | |
302 | mappable_size += i915_gem_obj_ggtt_size(vma->obj); \ | |
303 | ++mappable_count; \ | |
304 | } \ | |
305 | } \ | |
306 | } while (0) | |
307 | ||
308 | static int i915_gem_object_info(struct seq_file *m, void* data) | |
73aa808f CW |
309 | { |
310 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
311 | struct drm_device *dev = node->minor->dev; | |
312 | struct drm_i915_private *dev_priv = dev->dev_private; | |
b7abb714 CW |
313 | u32 count, mappable_count, purgeable_count; |
314 | size_t size, mappable_size, purgeable_size; | |
6299f992 | 315 | struct drm_i915_gem_object *obj; |
5cef07e1 | 316 | struct i915_address_space *vm = &dev_priv->gtt.base; |
2db8e9d6 | 317 | struct drm_file *file; |
ca191b13 | 318 | struct i915_vma *vma; |
73aa808f CW |
319 | int ret; |
320 | ||
321 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
322 | if (ret) | |
323 | return ret; | |
324 | ||
6299f992 CW |
325 | seq_printf(m, "%u objects, %zu bytes\n", |
326 | dev_priv->mm.object_count, | |
327 | dev_priv->mm.object_memory); | |
328 | ||
329 | size = count = mappable_size = mappable_count = 0; | |
35c20a60 | 330 | count_objects(&dev_priv->mm.bound_list, global_list); |
6299f992 CW |
331 | seq_printf(m, "%u [%u] objects, %zu [%zu] bytes in gtt\n", |
332 | count, mappable_count, size, mappable_size); | |
333 | ||
334 | size = count = mappable_size = mappable_count = 0; | |
ca191b13 | 335 | count_vmas(&vm->active_list, mm_list); |
6299f992 CW |
336 | seq_printf(m, " %u [%u] active objects, %zu [%zu] bytes\n", |
337 | count, mappable_count, size, mappable_size); | |
338 | ||
6299f992 | 339 | size = count = mappable_size = mappable_count = 0; |
ca191b13 | 340 | count_vmas(&vm->inactive_list, mm_list); |
6299f992 CW |
341 | seq_printf(m, " %u [%u] inactive objects, %zu [%zu] bytes\n", |
342 | count, mappable_count, size, mappable_size); | |
343 | ||
b7abb714 | 344 | size = count = purgeable_size = purgeable_count = 0; |
35c20a60 | 345 | list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) { |
6c085a72 | 346 | size += obj->base.size, ++count; |
b7abb714 CW |
347 | if (obj->madv == I915_MADV_DONTNEED) |
348 | purgeable_size += obj->base.size, ++purgeable_count; | |
349 | } | |
6c085a72 CW |
350 | seq_printf(m, "%u unbound objects, %zu bytes\n", count, size); |
351 | ||
6299f992 | 352 | size = count = mappable_size = mappable_count = 0; |
35c20a60 | 353 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) { |
6299f992 | 354 | if (obj->fault_mappable) { |
f343c5f6 | 355 | size += i915_gem_obj_ggtt_size(obj); |
6299f992 CW |
356 | ++count; |
357 | } | |
358 | if (obj->pin_mappable) { | |
f343c5f6 | 359 | mappable_size += i915_gem_obj_ggtt_size(obj); |
6299f992 CW |
360 | ++mappable_count; |
361 | } | |
b7abb714 CW |
362 | if (obj->madv == I915_MADV_DONTNEED) { |
363 | purgeable_size += obj->base.size; | |
364 | ++purgeable_count; | |
365 | } | |
6299f992 | 366 | } |
b7abb714 CW |
367 | seq_printf(m, "%u purgeable objects, %zu bytes\n", |
368 | purgeable_count, purgeable_size); | |
6299f992 CW |
369 | seq_printf(m, "%u pinned mappable objects, %zu bytes\n", |
370 | mappable_count, mappable_size); | |
371 | seq_printf(m, "%u fault mappable objects, %zu bytes\n", | |
372 | count, size); | |
373 | ||
93d18799 | 374 | seq_printf(m, "%zu [%lu] gtt total\n", |
853ba5d2 BW |
375 | dev_priv->gtt.base.total, |
376 | dev_priv->gtt.mappable_end - dev_priv->gtt.base.start); | |
73aa808f | 377 | |
267f0c90 | 378 | seq_putc(m, '\n'); |
2db8e9d6 CW |
379 | list_for_each_entry_reverse(file, &dev->filelist, lhead) { |
380 | struct file_stats stats; | |
381 | ||
382 | memset(&stats, 0, sizeof(stats)); | |
383 | idr_for_each(&file->object_idr, per_file_stats, &stats); | |
384 | seq_printf(m, "%s: %u objects, %zu bytes (%zu active, %zu inactive, %zu unbound)\n", | |
385 | get_pid_task(file->pid, PIDTYPE_PID)->comm, | |
386 | stats.count, | |
387 | stats.total, | |
388 | stats.active, | |
389 | stats.inactive, | |
390 | stats.unbound); | |
391 | } | |
392 | ||
73aa808f CW |
393 | mutex_unlock(&dev->struct_mutex); |
394 | ||
395 | return 0; | |
396 | } | |
397 | ||
aee56cff | 398 | static int i915_gem_gtt_info(struct seq_file *m, void *data) |
08c18323 CW |
399 | { |
400 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
401 | struct drm_device *dev = node->minor->dev; | |
1b50247a | 402 | uintptr_t list = (uintptr_t) node->info_ent->data; |
08c18323 CW |
403 | struct drm_i915_private *dev_priv = dev->dev_private; |
404 | struct drm_i915_gem_object *obj; | |
405 | size_t total_obj_size, total_gtt_size; | |
406 | int count, ret; | |
407 | ||
408 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
409 | if (ret) | |
410 | return ret; | |
411 | ||
412 | total_obj_size = total_gtt_size = count = 0; | |
35c20a60 | 413 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) { |
1b50247a CW |
414 | if (list == PINNED_LIST && obj->pin_count == 0) |
415 | continue; | |
416 | ||
267f0c90 | 417 | seq_puts(m, " "); |
08c18323 | 418 | describe_obj(m, obj); |
267f0c90 | 419 | seq_putc(m, '\n'); |
08c18323 | 420 | total_obj_size += obj->base.size; |
f343c5f6 | 421 | total_gtt_size += i915_gem_obj_ggtt_size(obj); |
08c18323 CW |
422 | count++; |
423 | } | |
424 | ||
425 | mutex_unlock(&dev->struct_mutex); | |
426 | ||
427 | seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n", | |
428 | count, total_obj_size, total_gtt_size); | |
429 | ||
430 | return 0; | |
431 | } | |
432 | ||
4e5359cd SF |
433 | static int i915_gem_pageflip_info(struct seq_file *m, void *data) |
434 | { | |
435 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
436 | struct drm_device *dev = node->minor->dev; | |
437 | unsigned long flags; | |
438 | struct intel_crtc *crtc; | |
439 | ||
440 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) { | |
9db4a9c7 JB |
441 | const char pipe = pipe_name(crtc->pipe); |
442 | const char plane = plane_name(crtc->plane); | |
4e5359cd SF |
443 | struct intel_unpin_work *work; |
444 | ||
445 | spin_lock_irqsave(&dev->event_lock, flags); | |
446 | work = crtc->unpin_work; | |
447 | if (work == NULL) { | |
9db4a9c7 | 448 | seq_printf(m, "No flip due on pipe %c (plane %c)\n", |
4e5359cd SF |
449 | pipe, plane); |
450 | } else { | |
e7d841ca | 451 | if (atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) { |
9db4a9c7 | 452 | seq_printf(m, "Flip queued on pipe %c (plane %c)\n", |
4e5359cd SF |
453 | pipe, plane); |
454 | } else { | |
9db4a9c7 | 455 | seq_printf(m, "Flip pending (waiting for vsync) on pipe %c (plane %c)\n", |
4e5359cd SF |
456 | pipe, plane); |
457 | } | |
458 | if (work->enable_stall_check) | |
267f0c90 | 459 | seq_puts(m, "Stall check enabled, "); |
4e5359cd | 460 | else |
267f0c90 | 461 | seq_puts(m, "Stall check waiting for page flip ioctl, "); |
e7d841ca | 462 | seq_printf(m, "%d prepares\n", atomic_read(&work->pending)); |
4e5359cd SF |
463 | |
464 | if (work->old_fb_obj) { | |
05394f39 CW |
465 | struct drm_i915_gem_object *obj = work->old_fb_obj; |
466 | if (obj) | |
f343c5f6 BW |
467 | seq_printf(m, "Old framebuffer gtt_offset 0x%08lx\n", |
468 | i915_gem_obj_ggtt_offset(obj)); | |
4e5359cd SF |
469 | } |
470 | if (work->pending_flip_obj) { | |
05394f39 CW |
471 | struct drm_i915_gem_object *obj = work->pending_flip_obj; |
472 | if (obj) | |
f343c5f6 BW |
473 | seq_printf(m, "New framebuffer gtt_offset 0x%08lx\n", |
474 | i915_gem_obj_ggtt_offset(obj)); | |
4e5359cd SF |
475 | } |
476 | } | |
477 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
478 | } | |
479 | ||
480 | return 0; | |
481 | } | |
482 | ||
2017263e BG |
483 | static int i915_gem_request_info(struct seq_file *m, void *data) |
484 | { | |
485 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
486 | struct drm_device *dev = node->minor->dev; | |
487 | drm_i915_private_t *dev_priv = dev->dev_private; | |
a2c7f6fd | 488 | struct intel_ring_buffer *ring; |
2017263e | 489 | struct drm_i915_gem_request *gem_request; |
a2c7f6fd | 490 | int ret, count, i; |
de227ef0 CW |
491 | |
492 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
493 | if (ret) | |
494 | return ret; | |
2017263e | 495 | |
c2c347a9 | 496 | count = 0; |
a2c7f6fd CW |
497 | for_each_ring(ring, dev_priv, i) { |
498 | if (list_empty(&ring->request_list)) | |
499 | continue; | |
500 | ||
501 | seq_printf(m, "%s requests:\n", ring->name); | |
c2c347a9 | 502 | list_for_each_entry(gem_request, |
a2c7f6fd | 503 | &ring->request_list, |
c2c347a9 CW |
504 | list) { |
505 | seq_printf(m, " %d @ %d\n", | |
506 | gem_request->seqno, | |
507 | (int) (jiffies - gem_request->emitted_jiffies)); | |
508 | } | |
509 | count++; | |
2017263e | 510 | } |
de227ef0 CW |
511 | mutex_unlock(&dev->struct_mutex); |
512 | ||
c2c347a9 | 513 | if (count == 0) |
267f0c90 | 514 | seq_puts(m, "No requests\n"); |
c2c347a9 | 515 | |
2017263e BG |
516 | return 0; |
517 | } | |
518 | ||
b2223497 CW |
519 | static void i915_ring_seqno_info(struct seq_file *m, |
520 | struct intel_ring_buffer *ring) | |
521 | { | |
522 | if (ring->get_seqno) { | |
43a7b924 | 523 | seq_printf(m, "Current sequence (%s): %u\n", |
b2eadbc8 | 524 | ring->name, ring->get_seqno(ring, false)); |
b2223497 CW |
525 | } |
526 | } | |
527 | ||
2017263e BG |
528 | static int i915_gem_seqno_info(struct seq_file *m, void *data) |
529 | { | |
530 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
531 | struct drm_device *dev = node->minor->dev; | |
532 | drm_i915_private_t *dev_priv = dev->dev_private; | |
a2c7f6fd | 533 | struct intel_ring_buffer *ring; |
1ec14ad3 | 534 | int ret, i; |
de227ef0 CW |
535 | |
536 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
537 | if (ret) | |
538 | return ret; | |
2017263e | 539 | |
a2c7f6fd CW |
540 | for_each_ring(ring, dev_priv, i) |
541 | i915_ring_seqno_info(m, ring); | |
de227ef0 CW |
542 | |
543 | mutex_unlock(&dev->struct_mutex); | |
544 | ||
2017263e BG |
545 | return 0; |
546 | } | |
547 | ||
548 | ||
549 | static int i915_interrupt_info(struct seq_file *m, void *data) | |
550 | { | |
551 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
552 | struct drm_device *dev = node->minor->dev; | |
553 | drm_i915_private_t *dev_priv = dev->dev_private; | |
a2c7f6fd | 554 | struct intel_ring_buffer *ring; |
9db4a9c7 | 555 | int ret, i, pipe; |
de227ef0 CW |
556 | |
557 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
558 | if (ret) | |
559 | return ret; | |
2017263e | 560 | |
7e231dbe JB |
561 | if (IS_VALLEYVIEW(dev)) { |
562 | seq_printf(m, "Display IER:\t%08x\n", | |
563 | I915_READ(VLV_IER)); | |
564 | seq_printf(m, "Display IIR:\t%08x\n", | |
565 | I915_READ(VLV_IIR)); | |
566 | seq_printf(m, "Display IIR_RW:\t%08x\n", | |
567 | I915_READ(VLV_IIR_RW)); | |
568 | seq_printf(m, "Display IMR:\t%08x\n", | |
569 | I915_READ(VLV_IMR)); | |
570 | for_each_pipe(pipe) | |
571 | seq_printf(m, "Pipe %c stat:\t%08x\n", | |
572 | pipe_name(pipe), | |
573 | I915_READ(PIPESTAT(pipe))); | |
574 | ||
575 | seq_printf(m, "Master IER:\t%08x\n", | |
576 | I915_READ(VLV_MASTER_IER)); | |
577 | ||
578 | seq_printf(m, "Render IER:\t%08x\n", | |
579 | I915_READ(GTIER)); | |
580 | seq_printf(m, "Render IIR:\t%08x\n", | |
581 | I915_READ(GTIIR)); | |
582 | seq_printf(m, "Render IMR:\t%08x\n", | |
583 | I915_READ(GTIMR)); | |
584 | ||
585 | seq_printf(m, "PM IER:\t\t%08x\n", | |
586 | I915_READ(GEN6_PMIER)); | |
587 | seq_printf(m, "PM IIR:\t\t%08x\n", | |
588 | I915_READ(GEN6_PMIIR)); | |
589 | seq_printf(m, "PM IMR:\t\t%08x\n", | |
590 | I915_READ(GEN6_PMIMR)); | |
591 | ||
592 | seq_printf(m, "Port hotplug:\t%08x\n", | |
593 | I915_READ(PORT_HOTPLUG_EN)); | |
594 | seq_printf(m, "DPFLIPSTAT:\t%08x\n", | |
595 | I915_READ(VLV_DPFLIPSTAT)); | |
596 | seq_printf(m, "DPINVGTT:\t%08x\n", | |
597 | I915_READ(DPINVGTT)); | |
598 | ||
599 | } else if (!HAS_PCH_SPLIT(dev)) { | |
5f6a1695 ZW |
600 | seq_printf(m, "Interrupt enable: %08x\n", |
601 | I915_READ(IER)); | |
602 | seq_printf(m, "Interrupt identity: %08x\n", | |
603 | I915_READ(IIR)); | |
604 | seq_printf(m, "Interrupt mask: %08x\n", | |
605 | I915_READ(IMR)); | |
9db4a9c7 JB |
606 | for_each_pipe(pipe) |
607 | seq_printf(m, "Pipe %c stat: %08x\n", | |
608 | pipe_name(pipe), | |
609 | I915_READ(PIPESTAT(pipe))); | |
5f6a1695 ZW |
610 | } else { |
611 | seq_printf(m, "North Display Interrupt enable: %08x\n", | |
612 | I915_READ(DEIER)); | |
613 | seq_printf(m, "North Display Interrupt identity: %08x\n", | |
614 | I915_READ(DEIIR)); | |
615 | seq_printf(m, "North Display Interrupt mask: %08x\n", | |
616 | I915_READ(DEIMR)); | |
617 | seq_printf(m, "South Display Interrupt enable: %08x\n", | |
618 | I915_READ(SDEIER)); | |
619 | seq_printf(m, "South Display Interrupt identity: %08x\n", | |
620 | I915_READ(SDEIIR)); | |
621 | seq_printf(m, "South Display Interrupt mask: %08x\n", | |
622 | I915_READ(SDEIMR)); | |
623 | seq_printf(m, "Graphics Interrupt enable: %08x\n", | |
624 | I915_READ(GTIER)); | |
625 | seq_printf(m, "Graphics Interrupt identity: %08x\n", | |
626 | I915_READ(GTIIR)); | |
627 | seq_printf(m, "Graphics Interrupt mask: %08x\n", | |
628 | I915_READ(GTIMR)); | |
629 | } | |
2017263e BG |
630 | seq_printf(m, "Interrupts received: %d\n", |
631 | atomic_read(&dev_priv->irq_received)); | |
a2c7f6fd | 632 | for_each_ring(ring, dev_priv, i) { |
da64c6fc | 633 | if (IS_GEN6(dev) || IS_GEN7(dev)) { |
a2c7f6fd CW |
634 | seq_printf(m, |
635 | "Graphics Interrupt mask (%s): %08x\n", | |
636 | ring->name, I915_READ_IMR(ring)); | |
9862e600 | 637 | } |
a2c7f6fd | 638 | i915_ring_seqno_info(m, ring); |
9862e600 | 639 | } |
de227ef0 CW |
640 | mutex_unlock(&dev->struct_mutex); |
641 | ||
2017263e BG |
642 | return 0; |
643 | } | |
644 | ||
a6172a80 CW |
645 | static int i915_gem_fence_regs_info(struct seq_file *m, void *data) |
646 | { | |
647 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
648 | struct drm_device *dev = node->minor->dev; | |
649 | drm_i915_private_t *dev_priv = dev->dev_private; | |
de227ef0 CW |
650 | int i, ret; |
651 | ||
652 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
653 | if (ret) | |
654 | return ret; | |
a6172a80 CW |
655 | |
656 | seq_printf(m, "Reserved fences = %d\n", dev_priv->fence_reg_start); | |
657 | seq_printf(m, "Total fences = %d\n", dev_priv->num_fence_regs); | |
658 | for (i = 0; i < dev_priv->num_fence_regs; i++) { | |
05394f39 | 659 | struct drm_i915_gem_object *obj = dev_priv->fence_regs[i].obj; |
a6172a80 | 660 | |
6c085a72 CW |
661 | seq_printf(m, "Fence %d, pin count = %d, object = ", |
662 | i, dev_priv->fence_regs[i].pin_count); | |
c2c347a9 | 663 | if (obj == NULL) |
267f0c90 | 664 | seq_puts(m, "unused"); |
c2c347a9 | 665 | else |
05394f39 | 666 | describe_obj(m, obj); |
267f0c90 | 667 | seq_putc(m, '\n'); |
a6172a80 CW |
668 | } |
669 | ||
05394f39 | 670 | mutex_unlock(&dev->struct_mutex); |
a6172a80 CW |
671 | return 0; |
672 | } | |
673 | ||
2017263e BG |
674 | static int i915_hws_info(struct seq_file *m, void *data) |
675 | { | |
676 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
677 | struct drm_device *dev = node->minor->dev; | |
678 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4066c0ae | 679 | struct intel_ring_buffer *ring; |
1a240d4d | 680 | const u32 *hws; |
4066c0ae CW |
681 | int i; |
682 | ||
1ec14ad3 | 683 | ring = &dev_priv->ring[(uintptr_t)node->info_ent->data]; |
1a240d4d | 684 | hws = ring->status_page.page_addr; |
2017263e BG |
685 | if (hws == NULL) |
686 | return 0; | |
687 | ||
688 | for (i = 0; i < 4096 / sizeof(u32) / 4; i += 4) { | |
689 | seq_printf(m, "0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x\n", | |
690 | i * 4, | |
691 | hws[i], hws[i + 1], hws[i + 2], hws[i + 3]); | |
692 | } | |
693 | return 0; | |
694 | } | |
695 | ||
d5442303 DV |
696 | static ssize_t |
697 | i915_error_state_write(struct file *filp, | |
698 | const char __user *ubuf, | |
699 | size_t cnt, | |
700 | loff_t *ppos) | |
701 | { | |
edc3d884 | 702 | struct i915_error_state_file_priv *error_priv = filp->private_data; |
d5442303 | 703 | struct drm_device *dev = error_priv->dev; |
22bcfc6a | 704 | int ret; |
d5442303 DV |
705 | |
706 | DRM_DEBUG_DRIVER("Resetting error state\n"); | |
707 | ||
22bcfc6a DV |
708 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
709 | if (ret) | |
710 | return ret; | |
711 | ||
d5442303 DV |
712 | i915_destroy_error_state(dev); |
713 | mutex_unlock(&dev->struct_mutex); | |
714 | ||
715 | return cnt; | |
716 | } | |
717 | ||
718 | static int i915_error_state_open(struct inode *inode, struct file *file) | |
719 | { | |
720 | struct drm_device *dev = inode->i_private; | |
d5442303 | 721 | struct i915_error_state_file_priv *error_priv; |
d5442303 DV |
722 | |
723 | error_priv = kzalloc(sizeof(*error_priv), GFP_KERNEL); | |
724 | if (!error_priv) | |
725 | return -ENOMEM; | |
726 | ||
727 | error_priv->dev = dev; | |
728 | ||
95d5bfb3 | 729 | i915_error_state_get(dev, error_priv); |
d5442303 | 730 | |
edc3d884 MK |
731 | file->private_data = error_priv; |
732 | ||
733 | return 0; | |
d5442303 DV |
734 | } |
735 | ||
736 | static int i915_error_state_release(struct inode *inode, struct file *file) | |
737 | { | |
edc3d884 | 738 | struct i915_error_state_file_priv *error_priv = file->private_data; |
d5442303 | 739 | |
95d5bfb3 | 740 | i915_error_state_put(error_priv); |
d5442303 DV |
741 | kfree(error_priv); |
742 | ||
edc3d884 MK |
743 | return 0; |
744 | } | |
745 | ||
4dc955f7 MK |
746 | static ssize_t i915_error_state_read(struct file *file, char __user *userbuf, |
747 | size_t count, loff_t *pos) | |
748 | { | |
749 | struct i915_error_state_file_priv *error_priv = file->private_data; | |
750 | struct drm_i915_error_state_buf error_str; | |
751 | loff_t tmp_pos = 0; | |
752 | ssize_t ret_count = 0; | |
753 | int ret; | |
754 | ||
755 | ret = i915_error_state_buf_init(&error_str, count, *pos); | |
756 | if (ret) | |
757 | return ret; | |
edc3d884 | 758 | |
fc16b48b | 759 | ret = i915_error_state_to_str(&error_str, error_priv); |
edc3d884 MK |
760 | if (ret) |
761 | goto out; | |
762 | ||
edc3d884 MK |
763 | ret_count = simple_read_from_buffer(userbuf, count, &tmp_pos, |
764 | error_str.buf, | |
765 | error_str.bytes); | |
766 | ||
767 | if (ret_count < 0) | |
768 | ret = ret_count; | |
769 | else | |
770 | *pos = error_str.start + ret_count; | |
771 | out: | |
4dc955f7 | 772 | i915_error_state_buf_release(&error_str); |
edc3d884 | 773 | return ret ?: ret_count; |
d5442303 DV |
774 | } |
775 | ||
776 | static const struct file_operations i915_error_state_fops = { | |
777 | .owner = THIS_MODULE, | |
778 | .open = i915_error_state_open, | |
edc3d884 | 779 | .read = i915_error_state_read, |
d5442303 DV |
780 | .write = i915_error_state_write, |
781 | .llseek = default_llseek, | |
782 | .release = i915_error_state_release, | |
783 | }; | |
784 | ||
647416f9 KC |
785 | static int |
786 | i915_next_seqno_get(void *data, u64 *val) | |
40633219 | 787 | { |
647416f9 | 788 | struct drm_device *dev = data; |
40633219 | 789 | drm_i915_private_t *dev_priv = dev->dev_private; |
40633219 MK |
790 | int ret; |
791 | ||
792 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
793 | if (ret) | |
794 | return ret; | |
795 | ||
647416f9 | 796 | *val = dev_priv->next_seqno; |
40633219 MK |
797 | mutex_unlock(&dev->struct_mutex); |
798 | ||
647416f9 | 799 | return 0; |
40633219 MK |
800 | } |
801 | ||
647416f9 KC |
802 | static int |
803 | i915_next_seqno_set(void *data, u64 val) | |
804 | { | |
805 | struct drm_device *dev = data; | |
40633219 MK |
806 | int ret; |
807 | ||
40633219 MK |
808 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
809 | if (ret) | |
810 | return ret; | |
811 | ||
e94fbaa8 | 812 | ret = i915_gem_set_seqno(dev, val); |
40633219 MK |
813 | mutex_unlock(&dev->struct_mutex); |
814 | ||
647416f9 | 815 | return ret; |
40633219 MK |
816 | } |
817 | ||
647416f9 KC |
818 | DEFINE_SIMPLE_ATTRIBUTE(i915_next_seqno_fops, |
819 | i915_next_seqno_get, i915_next_seqno_set, | |
3a3b4f98 | 820 | "0x%llx\n"); |
40633219 | 821 | |
f97108d1 JB |
822 | static int i915_rstdby_delays(struct seq_file *m, void *unused) |
823 | { | |
824 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
825 | struct drm_device *dev = node->minor->dev; | |
826 | drm_i915_private_t *dev_priv = dev->dev_private; | |
616fdb5a BW |
827 | u16 crstanddelay; |
828 | int ret; | |
829 | ||
830 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
831 | if (ret) | |
832 | return ret; | |
833 | ||
834 | crstanddelay = I915_READ16(CRSTANDVID); | |
835 | ||
836 | mutex_unlock(&dev->struct_mutex); | |
f97108d1 JB |
837 | |
838 | seq_printf(m, "w/ctx: %d, w/o ctx: %d\n", (crstanddelay >> 8) & 0x3f, (crstanddelay & 0x3f)); | |
839 | ||
840 | return 0; | |
841 | } | |
842 | ||
843 | static int i915_cur_delayinfo(struct seq_file *m, void *unused) | |
844 | { | |
845 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
846 | struct drm_device *dev = node->minor->dev; | |
847 | drm_i915_private_t *dev_priv = dev->dev_private; | |
d1ebd816 | 848 | int ret; |
3b8d8d91 JB |
849 | |
850 | if (IS_GEN5(dev)) { | |
851 | u16 rgvswctl = I915_READ16(MEMSWCTL); | |
852 | u16 rgvstat = I915_READ16(MEMSTAT_ILK); | |
853 | ||
854 | seq_printf(m, "Requested P-state: %d\n", (rgvswctl >> 8) & 0xf); | |
855 | seq_printf(m, "Requested VID: %d\n", rgvswctl & 0x3f); | |
856 | seq_printf(m, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK) >> | |
857 | MEMSTAT_VID_SHIFT); | |
858 | seq_printf(m, "Current P-state: %d\n", | |
859 | (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT); | |
0a073b84 | 860 | } else if ((IS_GEN6(dev) || IS_GEN7(dev)) && !IS_VALLEYVIEW(dev)) { |
3b8d8d91 JB |
861 | u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS); |
862 | u32 rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS); | |
863 | u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP); | |
8e8c06cd | 864 | u32 rpstat, cagf, reqf; |
ccab5c82 JB |
865 | u32 rpupei, rpcurup, rpprevup; |
866 | u32 rpdownei, rpcurdown, rpprevdown; | |
3b8d8d91 JB |
867 | int max_freq; |
868 | ||
869 | /* RPSTAT1 is in the GT power well */ | |
d1ebd816 BW |
870 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
871 | if (ret) | |
872 | return ret; | |
873 | ||
fcca7926 | 874 | gen6_gt_force_wake_get(dev_priv); |
3b8d8d91 | 875 | |
8e8c06cd CW |
876 | reqf = I915_READ(GEN6_RPNSWREQ); |
877 | reqf &= ~GEN6_TURBO_DISABLE; | |
878 | if (IS_HASWELL(dev)) | |
879 | reqf >>= 24; | |
880 | else | |
881 | reqf >>= 25; | |
882 | reqf *= GT_FREQUENCY_MULTIPLIER; | |
883 | ||
ccab5c82 JB |
884 | rpstat = I915_READ(GEN6_RPSTAT1); |
885 | rpupei = I915_READ(GEN6_RP_CUR_UP_EI); | |
886 | rpcurup = I915_READ(GEN6_RP_CUR_UP); | |
887 | rpprevup = I915_READ(GEN6_RP_PREV_UP); | |
888 | rpdownei = I915_READ(GEN6_RP_CUR_DOWN_EI); | |
889 | rpcurdown = I915_READ(GEN6_RP_CUR_DOWN); | |
890 | rpprevdown = I915_READ(GEN6_RP_PREV_DOWN); | |
f82855d3 BW |
891 | if (IS_HASWELL(dev)) |
892 | cagf = (rpstat & HSW_CAGF_MASK) >> HSW_CAGF_SHIFT; | |
893 | else | |
894 | cagf = (rpstat & GEN6_CAGF_MASK) >> GEN6_CAGF_SHIFT; | |
895 | cagf *= GT_FREQUENCY_MULTIPLIER; | |
ccab5c82 | 896 | |
d1ebd816 BW |
897 | gen6_gt_force_wake_put(dev_priv); |
898 | mutex_unlock(&dev->struct_mutex); | |
899 | ||
3b8d8d91 | 900 | seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status); |
ccab5c82 | 901 | seq_printf(m, "RPSTAT1: 0x%08x\n", rpstat); |
3b8d8d91 JB |
902 | seq_printf(m, "Render p-state ratio: %d\n", |
903 | (gt_perf_status & 0xff00) >> 8); | |
904 | seq_printf(m, "Render p-state VID: %d\n", | |
905 | gt_perf_status & 0xff); | |
906 | seq_printf(m, "Render p-state limit: %d\n", | |
907 | rp_state_limits & 0xff); | |
8e8c06cd | 908 | seq_printf(m, "RPNSWREQ: %dMHz\n", reqf); |
f82855d3 | 909 | seq_printf(m, "CAGF: %dMHz\n", cagf); |
ccab5c82 JB |
910 | seq_printf(m, "RP CUR UP EI: %dus\n", rpupei & |
911 | GEN6_CURICONT_MASK); | |
912 | seq_printf(m, "RP CUR UP: %dus\n", rpcurup & | |
913 | GEN6_CURBSYTAVG_MASK); | |
914 | seq_printf(m, "RP PREV UP: %dus\n", rpprevup & | |
915 | GEN6_CURBSYTAVG_MASK); | |
916 | seq_printf(m, "RP CUR DOWN EI: %dus\n", rpdownei & | |
917 | GEN6_CURIAVG_MASK); | |
918 | seq_printf(m, "RP CUR DOWN: %dus\n", rpcurdown & | |
919 | GEN6_CURBSYTAVG_MASK); | |
920 | seq_printf(m, "RP PREV DOWN: %dus\n", rpprevdown & | |
921 | GEN6_CURBSYTAVG_MASK); | |
3b8d8d91 JB |
922 | |
923 | max_freq = (rp_state_cap & 0xff0000) >> 16; | |
924 | seq_printf(m, "Lowest (RPN) frequency: %dMHz\n", | |
c8735b0c | 925 | max_freq * GT_FREQUENCY_MULTIPLIER); |
3b8d8d91 JB |
926 | |
927 | max_freq = (rp_state_cap & 0xff00) >> 8; | |
928 | seq_printf(m, "Nominal (RP1) frequency: %dMHz\n", | |
c8735b0c | 929 | max_freq * GT_FREQUENCY_MULTIPLIER); |
3b8d8d91 JB |
930 | |
931 | max_freq = rp_state_cap & 0xff; | |
932 | seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n", | |
c8735b0c | 933 | max_freq * GT_FREQUENCY_MULTIPLIER); |
31c77388 BW |
934 | |
935 | seq_printf(m, "Max overclocked frequency: %dMHz\n", | |
936 | dev_priv->rps.hw_max * GT_FREQUENCY_MULTIPLIER); | |
0a073b84 JB |
937 | } else if (IS_VALLEYVIEW(dev)) { |
938 | u32 freq_sts, val; | |
939 | ||
259bd5d4 | 940 | mutex_lock(&dev_priv->rps.hw_lock); |
64936258 | 941 | freq_sts = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS); |
0a073b84 JB |
942 | seq_printf(m, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts); |
943 | seq_printf(m, "DDR freq: %d MHz\n", dev_priv->mem_freq); | |
944 | ||
64936258 | 945 | val = vlv_punit_read(dev_priv, PUNIT_FUSE_BUS1); |
0a073b84 JB |
946 | seq_printf(m, "max GPU freq: %d MHz\n", |
947 | vlv_gpu_freq(dev_priv->mem_freq, val)); | |
948 | ||
64936258 | 949 | val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM); |
0a073b84 JB |
950 | seq_printf(m, "min GPU freq: %d MHz\n", |
951 | vlv_gpu_freq(dev_priv->mem_freq, val)); | |
952 | ||
953 | seq_printf(m, "current GPU freq: %d MHz\n", | |
954 | vlv_gpu_freq(dev_priv->mem_freq, | |
955 | (freq_sts >> 8) & 0xff)); | |
259bd5d4 | 956 | mutex_unlock(&dev_priv->rps.hw_lock); |
3b8d8d91 | 957 | } else { |
267f0c90 | 958 | seq_puts(m, "no P-state info available\n"); |
3b8d8d91 | 959 | } |
f97108d1 JB |
960 | |
961 | return 0; | |
962 | } | |
963 | ||
964 | static int i915_delayfreq_table(struct seq_file *m, void *unused) | |
965 | { | |
966 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
967 | struct drm_device *dev = node->minor->dev; | |
968 | drm_i915_private_t *dev_priv = dev->dev_private; | |
969 | u32 delayfreq; | |
616fdb5a BW |
970 | int ret, i; |
971 | ||
972 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
973 | if (ret) | |
974 | return ret; | |
f97108d1 JB |
975 | |
976 | for (i = 0; i < 16; i++) { | |
977 | delayfreq = I915_READ(PXVFREQ_BASE + i * 4); | |
7648fa99 JB |
978 | seq_printf(m, "P%02dVIDFREQ: 0x%08x (VID: %d)\n", i, delayfreq, |
979 | (delayfreq & PXVFREQ_PX_MASK) >> PXVFREQ_PX_SHIFT); | |
f97108d1 JB |
980 | } |
981 | ||
616fdb5a BW |
982 | mutex_unlock(&dev->struct_mutex); |
983 | ||
f97108d1 JB |
984 | return 0; |
985 | } | |
986 | ||
987 | static inline int MAP_TO_MV(int map) | |
988 | { | |
989 | return 1250 - (map * 25); | |
990 | } | |
991 | ||
992 | static int i915_inttoext_table(struct seq_file *m, void *unused) | |
993 | { | |
994 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
995 | struct drm_device *dev = node->minor->dev; | |
996 | drm_i915_private_t *dev_priv = dev->dev_private; | |
997 | u32 inttoext; | |
616fdb5a BW |
998 | int ret, i; |
999 | ||
1000 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
1001 | if (ret) | |
1002 | return ret; | |
f97108d1 JB |
1003 | |
1004 | for (i = 1; i <= 32; i++) { | |
1005 | inttoext = I915_READ(INTTOEXT_BASE_ILK + i * 4); | |
1006 | seq_printf(m, "INTTOEXT%02d: 0x%08x\n", i, inttoext); | |
1007 | } | |
1008 | ||
616fdb5a BW |
1009 | mutex_unlock(&dev->struct_mutex); |
1010 | ||
f97108d1 JB |
1011 | return 0; |
1012 | } | |
1013 | ||
4d85529d | 1014 | static int ironlake_drpc_info(struct seq_file *m) |
f97108d1 JB |
1015 | { |
1016 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1017 | struct drm_device *dev = node->minor->dev; | |
1018 | drm_i915_private_t *dev_priv = dev->dev_private; | |
616fdb5a BW |
1019 | u32 rgvmodectl, rstdbyctl; |
1020 | u16 crstandvid; | |
1021 | int ret; | |
1022 | ||
1023 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
1024 | if (ret) | |
1025 | return ret; | |
1026 | ||
1027 | rgvmodectl = I915_READ(MEMMODECTL); | |
1028 | rstdbyctl = I915_READ(RSTDBYCTL); | |
1029 | crstandvid = I915_READ16(CRSTANDVID); | |
1030 | ||
1031 | mutex_unlock(&dev->struct_mutex); | |
f97108d1 JB |
1032 | |
1033 | seq_printf(m, "HD boost: %s\n", (rgvmodectl & MEMMODE_BOOST_EN) ? | |
1034 | "yes" : "no"); | |
1035 | seq_printf(m, "Boost freq: %d\n", | |
1036 | (rgvmodectl & MEMMODE_BOOST_FREQ_MASK) >> | |
1037 | MEMMODE_BOOST_FREQ_SHIFT); | |
1038 | seq_printf(m, "HW control enabled: %s\n", | |
1039 | rgvmodectl & MEMMODE_HWIDLE_EN ? "yes" : "no"); | |
1040 | seq_printf(m, "SW control enabled: %s\n", | |
1041 | rgvmodectl & MEMMODE_SWMODE_EN ? "yes" : "no"); | |
1042 | seq_printf(m, "Gated voltage change: %s\n", | |
1043 | rgvmodectl & MEMMODE_RCLK_GATE ? "yes" : "no"); | |
1044 | seq_printf(m, "Starting frequency: P%d\n", | |
1045 | (rgvmodectl & MEMMODE_FSTART_MASK) >> MEMMODE_FSTART_SHIFT); | |
7648fa99 | 1046 | seq_printf(m, "Max P-state: P%d\n", |
f97108d1 | 1047 | (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT); |
7648fa99 JB |
1048 | seq_printf(m, "Min P-state: P%d\n", (rgvmodectl & MEMMODE_FMIN_MASK)); |
1049 | seq_printf(m, "RS1 VID: %d\n", (crstandvid & 0x3f)); | |
1050 | seq_printf(m, "RS2 VID: %d\n", ((crstandvid >> 8) & 0x3f)); | |
1051 | seq_printf(m, "Render standby enabled: %s\n", | |
1052 | (rstdbyctl & RCX_SW_EXIT) ? "no" : "yes"); | |
267f0c90 | 1053 | seq_puts(m, "Current RS state: "); |
88271da3 JB |
1054 | switch (rstdbyctl & RSX_STATUS_MASK) { |
1055 | case RSX_STATUS_ON: | |
267f0c90 | 1056 | seq_puts(m, "on\n"); |
88271da3 JB |
1057 | break; |
1058 | case RSX_STATUS_RC1: | |
267f0c90 | 1059 | seq_puts(m, "RC1\n"); |
88271da3 JB |
1060 | break; |
1061 | case RSX_STATUS_RC1E: | |
267f0c90 | 1062 | seq_puts(m, "RC1E\n"); |
88271da3 JB |
1063 | break; |
1064 | case RSX_STATUS_RS1: | |
267f0c90 | 1065 | seq_puts(m, "RS1\n"); |
88271da3 JB |
1066 | break; |
1067 | case RSX_STATUS_RS2: | |
267f0c90 | 1068 | seq_puts(m, "RS2 (RC6)\n"); |
88271da3 JB |
1069 | break; |
1070 | case RSX_STATUS_RS3: | |
267f0c90 | 1071 | seq_puts(m, "RC3 (RC6+)\n"); |
88271da3 JB |
1072 | break; |
1073 | default: | |
267f0c90 | 1074 | seq_puts(m, "unknown\n"); |
88271da3 JB |
1075 | break; |
1076 | } | |
f97108d1 JB |
1077 | |
1078 | return 0; | |
1079 | } | |
1080 | ||
4d85529d BW |
1081 | static int gen6_drpc_info(struct seq_file *m) |
1082 | { | |
1083 | ||
1084 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1085 | struct drm_device *dev = node->minor->dev; | |
1086 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ecd8faea | 1087 | u32 rpmodectl1, gt_core_status, rcctl1, rc6vids = 0; |
93b525dc | 1088 | unsigned forcewake_count; |
aee56cff | 1089 | int count = 0, ret; |
4d85529d BW |
1090 | |
1091 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
1092 | if (ret) | |
1093 | return ret; | |
1094 | ||
907b28c5 CW |
1095 | spin_lock_irq(&dev_priv->uncore.lock); |
1096 | forcewake_count = dev_priv->uncore.forcewake_count; | |
1097 | spin_unlock_irq(&dev_priv->uncore.lock); | |
93b525dc DV |
1098 | |
1099 | if (forcewake_count) { | |
267f0c90 DL |
1100 | seq_puts(m, "RC information inaccurate because somebody " |
1101 | "holds a forcewake reference \n"); | |
4d85529d BW |
1102 | } else { |
1103 | /* NB: we cannot use forcewake, else we read the wrong values */ | |
1104 | while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1)) | |
1105 | udelay(10); | |
1106 | seq_printf(m, "RC information accurate: %s\n", yesno(count < 51)); | |
1107 | } | |
1108 | ||
1109 | gt_core_status = readl(dev_priv->regs + GEN6_GT_CORE_STATUS); | |
ed71f1b4 | 1110 | trace_i915_reg_rw(false, GEN6_GT_CORE_STATUS, gt_core_status, 4, true); |
4d85529d BW |
1111 | |
1112 | rpmodectl1 = I915_READ(GEN6_RP_CONTROL); | |
1113 | rcctl1 = I915_READ(GEN6_RC_CONTROL); | |
1114 | mutex_unlock(&dev->struct_mutex); | |
44cbd338 BW |
1115 | mutex_lock(&dev_priv->rps.hw_lock); |
1116 | sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids); | |
1117 | mutex_unlock(&dev_priv->rps.hw_lock); | |
4d85529d BW |
1118 | |
1119 | seq_printf(m, "Video Turbo Mode: %s\n", | |
1120 | yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO)); | |
1121 | seq_printf(m, "HW control enabled: %s\n", | |
1122 | yesno(rpmodectl1 & GEN6_RP_ENABLE)); | |
1123 | seq_printf(m, "SW control enabled: %s\n", | |
1124 | yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) == | |
1125 | GEN6_RP_MEDIA_SW_MODE)); | |
fff24e21 | 1126 | seq_printf(m, "RC1e Enabled: %s\n", |
4d85529d BW |
1127 | yesno(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE)); |
1128 | seq_printf(m, "RC6 Enabled: %s\n", | |
1129 | yesno(rcctl1 & GEN6_RC_CTL_RC6_ENABLE)); | |
1130 | seq_printf(m, "Deep RC6 Enabled: %s\n", | |
1131 | yesno(rcctl1 & GEN6_RC_CTL_RC6p_ENABLE)); | |
1132 | seq_printf(m, "Deepest RC6 Enabled: %s\n", | |
1133 | yesno(rcctl1 & GEN6_RC_CTL_RC6pp_ENABLE)); | |
267f0c90 | 1134 | seq_puts(m, "Current RC state: "); |
4d85529d BW |
1135 | switch (gt_core_status & GEN6_RCn_MASK) { |
1136 | case GEN6_RC0: | |
1137 | if (gt_core_status & GEN6_CORE_CPD_STATE_MASK) | |
267f0c90 | 1138 | seq_puts(m, "Core Power Down\n"); |
4d85529d | 1139 | else |
267f0c90 | 1140 | seq_puts(m, "on\n"); |
4d85529d BW |
1141 | break; |
1142 | case GEN6_RC3: | |
267f0c90 | 1143 | seq_puts(m, "RC3\n"); |
4d85529d BW |
1144 | break; |
1145 | case GEN6_RC6: | |
267f0c90 | 1146 | seq_puts(m, "RC6\n"); |
4d85529d BW |
1147 | break; |
1148 | case GEN6_RC7: | |
267f0c90 | 1149 | seq_puts(m, "RC7\n"); |
4d85529d BW |
1150 | break; |
1151 | default: | |
267f0c90 | 1152 | seq_puts(m, "Unknown\n"); |
4d85529d BW |
1153 | break; |
1154 | } | |
1155 | ||
1156 | seq_printf(m, "Core Power Down: %s\n", | |
1157 | yesno(gt_core_status & GEN6_CORE_CPD_STATE_MASK)); | |
cce66a28 BW |
1158 | |
1159 | /* Not exactly sure what this is */ | |
1160 | seq_printf(m, "RC6 \"Locked to RPn\" residency since boot: %u\n", | |
1161 | I915_READ(GEN6_GT_GFX_RC6_LOCKED)); | |
1162 | seq_printf(m, "RC6 residency since boot: %u\n", | |
1163 | I915_READ(GEN6_GT_GFX_RC6)); | |
1164 | seq_printf(m, "RC6+ residency since boot: %u\n", | |
1165 | I915_READ(GEN6_GT_GFX_RC6p)); | |
1166 | seq_printf(m, "RC6++ residency since boot: %u\n", | |
1167 | I915_READ(GEN6_GT_GFX_RC6pp)); | |
1168 | ||
ecd8faea BW |
1169 | seq_printf(m, "RC6 voltage: %dmV\n", |
1170 | GEN6_DECODE_RC6_VID(((rc6vids >> 0) & 0xff))); | |
1171 | seq_printf(m, "RC6+ voltage: %dmV\n", | |
1172 | GEN6_DECODE_RC6_VID(((rc6vids >> 8) & 0xff))); | |
1173 | seq_printf(m, "RC6++ voltage: %dmV\n", | |
1174 | GEN6_DECODE_RC6_VID(((rc6vids >> 16) & 0xff))); | |
4d85529d BW |
1175 | return 0; |
1176 | } | |
1177 | ||
1178 | static int i915_drpc_info(struct seq_file *m, void *unused) | |
1179 | { | |
1180 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1181 | struct drm_device *dev = node->minor->dev; | |
1182 | ||
1183 | if (IS_GEN6(dev) || IS_GEN7(dev)) | |
1184 | return gen6_drpc_info(m); | |
1185 | else | |
1186 | return ironlake_drpc_info(m); | |
1187 | } | |
1188 | ||
b5e50c3f JB |
1189 | static int i915_fbc_status(struct seq_file *m, void *unused) |
1190 | { | |
1191 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1192 | struct drm_device *dev = node->minor->dev; | |
b5e50c3f | 1193 | drm_i915_private_t *dev_priv = dev->dev_private; |
b5e50c3f | 1194 | |
ee5382ae | 1195 | if (!I915_HAS_FBC(dev)) { |
267f0c90 | 1196 | seq_puts(m, "FBC unsupported on this chipset\n"); |
b5e50c3f JB |
1197 | return 0; |
1198 | } | |
1199 | ||
ee5382ae | 1200 | if (intel_fbc_enabled(dev)) { |
267f0c90 | 1201 | seq_puts(m, "FBC enabled\n"); |
b5e50c3f | 1202 | } else { |
267f0c90 | 1203 | seq_puts(m, "FBC disabled: "); |
5c3fe8b0 | 1204 | switch (dev_priv->fbc.no_fbc_reason) { |
29ebf90f CW |
1205 | case FBC_OK: |
1206 | seq_puts(m, "FBC actived, but currently disabled in hardware"); | |
1207 | break; | |
1208 | case FBC_UNSUPPORTED: | |
1209 | seq_puts(m, "unsupported by this chipset"); | |
1210 | break; | |
bed4a673 | 1211 | case FBC_NO_OUTPUT: |
267f0c90 | 1212 | seq_puts(m, "no outputs"); |
bed4a673 | 1213 | break; |
b5e50c3f | 1214 | case FBC_STOLEN_TOO_SMALL: |
267f0c90 | 1215 | seq_puts(m, "not enough stolen memory"); |
b5e50c3f JB |
1216 | break; |
1217 | case FBC_UNSUPPORTED_MODE: | |
267f0c90 | 1218 | seq_puts(m, "mode not supported"); |
b5e50c3f JB |
1219 | break; |
1220 | case FBC_MODE_TOO_LARGE: | |
267f0c90 | 1221 | seq_puts(m, "mode too large"); |
b5e50c3f JB |
1222 | break; |
1223 | case FBC_BAD_PLANE: | |
267f0c90 | 1224 | seq_puts(m, "FBC unsupported on plane"); |
b5e50c3f JB |
1225 | break; |
1226 | case FBC_NOT_TILED: | |
267f0c90 | 1227 | seq_puts(m, "scanout buffer not tiled"); |
b5e50c3f | 1228 | break; |
9c928d16 | 1229 | case FBC_MULTIPLE_PIPES: |
267f0c90 | 1230 | seq_puts(m, "multiple pipes are enabled"); |
9c928d16 | 1231 | break; |
c1a9f047 | 1232 | case FBC_MODULE_PARAM: |
267f0c90 | 1233 | seq_puts(m, "disabled per module param (default off)"); |
c1a9f047 | 1234 | break; |
8a5729a3 | 1235 | case FBC_CHIP_DEFAULT: |
267f0c90 | 1236 | seq_puts(m, "disabled per chip default"); |
8a5729a3 | 1237 | break; |
b5e50c3f | 1238 | default: |
267f0c90 | 1239 | seq_puts(m, "unknown reason"); |
b5e50c3f | 1240 | } |
267f0c90 | 1241 | seq_putc(m, '\n'); |
b5e50c3f JB |
1242 | } |
1243 | return 0; | |
1244 | } | |
1245 | ||
92d44621 PZ |
1246 | static int i915_ips_status(struct seq_file *m, void *unused) |
1247 | { | |
1248 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1249 | struct drm_device *dev = node->minor->dev; | |
1250 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1251 | ||
f5adf94e | 1252 | if (!HAS_IPS(dev)) { |
92d44621 PZ |
1253 | seq_puts(m, "not supported\n"); |
1254 | return 0; | |
1255 | } | |
1256 | ||
1257 | if (I915_READ(IPS_CTL) & IPS_ENABLE) | |
1258 | seq_puts(m, "enabled\n"); | |
1259 | else | |
1260 | seq_puts(m, "disabled\n"); | |
1261 | ||
1262 | return 0; | |
1263 | } | |
1264 | ||
4a9bef37 JB |
1265 | static int i915_sr_status(struct seq_file *m, void *unused) |
1266 | { | |
1267 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1268 | struct drm_device *dev = node->minor->dev; | |
1269 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1270 | bool sr_enabled = false; | |
1271 | ||
1398261a | 1272 | if (HAS_PCH_SPLIT(dev)) |
5ba2aaaa | 1273 | sr_enabled = I915_READ(WM1_LP_ILK) & WM1_LP_SR_EN; |
a6c45cf0 | 1274 | else if (IS_CRESTLINE(dev) || IS_I945G(dev) || IS_I945GM(dev)) |
4a9bef37 JB |
1275 | sr_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN; |
1276 | else if (IS_I915GM(dev)) | |
1277 | sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN; | |
1278 | else if (IS_PINEVIEW(dev)) | |
1279 | sr_enabled = I915_READ(DSPFW3) & PINEVIEW_SELF_REFRESH_EN; | |
1280 | ||
5ba2aaaa CW |
1281 | seq_printf(m, "self-refresh: %s\n", |
1282 | sr_enabled ? "enabled" : "disabled"); | |
4a9bef37 JB |
1283 | |
1284 | return 0; | |
1285 | } | |
1286 | ||
7648fa99 JB |
1287 | static int i915_emon_status(struct seq_file *m, void *unused) |
1288 | { | |
1289 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1290 | struct drm_device *dev = node->minor->dev; | |
1291 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1292 | unsigned long temp, chipset, gfx; | |
de227ef0 CW |
1293 | int ret; |
1294 | ||
582be6b4 CW |
1295 | if (!IS_GEN5(dev)) |
1296 | return -ENODEV; | |
1297 | ||
de227ef0 CW |
1298 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
1299 | if (ret) | |
1300 | return ret; | |
7648fa99 JB |
1301 | |
1302 | temp = i915_mch_val(dev_priv); | |
1303 | chipset = i915_chipset_val(dev_priv); | |
1304 | gfx = i915_gfx_val(dev_priv); | |
de227ef0 | 1305 | mutex_unlock(&dev->struct_mutex); |
7648fa99 JB |
1306 | |
1307 | seq_printf(m, "GMCH temp: %ld\n", temp); | |
1308 | seq_printf(m, "Chipset power: %ld\n", chipset); | |
1309 | seq_printf(m, "GFX power: %ld\n", gfx); | |
1310 | seq_printf(m, "Total power: %ld\n", chipset + gfx); | |
1311 | ||
1312 | return 0; | |
1313 | } | |
1314 | ||
23b2f8bb JB |
1315 | static int i915_ring_freq_table(struct seq_file *m, void *unused) |
1316 | { | |
1317 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1318 | struct drm_device *dev = node->minor->dev; | |
1319 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1320 | int ret; | |
1321 | int gpu_freq, ia_freq; | |
1322 | ||
1c70c0ce | 1323 | if (!(IS_GEN6(dev) || IS_GEN7(dev))) { |
267f0c90 | 1324 | seq_puts(m, "unsupported on this chipset\n"); |
23b2f8bb JB |
1325 | return 0; |
1326 | } | |
1327 | ||
4fc688ce | 1328 | ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock); |
23b2f8bb JB |
1329 | if (ret) |
1330 | return ret; | |
1331 | ||
267f0c90 | 1332 | seq_puts(m, "GPU freq (MHz)\tEffective CPU freq (MHz)\tEffective Ring freq (MHz)\n"); |
23b2f8bb | 1333 | |
c6a828d3 DV |
1334 | for (gpu_freq = dev_priv->rps.min_delay; |
1335 | gpu_freq <= dev_priv->rps.max_delay; | |
23b2f8bb | 1336 | gpu_freq++) { |
42c0526c BW |
1337 | ia_freq = gpu_freq; |
1338 | sandybridge_pcode_read(dev_priv, | |
1339 | GEN6_PCODE_READ_MIN_FREQ_TABLE, | |
1340 | &ia_freq); | |
3ebecd07 CW |
1341 | seq_printf(m, "%d\t\t%d\t\t\t\t%d\n", |
1342 | gpu_freq * GT_FREQUENCY_MULTIPLIER, | |
1343 | ((ia_freq >> 0) & 0xff) * 100, | |
1344 | ((ia_freq >> 8) & 0xff) * 100); | |
23b2f8bb JB |
1345 | } |
1346 | ||
4fc688ce | 1347 | mutex_unlock(&dev_priv->rps.hw_lock); |
23b2f8bb JB |
1348 | |
1349 | return 0; | |
1350 | } | |
1351 | ||
7648fa99 JB |
1352 | static int i915_gfxec(struct seq_file *m, void *unused) |
1353 | { | |
1354 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1355 | struct drm_device *dev = node->minor->dev; | |
1356 | drm_i915_private_t *dev_priv = dev->dev_private; | |
616fdb5a BW |
1357 | int ret; |
1358 | ||
1359 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
1360 | if (ret) | |
1361 | return ret; | |
7648fa99 JB |
1362 | |
1363 | seq_printf(m, "GFXEC: %ld\n", (unsigned long)I915_READ(0x112f4)); | |
1364 | ||
616fdb5a BW |
1365 | mutex_unlock(&dev->struct_mutex); |
1366 | ||
7648fa99 JB |
1367 | return 0; |
1368 | } | |
1369 | ||
44834a67 CW |
1370 | static int i915_opregion(struct seq_file *m, void *unused) |
1371 | { | |
1372 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1373 | struct drm_device *dev = node->minor->dev; | |
1374 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1375 | struct intel_opregion *opregion = &dev_priv->opregion; | |
0d38f009 | 1376 | void *data = kmalloc(OPREGION_SIZE, GFP_KERNEL); |
44834a67 CW |
1377 | int ret; |
1378 | ||
0d38f009 DV |
1379 | if (data == NULL) |
1380 | return -ENOMEM; | |
1381 | ||
44834a67 CW |
1382 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
1383 | if (ret) | |
0d38f009 | 1384 | goto out; |
44834a67 | 1385 | |
0d38f009 DV |
1386 | if (opregion->header) { |
1387 | memcpy_fromio(data, opregion->header, OPREGION_SIZE); | |
1388 | seq_write(m, data, OPREGION_SIZE); | |
1389 | } | |
44834a67 CW |
1390 | |
1391 | mutex_unlock(&dev->struct_mutex); | |
1392 | ||
0d38f009 DV |
1393 | out: |
1394 | kfree(data); | |
44834a67 CW |
1395 | return 0; |
1396 | } | |
1397 | ||
37811fcc CW |
1398 | static int i915_gem_framebuffer_info(struct seq_file *m, void *data) |
1399 | { | |
1400 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1401 | struct drm_device *dev = node->minor->dev; | |
1402 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1403 | struct intel_fbdev *ifbdev; | |
1404 | struct intel_framebuffer *fb; | |
1405 | int ret; | |
1406 | ||
1407 | ret = mutex_lock_interruptible(&dev->mode_config.mutex); | |
1408 | if (ret) | |
1409 | return ret; | |
1410 | ||
1411 | ifbdev = dev_priv->fbdev; | |
1412 | fb = to_intel_framebuffer(ifbdev->helper.fb); | |
1413 | ||
623f9783 | 1414 | seq_printf(m, "fbcon size: %d x %d, depth %d, %d bpp, refcount %d, obj ", |
37811fcc CW |
1415 | fb->base.width, |
1416 | fb->base.height, | |
1417 | fb->base.depth, | |
623f9783 DV |
1418 | fb->base.bits_per_pixel, |
1419 | atomic_read(&fb->base.refcount.refcount)); | |
05394f39 | 1420 | describe_obj(m, fb->obj); |
267f0c90 | 1421 | seq_putc(m, '\n'); |
4b096ac1 | 1422 | mutex_unlock(&dev->mode_config.mutex); |
37811fcc | 1423 | |
4b096ac1 | 1424 | mutex_lock(&dev->mode_config.fb_lock); |
37811fcc CW |
1425 | list_for_each_entry(fb, &dev->mode_config.fb_list, base.head) { |
1426 | if (&fb->base == ifbdev->helper.fb) | |
1427 | continue; | |
1428 | ||
623f9783 | 1429 | seq_printf(m, "user size: %d x %d, depth %d, %d bpp, refcount %d, obj ", |
37811fcc CW |
1430 | fb->base.width, |
1431 | fb->base.height, | |
1432 | fb->base.depth, | |
623f9783 DV |
1433 | fb->base.bits_per_pixel, |
1434 | atomic_read(&fb->base.refcount.refcount)); | |
05394f39 | 1435 | describe_obj(m, fb->obj); |
267f0c90 | 1436 | seq_putc(m, '\n'); |
37811fcc | 1437 | } |
4b096ac1 | 1438 | mutex_unlock(&dev->mode_config.fb_lock); |
37811fcc CW |
1439 | |
1440 | return 0; | |
1441 | } | |
1442 | ||
e76d3630 BW |
1443 | static int i915_context_status(struct seq_file *m, void *unused) |
1444 | { | |
1445 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1446 | struct drm_device *dev = node->minor->dev; | |
1447 | drm_i915_private_t *dev_priv = dev->dev_private; | |
a168c293 | 1448 | struct intel_ring_buffer *ring; |
a33afea5 | 1449 | struct i915_hw_context *ctx; |
a168c293 | 1450 | int ret, i; |
e76d3630 BW |
1451 | |
1452 | ret = mutex_lock_interruptible(&dev->mode_config.mutex); | |
1453 | if (ret) | |
1454 | return ret; | |
1455 | ||
3e373948 | 1456 | if (dev_priv->ips.pwrctx) { |
267f0c90 | 1457 | seq_puts(m, "power context "); |
3e373948 | 1458 | describe_obj(m, dev_priv->ips.pwrctx); |
267f0c90 | 1459 | seq_putc(m, '\n'); |
dc501fbc | 1460 | } |
e76d3630 | 1461 | |
3e373948 | 1462 | if (dev_priv->ips.renderctx) { |
267f0c90 | 1463 | seq_puts(m, "render context "); |
3e373948 | 1464 | describe_obj(m, dev_priv->ips.renderctx); |
267f0c90 | 1465 | seq_putc(m, '\n'); |
dc501fbc | 1466 | } |
e76d3630 | 1467 | |
a33afea5 BW |
1468 | list_for_each_entry(ctx, &dev_priv->context_list, link) { |
1469 | seq_puts(m, "HW context "); | |
3ccfd19d | 1470 | describe_ctx(m, ctx); |
a33afea5 BW |
1471 | for_each_ring(ring, dev_priv, i) |
1472 | if (ring->default_context == ctx) | |
1473 | seq_printf(m, "(default context %s) ", ring->name); | |
1474 | ||
1475 | describe_obj(m, ctx->obj); | |
1476 | seq_putc(m, '\n'); | |
a168c293 BW |
1477 | } |
1478 | ||
e76d3630 BW |
1479 | mutex_unlock(&dev->mode_config.mutex); |
1480 | ||
1481 | return 0; | |
1482 | } | |
1483 | ||
6d794d42 BW |
1484 | static int i915_gen6_forcewake_count_info(struct seq_file *m, void *data) |
1485 | { | |
1486 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1487 | struct drm_device *dev = node->minor->dev; | |
1488 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9f1f46a4 | 1489 | unsigned forcewake_count; |
6d794d42 | 1490 | |
907b28c5 CW |
1491 | spin_lock_irq(&dev_priv->uncore.lock); |
1492 | forcewake_count = dev_priv->uncore.forcewake_count; | |
1493 | spin_unlock_irq(&dev_priv->uncore.lock); | |
6d794d42 | 1494 | |
9f1f46a4 | 1495 | seq_printf(m, "forcewake count = %u\n", forcewake_count); |
6d794d42 BW |
1496 | |
1497 | return 0; | |
1498 | } | |
1499 | ||
ea16a3cd DV |
1500 | static const char *swizzle_string(unsigned swizzle) |
1501 | { | |
aee56cff | 1502 | switch (swizzle) { |
ea16a3cd DV |
1503 | case I915_BIT_6_SWIZZLE_NONE: |
1504 | return "none"; | |
1505 | case I915_BIT_6_SWIZZLE_9: | |
1506 | return "bit9"; | |
1507 | case I915_BIT_6_SWIZZLE_9_10: | |
1508 | return "bit9/bit10"; | |
1509 | case I915_BIT_6_SWIZZLE_9_11: | |
1510 | return "bit9/bit11"; | |
1511 | case I915_BIT_6_SWIZZLE_9_10_11: | |
1512 | return "bit9/bit10/bit11"; | |
1513 | case I915_BIT_6_SWIZZLE_9_17: | |
1514 | return "bit9/bit17"; | |
1515 | case I915_BIT_6_SWIZZLE_9_10_17: | |
1516 | return "bit9/bit10/bit17"; | |
1517 | case I915_BIT_6_SWIZZLE_UNKNOWN: | |
8a168ca7 | 1518 | return "unknown"; |
ea16a3cd DV |
1519 | } |
1520 | ||
1521 | return "bug"; | |
1522 | } | |
1523 | ||
1524 | static int i915_swizzle_info(struct seq_file *m, void *data) | |
1525 | { | |
1526 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1527 | struct drm_device *dev = node->minor->dev; | |
1528 | struct drm_i915_private *dev_priv = dev->dev_private; | |
22bcfc6a DV |
1529 | int ret; |
1530 | ||
1531 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
1532 | if (ret) | |
1533 | return ret; | |
ea16a3cd | 1534 | |
ea16a3cd DV |
1535 | seq_printf(m, "bit6 swizzle for X-tiling = %s\n", |
1536 | swizzle_string(dev_priv->mm.bit_6_swizzle_x)); | |
1537 | seq_printf(m, "bit6 swizzle for Y-tiling = %s\n", | |
1538 | swizzle_string(dev_priv->mm.bit_6_swizzle_y)); | |
1539 | ||
1540 | if (IS_GEN3(dev) || IS_GEN4(dev)) { | |
1541 | seq_printf(m, "DDC = 0x%08x\n", | |
1542 | I915_READ(DCC)); | |
1543 | seq_printf(m, "C0DRB3 = 0x%04x\n", | |
1544 | I915_READ16(C0DRB3)); | |
1545 | seq_printf(m, "C1DRB3 = 0x%04x\n", | |
1546 | I915_READ16(C1DRB3)); | |
3fa7d235 DV |
1547 | } else if (IS_GEN6(dev) || IS_GEN7(dev)) { |
1548 | seq_printf(m, "MAD_DIMM_C0 = 0x%08x\n", | |
1549 | I915_READ(MAD_DIMM_C0)); | |
1550 | seq_printf(m, "MAD_DIMM_C1 = 0x%08x\n", | |
1551 | I915_READ(MAD_DIMM_C1)); | |
1552 | seq_printf(m, "MAD_DIMM_C2 = 0x%08x\n", | |
1553 | I915_READ(MAD_DIMM_C2)); | |
1554 | seq_printf(m, "TILECTL = 0x%08x\n", | |
1555 | I915_READ(TILECTL)); | |
1556 | seq_printf(m, "ARB_MODE = 0x%08x\n", | |
1557 | I915_READ(ARB_MODE)); | |
1558 | seq_printf(m, "DISP_ARB_CTL = 0x%08x\n", | |
1559 | I915_READ(DISP_ARB_CTL)); | |
ea16a3cd DV |
1560 | } |
1561 | mutex_unlock(&dev->struct_mutex); | |
1562 | ||
1563 | return 0; | |
1564 | } | |
1565 | ||
3cf17fc5 DV |
1566 | static int i915_ppgtt_info(struct seq_file *m, void *data) |
1567 | { | |
1568 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1569 | struct drm_device *dev = node->minor->dev; | |
1570 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1571 | struct intel_ring_buffer *ring; | |
1572 | int i, ret; | |
1573 | ||
1574 | ||
1575 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
1576 | if (ret) | |
1577 | return ret; | |
1578 | if (INTEL_INFO(dev)->gen == 6) | |
1579 | seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(GFX_MODE)); | |
1580 | ||
a2c7f6fd | 1581 | for_each_ring(ring, dev_priv, i) { |
3cf17fc5 DV |
1582 | seq_printf(m, "%s\n", ring->name); |
1583 | if (INTEL_INFO(dev)->gen == 7) | |
1584 | seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(RING_MODE_GEN7(ring))); | |
1585 | seq_printf(m, "PP_DIR_BASE: 0x%08x\n", I915_READ(RING_PP_DIR_BASE(ring))); | |
1586 | seq_printf(m, "PP_DIR_BASE_READ: 0x%08x\n", I915_READ(RING_PP_DIR_BASE_READ(ring))); | |
1587 | seq_printf(m, "PP_DIR_DCLV: 0x%08x\n", I915_READ(RING_PP_DIR_DCLV(ring))); | |
1588 | } | |
1589 | if (dev_priv->mm.aliasing_ppgtt) { | |
1590 | struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt; | |
1591 | ||
267f0c90 | 1592 | seq_puts(m, "aliasing PPGTT:\n"); |
3cf17fc5 DV |
1593 | seq_printf(m, "pd gtt offset: 0x%08x\n", ppgtt->pd_offset); |
1594 | } | |
1595 | seq_printf(m, "ECOCHK: 0x%08x\n", I915_READ(GAM_ECOCHK)); | |
1596 | mutex_unlock(&dev->struct_mutex); | |
1597 | ||
1598 | return 0; | |
1599 | } | |
1600 | ||
57f350b6 JB |
1601 | static int i915_dpio_info(struct seq_file *m, void *data) |
1602 | { | |
1603 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1604 | struct drm_device *dev = node->minor->dev; | |
1605 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1606 | int ret; | |
1607 | ||
1608 | ||
1609 | if (!IS_VALLEYVIEW(dev)) { | |
267f0c90 | 1610 | seq_puts(m, "unsupported\n"); |
57f350b6 JB |
1611 | return 0; |
1612 | } | |
1613 | ||
09153000 | 1614 | ret = mutex_lock_interruptible(&dev_priv->dpio_lock); |
57f350b6 JB |
1615 | if (ret) |
1616 | return ret; | |
1617 | ||
1618 | seq_printf(m, "DPIO_CTL: 0x%08x\n", I915_READ(DPIO_CTL)); | |
1619 | ||
1620 | seq_printf(m, "DPIO_DIV_A: 0x%08x\n", | |
5e69f97f | 1621 | vlv_dpio_read(dev_priv, PIPE_A, _DPIO_DIV_A)); |
57f350b6 | 1622 | seq_printf(m, "DPIO_DIV_B: 0x%08x\n", |
5e69f97f | 1623 | vlv_dpio_read(dev_priv, PIPE_A, _DPIO_DIV_B)); |
57f350b6 JB |
1624 | |
1625 | seq_printf(m, "DPIO_REFSFR_A: 0x%08x\n", | |
5e69f97f | 1626 | vlv_dpio_read(dev_priv, PIPE_A, _DPIO_REFSFR_A)); |
57f350b6 | 1627 | seq_printf(m, "DPIO_REFSFR_B: 0x%08x\n", |
5e69f97f | 1628 | vlv_dpio_read(dev_priv, PIPE_A, _DPIO_REFSFR_B)); |
57f350b6 JB |
1629 | |
1630 | seq_printf(m, "DPIO_CORE_CLK_A: 0x%08x\n", | |
5e69f97f | 1631 | vlv_dpio_read(dev_priv, PIPE_A, _DPIO_CORE_CLK_A)); |
57f350b6 | 1632 | seq_printf(m, "DPIO_CORE_CLK_B: 0x%08x\n", |
5e69f97f | 1633 | vlv_dpio_read(dev_priv, PIPE_A, _DPIO_CORE_CLK_B)); |
57f350b6 | 1634 | |
4abb2c39 | 1635 | seq_printf(m, "DPIO_LPF_COEFF_A: 0x%08x\n", |
5e69f97f | 1636 | vlv_dpio_read(dev_priv, PIPE_A, _DPIO_LPF_COEFF_A)); |
4abb2c39 | 1637 | seq_printf(m, "DPIO_LPF_COEFF_B: 0x%08x\n", |
5e69f97f | 1638 | vlv_dpio_read(dev_priv, PIPE_A, _DPIO_LPF_COEFF_B)); |
57f350b6 JB |
1639 | |
1640 | seq_printf(m, "DPIO_FASTCLK_DISABLE: 0x%08x\n", | |
5e69f97f | 1641 | vlv_dpio_read(dev_priv, PIPE_A, DPIO_FASTCLK_DISABLE)); |
57f350b6 | 1642 | |
09153000 | 1643 | mutex_unlock(&dev_priv->dpio_lock); |
57f350b6 JB |
1644 | |
1645 | return 0; | |
1646 | } | |
1647 | ||
63573eb7 BW |
1648 | static int i915_llc(struct seq_file *m, void *data) |
1649 | { | |
1650 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1651 | struct drm_device *dev = node->minor->dev; | |
1652 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1653 | ||
1654 | /* Size calculation for LLC is a bit of a pain. Ignore for now. */ | |
1655 | seq_printf(m, "LLC: %s\n", yesno(HAS_LLC(dev))); | |
1656 | seq_printf(m, "eLLC: %zuMB\n", dev_priv->ellc_size); | |
1657 | ||
1658 | return 0; | |
1659 | } | |
1660 | ||
e91fd8c6 RV |
1661 | static int i915_edp_psr_status(struct seq_file *m, void *data) |
1662 | { | |
1663 | struct drm_info_node *node = m->private; | |
1664 | struct drm_device *dev = node->minor->dev; | |
1665 | struct drm_i915_private *dev_priv = dev->dev_private; | |
a031d709 RV |
1666 | u32 psrperf = 0; |
1667 | bool enabled = false; | |
e91fd8c6 | 1668 | |
a031d709 RV |
1669 | seq_printf(m, "Sink_Support: %s\n", yesno(dev_priv->psr.sink_support)); |
1670 | seq_printf(m, "Source_OK: %s\n", yesno(dev_priv->psr.source_ok)); | |
e91fd8c6 | 1671 | |
a031d709 RV |
1672 | enabled = HAS_PSR(dev) && |
1673 | I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE; | |
1674 | seq_printf(m, "Enabled: %s\n", yesno(enabled)); | |
e91fd8c6 | 1675 | |
a031d709 RV |
1676 | if (HAS_PSR(dev)) |
1677 | psrperf = I915_READ(EDP_PSR_PERF_CNT(dev)) & | |
1678 | EDP_PSR_PERF_CNT_MASK; | |
1679 | seq_printf(m, "Performance_Counter: %u\n", psrperf); | |
e91fd8c6 RV |
1680 | |
1681 | return 0; | |
1682 | } | |
1683 | ||
ec013e7f JB |
1684 | static int i915_energy_uJ(struct seq_file *m, void *data) |
1685 | { | |
1686 | struct drm_info_node *node = m->private; | |
1687 | struct drm_device *dev = node->minor->dev; | |
1688 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1689 | u64 power; | |
1690 | u32 units; | |
1691 | ||
1692 | if (INTEL_INFO(dev)->gen < 6) | |
1693 | return -ENODEV; | |
1694 | ||
1695 | rdmsrl(MSR_RAPL_POWER_UNIT, power); | |
1696 | power = (power & 0x1f00) >> 8; | |
1697 | units = 1000000 / (1 << power); /* convert to uJ */ | |
1698 | power = I915_READ(MCH_SECP_NRG_STTS); | |
1699 | power *= units; | |
1700 | ||
1701 | seq_printf(m, "%llu", (long long unsigned)power); | |
371db66a PZ |
1702 | |
1703 | return 0; | |
1704 | } | |
1705 | ||
1706 | static int i915_pc8_status(struct seq_file *m, void *unused) | |
1707 | { | |
1708 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1709 | struct drm_device *dev = node->minor->dev; | |
1710 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1711 | ||
1712 | if (!IS_HASWELL(dev)) { | |
1713 | seq_puts(m, "not supported\n"); | |
1714 | return 0; | |
1715 | } | |
1716 | ||
1717 | mutex_lock(&dev_priv->pc8.lock); | |
1718 | seq_printf(m, "Requirements met: %s\n", | |
1719 | yesno(dev_priv->pc8.requirements_met)); | |
1720 | seq_printf(m, "GPU idle: %s\n", yesno(dev_priv->pc8.gpu_idle)); | |
1721 | seq_printf(m, "Disable count: %d\n", dev_priv->pc8.disable_count); | |
1722 | seq_printf(m, "IRQs disabled: %s\n", | |
1723 | yesno(dev_priv->pc8.irqs_disabled)); | |
1724 | seq_printf(m, "Enabled: %s\n", yesno(dev_priv->pc8.enabled)); | |
1725 | mutex_unlock(&dev_priv->pc8.lock); | |
1726 | ||
ec013e7f JB |
1727 | return 0; |
1728 | } | |
1729 | ||
647416f9 KC |
1730 | static int |
1731 | i915_wedged_get(void *data, u64 *val) | |
f3cd474b | 1732 | { |
647416f9 | 1733 | struct drm_device *dev = data; |
f3cd474b | 1734 | drm_i915_private_t *dev_priv = dev->dev_private; |
f3cd474b | 1735 | |
647416f9 | 1736 | *val = atomic_read(&dev_priv->gpu_error.reset_counter); |
f3cd474b | 1737 | |
647416f9 | 1738 | return 0; |
f3cd474b CW |
1739 | } |
1740 | ||
647416f9 KC |
1741 | static int |
1742 | i915_wedged_set(void *data, u64 val) | |
f3cd474b | 1743 | { |
647416f9 | 1744 | struct drm_device *dev = data; |
f3cd474b | 1745 | |
647416f9 | 1746 | DRM_INFO("Manually setting wedged to %llu\n", val); |
527f9e90 | 1747 | i915_handle_error(dev, val); |
f3cd474b | 1748 | |
647416f9 | 1749 | return 0; |
f3cd474b CW |
1750 | } |
1751 | ||
647416f9 KC |
1752 | DEFINE_SIMPLE_ATTRIBUTE(i915_wedged_fops, |
1753 | i915_wedged_get, i915_wedged_set, | |
3a3b4f98 | 1754 | "%llu\n"); |
f3cd474b | 1755 | |
647416f9 KC |
1756 | static int |
1757 | i915_ring_stop_get(void *data, u64 *val) | |
e5eb3d63 | 1758 | { |
647416f9 | 1759 | struct drm_device *dev = data; |
e5eb3d63 | 1760 | drm_i915_private_t *dev_priv = dev->dev_private; |
e5eb3d63 | 1761 | |
647416f9 | 1762 | *val = dev_priv->gpu_error.stop_rings; |
e5eb3d63 | 1763 | |
647416f9 | 1764 | return 0; |
e5eb3d63 DV |
1765 | } |
1766 | ||
647416f9 KC |
1767 | static int |
1768 | i915_ring_stop_set(void *data, u64 val) | |
e5eb3d63 | 1769 | { |
647416f9 | 1770 | struct drm_device *dev = data; |
e5eb3d63 | 1771 | struct drm_i915_private *dev_priv = dev->dev_private; |
647416f9 | 1772 | int ret; |
e5eb3d63 | 1773 | |
647416f9 | 1774 | DRM_DEBUG_DRIVER("Stopping rings 0x%08llx\n", val); |
e5eb3d63 | 1775 | |
22bcfc6a DV |
1776 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
1777 | if (ret) | |
1778 | return ret; | |
1779 | ||
99584db3 | 1780 | dev_priv->gpu_error.stop_rings = val; |
e5eb3d63 DV |
1781 | mutex_unlock(&dev->struct_mutex); |
1782 | ||
647416f9 | 1783 | return 0; |
e5eb3d63 DV |
1784 | } |
1785 | ||
647416f9 KC |
1786 | DEFINE_SIMPLE_ATTRIBUTE(i915_ring_stop_fops, |
1787 | i915_ring_stop_get, i915_ring_stop_set, | |
1788 | "0x%08llx\n"); | |
d5442303 | 1789 | |
094f9a54 CW |
1790 | static int |
1791 | i915_ring_missed_irq_get(void *data, u64 *val) | |
1792 | { | |
1793 | struct drm_device *dev = data; | |
1794 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1795 | ||
1796 | *val = dev_priv->gpu_error.missed_irq_rings; | |
1797 | return 0; | |
1798 | } | |
1799 | ||
1800 | static int | |
1801 | i915_ring_missed_irq_set(void *data, u64 val) | |
1802 | { | |
1803 | struct drm_device *dev = data; | |
1804 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1805 | int ret; | |
1806 | ||
1807 | /* Lock against concurrent debugfs callers */ | |
1808 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
1809 | if (ret) | |
1810 | return ret; | |
1811 | dev_priv->gpu_error.missed_irq_rings = val; | |
1812 | mutex_unlock(&dev->struct_mutex); | |
1813 | ||
1814 | return 0; | |
1815 | } | |
1816 | ||
1817 | DEFINE_SIMPLE_ATTRIBUTE(i915_ring_missed_irq_fops, | |
1818 | i915_ring_missed_irq_get, i915_ring_missed_irq_set, | |
1819 | "0x%08llx\n"); | |
1820 | ||
1821 | static int | |
1822 | i915_ring_test_irq_get(void *data, u64 *val) | |
1823 | { | |
1824 | struct drm_device *dev = data; | |
1825 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1826 | ||
1827 | *val = dev_priv->gpu_error.test_irq_rings; | |
1828 | ||
1829 | return 0; | |
1830 | } | |
1831 | ||
1832 | static int | |
1833 | i915_ring_test_irq_set(void *data, u64 val) | |
1834 | { | |
1835 | struct drm_device *dev = data; | |
1836 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1837 | int ret; | |
1838 | ||
1839 | DRM_DEBUG_DRIVER("Masking interrupts on rings 0x%08llx\n", val); | |
1840 | ||
1841 | /* Lock against concurrent debugfs callers */ | |
1842 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
1843 | if (ret) | |
1844 | return ret; | |
1845 | ||
1846 | dev_priv->gpu_error.test_irq_rings = val; | |
1847 | mutex_unlock(&dev->struct_mutex); | |
1848 | ||
1849 | return 0; | |
1850 | } | |
1851 | ||
1852 | DEFINE_SIMPLE_ATTRIBUTE(i915_ring_test_irq_fops, | |
1853 | i915_ring_test_irq_get, i915_ring_test_irq_set, | |
1854 | "0x%08llx\n"); | |
1855 | ||
dd624afd CW |
1856 | #define DROP_UNBOUND 0x1 |
1857 | #define DROP_BOUND 0x2 | |
1858 | #define DROP_RETIRE 0x4 | |
1859 | #define DROP_ACTIVE 0x8 | |
1860 | #define DROP_ALL (DROP_UNBOUND | \ | |
1861 | DROP_BOUND | \ | |
1862 | DROP_RETIRE | \ | |
1863 | DROP_ACTIVE) | |
647416f9 KC |
1864 | static int |
1865 | i915_drop_caches_get(void *data, u64 *val) | |
dd624afd | 1866 | { |
647416f9 | 1867 | *val = DROP_ALL; |
dd624afd | 1868 | |
647416f9 | 1869 | return 0; |
dd624afd CW |
1870 | } |
1871 | ||
647416f9 KC |
1872 | static int |
1873 | i915_drop_caches_set(void *data, u64 val) | |
dd624afd | 1874 | { |
647416f9 | 1875 | struct drm_device *dev = data; |
dd624afd CW |
1876 | struct drm_i915_private *dev_priv = dev->dev_private; |
1877 | struct drm_i915_gem_object *obj, *next; | |
ca191b13 BW |
1878 | struct i915_address_space *vm; |
1879 | struct i915_vma *vma, *x; | |
647416f9 | 1880 | int ret; |
dd624afd | 1881 | |
647416f9 | 1882 | DRM_DEBUG_DRIVER("Dropping caches: 0x%08llx\n", val); |
dd624afd CW |
1883 | |
1884 | /* No need to check and wait for gpu resets, only libdrm auto-restarts | |
1885 | * on ioctls on -EAGAIN. */ | |
1886 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
1887 | if (ret) | |
1888 | return ret; | |
1889 | ||
1890 | if (val & DROP_ACTIVE) { | |
1891 | ret = i915_gpu_idle(dev); | |
1892 | if (ret) | |
1893 | goto unlock; | |
1894 | } | |
1895 | ||
1896 | if (val & (DROP_RETIRE | DROP_ACTIVE)) | |
1897 | i915_gem_retire_requests(dev); | |
1898 | ||
1899 | if (val & DROP_BOUND) { | |
ca191b13 BW |
1900 | list_for_each_entry(vm, &dev_priv->vm_list, global_link) { |
1901 | list_for_each_entry_safe(vma, x, &vm->inactive_list, | |
1902 | mm_list) { | |
1903 | if (vma->obj->pin_count) | |
1904 | continue; | |
1905 | ||
1906 | ret = i915_vma_unbind(vma); | |
1907 | if (ret) | |
1908 | goto unlock; | |
1909 | } | |
31a46c9c | 1910 | } |
dd624afd CW |
1911 | } |
1912 | ||
1913 | if (val & DROP_UNBOUND) { | |
35c20a60 BW |
1914 | list_for_each_entry_safe(obj, next, &dev_priv->mm.unbound_list, |
1915 | global_list) | |
dd624afd CW |
1916 | if (obj->pages_pin_count == 0) { |
1917 | ret = i915_gem_object_put_pages(obj); | |
1918 | if (ret) | |
1919 | goto unlock; | |
1920 | } | |
1921 | } | |
1922 | ||
1923 | unlock: | |
1924 | mutex_unlock(&dev->struct_mutex); | |
1925 | ||
647416f9 | 1926 | return ret; |
dd624afd CW |
1927 | } |
1928 | ||
647416f9 KC |
1929 | DEFINE_SIMPLE_ATTRIBUTE(i915_drop_caches_fops, |
1930 | i915_drop_caches_get, i915_drop_caches_set, | |
1931 | "0x%08llx\n"); | |
dd624afd | 1932 | |
647416f9 KC |
1933 | static int |
1934 | i915_max_freq_get(void *data, u64 *val) | |
358733e9 | 1935 | { |
647416f9 | 1936 | struct drm_device *dev = data; |
358733e9 | 1937 | drm_i915_private_t *dev_priv = dev->dev_private; |
647416f9 | 1938 | int ret; |
004777cb DV |
1939 | |
1940 | if (!(IS_GEN6(dev) || IS_GEN7(dev))) | |
1941 | return -ENODEV; | |
1942 | ||
4fc688ce | 1943 | ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock); |
004777cb DV |
1944 | if (ret) |
1945 | return ret; | |
358733e9 | 1946 | |
0a073b84 JB |
1947 | if (IS_VALLEYVIEW(dev)) |
1948 | *val = vlv_gpu_freq(dev_priv->mem_freq, | |
1949 | dev_priv->rps.max_delay); | |
1950 | else | |
1951 | *val = dev_priv->rps.max_delay * GT_FREQUENCY_MULTIPLIER; | |
4fc688ce | 1952 | mutex_unlock(&dev_priv->rps.hw_lock); |
358733e9 | 1953 | |
647416f9 | 1954 | return 0; |
358733e9 JB |
1955 | } |
1956 | ||
647416f9 KC |
1957 | static int |
1958 | i915_max_freq_set(void *data, u64 val) | |
358733e9 | 1959 | { |
647416f9 | 1960 | struct drm_device *dev = data; |
358733e9 | 1961 | struct drm_i915_private *dev_priv = dev->dev_private; |
647416f9 | 1962 | int ret; |
004777cb DV |
1963 | |
1964 | if (!(IS_GEN6(dev) || IS_GEN7(dev))) | |
1965 | return -ENODEV; | |
358733e9 | 1966 | |
647416f9 | 1967 | DRM_DEBUG_DRIVER("Manually setting max freq to %llu\n", val); |
358733e9 | 1968 | |
4fc688ce | 1969 | ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock); |
004777cb DV |
1970 | if (ret) |
1971 | return ret; | |
1972 | ||
358733e9 JB |
1973 | /* |
1974 | * Turbo will still be enabled, but won't go above the set value. | |
1975 | */ | |
0a073b84 JB |
1976 | if (IS_VALLEYVIEW(dev)) { |
1977 | val = vlv_freq_opcode(dev_priv->mem_freq, val); | |
1978 | dev_priv->rps.max_delay = val; | |
1979 | gen6_set_rps(dev, val); | |
1980 | } else { | |
1981 | do_div(val, GT_FREQUENCY_MULTIPLIER); | |
1982 | dev_priv->rps.max_delay = val; | |
1983 | gen6_set_rps(dev, val); | |
1984 | } | |
1985 | ||
4fc688ce | 1986 | mutex_unlock(&dev_priv->rps.hw_lock); |
358733e9 | 1987 | |
647416f9 | 1988 | return 0; |
358733e9 JB |
1989 | } |
1990 | ||
647416f9 KC |
1991 | DEFINE_SIMPLE_ATTRIBUTE(i915_max_freq_fops, |
1992 | i915_max_freq_get, i915_max_freq_set, | |
3a3b4f98 | 1993 | "%llu\n"); |
358733e9 | 1994 | |
647416f9 KC |
1995 | static int |
1996 | i915_min_freq_get(void *data, u64 *val) | |
1523c310 | 1997 | { |
647416f9 | 1998 | struct drm_device *dev = data; |
1523c310 | 1999 | drm_i915_private_t *dev_priv = dev->dev_private; |
647416f9 | 2000 | int ret; |
004777cb DV |
2001 | |
2002 | if (!(IS_GEN6(dev) || IS_GEN7(dev))) | |
2003 | return -ENODEV; | |
2004 | ||
4fc688ce | 2005 | ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock); |
004777cb DV |
2006 | if (ret) |
2007 | return ret; | |
1523c310 | 2008 | |
0a073b84 JB |
2009 | if (IS_VALLEYVIEW(dev)) |
2010 | *val = vlv_gpu_freq(dev_priv->mem_freq, | |
2011 | dev_priv->rps.min_delay); | |
2012 | else | |
2013 | *val = dev_priv->rps.min_delay * GT_FREQUENCY_MULTIPLIER; | |
4fc688ce | 2014 | mutex_unlock(&dev_priv->rps.hw_lock); |
1523c310 | 2015 | |
647416f9 | 2016 | return 0; |
1523c310 JB |
2017 | } |
2018 | ||
647416f9 KC |
2019 | static int |
2020 | i915_min_freq_set(void *data, u64 val) | |
1523c310 | 2021 | { |
647416f9 | 2022 | struct drm_device *dev = data; |
1523c310 | 2023 | struct drm_i915_private *dev_priv = dev->dev_private; |
647416f9 | 2024 | int ret; |
004777cb DV |
2025 | |
2026 | if (!(IS_GEN6(dev) || IS_GEN7(dev))) | |
2027 | return -ENODEV; | |
1523c310 | 2028 | |
647416f9 | 2029 | DRM_DEBUG_DRIVER("Manually setting min freq to %llu\n", val); |
1523c310 | 2030 | |
4fc688ce | 2031 | ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock); |
004777cb DV |
2032 | if (ret) |
2033 | return ret; | |
2034 | ||
1523c310 JB |
2035 | /* |
2036 | * Turbo will still be enabled, but won't go below the set value. | |
2037 | */ | |
0a073b84 JB |
2038 | if (IS_VALLEYVIEW(dev)) { |
2039 | val = vlv_freq_opcode(dev_priv->mem_freq, val); | |
2040 | dev_priv->rps.min_delay = val; | |
2041 | valleyview_set_rps(dev, val); | |
2042 | } else { | |
2043 | do_div(val, GT_FREQUENCY_MULTIPLIER); | |
2044 | dev_priv->rps.min_delay = val; | |
2045 | gen6_set_rps(dev, val); | |
2046 | } | |
4fc688ce | 2047 | mutex_unlock(&dev_priv->rps.hw_lock); |
1523c310 | 2048 | |
647416f9 | 2049 | return 0; |
1523c310 JB |
2050 | } |
2051 | ||
647416f9 KC |
2052 | DEFINE_SIMPLE_ATTRIBUTE(i915_min_freq_fops, |
2053 | i915_min_freq_get, i915_min_freq_set, | |
3a3b4f98 | 2054 | "%llu\n"); |
1523c310 | 2055 | |
647416f9 KC |
2056 | static int |
2057 | i915_cache_sharing_get(void *data, u64 *val) | |
07b7ddd9 | 2058 | { |
647416f9 | 2059 | struct drm_device *dev = data; |
07b7ddd9 | 2060 | drm_i915_private_t *dev_priv = dev->dev_private; |
07b7ddd9 | 2061 | u32 snpcr; |
647416f9 | 2062 | int ret; |
07b7ddd9 | 2063 | |
004777cb DV |
2064 | if (!(IS_GEN6(dev) || IS_GEN7(dev))) |
2065 | return -ENODEV; | |
2066 | ||
22bcfc6a DV |
2067 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
2068 | if (ret) | |
2069 | return ret; | |
2070 | ||
07b7ddd9 JB |
2071 | snpcr = I915_READ(GEN6_MBCUNIT_SNPCR); |
2072 | mutex_unlock(&dev_priv->dev->struct_mutex); | |
2073 | ||
647416f9 | 2074 | *val = (snpcr & GEN6_MBC_SNPCR_MASK) >> GEN6_MBC_SNPCR_SHIFT; |
07b7ddd9 | 2075 | |
647416f9 | 2076 | return 0; |
07b7ddd9 JB |
2077 | } |
2078 | ||
647416f9 KC |
2079 | static int |
2080 | i915_cache_sharing_set(void *data, u64 val) | |
07b7ddd9 | 2081 | { |
647416f9 | 2082 | struct drm_device *dev = data; |
07b7ddd9 | 2083 | struct drm_i915_private *dev_priv = dev->dev_private; |
07b7ddd9 | 2084 | u32 snpcr; |
07b7ddd9 | 2085 | |
004777cb DV |
2086 | if (!(IS_GEN6(dev) || IS_GEN7(dev))) |
2087 | return -ENODEV; | |
2088 | ||
647416f9 | 2089 | if (val > 3) |
07b7ddd9 JB |
2090 | return -EINVAL; |
2091 | ||
647416f9 | 2092 | DRM_DEBUG_DRIVER("Manually setting uncore sharing to %llu\n", val); |
07b7ddd9 JB |
2093 | |
2094 | /* Update the cache sharing policy here as well */ | |
2095 | snpcr = I915_READ(GEN6_MBCUNIT_SNPCR); | |
2096 | snpcr &= ~GEN6_MBC_SNPCR_MASK; | |
2097 | snpcr |= (val << GEN6_MBC_SNPCR_SHIFT); | |
2098 | I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr); | |
2099 | ||
647416f9 | 2100 | return 0; |
07b7ddd9 JB |
2101 | } |
2102 | ||
647416f9 KC |
2103 | DEFINE_SIMPLE_ATTRIBUTE(i915_cache_sharing_fops, |
2104 | i915_cache_sharing_get, i915_cache_sharing_set, | |
2105 | "%llu\n"); | |
07b7ddd9 | 2106 | |
f3cd474b CW |
2107 | /* As the drm_debugfs_init() routines are called before dev->dev_private is |
2108 | * allocated we need to hook into the minor for release. */ | |
2109 | static int | |
2110 | drm_add_fake_info_node(struct drm_minor *minor, | |
2111 | struct dentry *ent, | |
2112 | const void *key) | |
2113 | { | |
2114 | struct drm_info_node *node; | |
2115 | ||
b14c5679 | 2116 | node = kmalloc(sizeof(*node), GFP_KERNEL); |
f3cd474b CW |
2117 | if (node == NULL) { |
2118 | debugfs_remove(ent); | |
2119 | return -ENOMEM; | |
2120 | } | |
2121 | ||
2122 | node->minor = minor; | |
2123 | node->dent = ent; | |
2124 | node->info_ent = (void *) key; | |
b3e067c0 MS |
2125 | |
2126 | mutex_lock(&minor->debugfs_lock); | |
2127 | list_add(&node->list, &minor->debugfs_list); | |
2128 | mutex_unlock(&minor->debugfs_lock); | |
f3cd474b CW |
2129 | |
2130 | return 0; | |
2131 | } | |
2132 | ||
6d794d42 BW |
2133 | static int i915_forcewake_open(struct inode *inode, struct file *file) |
2134 | { | |
2135 | struct drm_device *dev = inode->i_private; | |
2136 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6d794d42 | 2137 | |
075edca4 | 2138 | if (INTEL_INFO(dev)->gen < 6) |
6d794d42 BW |
2139 | return 0; |
2140 | ||
6d794d42 | 2141 | gen6_gt_force_wake_get(dev_priv); |
6d794d42 BW |
2142 | |
2143 | return 0; | |
2144 | } | |
2145 | ||
c43b5634 | 2146 | static int i915_forcewake_release(struct inode *inode, struct file *file) |
6d794d42 BW |
2147 | { |
2148 | struct drm_device *dev = inode->i_private; | |
2149 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2150 | ||
075edca4 | 2151 | if (INTEL_INFO(dev)->gen < 6) |
6d794d42 BW |
2152 | return 0; |
2153 | ||
6d794d42 | 2154 | gen6_gt_force_wake_put(dev_priv); |
6d794d42 BW |
2155 | |
2156 | return 0; | |
2157 | } | |
2158 | ||
2159 | static const struct file_operations i915_forcewake_fops = { | |
2160 | .owner = THIS_MODULE, | |
2161 | .open = i915_forcewake_open, | |
2162 | .release = i915_forcewake_release, | |
2163 | }; | |
2164 | ||
2165 | static int i915_forcewake_create(struct dentry *root, struct drm_minor *minor) | |
2166 | { | |
2167 | struct drm_device *dev = minor->dev; | |
2168 | struct dentry *ent; | |
2169 | ||
2170 | ent = debugfs_create_file("i915_forcewake_user", | |
8eb57294 | 2171 | S_IRUSR, |
6d794d42 BW |
2172 | root, dev, |
2173 | &i915_forcewake_fops); | |
2174 | if (IS_ERR(ent)) | |
2175 | return PTR_ERR(ent); | |
2176 | ||
8eb57294 | 2177 | return drm_add_fake_info_node(minor, ent, &i915_forcewake_fops); |
6d794d42 BW |
2178 | } |
2179 | ||
6a9c308d DV |
2180 | static int i915_debugfs_create(struct dentry *root, |
2181 | struct drm_minor *minor, | |
2182 | const char *name, | |
2183 | const struct file_operations *fops) | |
07b7ddd9 JB |
2184 | { |
2185 | struct drm_device *dev = minor->dev; | |
2186 | struct dentry *ent; | |
2187 | ||
6a9c308d | 2188 | ent = debugfs_create_file(name, |
07b7ddd9 JB |
2189 | S_IRUGO | S_IWUSR, |
2190 | root, dev, | |
6a9c308d | 2191 | fops); |
07b7ddd9 JB |
2192 | if (IS_ERR(ent)) |
2193 | return PTR_ERR(ent); | |
2194 | ||
6a9c308d | 2195 | return drm_add_fake_info_node(minor, ent, fops); |
07b7ddd9 JB |
2196 | } |
2197 | ||
27c202ad | 2198 | static struct drm_info_list i915_debugfs_list[] = { |
311bd68e | 2199 | {"i915_capabilities", i915_capabilities, 0}, |
73aa808f | 2200 | {"i915_gem_objects", i915_gem_object_info, 0}, |
08c18323 | 2201 | {"i915_gem_gtt", i915_gem_gtt_info, 0}, |
1b50247a | 2202 | {"i915_gem_pinned", i915_gem_gtt_info, 0, (void *) PINNED_LIST}, |
433e12f7 | 2203 | {"i915_gem_active", i915_gem_object_list_info, 0, (void *) ACTIVE_LIST}, |
433e12f7 | 2204 | {"i915_gem_inactive", i915_gem_object_list_info, 0, (void *) INACTIVE_LIST}, |
6d2b8885 | 2205 | {"i915_gem_stolen", i915_gem_stolen_list_info }, |
4e5359cd | 2206 | {"i915_gem_pageflip", i915_gem_pageflip_info, 0}, |
2017263e BG |
2207 | {"i915_gem_request", i915_gem_request_info, 0}, |
2208 | {"i915_gem_seqno", i915_gem_seqno_info, 0}, | |
a6172a80 | 2209 | {"i915_gem_fence_regs", i915_gem_fence_regs_info, 0}, |
2017263e | 2210 | {"i915_gem_interrupt", i915_interrupt_info, 0}, |
1ec14ad3 CW |
2211 | {"i915_gem_hws", i915_hws_info, 0, (void *)RCS}, |
2212 | {"i915_gem_hws_blt", i915_hws_info, 0, (void *)BCS}, | |
2213 | {"i915_gem_hws_bsd", i915_hws_info, 0, (void *)VCS}, | |
9010ebfd | 2214 | {"i915_gem_hws_vebox", i915_hws_info, 0, (void *)VECS}, |
f97108d1 JB |
2215 | {"i915_rstdby_delays", i915_rstdby_delays, 0}, |
2216 | {"i915_cur_delayinfo", i915_cur_delayinfo, 0}, | |
2217 | {"i915_delayfreq_table", i915_delayfreq_table, 0}, | |
2218 | {"i915_inttoext_table", i915_inttoext_table, 0}, | |
2219 | {"i915_drpc_info", i915_drpc_info, 0}, | |
7648fa99 | 2220 | {"i915_emon_status", i915_emon_status, 0}, |
23b2f8bb | 2221 | {"i915_ring_freq_table", i915_ring_freq_table, 0}, |
7648fa99 | 2222 | {"i915_gfxec", i915_gfxec, 0}, |
b5e50c3f | 2223 | {"i915_fbc_status", i915_fbc_status, 0}, |
92d44621 | 2224 | {"i915_ips_status", i915_ips_status, 0}, |
4a9bef37 | 2225 | {"i915_sr_status", i915_sr_status, 0}, |
44834a67 | 2226 | {"i915_opregion", i915_opregion, 0}, |
37811fcc | 2227 | {"i915_gem_framebuffer", i915_gem_framebuffer_info, 0}, |
e76d3630 | 2228 | {"i915_context_status", i915_context_status, 0}, |
6d794d42 | 2229 | {"i915_gen6_forcewake_count", i915_gen6_forcewake_count_info, 0}, |
ea16a3cd | 2230 | {"i915_swizzle_info", i915_swizzle_info, 0}, |
3cf17fc5 | 2231 | {"i915_ppgtt_info", i915_ppgtt_info, 0}, |
57f350b6 | 2232 | {"i915_dpio", i915_dpio_info, 0}, |
63573eb7 | 2233 | {"i915_llc", i915_llc, 0}, |
e91fd8c6 | 2234 | {"i915_edp_psr_status", i915_edp_psr_status, 0}, |
ec013e7f | 2235 | {"i915_energy_uJ", i915_energy_uJ, 0}, |
371db66a | 2236 | {"i915_pc8_status", i915_pc8_status, 0}, |
2017263e | 2237 | }; |
27c202ad | 2238 | #define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list) |
2017263e | 2239 | |
2b4bd0e0 | 2240 | static struct i915_debugfs_files { |
34b9674c DV |
2241 | const char *name; |
2242 | const struct file_operations *fops; | |
2243 | } i915_debugfs_files[] = { | |
2244 | {"i915_wedged", &i915_wedged_fops}, | |
2245 | {"i915_max_freq", &i915_max_freq_fops}, | |
2246 | {"i915_min_freq", &i915_min_freq_fops}, | |
2247 | {"i915_cache_sharing", &i915_cache_sharing_fops}, | |
2248 | {"i915_ring_stop", &i915_ring_stop_fops}, | |
094f9a54 CW |
2249 | {"i915_ring_missed_irq", &i915_ring_missed_irq_fops}, |
2250 | {"i915_ring_test_irq", &i915_ring_test_irq_fops}, | |
34b9674c DV |
2251 | {"i915_gem_drop_caches", &i915_drop_caches_fops}, |
2252 | {"i915_error_state", &i915_error_state_fops}, | |
2253 | {"i915_next_seqno", &i915_next_seqno_fops}, | |
2254 | }; | |
2255 | ||
27c202ad | 2256 | int i915_debugfs_init(struct drm_minor *minor) |
2017263e | 2257 | { |
34b9674c | 2258 | int ret, i; |
f3cd474b | 2259 | |
6d794d42 | 2260 | ret = i915_forcewake_create(minor->debugfs_root, minor); |
358733e9 JB |
2261 | if (ret) |
2262 | return ret; | |
6a9c308d | 2263 | |
34b9674c DV |
2264 | for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) { |
2265 | ret = i915_debugfs_create(minor->debugfs_root, minor, | |
2266 | i915_debugfs_files[i].name, | |
2267 | i915_debugfs_files[i].fops); | |
2268 | if (ret) | |
2269 | return ret; | |
2270 | } | |
40633219 | 2271 | |
27c202ad BG |
2272 | return drm_debugfs_create_files(i915_debugfs_list, |
2273 | I915_DEBUGFS_ENTRIES, | |
2017263e BG |
2274 | minor->debugfs_root, minor); |
2275 | } | |
2276 | ||
27c202ad | 2277 | void i915_debugfs_cleanup(struct drm_minor *minor) |
2017263e | 2278 | { |
34b9674c DV |
2279 | int i; |
2280 | ||
27c202ad BG |
2281 | drm_debugfs_remove_files(i915_debugfs_list, |
2282 | I915_DEBUGFS_ENTRIES, minor); | |
6d794d42 BW |
2283 | drm_debugfs_remove_files((struct drm_info_list *) &i915_forcewake_fops, |
2284 | 1, minor); | |
34b9674c DV |
2285 | for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) { |
2286 | struct drm_info_list *info_list = | |
2287 | (struct drm_info_list *) i915_debugfs_files[i].fops; | |
2288 | ||
2289 | drm_debugfs_remove_files(info_list, 1, minor); | |
2290 | } | |
2017263e BG |
2291 | } |
2292 | ||
2293 | #endif /* CONFIG_DEBUG_FS */ |