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Commit | Line | Data |
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2017263e BG |
1 | /* |
2 | * Copyright © 2008 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | * Keith Packard <keithp@keithp.com> | |
26 | * | |
27 | */ | |
28 | ||
29 | #include <linux/seq_file.h> | |
b2c88f5b | 30 | #include <linux/circ_buf.h> |
926321d5 | 31 | #include <linux/ctype.h> |
f3cd474b | 32 | #include <linux/debugfs.h> |
5a0e3ad6 | 33 | #include <linux/slab.h> |
2d1a8a48 | 34 | #include <linux/export.h> |
6d2b8885 | 35 | #include <linux/list_sort.h> |
ec013e7f | 36 | #include <asm/msr-index.h> |
760285e7 | 37 | #include <drm/drmP.h> |
4e5359cd | 38 | #include "intel_drv.h" |
e5c65260 | 39 | #include "intel_ringbuffer.h" |
760285e7 | 40 | #include <drm/i915_drm.h> |
2017263e BG |
41 | #include "i915_drv.h" |
42 | ||
f13d3f73 | 43 | enum { |
69dc4987 | 44 | ACTIVE_LIST, |
f13d3f73 | 45 | INACTIVE_LIST, |
d21d5975 | 46 | PINNED_LIST, |
f13d3f73 | 47 | }; |
2017263e | 48 | |
497666d8 DL |
49 | /* As the drm_debugfs_init() routines are called before dev->dev_private is |
50 | * allocated we need to hook into the minor for release. */ | |
51 | static int | |
52 | drm_add_fake_info_node(struct drm_minor *minor, | |
53 | struct dentry *ent, | |
54 | const void *key) | |
55 | { | |
56 | struct drm_info_node *node; | |
57 | ||
58 | node = kmalloc(sizeof(*node), GFP_KERNEL); | |
59 | if (node == NULL) { | |
60 | debugfs_remove(ent); | |
61 | return -ENOMEM; | |
62 | } | |
63 | ||
64 | node->minor = minor; | |
65 | node->dent = ent; | |
66 | node->info_ent = (void *) key; | |
67 | ||
68 | mutex_lock(&minor->debugfs_lock); | |
69 | list_add(&node->list, &minor->debugfs_list); | |
70 | mutex_unlock(&minor->debugfs_lock); | |
71 | ||
72 | return 0; | |
73 | } | |
74 | ||
70d39fe4 CW |
75 | static int i915_capabilities(struct seq_file *m, void *data) |
76 | { | |
9f25d007 | 77 | struct drm_info_node *node = m->private; |
70d39fe4 CW |
78 | struct drm_device *dev = node->minor->dev; |
79 | const struct intel_device_info *info = INTEL_INFO(dev); | |
80 | ||
81 | seq_printf(m, "gen: %d\n", info->gen); | |
03d00ac5 | 82 | seq_printf(m, "pch: %d\n", INTEL_PCH_TYPE(dev)); |
79fc46df DL |
83 | #define PRINT_FLAG(x) seq_printf(m, #x ": %s\n", yesno(info->x)) |
84 | #define SEP_SEMICOLON ; | |
85 | DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG, SEP_SEMICOLON); | |
86 | #undef PRINT_FLAG | |
87 | #undef SEP_SEMICOLON | |
70d39fe4 CW |
88 | |
89 | return 0; | |
90 | } | |
2017263e | 91 | |
a7363de7 | 92 | static char get_active_flag(struct drm_i915_gem_object *obj) |
a6172a80 | 93 | { |
573adb39 | 94 | return i915_gem_object_is_active(obj) ? '*' : ' '; |
a6172a80 CW |
95 | } |
96 | ||
a7363de7 | 97 | static char get_pin_flag(struct drm_i915_gem_object *obj) |
be12a86b TU |
98 | { |
99 | return obj->pin_display ? 'p' : ' '; | |
100 | } | |
101 | ||
a7363de7 | 102 | static char get_tiling_flag(struct drm_i915_gem_object *obj) |
a6172a80 | 103 | { |
3e510a8e | 104 | switch (i915_gem_object_get_tiling(obj)) { |
0206e353 | 105 | default: |
be12a86b TU |
106 | case I915_TILING_NONE: return ' '; |
107 | case I915_TILING_X: return 'X'; | |
108 | case I915_TILING_Y: return 'Y'; | |
0206e353 | 109 | } |
a6172a80 CW |
110 | } |
111 | ||
a7363de7 | 112 | static char get_global_flag(struct drm_i915_gem_object *obj) |
be12a86b TU |
113 | { |
114 | return i915_gem_obj_to_ggtt(obj) ? 'g' : ' '; | |
115 | } | |
116 | ||
a7363de7 | 117 | static char get_pin_mapped_flag(struct drm_i915_gem_object *obj) |
1d693bcc | 118 | { |
be12a86b | 119 | return obj->mapping ? 'M' : ' '; |
1d693bcc BW |
120 | } |
121 | ||
ca1543be TU |
122 | static u64 i915_gem_obj_total_ggtt_size(struct drm_i915_gem_object *obj) |
123 | { | |
124 | u64 size = 0; | |
125 | struct i915_vma *vma; | |
126 | ||
1c7f4bca | 127 | list_for_each_entry(vma, &obj->vma_list, obj_link) { |
3272db53 | 128 | if (i915_vma_is_ggtt(vma) && drm_mm_node_allocated(&vma->node)) |
ca1543be TU |
129 | size += vma->node.size; |
130 | } | |
131 | ||
132 | return size; | |
133 | } | |
134 | ||
37811fcc CW |
135 | static void |
136 | describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj) | |
137 | { | |
b4716185 | 138 | struct drm_i915_private *dev_priv = to_i915(obj->base.dev); |
e2f80391 | 139 | struct intel_engine_cs *engine; |
1d693bcc | 140 | struct i915_vma *vma; |
faf5bf0a | 141 | unsigned int frontbuffer_bits; |
d7f46fc4 | 142 | int pin_count = 0; |
c3232b18 | 143 | enum intel_engine_id id; |
d7f46fc4 | 144 | |
188c1ab7 CW |
145 | lockdep_assert_held(&obj->base.dev->struct_mutex); |
146 | ||
be12a86b | 147 | seq_printf(m, "%pK: %c%c%c%c%c %8zdKiB %02x %02x [ ", |
37811fcc | 148 | &obj->base, |
be12a86b | 149 | get_active_flag(obj), |
37811fcc CW |
150 | get_pin_flag(obj), |
151 | get_tiling_flag(obj), | |
1d693bcc | 152 | get_global_flag(obj), |
be12a86b | 153 | get_pin_mapped_flag(obj), |
a05a5862 | 154 | obj->base.size / 1024, |
37811fcc | 155 | obj->base.read_domains, |
b4716185 | 156 | obj->base.write_domain); |
c3232b18 | 157 | for_each_engine_id(engine, dev_priv, id) |
b4716185 | 158 | seq_printf(m, "%x ", |
d72d908b CW |
159 | i915_gem_active_get_seqno(&obj->last_read[id], |
160 | &obj->base.dev->struct_mutex)); | |
b4716185 | 161 | seq_printf(m, "] %x %x%s%s%s", |
d72d908b CW |
162 | i915_gem_active_get_seqno(&obj->last_write, |
163 | &obj->base.dev->struct_mutex), | |
164 | i915_gem_active_get_seqno(&obj->last_fence, | |
165 | &obj->base.dev->struct_mutex), | |
0a4cd7c8 | 166 | i915_cache_level_str(to_i915(obj->base.dev), obj->cache_level), |
37811fcc CW |
167 | obj->dirty ? " dirty" : "", |
168 | obj->madv == I915_MADV_DONTNEED ? " purgeable" : ""); | |
169 | if (obj->base.name) | |
170 | seq_printf(m, " (name: %d)", obj->base.name); | |
1c7f4bca | 171 | list_for_each_entry(vma, &obj->vma_list, obj_link) { |
20dfbde4 | 172 | if (i915_vma_is_pinned(vma)) |
d7f46fc4 | 173 | pin_count++; |
ba0635ff DC |
174 | } |
175 | seq_printf(m, " (pinned x %d)", pin_count); | |
cc98b413 CW |
176 | if (obj->pin_display) |
177 | seq_printf(m, " (display)"); | |
37811fcc CW |
178 | if (obj->fence_reg != I915_FENCE_REG_NONE) |
179 | seq_printf(m, " (fence: %d)", obj->fence_reg); | |
1c7f4bca | 180 | list_for_each_entry(vma, &obj->vma_list, obj_link) { |
15717de2 CW |
181 | if (!drm_mm_node_allocated(&vma->node)) |
182 | continue; | |
183 | ||
8d2fdc3f | 184 | seq_printf(m, " (%sgtt offset: %08llx, size: %08llx", |
3272db53 | 185 | i915_vma_is_ggtt(vma) ? "g" : "pp", |
8d2fdc3f | 186 | vma->node.start, vma->node.size); |
3272db53 | 187 | if (i915_vma_is_ggtt(vma)) |
596c5923 CW |
188 | seq_printf(m, ", type: %u", vma->ggtt_view.type); |
189 | seq_puts(m, ")"); | |
1d693bcc | 190 | } |
c1ad11fc | 191 | if (obj->stolen) |
440fd528 | 192 | seq_printf(m, " (stolen: %08llx)", obj->stolen->start); |
30154650 | 193 | if (obj->pin_display || obj->fault_mappable) { |
6299f992 | 194 | char s[3], *t = s; |
30154650 | 195 | if (obj->pin_display) |
6299f992 CW |
196 | *t++ = 'p'; |
197 | if (obj->fault_mappable) | |
198 | *t++ = 'f'; | |
199 | *t = '\0'; | |
200 | seq_printf(m, " (%s mappable)", s); | |
201 | } | |
27c01aae | 202 | |
d72d908b CW |
203 | engine = i915_gem_active_get_engine(&obj->last_write, |
204 | &obj->base.dev->struct_mutex); | |
27c01aae CW |
205 | if (engine) |
206 | seq_printf(m, " (%s)", engine->name); | |
207 | ||
faf5bf0a CW |
208 | frontbuffer_bits = atomic_read(&obj->frontbuffer_bits); |
209 | if (frontbuffer_bits) | |
210 | seq_printf(m, " (frontbuffer: 0x%03x)", frontbuffer_bits); | |
37811fcc CW |
211 | } |
212 | ||
6d2b8885 CW |
213 | static int obj_rank_by_stolen(void *priv, |
214 | struct list_head *A, struct list_head *B) | |
215 | { | |
216 | struct drm_i915_gem_object *a = | |
b25cb2f8 | 217 | container_of(A, struct drm_i915_gem_object, obj_exec_link); |
6d2b8885 | 218 | struct drm_i915_gem_object *b = |
b25cb2f8 | 219 | container_of(B, struct drm_i915_gem_object, obj_exec_link); |
6d2b8885 | 220 | |
2d05fa16 RV |
221 | if (a->stolen->start < b->stolen->start) |
222 | return -1; | |
223 | if (a->stolen->start > b->stolen->start) | |
224 | return 1; | |
225 | return 0; | |
6d2b8885 CW |
226 | } |
227 | ||
228 | static int i915_gem_stolen_list_info(struct seq_file *m, void *data) | |
229 | { | |
9f25d007 | 230 | struct drm_info_node *node = m->private; |
6d2b8885 | 231 | struct drm_device *dev = node->minor->dev; |
fac5e23e | 232 | struct drm_i915_private *dev_priv = to_i915(dev); |
6d2b8885 | 233 | struct drm_i915_gem_object *obj; |
c44ef60e | 234 | u64 total_obj_size, total_gtt_size; |
6d2b8885 CW |
235 | LIST_HEAD(stolen); |
236 | int count, ret; | |
237 | ||
238 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
239 | if (ret) | |
240 | return ret; | |
241 | ||
242 | total_obj_size = total_gtt_size = count = 0; | |
243 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) { | |
244 | if (obj->stolen == NULL) | |
245 | continue; | |
246 | ||
b25cb2f8 | 247 | list_add(&obj->obj_exec_link, &stolen); |
6d2b8885 CW |
248 | |
249 | total_obj_size += obj->base.size; | |
ca1543be | 250 | total_gtt_size += i915_gem_obj_total_ggtt_size(obj); |
6d2b8885 CW |
251 | count++; |
252 | } | |
253 | list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) { | |
254 | if (obj->stolen == NULL) | |
255 | continue; | |
256 | ||
b25cb2f8 | 257 | list_add(&obj->obj_exec_link, &stolen); |
6d2b8885 CW |
258 | |
259 | total_obj_size += obj->base.size; | |
260 | count++; | |
261 | } | |
262 | list_sort(NULL, &stolen, obj_rank_by_stolen); | |
263 | seq_puts(m, "Stolen:\n"); | |
264 | while (!list_empty(&stolen)) { | |
b25cb2f8 | 265 | obj = list_first_entry(&stolen, typeof(*obj), obj_exec_link); |
6d2b8885 CW |
266 | seq_puts(m, " "); |
267 | describe_obj(m, obj); | |
268 | seq_putc(m, '\n'); | |
b25cb2f8 | 269 | list_del_init(&obj->obj_exec_link); |
6d2b8885 CW |
270 | } |
271 | mutex_unlock(&dev->struct_mutex); | |
272 | ||
c44ef60e | 273 | seq_printf(m, "Total %d objects, %llu bytes, %llu GTT size\n", |
6d2b8885 CW |
274 | count, total_obj_size, total_gtt_size); |
275 | return 0; | |
276 | } | |
277 | ||
6299f992 CW |
278 | #define count_objects(list, member) do { \ |
279 | list_for_each_entry(obj, list, member) { \ | |
ca1543be | 280 | size += i915_gem_obj_total_ggtt_size(obj); \ |
6299f992 CW |
281 | ++count; \ |
282 | if (obj->map_and_fenceable) { \ | |
f343c5f6 | 283 | mappable_size += i915_gem_obj_ggtt_size(obj); \ |
6299f992 CW |
284 | ++mappable_count; \ |
285 | } \ | |
286 | } \ | |
0206e353 | 287 | } while (0) |
6299f992 | 288 | |
2db8e9d6 | 289 | struct file_stats { |
6313c204 | 290 | struct drm_i915_file_private *file_priv; |
c44ef60e MK |
291 | unsigned long count; |
292 | u64 total, unbound; | |
293 | u64 global, shared; | |
294 | u64 active, inactive; | |
2db8e9d6 CW |
295 | }; |
296 | ||
297 | static int per_file_stats(int id, void *ptr, void *data) | |
298 | { | |
299 | struct drm_i915_gem_object *obj = ptr; | |
300 | struct file_stats *stats = data; | |
6313c204 | 301 | struct i915_vma *vma; |
2db8e9d6 CW |
302 | |
303 | stats->count++; | |
304 | stats->total += obj->base.size; | |
15717de2 CW |
305 | if (!obj->bind_count) |
306 | stats->unbound += obj->base.size; | |
c67a17e9 CW |
307 | if (obj->base.name || obj->base.dma_buf) |
308 | stats->shared += obj->base.size; | |
309 | ||
894eeecc CW |
310 | list_for_each_entry(vma, &obj->vma_list, obj_link) { |
311 | if (!drm_mm_node_allocated(&vma->node)) | |
312 | continue; | |
6313c204 | 313 | |
3272db53 | 314 | if (i915_vma_is_ggtt(vma)) { |
894eeecc CW |
315 | stats->global += vma->node.size; |
316 | } else { | |
317 | struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vma->vm); | |
6313c204 | 318 | |
2bfa996e | 319 | if (ppgtt->base.file != stats->file_priv) |
6313c204 | 320 | continue; |
6313c204 | 321 | } |
894eeecc | 322 | |
b0decaf7 | 323 | if (i915_vma_is_active(vma)) |
894eeecc CW |
324 | stats->active += vma->node.size; |
325 | else | |
326 | stats->inactive += vma->node.size; | |
2db8e9d6 CW |
327 | } |
328 | ||
329 | return 0; | |
330 | } | |
331 | ||
b0da1b79 CW |
332 | #define print_file_stats(m, name, stats) do { \ |
333 | if (stats.count) \ | |
c44ef60e | 334 | seq_printf(m, "%s: %lu objects, %llu bytes (%llu active, %llu inactive, %llu global, %llu shared, %llu unbound)\n", \ |
b0da1b79 CW |
335 | name, \ |
336 | stats.count, \ | |
337 | stats.total, \ | |
338 | stats.active, \ | |
339 | stats.inactive, \ | |
340 | stats.global, \ | |
341 | stats.shared, \ | |
342 | stats.unbound); \ | |
343 | } while (0) | |
493018dc BV |
344 | |
345 | static void print_batch_pool_stats(struct seq_file *m, | |
346 | struct drm_i915_private *dev_priv) | |
347 | { | |
348 | struct drm_i915_gem_object *obj; | |
349 | struct file_stats stats; | |
e2f80391 | 350 | struct intel_engine_cs *engine; |
b4ac5afc | 351 | int j; |
493018dc BV |
352 | |
353 | memset(&stats, 0, sizeof(stats)); | |
354 | ||
b4ac5afc | 355 | for_each_engine(engine, dev_priv) { |
e2f80391 | 356 | for (j = 0; j < ARRAY_SIZE(engine->batch_pool.cache_list); j++) { |
8d9d5744 | 357 | list_for_each_entry(obj, |
e2f80391 | 358 | &engine->batch_pool.cache_list[j], |
8d9d5744 CW |
359 | batch_pool_link) |
360 | per_file_stats(0, obj, &stats); | |
361 | } | |
06fbca71 | 362 | } |
493018dc | 363 | |
b0da1b79 | 364 | print_file_stats(m, "[k]batch pool", stats); |
493018dc BV |
365 | } |
366 | ||
15da9565 CW |
367 | static int per_file_ctx_stats(int id, void *ptr, void *data) |
368 | { | |
369 | struct i915_gem_context *ctx = ptr; | |
370 | int n; | |
371 | ||
372 | for (n = 0; n < ARRAY_SIZE(ctx->engine); n++) { | |
373 | if (ctx->engine[n].state) | |
374 | per_file_stats(0, ctx->engine[n].state, data); | |
dca33ecc CW |
375 | if (ctx->engine[n].ring) |
376 | per_file_stats(0, ctx->engine[n].ring->obj, data); | |
15da9565 CW |
377 | } |
378 | ||
379 | return 0; | |
380 | } | |
381 | ||
382 | static void print_context_stats(struct seq_file *m, | |
383 | struct drm_i915_private *dev_priv) | |
384 | { | |
385 | struct file_stats stats; | |
386 | struct drm_file *file; | |
387 | ||
388 | memset(&stats, 0, sizeof(stats)); | |
389 | ||
91c8a326 | 390 | mutex_lock(&dev_priv->drm.struct_mutex); |
15da9565 CW |
391 | if (dev_priv->kernel_context) |
392 | per_file_ctx_stats(0, dev_priv->kernel_context, &stats); | |
393 | ||
91c8a326 | 394 | list_for_each_entry(file, &dev_priv->drm.filelist, lhead) { |
15da9565 CW |
395 | struct drm_i915_file_private *fpriv = file->driver_priv; |
396 | idr_for_each(&fpriv->context_idr, per_file_ctx_stats, &stats); | |
397 | } | |
91c8a326 | 398 | mutex_unlock(&dev_priv->drm.struct_mutex); |
15da9565 CW |
399 | |
400 | print_file_stats(m, "[k]contexts", stats); | |
401 | } | |
402 | ||
ca191b13 BW |
403 | #define count_vmas(list, member) do { \ |
404 | list_for_each_entry(vma, list, member) { \ | |
ca1543be | 405 | size += i915_gem_obj_total_ggtt_size(vma->obj); \ |
ca191b13 BW |
406 | ++count; \ |
407 | if (vma->obj->map_and_fenceable) { \ | |
408 | mappable_size += i915_gem_obj_ggtt_size(vma->obj); \ | |
409 | ++mappable_count; \ | |
410 | } \ | |
411 | } \ | |
412 | } while (0) | |
413 | ||
414 | static int i915_gem_object_info(struct seq_file *m, void* data) | |
73aa808f | 415 | { |
9f25d007 | 416 | struct drm_info_node *node = m->private; |
73aa808f | 417 | struct drm_device *dev = node->minor->dev; |
72e96d64 JL |
418 | struct drm_i915_private *dev_priv = to_i915(dev); |
419 | struct i915_ggtt *ggtt = &dev_priv->ggtt; | |
b7abb714 | 420 | u32 count, mappable_count, purgeable_count; |
c44ef60e | 421 | u64 size, mappable_size, purgeable_size; |
be19b10d TU |
422 | unsigned long pin_mapped_count = 0, pin_mapped_purgeable_count = 0; |
423 | u64 pin_mapped_size = 0, pin_mapped_purgeable_size = 0; | |
6299f992 | 424 | struct drm_i915_gem_object *obj; |
2db8e9d6 | 425 | struct drm_file *file; |
ca191b13 | 426 | struct i915_vma *vma; |
73aa808f CW |
427 | int ret; |
428 | ||
429 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
430 | if (ret) | |
431 | return ret; | |
432 | ||
6299f992 CW |
433 | seq_printf(m, "%u objects, %zu bytes\n", |
434 | dev_priv->mm.object_count, | |
435 | dev_priv->mm.object_memory); | |
436 | ||
437 | size = count = mappable_size = mappable_count = 0; | |
35c20a60 | 438 | count_objects(&dev_priv->mm.bound_list, global_list); |
c44ef60e | 439 | seq_printf(m, "%u [%u] objects, %llu [%llu] bytes in gtt\n", |
6299f992 CW |
440 | count, mappable_count, size, mappable_size); |
441 | ||
442 | size = count = mappable_size = mappable_count = 0; | |
72e96d64 | 443 | count_vmas(&ggtt->base.active_list, vm_link); |
c44ef60e | 444 | seq_printf(m, " %u [%u] active objects, %llu [%llu] bytes\n", |
6299f992 CW |
445 | count, mappable_count, size, mappable_size); |
446 | ||
6299f992 | 447 | size = count = mappable_size = mappable_count = 0; |
72e96d64 | 448 | count_vmas(&ggtt->base.inactive_list, vm_link); |
c44ef60e | 449 | seq_printf(m, " %u [%u] inactive objects, %llu [%llu] bytes\n", |
6299f992 CW |
450 | count, mappable_count, size, mappable_size); |
451 | ||
b7abb714 | 452 | size = count = purgeable_size = purgeable_count = 0; |
35c20a60 | 453 | list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) { |
6c085a72 | 454 | size += obj->base.size, ++count; |
b7abb714 CW |
455 | if (obj->madv == I915_MADV_DONTNEED) |
456 | purgeable_size += obj->base.size, ++purgeable_count; | |
be19b10d TU |
457 | if (obj->mapping) { |
458 | pin_mapped_count++; | |
459 | pin_mapped_size += obj->base.size; | |
460 | if (obj->pages_pin_count == 0) { | |
461 | pin_mapped_purgeable_count++; | |
462 | pin_mapped_purgeable_size += obj->base.size; | |
463 | } | |
464 | } | |
b7abb714 | 465 | } |
c44ef60e | 466 | seq_printf(m, "%u unbound objects, %llu bytes\n", count, size); |
6c085a72 | 467 | |
6299f992 | 468 | size = count = mappable_size = mappable_count = 0; |
35c20a60 | 469 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) { |
6299f992 | 470 | if (obj->fault_mappable) { |
f343c5f6 | 471 | size += i915_gem_obj_ggtt_size(obj); |
6299f992 CW |
472 | ++count; |
473 | } | |
30154650 | 474 | if (obj->pin_display) { |
f343c5f6 | 475 | mappable_size += i915_gem_obj_ggtt_size(obj); |
6299f992 CW |
476 | ++mappable_count; |
477 | } | |
b7abb714 CW |
478 | if (obj->madv == I915_MADV_DONTNEED) { |
479 | purgeable_size += obj->base.size; | |
480 | ++purgeable_count; | |
481 | } | |
be19b10d TU |
482 | if (obj->mapping) { |
483 | pin_mapped_count++; | |
484 | pin_mapped_size += obj->base.size; | |
485 | if (obj->pages_pin_count == 0) { | |
486 | pin_mapped_purgeable_count++; | |
487 | pin_mapped_purgeable_size += obj->base.size; | |
488 | } | |
489 | } | |
6299f992 | 490 | } |
c44ef60e | 491 | seq_printf(m, "%u purgeable objects, %llu bytes\n", |
b7abb714 | 492 | purgeable_count, purgeable_size); |
c44ef60e | 493 | seq_printf(m, "%u pinned mappable objects, %llu bytes\n", |
6299f992 | 494 | mappable_count, mappable_size); |
c44ef60e | 495 | seq_printf(m, "%u fault mappable objects, %llu bytes\n", |
6299f992 | 496 | count, size); |
be19b10d TU |
497 | seq_printf(m, |
498 | "%lu [%lu] pin mapped objects, %llu [%llu] bytes [purgeable]\n", | |
499 | pin_mapped_count, pin_mapped_purgeable_count, | |
500 | pin_mapped_size, pin_mapped_purgeable_size); | |
6299f992 | 501 | |
c44ef60e | 502 | seq_printf(m, "%llu [%llu] gtt total\n", |
72e96d64 | 503 | ggtt->base.total, ggtt->mappable_end - ggtt->base.start); |
73aa808f | 504 | |
493018dc BV |
505 | seq_putc(m, '\n'); |
506 | print_batch_pool_stats(m, dev_priv); | |
1d2ac403 DV |
507 | mutex_unlock(&dev->struct_mutex); |
508 | ||
509 | mutex_lock(&dev->filelist_mutex); | |
15da9565 | 510 | print_context_stats(m, dev_priv); |
2db8e9d6 CW |
511 | list_for_each_entry_reverse(file, &dev->filelist, lhead) { |
512 | struct file_stats stats; | |
3ec2f427 | 513 | struct task_struct *task; |
2db8e9d6 CW |
514 | |
515 | memset(&stats, 0, sizeof(stats)); | |
6313c204 | 516 | stats.file_priv = file->driver_priv; |
5b5ffff0 | 517 | spin_lock(&file->table_lock); |
2db8e9d6 | 518 | idr_for_each(&file->object_idr, per_file_stats, &stats); |
5b5ffff0 | 519 | spin_unlock(&file->table_lock); |
3ec2f427 TH |
520 | /* |
521 | * Although we have a valid reference on file->pid, that does | |
522 | * not guarantee that the task_struct who called get_pid() is | |
523 | * still alive (e.g. get_pid(current) => fork() => exit()). | |
524 | * Therefore, we need to protect this ->comm access using RCU. | |
525 | */ | |
526 | rcu_read_lock(); | |
527 | task = pid_task(file->pid, PIDTYPE_PID); | |
493018dc | 528 | print_file_stats(m, task ? task->comm : "<unknown>", stats); |
3ec2f427 | 529 | rcu_read_unlock(); |
2db8e9d6 | 530 | } |
1d2ac403 | 531 | mutex_unlock(&dev->filelist_mutex); |
73aa808f CW |
532 | |
533 | return 0; | |
534 | } | |
535 | ||
aee56cff | 536 | static int i915_gem_gtt_info(struct seq_file *m, void *data) |
08c18323 | 537 | { |
9f25d007 | 538 | struct drm_info_node *node = m->private; |
08c18323 | 539 | struct drm_device *dev = node->minor->dev; |
1b50247a | 540 | uintptr_t list = (uintptr_t) node->info_ent->data; |
fac5e23e | 541 | struct drm_i915_private *dev_priv = to_i915(dev); |
08c18323 | 542 | struct drm_i915_gem_object *obj; |
c44ef60e | 543 | u64 total_obj_size, total_gtt_size; |
08c18323 CW |
544 | int count, ret; |
545 | ||
546 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
547 | if (ret) | |
548 | return ret; | |
549 | ||
550 | total_obj_size = total_gtt_size = count = 0; | |
35c20a60 | 551 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) { |
d7f46fc4 | 552 | if (list == PINNED_LIST && !i915_gem_obj_is_pinned(obj)) |
1b50247a CW |
553 | continue; |
554 | ||
267f0c90 | 555 | seq_puts(m, " "); |
08c18323 | 556 | describe_obj(m, obj); |
267f0c90 | 557 | seq_putc(m, '\n'); |
08c18323 | 558 | total_obj_size += obj->base.size; |
ca1543be | 559 | total_gtt_size += i915_gem_obj_total_ggtt_size(obj); |
08c18323 CW |
560 | count++; |
561 | } | |
562 | ||
563 | mutex_unlock(&dev->struct_mutex); | |
564 | ||
c44ef60e | 565 | seq_printf(m, "Total %d objects, %llu bytes, %llu GTT size\n", |
08c18323 CW |
566 | count, total_obj_size, total_gtt_size); |
567 | ||
568 | return 0; | |
569 | } | |
570 | ||
4e5359cd SF |
571 | static int i915_gem_pageflip_info(struct seq_file *m, void *data) |
572 | { | |
9f25d007 | 573 | struct drm_info_node *node = m->private; |
4e5359cd | 574 | struct drm_device *dev = node->minor->dev; |
fac5e23e | 575 | struct drm_i915_private *dev_priv = to_i915(dev); |
4e5359cd | 576 | struct intel_crtc *crtc; |
8a270ebf DV |
577 | int ret; |
578 | ||
579 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
580 | if (ret) | |
581 | return ret; | |
4e5359cd | 582 | |
d3fcc808 | 583 | for_each_intel_crtc(dev, crtc) { |
9db4a9c7 JB |
584 | const char pipe = pipe_name(crtc->pipe); |
585 | const char plane = plane_name(crtc->plane); | |
51cbaf01 | 586 | struct intel_flip_work *work; |
4e5359cd | 587 | |
5e2d7afc | 588 | spin_lock_irq(&dev->event_lock); |
5a21b665 DV |
589 | work = crtc->flip_work; |
590 | if (work == NULL) { | |
9db4a9c7 | 591 | seq_printf(m, "No flip due on pipe %c (plane %c)\n", |
4e5359cd SF |
592 | pipe, plane); |
593 | } else { | |
5a21b665 DV |
594 | u32 pending; |
595 | u32 addr; | |
596 | ||
597 | pending = atomic_read(&work->pending); | |
598 | if (pending) { | |
599 | seq_printf(m, "Flip ioctl preparing on pipe %c (plane %c)\n", | |
600 | pipe, plane); | |
601 | } else { | |
602 | seq_printf(m, "Flip pending (waiting for vsync) on pipe %c (plane %c)\n", | |
603 | pipe, plane); | |
604 | } | |
605 | if (work->flip_queued_req) { | |
606 | struct intel_engine_cs *engine = i915_gem_request_get_engine(work->flip_queued_req); | |
607 | ||
608 | seq_printf(m, "Flip queued on %s at seqno %x, next seqno %x [current breadcrumb %x], completed? %d\n", | |
609 | engine->name, | |
610 | i915_gem_request_get_seqno(work->flip_queued_req), | |
611 | dev_priv->next_seqno, | |
1b7744e7 | 612 | intel_engine_get_seqno(engine), |
f69a02c9 | 613 | i915_gem_request_completed(work->flip_queued_req)); |
5a21b665 DV |
614 | } else |
615 | seq_printf(m, "Flip not associated with any ring\n"); | |
616 | seq_printf(m, "Flip queued on frame %d, (was ready on frame %d), now %d\n", | |
617 | work->flip_queued_vblank, | |
618 | work->flip_ready_vblank, | |
619 | intel_crtc_get_vblank_counter(crtc)); | |
620 | seq_printf(m, "%d prepares\n", atomic_read(&work->pending)); | |
621 | ||
622 | if (INTEL_INFO(dev)->gen >= 4) | |
623 | addr = I915_HI_DISPBASE(I915_READ(DSPSURF(crtc->plane))); | |
624 | else | |
625 | addr = I915_READ(DSPADDR(crtc->plane)); | |
626 | seq_printf(m, "Current scanout address 0x%08x\n", addr); | |
627 | ||
628 | if (work->pending_flip_obj) { | |
629 | seq_printf(m, "New framebuffer address 0x%08lx\n", (long)work->gtt_offset); | |
630 | seq_printf(m, "MMIO update completed? %d\n", addr == work->gtt_offset); | |
4e5359cd SF |
631 | } |
632 | } | |
5e2d7afc | 633 | spin_unlock_irq(&dev->event_lock); |
4e5359cd SF |
634 | } |
635 | ||
8a270ebf DV |
636 | mutex_unlock(&dev->struct_mutex); |
637 | ||
4e5359cd SF |
638 | return 0; |
639 | } | |
640 | ||
493018dc BV |
641 | static int i915_gem_batch_pool_info(struct seq_file *m, void *data) |
642 | { | |
643 | struct drm_info_node *node = m->private; | |
644 | struct drm_device *dev = node->minor->dev; | |
fac5e23e | 645 | struct drm_i915_private *dev_priv = to_i915(dev); |
493018dc | 646 | struct drm_i915_gem_object *obj; |
e2f80391 | 647 | struct intel_engine_cs *engine; |
8d9d5744 | 648 | int total = 0; |
b4ac5afc | 649 | int ret, j; |
493018dc BV |
650 | |
651 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
652 | if (ret) | |
653 | return ret; | |
654 | ||
b4ac5afc | 655 | for_each_engine(engine, dev_priv) { |
e2f80391 | 656 | for (j = 0; j < ARRAY_SIZE(engine->batch_pool.cache_list); j++) { |
8d9d5744 CW |
657 | int count; |
658 | ||
659 | count = 0; | |
660 | list_for_each_entry(obj, | |
e2f80391 | 661 | &engine->batch_pool.cache_list[j], |
8d9d5744 CW |
662 | batch_pool_link) |
663 | count++; | |
664 | seq_printf(m, "%s cache[%d]: %d objects\n", | |
e2f80391 | 665 | engine->name, j, count); |
8d9d5744 CW |
666 | |
667 | list_for_each_entry(obj, | |
e2f80391 | 668 | &engine->batch_pool.cache_list[j], |
8d9d5744 CW |
669 | batch_pool_link) { |
670 | seq_puts(m, " "); | |
671 | describe_obj(m, obj); | |
672 | seq_putc(m, '\n'); | |
673 | } | |
674 | ||
675 | total += count; | |
06fbca71 | 676 | } |
493018dc BV |
677 | } |
678 | ||
8d9d5744 | 679 | seq_printf(m, "total: %d\n", total); |
493018dc BV |
680 | |
681 | mutex_unlock(&dev->struct_mutex); | |
682 | ||
683 | return 0; | |
684 | } | |
685 | ||
2017263e BG |
686 | static int i915_gem_request_info(struct seq_file *m, void *data) |
687 | { | |
9f25d007 | 688 | struct drm_info_node *node = m->private; |
2017263e | 689 | struct drm_device *dev = node->minor->dev; |
fac5e23e | 690 | struct drm_i915_private *dev_priv = to_i915(dev); |
e2f80391 | 691 | struct intel_engine_cs *engine; |
eed29a5b | 692 | struct drm_i915_gem_request *req; |
b4ac5afc | 693 | int ret, any; |
de227ef0 CW |
694 | |
695 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
696 | if (ret) | |
697 | return ret; | |
2017263e | 698 | |
2d1070b2 | 699 | any = 0; |
b4ac5afc | 700 | for_each_engine(engine, dev_priv) { |
2d1070b2 CW |
701 | int count; |
702 | ||
703 | count = 0; | |
efdf7c06 | 704 | list_for_each_entry(req, &engine->request_list, link) |
2d1070b2 CW |
705 | count++; |
706 | if (count == 0) | |
a2c7f6fd CW |
707 | continue; |
708 | ||
e2f80391 | 709 | seq_printf(m, "%s requests: %d\n", engine->name, count); |
efdf7c06 | 710 | list_for_each_entry(req, &engine->request_list, link) { |
2d1070b2 CW |
711 | struct task_struct *task; |
712 | ||
713 | rcu_read_lock(); | |
714 | task = NULL; | |
eed29a5b DV |
715 | if (req->pid) |
716 | task = pid_task(req->pid, PIDTYPE_PID); | |
2d1070b2 | 717 | seq_printf(m, " %x @ %d: %s [%d]\n", |
04769652 | 718 | req->fence.seqno, |
eed29a5b | 719 | (int) (jiffies - req->emitted_jiffies), |
2d1070b2 CW |
720 | task ? task->comm : "<unknown>", |
721 | task ? task->pid : -1); | |
722 | rcu_read_unlock(); | |
c2c347a9 | 723 | } |
2d1070b2 CW |
724 | |
725 | any++; | |
2017263e | 726 | } |
de227ef0 CW |
727 | mutex_unlock(&dev->struct_mutex); |
728 | ||
2d1070b2 | 729 | if (any == 0) |
267f0c90 | 730 | seq_puts(m, "No requests\n"); |
c2c347a9 | 731 | |
2017263e BG |
732 | return 0; |
733 | } | |
734 | ||
b2223497 | 735 | static void i915_ring_seqno_info(struct seq_file *m, |
0bc40be8 | 736 | struct intel_engine_cs *engine) |
b2223497 | 737 | { |
688e6c72 CW |
738 | struct intel_breadcrumbs *b = &engine->breadcrumbs; |
739 | struct rb_node *rb; | |
740 | ||
12471ba8 | 741 | seq_printf(m, "Current sequence (%s): %x\n", |
1b7744e7 | 742 | engine->name, intel_engine_get_seqno(engine)); |
688e6c72 CW |
743 | |
744 | spin_lock(&b->lock); | |
745 | for (rb = rb_first(&b->waiters); rb; rb = rb_next(rb)) { | |
746 | struct intel_wait *w = container_of(rb, typeof(*w), node); | |
747 | ||
748 | seq_printf(m, "Waiting (%s): %s [%d] on %x\n", | |
749 | engine->name, w->tsk->comm, w->tsk->pid, w->seqno); | |
750 | } | |
751 | spin_unlock(&b->lock); | |
b2223497 CW |
752 | } |
753 | ||
2017263e BG |
754 | static int i915_gem_seqno_info(struct seq_file *m, void *data) |
755 | { | |
9f25d007 | 756 | struct drm_info_node *node = m->private; |
2017263e | 757 | struct drm_device *dev = node->minor->dev; |
fac5e23e | 758 | struct drm_i915_private *dev_priv = to_i915(dev); |
e2f80391 | 759 | struct intel_engine_cs *engine; |
b4ac5afc | 760 | int ret; |
de227ef0 CW |
761 | |
762 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
763 | if (ret) | |
764 | return ret; | |
c8c8fb33 | 765 | intel_runtime_pm_get(dev_priv); |
2017263e | 766 | |
b4ac5afc | 767 | for_each_engine(engine, dev_priv) |
e2f80391 | 768 | i915_ring_seqno_info(m, engine); |
de227ef0 | 769 | |
c8c8fb33 | 770 | intel_runtime_pm_put(dev_priv); |
de227ef0 CW |
771 | mutex_unlock(&dev->struct_mutex); |
772 | ||
2017263e BG |
773 | return 0; |
774 | } | |
775 | ||
776 | ||
777 | static int i915_interrupt_info(struct seq_file *m, void *data) | |
778 | { | |
9f25d007 | 779 | struct drm_info_node *node = m->private; |
2017263e | 780 | struct drm_device *dev = node->minor->dev; |
fac5e23e | 781 | struct drm_i915_private *dev_priv = to_i915(dev); |
e2f80391 | 782 | struct intel_engine_cs *engine; |
9db4a9c7 | 783 | int ret, i, pipe; |
de227ef0 CW |
784 | |
785 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
786 | if (ret) | |
787 | return ret; | |
c8c8fb33 | 788 | intel_runtime_pm_get(dev_priv); |
2017263e | 789 | |
74e1ca8c | 790 | if (IS_CHERRYVIEW(dev)) { |
74e1ca8c VS |
791 | seq_printf(m, "Master Interrupt Control:\t%08x\n", |
792 | I915_READ(GEN8_MASTER_IRQ)); | |
793 | ||
794 | seq_printf(m, "Display IER:\t%08x\n", | |
795 | I915_READ(VLV_IER)); | |
796 | seq_printf(m, "Display IIR:\t%08x\n", | |
797 | I915_READ(VLV_IIR)); | |
798 | seq_printf(m, "Display IIR_RW:\t%08x\n", | |
799 | I915_READ(VLV_IIR_RW)); | |
800 | seq_printf(m, "Display IMR:\t%08x\n", | |
801 | I915_READ(VLV_IMR)); | |
055e393f | 802 | for_each_pipe(dev_priv, pipe) |
74e1ca8c VS |
803 | seq_printf(m, "Pipe %c stat:\t%08x\n", |
804 | pipe_name(pipe), | |
805 | I915_READ(PIPESTAT(pipe))); | |
806 | ||
807 | seq_printf(m, "Port hotplug:\t%08x\n", | |
808 | I915_READ(PORT_HOTPLUG_EN)); | |
809 | seq_printf(m, "DPFLIPSTAT:\t%08x\n", | |
810 | I915_READ(VLV_DPFLIPSTAT)); | |
811 | seq_printf(m, "DPINVGTT:\t%08x\n", | |
812 | I915_READ(DPINVGTT)); | |
813 | ||
814 | for (i = 0; i < 4; i++) { | |
815 | seq_printf(m, "GT Interrupt IMR %d:\t%08x\n", | |
816 | i, I915_READ(GEN8_GT_IMR(i))); | |
817 | seq_printf(m, "GT Interrupt IIR %d:\t%08x\n", | |
818 | i, I915_READ(GEN8_GT_IIR(i))); | |
819 | seq_printf(m, "GT Interrupt IER %d:\t%08x\n", | |
820 | i, I915_READ(GEN8_GT_IER(i))); | |
821 | } | |
822 | ||
823 | seq_printf(m, "PCU interrupt mask:\t%08x\n", | |
824 | I915_READ(GEN8_PCU_IMR)); | |
825 | seq_printf(m, "PCU interrupt identity:\t%08x\n", | |
826 | I915_READ(GEN8_PCU_IIR)); | |
827 | seq_printf(m, "PCU interrupt enable:\t%08x\n", | |
828 | I915_READ(GEN8_PCU_IER)); | |
829 | } else if (INTEL_INFO(dev)->gen >= 8) { | |
a123f157 BW |
830 | seq_printf(m, "Master Interrupt Control:\t%08x\n", |
831 | I915_READ(GEN8_MASTER_IRQ)); | |
832 | ||
833 | for (i = 0; i < 4; i++) { | |
834 | seq_printf(m, "GT Interrupt IMR %d:\t%08x\n", | |
835 | i, I915_READ(GEN8_GT_IMR(i))); | |
836 | seq_printf(m, "GT Interrupt IIR %d:\t%08x\n", | |
837 | i, I915_READ(GEN8_GT_IIR(i))); | |
838 | seq_printf(m, "GT Interrupt IER %d:\t%08x\n", | |
839 | i, I915_READ(GEN8_GT_IER(i))); | |
840 | } | |
841 | ||
055e393f | 842 | for_each_pipe(dev_priv, pipe) { |
e129649b ID |
843 | enum intel_display_power_domain power_domain; |
844 | ||
845 | power_domain = POWER_DOMAIN_PIPE(pipe); | |
846 | if (!intel_display_power_get_if_enabled(dev_priv, | |
847 | power_domain)) { | |
22c59960 PZ |
848 | seq_printf(m, "Pipe %c power disabled\n", |
849 | pipe_name(pipe)); | |
850 | continue; | |
851 | } | |
a123f157 | 852 | seq_printf(m, "Pipe %c IMR:\t%08x\n", |
07d27e20 DL |
853 | pipe_name(pipe), |
854 | I915_READ(GEN8_DE_PIPE_IMR(pipe))); | |
a123f157 | 855 | seq_printf(m, "Pipe %c IIR:\t%08x\n", |
07d27e20 DL |
856 | pipe_name(pipe), |
857 | I915_READ(GEN8_DE_PIPE_IIR(pipe))); | |
a123f157 | 858 | seq_printf(m, "Pipe %c IER:\t%08x\n", |
07d27e20 DL |
859 | pipe_name(pipe), |
860 | I915_READ(GEN8_DE_PIPE_IER(pipe))); | |
e129649b ID |
861 | |
862 | intel_display_power_put(dev_priv, power_domain); | |
a123f157 BW |
863 | } |
864 | ||
865 | seq_printf(m, "Display Engine port interrupt mask:\t%08x\n", | |
866 | I915_READ(GEN8_DE_PORT_IMR)); | |
867 | seq_printf(m, "Display Engine port interrupt identity:\t%08x\n", | |
868 | I915_READ(GEN8_DE_PORT_IIR)); | |
869 | seq_printf(m, "Display Engine port interrupt enable:\t%08x\n", | |
870 | I915_READ(GEN8_DE_PORT_IER)); | |
871 | ||
872 | seq_printf(m, "Display Engine misc interrupt mask:\t%08x\n", | |
873 | I915_READ(GEN8_DE_MISC_IMR)); | |
874 | seq_printf(m, "Display Engine misc interrupt identity:\t%08x\n", | |
875 | I915_READ(GEN8_DE_MISC_IIR)); | |
876 | seq_printf(m, "Display Engine misc interrupt enable:\t%08x\n", | |
877 | I915_READ(GEN8_DE_MISC_IER)); | |
878 | ||
879 | seq_printf(m, "PCU interrupt mask:\t%08x\n", | |
880 | I915_READ(GEN8_PCU_IMR)); | |
881 | seq_printf(m, "PCU interrupt identity:\t%08x\n", | |
882 | I915_READ(GEN8_PCU_IIR)); | |
883 | seq_printf(m, "PCU interrupt enable:\t%08x\n", | |
884 | I915_READ(GEN8_PCU_IER)); | |
885 | } else if (IS_VALLEYVIEW(dev)) { | |
7e231dbe JB |
886 | seq_printf(m, "Display IER:\t%08x\n", |
887 | I915_READ(VLV_IER)); | |
888 | seq_printf(m, "Display IIR:\t%08x\n", | |
889 | I915_READ(VLV_IIR)); | |
890 | seq_printf(m, "Display IIR_RW:\t%08x\n", | |
891 | I915_READ(VLV_IIR_RW)); | |
892 | seq_printf(m, "Display IMR:\t%08x\n", | |
893 | I915_READ(VLV_IMR)); | |
055e393f | 894 | for_each_pipe(dev_priv, pipe) |
7e231dbe JB |
895 | seq_printf(m, "Pipe %c stat:\t%08x\n", |
896 | pipe_name(pipe), | |
897 | I915_READ(PIPESTAT(pipe))); | |
898 | ||
899 | seq_printf(m, "Master IER:\t%08x\n", | |
900 | I915_READ(VLV_MASTER_IER)); | |
901 | ||
902 | seq_printf(m, "Render IER:\t%08x\n", | |
903 | I915_READ(GTIER)); | |
904 | seq_printf(m, "Render IIR:\t%08x\n", | |
905 | I915_READ(GTIIR)); | |
906 | seq_printf(m, "Render IMR:\t%08x\n", | |
907 | I915_READ(GTIMR)); | |
908 | ||
909 | seq_printf(m, "PM IER:\t\t%08x\n", | |
910 | I915_READ(GEN6_PMIER)); | |
911 | seq_printf(m, "PM IIR:\t\t%08x\n", | |
912 | I915_READ(GEN6_PMIIR)); | |
913 | seq_printf(m, "PM IMR:\t\t%08x\n", | |
914 | I915_READ(GEN6_PMIMR)); | |
915 | ||
916 | seq_printf(m, "Port hotplug:\t%08x\n", | |
917 | I915_READ(PORT_HOTPLUG_EN)); | |
918 | seq_printf(m, "DPFLIPSTAT:\t%08x\n", | |
919 | I915_READ(VLV_DPFLIPSTAT)); | |
920 | seq_printf(m, "DPINVGTT:\t%08x\n", | |
921 | I915_READ(DPINVGTT)); | |
922 | ||
923 | } else if (!HAS_PCH_SPLIT(dev)) { | |
5f6a1695 ZW |
924 | seq_printf(m, "Interrupt enable: %08x\n", |
925 | I915_READ(IER)); | |
926 | seq_printf(m, "Interrupt identity: %08x\n", | |
927 | I915_READ(IIR)); | |
928 | seq_printf(m, "Interrupt mask: %08x\n", | |
929 | I915_READ(IMR)); | |
055e393f | 930 | for_each_pipe(dev_priv, pipe) |
9db4a9c7 JB |
931 | seq_printf(m, "Pipe %c stat: %08x\n", |
932 | pipe_name(pipe), | |
933 | I915_READ(PIPESTAT(pipe))); | |
5f6a1695 ZW |
934 | } else { |
935 | seq_printf(m, "North Display Interrupt enable: %08x\n", | |
936 | I915_READ(DEIER)); | |
937 | seq_printf(m, "North Display Interrupt identity: %08x\n", | |
938 | I915_READ(DEIIR)); | |
939 | seq_printf(m, "North Display Interrupt mask: %08x\n", | |
940 | I915_READ(DEIMR)); | |
941 | seq_printf(m, "South Display Interrupt enable: %08x\n", | |
942 | I915_READ(SDEIER)); | |
943 | seq_printf(m, "South Display Interrupt identity: %08x\n", | |
944 | I915_READ(SDEIIR)); | |
945 | seq_printf(m, "South Display Interrupt mask: %08x\n", | |
946 | I915_READ(SDEIMR)); | |
947 | seq_printf(m, "Graphics Interrupt enable: %08x\n", | |
948 | I915_READ(GTIER)); | |
949 | seq_printf(m, "Graphics Interrupt identity: %08x\n", | |
950 | I915_READ(GTIIR)); | |
951 | seq_printf(m, "Graphics Interrupt mask: %08x\n", | |
952 | I915_READ(GTIMR)); | |
953 | } | |
b4ac5afc | 954 | for_each_engine(engine, dev_priv) { |
a123f157 | 955 | if (INTEL_INFO(dev)->gen >= 6) { |
a2c7f6fd CW |
956 | seq_printf(m, |
957 | "Graphics Interrupt mask (%s): %08x\n", | |
e2f80391 | 958 | engine->name, I915_READ_IMR(engine)); |
9862e600 | 959 | } |
e2f80391 | 960 | i915_ring_seqno_info(m, engine); |
9862e600 | 961 | } |
c8c8fb33 | 962 | intel_runtime_pm_put(dev_priv); |
de227ef0 CW |
963 | mutex_unlock(&dev->struct_mutex); |
964 | ||
2017263e BG |
965 | return 0; |
966 | } | |
967 | ||
a6172a80 CW |
968 | static int i915_gem_fence_regs_info(struct seq_file *m, void *data) |
969 | { | |
9f25d007 | 970 | struct drm_info_node *node = m->private; |
a6172a80 | 971 | struct drm_device *dev = node->minor->dev; |
fac5e23e | 972 | struct drm_i915_private *dev_priv = to_i915(dev); |
de227ef0 CW |
973 | int i, ret; |
974 | ||
975 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
976 | if (ret) | |
977 | return ret; | |
a6172a80 | 978 | |
a6172a80 CW |
979 | seq_printf(m, "Total fences = %d\n", dev_priv->num_fence_regs); |
980 | for (i = 0; i < dev_priv->num_fence_regs; i++) { | |
05394f39 | 981 | struct drm_i915_gem_object *obj = dev_priv->fence_regs[i].obj; |
a6172a80 | 982 | |
6c085a72 CW |
983 | seq_printf(m, "Fence %d, pin count = %d, object = ", |
984 | i, dev_priv->fence_regs[i].pin_count); | |
c2c347a9 | 985 | if (obj == NULL) |
267f0c90 | 986 | seq_puts(m, "unused"); |
c2c347a9 | 987 | else |
05394f39 | 988 | describe_obj(m, obj); |
267f0c90 | 989 | seq_putc(m, '\n'); |
a6172a80 CW |
990 | } |
991 | ||
05394f39 | 992 | mutex_unlock(&dev->struct_mutex); |
a6172a80 CW |
993 | return 0; |
994 | } | |
995 | ||
2017263e BG |
996 | static int i915_hws_info(struct seq_file *m, void *data) |
997 | { | |
9f25d007 | 998 | struct drm_info_node *node = m->private; |
2017263e | 999 | struct drm_device *dev = node->minor->dev; |
fac5e23e | 1000 | struct drm_i915_private *dev_priv = to_i915(dev); |
e2f80391 | 1001 | struct intel_engine_cs *engine; |
1a240d4d | 1002 | const u32 *hws; |
4066c0ae CW |
1003 | int i; |
1004 | ||
4a570db5 | 1005 | engine = &dev_priv->engine[(uintptr_t)node->info_ent->data]; |
e2f80391 | 1006 | hws = engine->status_page.page_addr; |
2017263e BG |
1007 | if (hws == NULL) |
1008 | return 0; | |
1009 | ||
1010 | for (i = 0; i < 4096 / sizeof(u32) / 4; i += 4) { | |
1011 | seq_printf(m, "0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x\n", | |
1012 | i * 4, | |
1013 | hws[i], hws[i + 1], hws[i + 2], hws[i + 3]); | |
1014 | } | |
1015 | return 0; | |
1016 | } | |
1017 | ||
d5442303 DV |
1018 | static ssize_t |
1019 | i915_error_state_write(struct file *filp, | |
1020 | const char __user *ubuf, | |
1021 | size_t cnt, | |
1022 | loff_t *ppos) | |
1023 | { | |
edc3d884 | 1024 | struct i915_error_state_file_priv *error_priv = filp->private_data; |
d5442303 | 1025 | struct drm_device *dev = error_priv->dev; |
22bcfc6a | 1026 | int ret; |
d5442303 DV |
1027 | |
1028 | DRM_DEBUG_DRIVER("Resetting error state\n"); | |
1029 | ||
22bcfc6a DV |
1030 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
1031 | if (ret) | |
1032 | return ret; | |
1033 | ||
d5442303 DV |
1034 | i915_destroy_error_state(dev); |
1035 | mutex_unlock(&dev->struct_mutex); | |
1036 | ||
1037 | return cnt; | |
1038 | } | |
1039 | ||
1040 | static int i915_error_state_open(struct inode *inode, struct file *file) | |
1041 | { | |
1042 | struct drm_device *dev = inode->i_private; | |
d5442303 | 1043 | struct i915_error_state_file_priv *error_priv; |
d5442303 DV |
1044 | |
1045 | error_priv = kzalloc(sizeof(*error_priv), GFP_KERNEL); | |
1046 | if (!error_priv) | |
1047 | return -ENOMEM; | |
1048 | ||
1049 | error_priv->dev = dev; | |
1050 | ||
95d5bfb3 | 1051 | i915_error_state_get(dev, error_priv); |
d5442303 | 1052 | |
edc3d884 MK |
1053 | file->private_data = error_priv; |
1054 | ||
1055 | return 0; | |
d5442303 DV |
1056 | } |
1057 | ||
1058 | static int i915_error_state_release(struct inode *inode, struct file *file) | |
1059 | { | |
edc3d884 | 1060 | struct i915_error_state_file_priv *error_priv = file->private_data; |
d5442303 | 1061 | |
95d5bfb3 | 1062 | i915_error_state_put(error_priv); |
d5442303 DV |
1063 | kfree(error_priv); |
1064 | ||
edc3d884 MK |
1065 | return 0; |
1066 | } | |
1067 | ||
4dc955f7 MK |
1068 | static ssize_t i915_error_state_read(struct file *file, char __user *userbuf, |
1069 | size_t count, loff_t *pos) | |
1070 | { | |
1071 | struct i915_error_state_file_priv *error_priv = file->private_data; | |
1072 | struct drm_i915_error_state_buf error_str; | |
1073 | loff_t tmp_pos = 0; | |
1074 | ssize_t ret_count = 0; | |
1075 | int ret; | |
1076 | ||
0a4cd7c8 | 1077 | ret = i915_error_state_buf_init(&error_str, to_i915(error_priv->dev), count, *pos); |
4dc955f7 MK |
1078 | if (ret) |
1079 | return ret; | |
edc3d884 | 1080 | |
fc16b48b | 1081 | ret = i915_error_state_to_str(&error_str, error_priv); |
edc3d884 MK |
1082 | if (ret) |
1083 | goto out; | |
1084 | ||
edc3d884 MK |
1085 | ret_count = simple_read_from_buffer(userbuf, count, &tmp_pos, |
1086 | error_str.buf, | |
1087 | error_str.bytes); | |
1088 | ||
1089 | if (ret_count < 0) | |
1090 | ret = ret_count; | |
1091 | else | |
1092 | *pos = error_str.start + ret_count; | |
1093 | out: | |
4dc955f7 | 1094 | i915_error_state_buf_release(&error_str); |
edc3d884 | 1095 | return ret ?: ret_count; |
d5442303 DV |
1096 | } |
1097 | ||
1098 | static const struct file_operations i915_error_state_fops = { | |
1099 | .owner = THIS_MODULE, | |
1100 | .open = i915_error_state_open, | |
edc3d884 | 1101 | .read = i915_error_state_read, |
d5442303 DV |
1102 | .write = i915_error_state_write, |
1103 | .llseek = default_llseek, | |
1104 | .release = i915_error_state_release, | |
1105 | }; | |
1106 | ||
647416f9 KC |
1107 | static int |
1108 | i915_next_seqno_get(void *data, u64 *val) | |
40633219 | 1109 | { |
647416f9 | 1110 | struct drm_device *dev = data; |
fac5e23e | 1111 | struct drm_i915_private *dev_priv = to_i915(dev); |
40633219 MK |
1112 | int ret; |
1113 | ||
1114 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
1115 | if (ret) | |
1116 | return ret; | |
1117 | ||
647416f9 | 1118 | *val = dev_priv->next_seqno; |
40633219 MK |
1119 | mutex_unlock(&dev->struct_mutex); |
1120 | ||
647416f9 | 1121 | return 0; |
40633219 MK |
1122 | } |
1123 | ||
647416f9 KC |
1124 | static int |
1125 | i915_next_seqno_set(void *data, u64 val) | |
1126 | { | |
1127 | struct drm_device *dev = data; | |
40633219 MK |
1128 | int ret; |
1129 | ||
40633219 MK |
1130 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
1131 | if (ret) | |
1132 | return ret; | |
1133 | ||
e94fbaa8 | 1134 | ret = i915_gem_set_seqno(dev, val); |
40633219 MK |
1135 | mutex_unlock(&dev->struct_mutex); |
1136 | ||
647416f9 | 1137 | return ret; |
40633219 MK |
1138 | } |
1139 | ||
647416f9 KC |
1140 | DEFINE_SIMPLE_ATTRIBUTE(i915_next_seqno_fops, |
1141 | i915_next_seqno_get, i915_next_seqno_set, | |
3a3b4f98 | 1142 | "0x%llx\n"); |
40633219 | 1143 | |
adb4bd12 | 1144 | static int i915_frequency_info(struct seq_file *m, void *unused) |
f97108d1 | 1145 | { |
9f25d007 | 1146 | struct drm_info_node *node = m->private; |
f97108d1 | 1147 | struct drm_device *dev = node->minor->dev; |
fac5e23e | 1148 | struct drm_i915_private *dev_priv = to_i915(dev); |
c8c8fb33 PZ |
1149 | int ret = 0; |
1150 | ||
1151 | intel_runtime_pm_get(dev_priv); | |
3b8d8d91 JB |
1152 | |
1153 | if (IS_GEN5(dev)) { | |
1154 | u16 rgvswctl = I915_READ16(MEMSWCTL); | |
1155 | u16 rgvstat = I915_READ16(MEMSTAT_ILK); | |
1156 | ||
1157 | seq_printf(m, "Requested P-state: %d\n", (rgvswctl >> 8) & 0xf); | |
1158 | seq_printf(m, "Requested VID: %d\n", rgvswctl & 0x3f); | |
1159 | seq_printf(m, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK) >> | |
1160 | MEMSTAT_VID_SHIFT); | |
1161 | seq_printf(m, "Current P-state: %d\n", | |
1162 | (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT); | |
666a4537 WB |
1163 | } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
1164 | u32 freq_sts; | |
1165 | ||
1166 | mutex_lock(&dev_priv->rps.hw_lock); | |
1167 | freq_sts = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS); | |
1168 | seq_printf(m, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts); | |
1169 | seq_printf(m, "DDR freq: %d MHz\n", dev_priv->mem_freq); | |
1170 | ||
1171 | seq_printf(m, "actual GPU freq: %d MHz\n", | |
1172 | intel_gpu_freq(dev_priv, (freq_sts >> 8) & 0xff)); | |
1173 | ||
1174 | seq_printf(m, "current GPU freq: %d MHz\n", | |
1175 | intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq)); | |
1176 | ||
1177 | seq_printf(m, "max GPU freq: %d MHz\n", | |
1178 | intel_gpu_freq(dev_priv, dev_priv->rps.max_freq)); | |
1179 | ||
1180 | seq_printf(m, "min GPU freq: %d MHz\n", | |
1181 | intel_gpu_freq(dev_priv, dev_priv->rps.min_freq)); | |
1182 | ||
1183 | seq_printf(m, "idle GPU freq: %d MHz\n", | |
1184 | intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq)); | |
1185 | ||
1186 | seq_printf(m, | |
1187 | "efficient (RPe) frequency: %d MHz\n", | |
1188 | intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq)); | |
1189 | mutex_unlock(&dev_priv->rps.hw_lock); | |
1190 | } else if (INTEL_INFO(dev)->gen >= 6) { | |
35040562 BP |
1191 | u32 rp_state_limits; |
1192 | u32 gt_perf_status; | |
1193 | u32 rp_state_cap; | |
0d8f9491 | 1194 | u32 rpmodectl, rpinclimit, rpdeclimit; |
8e8c06cd | 1195 | u32 rpstat, cagf, reqf; |
ccab5c82 JB |
1196 | u32 rpupei, rpcurup, rpprevup; |
1197 | u32 rpdownei, rpcurdown, rpprevdown; | |
9dd3c605 | 1198 | u32 pm_ier, pm_imr, pm_isr, pm_iir, pm_mask; |
3b8d8d91 JB |
1199 | int max_freq; |
1200 | ||
35040562 BP |
1201 | rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS); |
1202 | if (IS_BROXTON(dev)) { | |
1203 | rp_state_cap = I915_READ(BXT_RP_STATE_CAP); | |
1204 | gt_perf_status = I915_READ(BXT_GT_PERF_STATUS); | |
1205 | } else { | |
1206 | rp_state_cap = I915_READ(GEN6_RP_STATE_CAP); | |
1207 | gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS); | |
1208 | } | |
1209 | ||
3b8d8d91 | 1210 | /* RPSTAT1 is in the GT power well */ |
d1ebd816 BW |
1211 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
1212 | if (ret) | |
c8c8fb33 | 1213 | goto out; |
d1ebd816 | 1214 | |
59bad947 | 1215 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); |
3b8d8d91 | 1216 | |
8e8c06cd | 1217 | reqf = I915_READ(GEN6_RPNSWREQ); |
60260a5b AG |
1218 | if (IS_GEN9(dev)) |
1219 | reqf >>= 23; | |
1220 | else { | |
1221 | reqf &= ~GEN6_TURBO_DISABLE; | |
1222 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) | |
1223 | reqf >>= 24; | |
1224 | else | |
1225 | reqf >>= 25; | |
1226 | } | |
7c59a9c1 | 1227 | reqf = intel_gpu_freq(dev_priv, reqf); |
8e8c06cd | 1228 | |
0d8f9491 CW |
1229 | rpmodectl = I915_READ(GEN6_RP_CONTROL); |
1230 | rpinclimit = I915_READ(GEN6_RP_UP_THRESHOLD); | |
1231 | rpdeclimit = I915_READ(GEN6_RP_DOWN_THRESHOLD); | |
1232 | ||
ccab5c82 | 1233 | rpstat = I915_READ(GEN6_RPSTAT1); |
d6cda9c7 AG |
1234 | rpupei = I915_READ(GEN6_RP_CUR_UP_EI) & GEN6_CURICONT_MASK; |
1235 | rpcurup = I915_READ(GEN6_RP_CUR_UP) & GEN6_CURBSYTAVG_MASK; | |
1236 | rpprevup = I915_READ(GEN6_RP_PREV_UP) & GEN6_CURBSYTAVG_MASK; | |
1237 | rpdownei = I915_READ(GEN6_RP_CUR_DOWN_EI) & GEN6_CURIAVG_MASK; | |
1238 | rpcurdown = I915_READ(GEN6_RP_CUR_DOWN) & GEN6_CURBSYTAVG_MASK; | |
1239 | rpprevdown = I915_READ(GEN6_RP_PREV_DOWN) & GEN6_CURBSYTAVG_MASK; | |
60260a5b AG |
1240 | if (IS_GEN9(dev)) |
1241 | cagf = (rpstat & GEN9_CAGF_MASK) >> GEN9_CAGF_SHIFT; | |
1242 | else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) | |
f82855d3 BW |
1243 | cagf = (rpstat & HSW_CAGF_MASK) >> HSW_CAGF_SHIFT; |
1244 | else | |
1245 | cagf = (rpstat & GEN6_CAGF_MASK) >> GEN6_CAGF_SHIFT; | |
7c59a9c1 | 1246 | cagf = intel_gpu_freq(dev_priv, cagf); |
ccab5c82 | 1247 | |
59bad947 | 1248 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); |
d1ebd816 BW |
1249 | mutex_unlock(&dev->struct_mutex); |
1250 | ||
9dd3c605 PZ |
1251 | if (IS_GEN6(dev) || IS_GEN7(dev)) { |
1252 | pm_ier = I915_READ(GEN6_PMIER); | |
1253 | pm_imr = I915_READ(GEN6_PMIMR); | |
1254 | pm_isr = I915_READ(GEN6_PMISR); | |
1255 | pm_iir = I915_READ(GEN6_PMIIR); | |
1256 | pm_mask = I915_READ(GEN6_PMINTRMSK); | |
1257 | } else { | |
1258 | pm_ier = I915_READ(GEN8_GT_IER(2)); | |
1259 | pm_imr = I915_READ(GEN8_GT_IMR(2)); | |
1260 | pm_isr = I915_READ(GEN8_GT_ISR(2)); | |
1261 | pm_iir = I915_READ(GEN8_GT_IIR(2)); | |
1262 | pm_mask = I915_READ(GEN6_PMINTRMSK); | |
1263 | } | |
0d8f9491 | 1264 | seq_printf(m, "PM IER=0x%08x IMR=0x%08x ISR=0x%08x IIR=0x%08x, MASK=0x%08x\n", |
9dd3c605 | 1265 | pm_ier, pm_imr, pm_isr, pm_iir, pm_mask); |
1800ad25 | 1266 | seq_printf(m, "pm_intr_keep: 0x%08x\n", dev_priv->rps.pm_intr_keep); |
3b8d8d91 | 1267 | seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status); |
3b8d8d91 | 1268 | seq_printf(m, "Render p-state ratio: %d\n", |
60260a5b | 1269 | (gt_perf_status & (IS_GEN9(dev) ? 0x1ff00 : 0xff00)) >> 8); |
3b8d8d91 JB |
1270 | seq_printf(m, "Render p-state VID: %d\n", |
1271 | gt_perf_status & 0xff); | |
1272 | seq_printf(m, "Render p-state limit: %d\n", | |
1273 | rp_state_limits & 0xff); | |
0d8f9491 CW |
1274 | seq_printf(m, "RPSTAT1: 0x%08x\n", rpstat); |
1275 | seq_printf(m, "RPMODECTL: 0x%08x\n", rpmodectl); | |
1276 | seq_printf(m, "RPINCLIMIT: 0x%08x\n", rpinclimit); | |
1277 | seq_printf(m, "RPDECLIMIT: 0x%08x\n", rpdeclimit); | |
8e8c06cd | 1278 | seq_printf(m, "RPNSWREQ: %dMHz\n", reqf); |
f82855d3 | 1279 | seq_printf(m, "CAGF: %dMHz\n", cagf); |
d6cda9c7 AG |
1280 | seq_printf(m, "RP CUR UP EI: %d (%dus)\n", |
1281 | rpupei, GT_PM_INTERVAL_TO_US(dev_priv, rpupei)); | |
1282 | seq_printf(m, "RP CUR UP: %d (%dus)\n", | |
1283 | rpcurup, GT_PM_INTERVAL_TO_US(dev_priv, rpcurup)); | |
1284 | seq_printf(m, "RP PREV UP: %d (%dus)\n", | |
1285 | rpprevup, GT_PM_INTERVAL_TO_US(dev_priv, rpprevup)); | |
d86ed34a CW |
1286 | seq_printf(m, "Up threshold: %d%%\n", |
1287 | dev_priv->rps.up_threshold); | |
1288 | ||
d6cda9c7 AG |
1289 | seq_printf(m, "RP CUR DOWN EI: %d (%dus)\n", |
1290 | rpdownei, GT_PM_INTERVAL_TO_US(dev_priv, rpdownei)); | |
1291 | seq_printf(m, "RP CUR DOWN: %d (%dus)\n", | |
1292 | rpcurdown, GT_PM_INTERVAL_TO_US(dev_priv, rpcurdown)); | |
1293 | seq_printf(m, "RP PREV DOWN: %d (%dus)\n", | |
1294 | rpprevdown, GT_PM_INTERVAL_TO_US(dev_priv, rpprevdown)); | |
d86ed34a CW |
1295 | seq_printf(m, "Down threshold: %d%%\n", |
1296 | dev_priv->rps.down_threshold); | |
3b8d8d91 | 1297 | |
35040562 BP |
1298 | max_freq = (IS_BROXTON(dev) ? rp_state_cap >> 0 : |
1299 | rp_state_cap >> 16) & 0xff; | |
ef11bdb3 RV |
1300 | max_freq *= (IS_SKYLAKE(dev) || IS_KABYLAKE(dev) ? |
1301 | GEN9_FREQ_SCALER : 1); | |
3b8d8d91 | 1302 | seq_printf(m, "Lowest (RPN) frequency: %dMHz\n", |
7c59a9c1 | 1303 | intel_gpu_freq(dev_priv, max_freq)); |
3b8d8d91 JB |
1304 | |
1305 | max_freq = (rp_state_cap & 0xff00) >> 8; | |
ef11bdb3 RV |
1306 | max_freq *= (IS_SKYLAKE(dev) || IS_KABYLAKE(dev) ? |
1307 | GEN9_FREQ_SCALER : 1); | |
3b8d8d91 | 1308 | seq_printf(m, "Nominal (RP1) frequency: %dMHz\n", |
7c59a9c1 | 1309 | intel_gpu_freq(dev_priv, max_freq)); |
3b8d8d91 | 1310 | |
35040562 BP |
1311 | max_freq = (IS_BROXTON(dev) ? rp_state_cap >> 16 : |
1312 | rp_state_cap >> 0) & 0xff; | |
ef11bdb3 RV |
1313 | max_freq *= (IS_SKYLAKE(dev) || IS_KABYLAKE(dev) ? |
1314 | GEN9_FREQ_SCALER : 1); | |
3b8d8d91 | 1315 | seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n", |
7c59a9c1 | 1316 | intel_gpu_freq(dev_priv, max_freq)); |
31c77388 | 1317 | seq_printf(m, "Max overclocked frequency: %dMHz\n", |
7c59a9c1 | 1318 | intel_gpu_freq(dev_priv, dev_priv->rps.max_freq)); |
aed242ff | 1319 | |
d86ed34a CW |
1320 | seq_printf(m, "Current freq: %d MHz\n", |
1321 | intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq)); | |
1322 | seq_printf(m, "Actual freq: %d MHz\n", cagf); | |
aed242ff CW |
1323 | seq_printf(m, "Idle freq: %d MHz\n", |
1324 | intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq)); | |
d86ed34a CW |
1325 | seq_printf(m, "Min freq: %d MHz\n", |
1326 | intel_gpu_freq(dev_priv, dev_priv->rps.min_freq)); | |
29ecd78d CW |
1327 | seq_printf(m, "Boost freq: %d MHz\n", |
1328 | intel_gpu_freq(dev_priv, dev_priv->rps.boost_freq)); | |
d86ed34a CW |
1329 | seq_printf(m, "Max freq: %d MHz\n", |
1330 | intel_gpu_freq(dev_priv, dev_priv->rps.max_freq)); | |
1331 | seq_printf(m, | |
1332 | "efficient (RPe) frequency: %d MHz\n", | |
1333 | intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq)); | |
3b8d8d91 | 1334 | } else { |
267f0c90 | 1335 | seq_puts(m, "no P-state info available\n"); |
3b8d8d91 | 1336 | } |
f97108d1 | 1337 | |
1170f28c MK |
1338 | seq_printf(m, "Current CD clock frequency: %d kHz\n", dev_priv->cdclk_freq); |
1339 | seq_printf(m, "Max CD clock frequency: %d kHz\n", dev_priv->max_cdclk_freq); | |
1340 | seq_printf(m, "Max pixel clock frequency: %d kHz\n", dev_priv->max_dotclk_freq); | |
1341 | ||
c8c8fb33 PZ |
1342 | out: |
1343 | intel_runtime_pm_put(dev_priv); | |
1344 | return ret; | |
f97108d1 JB |
1345 | } |
1346 | ||
f654449a CW |
1347 | static int i915_hangcheck_info(struct seq_file *m, void *unused) |
1348 | { | |
1349 | struct drm_info_node *node = m->private; | |
ebbc7546 | 1350 | struct drm_device *dev = node->minor->dev; |
fac5e23e | 1351 | struct drm_i915_private *dev_priv = to_i915(dev); |
e2f80391 | 1352 | struct intel_engine_cs *engine; |
666796da TU |
1353 | u64 acthd[I915_NUM_ENGINES]; |
1354 | u32 seqno[I915_NUM_ENGINES]; | |
61642ff0 | 1355 | u32 instdone[I915_NUM_INSTDONE_REG]; |
c3232b18 DG |
1356 | enum intel_engine_id id; |
1357 | int j; | |
f654449a CW |
1358 | |
1359 | if (!i915.enable_hangcheck) { | |
1360 | seq_printf(m, "Hangcheck disabled\n"); | |
1361 | return 0; | |
1362 | } | |
1363 | ||
ebbc7546 MK |
1364 | intel_runtime_pm_get(dev_priv); |
1365 | ||
c3232b18 | 1366 | for_each_engine_id(engine, dev_priv, id) { |
7e37f889 | 1367 | acthd[id] = intel_engine_get_active_head(engine); |
1b7744e7 | 1368 | seqno[id] = intel_engine_get_seqno(engine); |
ebbc7546 MK |
1369 | } |
1370 | ||
c033666a | 1371 | i915_get_extra_instdone(dev_priv, instdone); |
61642ff0 | 1372 | |
ebbc7546 MK |
1373 | intel_runtime_pm_put(dev_priv); |
1374 | ||
f654449a CW |
1375 | if (delayed_work_pending(&dev_priv->gpu_error.hangcheck_work)) { |
1376 | seq_printf(m, "Hangcheck active, fires in %dms\n", | |
1377 | jiffies_to_msecs(dev_priv->gpu_error.hangcheck_work.timer.expires - | |
1378 | jiffies)); | |
1379 | } else | |
1380 | seq_printf(m, "Hangcheck inactive\n"); | |
1381 | ||
c3232b18 | 1382 | for_each_engine_id(engine, dev_priv, id) { |
e2f80391 | 1383 | seq_printf(m, "%s:\n", engine->name); |
14fd0d6d CW |
1384 | seq_printf(m, "\tseqno = %x [current %x, last %x]\n", |
1385 | engine->hangcheck.seqno, | |
1386 | seqno[id], | |
1387 | engine->last_submitted_seqno); | |
83348ba8 CW |
1388 | seq_printf(m, "\twaiters? %s, fake irq active? %s\n", |
1389 | yesno(intel_engine_has_waiter(engine)), | |
1390 | yesno(test_bit(engine->id, | |
1391 | &dev_priv->gpu_error.missed_irq_rings))); | |
f654449a | 1392 | seq_printf(m, "\tACTHD = 0x%08llx [current 0x%08llx]\n", |
e2f80391 | 1393 | (long long)engine->hangcheck.acthd, |
c3232b18 | 1394 | (long long)acthd[id]); |
e2f80391 TU |
1395 | seq_printf(m, "\tscore = %d\n", engine->hangcheck.score); |
1396 | seq_printf(m, "\taction = %d\n", engine->hangcheck.action); | |
61642ff0 | 1397 | |
e2f80391 | 1398 | if (engine->id == RCS) { |
61642ff0 MK |
1399 | seq_puts(m, "\tinstdone read ="); |
1400 | ||
1401 | for (j = 0; j < I915_NUM_INSTDONE_REG; j++) | |
1402 | seq_printf(m, " 0x%08x", instdone[j]); | |
1403 | ||
1404 | seq_puts(m, "\n\tinstdone accu ="); | |
1405 | ||
1406 | for (j = 0; j < I915_NUM_INSTDONE_REG; j++) | |
1407 | seq_printf(m, " 0x%08x", | |
e2f80391 | 1408 | engine->hangcheck.instdone[j]); |
61642ff0 MK |
1409 | |
1410 | seq_puts(m, "\n"); | |
1411 | } | |
f654449a CW |
1412 | } |
1413 | ||
1414 | return 0; | |
1415 | } | |
1416 | ||
4d85529d | 1417 | static int ironlake_drpc_info(struct seq_file *m) |
f97108d1 | 1418 | { |
9f25d007 | 1419 | struct drm_info_node *node = m->private; |
f97108d1 | 1420 | struct drm_device *dev = node->minor->dev; |
fac5e23e | 1421 | struct drm_i915_private *dev_priv = to_i915(dev); |
616fdb5a BW |
1422 | u32 rgvmodectl, rstdbyctl; |
1423 | u16 crstandvid; | |
1424 | int ret; | |
1425 | ||
1426 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
1427 | if (ret) | |
1428 | return ret; | |
c8c8fb33 | 1429 | intel_runtime_pm_get(dev_priv); |
616fdb5a BW |
1430 | |
1431 | rgvmodectl = I915_READ(MEMMODECTL); | |
1432 | rstdbyctl = I915_READ(RSTDBYCTL); | |
1433 | crstandvid = I915_READ16(CRSTANDVID); | |
1434 | ||
c8c8fb33 | 1435 | intel_runtime_pm_put(dev_priv); |
616fdb5a | 1436 | mutex_unlock(&dev->struct_mutex); |
f97108d1 | 1437 | |
742f491d | 1438 | seq_printf(m, "HD boost: %s\n", yesno(rgvmodectl & MEMMODE_BOOST_EN)); |
f97108d1 JB |
1439 | seq_printf(m, "Boost freq: %d\n", |
1440 | (rgvmodectl & MEMMODE_BOOST_FREQ_MASK) >> | |
1441 | MEMMODE_BOOST_FREQ_SHIFT); | |
1442 | seq_printf(m, "HW control enabled: %s\n", | |
742f491d | 1443 | yesno(rgvmodectl & MEMMODE_HWIDLE_EN)); |
f97108d1 | 1444 | seq_printf(m, "SW control enabled: %s\n", |
742f491d | 1445 | yesno(rgvmodectl & MEMMODE_SWMODE_EN)); |
f97108d1 | 1446 | seq_printf(m, "Gated voltage change: %s\n", |
742f491d | 1447 | yesno(rgvmodectl & MEMMODE_RCLK_GATE)); |
f97108d1 JB |
1448 | seq_printf(m, "Starting frequency: P%d\n", |
1449 | (rgvmodectl & MEMMODE_FSTART_MASK) >> MEMMODE_FSTART_SHIFT); | |
7648fa99 | 1450 | seq_printf(m, "Max P-state: P%d\n", |
f97108d1 | 1451 | (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT); |
7648fa99 JB |
1452 | seq_printf(m, "Min P-state: P%d\n", (rgvmodectl & MEMMODE_FMIN_MASK)); |
1453 | seq_printf(m, "RS1 VID: %d\n", (crstandvid & 0x3f)); | |
1454 | seq_printf(m, "RS2 VID: %d\n", ((crstandvid >> 8) & 0x3f)); | |
1455 | seq_printf(m, "Render standby enabled: %s\n", | |
742f491d | 1456 | yesno(!(rstdbyctl & RCX_SW_EXIT))); |
267f0c90 | 1457 | seq_puts(m, "Current RS state: "); |
88271da3 JB |
1458 | switch (rstdbyctl & RSX_STATUS_MASK) { |
1459 | case RSX_STATUS_ON: | |
267f0c90 | 1460 | seq_puts(m, "on\n"); |
88271da3 JB |
1461 | break; |
1462 | case RSX_STATUS_RC1: | |
267f0c90 | 1463 | seq_puts(m, "RC1\n"); |
88271da3 JB |
1464 | break; |
1465 | case RSX_STATUS_RC1E: | |
267f0c90 | 1466 | seq_puts(m, "RC1E\n"); |
88271da3 JB |
1467 | break; |
1468 | case RSX_STATUS_RS1: | |
267f0c90 | 1469 | seq_puts(m, "RS1\n"); |
88271da3 JB |
1470 | break; |
1471 | case RSX_STATUS_RS2: | |
267f0c90 | 1472 | seq_puts(m, "RS2 (RC6)\n"); |
88271da3 JB |
1473 | break; |
1474 | case RSX_STATUS_RS3: | |
267f0c90 | 1475 | seq_puts(m, "RC3 (RC6+)\n"); |
88271da3 JB |
1476 | break; |
1477 | default: | |
267f0c90 | 1478 | seq_puts(m, "unknown\n"); |
88271da3 JB |
1479 | break; |
1480 | } | |
f97108d1 JB |
1481 | |
1482 | return 0; | |
1483 | } | |
1484 | ||
f65367b5 | 1485 | static int i915_forcewake_domains(struct seq_file *m, void *data) |
669ab5aa | 1486 | { |
b2cff0db CW |
1487 | struct drm_info_node *node = m->private; |
1488 | struct drm_device *dev = node->minor->dev; | |
fac5e23e | 1489 | struct drm_i915_private *dev_priv = to_i915(dev); |
b2cff0db | 1490 | struct intel_uncore_forcewake_domain *fw_domain; |
b2cff0db CW |
1491 | |
1492 | spin_lock_irq(&dev_priv->uncore.lock); | |
33c582c1 | 1493 | for_each_fw_domain(fw_domain, dev_priv) { |
b2cff0db | 1494 | seq_printf(m, "%s.wake_count = %u\n", |
33c582c1 | 1495 | intel_uncore_forcewake_domain_to_str(fw_domain->id), |
b2cff0db CW |
1496 | fw_domain->wake_count); |
1497 | } | |
1498 | spin_unlock_irq(&dev_priv->uncore.lock); | |
669ab5aa | 1499 | |
b2cff0db CW |
1500 | return 0; |
1501 | } | |
1502 | ||
1503 | static int vlv_drpc_info(struct seq_file *m) | |
1504 | { | |
9f25d007 | 1505 | struct drm_info_node *node = m->private; |
669ab5aa | 1506 | struct drm_device *dev = node->minor->dev; |
fac5e23e | 1507 | struct drm_i915_private *dev_priv = to_i915(dev); |
6b312cd3 | 1508 | u32 rpmodectl1, rcctl1, pw_status; |
669ab5aa | 1509 | |
d46c0517 ID |
1510 | intel_runtime_pm_get(dev_priv); |
1511 | ||
6b312cd3 | 1512 | pw_status = I915_READ(VLV_GTLC_PW_STATUS); |
669ab5aa D |
1513 | rpmodectl1 = I915_READ(GEN6_RP_CONTROL); |
1514 | rcctl1 = I915_READ(GEN6_RC_CONTROL); | |
1515 | ||
d46c0517 ID |
1516 | intel_runtime_pm_put(dev_priv); |
1517 | ||
669ab5aa D |
1518 | seq_printf(m, "Video Turbo Mode: %s\n", |
1519 | yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO)); | |
1520 | seq_printf(m, "Turbo enabled: %s\n", | |
1521 | yesno(rpmodectl1 & GEN6_RP_ENABLE)); | |
1522 | seq_printf(m, "HW control enabled: %s\n", | |
1523 | yesno(rpmodectl1 & GEN6_RP_ENABLE)); | |
1524 | seq_printf(m, "SW control enabled: %s\n", | |
1525 | yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) == | |
1526 | GEN6_RP_MEDIA_SW_MODE)); | |
1527 | seq_printf(m, "RC6 Enabled: %s\n", | |
1528 | yesno(rcctl1 & (GEN7_RC_CTL_TO_MODE | | |
1529 | GEN6_RC_CTL_EI_MODE(1)))); | |
1530 | seq_printf(m, "Render Power Well: %s\n", | |
6b312cd3 | 1531 | (pw_status & VLV_GTLC_PW_RENDER_STATUS_MASK) ? "Up" : "Down"); |
669ab5aa | 1532 | seq_printf(m, "Media Power Well: %s\n", |
6b312cd3 | 1533 | (pw_status & VLV_GTLC_PW_MEDIA_STATUS_MASK) ? "Up" : "Down"); |
669ab5aa | 1534 | |
9cc19be5 ID |
1535 | seq_printf(m, "Render RC6 residency since boot: %u\n", |
1536 | I915_READ(VLV_GT_RENDER_RC6)); | |
1537 | seq_printf(m, "Media RC6 residency since boot: %u\n", | |
1538 | I915_READ(VLV_GT_MEDIA_RC6)); | |
1539 | ||
f65367b5 | 1540 | return i915_forcewake_domains(m, NULL); |
669ab5aa D |
1541 | } |
1542 | ||
4d85529d BW |
1543 | static int gen6_drpc_info(struct seq_file *m) |
1544 | { | |
9f25d007 | 1545 | struct drm_info_node *node = m->private; |
4d85529d | 1546 | struct drm_device *dev = node->minor->dev; |
fac5e23e | 1547 | struct drm_i915_private *dev_priv = to_i915(dev); |
ecd8faea | 1548 | u32 rpmodectl1, gt_core_status, rcctl1, rc6vids = 0; |
f2dd7578 | 1549 | u32 gen9_powergate_enable = 0, gen9_powergate_status = 0; |
93b525dc | 1550 | unsigned forcewake_count; |
aee56cff | 1551 | int count = 0, ret; |
4d85529d BW |
1552 | |
1553 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
1554 | if (ret) | |
1555 | return ret; | |
c8c8fb33 | 1556 | intel_runtime_pm_get(dev_priv); |
4d85529d | 1557 | |
907b28c5 | 1558 | spin_lock_irq(&dev_priv->uncore.lock); |
b2cff0db | 1559 | forcewake_count = dev_priv->uncore.fw_domain[FW_DOMAIN_ID_RENDER].wake_count; |
907b28c5 | 1560 | spin_unlock_irq(&dev_priv->uncore.lock); |
93b525dc DV |
1561 | |
1562 | if (forcewake_count) { | |
267f0c90 DL |
1563 | seq_puts(m, "RC information inaccurate because somebody " |
1564 | "holds a forcewake reference \n"); | |
4d85529d BW |
1565 | } else { |
1566 | /* NB: we cannot use forcewake, else we read the wrong values */ | |
1567 | while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1)) | |
1568 | udelay(10); | |
1569 | seq_printf(m, "RC information accurate: %s\n", yesno(count < 51)); | |
1570 | } | |
1571 | ||
75aa3f63 | 1572 | gt_core_status = I915_READ_FW(GEN6_GT_CORE_STATUS); |
ed71f1b4 | 1573 | trace_i915_reg_rw(false, GEN6_GT_CORE_STATUS, gt_core_status, 4, true); |
4d85529d BW |
1574 | |
1575 | rpmodectl1 = I915_READ(GEN6_RP_CONTROL); | |
1576 | rcctl1 = I915_READ(GEN6_RC_CONTROL); | |
f2dd7578 AG |
1577 | if (INTEL_INFO(dev)->gen >= 9) { |
1578 | gen9_powergate_enable = I915_READ(GEN9_PG_ENABLE); | |
1579 | gen9_powergate_status = I915_READ(GEN9_PWRGT_DOMAIN_STATUS); | |
1580 | } | |
4d85529d | 1581 | mutex_unlock(&dev->struct_mutex); |
44cbd338 BW |
1582 | mutex_lock(&dev_priv->rps.hw_lock); |
1583 | sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids); | |
1584 | mutex_unlock(&dev_priv->rps.hw_lock); | |
4d85529d | 1585 | |
c8c8fb33 PZ |
1586 | intel_runtime_pm_put(dev_priv); |
1587 | ||
4d85529d BW |
1588 | seq_printf(m, "Video Turbo Mode: %s\n", |
1589 | yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO)); | |
1590 | seq_printf(m, "HW control enabled: %s\n", | |
1591 | yesno(rpmodectl1 & GEN6_RP_ENABLE)); | |
1592 | seq_printf(m, "SW control enabled: %s\n", | |
1593 | yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) == | |
1594 | GEN6_RP_MEDIA_SW_MODE)); | |
fff24e21 | 1595 | seq_printf(m, "RC1e Enabled: %s\n", |
4d85529d BW |
1596 | yesno(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE)); |
1597 | seq_printf(m, "RC6 Enabled: %s\n", | |
1598 | yesno(rcctl1 & GEN6_RC_CTL_RC6_ENABLE)); | |
f2dd7578 AG |
1599 | if (INTEL_INFO(dev)->gen >= 9) { |
1600 | seq_printf(m, "Render Well Gating Enabled: %s\n", | |
1601 | yesno(gen9_powergate_enable & GEN9_RENDER_PG_ENABLE)); | |
1602 | seq_printf(m, "Media Well Gating Enabled: %s\n", | |
1603 | yesno(gen9_powergate_enable & GEN9_MEDIA_PG_ENABLE)); | |
1604 | } | |
4d85529d BW |
1605 | seq_printf(m, "Deep RC6 Enabled: %s\n", |
1606 | yesno(rcctl1 & GEN6_RC_CTL_RC6p_ENABLE)); | |
1607 | seq_printf(m, "Deepest RC6 Enabled: %s\n", | |
1608 | yesno(rcctl1 & GEN6_RC_CTL_RC6pp_ENABLE)); | |
267f0c90 | 1609 | seq_puts(m, "Current RC state: "); |
4d85529d BW |
1610 | switch (gt_core_status & GEN6_RCn_MASK) { |
1611 | case GEN6_RC0: | |
1612 | if (gt_core_status & GEN6_CORE_CPD_STATE_MASK) | |
267f0c90 | 1613 | seq_puts(m, "Core Power Down\n"); |
4d85529d | 1614 | else |
267f0c90 | 1615 | seq_puts(m, "on\n"); |
4d85529d BW |
1616 | break; |
1617 | case GEN6_RC3: | |
267f0c90 | 1618 | seq_puts(m, "RC3\n"); |
4d85529d BW |
1619 | break; |
1620 | case GEN6_RC6: | |
267f0c90 | 1621 | seq_puts(m, "RC6\n"); |
4d85529d BW |
1622 | break; |
1623 | case GEN6_RC7: | |
267f0c90 | 1624 | seq_puts(m, "RC7\n"); |
4d85529d BW |
1625 | break; |
1626 | default: | |
267f0c90 | 1627 | seq_puts(m, "Unknown\n"); |
4d85529d BW |
1628 | break; |
1629 | } | |
1630 | ||
1631 | seq_printf(m, "Core Power Down: %s\n", | |
1632 | yesno(gt_core_status & GEN6_CORE_CPD_STATE_MASK)); | |
f2dd7578 AG |
1633 | if (INTEL_INFO(dev)->gen >= 9) { |
1634 | seq_printf(m, "Render Power Well: %s\n", | |
1635 | (gen9_powergate_status & | |
1636 | GEN9_PWRGT_RENDER_STATUS_MASK) ? "Up" : "Down"); | |
1637 | seq_printf(m, "Media Power Well: %s\n", | |
1638 | (gen9_powergate_status & | |
1639 | GEN9_PWRGT_MEDIA_STATUS_MASK) ? "Up" : "Down"); | |
1640 | } | |
cce66a28 BW |
1641 | |
1642 | /* Not exactly sure what this is */ | |
1643 | seq_printf(m, "RC6 \"Locked to RPn\" residency since boot: %u\n", | |
1644 | I915_READ(GEN6_GT_GFX_RC6_LOCKED)); | |
1645 | seq_printf(m, "RC6 residency since boot: %u\n", | |
1646 | I915_READ(GEN6_GT_GFX_RC6)); | |
1647 | seq_printf(m, "RC6+ residency since boot: %u\n", | |
1648 | I915_READ(GEN6_GT_GFX_RC6p)); | |
1649 | seq_printf(m, "RC6++ residency since boot: %u\n", | |
1650 | I915_READ(GEN6_GT_GFX_RC6pp)); | |
1651 | ||
ecd8faea BW |
1652 | seq_printf(m, "RC6 voltage: %dmV\n", |
1653 | GEN6_DECODE_RC6_VID(((rc6vids >> 0) & 0xff))); | |
1654 | seq_printf(m, "RC6+ voltage: %dmV\n", | |
1655 | GEN6_DECODE_RC6_VID(((rc6vids >> 8) & 0xff))); | |
1656 | seq_printf(m, "RC6++ voltage: %dmV\n", | |
1657 | GEN6_DECODE_RC6_VID(((rc6vids >> 16) & 0xff))); | |
f2dd7578 | 1658 | return i915_forcewake_domains(m, NULL); |
4d85529d BW |
1659 | } |
1660 | ||
1661 | static int i915_drpc_info(struct seq_file *m, void *unused) | |
1662 | { | |
9f25d007 | 1663 | struct drm_info_node *node = m->private; |
4d85529d BW |
1664 | struct drm_device *dev = node->minor->dev; |
1665 | ||
666a4537 | 1666 | if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) |
669ab5aa | 1667 | return vlv_drpc_info(m); |
ac66cf4b | 1668 | else if (INTEL_INFO(dev)->gen >= 6) |
4d85529d BW |
1669 | return gen6_drpc_info(m); |
1670 | else | |
1671 | return ironlake_drpc_info(m); | |
1672 | } | |
1673 | ||
9a851789 DV |
1674 | static int i915_frontbuffer_tracking(struct seq_file *m, void *unused) |
1675 | { | |
1676 | struct drm_info_node *node = m->private; | |
1677 | struct drm_device *dev = node->minor->dev; | |
fac5e23e | 1678 | struct drm_i915_private *dev_priv = to_i915(dev); |
9a851789 DV |
1679 | |
1680 | seq_printf(m, "FB tracking busy bits: 0x%08x\n", | |
1681 | dev_priv->fb_tracking.busy_bits); | |
1682 | ||
1683 | seq_printf(m, "FB tracking flip bits: 0x%08x\n", | |
1684 | dev_priv->fb_tracking.flip_bits); | |
1685 | ||
1686 | return 0; | |
1687 | } | |
1688 | ||
b5e50c3f JB |
1689 | static int i915_fbc_status(struct seq_file *m, void *unused) |
1690 | { | |
9f25d007 | 1691 | struct drm_info_node *node = m->private; |
b5e50c3f | 1692 | struct drm_device *dev = node->minor->dev; |
fac5e23e | 1693 | struct drm_i915_private *dev_priv = to_i915(dev); |
b5e50c3f | 1694 | |
3a77c4c4 | 1695 | if (!HAS_FBC(dev)) { |
267f0c90 | 1696 | seq_puts(m, "FBC unsupported on this chipset\n"); |
b5e50c3f JB |
1697 | return 0; |
1698 | } | |
1699 | ||
36623ef8 | 1700 | intel_runtime_pm_get(dev_priv); |
25ad93fd | 1701 | mutex_lock(&dev_priv->fbc.lock); |
36623ef8 | 1702 | |
0e631adc | 1703 | if (intel_fbc_is_active(dev_priv)) |
267f0c90 | 1704 | seq_puts(m, "FBC enabled\n"); |
2e8144a5 PZ |
1705 | else |
1706 | seq_printf(m, "FBC disabled: %s\n", | |
bf6189c6 | 1707 | dev_priv->fbc.no_fbc_reason); |
36623ef8 | 1708 | |
31b9df10 PZ |
1709 | if (INTEL_INFO(dev_priv)->gen >= 7) |
1710 | seq_printf(m, "Compressing: %s\n", | |
1711 | yesno(I915_READ(FBC_STATUS2) & | |
1712 | FBC_COMPRESSION_MASK)); | |
1713 | ||
25ad93fd | 1714 | mutex_unlock(&dev_priv->fbc.lock); |
36623ef8 PZ |
1715 | intel_runtime_pm_put(dev_priv); |
1716 | ||
b5e50c3f JB |
1717 | return 0; |
1718 | } | |
1719 | ||
da46f936 RV |
1720 | static int i915_fbc_fc_get(void *data, u64 *val) |
1721 | { | |
1722 | struct drm_device *dev = data; | |
fac5e23e | 1723 | struct drm_i915_private *dev_priv = to_i915(dev); |
da46f936 RV |
1724 | |
1725 | if (INTEL_INFO(dev)->gen < 7 || !HAS_FBC(dev)) | |
1726 | return -ENODEV; | |
1727 | ||
da46f936 | 1728 | *val = dev_priv->fbc.false_color; |
da46f936 RV |
1729 | |
1730 | return 0; | |
1731 | } | |
1732 | ||
1733 | static int i915_fbc_fc_set(void *data, u64 val) | |
1734 | { | |
1735 | struct drm_device *dev = data; | |
fac5e23e | 1736 | struct drm_i915_private *dev_priv = to_i915(dev); |
da46f936 RV |
1737 | u32 reg; |
1738 | ||
1739 | if (INTEL_INFO(dev)->gen < 7 || !HAS_FBC(dev)) | |
1740 | return -ENODEV; | |
1741 | ||
25ad93fd | 1742 | mutex_lock(&dev_priv->fbc.lock); |
da46f936 RV |
1743 | |
1744 | reg = I915_READ(ILK_DPFC_CONTROL); | |
1745 | dev_priv->fbc.false_color = val; | |
1746 | ||
1747 | I915_WRITE(ILK_DPFC_CONTROL, val ? | |
1748 | (reg | FBC_CTL_FALSE_COLOR) : | |
1749 | (reg & ~FBC_CTL_FALSE_COLOR)); | |
1750 | ||
25ad93fd | 1751 | mutex_unlock(&dev_priv->fbc.lock); |
da46f936 RV |
1752 | return 0; |
1753 | } | |
1754 | ||
1755 | DEFINE_SIMPLE_ATTRIBUTE(i915_fbc_fc_fops, | |
1756 | i915_fbc_fc_get, i915_fbc_fc_set, | |
1757 | "%llu\n"); | |
1758 | ||
92d44621 PZ |
1759 | static int i915_ips_status(struct seq_file *m, void *unused) |
1760 | { | |
9f25d007 | 1761 | struct drm_info_node *node = m->private; |
92d44621 | 1762 | struct drm_device *dev = node->minor->dev; |
fac5e23e | 1763 | struct drm_i915_private *dev_priv = to_i915(dev); |
92d44621 | 1764 | |
f5adf94e | 1765 | if (!HAS_IPS(dev)) { |
92d44621 PZ |
1766 | seq_puts(m, "not supported\n"); |
1767 | return 0; | |
1768 | } | |
1769 | ||
36623ef8 PZ |
1770 | intel_runtime_pm_get(dev_priv); |
1771 | ||
0eaa53f0 RV |
1772 | seq_printf(m, "Enabled by kernel parameter: %s\n", |
1773 | yesno(i915.enable_ips)); | |
1774 | ||
1775 | if (INTEL_INFO(dev)->gen >= 8) { | |
1776 | seq_puts(m, "Currently: unknown\n"); | |
1777 | } else { | |
1778 | if (I915_READ(IPS_CTL) & IPS_ENABLE) | |
1779 | seq_puts(m, "Currently: enabled\n"); | |
1780 | else | |
1781 | seq_puts(m, "Currently: disabled\n"); | |
1782 | } | |
92d44621 | 1783 | |
36623ef8 PZ |
1784 | intel_runtime_pm_put(dev_priv); |
1785 | ||
92d44621 PZ |
1786 | return 0; |
1787 | } | |
1788 | ||
4a9bef37 JB |
1789 | static int i915_sr_status(struct seq_file *m, void *unused) |
1790 | { | |
9f25d007 | 1791 | struct drm_info_node *node = m->private; |
4a9bef37 | 1792 | struct drm_device *dev = node->minor->dev; |
fac5e23e | 1793 | struct drm_i915_private *dev_priv = to_i915(dev); |
4a9bef37 JB |
1794 | bool sr_enabled = false; |
1795 | ||
36623ef8 PZ |
1796 | intel_runtime_pm_get(dev_priv); |
1797 | ||
1398261a | 1798 | if (HAS_PCH_SPLIT(dev)) |
5ba2aaaa | 1799 | sr_enabled = I915_READ(WM1_LP_ILK) & WM1_LP_SR_EN; |
77b64555 ACO |
1800 | else if (IS_CRESTLINE(dev) || IS_G4X(dev) || |
1801 | IS_I945G(dev) || IS_I945GM(dev)) | |
4a9bef37 JB |
1802 | sr_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN; |
1803 | else if (IS_I915GM(dev)) | |
1804 | sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN; | |
1805 | else if (IS_PINEVIEW(dev)) | |
1806 | sr_enabled = I915_READ(DSPFW3) & PINEVIEW_SELF_REFRESH_EN; | |
666a4537 | 1807 | else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) |
77b64555 | 1808 | sr_enabled = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN; |
4a9bef37 | 1809 | |
36623ef8 PZ |
1810 | intel_runtime_pm_put(dev_priv); |
1811 | ||
5ba2aaaa CW |
1812 | seq_printf(m, "self-refresh: %s\n", |
1813 | sr_enabled ? "enabled" : "disabled"); | |
4a9bef37 JB |
1814 | |
1815 | return 0; | |
1816 | } | |
1817 | ||
7648fa99 JB |
1818 | static int i915_emon_status(struct seq_file *m, void *unused) |
1819 | { | |
9f25d007 | 1820 | struct drm_info_node *node = m->private; |
7648fa99 | 1821 | struct drm_device *dev = node->minor->dev; |
fac5e23e | 1822 | struct drm_i915_private *dev_priv = to_i915(dev); |
7648fa99 | 1823 | unsigned long temp, chipset, gfx; |
de227ef0 CW |
1824 | int ret; |
1825 | ||
582be6b4 CW |
1826 | if (!IS_GEN5(dev)) |
1827 | return -ENODEV; | |
1828 | ||
de227ef0 CW |
1829 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
1830 | if (ret) | |
1831 | return ret; | |
7648fa99 JB |
1832 | |
1833 | temp = i915_mch_val(dev_priv); | |
1834 | chipset = i915_chipset_val(dev_priv); | |
1835 | gfx = i915_gfx_val(dev_priv); | |
de227ef0 | 1836 | mutex_unlock(&dev->struct_mutex); |
7648fa99 JB |
1837 | |
1838 | seq_printf(m, "GMCH temp: %ld\n", temp); | |
1839 | seq_printf(m, "Chipset power: %ld\n", chipset); | |
1840 | seq_printf(m, "GFX power: %ld\n", gfx); | |
1841 | seq_printf(m, "Total power: %ld\n", chipset + gfx); | |
1842 | ||
1843 | return 0; | |
1844 | } | |
1845 | ||
23b2f8bb JB |
1846 | static int i915_ring_freq_table(struct seq_file *m, void *unused) |
1847 | { | |
9f25d007 | 1848 | struct drm_info_node *node = m->private; |
23b2f8bb | 1849 | struct drm_device *dev = node->minor->dev; |
fac5e23e | 1850 | struct drm_i915_private *dev_priv = to_i915(dev); |
5bfa0199 | 1851 | int ret = 0; |
23b2f8bb | 1852 | int gpu_freq, ia_freq; |
f936ec34 | 1853 | unsigned int max_gpu_freq, min_gpu_freq; |
23b2f8bb | 1854 | |
97d3308a | 1855 | if (!HAS_CORE_RING_FREQ(dev)) { |
267f0c90 | 1856 | seq_puts(m, "unsupported on this chipset\n"); |
23b2f8bb JB |
1857 | return 0; |
1858 | } | |
1859 | ||
5bfa0199 PZ |
1860 | intel_runtime_pm_get(dev_priv); |
1861 | ||
4fc688ce | 1862 | ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock); |
23b2f8bb | 1863 | if (ret) |
5bfa0199 | 1864 | goto out; |
23b2f8bb | 1865 | |
ef11bdb3 | 1866 | if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) { |
f936ec34 AG |
1867 | /* Convert GT frequency to 50 HZ units */ |
1868 | min_gpu_freq = | |
1869 | dev_priv->rps.min_freq_softlimit / GEN9_FREQ_SCALER; | |
1870 | max_gpu_freq = | |
1871 | dev_priv->rps.max_freq_softlimit / GEN9_FREQ_SCALER; | |
1872 | } else { | |
1873 | min_gpu_freq = dev_priv->rps.min_freq_softlimit; | |
1874 | max_gpu_freq = dev_priv->rps.max_freq_softlimit; | |
1875 | } | |
1876 | ||
267f0c90 | 1877 | seq_puts(m, "GPU freq (MHz)\tEffective CPU freq (MHz)\tEffective Ring freq (MHz)\n"); |
23b2f8bb | 1878 | |
f936ec34 | 1879 | for (gpu_freq = min_gpu_freq; gpu_freq <= max_gpu_freq; gpu_freq++) { |
42c0526c BW |
1880 | ia_freq = gpu_freq; |
1881 | sandybridge_pcode_read(dev_priv, | |
1882 | GEN6_PCODE_READ_MIN_FREQ_TABLE, | |
1883 | &ia_freq); | |
3ebecd07 | 1884 | seq_printf(m, "%d\t\t%d\t\t\t\t%d\n", |
f936ec34 | 1885 | intel_gpu_freq(dev_priv, (gpu_freq * |
ef11bdb3 RV |
1886 | (IS_SKYLAKE(dev) || IS_KABYLAKE(dev) ? |
1887 | GEN9_FREQ_SCALER : 1))), | |
3ebecd07 CW |
1888 | ((ia_freq >> 0) & 0xff) * 100, |
1889 | ((ia_freq >> 8) & 0xff) * 100); | |
23b2f8bb JB |
1890 | } |
1891 | ||
4fc688ce | 1892 | mutex_unlock(&dev_priv->rps.hw_lock); |
23b2f8bb | 1893 | |
5bfa0199 PZ |
1894 | out: |
1895 | intel_runtime_pm_put(dev_priv); | |
1896 | return ret; | |
23b2f8bb JB |
1897 | } |
1898 | ||
44834a67 CW |
1899 | static int i915_opregion(struct seq_file *m, void *unused) |
1900 | { | |
9f25d007 | 1901 | struct drm_info_node *node = m->private; |
44834a67 | 1902 | struct drm_device *dev = node->minor->dev; |
fac5e23e | 1903 | struct drm_i915_private *dev_priv = to_i915(dev); |
44834a67 CW |
1904 | struct intel_opregion *opregion = &dev_priv->opregion; |
1905 | int ret; | |
1906 | ||
1907 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
1908 | if (ret) | |
0d38f009 | 1909 | goto out; |
44834a67 | 1910 | |
2455a8e4 JN |
1911 | if (opregion->header) |
1912 | seq_write(m, opregion->header, OPREGION_SIZE); | |
44834a67 CW |
1913 | |
1914 | mutex_unlock(&dev->struct_mutex); | |
1915 | ||
0d38f009 | 1916 | out: |
44834a67 CW |
1917 | return 0; |
1918 | } | |
1919 | ||
ada8f955 JN |
1920 | static int i915_vbt(struct seq_file *m, void *unused) |
1921 | { | |
1922 | struct drm_info_node *node = m->private; | |
1923 | struct drm_device *dev = node->minor->dev; | |
fac5e23e | 1924 | struct drm_i915_private *dev_priv = to_i915(dev); |
ada8f955 JN |
1925 | struct intel_opregion *opregion = &dev_priv->opregion; |
1926 | ||
1927 | if (opregion->vbt) | |
1928 | seq_write(m, opregion->vbt, opregion->vbt_size); | |
1929 | ||
1930 | return 0; | |
1931 | } | |
1932 | ||
37811fcc CW |
1933 | static int i915_gem_framebuffer_info(struct seq_file *m, void *data) |
1934 | { | |
9f25d007 | 1935 | struct drm_info_node *node = m->private; |
37811fcc | 1936 | struct drm_device *dev = node->minor->dev; |
b13b8402 | 1937 | struct intel_framebuffer *fbdev_fb = NULL; |
3a58ee10 | 1938 | struct drm_framebuffer *drm_fb; |
188c1ab7 CW |
1939 | int ret; |
1940 | ||
1941 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
1942 | if (ret) | |
1943 | return ret; | |
37811fcc | 1944 | |
0695726e | 1945 | #ifdef CONFIG_DRM_FBDEV_EMULATION |
25bcce94 CW |
1946 | if (to_i915(dev)->fbdev) { |
1947 | fbdev_fb = to_intel_framebuffer(to_i915(dev)->fbdev->helper.fb); | |
1948 | ||
1949 | seq_printf(m, "fbcon size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ", | |
1950 | fbdev_fb->base.width, | |
1951 | fbdev_fb->base.height, | |
1952 | fbdev_fb->base.depth, | |
1953 | fbdev_fb->base.bits_per_pixel, | |
1954 | fbdev_fb->base.modifier[0], | |
1955 | drm_framebuffer_read_refcount(&fbdev_fb->base)); | |
1956 | describe_obj(m, fbdev_fb->obj); | |
1957 | seq_putc(m, '\n'); | |
1958 | } | |
4520f53a | 1959 | #endif |
37811fcc | 1960 | |
4b096ac1 | 1961 | mutex_lock(&dev->mode_config.fb_lock); |
3a58ee10 | 1962 | drm_for_each_fb(drm_fb, dev) { |
b13b8402 NS |
1963 | struct intel_framebuffer *fb = to_intel_framebuffer(drm_fb); |
1964 | if (fb == fbdev_fb) | |
37811fcc CW |
1965 | continue; |
1966 | ||
c1ca506d | 1967 | seq_printf(m, "user size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ", |
37811fcc CW |
1968 | fb->base.width, |
1969 | fb->base.height, | |
1970 | fb->base.depth, | |
623f9783 | 1971 | fb->base.bits_per_pixel, |
c1ca506d | 1972 | fb->base.modifier[0], |
747a598f | 1973 | drm_framebuffer_read_refcount(&fb->base)); |
05394f39 | 1974 | describe_obj(m, fb->obj); |
267f0c90 | 1975 | seq_putc(m, '\n'); |
37811fcc | 1976 | } |
4b096ac1 | 1977 | mutex_unlock(&dev->mode_config.fb_lock); |
188c1ab7 | 1978 | mutex_unlock(&dev->struct_mutex); |
37811fcc CW |
1979 | |
1980 | return 0; | |
1981 | } | |
1982 | ||
7e37f889 | 1983 | static void describe_ctx_ring(struct seq_file *m, struct intel_ring *ring) |
c9fe99bd OM |
1984 | { |
1985 | seq_printf(m, " (ringbuffer, space: %d, head: %u, tail: %u, last head: %d)", | |
7e37f889 CW |
1986 | ring->space, ring->head, ring->tail, |
1987 | ring->last_retired_head); | |
c9fe99bd OM |
1988 | } |
1989 | ||
e76d3630 BW |
1990 | static int i915_context_status(struct seq_file *m, void *unused) |
1991 | { | |
9f25d007 | 1992 | struct drm_info_node *node = m->private; |
e76d3630 | 1993 | struct drm_device *dev = node->minor->dev; |
fac5e23e | 1994 | struct drm_i915_private *dev_priv = to_i915(dev); |
e2f80391 | 1995 | struct intel_engine_cs *engine; |
e2efd130 | 1996 | struct i915_gem_context *ctx; |
c3232b18 | 1997 | int ret; |
e76d3630 | 1998 | |
f3d28878 | 1999 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
e76d3630 BW |
2000 | if (ret) |
2001 | return ret; | |
2002 | ||
a33afea5 | 2003 | list_for_each_entry(ctx, &dev_priv->context_list, link) { |
5d1808ec | 2004 | seq_printf(m, "HW context %u ", ctx->hw_id); |
d28b99ab CW |
2005 | if (IS_ERR(ctx->file_priv)) { |
2006 | seq_puts(m, "(deleted) "); | |
2007 | } else if (ctx->file_priv) { | |
2008 | struct pid *pid = ctx->file_priv->file->pid; | |
2009 | struct task_struct *task; | |
2010 | ||
2011 | task = get_pid_task(pid, PIDTYPE_PID); | |
2012 | if (task) { | |
2013 | seq_printf(m, "(%s [%d]) ", | |
2014 | task->comm, task->pid); | |
2015 | put_task_struct(task); | |
2016 | } | |
2017 | } else { | |
2018 | seq_puts(m, "(kernel) "); | |
2019 | } | |
2020 | ||
bca44d80 CW |
2021 | seq_putc(m, ctx->remap_slice ? 'R' : 'r'); |
2022 | seq_putc(m, '\n'); | |
c9fe99bd | 2023 | |
bca44d80 CW |
2024 | for_each_engine(engine, dev_priv) { |
2025 | struct intel_context *ce = &ctx->engine[engine->id]; | |
2026 | ||
2027 | seq_printf(m, "%s: ", engine->name); | |
2028 | seq_putc(m, ce->initialised ? 'I' : 'i'); | |
2029 | if (ce->state) | |
2030 | describe_obj(m, ce->state); | |
dca33ecc | 2031 | if (ce->ring) |
7e37f889 | 2032 | describe_ctx_ring(m, ce->ring); |
c9fe99bd | 2033 | seq_putc(m, '\n'); |
c9fe99bd | 2034 | } |
a33afea5 | 2035 | |
a33afea5 | 2036 | seq_putc(m, '\n'); |
a168c293 BW |
2037 | } |
2038 | ||
f3d28878 | 2039 | mutex_unlock(&dev->struct_mutex); |
e76d3630 BW |
2040 | |
2041 | return 0; | |
2042 | } | |
2043 | ||
064ca1d2 | 2044 | static void i915_dump_lrc_obj(struct seq_file *m, |
e2efd130 | 2045 | struct i915_gem_context *ctx, |
0bc40be8 | 2046 | struct intel_engine_cs *engine) |
064ca1d2 | 2047 | { |
bca44d80 | 2048 | struct drm_i915_gem_object *ctx_obj = ctx->engine[engine->id].state; |
064ca1d2 TD |
2049 | struct page *page; |
2050 | uint32_t *reg_state; | |
2051 | int j; | |
2052 | unsigned long ggtt_offset = 0; | |
2053 | ||
7069b144 CW |
2054 | seq_printf(m, "CONTEXT: %s %u\n", engine->name, ctx->hw_id); |
2055 | ||
064ca1d2 | 2056 | if (ctx_obj == NULL) { |
7069b144 | 2057 | seq_puts(m, "\tNot allocated\n"); |
064ca1d2 TD |
2058 | return; |
2059 | } | |
2060 | ||
064ca1d2 TD |
2061 | if (!i915_gem_obj_ggtt_bound(ctx_obj)) |
2062 | seq_puts(m, "\tNot bound in GGTT\n"); | |
2063 | else | |
2064 | ggtt_offset = i915_gem_obj_ggtt_offset(ctx_obj); | |
2065 | ||
2066 | if (i915_gem_object_get_pages(ctx_obj)) { | |
2067 | seq_puts(m, "\tFailed to get pages for context object\n"); | |
2068 | return; | |
2069 | } | |
2070 | ||
d1675198 | 2071 | page = i915_gem_object_get_page(ctx_obj, LRC_STATE_PN); |
064ca1d2 TD |
2072 | if (!WARN_ON(page == NULL)) { |
2073 | reg_state = kmap_atomic(page); | |
2074 | ||
2075 | for (j = 0; j < 0x600 / sizeof(u32) / 4; j += 4) { | |
2076 | seq_printf(m, "\t[0x%08lx] 0x%08x 0x%08x 0x%08x 0x%08x\n", | |
2077 | ggtt_offset + 4096 + (j * 4), | |
2078 | reg_state[j], reg_state[j + 1], | |
2079 | reg_state[j + 2], reg_state[j + 3]); | |
2080 | } | |
2081 | kunmap_atomic(reg_state); | |
2082 | } | |
2083 | ||
2084 | seq_putc(m, '\n'); | |
2085 | } | |
2086 | ||
c0ab1ae9 BW |
2087 | static int i915_dump_lrc(struct seq_file *m, void *unused) |
2088 | { | |
2089 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
2090 | struct drm_device *dev = node->minor->dev; | |
fac5e23e | 2091 | struct drm_i915_private *dev_priv = to_i915(dev); |
e2f80391 | 2092 | struct intel_engine_cs *engine; |
e2efd130 | 2093 | struct i915_gem_context *ctx; |
b4ac5afc | 2094 | int ret; |
c0ab1ae9 BW |
2095 | |
2096 | if (!i915.enable_execlists) { | |
2097 | seq_printf(m, "Logical Ring Contexts are disabled\n"); | |
2098 | return 0; | |
2099 | } | |
2100 | ||
2101 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
2102 | if (ret) | |
2103 | return ret; | |
2104 | ||
e28e404c | 2105 | list_for_each_entry(ctx, &dev_priv->context_list, link) |
24f1d3cc CW |
2106 | for_each_engine(engine, dev_priv) |
2107 | i915_dump_lrc_obj(m, ctx, engine); | |
c0ab1ae9 BW |
2108 | |
2109 | mutex_unlock(&dev->struct_mutex); | |
2110 | ||
2111 | return 0; | |
2112 | } | |
2113 | ||
4ba70e44 OM |
2114 | static int i915_execlists(struct seq_file *m, void *data) |
2115 | { | |
2116 | struct drm_info_node *node = (struct drm_info_node *)m->private; | |
2117 | struct drm_device *dev = node->minor->dev; | |
fac5e23e | 2118 | struct drm_i915_private *dev_priv = to_i915(dev); |
e2f80391 | 2119 | struct intel_engine_cs *engine; |
4ba70e44 OM |
2120 | u32 status_pointer; |
2121 | u8 read_pointer; | |
2122 | u8 write_pointer; | |
2123 | u32 status; | |
2124 | u32 ctx_id; | |
2125 | struct list_head *cursor; | |
b4ac5afc | 2126 | int i, ret; |
4ba70e44 OM |
2127 | |
2128 | if (!i915.enable_execlists) { | |
2129 | seq_puts(m, "Logical Ring Contexts are disabled\n"); | |
2130 | return 0; | |
2131 | } | |
2132 | ||
2133 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
2134 | if (ret) | |
2135 | return ret; | |
2136 | ||
fc0412ec MT |
2137 | intel_runtime_pm_get(dev_priv); |
2138 | ||
b4ac5afc | 2139 | for_each_engine(engine, dev_priv) { |
6d3d8274 | 2140 | struct drm_i915_gem_request *head_req = NULL; |
4ba70e44 | 2141 | int count = 0; |
4ba70e44 | 2142 | |
e2f80391 | 2143 | seq_printf(m, "%s\n", engine->name); |
4ba70e44 | 2144 | |
e2f80391 TU |
2145 | status = I915_READ(RING_EXECLIST_STATUS_LO(engine)); |
2146 | ctx_id = I915_READ(RING_EXECLIST_STATUS_HI(engine)); | |
4ba70e44 OM |
2147 | seq_printf(m, "\tExeclist status: 0x%08X, context: %u\n", |
2148 | status, ctx_id); | |
2149 | ||
e2f80391 | 2150 | status_pointer = I915_READ(RING_CONTEXT_STATUS_PTR(engine)); |
4ba70e44 OM |
2151 | seq_printf(m, "\tStatus pointer: 0x%08X\n", status_pointer); |
2152 | ||
e2f80391 | 2153 | read_pointer = engine->next_context_status_buffer; |
5590a5f0 | 2154 | write_pointer = GEN8_CSB_WRITE_PTR(status_pointer); |
4ba70e44 | 2155 | if (read_pointer > write_pointer) |
5590a5f0 | 2156 | write_pointer += GEN8_CSB_ENTRIES; |
4ba70e44 OM |
2157 | seq_printf(m, "\tRead pointer: 0x%08X, write pointer 0x%08X\n", |
2158 | read_pointer, write_pointer); | |
2159 | ||
5590a5f0 | 2160 | for (i = 0; i < GEN8_CSB_ENTRIES; i++) { |
e2f80391 TU |
2161 | status = I915_READ(RING_CONTEXT_STATUS_BUF_LO(engine, i)); |
2162 | ctx_id = I915_READ(RING_CONTEXT_STATUS_BUF_HI(engine, i)); | |
4ba70e44 OM |
2163 | |
2164 | seq_printf(m, "\tStatus buffer %d: 0x%08X, context: %u\n", | |
2165 | i, status, ctx_id); | |
2166 | } | |
2167 | ||
27af5eea | 2168 | spin_lock_bh(&engine->execlist_lock); |
e2f80391 | 2169 | list_for_each(cursor, &engine->execlist_queue) |
4ba70e44 | 2170 | count++; |
e2f80391 TU |
2171 | head_req = list_first_entry_or_null(&engine->execlist_queue, |
2172 | struct drm_i915_gem_request, | |
2173 | execlist_link); | |
27af5eea | 2174 | spin_unlock_bh(&engine->execlist_lock); |
4ba70e44 OM |
2175 | |
2176 | seq_printf(m, "\t%d requests in queue\n", count); | |
2177 | if (head_req) { | |
7069b144 CW |
2178 | seq_printf(m, "\tHead request context: %u\n", |
2179 | head_req->ctx->hw_id); | |
4ba70e44 | 2180 | seq_printf(m, "\tHead request tail: %u\n", |
6d3d8274 | 2181 | head_req->tail); |
4ba70e44 OM |
2182 | } |
2183 | ||
2184 | seq_putc(m, '\n'); | |
2185 | } | |
2186 | ||
fc0412ec | 2187 | intel_runtime_pm_put(dev_priv); |
4ba70e44 OM |
2188 | mutex_unlock(&dev->struct_mutex); |
2189 | ||
2190 | return 0; | |
2191 | } | |
2192 | ||
ea16a3cd DV |
2193 | static const char *swizzle_string(unsigned swizzle) |
2194 | { | |
aee56cff | 2195 | switch (swizzle) { |
ea16a3cd DV |
2196 | case I915_BIT_6_SWIZZLE_NONE: |
2197 | return "none"; | |
2198 | case I915_BIT_6_SWIZZLE_9: | |
2199 | return "bit9"; | |
2200 | case I915_BIT_6_SWIZZLE_9_10: | |
2201 | return "bit9/bit10"; | |
2202 | case I915_BIT_6_SWIZZLE_9_11: | |
2203 | return "bit9/bit11"; | |
2204 | case I915_BIT_6_SWIZZLE_9_10_11: | |
2205 | return "bit9/bit10/bit11"; | |
2206 | case I915_BIT_6_SWIZZLE_9_17: | |
2207 | return "bit9/bit17"; | |
2208 | case I915_BIT_6_SWIZZLE_9_10_17: | |
2209 | return "bit9/bit10/bit17"; | |
2210 | case I915_BIT_6_SWIZZLE_UNKNOWN: | |
8a168ca7 | 2211 | return "unknown"; |
ea16a3cd DV |
2212 | } |
2213 | ||
2214 | return "bug"; | |
2215 | } | |
2216 | ||
2217 | static int i915_swizzle_info(struct seq_file *m, void *data) | |
2218 | { | |
9f25d007 | 2219 | struct drm_info_node *node = m->private; |
ea16a3cd | 2220 | struct drm_device *dev = node->minor->dev; |
fac5e23e | 2221 | struct drm_i915_private *dev_priv = to_i915(dev); |
22bcfc6a DV |
2222 | int ret; |
2223 | ||
2224 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
2225 | if (ret) | |
2226 | return ret; | |
c8c8fb33 | 2227 | intel_runtime_pm_get(dev_priv); |
ea16a3cd | 2228 | |
ea16a3cd DV |
2229 | seq_printf(m, "bit6 swizzle for X-tiling = %s\n", |
2230 | swizzle_string(dev_priv->mm.bit_6_swizzle_x)); | |
2231 | seq_printf(m, "bit6 swizzle for Y-tiling = %s\n", | |
2232 | swizzle_string(dev_priv->mm.bit_6_swizzle_y)); | |
2233 | ||
2234 | if (IS_GEN3(dev) || IS_GEN4(dev)) { | |
2235 | seq_printf(m, "DDC = 0x%08x\n", | |
2236 | I915_READ(DCC)); | |
656bfa3a DV |
2237 | seq_printf(m, "DDC2 = 0x%08x\n", |
2238 | I915_READ(DCC2)); | |
ea16a3cd DV |
2239 | seq_printf(m, "C0DRB3 = 0x%04x\n", |
2240 | I915_READ16(C0DRB3)); | |
2241 | seq_printf(m, "C1DRB3 = 0x%04x\n", | |
2242 | I915_READ16(C1DRB3)); | |
9d3203e1 | 2243 | } else if (INTEL_INFO(dev)->gen >= 6) { |
3fa7d235 DV |
2244 | seq_printf(m, "MAD_DIMM_C0 = 0x%08x\n", |
2245 | I915_READ(MAD_DIMM_C0)); | |
2246 | seq_printf(m, "MAD_DIMM_C1 = 0x%08x\n", | |
2247 | I915_READ(MAD_DIMM_C1)); | |
2248 | seq_printf(m, "MAD_DIMM_C2 = 0x%08x\n", | |
2249 | I915_READ(MAD_DIMM_C2)); | |
2250 | seq_printf(m, "TILECTL = 0x%08x\n", | |
2251 | I915_READ(TILECTL)); | |
5907f5fb | 2252 | if (INTEL_INFO(dev)->gen >= 8) |
9d3203e1 BW |
2253 | seq_printf(m, "GAMTARBMODE = 0x%08x\n", |
2254 | I915_READ(GAMTARBMODE)); | |
2255 | else | |
2256 | seq_printf(m, "ARB_MODE = 0x%08x\n", | |
2257 | I915_READ(ARB_MODE)); | |
3fa7d235 DV |
2258 | seq_printf(m, "DISP_ARB_CTL = 0x%08x\n", |
2259 | I915_READ(DISP_ARB_CTL)); | |
ea16a3cd | 2260 | } |
656bfa3a DV |
2261 | |
2262 | if (dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES) | |
2263 | seq_puts(m, "L-shaped memory detected\n"); | |
2264 | ||
c8c8fb33 | 2265 | intel_runtime_pm_put(dev_priv); |
ea16a3cd DV |
2266 | mutex_unlock(&dev->struct_mutex); |
2267 | ||
2268 | return 0; | |
2269 | } | |
2270 | ||
1c60fef5 BW |
2271 | static int per_file_ctx(int id, void *ptr, void *data) |
2272 | { | |
e2efd130 | 2273 | struct i915_gem_context *ctx = ptr; |
1c60fef5 | 2274 | struct seq_file *m = data; |
ae6c4806 DV |
2275 | struct i915_hw_ppgtt *ppgtt = ctx->ppgtt; |
2276 | ||
2277 | if (!ppgtt) { | |
2278 | seq_printf(m, " no ppgtt for context %d\n", | |
2279 | ctx->user_handle); | |
2280 | return 0; | |
2281 | } | |
1c60fef5 | 2282 | |
f83d6518 OM |
2283 | if (i915_gem_context_is_default(ctx)) |
2284 | seq_puts(m, " default context:\n"); | |
2285 | else | |
821d66dd | 2286 | seq_printf(m, " context %d:\n", ctx->user_handle); |
1c60fef5 BW |
2287 | ppgtt->debug_dump(ppgtt, m); |
2288 | ||
2289 | return 0; | |
2290 | } | |
2291 | ||
77df6772 | 2292 | static void gen8_ppgtt_info(struct seq_file *m, struct drm_device *dev) |
3cf17fc5 | 2293 | { |
fac5e23e | 2294 | struct drm_i915_private *dev_priv = to_i915(dev); |
e2f80391 | 2295 | struct intel_engine_cs *engine; |
77df6772 | 2296 | struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt; |
b4ac5afc | 2297 | int i; |
3cf17fc5 | 2298 | |
77df6772 BW |
2299 | if (!ppgtt) |
2300 | return; | |
2301 | ||
b4ac5afc | 2302 | for_each_engine(engine, dev_priv) { |
e2f80391 | 2303 | seq_printf(m, "%s\n", engine->name); |
77df6772 | 2304 | for (i = 0; i < 4; i++) { |
e2f80391 | 2305 | u64 pdp = I915_READ(GEN8_RING_PDP_UDW(engine, i)); |
77df6772 | 2306 | pdp <<= 32; |
e2f80391 | 2307 | pdp |= I915_READ(GEN8_RING_PDP_LDW(engine, i)); |
a2a5b15c | 2308 | seq_printf(m, "\tPDP%d 0x%016llx\n", i, pdp); |
77df6772 BW |
2309 | } |
2310 | } | |
2311 | } | |
2312 | ||
2313 | static void gen6_ppgtt_info(struct seq_file *m, struct drm_device *dev) | |
2314 | { | |
fac5e23e | 2315 | struct drm_i915_private *dev_priv = to_i915(dev); |
e2f80391 | 2316 | struct intel_engine_cs *engine; |
3cf17fc5 | 2317 | |
7e22dbbb | 2318 | if (IS_GEN6(dev_priv)) |
3cf17fc5 DV |
2319 | seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(GFX_MODE)); |
2320 | ||
b4ac5afc | 2321 | for_each_engine(engine, dev_priv) { |
e2f80391 | 2322 | seq_printf(m, "%s\n", engine->name); |
7e22dbbb | 2323 | if (IS_GEN7(dev_priv)) |
e2f80391 TU |
2324 | seq_printf(m, "GFX_MODE: 0x%08x\n", |
2325 | I915_READ(RING_MODE_GEN7(engine))); | |
2326 | seq_printf(m, "PP_DIR_BASE: 0x%08x\n", | |
2327 | I915_READ(RING_PP_DIR_BASE(engine))); | |
2328 | seq_printf(m, "PP_DIR_BASE_READ: 0x%08x\n", | |
2329 | I915_READ(RING_PP_DIR_BASE_READ(engine))); | |
2330 | seq_printf(m, "PP_DIR_DCLV: 0x%08x\n", | |
2331 | I915_READ(RING_PP_DIR_DCLV(engine))); | |
3cf17fc5 DV |
2332 | } |
2333 | if (dev_priv->mm.aliasing_ppgtt) { | |
2334 | struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt; | |
2335 | ||
267f0c90 | 2336 | seq_puts(m, "aliasing PPGTT:\n"); |
44159ddb | 2337 | seq_printf(m, "pd gtt offset: 0x%08x\n", ppgtt->pd.base.ggtt_offset); |
1c60fef5 | 2338 | |
87d60b63 | 2339 | ppgtt->debug_dump(ppgtt, m); |
ae6c4806 | 2340 | } |
1c60fef5 | 2341 | |
3cf17fc5 | 2342 | seq_printf(m, "ECOCHK: 0x%08x\n", I915_READ(GAM_ECOCHK)); |
77df6772 BW |
2343 | } |
2344 | ||
2345 | static int i915_ppgtt_info(struct seq_file *m, void *data) | |
2346 | { | |
9f25d007 | 2347 | struct drm_info_node *node = m->private; |
77df6772 | 2348 | struct drm_device *dev = node->minor->dev; |
fac5e23e | 2349 | struct drm_i915_private *dev_priv = to_i915(dev); |
ea91e401 | 2350 | struct drm_file *file; |
77df6772 BW |
2351 | |
2352 | int ret = mutex_lock_interruptible(&dev->struct_mutex); | |
2353 | if (ret) | |
2354 | return ret; | |
c8c8fb33 | 2355 | intel_runtime_pm_get(dev_priv); |
77df6772 BW |
2356 | |
2357 | if (INTEL_INFO(dev)->gen >= 8) | |
2358 | gen8_ppgtt_info(m, dev); | |
2359 | else if (INTEL_INFO(dev)->gen >= 6) | |
2360 | gen6_ppgtt_info(m, dev); | |
2361 | ||
1d2ac403 | 2362 | mutex_lock(&dev->filelist_mutex); |
ea91e401 MT |
2363 | list_for_each_entry_reverse(file, &dev->filelist, lhead) { |
2364 | struct drm_i915_file_private *file_priv = file->driver_priv; | |
7cb5dff8 | 2365 | struct task_struct *task; |
ea91e401 | 2366 | |
7cb5dff8 | 2367 | task = get_pid_task(file->pid, PIDTYPE_PID); |
06812760 DC |
2368 | if (!task) { |
2369 | ret = -ESRCH; | |
b0212486 | 2370 | goto out_unlock; |
06812760 | 2371 | } |
7cb5dff8 GT |
2372 | seq_printf(m, "\nproc: %s\n", task->comm); |
2373 | put_task_struct(task); | |
ea91e401 MT |
2374 | idr_for_each(&file_priv->context_idr, per_file_ctx, |
2375 | (void *)(unsigned long)m); | |
2376 | } | |
b0212486 | 2377 | out_unlock: |
1d2ac403 | 2378 | mutex_unlock(&dev->filelist_mutex); |
ea91e401 | 2379 | |
c8c8fb33 | 2380 | intel_runtime_pm_put(dev_priv); |
3cf17fc5 DV |
2381 | mutex_unlock(&dev->struct_mutex); |
2382 | ||
06812760 | 2383 | return ret; |
3cf17fc5 DV |
2384 | } |
2385 | ||
f5a4c67d CW |
2386 | static int count_irq_waiters(struct drm_i915_private *i915) |
2387 | { | |
e2f80391 | 2388 | struct intel_engine_cs *engine; |
f5a4c67d | 2389 | int count = 0; |
f5a4c67d | 2390 | |
b4ac5afc | 2391 | for_each_engine(engine, i915) |
688e6c72 | 2392 | count += intel_engine_has_waiter(engine); |
f5a4c67d CW |
2393 | |
2394 | return count; | |
2395 | } | |
2396 | ||
7466c291 CW |
2397 | static const char *rps_power_to_str(unsigned int power) |
2398 | { | |
2399 | static const char * const strings[] = { | |
2400 | [LOW_POWER] = "low power", | |
2401 | [BETWEEN] = "mixed", | |
2402 | [HIGH_POWER] = "high power", | |
2403 | }; | |
2404 | ||
2405 | if (power >= ARRAY_SIZE(strings) || !strings[power]) | |
2406 | return "unknown"; | |
2407 | ||
2408 | return strings[power]; | |
2409 | } | |
2410 | ||
1854d5ca CW |
2411 | static int i915_rps_boost_info(struct seq_file *m, void *data) |
2412 | { | |
2413 | struct drm_info_node *node = m->private; | |
2414 | struct drm_device *dev = node->minor->dev; | |
fac5e23e | 2415 | struct drm_i915_private *dev_priv = to_i915(dev); |
1854d5ca | 2416 | struct drm_file *file; |
1854d5ca | 2417 | |
f5a4c67d | 2418 | seq_printf(m, "RPS enabled? %d\n", dev_priv->rps.enabled); |
67d97da3 CW |
2419 | seq_printf(m, "GPU busy? %s [%x]\n", |
2420 | yesno(dev_priv->gt.awake), dev_priv->gt.active_engines); | |
f5a4c67d | 2421 | seq_printf(m, "CPU waiting? %d\n", count_irq_waiters(dev_priv)); |
7466c291 CW |
2422 | seq_printf(m, "Frequency requested %d\n", |
2423 | intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq)); | |
2424 | seq_printf(m, " min hard:%d, soft:%d; max soft:%d, hard:%d\n", | |
f5a4c67d CW |
2425 | intel_gpu_freq(dev_priv, dev_priv->rps.min_freq), |
2426 | intel_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit), | |
2427 | intel_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit), | |
2428 | intel_gpu_freq(dev_priv, dev_priv->rps.max_freq)); | |
7466c291 CW |
2429 | seq_printf(m, " idle:%d, efficient:%d, boost:%d\n", |
2430 | intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq), | |
2431 | intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq), | |
2432 | intel_gpu_freq(dev_priv, dev_priv->rps.boost_freq)); | |
1d2ac403 DV |
2433 | |
2434 | mutex_lock(&dev->filelist_mutex); | |
8d3afd7d | 2435 | spin_lock(&dev_priv->rps.client_lock); |
1854d5ca CW |
2436 | list_for_each_entry_reverse(file, &dev->filelist, lhead) { |
2437 | struct drm_i915_file_private *file_priv = file->driver_priv; | |
2438 | struct task_struct *task; | |
2439 | ||
2440 | rcu_read_lock(); | |
2441 | task = pid_task(file->pid, PIDTYPE_PID); | |
2442 | seq_printf(m, "%s [%d]: %d boosts%s\n", | |
2443 | task ? task->comm : "<unknown>", | |
2444 | task ? task->pid : -1, | |
2e1b8730 CW |
2445 | file_priv->rps.boosts, |
2446 | list_empty(&file_priv->rps.link) ? "" : ", active"); | |
1854d5ca CW |
2447 | rcu_read_unlock(); |
2448 | } | |
197be2ae | 2449 | seq_printf(m, "Kernel (anonymous) boosts: %d\n", dev_priv->rps.boosts); |
8d3afd7d | 2450 | spin_unlock(&dev_priv->rps.client_lock); |
1d2ac403 | 2451 | mutex_unlock(&dev->filelist_mutex); |
1854d5ca | 2452 | |
7466c291 CW |
2453 | if (INTEL_GEN(dev_priv) >= 6 && |
2454 | dev_priv->rps.enabled && | |
2455 | dev_priv->gt.active_engines) { | |
2456 | u32 rpup, rpupei; | |
2457 | u32 rpdown, rpdownei; | |
2458 | ||
2459 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); | |
2460 | rpup = I915_READ_FW(GEN6_RP_CUR_UP) & GEN6_RP_EI_MASK; | |
2461 | rpupei = I915_READ_FW(GEN6_RP_CUR_UP_EI) & GEN6_RP_EI_MASK; | |
2462 | rpdown = I915_READ_FW(GEN6_RP_CUR_DOWN) & GEN6_RP_EI_MASK; | |
2463 | rpdownei = I915_READ_FW(GEN6_RP_CUR_DOWN_EI) & GEN6_RP_EI_MASK; | |
2464 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); | |
2465 | ||
2466 | seq_printf(m, "\nRPS Autotuning (current \"%s\" window):\n", | |
2467 | rps_power_to_str(dev_priv->rps.power)); | |
2468 | seq_printf(m, " Avg. up: %d%% [above threshold? %d%%]\n", | |
2469 | 100 * rpup / rpupei, | |
2470 | dev_priv->rps.up_threshold); | |
2471 | seq_printf(m, " Avg. down: %d%% [below threshold? %d%%]\n", | |
2472 | 100 * rpdown / rpdownei, | |
2473 | dev_priv->rps.down_threshold); | |
2474 | } else { | |
2475 | seq_puts(m, "\nRPS Autotuning inactive\n"); | |
2476 | } | |
2477 | ||
8d3afd7d | 2478 | return 0; |
1854d5ca CW |
2479 | } |
2480 | ||
63573eb7 BW |
2481 | static int i915_llc(struct seq_file *m, void *data) |
2482 | { | |
9f25d007 | 2483 | struct drm_info_node *node = m->private; |
63573eb7 | 2484 | struct drm_device *dev = node->minor->dev; |
fac5e23e | 2485 | struct drm_i915_private *dev_priv = to_i915(dev); |
3accaf7e | 2486 | const bool edram = INTEL_GEN(dev_priv) > 8; |
63573eb7 | 2487 | |
63573eb7 | 2488 | seq_printf(m, "LLC: %s\n", yesno(HAS_LLC(dev))); |
3accaf7e MK |
2489 | seq_printf(m, "%s: %lluMB\n", edram ? "eDRAM" : "eLLC", |
2490 | intel_uncore_edram_size(dev_priv)/1024/1024); | |
63573eb7 BW |
2491 | |
2492 | return 0; | |
2493 | } | |
2494 | ||
fdf5d357 AD |
2495 | static int i915_guc_load_status_info(struct seq_file *m, void *data) |
2496 | { | |
2497 | struct drm_info_node *node = m->private; | |
fac5e23e | 2498 | struct drm_i915_private *dev_priv = to_i915(node->minor->dev); |
fdf5d357 AD |
2499 | struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw; |
2500 | u32 tmp, i; | |
2501 | ||
2d1fe073 | 2502 | if (!HAS_GUC_UCODE(dev_priv)) |
fdf5d357 AD |
2503 | return 0; |
2504 | ||
2505 | seq_printf(m, "GuC firmware status:\n"); | |
2506 | seq_printf(m, "\tpath: %s\n", | |
2507 | guc_fw->guc_fw_path); | |
2508 | seq_printf(m, "\tfetch: %s\n", | |
2509 | intel_guc_fw_status_repr(guc_fw->guc_fw_fetch_status)); | |
2510 | seq_printf(m, "\tload: %s\n", | |
2511 | intel_guc_fw_status_repr(guc_fw->guc_fw_load_status)); | |
2512 | seq_printf(m, "\tversion wanted: %d.%d\n", | |
2513 | guc_fw->guc_fw_major_wanted, guc_fw->guc_fw_minor_wanted); | |
2514 | seq_printf(m, "\tversion found: %d.%d\n", | |
2515 | guc_fw->guc_fw_major_found, guc_fw->guc_fw_minor_found); | |
feda33ef AD |
2516 | seq_printf(m, "\theader: offset is %d; size = %d\n", |
2517 | guc_fw->header_offset, guc_fw->header_size); | |
2518 | seq_printf(m, "\tuCode: offset is %d; size = %d\n", | |
2519 | guc_fw->ucode_offset, guc_fw->ucode_size); | |
2520 | seq_printf(m, "\tRSA: offset is %d; size = %d\n", | |
2521 | guc_fw->rsa_offset, guc_fw->rsa_size); | |
fdf5d357 AD |
2522 | |
2523 | tmp = I915_READ(GUC_STATUS); | |
2524 | ||
2525 | seq_printf(m, "\nGuC status 0x%08x:\n", tmp); | |
2526 | seq_printf(m, "\tBootrom status = 0x%x\n", | |
2527 | (tmp & GS_BOOTROM_MASK) >> GS_BOOTROM_SHIFT); | |
2528 | seq_printf(m, "\tuKernel status = 0x%x\n", | |
2529 | (tmp & GS_UKERNEL_MASK) >> GS_UKERNEL_SHIFT); | |
2530 | seq_printf(m, "\tMIA Core status = 0x%x\n", | |
2531 | (tmp & GS_MIA_MASK) >> GS_MIA_SHIFT); | |
2532 | seq_puts(m, "\nScratch registers:\n"); | |
2533 | for (i = 0; i < 16; i++) | |
2534 | seq_printf(m, "\t%2d: \t0x%x\n", i, I915_READ(SOFT_SCRATCH(i))); | |
2535 | ||
2536 | return 0; | |
2537 | } | |
2538 | ||
8b417c26 DG |
2539 | static void i915_guc_client_info(struct seq_file *m, |
2540 | struct drm_i915_private *dev_priv, | |
2541 | struct i915_guc_client *client) | |
2542 | { | |
e2f80391 | 2543 | struct intel_engine_cs *engine; |
c18468c4 | 2544 | enum intel_engine_id id; |
8b417c26 | 2545 | uint64_t tot = 0; |
8b417c26 DG |
2546 | |
2547 | seq_printf(m, "\tPriority %d, GuC ctx index: %u, PD offset 0x%x\n", | |
2548 | client->priority, client->ctx_index, client->proc_desc_offset); | |
2549 | seq_printf(m, "\tDoorbell id %d, offset: 0x%x, cookie 0x%x\n", | |
2550 | client->doorbell_id, client->doorbell_offset, client->cookie); | |
2551 | seq_printf(m, "\tWQ size %d, offset: 0x%x, tail %d\n", | |
2552 | client->wq_size, client->wq_offset, client->wq_tail); | |
2553 | ||
551aaecd | 2554 | seq_printf(m, "\tWork queue full: %u\n", client->no_wq_space); |
8b417c26 DG |
2555 | seq_printf(m, "\tFailed doorbell: %u\n", client->b_fail); |
2556 | seq_printf(m, "\tLast submission result: %d\n", client->retcode); | |
2557 | ||
c18468c4 DG |
2558 | for_each_engine_id(engine, dev_priv, id) { |
2559 | u64 submissions = client->submissions[id]; | |
2560 | tot += submissions; | |
8b417c26 | 2561 | seq_printf(m, "\tSubmissions: %llu %s\n", |
c18468c4 | 2562 | submissions, engine->name); |
8b417c26 DG |
2563 | } |
2564 | seq_printf(m, "\tTotal: %llu\n", tot); | |
2565 | } | |
2566 | ||
2567 | static int i915_guc_info(struct seq_file *m, void *data) | |
2568 | { | |
2569 | struct drm_info_node *node = m->private; | |
2570 | struct drm_device *dev = node->minor->dev; | |
fac5e23e | 2571 | struct drm_i915_private *dev_priv = to_i915(dev); |
8b417c26 | 2572 | struct intel_guc guc; |
0a0b457f | 2573 | struct i915_guc_client client = {}; |
e2f80391 | 2574 | struct intel_engine_cs *engine; |
c18468c4 | 2575 | enum intel_engine_id id; |
8b417c26 DG |
2576 | u64 total = 0; |
2577 | ||
2d1fe073 | 2578 | if (!HAS_GUC_SCHED(dev_priv)) |
8b417c26 DG |
2579 | return 0; |
2580 | ||
5a843307 AD |
2581 | if (mutex_lock_interruptible(&dev->struct_mutex)) |
2582 | return 0; | |
2583 | ||
8b417c26 | 2584 | /* Take a local copy of the GuC data, so we can dump it at leisure */ |
8b417c26 | 2585 | guc = dev_priv->guc; |
5a843307 | 2586 | if (guc.execbuf_client) |
8b417c26 | 2587 | client = *guc.execbuf_client; |
5a843307 AD |
2588 | |
2589 | mutex_unlock(&dev->struct_mutex); | |
8b417c26 | 2590 | |
9636f6db DG |
2591 | seq_printf(m, "Doorbell map:\n"); |
2592 | seq_printf(m, "\t%*pb\n", GUC_MAX_DOORBELLS, guc.doorbell_bitmap); | |
2593 | seq_printf(m, "Doorbell next cacheline: 0x%x\n\n", guc.db_cacheline); | |
2594 | ||
8b417c26 DG |
2595 | seq_printf(m, "GuC total action count: %llu\n", guc.action_count); |
2596 | seq_printf(m, "GuC action failure count: %u\n", guc.action_fail); | |
2597 | seq_printf(m, "GuC last action command: 0x%x\n", guc.action_cmd); | |
2598 | seq_printf(m, "GuC last action status: 0x%x\n", guc.action_status); | |
2599 | seq_printf(m, "GuC last action error code: %d\n", guc.action_err); | |
2600 | ||
2601 | seq_printf(m, "\nGuC submissions:\n"); | |
c18468c4 DG |
2602 | for_each_engine_id(engine, dev_priv, id) { |
2603 | u64 submissions = guc.submissions[id]; | |
2604 | total += submissions; | |
397097b0 | 2605 | seq_printf(m, "\t%-24s: %10llu, last seqno 0x%08x\n", |
c18468c4 | 2606 | engine->name, submissions, guc.last_seqno[id]); |
8b417c26 DG |
2607 | } |
2608 | seq_printf(m, "\t%s: %llu\n", "Total", total); | |
2609 | ||
2610 | seq_printf(m, "\nGuC execbuf client @ %p:\n", guc.execbuf_client); | |
2611 | i915_guc_client_info(m, dev_priv, &client); | |
2612 | ||
2613 | /* Add more as required ... */ | |
2614 | ||
2615 | return 0; | |
2616 | } | |
2617 | ||
4c7e77fc AD |
2618 | static int i915_guc_log_dump(struct seq_file *m, void *data) |
2619 | { | |
2620 | struct drm_info_node *node = m->private; | |
2621 | struct drm_device *dev = node->minor->dev; | |
fac5e23e | 2622 | struct drm_i915_private *dev_priv = to_i915(dev); |
4c7e77fc AD |
2623 | struct drm_i915_gem_object *log_obj = dev_priv->guc.log_obj; |
2624 | u32 *log; | |
2625 | int i = 0, pg; | |
2626 | ||
2627 | if (!log_obj) | |
2628 | return 0; | |
2629 | ||
2630 | for (pg = 0; pg < log_obj->base.size / PAGE_SIZE; pg++) { | |
2631 | log = kmap_atomic(i915_gem_object_get_page(log_obj, pg)); | |
2632 | ||
2633 | for (i = 0; i < PAGE_SIZE / sizeof(u32); i += 4) | |
2634 | seq_printf(m, "0x%08x 0x%08x 0x%08x 0x%08x\n", | |
2635 | *(log + i), *(log + i + 1), | |
2636 | *(log + i + 2), *(log + i + 3)); | |
2637 | ||
2638 | kunmap_atomic(log); | |
2639 | } | |
2640 | ||
2641 | seq_putc(m, '\n'); | |
2642 | ||
2643 | return 0; | |
2644 | } | |
2645 | ||
e91fd8c6 RV |
2646 | static int i915_edp_psr_status(struct seq_file *m, void *data) |
2647 | { | |
2648 | struct drm_info_node *node = m->private; | |
2649 | struct drm_device *dev = node->minor->dev; | |
fac5e23e | 2650 | struct drm_i915_private *dev_priv = to_i915(dev); |
a031d709 | 2651 | u32 psrperf = 0; |
a6cbdb8e RV |
2652 | u32 stat[3]; |
2653 | enum pipe pipe; | |
a031d709 | 2654 | bool enabled = false; |
e91fd8c6 | 2655 | |
3553a8ea DL |
2656 | if (!HAS_PSR(dev)) { |
2657 | seq_puts(m, "PSR not supported\n"); | |
2658 | return 0; | |
2659 | } | |
2660 | ||
c8c8fb33 PZ |
2661 | intel_runtime_pm_get(dev_priv); |
2662 | ||
fa128fa6 | 2663 | mutex_lock(&dev_priv->psr.lock); |
a031d709 RV |
2664 | seq_printf(m, "Sink_Support: %s\n", yesno(dev_priv->psr.sink_support)); |
2665 | seq_printf(m, "Source_OK: %s\n", yesno(dev_priv->psr.source_ok)); | |
2807cf69 | 2666 | seq_printf(m, "Enabled: %s\n", yesno((bool)dev_priv->psr.enabled)); |
5755c78f | 2667 | seq_printf(m, "Active: %s\n", yesno(dev_priv->psr.active)); |
fa128fa6 DV |
2668 | seq_printf(m, "Busy frontbuffer bits: 0x%03x\n", |
2669 | dev_priv->psr.busy_frontbuffer_bits); | |
2670 | seq_printf(m, "Re-enable work scheduled: %s\n", | |
2671 | yesno(work_busy(&dev_priv->psr.work.work))); | |
e91fd8c6 | 2672 | |
3553a8ea | 2673 | if (HAS_DDI(dev)) |
443a389f | 2674 | enabled = I915_READ(EDP_PSR_CTL) & EDP_PSR_ENABLE; |
3553a8ea DL |
2675 | else { |
2676 | for_each_pipe(dev_priv, pipe) { | |
2677 | stat[pipe] = I915_READ(VLV_PSRSTAT(pipe)) & | |
2678 | VLV_EDP_PSR_CURR_STATE_MASK; | |
2679 | if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) || | |
2680 | (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE)) | |
2681 | enabled = true; | |
a6cbdb8e RV |
2682 | } |
2683 | } | |
60e5ffe3 RV |
2684 | |
2685 | seq_printf(m, "Main link in standby mode: %s\n", | |
2686 | yesno(dev_priv->psr.link_standby)); | |
2687 | ||
a6cbdb8e RV |
2688 | seq_printf(m, "HW Enabled & Active bit: %s", yesno(enabled)); |
2689 | ||
2690 | if (!HAS_DDI(dev)) | |
2691 | for_each_pipe(dev_priv, pipe) { | |
2692 | if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) || | |
2693 | (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE)) | |
2694 | seq_printf(m, " pipe %c", pipe_name(pipe)); | |
2695 | } | |
2696 | seq_puts(m, "\n"); | |
e91fd8c6 | 2697 | |
05eec3c2 RV |
2698 | /* |
2699 | * VLV/CHV PSR has no kind of performance counter | |
2700 | * SKL+ Perf counter is reset to 0 everytime DC state is entered | |
2701 | */ | |
2702 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { | |
443a389f | 2703 | psrperf = I915_READ(EDP_PSR_PERF_CNT) & |
a031d709 | 2704 | EDP_PSR_PERF_CNT_MASK; |
a6cbdb8e RV |
2705 | |
2706 | seq_printf(m, "Performance_Counter: %u\n", psrperf); | |
2707 | } | |
fa128fa6 | 2708 | mutex_unlock(&dev_priv->psr.lock); |
e91fd8c6 | 2709 | |
c8c8fb33 | 2710 | intel_runtime_pm_put(dev_priv); |
e91fd8c6 RV |
2711 | return 0; |
2712 | } | |
2713 | ||
d2e216d0 RV |
2714 | static int i915_sink_crc(struct seq_file *m, void *data) |
2715 | { | |
2716 | struct drm_info_node *node = m->private; | |
2717 | struct drm_device *dev = node->minor->dev; | |
d2e216d0 RV |
2718 | struct intel_connector *connector; |
2719 | struct intel_dp *intel_dp = NULL; | |
2720 | int ret; | |
2721 | u8 crc[6]; | |
2722 | ||
2723 | drm_modeset_lock_all(dev); | |
aca5e361 | 2724 | for_each_intel_connector(dev, connector) { |
26c17cf6 | 2725 | struct drm_crtc *crtc; |
d2e216d0 | 2726 | |
26c17cf6 | 2727 | if (!connector->base.state->best_encoder) |
d2e216d0 RV |
2728 | continue; |
2729 | ||
26c17cf6 ML |
2730 | crtc = connector->base.state->crtc; |
2731 | if (!crtc->state->active) | |
b6ae3c7c PZ |
2732 | continue; |
2733 | ||
26c17cf6 | 2734 | if (connector->base.connector_type != DRM_MODE_CONNECTOR_eDP) |
d2e216d0 RV |
2735 | continue; |
2736 | ||
26c17cf6 | 2737 | intel_dp = enc_to_intel_dp(connector->base.state->best_encoder); |
d2e216d0 RV |
2738 | |
2739 | ret = intel_dp_sink_crc(intel_dp, crc); | |
2740 | if (ret) | |
2741 | goto out; | |
2742 | ||
2743 | seq_printf(m, "%02x%02x%02x%02x%02x%02x\n", | |
2744 | crc[0], crc[1], crc[2], | |
2745 | crc[3], crc[4], crc[5]); | |
2746 | goto out; | |
2747 | } | |
2748 | ret = -ENODEV; | |
2749 | out: | |
2750 | drm_modeset_unlock_all(dev); | |
2751 | return ret; | |
2752 | } | |
2753 | ||
ec013e7f JB |
2754 | static int i915_energy_uJ(struct seq_file *m, void *data) |
2755 | { | |
2756 | struct drm_info_node *node = m->private; | |
2757 | struct drm_device *dev = node->minor->dev; | |
fac5e23e | 2758 | struct drm_i915_private *dev_priv = to_i915(dev); |
ec013e7f JB |
2759 | u64 power; |
2760 | u32 units; | |
2761 | ||
2762 | if (INTEL_INFO(dev)->gen < 6) | |
2763 | return -ENODEV; | |
2764 | ||
36623ef8 PZ |
2765 | intel_runtime_pm_get(dev_priv); |
2766 | ||
ec013e7f JB |
2767 | rdmsrl(MSR_RAPL_POWER_UNIT, power); |
2768 | power = (power & 0x1f00) >> 8; | |
2769 | units = 1000000 / (1 << power); /* convert to uJ */ | |
2770 | power = I915_READ(MCH_SECP_NRG_STTS); | |
2771 | power *= units; | |
2772 | ||
36623ef8 PZ |
2773 | intel_runtime_pm_put(dev_priv); |
2774 | ||
ec013e7f | 2775 | seq_printf(m, "%llu", (long long unsigned)power); |
371db66a PZ |
2776 | |
2777 | return 0; | |
2778 | } | |
2779 | ||
6455c870 | 2780 | static int i915_runtime_pm_status(struct seq_file *m, void *unused) |
371db66a | 2781 | { |
9f25d007 | 2782 | struct drm_info_node *node = m->private; |
371db66a | 2783 | struct drm_device *dev = node->minor->dev; |
fac5e23e | 2784 | struct drm_i915_private *dev_priv = to_i915(dev); |
371db66a | 2785 | |
a156e64d CW |
2786 | if (!HAS_RUNTIME_PM(dev_priv)) |
2787 | seq_puts(m, "Runtime power management not supported\n"); | |
371db66a | 2788 | |
67d97da3 | 2789 | seq_printf(m, "GPU idle: %s\n", yesno(!dev_priv->gt.awake)); |
371db66a | 2790 | seq_printf(m, "IRQs disabled: %s\n", |
9df7575f | 2791 | yesno(!intel_irqs_enabled(dev_priv))); |
0d804184 | 2792 | #ifdef CONFIG_PM |
a6aaec8b DL |
2793 | seq_printf(m, "Usage count: %d\n", |
2794 | atomic_read(&dev->dev->power.usage_count)); | |
0d804184 CW |
2795 | #else |
2796 | seq_printf(m, "Device Power Management (CONFIG_PM) disabled\n"); | |
2797 | #endif | |
a156e64d | 2798 | seq_printf(m, "PCI device power state: %s [%d]\n", |
91c8a326 CW |
2799 | pci_power_name(dev_priv->drm.pdev->current_state), |
2800 | dev_priv->drm.pdev->current_state); | |
371db66a | 2801 | |
ec013e7f JB |
2802 | return 0; |
2803 | } | |
2804 | ||
1da51581 ID |
2805 | static int i915_power_domain_info(struct seq_file *m, void *unused) |
2806 | { | |
9f25d007 | 2807 | struct drm_info_node *node = m->private; |
1da51581 | 2808 | struct drm_device *dev = node->minor->dev; |
fac5e23e | 2809 | struct drm_i915_private *dev_priv = to_i915(dev); |
1da51581 ID |
2810 | struct i915_power_domains *power_domains = &dev_priv->power_domains; |
2811 | int i; | |
2812 | ||
2813 | mutex_lock(&power_domains->lock); | |
2814 | ||
2815 | seq_printf(m, "%-25s %s\n", "Power well/domain", "Use count"); | |
2816 | for (i = 0; i < power_domains->power_well_count; i++) { | |
2817 | struct i915_power_well *power_well; | |
2818 | enum intel_display_power_domain power_domain; | |
2819 | ||
2820 | power_well = &power_domains->power_wells[i]; | |
2821 | seq_printf(m, "%-25s %d\n", power_well->name, | |
2822 | power_well->count); | |
2823 | ||
2824 | for (power_domain = 0; power_domain < POWER_DOMAIN_NUM; | |
2825 | power_domain++) { | |
2826 | if (!(BIT(power_domain) & power_well->domains)) | |
2827 | continue; | |
2828 | ||
2829 | seq_printf(m, " %-23s %d\n", | |
9895ad03 | 2830 | intel_display_power_domain_str(power_domain), |
1da51581 ID |
2831 | power_domains->domain_use_count[power_domain]); |
2832 | } | |
2833 | } | |
2834 | ||
2835 | mutex_unlock(&power_domains->lock); | |
2836 | ||
2837 | return 0; | |
2838 | } | |
2839 | ||
b7cec66d DL |
2840 | static int i915_dmc_info(struct seq_file *m, void *unused) |
2841 | { | |
2842 | struct drm_info_node *node = m->private; | |
2843 | struct drm_device *dev = node->minor->dev; | |
fac5e23e | 2844 | struct drm_i915_private *dev_priv = to_i915(dev); |
b7cec66d DL |
2845 | struct intel_csr *csr; |
2846 | ||
2847 | if (!HAS_CSR(dev)) { | |
2848 | seq_puts(m, "not supported\n"); | |
2849 | return 0; | |
2850 | } | |
2851 | ||
2852 | csr = &dev_priv->csr; | |
2853 | ||
6fb403de MK |
2854 | intel_runtime_pm_get(dev_priv); |
2855 | ||
b7cec66d DL |
2856 | seq_printf(m, "fw loaded: %s\n", yesno(csr->dmc_payload != NULL)); |
2857 | seq_printf(m, "path: %s\n", csr->fw_path); | |
2858 | ||
2859 | if (!csr->dmc_payload) | |
6fb403de | 2860 | goto out; |
b7cec66d DL |
2861 | |
2862 | seq_printf(m, "version: %d.%d\n", CSR_VERSION_MAJOR(csr->version), | |
2863 | CSR_VERSION_MINOR(csr->version)); | |
2864 | ||
8337206d DL |
2865 | if (IS_SKYLAKE(dev) && csr->version >= CSR_VERSION(1, 6)) { |
2866 | seq_printf(m, "DC3 -> DC5 count: %d\n", | |
2867 | I915_READ(SKL_CSR_DC3_DC5_COUNT)); | |
2868 | seq_printf(m, "DC5 -> DC6 count: %d\n", | |
2869 | I915_READ(SKL_CSR_DC5_DC6_COUNT)); | |
16e11b99 MK |
2870 | } else if (IS_BROXTON(dev) && csr->version >= CSR_VERSION(1, 4)) { |
2871 | seq_printf(m, "DC3 -> DC5 count: %d\n", | |
2872 | I915_READ(BXT_CSR_DC3_DC5_COUNT)); | |
8337206d DL |
2873 | } |
2874 | ||
6fb403de MK |
2875 | out: |
2876 | seq_printf(m, "program base: 0x%08x\n", I915_READ(CSR_PROGRAM(0))); | |
2877 | seq_printf(m, "ssp base: 0x%08x\n", I915_READ(CSR_SSP_BASE)); | |
2878 | seq_printf(m, "htp: 0x%08x\n", I915_READ(CSR_HTP_SKL)); | |
2879 | ||
8337206d DL |
2880 | intel_runtime_pm_put(dev_priv); |
2881 | ||
b7cec66d DL |
2882 | return 0; |
2883 | } | |
2884 | ||
53f5e3ca JB |
2885 | static void intel_seq_print_mode(struct seq_file *m, int tabs, |
2886 | struct drm_display_mode *mode) | |
2887 | { | |
2888 | int i; | |
2889 | ||
2890 | for (i = 0; i < tabs; i++) | |
2891 | seq_putc(m, '\t'); | |
2892 | ||
2893 | seq_printf(m, "id %d:\"%s\" freq %d clock %d hdisp %d hss %d hse %d htot %d vdisp %d vss %d vse %d vtot %d type 0x%x flags 0x%x\n", | |
2894 | mode->base.id, mode->name, | |
2895 | mode->vrefresh, mode->clock, | |
2896 | mode->hdisplay, mode->hsync_start, | |
2897 | mode->hsync_end, mode->htotal, | |
2898 | mode->vdisplay, mode->vsync_start, | |
2899 | mode->vsync_end, mode->vtotal, | |
2900 | mode->type, mode->flags); | |
2901 | } | |
2902 | ||
2903 | static void intel_encoder_info(struct seq_file *m, | |
2904 | struct intel_crtc *intel_crtc, | |
2905 | struct intel_encoder *intel_encoder) | |
2906 | { | |
9f25d007 | 2907 | struct drm_info_node *node = m->private; |
53f5e3ca JB |
2908 | struct drm_device *dev = node->minor->dev; |
2909 | struct drm_crtc *crtc = &intel_crtc->base; | |
2910 | struct intel_connector *intel_connector; | |
2911 | struct drm_encoder *encoder; | |
2912 | ||
2913 | encoder = &intel_encoder->base; | |
2914 | seq_printf(m, "\tencoder %d: type: %s, connectors:\n", | |
8e329a03 | 2915 | encoder->base.id, encoder->name); |
53f5e3ca JB |
2916 | for_each_connector_on_encoder(dev, encoder, intel_connector) { |
2917 | struct drm_connector *connector = &intel_connector->base; | |
2918 | seq_printf(m, "\t\tconnector %d: type: %s, status: %s", | |
2919 | connector->base.id, | |
c23cc417 | 2920 | connector->name, |
53f5e3ca JB |
2921 | drm_get_connector_status_name(connector->status)); |
2922 | if (connector->status == connector_status_connected) { | |
2923 | struct drm_display_mode *mode = &crtc->mode; | |
2924 | seq_printf(m, ", mode:\n"); | |
2925 | intel_seq_print_mode(m, 2, mode); | |
2926 | } else { | |
2927 | seq_putc(m, '\n'); | |
2928 | } | |
2929 | } | |
2930 | } | |
2931 | ||
2932 | static void intel_crtc_info(struct seq_file *m, struct intel_crtc *intel_crtc) | |
2933 | { | |
9f25d007 | 2934 | struct drm_info_node *node = m->private; |
53f5e3ca JB |
2935 | struct drm_device *dev = node->minor->dev; |
2936 | struct drm_crtc *crtc = &intel_crtc->base; | |
2937 | struct intel_encoder *intel_encoder; | |
23a48d53 ML |
2938 | struct drm_plane_state *plane_state = crtc->primary->state; |
2939 | struct drm_framebuffer *fb = plane_state->fb; | |
53f5e3ca | 2940 | |
23a48d53 | 2941 | if (fb) |
5aa8a937 | 2942 | seq_printf(m, "\tfb: %d, pos: %dx%d, size: %dx%d\n", |
23a48d53 ML |
2943 | fb->base.id, plane_state->src_x >> 16, |
2944 | plane_state->src_y >> 16, fb->width, fb->height); | |
5aa8a937 MR |
2945 | else |
2946 | seq_puts(m, "\tprimary plane disabled\n"); | |
53f5e3ca JB |
2947 | for_each_encoder_on_crtc(dev, crtc, intel_encoder) |
2948 | intel_encoder_info(m, intel_crtc, intel_encoder); | |
2949 | } | |
2950 | ||
2951 | static void intel_panel_info(struct seq_file *m, struct intel_panel *panel) | |
2952 | { | |
2953 | struct drm_display_mode *mode = panel->fixed_mode; | |
2954 | ||
2955 | seq_printf(m, "\tfixed mode:\n"); | |
2956 | intel_seq_print_mode(m, 2, mode); | |
2957 | } | |
2958 | ||
2959 | static void intel_dp_info(struct seq_file *m, | |
2960 | struct intel_connector *intel_connector) | |
2961 | { | |
2962 | struct intel_encoder *intel_encoder = intel_connector->encoder; | |
2963 | struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base); | |
2964 | ||
2965 | seq_printf(m, "\tDPCD rev: %x\n", intel_dp->dpcd[DP_DPCD_REV]); | |
742f491d | 2966 | seq_printf(m, "\taudio support: %s\n", yesno(intel_dp->has_audio)); |
b6dabe3b | 2967 | if (intel_connector->base.connector_type == DRM_MODE_CONNECTOR_eDP) |
53f5e3ca JB |
2968 | intel_panel_info(m, &intel_connector->panel); |
2969 | } | |
2970 | ||
2971 | static void intel_hdmi_info(struct seq_file *m, | |
2972 | struct intel_connector *intel_connector) | |
2973 | { | |
2974 | struct intel_encoder *intel_encoder = intel_connector->encoder; | |
2975 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&intel_encoder->base); | |
2976 | ||
742f491d | 2977 | seq_printf(m, "\taudio support: %s\n", yesno(intel_hdmi->has_audio)); |
53f5e3ca JB |
2978 | } |
2979 | ||
2980 | static void intel_lvds_info(struct seq_file *m, | |
2981 | struct intel_connector *intel_connector) | |
2982 | { | |
2983 | intel_panel_info(m, &intel_connector->panel); | |
2984 | } | |
2985 | ||
2986 | static void intel_connector_info(struct seq_file *m, | |
2987 | struct drm_connector *connector) | |
2988 | { | |
2989 | struct intel_connector *intel_connector = to_intel_connector(connector); | |
2990 | struct intel_encoder *intel_encoder = intel_connector->encoder; | |
f103fc7d | 2991 | struct drm_display_mode *mode; |
53f5e3ca JB |
2992 | |
2993 | seq_printf(m, "connector %d: type %s, status: %s\n", | |
c23cc417 | 2994 | connector->base.id, connector->name, |
53f5e3ca JB |
2995 | drm_get_connector_status_name(connector->status)); |
2996 | if (connector->status == connector_status_connected) { | |
2997 | seq_printf(m, "\tname: %s\n", connector->display_info.name); | |
2998 | seq_printf(m, "\tphysical dimensions: %dx%dmm\n", | |
2999 | connector->display_info.width_mm, | |
3000 | connector->display_info.height_mm); | |
3001 | seq_printf(m, "\tsubpixel order: %s\n", | |
3002 | drm_get_subpixel_order_name(connector->display_info.subpixel_order)); | |
3003 | seq_printf(m, "\tCEA rev: %d\n", | |
3004 | connector->display_info.cea_rev); | |
3005 | } | |
ee648a74 ML |
3006 | |
3007 | if (!intel_encoder || intel_encoder->type == INTEL_OUTPUT_DP_MST) | |
3008 | return; | |
3009 | ||
3010 | switch (connector->connector_type) { | |
3011 | case DRM_MODE_CONNECTOR_DisplayPort: | |
3012 | case DRM_MODE_CONNECTOR_eDP: | |
3013 | intel_dp_info(m, intel_connector); | |
3014 | break; | |
3015 | case DRM_MODE_CONNECTOR_LVDS: | |
3016 | if (intel_encoder->type == INTEL_OUTPUT_LVDS) | |
36cd7444 | 3017 | intel_lvds_info(m, intel_connector); |
ee648a74 ML |
3018 | break; |
3019 | case DRM_MODE_CONNECTOR_HDMIA: | |
3020 | if (intel_encoder->type == INTEL_OUTPUT_HDMI || | |
3021 | intel_encoder->type == INTEL_OUTPUT_UNKNOWN) | |
3022 | intel_hdmi_info(m, intel_connector); | |
3023 | break; | |
3024 | default: | |
3025 | break; | |
36cd7444 | 3026 | } |
53f5e3ca | 3027 | |
f103fc7d JB |
3028 | seq_printf(m, "\tmodes:\n"); |
3029 | list_for_each_entry(mode, &connector->modes, head) | |
3030 | intel_seq_print_mode(m, 2, mode); | |
53f5e3ca JB |
3031 | } |
3032 | ||
065f2ec2 CW |
3033 | static bool cursor_active(struct drm_device *dev, int pipe) |
3034 | { | |
fac5e23e | 3035 | struct drm_i915_private *dev_priv = to_i915(dev); |
065f2ec2 CW |
3036 | u32 state; |
3037 | ||
3038 | if (IS_845G(dev) || IS_I865G(dev)) | |
0b87c24e | 3039 | state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE; |
065f2ec2 | 3040 | else |
5efb3e28 | 3041 | state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE; |
065f2ec2 CW |
3042 | |
3043 | return state; | |
3044 | } | |
3045 | ||
3046 | static bool cursor_position(struct drm_device *dev, int pipe, int *x, int *y) | |
3047 | { | |
fac5e23e | 3048 | struct drm_i915_private *dev_priv = to_i915(dev); |
065f2ec2 CW |
3049 | u32 pos; |
3050 | ||
5efb3e28 | 3051 | pos = I915_READ(CURPOS(pipe)); |
065f2ec2 CW |
3052 | |
3053 | *x = (pos >> CURSOR_X_SHIFT) & CURSOR_POS_MASK; | |
3054 | if (pos & (CURSOR_POS_SIGN << CURSOR_X_SHIFT)) | |
3055 | *x = -*x; | |
3056 | ||
3057 | *y = (pos >> CURSOR_Y_SHIFT) & CURSOR_POS_MASK; | |
3058 | if (pos & (CURSOR_POS_SIGN << CURSOR_Y_SHIFT)) | |
3059 | *y = -*y; | |
3060 | ||
3061 | return cursor_active(dev, pipe); | |
3062 | } | |
3063 | ||
3abc4e09 RF |
3064 | static const char *plane_type(enum drm_plane_type type) |
3065 | { | |
3066 | switch (type) { | |
3067 | case DRM_PLANE_TYPE_OVERLAY: | |
3068 | return "OVL"; | |
3069 | case DRM_PLANE_TYPE_PRIMARY: | |
3070 | return "PRI"; | |
3071 | case DRM_PLANE_TYPE_CURSOR: | |
3072 | return "CUR"; | |
3073 | /* | |
3074 | * Deliberately omitting default: to generate compiler warnings | |
3075 | * when a new drm_plane_type gets added. | |
3076 | */ | |
3077 | } | |
3078 | ||
3079 | return "unknown"; | |
3080 | } | |
3081 | ||
3082 | static const char *plane_rotation(unsigned int rotation) | |
3083 | { | |
3084 | static char buf[48]; | |
3085 | /* | |
3086 | * According to doc only one DRM_ROTATE_ is allowed but this | |
3087 | * will print them all to visualize if the values are misused | |
3088 | */ | |
3089 | snprintf(buf, sizeof(buf), | |
3090 | "%s%s%s%s%s%s(0x%08x)", | |
31ad61e4 JL |
3091 | (rotation & DRM_ROTATE_0) ? "0 " : "", |
3092 | (rotation & DRM_ROTATE_90) ? "90 " : "", | |
3093 | (rotation & DRM_ROTATE_180) ? "180 " : "", | |
3094 | (rotation & DRM_ROTATE_270) ? "270 " : "", | |
3095 | (rotation & DRM_REFLECT_X) ? "FLIPX " : "", | |
3096 | (rotation & DRM_REFLECT_Y) ? "FLIPY " : "", | |
3abc4e09 RF |
3097 | rotation); |
3098 | ||
3099 | return buf; | |
3100 | } | |
3101 | ||
3102 | static void intel_plane_info(struct seq_file *m, struct intel_crtc *intel_crtc) | |
3103 | { | |
3104 | struct drm_info_node *node = m->private; | |
3105 | struct drm_device *dev = node->minor->dev; | |
3106 | struct intel_plane *intel_plane; | |
3107 | ||
3108 | for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) { | |
3109 | struct drm_plane_state *state; | |
3110 | struct drm_plane *plane = &intel_plane->base; | |
3111 | ||
3112 | if (!plane->state) { | |
3113 | seq_puts(m, "plane->state is NULL!\n"); | |
3114 | continue; | |
3115 | } | |
3116 | ||
3117 | state = plane->state; | |
3118 | ||
3119 | seq_printf(m, "\t--Plane id %d: type=%s, crtc_pos=%4dx%4d, crtc_size=%4dx%4d, src_pos=%d.%04ux%d.%04u, src_size=%d.%04ux%d.%04u, format=%s, rotation=%s\n", | |
3120 | plane->base.id, | |
3121 | plane_type(intel_plane->base.type), | |
3122 | state->crtc_x, state->crtc_y, | |
3123 | state->crtc_w, state->crtc_h, | |
3124 | (state->src_x >> 16), | |
3125 | ((state->src_x & 0xffff) * 15625) >> 10, | |
3126 | (state->src_y >> 16), | |
3127 | ((state->src_y & 0xffff) * 15625) >> 10, | |
3128 | (state->src_w >> 16), | |
3129 | ((state->src_w & 0xffff) * 15625) >> 10, | |
3130 | (state->src_h >> 16), | |
3131 | ((state->src_h & 0xffff) * 15625) >> 10, | |
3132 | state->fb ? drm_get_format_name(state->fb->pixel_format) : "N/A", | |
3133 | plane_rotation(state->rotation)); | |
3134 | } | |
3135 | } | |
3136 | ||
3137 | static void intel_scaler_info(struct seq_file *m, struct intel_crtc *intel_crtc) | |
3138 | { | |
3139 | struct intel_crtc_state *pipe_config; | |
3140 | int num_scalers = intel_crtc->num_scalers; | |
3141 | int i; | |
3142 | ||
3143 | pipe_config = to_intel_crtc_state(intel_crtc->base.state); | |
3144 | ||
3145 | /* Not all platformas have a scaler */ | |
3146 | if (num_scalers) { | |
3147 | seq_printf(m, "\tnum_scalers=%d, scaler_users=%x scaler_id=%d", | |
3148 | num_scalers, | |
3149 | pipe_config->scaler_state.scaler_users, | |
3150 | pipe_config->scaler_state.scaler_id); | |
3151 | ||
3152 | for (i = 0; i < SKL_NUM_SCALERS; i++) { | |
3153 | struct intel_scaler *sc = | |
3154 | &pipe_config->scaler_state.scalers[i]; | |
3155 | ||
3156 | seq_printf(m, ", scalers[%d]: use=%s, mode=%x", | |
3157 | i, yesno(sc->in_use), sc->mode); | |
3158 | } | |
3159 | seq_puts(m, "\n"); | |
3160 | } else { | |
3161 | seq_puts(m, "\tNo scalers available on this platform\n"); | |
3162 | } | |
3163 | } | |
3164 | ||
53f5e3ca JB |
3165 | static int i915_display_info(struct seq_file *m, void *unused) |
3166 | { | |
9f25d007 | 3167 | struct drm_info_node *node = m->private; |
53f5e3ca | 3168 | struct drm_device *dev = node->minor->dev; |
fac5e23e | 3169 | struct drm_i915_private *dev_priv = to_i915(dev); |
065f2ec2 | 3170 | struct intel_crtc *crtc; |
53f5e3ca JB |
3171 | struct drm_connector *connector; |
3172 | ||
b0e5ddf3 | 3173 | intel_runtime_pm_get(dev_priv); |
53f5e3ca JB |
3174 | drm_modeset_lock_all(dev); |
3175 | seq_printf(m, "CRTC info\n"); | |
3176 | seq_printf(m, "---------\n"); | |
d3fcc808 | 3177 | for_each_intel_crtc(dev, crtc) { |
065f2ec2 | 3178 | bool active; |
f77076c9 | 3179 | struct intel_crtc_state *pipe_config; |
065f2ec2 | 3180 | int x, y; |
53f5e3ca | 3181 | |
f77076c9 ML |
3182 | pipe_config = to_intel_crtc_state(crtc->base.state); |
3183 | ||
3abc4e09 | 3184 | seq_printf(m, "CRTC %d: pipe: %c, active=%s, (size=%dx%d), dither=%s, bpp=%d\n", |
065f2ec2 | 3185 | crtc->base.base.id, pipe_name(crtc->pipe), |
f77076c9 | 3186 | yesno(pipe_config->base.active), |
3abc4e09 RF |
3187 | pipe_config->pipe_src_w, pipe_config->pipe_src_h, |
3188 | yesno(pipe_config->dither), pipe_config->pipe_bpp); | |
3189 | ||
f77076c9 | 3190 | if (pipe_config->base.active) { |
065f2ec2 CW |
3191 | intel_crtc_info(m, crtc); |
3192 | ||
a23dc658 | 3193 | active = cursor_position(dev, crtc->pipe, &x, &y); |
57127efa | 3194 | seq_printf(m, "\tcursor visible? %s, position (%d, %d), size %dx%d, addr 0x%08x, active? %s\n", |
4b0e333e | 3195 | yesno(crtc->cursor_base), |
3dd512fb MR |
3196 | x, y, crtc->base.cursor->state->crtc_w, |
3197 | crtc->base.cursor->state->crtc_h, | |
57127efa | 3198 | crtc->cursor_addr, yesno(active)); |
3abc4e09 RF |
3199 | intel_scaler_info(m, crtc); |
3200 | intel_plane_info(m, crtc); | |
a23dc658 | 3201 | } |
cace841c DV |
3202 | |
3203 | seq_printf(m, "\tunderrun reporting: cpu=%s pch=%s \n", | |
3204 | yesno(!crtc->cpu_fifo_underrun_disabled), | |
3205 | yesno(!crtc->pch_fifo_underrun_disabled)); | |
53f5e3ca JB |
3206 | } |
3207 | ||
3208 | seq_printf(m, "\n"); | |
3209 | seq_printf(m, "Connector info\n"); | |
3210 | seq_printf(m, "--------------\n"); | |
3211 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
3212 | intel_connector_info(m, connector); | |
3213 | } | |
3214 | drm_modeset_unlock_all(dev); | |
b0e5ddf3 | 3215 | intel_runtime_pm_put(dev_priv); |
53f5e3ca JB |
3216 | |
3217 | return 0; | |
3218 | } | |
3219 | ||
e04934cf BW |
3220 | static int i915_semaphore_status(struct seq_file *m, void *unused) |
3221 | { | |
3222 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
3223 | struct drm_device *dev = node->minor->dev; | |
fac5e23e | 3224 | struct drm_i915_private *dev_priv = to_i915(dev); |
e2f80391 | 3225 | struct intel_engine_cs *engine; |
c1bb1145 | 3226 | int num_rings = INTEL_INFO(dev)->num_rings; |
c3232b18 DG |
3227 | enum intel_engine_id id; |
3228 | int j, ret; | |
e04934cf | 3229 | |
39df9190 | 3230 | if (!i915.semaphores) { |
e04934cf BW |
3231 | seq_puts(m, "Semaphores are disabled\n"); |
3232 | return 0; | |
3233 | } | |
3234 | ||
3235 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
3236 | if (ret) | |
3237 | return ret; | |
03872064 | 3238 | intel_runtime_pm_get(dev_priv); |
e04934cf BW |
3239 | |
3240 | if (IS_BROADWELL(dev)) { | |
3241 | struct page *page; | |
3242 | uint64_t *seqno; | |
3243 | ||
3244 | page = i915_gem_object_get_page(dev_priv->semaphore_obj, 0); | |
3245 | ||
3246 | seqno = (uint64_t *)kmap_atomic(page); | |
c3232b18 | 3247 | for_each_engine_id(engine, dev_priv, id) { |
e04934cf BW |
3248 | uint64_t offset; |
3249 | ||
e2f80391 | 3250 | seq_printf(m, "%s\n", engine->name); |
e04934cf BW |
3251 | |
3252 | seq_puts(m, " Last signal:"); | |
3253 | for (j = 0; j < num_rings; j++) { | |
c3232b18 | 3254 | offset = id * I915_NUM_ENGINES + j; |
e04934cf BW |
3255 | seq_printf(m, "0x%08llx (0x%02llx) ", |
3256 | seqno[offset], offset * 8); | |
3257 | } | |
3258 | seq_putc(m, '\n'); | |
3259 | ||
3260 | seq_puts(m, " Last wait: "); | |
3261 | for (j = 0; j < num_rings; j++) { | |
c3232b18 | 3262 | offset = id + (j * I915_NUM_ENGINES); |
e04934cf BW |
3263 | seq_printf(m, "0x%08llx (0x%02llx) ", |
3264 | seqno[offset], offset * 8); | |
3265 | } | |
3266 | seq_putc(m, '\n'); | |
3267 | ||
3268 | } | |
3269 | kunmap_atomic(seqno); | |
3270 | } else { | |
3271 | seq_puts(m, " Last signal:"); | |
b4ac5afc | 3272 | for_each_engine(engine, dev_priv) |
e04934cf BW |
3273 | for (j = 0; j < num_rings; j++) |
3274 | seq_printf(m, "0x%08x\n", | |
e2f80391 | 3275 | I915_READ(engine->semaphore.mbox.signal[j])); |
e04934cf BW |
3276 | seq_putc(m, '\n'); |
3277 | } | |
3278 | ||
3279 | seq_puts(m, "\nSync seqno:\n"); | |
b4ac5afc DG |
3280 | for_each_engine(engine, dev_priv) { |
3281 | for (j = 0; j < num_rings; j++) | |
e2f80391 TU |
3282 | seq_printf(m, " 0x%08x ", |
3283 | engine->semaphore.sync_seqno[j]); | |
e04934cf BW |
3284 | seq_putc(m, '\n'); |
3285 | } | |
3286 | seq_putc(m, '\n'); | |
3287 | ||
03872064 | 3288 | intel_runtime_pm_put(dev_priv); |
e04934cf BW |
3289 | mutex_unlock(&dev->struct_mutex); |
3290 | return 0; | |
3291 | } | |
3292 | ||
728e29d7 DV |
3293 | static int i915_shared_dplls_info(struct seq_file *m, void *unused) |
3294 | { | |
3295 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
3296 | struct drm_device *dev = node->minor->dev; | |
fac5e23e | 3297 | struct drm_i915_private *dev_priv = to_i915(dev); |
728e29d7 DV |
3298 | int i; |
3299 | ||
3300 | drm_modeset_lock_all(dev); | |
3301 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { | |
3302 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; | |
3303 | ||
3304 | seq_printf(m, "DPLL%i: %s, id: %i\n", i, pll->name, pll->id); | |
2dd66ebd ML |
3305 | seq_printf(m, " crtc_mask: 0x%08x, active: 0x%x, on: %s\n", |
3306 | pll->config.crtc_mask, pll->active_mask, yesno(pll->on)); | |
728e29d7 | 3307 | seq_printf(m, " tracked hardware state:\n"); |
3e369b76 ACO |
3308 | seq_printf(m, " dpll: 0x%08x\n", pll->config.hw_state.dpll); |
3309 | seq_printf(m, " dpll_md: 0x%08x\n", | |
3310 | pll->config.hw_state.dpll_md); | |
3311 | seq_printf(m, " fp0: 0x%08x\n", pll->config.hw_state.fp0); | |
3312 | seq_printf(m, " fp1: 0x%08x\n", pll->config.hw_state.fp1); | |
3313 | seq_printf(m, " wrpll: 0x%08x\n", pll->config.hw_state.wrpll); | |
728e29d7 DV |
3314 | } |
3315 | drm_modeset_unlock_all(dev); | |
3316 | ||
3317 | return 0; | |
3318 | } | |
3319 | ||
1ed1ef9d | 3320 | static int i915_wa_registers(struct seq_file *m, void *unused) |
888b5995 AS |
3321 | { |
3322 | int i; | |
3323 | int ret; | |
e2f80391 | 3324 | struct intel_engine_cs *engine; |
888b5995 AS |
3325 | struct drm_info_node *node = (struct drm_info_node *) m->private; |
3326 | struct drm_device *dev = node->minor->dev; | |
fac5e23e | 3327 | struct drm_i915_private *dev_priv = to_i915(dev); |
33136b06 | 3328 | struct i915_workarounds *workarounds = &dev_priv->workarounds; |
c3232b18 | 3329 | enum intel_engine_id id; |
888b5995 | 3330 | |
888b5995 AS |
3331 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
3332 | if (ret) | |
3333 | return ret; | |
3334 | ||
3335 | intel_runtime_pm_get(dev_priv); | |
3336 | ||
33136b06 | 3337 | seq_printf(m, "Workarounds applied: %d\n", workarounds->count); |
c3232b18 | 3338 | for_each_engine_id(engine, dev_priv, id) |
33136b06 | 3339 | seq_printf(m, "HW whitelist count for %s: %d\n", |
c3232b18 | 3340 | engine->name, workarounds->hw_whitelist_count[id]); |
33136b06 | 3341 | for (i = 0; i < workarounds->count; ++i) { |
f0f59a00 VS |
3342 | i915_reg_t addr; |
3343 | u32 mask, value, read; | |
2fa60f6d | 3344 | bool ok; |
888b5995 | 3345 | |
33136b06 AS |
3346 | addr = workarounds->reg[i].addr; |
3347 | mask = workarounds->reg[i].mask; | |
3348 | value = workarounds->reg[i].value; | |
2fa60f6d MK |
3349 | read = I915_READ(addr); |
3350 | ok = (value & mask) == (read & mask); | |
3351 | seq_printf(m, "0x%X: 0x%08X, mask: 0x%08X, read: 0x%08x, status: %s\n", | |
f0f59a00 | 3352 | i915_mmio_reg_offset(addr), value, mask, read, ok ? "OK" : "FAIL"); |
888b5995 AS |
3353 | } |
3354 | ||
3355 | intel_runtime_pm_put(dev_priv); | |
3356 | mutex_unlock(&dev->struct_mutex); | |
3357 | ||
3358 | return 0; | |
3359 | } | |
3360 | ||
c5511e44 DL |
3361 | static int i915_ddb_info(struct seq_file *m, void *unused) |
3362 | { | |
3363 | struct drm_info_node *node = m->private; | |
3364 | struct drm_device *dev = node->minor->dev; | |
fac5e23e | 3365 | struct drm_i915_private *dev_priv = to_i915(dev); |
c5511e44 DL |
3366 | struct skl_ddb_allocation *ddb; |
3367 | struct skl_ddb_entry *entry; | |
3368 | enum pipe pipe; | |
3369 | int plane; | |
3370 | ||
2fcffe19 DL |
3371 | if (INTEL_INFO(dev)->gen < 9) |
3372 | return 0; | |
3373 | ||
c5511e44 DL |
3374 | drm_modeset_lock_all(dev); |
3375 | ||
3376 | ddb = &dev_priv->wm.skl_hw.ddb; | |
3377 | ||
3378 | seq_printf(m, "%-15s%8s%8s%8s\n", "", "Start", "End", "Size"); | |
3379 | ||
3380 | for_each_pipe(dev_priv, pipe) { | |
3381 | seq_printf(m, "Pipe %c\n", pipe_name(pipe)); | |
3382 | ||
dd740780 | 3383 | for_each_plane(dev_priv, pipe, plane) { |
c5511e44 DL |
3384 | entry = &ddb->plane[pipe][plane]; |
3385 | seq_printf(m, " Plane%-8d%8u%8u%8u\n", plane + 1, | |
3386 | entry->start, entry->end, | |
3387 | skl_ddb_entry_size(entry)); | |
3388 | } | |
3389 | ||
4969d33e | 3390 | entry = &ddb->plane[pipe][PLANE_CURSOR]; |
c5511e44 DL |
3391 | seq_printf(m, " %-13s%8u%8u%8u\n", "Cursor", entry->start, |
3392 | entry->end, skl_ddb_entry_size(entry)); | |
3393 | } | |
3394 | ||
3395 | drm_modeset_unlock_all(dev); | |
3396 | ||
3397 | return 0; | |
3398 | } | |
3399 | ||
a54746e3 VK |
3400 | static void drrs_status_per_crtc(struct seq_file *m, |
3401 | struct drm_device *dev, struct intel_crtc *intel_crtc) | |
3402 | { | |
fac5e23e | 3403 | struct drm_i915_private *dev_priv = to_i915(dev); |
a54746e3 VK |
3404 | struct i915_drrs *drrs = &dev_priv->drrs; |
3405 | int vrefresh = 0; | |
26875fe5 | 3406 | struct drm_connector *connector; |
a54746e3 | 3407 | |
26875fe5 ML |
3408 | drm_for_each_connector(connector, dev) { |
3409 | if (connector->state->crtc != &intel_crtc->base) | |
3410 | continue; | |
3411 | ||
3412 | seq_printf(m, "%s:\n", connector->name); | |
a54746e3 VK |
3413 | } |
3414 | ||
3415 | if (dev_priv->vbt.drrs_type == STATIC_DRRS_SUPPORT) | |
3416 | seq_puts(m, "\tVBT: DRRS_type: Static"); | |
3417 | else if (dev_priv->vbt.drrs_type == SEAMLESS_DRRS_SUPPORT) | |
3418 | seq_puts(m, "\tVBT: DRRS_type: Seamless"); | |
3419 | else if (dev_priv->vbt.drrs_type == DRRS_NOT_SUPPORTED) | |
3420 | seq_puts(m, "\tVBT: DRRS_type: None"); | |
3421 | else | |
3422 | seq_puts(m, "\tVBT: DRRS_type: FIXME: Unrecognized Value"); | |
3423 | ||
3424 | seq_puts(m, "\n\n"); | |
3425 | ||
f77076c9 | 3426 | if (to_intel_crtc_state(intel_crtc->base.state)->has_drrs) { |
a54746e3 VK |
3427 | struct intel_panel *panel; |
3428 | ||
3429 | mutex_lock(&drrs->mutex); | |
3430 | /* DRRS Supported */ | |
3431 | seq_puts(m, "\tDRRS Supported: Yes\n"); | |
3432 | ||
3433 | /* disable_drrs() will make drrs->dp NULL */ | |
3434 | if (!drrs->dp) { | |
3435 | seq_puts(m, "Idleness DRRS: Disabled"); | |
3436 | mutex_unlock(&drrs->mutex); | |
3437 | return; | |
3438 | } | |
3439 | ||
3440 | panel = &drrs->dp->attached_connector->panel; | |
3441 | seq_printf(m, "\t\tBusy_frontbuffer_bits: 0x%X", | |
3442 | drrs->busy_frontbuffer_bits); | |
3443 | ||
3444 | seq_puts(m, "\n\t\t"); | |
3445 | if (drrs->refresh_rate_type == DRRS_HIGH_RR) { | |
3446 | seq_puts(m, "DRRS_State: DRRS_HIGH_RR\n"); | |
3447 | vrefresh = panel->fixed_mode->vrefresh; | |
3448 | } else if (drrs->refresh_rate_type == DRRS_LOW_RR) { | |
3449 | seq_puts(m, "DRRS_State: DRRS_LOW_RR\n"); | |
3450 | vrefresh = panel->downclock_mode->vrefresh; | |
3451 | } else { | |
3452 | seq_printf(m, "DRRS_State: Unknown(%d)\n", | |
3453 | drrs->refresh_rate_type); | |
3454 | mutex_unlock(&drrs->mutex); | |
3455 | return; | |
3456 | } | |
3457 | seq_printf(m, "\t\tVrefresh: %d", vrefresh); | |
3458 | ||
3459 | seq_puts(m, "\n\t\t"); | |
3460 | mutex_unlock(&drrs->mutex); | |
3461 | } else { | |
3462 | /* DRRS not supported. Print the VBT parameter*/ | |
3463 | seq_puts(m, "\tDRRS Supported : No"); | |
3464 | } | |
3465 | seq_puts(m, "\n"); | |
3466 | } | |
3467 | ||
3468 | static int i915_drrs_status(struct seq_file *m, void *unused) | |
3469 | { | |
3470 | struct drm_info_node *node = m->private; | |
3471 | struct drm_device *dev = node->minor->dev; | |
3472 | struct intel_crtc *intel_crtc; | |
3473 | int active_crtc_cnt = 0; | |
3474 | ||
26875fe5 | 3475 | drm_modeset_lock_all(dev); |
a54746e3 | 3476 | for_each_intel_crtc(dev, intel_crtc) { |
f77076c9 | 3477 | if (intel_crtc->base.state->active) { |
a54746e3 VK |
3478 | active_crtc_cnt++; |
3479 | seq_printf(m, "\nCRTC %d: ", active_crtc_cnt); | |
3480 | ||
3481 | drrs_status_per_crtc(m, dev, intel_crtc); | |
3482 | } | |
a54746e3 | 3483 | } |
26875fe5 | 3484 | drm_modeset_unlock_all(dev); |
a54746e3 VK |
3485 | |
3486 | if (!active_crtc_cnt) | |
3487 | seq_puts(m, "No active crtc found\n"); | |
3488 | ||
3489 | return 0; | |
3490 | } | |
3491 | ||
07144428 DL |
3492 | struct pipe_crc_info { |
3493 | const char *name; | |
3494 | struct drm_device *dev; | |
3495 | enum pipe pipe; | |
3496 | }; | |
3497 | ||
11bed958 DA |
3498 | static int i915_dp_mst_info(struct seq_file *m, void *unused) |
3499 | { | |
3500 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
3501 | struct drm_device *dev = node->minor->dev; | |
11bed958 DA |
3502 | struct intel_encoder *intel_encoder; |
3503 | struct intel_digital_port *intel_dig_port; | |
b6dabe3b ML |
3504 | struct drm_connector *connector; |
3505 | ||
11bed958 | 3506 | drm_modeset_lock_all(dev); |
b6dabe3b ML |
3507 | drm_for_each_connector(connector, dev) { |
3508 | if (connector->connector_type != DRM_MODE_CONNECTOR_DisplayPort) | |
11bed958 | 3509 | continue; |
b6dabe3b ML |
3510 | |
3511 | intel_encoder = intel_attached_encoder(connector); | |
3512 | if (!intel_encoder || intel_encoder->type == INTEL_OUTPUT_DP_MST) | |
3513 | continue; | |
3514 | ||
3515 | intel_dig_port = enc_to_dig_port(&intel_encoder->base); | |
11bed958 DA |
3516 | if (!intel_dig_port->dp.can_mst) |
3517 | continue; | |
b6dabe3b | 3518 | |
40ae80cc JB |
3519 | seq_printf(m, "MST Source Port %c\n", |
3520 | port_name(intel_dig_port->port)); | |
11bed958 DA |
3521 | drm_dp_mst_dump_topology(m, &intel_dig_port->dp.mst_mgr); |
3522 | } | |
3523 | drm_modeset_unlock_all(dev); | |
3524 | return 0; | |
3525 | } | |
3526 | ||
07144428 DL |
3527 | static int i915_pipe_crc_open(struct inode *inode, struct file *filep) |
3528 | { | |
be5c7a90 | 3529 | struct pipe_crc_info *info = inode->i_private; |
fac5e23e | 3530 | struct drm_i915_private *dev_priv = to_i915(info->dev); |
be5c7a90 DL |
3531 | struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe]; |
3532 | ||
7eb1c496 DV |
3533 | if (info->pipe >= INTEL_INFO(info->dev)->num_pipes) |
3534 | return -ENODEV; | |
3535 | ||
d538bbdf DL |
3536 | spin_lock_irq(&pipe_crc->lock); |
3537 | ||
3538 | if (pipe_crc->opened) { | |
3539 | spin_unlock_irq(&pipe_crc->lock); | |
be5c7a90 DL |
3540 | return -EBUSY; /* already open */ |
3541 | } | |
3542 | ||
d538bbdf | 3543 | pipe_crc->opened = true; |
07144428 DL |
3544 | filep->private_data = inode->i_private; |
3545 | ||
d538bbdf DL |
3546 | spin_unlock_irq(&pipe_crc->lock); |
3547 | ||
07144428 DL |
3548 | return 0; |
3549 | } | |
3550 | ||
3551 | static int i915_pipe_crc_release(struct inode *inode, struct file *filep) | |
3552 | { | |
be5c7a90 | 3553 | struct pipe_crc_info *info = inode->i_private; |
fac5e23e | 3554 | struct drm_i915_private *dev_priv = to_i915(info->dev); |
be5c7a90 DL |
3555 | struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe]; |
3556 | ||
d538bbdf DL |
3557 | spin_lock_irq(&pipe_crc->lock); |
3558 | pipe_crc->opened = false; | |
3559 | spin_unlock_irq(&pipe_crc->lock); | |
be5c7a90 | 3560 | |
07144428 DL |
3561 | return 0; |
3562 | } | |
3563 | ||
3564 | /* (6 fields, 8 chars each, space separated (5) + '\n') */ | |
3565 | #define PIPE_CRC_LINE_LEN (6 * 8 + 5 + 1) | |
3566 | /* account for \'0' */ | |
3567 | #define PIPE_CRC_BUFFER_LEN (PIPE_CRC_LINE_LEN + 1) | |
3568 | ||
3569 | static int pipe_crc_data_count(struct intel_pipe_crc *pipe_crc) | |
8bf1e9f1 | 3570 | { |
d538bbdf DL |
3571 | assert_spin_locked(&pipe_crc->lock); |
3572 | return CIRC_CNT(pipe_crc->head, pipe_crc->tail, | |
3573 | INTEL_PIPE_CRC_ENTRIES_NR); | |
07144428 DL |
3574 | } |
3575 | ||
3576 | static ssize_t | |
3577 | i915_pipe_crc_read(struct file *filep, char __user *user_buf, size_t count, | |
3578 | loff_t *pos) | |
3579 | { | |
3580 | struct pipe_crc_info *info = filep->private_data; | |
3581 | struct drm_device *dev = info->dev; | |
fac5e23e | 3582 | struct drm_i915_private *dev_priv = to_i915(dev); |
07144428 DL |
3583 | struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe]; |
3584 | char buf[PIPE_CRC_BUFFER_LEN]; | |
9ad6d99f | 3585 | int n_entries; |
07144428 DL |
3586 | ssize_t bytes_read; |
3587 | ||
3588 | /* | |
3589 | * Don't allow user space to provide buffers not big enough to hold | |
3590 | * a line of data. | |
3591 | */ | |
3592 | if (count < PIPE_CRC_LINE_LEN) | |
3593 | return -EINVAL; | |
3594 | ||
3595 | if (pipe_crc->source == INTEL_PIPE_CRC_SOURCE_NONE) | |
8bf1e9f1 | 3596 | return 0; |
07144428 DL |
3597 | |
3598 | /* nothing to read */ | |
d538bbdf | 3599 | spin_lock_irq(&pipe_crc->lock); |
07144428 | 3600 | while (pipe_crc_data_count(pipe_crc) == 0) { |
d538bbdf DL |
3601 | int ret; |
3602 | ||
3603 | if (filep->f_flags & O_NONBLOCK) { | |
3604 | spin_unlock_irq(&pipe_crc->lock); | |
07144428 | 3605 | return -EAGAIN; |
d538bbdf | 3606 | } |
07144428 | 3607 | |
d538bbdf DL |
3608 | ret = wait_event_interruptible_lock_irq(pipe_crc->wq, |
3609 | pipe_crc_data_count(pipe_crc), pipe_crc->lock); | |
3610 | if (ret) { | |
3611 | spin_unlock_irq(&pipe_crc->lock); | |
3612 | return ret; | |
3613 | } | |
8bf1e9f1 SH |
3614 | } |
3615 | ||
07144428 | 3616 | /* We now have one or more entries to read */ |
9ad6d99f | 3617 | n_entries = count / PIPE_CRC_LINE_LEN; |
d538bbdf | 3618 | |
07144428 | 3619 | bytes_read = 0; |
9ad6d99f VS |
3620 | while (n_entries > 0) { |
3621 | struct intel_pipe_crc_entry *entry = | |
3622 | &pipe_crc->entries[pipe_crc->tail]; | |
8bf1e9f1 | 3623 | |
9ad6d99f VS |
3624 | if (CIRC_CNT(pipe_crc->head, pipe_crc->tail, |
3625 | INTEL_PIPE_CRC_ENTRIES_NR) < 1) | |
3626 | break; | |
3627 | ||
3628 | BUILD_BUG_ON_NOT_POWER_OF_2(INTEL_PIPE_CRC_ENTRIES_NR); | |
3629 | pipe_crc->tail = (pipe_crc->tail + 1) & (INTEL_PIPE_CRC_ENTRIES_NR - 1); | |
3630 | ||
07144428 DL |
3631 | bytes_read += snprintf(buf, PIPE_CRC_BUFFER_LEN, |
3632 | "%8u %8x %8x %8x %8x %8x\n", | |
3633 | entry->frame, entry->crc[0], | |
3634 | entry->crc[1], entry->crc[2], | |
3635 | entry->crc[3], entry->crc[4]); | |
3636 | ||
9ad6d99f VS |
3637 | spin_unlock_irq(&pipe_crc->lock); |
3638 | ||
4e9121e6 | 3639 | if (copy_to_user(user_buf, buf, PIPE_CRC_LINE_LEN)) |
07144428 | 3640 | return -EFAULT; |
b2c88f5b | 3641 | |
9ad6d99f VS |
3642 | user_buf += PIPE_CRC_LINE_LEN; |
3643 | n_entries--; | |
3644 | ||
3645 | spin_lock_irq(&pipe_crc->lock); | |
3646 | } | |
8bf1e9f1 | 3647 | |
d538bbdf DL |
3648 | spin_unlock_irq(&pipe_crc->lock); |
3649 | ||
07144428 DL |
3650 | return bytes_read; |
3651 | } | |
3652 | ||
3653 | static const struct file_operations i915_pipe_crc_fops = { | |
3654 | .owner = THIS_MODULE, | |
3655 | .open = i915_pipe_crc_open, | |
3656 | .read = i915_pipe_crc_read, | |
3657 | .release = i915_pipe_crc_release, | |
3658 | }; | |
3659 | ||
3660 | static struct pipe_crc_info i915_pipe_crc_data[I915_MAX_PIPES] = { | |
3661 | { | |
3662 | .name = "i915_pipe_A_crc", | |
3663 | .pipe = PIPE_A, | |
3664 | }, | |
3665 | { | |
3666 | .name = "i915_pipe_B_crc", | |
3667 | .pipe = PIPE_B, | |
3668 | }, | |
3669 | { | |
3670 | .name = "i915_pipe_C_crc", | |
3671 | .pipe = PIPE_C, | |
3672 | }, | |
3673 | }; | |
3674 | ||
3675 | static int i915_pipe_crc_create(struct dentry *root, struct drm_minor *minor, | |
3676 | enum pipe pipe) | |
3677 | { | |
3678 | struct drm_device *dev = minor->dev; | |
3679 | struct dentry *ent; | |
3680 | struct pipe_crc_info *info = &i915_pipe_crc_data[pipe]; | |
3681 | ||
3682 | info->dev = dev; | |
3683 | ent = debugfs_create_file(info->name, S_IRUGO, root, info, | |
3684 | &i915_pipe_crc_fops); | |
f3c5fe97 WY |
3685 | if (!ent) |
3686 | return -ENOMEM; | |
07144428 DL |
3687 | |
3688 | return drm_add_fake_info_node(minor, ent, info); | |
8bf1e9f1 SH |
3689 | } |
3690 | ||
e8dfcf78 | 3691 | static const char * const pipe_crc_sources[] = { |
926321d5 DV |
3692 | "none", |
3693 | "plane1", | |
3694 | "plane2", | |
3695 | "pf", | |
5b3a856b | 3696 | "pipe", |
3d099a05 DV |
3697 | "TV", |
3698 | "DP-B", | |
3699 | "DP-C", | |
3700 | "DP-D", | |
46a19188 | 3701 | "auto", |
926321d5 DV |
3702 | }; |
3703 | ||
3704 | static const char *pipe_crc_source_name(enum intel_pipe_crc_source source) | |
3705 | { | |
3706 | BUILD_BUG_ON(ARRAY_SIZE(pipe_crc_sources) != INTEL_PIPE_CRC_SOURCE_MAX); | |
3707 | return pipe_crc_sources[source]; | |
3708 | } | |
3709 | ||
bd9db02f | 3710 | static int display_crc_ctl_show(struct seq_file *m, void *data) |
926321d5 DV |
3711 | { |
3712 | struct drm_device *dev = m->private; | |
fac5e23e | 3713 | struct drm_i915_private *dev_priv = to_i915(dev); |
926321d5 DV |
3714 | int i; |
3715 | ||
3716 | for (i = 0; i < I915_MAX_PIPES; i++) | |
3717 | seq_printf(m, "%c %s\n", pipe_name(i), | |
3718 | pipe_crc_source_name(dev_priv->pipe_crc[i].source)); | |
3719 | ||
3720 | return 0; | |
3721 | } | |
3722 | ||
bd9db02f | 3723 | static int display_crc_ctl_open(struct inode *inode, struct file *file) |
926321d5 DV |
3724 | { |
3725 | struct drm_device *dev = inode->i_private; | |
3726 | ||
bd9db02f | 3727 | return single_open(file, display_crc_ctl_show, dev); |
926321d5 DV |
3728 | } |
3729 | ||
46a19188 | 3730 | static int i8xx_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source, |
52f843f6 DV |
3731 | uint32_t *val) |
3732 | { | |
46a19188 DV |
3733 | if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) |
3734 | *source = INTEL_PIPE_CRC_SOURCE_PIPE; | |
3735 | ||
3736 | switch (*source) { | |
52f843f6 DV |
3737 | case INTEL_PIPE_CRC_SOURCE_PIPE: |
3738 | *val = PIPE_CRC_ENABLE | PIPE_CRC_INCLUDE_BORDER_I8XX; | |
3739 | break; | |
3740 | case INTEL_PIPE_CRC_SOURCE_NONE: | |
3741 | *val = 0; | |
3742 | break; | |
3743 | default: | |
3744 | return -EINVAL; | |
3745 | } | |
3746 | ||
3747 | return 0; | |
3748 | } | |
3749 | ||
46a19188 DV |
3750 | static int i9xx_pipe_crc_auto_source(struct drm_device *dev, enum pipe pipe, |
3751 | enum intel_pipe_crc_source *source) | |
3752 | { | |
3753 | struct intel_encoder *encoder; | |
3754 | struct intel_crtc *crtc; | |
26756809 | 3755 | struct intel_digital_port *dig_port; |
46a19188 DV |
3756 | int ret = 0; |
3757 | ||
3758 | *source = INTEL_PIPE_CRC_SOURCE_PIPE; | |
3759 | ||
6e9f798d | 3760 | drm_modeset_lock_all(dev); |
b2784e15 | 3761 | for_each_intel_encoder(dev, encoder) { |
46a19188 DV |
3762 | if (!encoder->base.crtc) |
3763 | continue; | |
3764 | ||
3765 | crtc = to_intel_crtc(encoder->base.crtc); | |
3766 | ||
3767 | if (crtc->pipe != pipe) | |
3768 | continue; | |
3769 | ||
3770 | switch (encoder->type) { | |
3771 | case INTEL_OUTPUT_TVOUT: | |
3772 | *source = INTEL_PIPE_CRC_SOURCE_TV; | |
3773 | break; | |
cca0502b | 3774 | case INTEL_OUTPUT_DP: |
46a19188 | 3775 | case INTEL_OUTPUT_EDP: |
26756809 DV |
3776 | dig_port = enc_to_dig_port(&encoder->base); |
3777 | switch (dig_port->port) { | |
3778 | case PORT_B: | |
3779 | *source = INTEL_PIPE_CRC_SOURCE_DP_B; | |
3780 | break; | |
3781 | case PORT_C: | |
3782 | *source = INTEL_PIPE_CRC_SOURCE_DP_C; | |
3783 | break; | |
3784 | case PORT_D: | |
3785 | *source = INTEL_PIPE_CRC_SOURCE_DP_D; | |
3786 | break; | |
3787 | default: | |
3788 | WARN(1, "nonexisting DP port %c\n", | |
3789 | port_name(dig_port->port)); | |
3790 | break; | |
3791 | } | |
46a19188 | 3792 | break; |
6847d71b PZ |
3793 | default: |
3794 | break; | |
46a19188 DV |
3795 | } |
3796 | } | |
6e9f798d | 3797 | drm_modeset_unlock_all(dev); |
46a19188 DV |
3798 | |
3799 | return ret; | |
3800 | } | |
3801 | ||
3802 | static int vlv_pipe_crc_ctl_reg(struct drm_device *dev, | |
3803 | enum pipe pipe, | |
3804 | enum intel_pipe_crc_source *source, | |
7ac0129b DV |
3805 | uint32_t *val) |
3806 | { | |
fac5e23e | 3807 | struct drm_i915_private *dev_priv = to_i915(dev); |
8d2f24ca DV |
3808 | bool need_stable_symbols = false; |
3809 | ||
46a19188 DV |
3810 | if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) { |
3811 | int ret = i9xx_pipe_crc_auto_source(dev, pipe, source); | |
3812 | if (ret) | |
3813 | return ret; | |
3814 | } | |
3815 | ||
3816 | switch (*source) { | |
7ac0129b DV |
3817 | case INTEL_PIPE_CRC_SOURCE_PIPE: |
3818 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_VLV; | |
3819 | break; | |
3820 | case INTEL_PIPE_CRC_SOURCE_DP_B: | |
3821 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_VLV; | |
8d2f24ca | 3822 | need_stable_symbols = true; |
7ac0129b DV |
3823 | break; |
3824 | case INTEL_PIPE_CRC_SOURCE_DP_C: | |
3825 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_VLV; | |
8d2f24ca | 3826 | need_stable_symbols = true; |
7ac0129b | 3827 | break; |
2be57922 VS |
3828 | case INTEL_PIPE_CRC_SOURCE_DP_D: |
3829 | if (!IS_CHERRYVIEW(dev)) | |
3830 | return -EINVAL; | |
3831 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_VLV; | |
3832 | need_stable_symbols = true; | |
3833 | break; | |
7ac0129b DV |
3834 | case INTEL_PIPE_CRC_SOURCE_NONE: |
3835 | *val = 0; | |
3836 | break; | |
3837 | default: | |
3838 | return -EINVAL; | |
3839 | } | |
3840 | ||
8d2f24ca DV |
3841 | /* |
3842 | * When the pipe CRC tap point is after the transcoders we need | |
3843 | * to tweak symbol-level features to produce a deterministic series of | |
3844 | * symbols for a given frame. We need to reset those features only once | |
3845 | * a frame (instead of every nth symbol): | |
3846 | * - DC-balance: used to ensure a better clock recovery from the data | |
3847 | * link (SDVO) | |
3848 | * - DisplayPort scrambling: used for EMI reduction | |
3849 | */ | |
3850 | if (need_stable_symbols) { | |
3851 | uint32_t tmp = I915_READ(PORT_DFT2_G4X); | |
3852 | ||
8d2f24ca | 3853 | tmp |= DC_BALANCE_RESET_VLV; |
eb736679 VS |
3854 | switch (pipe) { |
3855 | case PIPE_A: | |
8d2f24ca | 3856 | tmp |= PIPE_A_SCRAMBLE_RESET; |
eb736679 VS |
3857 | break; |
3858 | case PIPE_B: | |
8d2f24ca | 3859 | tmp |= PIPE_B_SCRAMBLE_RESET; |
eb736679 VS |
3860 | break; |
3861 | case PIPE_C: | |
3862 | tmp |= PIPE_C_SCRAMBLE_RESET; | |
3863 | break; | |
3864 | default: | |
3865 | return -EINVAL; | |
3866 | } | |
8d2f24ca DV |
3867 | I915_WRITE(PORT_DFT2_G4X, tmp); |
3868 | } | |
3869 | ||
7ac0129b DV |
3870 | return 0; |
3871 | } | |
3872 | ||
4b79ebf7 | 3873 | static int i9xx_pipe_crc_ctl_reg(struct drm_device *dev, |
46a19188 DV |
3874 | enum pipe pipe, |
3875 | enum intel_pipe_crc_source *source, | |
4b79ebf7 DV |
3876 | uint32_t *val) |
3877 | { | |
fac5e23e | 3878 | struct drm_i915_private *dev_priv = to_i915(dev); |
84093603 DV |
3879 | bool need_stable_symbols = false; |
3880 | ||
46a19188 DV |
3881 | if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) { |
3882 | int ret = i9xx_pipe_crc_auto_source(dev, pipe, source); | |
3883 | if (ret) | |
3884 | return ret; | |
3885 | } | |
3886 | ||
3887 | switch (*source) { | |
4b79ebf7 DV |
3888 | case INTEL_PIPE_CRC_SOURCE_PIPE: |
3889 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_I9XX; | |
3890 | break; | |
3891 | case INTEL_PIPE_CRC_SOURCE_TV: | |
3892 | if (!SUPPORTS_TV(dev)) | |
3893 | return -EINVAL; | |
3894 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_TV_PRE; | |
3895 | break; | |
3896 | case INTEL_PIPE_CRC_SOURCE_DP_B: | |
3897 | if (!IS_G4X(dev)) | |
3898 | return -EINVAL; | |
3899 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_G4X; | |
84093603 | 3900 | need_stable_symbols = true; |
4b79ebf7 DV |
3901 | break; |
3902 | case INTEL_PIPE_CRC_SOURCE_DP_C: | |
3903 | if (!IS_G4X(dev)) | |
3904 | return -EINVAL; | |
3905 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_G4X; | |
84093603 | 3906 | need_stable_symbols = true; |
4b79ebf7 DV |
3907 | break; |
3908 | case INTEL_PIPE_CRC_SOURCE_DP_D: | |
3909 | if (!IS_G4X(dev)) | |
3910 | return -EINVAL; | |
3911 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_G4X; | |
84093603 | 3912 | need_stable_symbols = true; |
4b79ebf7 DV |
3913 | break; |
3914 | case INTEL_PIPE_CRC_SOURCE_NONE: | |
3915 | *val = 0; | |
3916 | break; | |
3917 | default: | |
3918 | return -EINVAL; | |
3919 | } | |
3920 | ||
84093603 DV |
3921 | /* |
3922 | * When the pipe CRC tap point is after the transcoders we need | |
3923 | * to tweak symbol-level features to produce a deterministic series of | |
3924 | * symbols for a given frame. We need to reset those features only once | |
3925 | * a frame (instead of every nth symbol): | |
3926 | * - DC-balance: used to ensure a better clock recovery from the data | |
3927 | * link (SDVO) | |
3928 | * - DisplayPort scrambling: used for EMI reduction | |
3929 | */ | |
3930 | if (need_stable_symbols) { | |
3931 | uint32_t tmp = I915_READ(PORT_DFT2_G4X); | |
3932 | ||
3933 | WARN_ON(!IS_G4X(dev)); | |
3934 | ||
3935 | I915_WRITE(PORT_DFT_I9XX, | |
3936 | I915_READ(PORT_DFT_I9XX) | DC_BALANCE_RESET); | |
3937 | ||
3938 | if (pipe == PIPE_A) | |
3939 | tmp |= PIPE_A_SCRAMBLE_RESET; | |
3940 | else | |
3941 | tmp |= PIPE_B_SCRAMBLE_RESET; | |
3942 | ||
3943 | I915_WRITE(PORT_DFT2_G4X, tmp); | |
3944 | } | |
3945 | ||
4b79ebf7 DV |
3946 | return 0; |
3947 | } | |
3948 | ||
8d2f24ca DV |
3949 | static void vlv_undo_pipe_scramble_reset(struct drm_device *dev, |
3950 | enum pipe pipe) | |
3951 | { | |
fac5e23e | 3952 | struct drm_i915_private *dev_priv = to_i915(dev); |
8d2f24ca DV |
3953 | uint32_t tmp = I915_READ(PORT_DFT2_G4X); |
3954 | ||
eb736679 VS |
3955 | switch (pipe) { |
3956 | case PIPE_A: | |
8d2f24ca | 3957 | tmp &= ~PIPE_A_SCRAMBLE_RESET; |
eb736679 VS |
3958 | break; |
3959 | case PIPE_B: | |
8d2f24ca | 3960 | tmp &= ~PIPE_B_SCRAMBLE_RESET; |
eb736679 VS |
3961 | break; |
3962 | case PIPE_C: | |
3963 | tmp &= ~PIPE_C_SCRAMBLE_RESET; | |
3964 | break; | |
3965 | default: | |
3966 | return; | |
3967 | } | |
8d2f24ca DV |
3968 | if (!(tmp & PIPE_SCRAMBLE_RESET_MASK)) |
3969 | tmp &= ~DC_BALANCE_RESET_VLV; | |
3970 | I915_WRITE(PORT_DFT2_G4X, tmp); | |
3971 | ||
3972 | } | |
3973 | ||
84093603 DV |
3974 | static void g4x_undo_pipe_scramble_reset(struct drm_device *dev, |
3975 | enum pipe pipe) | |
3976 | { | |
fac5e23e | 3977 | struct drm_i915_private *dev_priv = to_i915(dev); |
84093603 DV |
3978 | uint32_t tmp = I915_READ(PORT_DFT2_G4X); |
3979 | ||
3980 | if (pipe == PIPE_A) | |
3981 | tmp &= ~PIPE_A_SCRAMBLE_RESET; | |
3982 | else | |
3983 | tmp &= ~PIPE_B_SCRAMBLE_RESET; | |
3984 | I915_WRITE(PORT_DFT2_G4X, tmp); | |
3985 | ||
3986 | if (!(tmp & PIPE_SCRAMBLE_RESET_MASK)) { | |
3987 | I915_WRITE(PORT_DFT_I9XX, | |
3988 | I915_READ(PORT_DFT_I9XX) & ~DC_BALANCE_RESET); | |
3989 | } | |
3990 | } | |
3991 | ||
46a19188 | 3992 | static int ilk_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source, |
5b3a856b DV |
3993 | uint32_t *val) |
3994 | { | |
46a19188 DV |
3995 | if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) |
3996 | *source = INTEL_PIPE_CRC_SOURCE_PIPE; | |
3997 | ||
3998 | switch (*source) { | |
5b3a856b DV |
3999 | case INTEL_PIPE_CRC_SOURCE_PLANE1: |
4000 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_ILK; | |
4001 | break; | |
4002 | case INTEL_PIPE_CRC_SOURCE_PLANE2: | |
4003 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_ILK; | |
4004 | break; | |
5b3a856b DV |
4005 | case INTEL_PIPE_CRC_SOURCE_PIPE: |
4006 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_ILK; | |
4007 | break; | |
3d099a05 | 4008 | case INTEL_PIPE_CRC_SOURCE_NONE: |
5b3a856b DV |
4009 | *val = 0; |
4010 | break; | |
3d099a05 DV |
4011 | default: |
4012 | return -EINVAL; | |
5b3a856b DV |
4013 | } |
4014 | ||
4015 | return 0; | |
4016 | } | |
4017 | ||
c4e2d043 | 4018 | static void hsw_trans_edp_pipe_A_crc_wa(struct drm_device *dev, bool enable) |
fabf6e51 | 4019 | { |
fac5e23e | 4020 | struct drm_i915_private *dev_priv = to_i915(dev); |
fabf6e51 DV |
4021 | struct intel_crtc *crtc = |
4022 | to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_A]); | |
f77076c9 | 4023 | struct intel_crtc_state *pipe_config; |
c4e2d043 ML |
4024 | struct drm_atomic_state *state; |
4025 | int ret = 0; | |
fabf6e51 DV |
4026 | |
4027 | drm_modeset_lock_all(dev); | |
c4e2d043 ML |
4028 | state = drm_atomic_state_alloc(dev); |
4029 | if (!state) { | |
4030 | ret = -ENOMEM; | |
4031 | goto out; | |
fabf6e51 | 4032 | } |
fabf6e51 | 4033 | |
c4e2d043 ML |
4034 | state->acquire_ctx = drm_modeset_legacy_acquire_ctx(&crtc->base); |
4035 | pipe_config = intel_atomic_get_crtc_state(state, crtc); | |
4036 | if (IS_ERR(pipe_config)) { | |
4037 | ret = PTR_ERR(pipe_config); | |
4038 | goto out; | |
4039 | } | |
fabf6e51 | 4040 | |
c4e2d043 ML |
4041 | pipe_config->pch_pfit.force_thru = enable; |
4042 | if (pipe_config->cpu_transcoder == TRANSCODER_EDP && | |
4043 | pipe_config->pch_pfit.enabled != enable) | |
4044 | pipe_config->base.connectors_changed = true; | |
1b509259 | 4045 | |
c4e2d043 ML |
4046 | ret = drm_atomic_commit(state); |
4047 | out: | |
fabf6e51 | 4048 | drm_modeset_unlock_all(dev); |
c4e2d043 ML |
4049 | WARN(ret, "Toggling workaround to %i returns %i\n", enable, ret); |
4050 | if (ret) | |
4051 | drm_atomic_state_free(state); | |
fabf6e51 DV |
4052 | } |
4053 | ||
4054 | static int ivb_pipe_crc_ctl_reg(struct drm_device *dev, | |
4055 | enum pipe pipe, | |
4056 | enum intel_pipe_crc_source *source, | |
5b3a856b DV |
4057 | uint32_t *val) |
4058 | { | |
46a19188 DV |
4059 | if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) |
4060 | *source = INTEL_PIPE_CRC_SOURCE_PF; | |
4061 | ||
4062 | switch (*source) { | |
5b3a856b DV |
4063 | case INTEL_PIPE_CRC_SOURCE_PLANE1: |
4064 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_IVB; | |
4065 | break; | |
4066 | case INTEL_PIPE_CRC_SOURCE_PLANE2: | |
4067 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_IVB; | |
4068 | break; | |
4069 | case INTEL_PIPE_CRC_SOURCE_PF: | |
fabf6e51 | 4070 | if (IS_HASWELL(dev) && pipe == PIPE_A) |
c4e2d043 | 4071 | hsw_trans_edp_pipe_A_crc_wa(dev, true); |
fabf6e51 | 4072 | |
5b3a856b DV |
4073 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PF_IVB; |
4074 | break; | |
3d099a05 | 4075 | case INTEL_PIPE_CRC_SOURCE_NONE: |
5b3a856b DV |
4076 | *val = 0; |
4077 | break; | |
3d099a05 DV |
4078 | default: |
4079 | return -EINVAL; | |
5b3a856b DV |
4080 | } |
4081 | ||
4082 | return 0; | |
4083 | } | |
4084 | ||
926321d5 DV |
4085 | static int pipe_crc_set_source(struct drm_device *dev, enum pipe pipe, |
4086 | enum intel_pipe_crc_source source) | |
4087 | { | |
fac5e23e | 4088 | struct drm_i915_private *dev_priv = to_i915(dev); |
cc3da175 | 4089 | struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe]; |
8c740dce PZ |
4090 | struct intel_crtc *crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, |
4091 | pipe)); | |
e129649b | 4092 | enum intel_display_power_domain power_domain; |
432f3342 | 4093 | u32 val = 0; /* shut up gcc */ |
5b3a856b | 4094 | int ret; |
926321d5 | 4095 | |
cc3da175 DL |
4096 | if (pipe_crc->source == source) |
4097 | return 0; | |
4098 | ||
ae676fcd DL |
4099 | /* forbid changing the source without going back to 'none' */ |
4100 | if (pipe_crc->source && source) | |
4101 | return -EINVAL; | |
4102 | ||
e129649b ID |
4103 | power_domain = POWER_DOMAIN_PIPE(pipe); |
4104 | if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) { | |
9d8b0588 DV |
4105 | DRM_DEBUG_KMS("Trying to capture CRC while pipe is off\n"); |
4106 | return -EIO; | |
4107 | } | |
4108 | ||
52f843f6 | 4109 | if (IS_GEN2(dev)) |
46a19188 | 4110 | ret = i8xx_pipe_crc_ctl_reg(&source, &val); |
52f843f6 | 4111 | else if (INTEL_INFO(dev)->gen < 5) |
46a19188 | 4112 | ret = i9xx_pipe_crc_ctl_reg(dev, pipe, &source, &val); |
666a4537 | 4113 | else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) |
fabf6e51 | 4114 | ret = vlv_pipe_crc_ctl_reg(dev, pipe, &source, &val); |
4b79ebf7 | 4115 | else if (IS_GEN5(dev) || IS_GEN6(dev)) |
46a19188 | 4116 | ret = ilk_pipe_crc_ctl_reg(&source, &val); |
5b3a856b | 4117 | else |
fabf6e51 | 4118 | ret = ivb_pipe_crc_ctl_reg(dev, pipe, &source, &val); |
5b3a856b DV |
4119 | |
4120 | if (ret != 0) | |
e129649b | 4121 | goto out; |
5b3a856b | 4122 | |
4b584369 DL |
4123 | /* none -> real source transition */ |
4124 | if (source) { | |
4252fbc3 VS |
4125 | struct intel_pipe_crc_entry *entries; |
4126 | ||
7cd6ccff DL |
4127 | DRM_DEBUG_DRIVER("collecting CRCs for pipe %c, %s\n", |
4128 | pipe_name(pipe), pipe_crc_source_name(source)); | |
4129 | ||
3cf54b34 VS |
4130 | entries = kcalloc(INTEL_PIPE_CRC_ENTRIES_NR, |
4131 | sizeof(pipe_crc->entries[0]), | |
4252fbc3 | 4132 | GFP_KERNEL); |
e129649b ID |
4133 | if (!entries) { |
4134 | ret = -ENOMEM; | |
4135 | goto out; | |
4136 | } | |
e5f75aca | 4137 | |
8c740dce PZ |
4138 | /* |
4139 | * When IPS gets enabled, the pipe CRC changes. Since IPS gets | |
4140 | * enabled and disabled dynamically based on package C states, | |
4141 | * user space can't make reliable use of the CRCs, so let's just | |
4142 | * completely disable it. | |
4143 | */ | |
4144 | hsw_disable_ips(crtc); | |
4145 | ||
d538bbdf | 4146 | spin_lock_irq(&pipe_crc->lock); |
64387b61 | 4147 | kfree(pipe_crc->entries); |
4252fbc3 | 4148 | pipe_crc->entries = entries; |
d538bbdf DL |
4149 | pipe_crc->head = 0; |
4150 | pipe_crc->tail = 0; | |
4151 | spin_unlock_irq(&pipe_crc->lock); | |
4b584369 DL |
4152 | } |
4153 | ||
cc3da175 | 4154 | pipe_crc->source = source; |
926321d5 | 4155 | |
926321d5 DV |
4156 | I915_WRITE(PIPE_CRC_CTL(pipe), val); |
4157 | POSTING_READ(PIPE_CRC_CTL(pipe)); | |
4158 | ||
e5f75aca DL |
4159 | /* real source -> none transition */ |
4160 | if (source == INTEL_PIPE_CRC_SOURCE_NONE) { | |
d538bbdf | 4161 | struct intel_pipe_crc_entry *entries; |
a33d7105 DV |
4162 | struct intel_crtc *crtc = |
4163 | to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); | |
d538bbdf | 4164 | |
7cd6ccff DL |
4165 | DRM_DEBUG_DRIVER("stopping CRCs for pipe %c\n", |
4166 | pipe_name(pipe)); | |
4167 | ||
a33d7105 | 4168 | drm_modeset_lock(&crtc->base.mutex, NULL); |
f77076c9 | 4169 | if (crtc->base.state->active) |
a33d7105 DV |
4170 | intel_wait_for_vblank(dev, pipe); |
4171 | drm_modeset_unlock(&crtc->base.mutex); | |
bcf17ab2 | 4172 | |
d538bbdf DL |
4173 | spin_lock_irq(&pipe_crc->lock); |
4174 | entries = pipe_crc->entries; | |
e5f75aca | 4175 | pipe_crc->entries = NULL; |
9ad6d99f VS |
4176 | pipe_crc->head = 0; |
4177 | pipe_crc->tail = 0; | |
d538bbdf DL |
4178 | spin_unlock_irq(&pipe_crc->lock); |
4179 | ||
4180 | kfree(entries); | |
84093603 DV |
4181 | |
4182 | if (IS_G4X(dev)) | |
4183 | g4x_undo_pipe_scramble_reset(dev, pipe); | |
666a4537 | 4184 | else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) |
8d2f24ca | 4185 | vlv_undo_pipe_scramble_reset(dev, pipe); |
fabf6e51 | 4186 | else if (IS_HASWELL(dev) && pipe == PIPE_A) |
c4e2d043 | 4187 | hsw_trans_edp_pipe_A_crc_wa(dev, false); |
8c740dce PZ |
4188 | |
4189 | hsw_enable_ips(crtc); | |
e5f75aca DL |
4190 | } |
4191 | ||
e129649b ID |
4192 | ret = 0; |
4193 | ||
4194 | out: | |
4195 | intel_display_power_put(dev_priv, power_domain); | |
4196 | ||
4197 | return ret; | |
926321d5 DV |
4198 | } |
4199 | ||
4200 | /* | |
4201 | * Parse pipe CRC command strings: | |
b94dec87 DL |
4202 | * command: wsp* object wsp+ name wsp+ source wsp* |
4203 | * object: 'pipe' | |
4204 | * name: (A | B | C) | |
926321d5 DV |
4205 | * source: (none | plane1 | plane2 | pf) |
4206 | * wsp: (#0x20 | #0x9 | #0xA)+ | |
4207 | * | |
4208 | * eg.: | |
b94dec87 DL |
4209 | * "pipe A plane1" -> Start CRC computations on plane1 of pipe A |
4210 | * "pipe A none" -> Stop CRC | |
926321d5 | 4211 | */ |
bd9db02f | 4212 | static int display_crc_ctl_tokenize(char *buf, char *words[], int max_words) |
926321d5 DV |
4213 | { |
4214 | int n_words = 0; | |
4215 | ||
4216 | while (*buf) { | |
4217 | char *end; | |
4218 | ||
4219 | /* skip leading white space */ | |
4220 | buf = skip_spaces(buf); | |
4221 | if (!*buf) | |
4222 | break; /* end of buffer */ | |
4223 | ||
4224 | /* find end of word */ | |
4225 | for (end = buf; *end && !isspace(*end); end++) | |
4226 | ; | |
4227 | ||
4228 | if (n_words == max_words) { | |
4229 | DRM_DEBUG_DRIVER("too many words, allowed <= %d\n", | |
4230 | max_words); | |
4231 | return -EINVAL; /* ran out of words[] before bytes */ | |
4232 | } | |
4233 | ||
4234 | if (*end) | |
4235 | *end++ = '\0'; | |
4236 | words[n_words++] = buf; | |
4237 | buf = end; | |
4238 | } | |
4239 | ||
4240 | return n_words; | |
4241 | } | |
4242 | ||
b94dec87 DL |
4243 | enum intel_pipe_crc_object { |
4244 | PIPE_CRC_OBJECT_PIPE, | |
4245 | }; | |
4246 | ||
e8dfcf78 | 4247 | static const char * const pipe_crc_objects[] = { |
b94dec87 DL |
4248 | "pipe", |
4249 | }; | |
4250 | ||
4251 | static int | |
bd9db02f | 4252 | display_crc_ctl_parse_object(const char *buf, enum intel_pipe_crc_object *o) |
b94dec87 DL |
4253 | { |
4254 | int i; | |
4255 | ||
4256 | for (i = 0; i < ARRAY_SIZE(pipe_crc_objects); i++) | |
4257 | if (!strcmp(buf, pipe_crc_objects[i])) { | |
bd9db02f | 4258 | *o = i; |
b94dec87 DL |
4259 | return 0; |
4260 | } | |
4261 | ||
4262 | return -EINVAL; | |
4263 | } | |
4264 | ||
bd9db02f | 4265 | static int display_crc_ctl_parse_pipe(const char *buf, enum pipe *pipe) |
926321d5 DV |
4266 | { |
4267 | const char name = buf[0]; | |
4268 | ||
4269 | if (name < 'A' || name >= pipe_name(I915_MAX_PIPES)) | |
4270 | return -EINVAL; | |
4271 | ||
4272 | *pipe = name - 'A'; | |
4273 | ||
4274 | return 0; | |
4275 | } | |
4276 | ||
4277 | static int | |
bd9db02f | 4278 | display_crc_ctl_parse_source(const char *buf, enum intel_pipe_crc_source *s) |
926321d5 DV |
4279 | { |
4280 | int i; | |
4281 | ||
4282 | for (i = 0; i < ARRAY_SIZE(pipe_crc_sources); i++) | |
4283 | if (!strcmp(buf, pipe_crc_sources[i])) { | |
bd9db02f | 4284 | *s = i; |
926321d5 DV |
4285 | return 0; |
4286 | } | |
4287 | ||
4288 | return -EINVAL; | |
4289 | } | |
4290 | ||
bd9db02f | 4291 | static int display_crc_ctl_parse(struct drm_device *dev, char *buf, size_t len) |
926321d5 | 4292 | { |
b94dec87 | 4293 | #define N_WORDS 3 |
926321d5 | 4294 | int n_words; |
b94dec87 | 4295 | char *words[N_WORDS]; |
926321d5 | 4296 | enum pipe pipe; |
b94dec87 | 4297 | enum intel_pipe_crc_object object; |
926321d5 DV |
4298 | enum intel_pipe_crc_source source; |
4299 | ||
bd9db02f | 4300 | n_words = display_crc_ctl_tokenize(buf, words, N_WORDS); |
b94dec87 DL |
4301 | if (n_words != N_WORDS) { |
4302 | DRM_DEBUG_DRIVER("tokenize failed, a command is %d words\n", | |
4303 | N_WORDS); | |
4304 | return -EINVAL; | |
4305 | } | |
4306 | ||
bd9db02f | 4307 | if (display_crc_ctl_parse_object(words[0], &object) < 0) { |
b94dec87 | 4308 | DRM_DEBUG_DRIVER("unknown object %s\n", words[0]); |
926321d5 DV |
4309 | return -EINVAL; |
4310 | } | |
4311 | ||
bd9db02f | 4312 | if (display_crc_ctl_parse_pipe(words[1], &pipe) < 0) { |
b94dec87 | 4313 | DRM_DEBUG_DRIVER("unknown pipe %s\n", words[1]); |
926321d5 DV |
4314 | return -EINVAL; |
4315 | } | |
4316 | ||
bd9db02f | 4317 | if (display_crc_ctl_parse_source(words[2], &source) < 0) { |
b94dec87 | 4318 | DRM_DEBUG_DRIVER("unknown source %s\n", words[2]); |
926321d5 DV |
4319 | return -EINVAL; |
4320 | } | |
4321 | ||
4322 | return pipe_crc_set_source(dev, pipe, source); | |
4323 | } | |
4324 | ||
bd9db02f DL |
4325 | static ssize_t display_crc_ctl_write(struct file *file, const char __user *ubuf, |
4326 | size_t len, loff_t *offp) | |
926321d5 DV |
4327 | { |
4328 | struct seq_file *m = file->private_data; | |
4329 | struct drm_device *dev = m->private; | |
4330 | char *tmpbuf; | |
4331 | int ret; | |
4332 | ||
4333 | if (len == 0) | |
4334 | return 0; | |
4335 | ||
4336 | if (len > PAGE_SIZE - 1) { | |
4337 | DRM_DEBUG_DRIVER("expected <%lu bytes into pipe crc control\n", | |
4338 | PAGE_SIZE); | |
4339 | return -E2BIG; | |
4340 | } | |
4341 | ||
4342 | tmpbuf = kmalloc(len + 1, GFP_KERNEL); | |
4343 | if (!tmpbuf) | |
4344 | return -ENOMEM; | |
4345 | ||
4346 | if (copy_from_user(tmpbuf, ubuf, len)) { | |
4347 | ret = -EFAULT; | |
4348 | goto out; | |
4349 | } | |
4350 | tmpbuf[len] = '\0'; | |
4351 | ||
bd9db02f | 4352 | ret = display_crc_ctl_parse(dev, tmpbuf, len); |
926321d5 DV |
4353 | |
4354 | out: | |
4355 | kfree(tmpbuf); | |
4356 | if (ret < 0) | |
4357 | return ret; | |
4358 | ||
4359 | *offp += len; | |
4360 | return len; | |
4361 | } | |
4362 | ||
bd9db02f | 4363 | static const struct file_operations i915_display_crc_ctl_fops = { |
926321d5 | 4364 | .owner = THIS_MODULE, |
bd9db02f | 4365 | .open = display_crc_ctl_open, |
926321d5 DV |
4366 | .read = seq_read, |
4367 | .llseek = seq_lseek, | |
4368 | .release = single_release, | |
bd9db02f | 4369 | .write = display_crc_ctl_write |
926321d5 DV |
4370 | }; |
4371 | ||
eb3394fa TP |
4372 | static ssize_t i915_displayport_test_active_write(struct file *file, |
4373 | const char __user *ubuf, | |
4374 | size_t len, loff_t *offp) | |
4375 | { | |
4376 | char *input_buffer; | |
4377 | int status = 0; | |
eb3394fa TP |
4378 | struct drm_device *dev; |
4379 | struct drm_connector *connector; | |
4380 | struct list_head *connector_list; | |
4381 | struct intel_dp *intel_dp; | |
4382 | int val = 0; | |
4383 | ||
9aaffa34 | 4384 | dev = ((struct seq_file *)file->private_data)->private; |
eb3394fa | 4385 | |
eb3394fa TP |
4386 | connector_list = &dev->mode_config.connector_list; |
4387 | ||
4388 | if (len == 0) | |
4389 | return 0; | |
4390 | ||
4391 | input_buffer = kmalloc(len + 1, GFP_KERNEL); | |
4392 | if (!input_buffer) | |
4393 | return -ENOMEM; | |
4394 | ||
4395 | if (copy_from_user(input_buffer, ubuf, len)) { | |
4396 | status = -EFAULT; | |
4397 | goto out; | |
4398 | } | |
4399 | ||
4400 | input_buffer[len] = '\0'; | |
4401 | DRM_DEBUG_DRIVER("Copied %d bytes from user\n", (unsigned int)len); | |
4402 | ||
4403 | list_for_each_entry(connector, connector_list, head) { | |
4404 | ||
4405 | if (connector->connector_type != | |
4406 | DRM_MODE_CONNECTOR_DisplayPort) | |
4407 | continue; | |
4408 | ||
b8bb08ec | 4409 | if (connector->status == connector_status_connected && |
eb3394fa TP |
4410 | connector->encoder != NULL) { |
4411 | intel_dp = enc_to_intel_dp(connector->encoder); | |
4412 | status = kstrtoint(input_buffer, 10, &val); | |
4413 | if (status < 0) | |
4414 | goto out; | |
4415 | DRM_DEBUG_DRIVER("Got %d for test active\n", val); | |
4416 | /* To prevent erroneous activation of the compliance | |
4417 | * testing code, only accept an actual value of 1 here | |
4418 | */ | |
4419 | if (val == 1) | |
4420 | intel_dp->compliance_test_active = 1; | |
4421 | else | |
4422 | intel_dp->compliance_test_active = 0; | |
4423 | } | |
4424 | } | |
4425 | out: | |
4426 | kfree(input_buffer); | |
4427 | if (status < 0) | |
4428 | return status; | |
4429 | ||
4430 | *offp += len; | |
4431 | return len; | |
4432 | } | |
4433 | ||
4434 | static int i915_displayport_test_active_show(struct seq_file *m, void *data) | |
4435 | { | |
4436 | struct drm_device *dev = m->private; | |
4437 | struct drm_connector *connector; | |
4438 | struct list_head *connector_list = &dev->mode_config.connector_list; | |
4439 | struct intel_dp *intel_dp; | |
4440 | ||
eb3394fa TP |
4441 | list_for_each_entry(connector, connector_list, head) { |
4442 | ||
4443 | if (connector->connector_type != | |
4444 | DRM_MODE_CONNECTOR_DisplayPort) | |
4445 | continue; | |
4446 | ||
4447 | if (connector->status == connector_status_connected && | |
4448 | connector->encoder != NULL) { | |
4449 | intel_dp = enc_to_intel_dp(connector->encoder); | |
4450 | if (intel_dp->compliance_test_active) | |
4451 | seq_puts(m, "1"); | |
4452 | else | |
4453 | seq_puts(m, "0"); | |
4454 | } else | |
4455 | seq_puts(m, "0"); | |
4456 | } | |
4457 | ||
4458 | return 0; | |
4459 | } | |
4460 | ||
4461 | static int i915_displayport_test_active_open(struct inode *inode, | |
4462 | struct file *file) | |
4463 | { | |
4464 | struct drm_device *dev = inode->i_private; | |
4465 | ||
4466 | return single_open(file, i915_displayport_test_active_show, dev); | |
4467 | } | |
4468 | ||
4469 | static const struct file_operations i915_displayport_test_active_fops = { | |
4470 | .owner = THIS_MODULE, | |
4471 | .open = i915_displayport_test_active_open, | |
4472 | .read = seq_read, | |
4473 | .llseek = seq_lseek, | |
4474 | .release = single_release, | |
4475 | .write = i915_displayport_test_active_write | |
4476 | }; | |
4477 | ||
4478 | static int i915_displayport_test_data_show(struct seq_file *m, void *data) | |
4479 | { | |
4480 | struct drm_device *dev = m->private; | |
4481 | struct drm_connector *connector; | |
4482 | struct list_head *connector_list = &dev->mode_config.connector_list; | |
4483 | struct intel_dp *intel_dp; | |
4484 | ||
eb3394fa TP |
4485 | list_for_each_entry(connector, connector_list, head) { |
4486 | ||
4487 | if (connector->connector_type != | |
4488 | DRM_MODE_CONNECTOR_DisplayPort) | |
4489 | continue; | |
4490 | ||
4491 | if (connector->status == connector_status_connected && | |
4492 | connector->encoder != NULL) { | |
4493 | intel_dp = enc_to_intel_dp(connector->encoder); | |
4494 | seq_printf(m, "%lx", intel_dp->compliance_test_data); | |
4495 | } else | |
4496 | seq_puts(m, "0"); | |
4497 | } | |
4498 | ||
4499 | return 0; | |
4500 | } | |
4501 | static int i915_displayport_test_data_open(struct inode *inode, | |
4502 | struct file *file) | |
4503 | { | |
4504 | struct drm_device *dev = inode->i_private; | |
4505 | ||
4506 | return single_open(file, i915_displayport_test_data_show, dev); | |
4507 | } | |
4508 | ||
4509 | static const struct file_operations i915_displayport_test_data_fops = { | |
4510 | .owner = THIS_MODULE, | |
4511 | .open = i915_displayport_test_data_open, | |
4512 | .read = seq_read, | |
4513 | .llseek = seq_lseek, | |
4514 | .release = single_release | |
4515 | }; | |
4516 | ||
4517 | static int i915_displayport_test_type_show(struct seq_file *m, void *data) | |
4518 | { | |
4519 | struct drm_device *dev = m->private; | |
4520 | struct drm_connector *connector; | |
4521 | struct list_head *connector_list = &dev->mode_config.connector_list; | |
4522 | struct intel_dp *intel_dp; | |
4523 | ||
eb3394fa TP |
4524 | list_for_each_entry(connector, connector_list, head) { |
4525 | ||
4526 | if (connector->connector_type != | |
4527 | DRM_MODE_CONNECTOR_DisplayPort) | |
4528 | continue; | |
4529 | ||
4530 | if (connector->status == connector_status_connected && | |
4531 | connector->encoder != NULL) { | |
4532 | intel_dp = enc_to_intel_dp(connector->encoder); | |
4533 | seq_printf(m, "%02lx", intel_dp->compliance_test_type); | |
4534 | } else | |
4535 | seq_puts(m, "0"); | |
4536 | } | |
4537 | ||
4538 | return 0; | |
4539 | } | |
4540 | ||
4541 | static int i915_displayport_test_type_open(struct inode *inode, | |
4542 | struct file *file) | |
4543 | { | |
4544 | struct drm_device *dev = inode->i_private; | |
4545 | ||
4546 | return single_open(file, i915_displayport_test_type_show, dev); | |
4547 | } | |
4548 | ||
4549 | static const struct file_operations i915_displayport_test_type_fops = { | |
4550 | .owner = THIS_MODULE, | |
4551 | .open = i915_displayport_test_type_open, | |
4552 | .read = seq_read, | |
4553 | .llseek = seq_lseek, | |
4554 | .release = single_release | |
4555 | }; | |
4556 | ||
97e94b22 | 4557 | static void wm_latency_show(struct seq_file *m, const uint16_t wm[8]) |
369a1342 VS |
4558 | { |
4559 | struct drm_device *dev = m->private; | |
369a1342 | 4560 | int level; |
de38b95c VS |
4561 | int num_levels; |
4562 | ||
4563 | if (IS_CHERRYVIEW(dev)) | |
4564 | num_levels = 3; | |
4565 | else if (IS_VALLEYVIEW(dev)) | |
4566 | num_levels = 1; | |
4567 | else | |
4568 | num_levels = ilk_wm_max_level(dev) + 1; | |
369a1342 VS |
4569 | |
4570 | drm_modeset_lock_all(dev); | |
4571 | ||
4572 | for (level = 0; level < num_levels; level++) { | |
4573 | unsigned int latency = wm[level]; | |
4574 | ||
97e94b22 DL |
4575 | /* |
4576 | * - WM1+ latency values in 0.5us units | |
de38b95c | 4577 | * - latencies are in us on gen9/vlv/chv |
97e94b22 | 4578 | */ |
666a4537 WB |
4579 | if (INTEL_INFO(dev)->gen >= 9 || IS_VALLEYVIEW(dev) || |
4580 | IS_CHERRYVIEW(dev)) | |
97e94b22 DL |
4581 | latency *= 10; |
4582 | else if (level > 0) | |
369a1342 VS |
4583 | latency *= 5; |
4584 | ||
4585 | seq_printf(m, "WM%d %u (%u.%u usec)\n", | |
97e94b22 | 4586 | level, wm[level], latency / 10, latency % 10); |
369a1342 VS |
4587 | } |
4588 | ||
4589 | drm_modeset_unlock_all(dev); | |
4590 | } | |
4591 | ||
4592 | static int pri_wm_latency_show(struct seq_file *m, void *data) | |
4593 | { | |
4594 | struct drm_device *dev = m->private; | |
fac5e23e | 4595 | struct drm_i915_private *dev_priv = to_i915(dev); |
97e94b22 DL |
4596 | const uint16_t *latencies; |
4597 | ||
4598 | if (INTEL_INFO(dev)->gen >= 9) | |
4599 | latencies = dev_priv->wm.skl_latency; | |
4600 | else | |
4601 | latencies = to_i915(dev)->wm.pri_latency; | |
369a1342 | 4602 | |
97e94b22 | 4603 | wm_latency_show(m, latencies); |
369a1342 VS |
4604 | |
4605 | return 0; | |
4606 | } | |
4607 | ||
4608 | static int spr_wm_latency_show(struct seq_file *m, void *data) | |
4609 | { | |
4610 | struct drm_device *dev = m->private; | |
fac5e23e | 4611 | struct drm_i915_private *dev_priv = to_i915(dev); |
97e94b22 DL |
4612 | const uint16_t *latencies; |
4613 | ||
4614 | if (INTEL_INFO(dev)->gen >= 9) | |
4615 | latencies = dev_priv->wm.skl_latency; | |
4616 | else | |
4617 | latencies = to_i915(dev)->wm.spr_latency; | |
369a1342 | 4618 | |
97e94b22 | 4619 | wm_latency_show(m, latencies); |
369a1342 VS |
4620 | |
4621 | return 0; | |
4622 | } | |
4623 | ||
4624 | static int cur_wm_latency_show(struct seq_file *m, void *data) | |
4625 | { | |
4626 | struct drm_device *dev = m->private; | |
fac5e23e | 4627 | struct drm_i915_private *dev_priv = to_i915(dev); |
97e94b22 DL |
4628 | const uint16_t *latencies; |
4629 | ||
4630 | if (INTEL_INFO(dev)->gen >= 9) | |
4631 | latencies = dev_priv->wm.skl_latency; | |
4632 | else | |
4633 | latencies = to_i915(dev)->wm.cur_latency; | |
369a1342 | 4634 | |
97e94b22 | 4635 | wm_latency_show(m, latencies); |
369a1342 VS |
4636 | |
4637 | return 0; | |
4638 | } | |
4639 | ||
4640 | static int pri_wm_latency_open(struct inode *inode, struct file *file) | |
4641 | { | |
4642 | struct drm_device *dev = inode->i_private; | |
4643 | ||
de38b95c | 4644 | if (INTEL_INFO(dev)->gen < 5) |
369a1342 VS |
4645 | return -ENODEV; |
4646 | ||
4647 | return single_open(file, pri_wm_latency_show, dev); | |
4648 | } | |
4649 | ||
4650 | static int spr_wm_latency_open(struct inode *inode, struct file *file) | |
4651 | { | |
4652 | struct drm_device *dev = inode->i_private; | |
4653 | ||
9ad0257c | 4654 | if (HAS_GMCH_DISPLAY(dev)) |
369a1342 VS |
4655 | return -ENODEV; |
4656 | ||
4657 | return single_open(file, spr_wm_latency_show, dev); | |
4658 | } | |
4659 | ||
4660 | static int cur_wm_latency_open(struct inode *inode, struct file *file) | |
4661 | { | |
4662 | struct drm_device *dev = inode->i_private; | |
4663 | ||
9ad0257c | 4664 | if (HAS_GMCH_DISPLAY(dev)) |
369a1342 VS |
4665 | return -ENODEV; |
4666 | ||
4667 | return single_open(file, cur_wm_latency_show, dev); | |
4668 | } | |
4669 | ||
4670 | static ssize_t wm_latency_write(struct file *file, const char __user *ubuf, | |
97e94b22 | 4671 | size_t len, loff_t *offp, uint16_t wm[8]) |
369a1342 VS |
4672 | { |
4673 | struct seq_file *m = file->private_data; | |
4674 | struct drm_device *dev = m->private; | |
97e94b22 | 4675 | uint16_t new[8] = { 0 }; |
de38b95c | 4676 | int num_levels; |
369a1342 VS |
4677 | int level; |
4678 | int ret; | |
4679 | char tmp[32]; | |
4680 | ||
de38b95c VS |
4681 | if (IS_CHERRYVIEW(dev)) |
4682 | num_levels = 3; | |
4683 | else if (IS_VALLEYVIEW(dev)) | |
4684 | num_levels = 1; | |
4685 | else | |
4686 | num_levels = ilk_wm_max_level(dev) + 1; | |
4687 | ||
369a1342 VS |
4688 | if (len >= sizeof(tmp)) |
4689 | return -EINVAL; | |
4690 | ||
4691 | if (copy_from_user(tmp, ubuf, len)) | |
4692 | return -EFAULT; | |
4693 | ||
4694 | tmp[len] = '\0'; | |
4695 | ||
97e94b22 DL |
4696 | ret = sscanf(tmp, "%hu %hu %hu %hu %hu %hu %hu %hu", |
4697 | &new[0], &new[1], &new[2], &new[3], | |
4698 | &new[4], &new[5], &new[6], &new[7]); | |
369a1342 VS |
4699 | if (ret != num_levels) |
4700 | return -EINVAL; | |
4701 | ||
4702 | drm_modeset_lock_all(dev); | |
4703 | ||
4704 | for (level = 0; level < num_levels; level++) | |
4705 | wm[level] = new[level]; | |
4706 | ||
4707 | drm_modeset_unlock_all(dev); | |
4708 | ||
4709 | return len; | |
4710 | } | |
4711 | ||
4712 | ||
4713 | static ssize_t pri_wm_latency_write(struct file *file, const char __user *ubuf, | |
4714 | size_t len, loff_t *offp) | |
4715 | { | |
4716 | struct seq_file *m = file->private_data; | |
4717 | struct drm_device *dev = m->private; | |
fac5e23e | 4718 | struct drm_i915_private *dev_priv = to_i915(dev); |
97e94b22 | 4719 | uint16_t *latencies; |
369a1342 | 4720 | |
97e94b22 DL |
4721 | if (INTEL_INFO(dev)->gen >= 9) |
4722 | latencies = dev_priv->wm.skl_latency; | |
4723 | else | |
4724 | latencies = to_i915(dev)->wm.pri_latency; | |
4725 | ||
4726 | return wm_latency_write(file, ubuf, len, offp, latencies); | |
369a1342 VS |
4727 | } |
4728 | ||
4729 | static ssize_t spr_wm_latency_write(struct file *file, const char __user *ubuf, | |
4730 | size_t len, loff_t *offp) | |
4731 | { | |
4732 | struct seq_file *m = file->private_data; | |
4733 | struct drm_device *dev = m->private; | |
fac5e23e | 4734 | struct drm_i915_private *dev_priv = to_i915(dev); |
97e94b22 | 4735 | uint16_t *latencies; |
369a1342 | 4736 | |
97e94b22 DL |
4737 | if (INTEL_INFO(dev)->gen >= 9) |
4738 | latencies = dev_priv->wm.skl_latency; | |
4739 | else | |
4740 | latencies = to_i915(dev)->wm.spr_latency; | |
4741 | ||
4742 | return wm_latency_write(file, ubuf, len, offp, latencies); | |
369a1342 VS |
4743 | } |
4744 | ||
4745 | static ssize_t cur_wm_latency_write(struct file *file, const char __user *ubuf, | |
4746 | size_t len, loff_t *offp) | |
4747 | { | |
4748 | struct seq_file *m = file->private_data; | |
4749 | struct drm_device *dev = m->private; | |
fac5e23e | 4750 | struct drm_i915_private *dev_priv = to_i915(dev); |
97e94b22 DL |
4751 | uint16_t *latencies; |
4752 | ||
4753 | if (INTEL_INFO(dev)->gen >= 9) | |
4754 | latencies = dev_priv->wm.skl_latency; | |
4755 | else | |
4756 | latencies = to_i915(dev)->wm.cur_latency; | |
369a1342 | 4757 | |
97e94b22 | 4758 | return wm_latency_write(file, ubuf, len, offp, latencies); |
369a1342 VS |
4759 | } |
4760 | ||
4761 | static const struct file_operations i915_pri_wm_latency_fops = { | |
4762 | .owner = THIS_MODULE, | |
4763 | .open = pri_wm_latency_open, | |
4764 | .read = seq_read, | |
4765 | .llseek = seq_lseek, | |
4766 | .release = single_release, | |
4767 | .write = pri_wm_latency_write | |
4768 | }; | |
4769 | ||
4770 | static const struct file_operations i915_spr_wm_latency_fops = { | |
4771 | .owner = THIS_MODULE, | |
4772 | .open = spr_wm_latency_open, | |
4773 | .read = seq_read, | |
4774 | .llseek = seq_lseek, | |
4775 | .release = single_release, | |
4776 | .write = spr_wm_latency_write | |
4777 | }; | |
4778 | ||
4779 | static const struct file_operations i915_cur_wm_latency_fops = { | |
4780 | .owner = THIS_MODULE, | |
4781 | .open = cur_wm_latency_open, | |
4782 | .read = seq_read, | |
4783 | .llseek = seq_lseek, | |
4784 | .release = single_release, | |
4785 | .write = cur_wm_latency_write | |
4786 | }; | |
4787 | ||
647416f9 KC |
4788 | static int |
4789 | i915_wedged_get(void *data, u64 *val) | |
f3cd474b | 4790 | { |
647416f9 | 4791 | struct drm_device *dev = data; |
fac5e23e | 4792 | struct drm_i915_private *dev_priv = to_i915(dev); |
f3cd474b | 4793 | |
d98c52cf | 4794 | *val = i915_terminally_wedged(&dev_priv->gpu_error); |
f3cd474b | 4795 | |
647416f9 | 4796 | return 0; |
f3cd474b CW |
4797 | } |
4798 | ||
647416f9 KC |
4799 | static int |
4800 | i915_wedged_set(void *data, u64 val) | |
f3cd474b | 4801 | { |
647416f9 | 4802 | struct drm_device *dev = data; |
fac5e23e | 4803 | struct drm_i915_private *dev_priv = to_i915(dev); |
d46c0517 | 4804 | |
b8d24a06 MK |
4805 | /* |
4806 | * There is no safeguard against this debugfs entry colliding | |
4807 | * with the hangcheck calling same i915_handle_error() in | |
4808 | * parallel, causing an explosion. For now we assume that the | |
4809 | * test harness is responsible enough not to inject gpu hangs | |
4810 | * while it is writing to 'i915_wedged' | |
4811 | */ | |
4812 | ||
d98c52cf | 4813 | if (i915_reset_in_progress(&dev_priv->gpu_error)) |
b8d24a06 MK |
4814 | return -EAGAIN; |
4815 | ||
d46c0517 | 4816 | intel_runtime_pm_get(dev_priv); |
f3cd474b | 4817 | |
c033666a | 4818 | i915_handle_error(dev_priv, val, |
58174462 | 4819 | "Manually setting wedged to %llu", val); |
d46c0517 ID |
4820 | |
4821 | intel_runtime_pm_put(dev_priv); | |
4822 | ||
647416f9 | 4823 | return 0; |
f3cd474b CW |
4824 | } |
4825 | ||
647416f9 KC |
4826 | DEFINE_SIMPLE_ATTRIBUTE(i915_wedged_fops, |
4827 | i915_wedged_get, i915_wedged_set, | |
3a3b4f98 | 4828 | "%llu\n"); |
f3cd474b | 4829 | |
094f9a54 CW |
4830 | static int |
4831 | i915_ring_missed_irq_get(void *data, u64 *val) | |
4832 | { | |
4833 | struct drm_device *dev = data; | |
fac5e23e | 4834 | struct drm_i915_private *dev_priv = to_i915(dev); |
094f9a54 CW |
4835 | |
4836 | *val = dev_priv->gpu_error.missed_irq_rings; | |
4837 | return 0; | |
4838 | } | |
4839 | ||
4840 | static int | |
4841 | i915_ring_missed_irq_set(void *data, u64 val) | |
4842 | { | |
4843 | struct drm_device *dev = data; | |
fac5e23e | 4844 | struct drm_i915_private *dev_priv = to_i915(dev); |
094f9a54 CW |
4845 | int ret; |
4846 | ||
4847 | /* Lock against concurrent debugfs callers */ | |
4848 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
4849 | if (ret) | |
4850 | return ret; | |
4851 | dev_priv->gpu_error.missed_irq_rings = val; | |
4852 | mutex_unlock(&dev->struct_mutex); | |
4853 | ||
4854 | return 0; | |
4855 | } | |
4856 | ||
4857 | DEFINE_SIMPLE_ATTRIBUTE(i915_ring_missed_irq_fops, | |
4858 | i915_ring_missed_irq_get, i915_ring_missed_irq_set, | |
4859 | "0x%08llx\n"); | |
4860 | ||
4861 | static int | |
4862 | i915_ring_test_irq_get(void *data, u64 *val) | |
4863 | { | |
4864 | struct drm_device *dev = data; | |
fac5e23e | 4865 | struct drm_i915_private *dev_priv = to_i915(dev); |
094f9a54 CW |
4866 | |
4867 | *val = dev_priv->gpu_error.test_irq_rings; | |
4868 | ||
4869 | return 0; | |
4870 | } | |
4871 | ||
4872 | static int | |
4873 | i915_ring_test_irq_set(void *data, u64 val) | |
4874 | { | |
4875 | struct drm_device *dev = data; | |
fac5e23e | 4876 | struct drm_i915_private *dev_priv = to_i915(dev); |
094f9a54 | 4877 | |
3a122c27 | 4878 | val &= INTEL_INFO(dev_priv)->ring_mask; |
094f9a54 | 4879 | DRM_DEBUG_DRIVER("Masking interrupts on rings 0x%08llx\n", val); |
094f9a54 | 4880 | dev_priv->gpu_error.test_irq_rings = val; |
094f9a54 CW |
4881 | |
4882 | return 0; | |
4883 | } | |
4884 | ||
4885 | DEFINE_SIMPLE_ATTRIBUTE(i915_ring_test_irq_fops, | |
4886 | i915_ring_test_irq_get, i915_ring_test_irq_set, | |
4887 | "0x%08llx\n"); | |
4888 | ||
dd624afd CW |
4889 | #define DROP_UNBOUND 0x1 |
4890 | #define DROP_BOUND 0x2 | |
4891 | #define DROP_RETIRE 0x4 | |
4892 | #define DROP_ACTIVE 0x8 | |
4893 | #define DROP_ALL (DROP_UNBOUND | \ | |
4894 | DROP_BOUND | \ | |
4895 | DROP_RETIRE | \ | |
4896 | DROP_ACTIVE) | |
647416f9 KC |
4897 | static int |
4898 | i915_drop_caches_get(void *data, u64 *val) | |
dd624afd | 4899 | { |
647416f9 | 4900 | *val = DROP_ALL; |
dd624afd | 4901 | |
647416f9 | 4902 | return 0; |
dd624afd CW |
4903 | } |
4904 | ||
647416f9 KC |
4905 | static int |
4906 | i915_drop_caches_set(void *data, u64 val) | |
dd624afd | 4907 | { |
647416f9 | 4908 | struct drm_device *dev = data; |
fac5e23e | 4909 | struct drm_i915_private *dev_priv = to_i915(dev); |
647416f9 | 4910 | int ret; |
dd624afd | 4911 | |
2f9fe5ff | 4912 | DRM_DEBUG("Dropping caches: 0x%08llx\n", val); |
dd624afd CW |
4913 | |
4914 | /* No need to check and wait for gpu resets, only libdrm auto-restarts | |
4915 | * on ioctls on -EAGAIN. */ | |
4916 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
4917 | if (ret) | |
4918 | return ret; | |
4919 | ||
4920 | if (val & DROP_ACTIVE) { | |
dcff85c8 | 4921 | ret = i915_gem_wait_for_idle(dev_priv, true); |
dd624afd CW |
4922 | if (ret) |
4923 | goto unlock; | |
4924 | } | |
4925 | ||
4926 | if (val & (DROP_RETIRE | DROP_ACTIVE)) | |
c033666a | 4927 | i915_gem_retire_requests(dev_priv); |
dd624afd | 4928 | |
21ab4e74 CW |
4929 | if (val & DROP_BOUND) |
4930 | i915_gem_shrink(dev_priv, LONG_MAX, I915_SHRINK_BOUND); | |
4ad72b7f | 4931 | |
21ab4e74 CW |
4932 | if (val & DROP_UNBOUND) |
4933 | i915_gem_shrink(dev_priv, LONG_MAX, I915_SHRINK_UNBOUND); | |
dd624afd CW |
4934 | |
4935 | unlock: | |
4936 | mutex_unlock(&dev->struct_mutex); | |
4937 | ||
647416f9 | 4938 | return ret; |
dd624afd CW |
4939 | } |
4940 | ||
647416f9 KC |
4941 | DEFINE_SIMPLE_ATTRIBUTE(i915_drop_caches_fops, |
4942 | i915_drop_caches_get, i915_drop_caches_set, | |
4943 | "0x%08llx\n"); | |
dd624afd | 4944 | |
647416f9 KC |
4945 | static int |
4946 | i915_max_freq_get(void *data, u64 *val) | |
358733e9 | 4947 | { |
647416f9 | 4948 | struct drm_device *dev = data; |
fac5e23e | 4949 | struct drm_i915_private *dev_priv = to_i915(dev); |
004777cb | 4950 | |
daa3afb2 | 4951 | if (INTEL_INFO(dev)->gen < 6) |
004777cb DV |
4952 | return -ENODEV; |
4953 | ||
7c59a9c1 | 4954 | *val = intel_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit); |
647416f9 | 4955 | return 0; |
358733e9 JB |
4956 | } |
4957 | ||
647416f9 KC |
4958 | static int |
4959 | i915_max_freq_set(void *data, u64 val) | |
358733e9 | 4960 | { |
647416f9 | 4961 | struct drm_device *dev = data; |
fac5e23e | 4962 | struct drm_i915_private *dev_priv = to_i915(dev); |
bc4d91f6 | 4963 | u32 hw_max, hw_min; |
647416f9 | 4964 | int ret; |
004777cb | 4965 | |
daa3afb2 | 4966 | if (INTEL_INFO(dev)->gen < 6) |
004777cb | 4967 | return -ENODEV; |
358733e9 | 4968 | |
647416f9 | 4969 | DRM_DEBUG_DRIVER("Manually setting max freq to %llu\n", val); |
358733e9 | 4970 | |
4fc688ce | 4971 | ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock); |
004777cb DV |
4972 | if (ret) |
4973 | return ret; | |
4974 | ||
358733e9 JB |
4975 | /* |
4976 | * Turbo will still be enabled, but won't go above the set value. | |
4977 | */ | |
bc4d91f6 | 4978 | val = intel_freq_opcode(dev_priv, val); |
dd0a1aa1 | 4979 | |
bc4d91f6 AG |
4980 | hw_max = dev_priv->rps.max_freq; |
4981 | hw_min = dev_priv->rps.min_freq; | |
dd0a1aa1 | 4982 | |
b39fb297 | 4983 | if (val < hw_min || val > hw_max || val < dev_priv->rps.min_freq_softlimit) { |
dd0a1aa1 JM |
4984 | mutex_unlock(&dev_priv->rps.hw_lock); |
4985 | return -EINVAL; | |
0a073b84 JB |
4986 | } |
4987 | ||
b39fb297 | 4988 | dev_priv->rps.max_freq_softlimit = val; |
dd0a1aa1 | 4989 | |
dc97997a | 4990 | intel_set_rps(dev_priv, val); |
dd0a1aa1 | 4991 | |
4fc688ce | 4992 | mutex_unlock(&dev_priv->rps.hw_lock); |
358733e9 | 4993 | |
647416f9 | 4994 | return 0; |
358733e9 JB |
4995 | } |
4996 | ||
647416f9 KC |
4997 | DEFINE_SIMPLE_ATTRIBUTE(i915_max_freq_fops, |
4998 | i915_max_freq_get, i915_max_freq_set, | |
3a3b4f98 | 4999 | "%llu\n"); |
358733e9 | 5000 | |
647416f9 KC |
5001 | static int |
5002 | i915_min_freq_get(void *data, u64 *val) | |
1523c310 | 5003 | { |
647416f9 | 5004 | struct drm_device *dev = data; |
fac5e23e | 5005 | struct drm_i915_private *dev_priv = to_i915(dev); |
004777cb | 5006 | |
62e1baa1 | 5007 | if (INTEL_GEN(dev_priv) < 6) |
004777cb DV |
5008 | return -ENODEV; |
5009 | ||
7c59a9c1 | 5010 | *val = intel_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit); |
647416f9 | 5011 | return 0; |
1523c310 JB |
5012 | } |
5013 | ||
647416f9 KC |
5014 | static int |
5015 | i915_min_freq_set(void *data, u64 val) | |
1523c310 | 5016 | { |
647416f9 | 5017 | struct drm_device *dev = data; |
fac5e23e | 5018 | struct drm_i915_private *dev_priv = to_i915(dev); |
bc4d91f6 | 5019 | u32 hw_max, hw_min; |
647416f9 | 5020 | int ret; |
004777cb | 5021 | |
62e1baa1 | 5022 | if (INTEL_GEN(dev_priv) < 6) |
004777cb | 5023 | return -ENODEV; |
1523c310 | 5024 | |
647416f9 | 5025 | DRM_DEBUG_DRIVER("Manually setting min freq to %llu\n", val); |
1523c310 | 5026 | |
4fc688ce | 5027 | ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock); |
004777cb DV |
5028 | if (ret) |
5029 | return ret; | |
5030 | ||
1523c310 JB |
5031 | /* |
5032 | * Turbo will still be enabled, but won't go below the set value. | |
5033 | */ | |
bc4d91f6 | 5034 | val = intel_freq_opcode(dev_priv, val); |
dd0a1aa1 | 5035 | |
bc4d91f6 AG |
5036 | hw_max = dev_priv->rps.max_freq; |
5037 | hw_min = dev_priv->rps.min_freq; | |
dd0a1aa1 | 5038 | |
b39fb297 | 5039 | if (val < hw_min || val > hw_max || val > dev_priv->rps.max_freq_softlimit) { |
dd0a1aa1 JM |
5040 | mutex_unlock(&dev_priv->rps.hw_lock); |
5041 | return -EINVAL; | |
0a073b84 | 5042 | } |
dd0a1aa1 | 5043 | |
b39fb297 | 5044 | dev_priv->rps.min_freq_softlimit = val; |
dd0a1aa1 | 5045 | |
dc97997a | 5046 | intel_set_rps(dev_priv, val); |
dd0a1aa1 | 5047 | |
4fc688ce | 5048 | mutex_unlock(&dev_priv->rps.hw_lock); |
1523c310 | 5049 | |
647416f9 | 5050 | return 0; |
1523c310 JB |
5051 | } |
5052 | ||
647416f9 KC |
5053 | DEFINE_SIMPLE_ATTRIBUTE(i915_min_freq_fops, |
5054 | i915_min_freq_get, i915_min_freq_set, | |
3a3b4f98 | 5055 | "%llu\n"); |
1523c310 | 5056 | |
647416f9 KC |
5057 | static int |
5058 | i915_cache_sharing_get(void *data, u64 *val) | |
07b7ddd9 | 5059 | { |
647416f9 | 5060 | struct drm_device *dev = data; |
fac5e23e | 5061 | struct drm_i915_private *dev_priv = to_i915(dev); |
07b7ddd9 | 5062 | u32 snpcr; |
647416f9 | 5063 | int ret; |
07b7ddd9 | 5064 | |
004777cb DV |
5065 | if (!(IS_GEN6(dev) || IS_GEN7(dev))) |
5066 | return -ENODEV; | |
5067 | ||
22bcfc6a DV |
5068 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
5069 | if (ret) | |
5070 | return ret; | |
c8c8fb33 | 5071 | intel_runtime_pm_get(dev_priv); |
22bcfc6a | 5072 | |
07b7ddd9 | 5073 | snpcr = I915_READ(GEN6_MBCUNIT_SNPCR); |
c8c8fb33 PZ |
5074 | |
5075 | intel_runtime_pm_put(dev_priv); | |
91c8a326 | 5076 | mutex_unlock(&dev_priv->drm.struct_mutex); |
07b7ddd9 | 5077 | |
647416f9 | 5078 | *val = (snpcr & GEN6_MBC_SNPCR_MASK) >> GEN6_MBC_SNPCR_SHIFT; |
07b7ddd9 | 5079 | |
647416f9 | 5080 | return 0; |
07b7ddd9 JB |
5081 | } |
5082 | ||
647416f9 KC |
5083 | static int |
5084 | i915_cache_sharing_set(void *data, u64 val) | |
07b7ddd9 | 5085 | { |
647416f9 | 5086 | struct drm_device *dev = data; |
fac5e23e | 5087 | struct drm_i915_private *dev_priv = to_i915(dev); |
07b7ddd9 | 5088 | u32 snpcr; |
07b7ddd9 | 5089 | |
004777cb DV |
5090 | if (!(IS_GEN6(dev) || IS_GEN7(dev))) |
5091 | return -ENODEV; | |
5092 | ||
647416f9 | 5093 | if (val > 3) |
07b7ddd9 JB |
5094 | return -EINVAL; |
5095 | ||
c8c8fb33 | 5096 | intel_runtime_pm_get(dev_priv); |
647416f9 | 5097 | DRM_DEBUG_DRIVER("Manually setting uncore sharing to %llu\n", val); |
07b7ddd9 JB |
5098 | |
5099 | /* Update the cache sharing policy here as well */ | |
5100 | snpcr = I915_READ(GEN6_MBCUNIT_SNPCR); | |
5101 | snpcr &= ~GEN6_MBC_SNPCR_MASK; | |
5102 | snpcr |= (val << GEN6_MBC_SNPCR_SHIFT); | |
5103 | I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr); | |
5104 | ||
c8c8fb33 | 5105 | intel_runtime_pm_put(dev_priv); |
647416f9 | 5106 | return 0; |
07b7ddd9 JB |
5107 | } |
5108 | ||
647416f9 KC |
5109 | DEFINE_SIMPLE_ATTRIBUTE(i915_cache_sharing_fops, |
5110 | i915_cache_sharing_get, i915_cache_sharing_set, | |
5111 | "%llu\n"); | |
07b7ddd9 | 5112 | |
5d39525a JM |
5113 | struct sseu_dev_status { |
5114 | unsigned int slice_total; | |
5115 | unsigned int subslice_total; | |
5116 | unsigned int subslice_per_slice; | |
5117 | unsigned int eu_total; | |
5118 | unsigned int eu_per_subslice; | |
5119 | }; | |
5120 | ||
5121 | static void cherryview_sseu_device_status(struct drm_device *dev, | |
5122 | struct sseu_dev_status *stat) | |
5123 | { | |
fac5e23e | 5124 | struct drm_i915_private *dev_priv = to_i915(dev); |
0a0b457f | 5125 | int ss_max = 2; |
5d39525a JM |
5126 | int ss; |
5127 | u32 sig1[ss_max], sig2[ss_max]; | |
5128 | ||
5129 | sig1[0] = I915_READ(CHV_POWER_SS0_SIG1); | |
5130 | sig1[1] = I915_READ(CHV_POWER_SS1_SIG1); | |
5131 | sig2[0] = I915_READ(CHV_POWER_SS0_SIG2); | |
5132 | sig2[1] = I915_READ(CHV_POWER_SS1_SIG2); | |
5133 | ||
5134 | for (ss = 0; ss < ss_max; ss++) { | |
5135 | unsigned int eu_cnt; | |
5136 | ||
5137 | if (sig1[ss] & CHV_SS_PG_ENABLE) | |
5138 | /* skip disabled subslice */ | |
5139 | continue; | |
5140 | ||
5141 | stat->slice_total = 1; | |
5142 | stat->subslice_per_slice++; | |
5143 | eu_cnt = ((sig1[ss] & CHV_EU08_PG_ENABLE) ? 0 : 2) + | |
5144 | ((sig1[ss] & CHV_EU19_PG_ENABLE) ? 0 : 2) + | |
5145 | ((sig1[ss] & CHV_EU210_PG_ENABLE) ? 0 : 2) + | |
5146 | ((sig2[ss] & CHV_EU311_PG_ENABLE) ? 0 : 2); | |
5147 | stat->eu_total += eu_cnt; | |
5148 | stat->eu_per_subslice = max(stat->eu_per_subslice, eu_cnt); | |
5149 | } | |
5150 | stat->subslice_total = stat->subslice_per_slice; | |
5151 | } | |
5152 | ||
5153 | static void gen9_sseu_device_status(struct drm_device *dev, | |
5154 | struct sseu_dev_status *stat) | |
5155 | { | |
fac5e23e | 5156 | struct drm_i915_private *dev_priv = to_i915(dev); |
1c046bc1 | 5157 | int s_max = 3, ss_max = 4; |
5d39525a JM |
5158 | int s, ss; |
5159 | u32 s_reg[s_max], eu_reg[2*s_max], eu_mask[2]; | |
5160 | ||
1c046bc1 JM |
5161 | /* BXT has a single slice and at most 3 subslices. */ |
5162 | if (IS_BROXTON(dev)) { | |
5163 | s_max = 1; | |
5164 | ss_max = 3; | |
5165 | } | |
5166 | ||
5167 | for (s = 0; s < s_max; s++) { | |
5168 | s_reg[s] = I915_READ(GEN9_SLICE_PGCTL_ACK(s)); | |
5169 | eu_reg[2*s] = I915_READ(GEN9_SS01_EU_PGCTL_ACK(s)); | |
5170 | eu_reg[2*s + 1] = I915_READ(GEN9_SS23_EU_PGCTL_ACK(s)); | |
5171 | } | |
5172 | ||
5d39525a JM |
5173 | eu_mask[0] = GEN9_PGCTL_SSA_EU08_ACK | |
5174 | GEN9_PGCTL_SSA_EU19_ACK | | |
5175 | GEN9_PGCTL_SSA_EU210_ACK | | |
5176 | GEN9_PGCTL_SSA_EU311_ACK; | |
5177 | eu_mask[1] = GEN9_PGCTL_SSB_EU08_ACK | | |
5178 | GEN9_PGCTL_SSB_EU19_ACK | | |
5179 | GEN9_PGCTL_SSB_EU210_ACK | | |
5180 | GEN9_PGCTL_SSB_EU311_ACK; | |
5181 | ||
5182 | for (s = 0; s < s_max; s++) { | |
1c046bc1 JM |
5183 | unsigned int ss_cnt = 0; |
5184 | ||
5d39525a JM |
5185 | if ((s_reg[s] & GEN9_PGCTL_SLICE_ACK) == 0) |
5186 | /* skip disabled slice */ | |
5187 | continue; | |
5188 | ||
5189 | stat->slice_total++; | |
1c046bc1 | 5190 | |
ef11bdb3 | 5191 | if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) |
1c046bc1 JM |
5192 | ss_cnt = INTEL_INFO(dev)->subslice_per_slice; |
5193 | ||
5d39525a JM |
5194 | for (ss = 0; ss < ss_max; ss++) { |
5195 | unsigned int eu_cnt; | |
5196 | ||
1c046bc1 JM |
5197 | if (IS_BROXTON(dev) && |
5198 | !(s_reg[s] & (GEN9_PGCTL_SS_ACK(ss)))) | |
5199 | /* skip disabled subslice */ | |
5200 | continue; | |
5201 | ||
5202 | if (IS_BROXTON(dev)) | |
5203 | ss_cnt++; | |
5204 | ||
5d39525a JM |
5205 | eu_cnt = 2 * hweight32(eu_reg[2*s + ss/2] & |
5206 | eu_mask[ss%2]); | |
5207 | stat->eu_total += eu_cnt; | |
5208 | stat->eu_per_subslice = max(stat->eu_per_subslice, | |
5209 | eu_cnt); | |
5210 | } | |
1c046bc1 JM |
5211 | |
5212 | stat->subslice_total += ss_cnt; | |
5213 | stat->subslice_per_slice = max(stat->subslice_per_slice, | |
5214 | ss_cnt); | |
5d39525a JM |
5215 | } |
5216 | } | |
5217 | ||
91bedd34 ŁD |
5218 | static void broadwell_sseu_device_status(struct drm_device *dev, |
5219 | struct sseu_dev_status *stat) | |
5220 | { | |
fac5e23e | 5221 | struct drm_i915_private *dev_priv = to_i915(dev); |
91bedd34 ŁD |
5222 | int s; |
5223 | u32 slice_info = I915_READ(GEN8_GT_SLICE_INFO); | |
5224 | ||
5225 | stat->slice_total = hweight32(slice_info & GEN8_LSLICESTAT_MASK); | |
5226 | ||
5227 | if (stat->slice_total) { | |
5228 | stat->subslice_per_slice = INTEL_INFO(dev)->subslice_per_slice; | |
5229 | stat->subslice_total = stat->slice_total * | |
5230 | stat->subslice_per_slice; | |
5231 | stat->eu_per_subslice = INTEL_INFO(dev)->eu_per_subslice; | |
5232 | stat->eu_total = stat->eu_per_subslice * stat->subslice_total; | |
5233 | ||
5234 | /* subtract fused off EU(s) from enabled slice(s) */ | |
5235 | for (s = 0; s < stat->slice_total; s++) { | |
5236 | u8 subslice_7eu = INTEL_INFO(dev)->subslice_7eu[s]; | |
5237 | ||
5238 | stat->eu_total -= hweight8(subslice_7eu); | |
5239 | } | |
5240 | } | |
5241 | } | |
5242 | ||
3873218f JM |
5243 | static int i915_sseu_status(struct seq_file *m, void *unused) |
5244 | { | |
5245 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
238010ed DW |
5246 | struct drm_i915_private *dev_priv = to_i915(node->minor->dev); |
5247 | struct drm_device *dev = &dev_priv->drm; | |
5d39525a | 5248 | struct sseu_dev_status stat; |
3873218f | 5249 | |
91bedd34 | 5250 | if (INTEL_INFO(dev)->gen < 8) |
3873218f JM |
5251 | return -ENODEV; |
5252 | ||
5253 | seq_puts(m, "SSEU Device Info\n"); | |
5254 | seq_printf(m, " Available Slice Total: %u\n", | |
5255 | INTEL_INFO(dev)->slice_total); | |
5256 | seq_printf(m, " Available Subslice Total: %u\n", | |
5257 | INTEL_INFO(dev)->subslice_total); | |
5258 | seq_printf(m, " Available Subslice Per Slice: %u\n", | |
5259 | INTEL_INFO(dev)->subslice_per_slice); | |
5260 | seq_printf(m, " Available EU Total: %u\n", | |
5261 | INTEL_INFO(dev)->eu_total); | |
5262 | seq_printf(m, " Available EU Per Subslice: %u\n", | |
5263 | INTEL_INFO(dev)->eu_per_subslice); | |
33e141ed | 5264 | seq_printf(m, " Has Pooled EU: %s\n", yesno(HAS_POOLED_EU(dev))); |
5265 | if (HAS_POOLED_EU(dev)) | |
5266 | seq_printf(m, " Min EU in pool: %u\n", | |
5267 | INTEL_INFO(dev)->min_eu_in_pool); | |
3873218f JM |
5268 | seq_printf(m, " Has Slice Power Gating: %s\n", |
5269 | yesno(INTEL_INFO(dev)->has_slice_pg)); | |
5270 | seq_printf(m, " Has Subslice Power Gating: %s\n", | |
5271 | yesno(INTEL_INFO(dev)->has_subslice_pg)); | |
5272 | seq_printf(m, " Has EU Power Gating: %s\n", | |
5273 | yesno(INTEL_INFO(dev)->has_eu_pg)); | |
5274 | ||
7f992aba | 5275 | seq_puts(m, "SSEU Device Status\n"); |
5d39525a | 5276 | memset(&stat, 0, sizeof(stat)); |
238010ed DW |
5277 | |
5278 | intel_runtime_pm_get(dev_priv); | |
5279 | ||
5575f03a | 5280 | if (IS_CHERRYVIEW(dev)) { |
5d39525a | 5281 | cherryview_sseu_device_status(dev, &stat); |
91bedd34 ŁD |
5282 | } else if (IS_BROADWELL(dev)) { |
5283 | broadwell_sseu_device_status(dev, &stat); | |
1c046bc1 | 5284 | } else if (INTEL_INFO(dev)->gen >= 9) { |
5d39525a | 5285 | gen9_sseu_device_status(dev, &stat); |
7f992aba | 5286 | } |
238010ed DW |
5287 | |
5288 | intel_runtime_pm_put(dev_priv); | |
5289 | ||
5d39525a JM |
5290 | seq_printf(m, " Enabled Slice Total: %u\n", |
5291 | stat.slice_total); | |
5292 | seq_printf(m, " Enabled Subslice Total: %u\n", | |
5293 | stat.subslice_total); | |
5294 | seq_printf(m, " Enabled Subslice Per Slice: %u\n", | |
5295 | stat.subslice_per_slice); | |
5296 | seq_printf(m, " Enabled EU Total: %u\n", | |
5297 | stat.eu_total); | |
5298 | seq_printf(m, " Enabled EU Per Subslice: %u\n", | |
5299 | stat.eu_per_subslice); | |
7f992aba | 5300 | |
3873218f JM |
5301 | return 0; |
5302 | } | |
5303 | ||
6d794d42 BW |
5304 | static int i915_forcewake_open(struct inode *inode, struct file *file) |
5305 | { | |
5306 | struct drm_device *dev = inode->i_private; | |
fac5e23e | 5307 | struct drm_i915_private *dev_priv = to_i915(dev); |
6d794d42 | 5308 | |
075edca4 | 5309 | if (INTEL_INFO(dev)->gen < 6) |
6d794d42 BW |
5310 | return 0; |
5311 | ||
6daccb0b | 5312 | intel_runtime_pm_get(dev_priv); |
59bad947 | 5313 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); |
6d794d42 BW |
5314 | |
5315 | return 0; | |
5316 | } | |
5317 | ||
c43b5634 | 5318 | static int i915_forcewake_release(struct inode *inode, struct file *file) |
6d794d42 BW |
5319 | { |
5320 | struct drm_device *dev = inode->i_private; | |
fac5e23e | 5321 | struct drm_i915_private *dev_priv = to_i915(dev); |
6d794d42 | 5322 | |
075edca4 | 5323 | if (INTEL_INFO(dev)->gen < 6) |
6d794d42 BW |
5324 | return 0; |
5325 | ||
59bad947 | 5326 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); |
6daccb0b | 5327 | intel_runtime_pm_put(dev_priv); |
6d794d42 BW |
5328 | |
5329 | return 0; | |
5330 | } | |
5331 | ||
5332 | static const struct file_operations i915_forcewake_fops = { | |
5333 | .owner = THIS_MODULE, | |
5334 | .open = i915_forcewake_open, | |
5335 | .release = i915_forcewake_release, | |
5336 | }; | |
5337 | ||
5338 | static int i915_forcewake_create(struct dentry *root, struct drm_minor *minor) | |
5339 | { | |
5340 | struct drm_device *dev = minor->dev; | |
5341 | struct dentry *ent; | |
5342 | ||
5343 | ent = debugfs_create_file("i915_forcewake_user", | |
8eb57294 | 5344 | S_IRUSR, |
6d794d42 BW |
5345 | root, dev, |
5346 | &i915_forcewake_fops); | |
f3c5fe97 WY |
5347 | if (!ent) |
5348 | return -ENOMEM; | |
6d794d42 | 5349 | |
8eb57294 | 5350 | return drm_add_fake_info_node(minor, ent, &i915_forcewake_fops); |
6d794d42 BW |
5351 | } |
5352 | ||
6a9c308d DV |
5353 | static int i915_debugfs_create(struct dentry *root, |
5354 | struct drm_minor *minor, | |
5355 | const char *name, | |
5356 | const struct file_operations *fops) | |
07b7ddd9 JB |
5357 | { |
5358 | struct drm_device *dev = minor->dev; | |
5359 | struct dentry *ent; | |
5360 | ||
6a9c308d | 5361 | ent = debugfs_create_file(name, |
07b7ddd9 JB |
5362 | S_IRUGO | S_IWUSR, |
5363 | root, dev, | |
6a9c308d | 5364 | fops); |
f3c5fe97 WY |
5365 | if (!ent) |
5366 | return -ENOMEM; | |
07b7ddd9 | 5367 | |
6a9c308d | 5368 | return drm_add_fake_info_node(minor, ent, fops); |
07b7ddd9 JB |
5369 | } |
5370 | ||
06c5bf8c | 5371 | static const struct drm_info_list i915_debugfs_list[] = { |
311bd68e | 5372 | {"i915_capabilities", i915_capabilities, 0}, |
73aa808f | 5373 | {"i915_gem_objects", i915_gem_object_info, 0}, |
08c18323 | 5374 | {"i915_gem_gtt", i915_gem_gtt_info, 0}, |
1b50247a | 5375 | {"i915_gem_pinned", i915_gem_gtt_info, 0, (void *) PINNED_LIST}, |
6d2b8885 | 5376 | {"i915_gem_stolen", i915_gem_stolen_list_info }, |
4e5359cd | 5377 | {"i915_gem_pageflip", i915_gem_pageflip_info, 0}, |
2017263e BG |
5378 | {"i915_gem_request", i915_gem_request_info, 0}, |
5379 | {"i915_gem_seqno", i915_gem_seqno_info, 0}, | |
a6172a80 | 5380 | {"i915_gem_fence_regs", i915_gem_fence_regs_info, 0}, |
2017263e | 5381 | {"i915_gem_interrupt", i915_interrupt_info, 0}, |
1ec14ad3 CW |
5382 | {"i915_gem_hws", i915_hws_info, 0, (void *)RCS}, |
5383 | {"i915_gem_hws_blt", i915_hws_info, 0, (void *)BCS}, | |
5384 | {"i915_gem_hws_bsd", i915_hws_info, 0, (void *)VCS}, | |
9010ebfd | 5385 | {"i915_gem_hws_vebox", i915_hws_info, 0, (void *)VECS}, |
493018dc | 5386 | {"i915_gem_batch_pool", i915_gem_batch_pool_info, 0}, |
8b417c26 | 5387 | {"i915_guc_info", i915_guc_info, 0}, |
fdf5d357 | 5388 | {"i915_guc_load_status", i915_guc_load_status_info, 0}, |
4c7e77fc | 5389 | {"i915_guc_log_dump", i915_guc_log_dump, 0}, |
adb4bd12 | 5390 | {"i915_frequency_info", i915_frequency_info, 0}, |
f654449a | 5391 | {"i915_hangcheck_info", i915_hangcheck_info, 0}, |
f97108d1 | 5392 | {"i915_drpc_info", i915_drpc_info, 0}, |
7648fa99 | 5393 | {"i915_emon_status", i915_emon_status, 0}, |
23b2f8bb | 5394 | {"i915_ring_freq_table", i915_ring_freq_table, 0}, |
9a851789 | 5395 | {"i915_frontbuffer_tracking", i915_frontbuffer_tracking, 0}, |
b5e50c3f | 5396 | {"i915_fbc_status", i915_fbc_status, 0}, |
92d44621 | 5397 | {"i915_ips_status", i915_ips_status, 0}, |
4a9bef37 | 5398 | {"i915_sr_status", i915_sr_status, 0}, |
44834a67 | 5399 | {"i915_opregion", i915_opregion, 0}, |
ada8f955 | 5400 | {"i915_vbt", i915_vbt, 0}, |
37811fcc | 5401 | {"i915_gem_framebuffer", i915_gem_framebuffer_info, 0}, |
e76d3630 | 5402 | {"i915_context_status", i915_context_status, 0}, |
c0ab1ae9 | 5403 | {"i915_dump_lrc", i915_dump_lrc, 0}, |
4ba70e44 | 5404 | {"i915_execlists", i915_execlists, 0}, |
f65367b5 | 5405 | {"i915_forcewake_domains", i915_forcewake_domains, 0}, |
ea16a3cd | 5406 | {"i915_swizzle_info", i915_swizzle_info, 0}, |
3cf17fc5 | 5407 | {"i915_ppgtt_info", i915_ppgtt_info, 0}, |
63573eb7 | 5408 | {"i915_llc", i915_llc, 0}, |
e91fd8c6 | 5409 | {"i915_edp_psr_status", i915_edp_psr_status, 0}, |
d2e216d0 | 5410 | {"i915_sink_crc_eDP1", i915_sink_crc, 0}, |
ec013e7f | 5411 | {"i915_energy_uJ", i915_energy_uJ, 0}, |
6455c870 | 5412 | {"i915_runtime_pm_status", i915_runtime_pm_status, 0}, |
1da51581 | 5413 | {"i915_power_domain_info", i915_power_domain_info, 0}, |
b7cec66d | 5414 | {"i915_dmc_info", i915_dmc_info, 0}, |
53f5e3ca | 5415 | {"i915_display_info", i915_display_info, 0}, |
e04934cf | 5416 | {"i915_semaphore_status", i915_semaphore_status, 0}, |
728e29d7 | 5417 | {"i915_shared_dplls_info", i915_shared_dplls_info, 0}, |
11bed958 | 5418 | {"i915_dp_mst_info", i915_dp_mst_info, 0}, |
1ed1ef9d | 5419 | {"i915_wa_registers", i915_wa_registers, 0}, |
c5511e44 | 5420 | {"i915_ddb_info", i915_ddb_info, 0}, |
3873218f | 5421 | {"i915_sseu_status", i915_sseu_status, 0}, |
a54746e3 | 5422 | {"i915_drrs_status", i915_drrs_status, 0}, |
1854d5ca | 5423 | {"i915_rps_boost_info", i915_rps_boost_info, 0}, |
2017263e | 5424 | }; |
27c202ad | 5425 | #define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list) |
2017263e | 5426 | |
06c5bf8c | 5427 | static const struct i915_debugfs_files { |
34b9674c DV |
5428 | const char *name; |
5429 | const struct file_operations *fops; | |
5430 | } i915_debugfs_files[] = { | |
5431 | {"i915_wedged", &i915_wedged_fops}, | |
5432 | {"i915_max_freq", &i915_max_freq_fops}, | |
5433 | {"i915_min_freq", &i915_min_freq_fops}, | |
5434 | {"i915_cache_sharing", &i915_cache_sharing_fops}, | |
094f9a54 CW |
5435 | {"i915_ring_missed_irq", &i915_ring_missed_irq_fops}, |
5436 | {"i915_ring_test_irq", &i915_ring_test_irq_fops}, | |
34b9674c DV |
5437 | {"i915_gem_drop_caches", &i915_drop_caches_fops}, |
5438 | {"i915_error_state", &i915_error_state_fops}, | |
5439 | {"i915_next_seqno", &i915_next_seqno_fops}, | |
bd9db02f | 5440 | {"i915_display_crc_ctl", &i915_display_crc_ctl_fops}, |
369a1342 VS |
5441 | {"i915_pri_wm_latency", &i915_pri_wm_latency_fops}, |
5442 | {"i915_spr_wm_latency", &i915_spr_wm_latency_fops}, | |
5443 | {"i915_cur_wm_latency", &i915_cur_wm_latency_fops}, | |
da46f936 | 5444 | {"i915_fbc_false_color", &i915_fbc_fc_fops}, |
eb3394fa TP |
5445 | {"i915_dp_test_data", &i915_displayport_test_data_fops}, |
5446 | {"i915_dp_test_type", &i915_displayport_test_type_fops}, | |
5447 | {"i915_dp_test_active", &i915_displayport_test_active_fops} | |
34b9674c DV |
5448 | }; |
5449 | ||
07144428 DL |
5450 | void intel_display_crc_init(struct drm_device *dev) |
5451 | { | |
fac5e23e | 5452 | struct drm_i915_private *dev_priv = to_i915(dev); |
b378360e | 5453 | enum pipe pipe; |
07144428 | 5454 | |
055e393f | 5455 | for_each_pipe(dev_priv, pipe) { |
b378360e | 5456 | struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe]; |
07144428 | 5457 | |
d538bbdf DL |
5458 | pipe_crc->opened = false; |
5459 | spin_lock_init(&pipe_crc->lock); | |
07144428 DL |
5460 | init_waitqueue_head(&pipe_crc->wq); |
5461 | } | |
5462 | } | |
5463 | ||
1dac891c | 5464 | int i915_debugfs_register(struct drm_i915_private *dev_priv) |
2017263e | 5465 | { |
91c8a326 | 5466 | struct drm_minor *minor = dev_priv->drm.primary; |
34b9674c | 5467 | int ret, i; |
f3cd474b | 5468 | |
6d794d42 | 5469 | ret = i915_forcewake_create(minor->debugfs_root, minor); |
358733e9 JB |
5470 | if (ret) |
5471 | return ret; | |
6a9c308d | 5472 | |
07144428 DL |
5473 | for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) { |
5474 | ret = i915_pipe_crc_create(minor->debugfs_root, minor, i); | |
5475 | if (ret) | |
5476 | return ret; | |
5477 | } | |
5478 | ||
34b9674c DV |
5479 | for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) { |
5480 | ret = i915_debugfs_create(minor->debugfs_root, minor, | |
5481 | i915_debugfs_files[i].name, | |
5482 | i915_debugfs_files[i].fops); | |
5483 | if (ret) | |
5484 | return ret; | |
5485 | } | |
40633219 | 5486 | |
27c202ad BG |
5487 | return drm_debugfs_create_files(i915_debugfs_list, |
5488 | I915_DEBUGFS_ENTRIES, | |
2017263e BG |
5489 | minor->debugfs_root, minor); |
5490 | } | |
5491 | ||
1dac891c | 5492 | void i915_debugfs_unregister(struct drm_i915_private *dev_priv) |
2017263e | 5493 | { |
91c8a326 | 5494 | struct drm_minor *minor = dev_priv->drm.primary; |
34b9674c DV |
5495 | int i; |
5496 | ||
27c202ad BG |
5497 | drm_debugfs_remove_files(i915_debugfs_list, |
5498 | I915_DEBUGFS_ENTRIES, minor); | |
07144428 | 5499 | |
6d794d42 BW |
5500 | drm_debugfs_remove_files((struct drm_info_list *) &i915_forcewake_fops, |
5501 | 1, minor); | |
07144428 | 5502 | |
e309a997 | 5503 | for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) { |
07144428 DL |
5504 | struct drm_info_list *info_list = |
5505 | (struct drm_info_list *)&i915_pipe_crc_data[i]; | |
5506 | ||
5507 | drm_debugfs_remove_files(info_list, 1, minor); | |
5508 | } | |
5509 | ||
34b9674c DV |
5510 | for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) { |
5511 | struct drm_info_list *info_list = | |
5512 | (struct drm_info_list *) i915_debugfs_files[i].fops; | |
5513 | ||
5514 | drm_debugfs_remove_files(info_list, 1, minor); | |
5515 | } | |
2017263e | 5516 | } |
aa7471d2 JN |
5517 | |
5518 | struct dpcd_block { | |
5519 | /* DPCD dump start address. */ | |
5520 | unsigned int offset; | |
5521 | /* DPCD dump end address, inclusive. If unset, .size will be used. */ | |
5522 | unsigned int end; | |
5523 | /* DPCD dump size. Used if .end is unset. If unset, defaults to 1. */ | |
5524 | size_t size; | |
5525 | /* Only valid for eDP. */ | |
5526 | bool edp; | |
5527 | }; | |
5528 | ||
5529 | static const struct dpcd_block i915_dpcd_debug[] = { | |
5530 | { .offset = DP_DPCD_REV, .size = DP_RECEIVER_CAP_SIZE }, | |
5531 | { .offset = DP_PSR_SUPPORT, .end = DP_PSR_CAPS }, | |
5532 | { .offset = DP_DOWNSTREAM_PORT_0, .size = 16 }, | |
5533 | { .offset = DP_LINK_BW_SET, .end = DP_EDP_CONFIGURATION_SET }, | |
5534 | { .offset = DP_SINK_COUNT, .end = DP_ADJUST_REQUEST_LANE2_3 }, | |
5535 | { .offset = DP_SET_POWER }, | |
5536 | { .offset = DP_EDP_DPCD_REV }, | |
5537 | { .offset = DP_EDP_GENERAL_CAP_1, .end = DP_EDP_GENERAL_CAP_3 }, | |
5538 | { .offset = DP_EDP_DISPLAY_CONTROL_REGISTER, .end = DP_EDP_BACKLIGHT_FREQ_CAP_MAX_LSB }, | |
5539 | { .offset = DP_EDP_DBC_MINIMUM_BRIGHTNESS_SET, .end = DP_EDP_DBC_MAXIMUM_BRIGHTNESS_SET }, | |
5540 | }; | |
5541 | ||
5542 | static int i915_dpcd_show(struct seq_file *m, void *data) | |
5543 | { | |
5544 | struct drm_connector *connector = m->private; | |
5545 | struct intel_dp *intel_dp = | |
5546 | enc_to_intel_dp(&intel_attached_encoder(connector)->base); | |
5547 | uint8_t buf[16]; | |
5548 | ssize_t err; | |
5549 | int i; | |
5550 | ||
5c1a8875 MK |
5551 | if (connector->status != connector_status_connected) |
5552 | return -ENODEV; | |
5553 | ||
aa7471d2 JN |
5554 | for (i = 0; i < ARRAY_SIZE(i915_dpcd_debug); i++) { |
5555 | const struct dpcd_block *b = &i915_dpcd_debug[i]; | |
5556 | size_t size = b->end ? b->end - b->offset + 1 : (b->size ?: 1); | |
5557 | ||
5558 | if (b->edp && | |
5559 | connector->connector_type != DRM_MODE_CONNECTOR_eDP) | |
5560 | continue; | |
5561 | ||
5562 | /* low tech for now */ | |
5563 | if (WARN_ON(size > sizeof(buf))) | |
5564 | continue; | |
5565 | ||
5566 | err = drm_dp_dpcd_read(&intel_dp->aux, b->offset, buf, size); | |
5567 | if (err <= 0) { | |
5568 | DRM_ERROR("dpcd read (%zu bytes at %u) failed (%zd)\n", | |
5569 | size, b->offset, err); | |
5570 | continue; | |
5571 | } | |
5572 | ||
5573 | seq_printf(m, "%04x: %*ph\n", b->offset, (int) size, buf); | |
b3f9d7d7 | 5574 | } |
aa7471d2 JN |
5575 | |
5576 | return 0; | |
5577 | } | |
5578 | ||
5579 | static int i915_dpcd_open(struct inode *inode, struct file *file) | |
5580 | { | |
5581 | return single_open(file, i915_dpcd_show, inode->i_private); | |
5582 | } | |
5583 | ||
5584 | static const struct file_operations i915_dpcd_fops = { | |
5585 | .owner = THIS_MODULE, | |
5586 | .open = i915_dpcd_open, | |
5587 | .read = seq_read, | |
5588 | .llseek = seq_lseek, | |
5589 | .release = single_release, | |
5590 | }; | |
5591 | ||
5592 | /** | |
5593 | * i915_debugfs_connector_add - add i915 specific connector debugfs files | |
5594 | * @connector: pointer to a registered drm_connector | |
5595 | * | |
5596 | * Cleanup will be done by drm_connector_unregister() through a call to | |
5597 | * drm_debugfs_connector_remove(). | |
5598 | * | |
5599 | * Returns 0 on success, negative error codes on error. | |
5600 | */ | |
5601 | int i915_debugfs_connector_add(struct drm_connector *connector) | |
5602 | { | |
5603 | struct dentry *root = connector->debugfs_entry; | |
5604 | ||
5605 | /* The connector must have been registered beforehands. */ | |
5606 | if (!root) | |
5607 | return -ENODEV; | |
5608 | ||
5609 | if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort || | |
5610 | connector->connector_type == DRM_MODE_CONNECTOR_eDP) | |
5611 | debugfs_create_file("i915_dpcd", S_IRUGO, root, connector, | |
5612 | &i915_dpcd_fops); | |
5613 | ||
5614 | return 0; | |
5615 | } |