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Commit | Line | Data |
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2017263e BG |
1 | /* |
2 | * Copyright © 2008 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | * Keith Packard <keithp@keithp.com> | |
26 | * | |
27 | */ | |
28 | ||
29 | #include <linux/seq_file.h> | |
b2c88f5b | 30 | #include <linux/circ_buf.h> |
926321d5 | 31 | #include <linux/ctype.h> |
f3cd474b | 32 | #include <linux/debugfs.h> |
5a0e3ad6 | 33 | #include <linux/slab.h> |
2d1a8a48 | 34 | #include <linux/export.h> |
6d2b8885 | 35 | #include <linux/list_sort.h> |
ec013e7f | 36 | #include <asm/msr-index.h> |
760285e7 | 37 | #include <drm/drmP.h> |
4e5359cd | 38 | #include "intel_drv.h" |
e5c65260 | 39 | #include "intel_ringbuffer.h" |
760285e7 | 40 | #include <drm/i915_drm.h> |
2017263e BG |
41 | #include "i915_drv.h" |
42 | ||
36cdd013 DW |
43 | static inline struct drm_i915_private *node_to_i915(struct drm_info_node *node) |
44 | { | |
45 | return to_i915(node->minor->dev); | |
46 | } | |
47 | ||
497666d8 DL |
48 | /* As the drm_debugfs_init() routines are called before dev->dev_private is |
49 | * allocated we need to hook into the minor for release. */ | |
50 | static int | |
51 | drm_add_fake_info_node(struct drm_minor *minor, | |
52 | struct dentry *ent, | |
53 | const void *key) | |
54 | { | |
55 | struct drm_info_node *node; | |
56 | ||
57 | node = kmalloc(sizeof(*node), GFP_KERNEL); | |
58 | if (node == NULL) { | |
59 | debugfs_remove(ent); | |
60 | return -ENOMEM; | |
61 | } | |
62 | ||
63 | node->minor = minor; | |
64 | node->dent = ent; | |
36cdd013 | 65 | node->info_ent = (void *)key; |
497666d8 DL |
66 | |
67 | mutex_lock(&minor->debugfs_lock); | |
68 | list_add(&node->list, &minor->debugfs_list); | |
69 | mutex_unlock(&minor->debugfs_lock); | |
70 | ||
71 | return 0; | |
72 | } | |
73 | ||
70d39fe4 CW |
74 | static int i915_capabilities(struct seq_file *m, void *data) |
75 | { | |
36cdd013 DW |
76 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
77 | const struct intel_device_info *info = INTEL_INFO(dev_priv); | |
70d39fe4 | 78 | |
36cdd013 DW |
79 | seq_printf(m, "gen: %d\n", INTEL_GEN(dev_priv)); |
80 | seq_printf(m, "pch: %d\n", INTEL_PCH_TYPE(dev_priv)); | |
79fc46df | 81 | #define PRINT_FLAG(x) seq_printf(m, #x ": %s\n", yesno(info->x)) |
604db650 | 82 | DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG); |
79fc46df | 83 | #undef PRINT_FLAG |
70d39fe4 CW |
84 | |
85 | return 0; | |
86 | } | |
2017263e | 87 | |
a7363de7 | 88 | static char get_active_flag(struct drm_i915_gem_object *obj) |
a6172a80 | 89 | { |
573adb39 | 90 | return i915_gem_object_is_active(obj) ? '*' : ' '; |
a6172a80 CW |
91 | } |
92 | ||
a7363de7 | 93 | static char get_pin_flag(struct drm_i915_gem_object *obj) |
be12a86b TU |
94 | { |
95 | return obj->pin_display ? 'p' : ' '; | |
96 | } | |
97 | ||
a7363de7 | 98 | static char get_tiling_flag(struct drm_i915_gem_object *obj) |
a6172a80 | 99 | { |
3e510a8e | 100 | switch (i915_gem_object_get_tiling(obj)) { |
0206e353 | 101 | default: |
be12a86b TU |
102 | case I915_TILING_NONE: return ' '; |
103 | case I915_TILING_X: return 'X'; | |
104 | case I915_TILING_Y: return 'Y'; | |
0206e353 | 105 | } |
a6172a80 CW |
106 | } |
107 | ||
a7363de7 | 108 | static char get_global_flag(struct drm_i915_gem_object *obj) |
be12a86b | 109 | { |
275f039d | 110 | return !list_empty(&obj->userfault_link) ? 'g' : ' '; |
be12a86b TU |
111 | } |
112 | ||
a7363de7 | 113 | static char get_pin_mapped_flag(struct drm_i915_gem_object *obj) |
1d693bcc | 114 | { |
a4f5ea64 | 115 | return obj->mm.mapping ? 'M' : ' '; |
1d693bcc BW |
116 | } |
117 | ||
ca1543be TU |
118 | static u64 i915_gem_obj_total_ggtt_size(struct drm_i915_gem_object *obj) |
119 | { | |
120 | u64 size = 0; | |
121 | struct i915_vma *vma; | |
122 | ||
1c7f4bca | 123 | list_for_each_entry(vma, &obj->vma_list, obj_link) { |
3272db53 | 124 | if (i915_vma_is_ggtt(vma) && drm_mm_node_allocated(&vma->node)) |
ca1543be TU |
125 | size += vma->node.size; |
126 | } | |
127 | ||
128 | return size; | |
129 | } | |
130 | ||
37811fcc CW |
131 | static void |
132 | describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj) | |
133 | { | |
b4716185 | 134 | struct drm_i915_private *dev_priv = to_i915(obj->base.dev); |
e2f80391 | 135 | struct intel_engine_cs *engine; |
1d693bcc | 136 | struct i915_vma *vma; |
faf5bf0a | 137 | unsigned int frontbuffer_bits; |
d7f46fc4 BW |
138 | int pin_count = 0; |
139 | ||
188c1ab7 CW |
140 | lockdep_assert_held(&obj->base.dev->struct_mutex); |
141 | ||
d07f0e59 | 142 | seq_printf(m, "%pK: %c%c%c%c%c %8zdKiB %02x %02x %s%s%s", |
37811fcc | 143 | &obj->base, |
be12a86b | 144 | get_active_flag(obj), |
37811fcc CW |
145 | get_pin_flag(obj), |
146 | get_tiling_flag(obj), | |
1d693bcc | 147 | get_global_flag(obj), |
be12a86b | 148 | get_pin_mapped_flag(obj), |
a05a5862 | 149 | obj->base.size / 1024, |
37811fcc | 150 | obj->base.read_domains, |
d07f0e59 | 151 | obj->base.write_domain, |
36cdd013 | 152 | i915_cache_level_str(dev_priv, obj->cache_level), |
a4f5ea64 CW |
153 | obj->mm.dirty ? " dirty" : "", |
154 | obj->mm.madv == I915_MADV_DONTNEED ? " purgeable" : ""); | |
37811fcc CW |
155 | if (obj->base.name) |
156 | seq_printf(m, " (name: %d)", obj->base.name); | |
1c7f4bca | 157 | list_for_each_entry(vma, &obj->vma_list, obj_link) { |
20dfbde4 | 158 | if (i915_vma_is_pinned(vma)) |
d7f46fc4 | 159 | pin_count++; |
ba0635ff DC |
160 | } |
161 | seq_printf(m, " (pinned x %d)", pin_count); | |
cc98b413 CW |
162 | if (obj->pin_display) |
163 | seq_printf(m, " (display)"); | |
1c7f4bca | 164 | list_for_each_entry(vma, &obj->vma_list, obj_link) { |
15717de2 CW |
165 | if (!drm_mm_node_allocated(&vma->node)) |
166 | continue; | |
167 | ||
8d2fdc3f | 168 | seq_printf(m, " (%sgtt offset: %08llx, size: %08llx", |
3272db53 | 169 | i915_vma_is_ggtt(vma) ? "g" : "pp", |
8d2fdc3f | 170 | vma->node.start, vma->node.size); |
3272db53 | 171 | if (i915_vma_is_ggtt(vma)) |
596c5923 | 172 | seq_printf(m, ", type: %u", vma->ggtt_view.type); |
49ef5294 CW |
173 | if (vma->fence) |
174 | seq_printf(m, " , fence: %d%s", | |
175 | vma->fence->id, | |
176 | i915_gem_active_isset(&vma->last_fence) ? "*" : ""); | |
596c5923 | 177 | seq_puts(m, ")"); |
1d693bcc | 178 | } |
c1ad11fc | 179 | if (obj->stolen) |
440fd528 | 180 | seq_printf(m, " (stolen: %08llx)", obj->stolen->start); |
27c01aae | 181 | |
d07f0e59 | 182 | engine = i915_gem_object_last_write_engine(obj); |
27c01aae CW |
183 | if (engine) |
184 | seq_printf(m, " (%s)", engine->name); | |
185 | ||
faf5bf0a CW |
186 | frontbuffer_bits = atomic_read(&obj->frontbuffer_bits); |
187 | if (frontbuffer_bits) | |
188 | seq_printf(m, " (frontbuffer: 0x%03x)", frontbuffer_bits); | |
37811fcc CW |
189 | } |
190 | ||
6d2b8885 CW |
191 | static int obj_rank_by_stolen(void *priv, |
192 | struct list_head *A, struct list_head *B) | |
193 | { | |
194 | struct drm_i915_gem_object *a = | |
b25cb2f8 | 195 | container_of(A, struct drm_i915_gem_object, obj_exec_link); |
6d2b8885 | 196 | struct drm_i915_gem_object *b = |
b25cb2f8 | 197 | container_of(B, struct drm_i915_gem_object, obj_exec_link); |
6d2b8885 | 198 | |
2d05fa16 RV |
199 | if (a->stolen->start < b->stolen->start) |
200 | return -1; | |
201 | if (a->stolen->start > b->stolen->start) | |
202 | return 1; | |
203 | return 0; | |
6d2b8885 CW |
204 | } |
205 | ||
206 | static int i915_gem_stolen_list_info(struct seq_file *m, void *data) | |
207 | { | |
36cdd013 DW |
208 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
209 | struct drm_device *dev = &dev_priv->drm; | |
6d2b8885 | 210 | struct drm_i915_gem_object *obj; |
c44ef60e | 211 | u64 total_obj_size, total_gtt_size; |
6d2b8885 CW |
212 | LIST_HEAD(stolen); |
213 | int count, ret; | |
214 | ||
215 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
216 | if (ret) | |
217 | return ret; | |
218 | ||
219 | total_obj_size = total_gtt_size = count = 0; | |
220 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) { | |
221 | if (obj->stolen == NULL) | |
222 | continue; | |
223 | ||
b25cb2f8 | 224 | list_add(&obj->obj_exec_link, &stolen); |
6d2b8885 CW |
225 | |
226 | total_obj_size += obj->base.size; | |
ca1543be | 227 | total_gtt_size += i915_gem_obj_total_ggtt_size(obj); |
6d2b8885 CW |
228 | count++; |
229 | } | |
230 | list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) { | |
231 | if (obj->stolen == NULL) | |
232 | continue; | |
233 | ||
b25cb2f8 | 234 | list_add(&obj->obj_exec_link, &stolen); |
6d2b8885 CW |
235 | |
236 | total_obj_size += obj->base.size; | |
237 | count++; | |
238 | } | |
239 | list_sort(NULL, &stolen, obj_rank_by_stolen); | |
240 | seq_puts(m, "Stolen:\n"); | |
241 | while (!list_empty(&stolen)) { | |
b25cb2f8 | 242 | obj = list_first_entry(&stolen, typeof(*obj), obj_exec_link); |
6d2b8885 CW |
243 | seq_puts(m, " "); |
244 | describe_obj(m, obj); | |
245 | seq_putc(m, '\n'); | |
b25cb2f8 | 246 | list_del_init(&obj->obj_exec_link); |
6d2b8885 CW |
247 | } |
248 | mutex_unlock(&dev->struct_mutex); | |
249 | ||
c44ef60e | 250 | seq_printf(m, "Total %d objects, %llu bytes, %llu GTT size\n", |
6d2b8885 CW |
251 | count, total_obj_size, total_gtt_size); |
252 | return 0; | |
253 | } | |
254 | ||
2db8e9d6 | 255 | struct file_stats { |
6313c204 | 256 | struct drm_i915_file_private *file_priv; |
c44ef60e MK |
257 | unsigned long count; |
258 | u64 total, unbound; | |
259 | u64 global, shared; | |
260 | u64 active, inactive; | |
2db8e9d6 CW |
261 | }; |
262 | ||
263 | static int per_file_stats(int id, void *ptr, void *data) | |
264 | { | |
265 | struct drm_i915_gem_object *obj = ptr; | |
266 | struct file_stats *stats = data; | |
6313c204 | 267 | struct i915_vma *vma; |
2db8e9d6 CW |
268 | |
269 | stats->count++; | |
270 | stats->total += obj->base.size; | |
15717de2 CW |
271 | if (!obj->bind_count) |
272 | stats->unbound += obj->base.size; | |
c67a17e9 CW |
273 | if (obj->base.name || obj->base.dma_buf) |
274 | stats->shared += obj->base.size; | |
275 | ||
894eeecc CW |
276 | list_for_each_entry(vma, &obj->vma_list, obj_link) { |
277 | if (!drm_mm_node_allocated(&vma->node)) | |
278 | continue; | |
6313c204 | 279 | |
3272db53 | 280 | if (i915_vma_is_ggtt(vma)) { |
894eeecc CW |
281 | stats->global += vma->node.size; |
282 | } else { | |
283 | struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vma->vm); | |
6313c204 | 284 | |
2bfa996e | 285 | if (ppgtt->base.file != stats->file_priv) |
6313c204 | 286 | continue; |
6313c204 | 287 | } |
894eeecc | 288 | |
b0decaf7 | 289 | if (i915_vma_is_active(vma)) |
894eeecc CW |
290 | stats->active += vma->node.size; |
291 | else | |
292 | stats->inactive += vma->node.size; | |
2db8e9d6 CW |
293 | } |
294 | ||
295 | return 0; | |
296 | } | |
297 | ||
b0da1b79 CW |
298 | #define print_file_stats(m, name, stats) do { \ |
299 | if (stats.count) \ | |
c44ef60e | 300 | seq_printf(m, "%s: %lu objects, %llu bytes (%llu active, %llu inactive, %llu global, %llu shared, %llu unbound)\n", \ |
b0da1b79 CW |
301 | name, \ |
302 | stats.count, \ | |
303 | stats.total, \ | |
304 | stats.active, \ | |
305 | stats.inactive, \ | |
306 | stats.global, \ | |
307 | stats.shared, \ | |
308 | stats.unbound); \ | |
309 | } while (0) | |
493018dc BV |
310 | |
311 | static void print_batch_pool_stats(struct seq_file *m, | |
312 | struct drm_i915_private *dev_priv) | |
313 | { | |
314 | struct drm_i915_gem_object *obj; | |
315 | struct file_stats stats; | |
e2f80391 | 316 | struct intel_engine_cs *engine; |
3b3f1650 | 317 | enum intel_engine_id id; |
b4ac5afc | 318 | int j; |
493018dc BV |
319 | |
320 | memset(&stats, 0, sizeof(stats)); | |
321 | ||
3b3f1650 | 322 | for_each_engine(engine, dev_priv, id) { |
e2f80391 | 323 | for (j = 0; j < ARRAY_SIZE(engine->batch_pool.cache_list); j++) { |
8d9d5744 | 324 | list_for_each_entry(obj, |
e2f80391 | 325 | &engine->batch_pool.cache_list[j], |
8d9d5744 CW |
326 | batch_pool_link) |
327 | per_file_stats(0, obj, &stats); | |
328 | } | |
06fbca71 | 329 | } |
493018dc | 330 | |
b0da1b79 | 331 | print_file_stats(m, "[k]batch pool", stats); |
493018dc BV |
332 | } |
333 | ||
15da9565 CW |
334 | static int per_file_ctx_stats(int id, void *ptr, void *data) |
335 | { | |
336 | struct i915_gem_context *ctx = ptr; | |
337 | int n; | |
338 | ||
339 | for (n = 0; n < ARRAY_SIZE(ctx->engine); n++) { | |
340 | if (ctx->engine[n].state) | |
bf3783e5 | 341 | per_file_stats(0, ctx->engine[n].state->obj, data); |
dca33ecc | 342 | if (ctx->engine[n].ring) |
57e88531 | 343 | per_file_stats(0, ctx->engine[n].ring->vma->obj, data); |
15da9565 CW |
344 | } |
345 | ||
346 | return 0; | |
347 | } | |
348 | ||
349 | static void print_context_stats(struct seq_file *m, | |
350 | struct drm_i915_private *dev_priv) | |
351 | { | |
36cdd013 | 352 | struct drm_device *dev = &dev_priv->drm; |
15da9565 CW |
353 | struct file_stats stats; |
354 | struct drm_file *file; | |
355 | ||
356 | memset(&stats, 0, sizeof(stats)); | |
357 | ||
36cdd013 | 358 | mutex_lock(&dev->struct_mutex); |
15da9565 CW |
359 | if (dev_priv->kernel_context) |
360 | per_file_ctx_stats(0, dev_priv->kernel_context, &stats); | |
361 | ||
36cdd013 | 362 | list_for_each_entry(file, &dev->filelist, lhead) { |
15da9565 CW |
363 | struct drm_i915_file_private *fpriv = file->driver_priv; |
364 | idr_for_each(&fpriv->context_idr, per_file_ctx_stats, &stats); | |
365 | } | |
36cdd013 | 366 | mutex_unlock(&dev->struct_mutex); |
15da9565 CW |
367 | |
368 | print_file_stats(m, "[k]contexts", stats); | |
369 | } | |
370 | ||
36cdd013 | 371 | static int i915_gem_object_info(struct seq_file *m, void *data) |
73aa808f | 372 | { |
36cdd013 DW |
373 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
374 | struct drm_device *dev = &dev_priv->drm; | |
72e96d64 | 375 | struct i915_ggtt *ggtt = &dev_priv->ggtt; |
2bd160a1 CW |
376 | u32 count, mapped_count, purgeable_count, dpy_count; |
377 | u64 size, mapped_size, purgeable_size, dpy_size; | |
6299f992 | 378 | struct drm_i915_gem_object *obj; |
2db8e9d6 | 379 | struct drm_file *file; |
73aa808f CW |
380 | int ret; |
381 | ||
382 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
383 | if (ret) | |
384 | return ret; | |
385 | ||
3ef7f228 | 386 | seq_printf(m, "%u objects, %llu bytes\n", |
6299f992 CW |
387 | dev_priv->mm.object_count, |
388 | dev_priv->mm.object_memory); | |
389 | ||
1544c42e CW |
390 | size = count = 0; |
391 | mapped_size = mapped_count = 0; | |
392 | purgeable_size = purgeable_count = 0; | |
35c20a60 | 393 | list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) { |
2bd160a1 CW |
394 | size += obj->base.size; |
395 | ++count; | |
396 | ||
a4f5ea64 | 397 | if (obj->mm.madv == I915_MADV_DONTNEED) { |
2bd160a1 CW |
398 | purgeable_size += obj->base.size; |
399 | ++purgeable_count; | |
400 | } | |
401 | ||
a4f5ea64 | 402 | if (obj->mm.mapping) { |
2bd160a1 CW |
403 | mapped_count++; |
404 | mapped_size += obj->base.size; | |
be19b10d | 405 | } |
b7abb714 | 406 | } |
c44ef60e | 407 | seq_printf(m, "%u unbound objects, %llu bytes\n", count, size); |
6c085a72 | 408 | |
2bd160a1 | 409 | size = count = dpy_size = dpy_count = 0; |
35c20a60 | 410 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) { |
2bd160a1 CW |
411 | size += obj->base.size; |
412 | ++count; | |
413 | ||
30154650 | 414 | if (obj->pin_display) { |
2bd160a1 CW |
415 | dpy_size += obj->base.size; |
416 | ++dpy_count; | |
6299f992 | 417 | } |
2bd160a1 | 418 | |
a4f5ea64 | 419 | if (obj->mm.madv == I915_MADV_DONTNEED) { |
b7abb714 CW |
420 | purgeable_size += obj->base.size; |
421 | ++purgeable_count; | |
422 | } | |
2bd160a1 | 423 | |
a4f5ea64 | 424 | if (obj->mm.mapping) { |
2bd160a1 CW |
425 | mapped_count++; |
426 | mapped_size += obj->base.size; | |
be19b10d | 427 | } |
6299f992 | 428 | } |
2bd160a1 CW |
429 | seq_printf(m, "%u bound objects, %llu bytes\n", |
430 | count, size); | |
c44ef60e | 431 | seq_printf(m, "%u purgeable objects, %llu bytes\n", |
b7abb714 | 432 | purgeable_count, purgeable_size); |
2bd160a1 CW |
433 | seq_printf(m, "%u mapped objects, %llu bytes\n", |
434 | mapped_count, mapped_size); | |
435 | seq_printf(m, "%u display objects (pinned), %llu bytes\n", | |
436 | dpy_count, dpy_size); | |
6299f992 | 437 | |
c44ef60e | 438 | seq_printf(m, "%llu [%llu] gtt total\n", |
72e96d64 | 439 | ggtt->base.total, ggtt->mappable_end - ggtt->base.start); |
73aa808f | 440 | |
493018dc BV |
441 | seq_putc(m, '\n'); |
442 | print_batch_pool_stats(m, dev_priv); | |
1d2ac403 DV |
443 | mutex_unlock(&dev->struct_mutex); |
444 | ||
445 | mutex_lock(&dev->filelist_mutex); | |
15da9565 | 446 | print_context_stats(m, dev_priv); |
2db8e9d6 CW |
447 | list_for_each_entry_reverse(file, &dev->filelist, lhead) { |
448 | struct file_stats stats; | |
c84455b4 CW |
449 | struct drm_i915_file_private *file_priv = file->driver_priv; |
450 | struct drm_i915_gem_request *request; | |
3ec2f427 | 451 | struct task_struct *task; |
2db8e9d6 CW |
452 | |
453 | memset(&stats, 0, sizeof(stats)); | |
6313c204 | 454 | stats.file_priv = file->driver_priv; |
5b5ffff0 | 455 | spin_lock(&file->table_lock); |
2db8e9d6 | 456 | idr_for_each(&file->object_idr, per_file_stats, &stats); |
5b5ffff0 | 457 | spin_unlock(&file->table_lock); |
3ec2f427 TH |
458 | /* |
459 | * Although we have a valid reference on file->pid, that does | |
460 | * not guarantee that the task_struct who called get_pid() is | |
461 | * still alive (e.g. get_pid(current) => fork() => exit()). | |
462 | * Therefore, we need to protect this ->comm access using RCU. | |
463 | */ | |
c84455b4 CW |
464 | mutex_lock(&dev->struct_mutex); |
465 | request = list_first_entry_or_null(&file_priv->mm.request_list, | |
466 | struct drm_i915_gem_request, | |
467 | client_list); | |
3ec2f427 | 468 | rcu_read_lock(); |
c84455b4 CW |
469 | task = pid_task(request && request->ctx->pid ? |
470 | request->ctx->pid : file->pid, | |
471 | PIDTYPE_PID); | |
493018dc | 472 | print_file_stats(m, task ? task->comm : "<unknown>", stats); |
3ec2f427 | 473 | rcu_read_unlock(); |
c84455b4 | 474 | mutex_unlock(&dev->struct_mutex); |
2db8e9d6 | 475 | } |
1d2ac403 | 476 | mutex_unlock(&dev->filelist_mutex); |
73aa808f CW |
477 | |
478 | return 0; | |
479 | } | |
480 | ||
aee56cff | 481 | static int i915_gem_gtt_info(struct seq_file *m, void *data) |
08c18323 | 482 | { |
9f25d007 | 483 | struct drm_info_node *node = m->private; |
36cdd013 DW |
484 | struct drm_i915_private *dev_priv = node_to_i915(node); |
485 | struct drm_device *dev = &dev_priv->drm; | |
5f4b091a | 486 | bool show_pin_display_only = !!node->info_ent->data; |
08c18323 | 487 | struct drm_i915_gem_object *obj; |
c44ef60e | 488 | u64 total_obj_size, total_gtt_size; |
08c18323 CW |
489 | int count, ret; |
490 | ||
491 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
492 | if (ret) | |
493 | return ret; | |
494 | ||
495 | total_obj_size = total_gtt_size = count = 0; | |
35c20a60 | 496 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) { |
6da84829 | 497 | if (show_pin_display_only && !obj->pin_display) |
1b50247a CW |
498 | continue; |
499 | ||
267f0c90 | 500 | seq_puts(m, " "); |
08c18323 | 501 | describe_obj(m, obj); |
267f0c90 | 502 | seq_putc(m, '\n'); |
08c18323 | 503 | total_obj_size += obj->base.size; |
ca1543be | 504 | total_gtt_size += i915_gem_obj_total_ggtt_size(obj); |
08c18323 CW |
505 | count++; |
506 | } | |
507 | ||
508 | mutex_unlock(&dev->struct_mutex); | |
509 | ||
c44ef60e | 510 | seq_printf(m, "Total %d objects, %llu bytes, %llu GTT size\n", |
08c18323 CW |
511 | count, total_obj_size, total_gtt_size); |
512 | ||
513 | return 0; | |
514 | } | |
515 | ||
4e5359cd SF |
516 | static int i915_gem_pageflip_info(struct seq_file *m, void *data) |
517 | { | |
36cdd013 DW |
518 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
519 | struct drm_device *dev = &dev_priv->drm; | |
4e5359cd | 520 | struct intel_crtc *crtc; |
8a270ebf DV |
521 | int ret; |
522 | ||
523 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
524 | if (ret) | |
525 | return ret; | |
4e5359cd | 526 | |
d3fcc808 | 527 | for_each_intel_crtc(dev, crtc) { |
9db4a9c7 JB |
528 | const char pipe = pipe_name(crtc->pipe); |
529 | const char plane = plane_name(crtc->plane); | |
51cbaf01 | 530 | struct intel_flip_work *work; |
4e5359cd | 531 | |
5e2d7afc | 532 | spin_lock_irq(&dev->event_lock); |
5a21b665 DV |
533 | work = crtc->flip_work; |
534 | if (work == NULL) { | |
9db4a9c7 | 535 | seq_printf(m, "No flip due on pipe %c (plane %c)\n", |
4e5359cd SF |
536 | pipe, plane); |
537 | } else { | |
5a21b665 DV |
538 | u32 pending; |
539 | u32 addr; | |
540 | ||
541 | pending = atomic_read(&work->pending); | |
542 | if (pending) { | |
543 | seq_printf(m, "Flip ioctl preparing on pipe %c (plane %c)\n", | |
544 | pipe, plane); | |
545 | } else { | |
546 | seq_printf(m, "Flip pending (waiting for vsync) on pipe %c (plane %c)\n", | |
547 | pipe, plane); | |
548 | } | |
549 | if (work->flip_queued_req) { | |
550 | struct intel_engine_cs *engine = i915_gem_request_get_engine(work->flip_queued_req); | |
551 | ||
552 | seq_printf(m, "Flip queued on %s at seqno %x, next seqno %x [current breadcrumb %x], completed? %d\n", | |
553 | engine->name, | |
554 | i915_gem_request_get_seqno(work->flip_queued_req), | |
555 | dev_priv->next_seqno, | |
1b7744e7 | 556 | intel_engine_get_seqno(engine), |
f69a02c9 | 557 | i915_gem_request_completed(work->flip_queued_req)); |
5a21b665 DV |
558 | } else |
559 | seq_printf(m, "Flip not associated with any ring\n"); | |
560 | seq_printf(m, "Flip queued on frame %d, (was ready on frame %d), now %d\n", | |
561 | work->flip_queued_vblank, | |
562 | work->flip_ready_vblank, | |
563 | intel_crtc_get_vblank_counter(crtc)); | |
564 | seq_printf(m, "%d prepares\n", atomic_read(&work->pending)); | |
565 | ||
36cdd013 | 566 | if (INTEL_GEN(dev_priv) >= 4) |
5a21b665 DV |
567 | addr = I915_HI_DISPBASE(I915_READ(DSPSURF(crtc->plane))); |
568 | else | |
569 | addr = I915_READ(DSPADDR(crtc->plane)); | |
570 | seq_printf(m, "Current scanout address 0x%08x\n", addr); | |
571 | ||
572 | if (work->pending_flip_obj) { | |
573 | seq_printf(m, "New framebuffer address 0x%08lx\n", (long)work->gtt_offset); | |
574 | seq_printf(m, "MMIO update completed? %d\n", addr == work->gtt_offset); | |
4e5359cd SF |
575 | } |
576 | } | |
5e2d7afc | 577 | spin_unlock_irq(&dev->event_lock); |
4e5359cd SF |
578 | } |
579 | ||
8a270ebf DV |
580 | mutex_unlock(&dev->struct_mutex); |
581 | ||
4e5359cd SF |
582 | return 0; |
583 | } | |
584 | ||
493018dc BV |
585 | static int i915_gem_batch_pool_info(struct seq_file *m, void *data) |
586 | { | |
36cdd013 DW |
587 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
588 | struct drm_device *dev = &dev_priv->drm; | |
493018dc | 589 | struct drm_i915_gem_object *obj; |
e2f80391 | 590 | struct intel_engine_cs *engine; |
3b3f1650 | 591 | enum intel_engine_id id; |
8d9d5744 | 592 | int total = 0; |
b4ac5afc | 593 | int ret, j; |
493018dc BV |
594 | |
595 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
596 | if (ret) | |
597 | return ret; | |
598 | ||
3b3f1650 | 599 | for_each_engine(engine, dev_priv, id) { |
e2f80391 | 600 | for (j = 0; j < ARRAY_SIZE(engine->batch_pool.cache_list); j++) { |
8d9d5744 CW |
601 | int count; |
602 | ||
603 | count = 0; | |
604 | list_for_each_entry(obj, | |
e2f80391 | 605 | &engine->batch_pool.cache_list[j], |
8d9d5744 CW |
606 | batch_pool_link) |
607 | count++; | |
608 | seq_printf(m, "%s cache[%d]: %d objects\n", | |
e2f80391 | 609 | engine->name, j, count); |
8d9d5744 CW |
610 | |
611 | list_for_each_entry(obj, | |
e2f80391 | 612 | &engine->batch_pool.cache_list[j], |
8d9d5744 CW |
613 | batch_pool_link) { |
614 | seq_puts(m, " "); | |
615 | describe_obj(m, obj); | |
616 | seq_putc(m, '\n'); | |
617 | } | |
618 | ||
619 | total += count; | |
06fbca71 | 620 | } |
493018dc BV |
621 | } |
622 | ||
8d9d5744 | 623 | seq_printf(m, "total: %d\n", total); |
493018dc BV |
624 | |
625 | mutex_unlock(&dev->struct_mutex); | |
626 | ||
627 | return 0; | |
628 | } | |
629 | ||
1b36595f CW |
630 | static void print_request(struct seq_file *m, |
631 | struct drm_i915_gem_request *rq, | |
632 | const char *prefix) | |
633 | { | |
634 | struct pid *pid = rq->ctx->pid; | |
635 | struct task_struct *task; | |
636 | ||
637 | rcu_read_lock(); | |
638 | task = pid ? pid_task(pid, PIDTYPE_PID) : NULL; | |
639 | seq_printf(m, "%s%x [%x:%x] @ %d: %s [%d]\n", prefix, | |
640 | rq->fence.seqno, rq->ctx->hw_id, rq->fence.seqno, | |
641 | jiffies_to_msecs(jiffies - rq->emitted_jiffies), | |
642 | task ? task->comm : "<unknown>", | |
643 | task ? task->pid : -1); | |
644 | rcu_read_unlock(); | |
645 | } | |
646 | ||
2017263e BG |
647 | static int i915_gem_request_info(struct seq_file *m, void *data) |
648 | { | |
36cdd013 DW |
649 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
650 | struct drm_device *dev = &dev_priv->drm; | |
eed29a5b | 651 | struct drm_i915_gem_request *req; |
3b3f1650 AG |
652 | struct intel_engine_cs *engine; |
653 | enum intel_engine_id id; | |
b4ac5afc | 654 | int ret, any; |
de227ef0 CW |
655 | |
656 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
657 | if (ret) | |
658 | return ret; | |
2017263e | 659 | |
2d1070b2 | 660 | any = 0; |
3b3f1650 | 661 | for_each_engine(engine, dev_priv, id) { |
2d1070b2 CW |
662 | int count; |
663 | ||
664 | count = 0; | |
efdf7c06 | 665 | list_for_each_entry(req, &engine->request_list, link) |
2d1070b2 CW |
666 | count++; |
667 | if (count == 0) | |
a2c7f6fd CW |
668 | continue; |
669 | ||
e2f80391 | 670 | seq_printf(m, "%s requests: %d\n", engine->name, count); |
1b36595f CW |
671 | list_for_each_entry(req, &engine->request_list, link) |
672 | print_request(m, req, " "); | |
2d1070b2 CW |
673 | |
674 | any++; | |
2017263e | 675 | } |
de227ef0 CW |
676 | mutex_unlock(&dev->struct_mutex); |
677 | ||
2d1070b2 | 678 | if (any == 0) |
267f0c90 | 679 | seq_puts(m, "No requests\n"); |
c2c347a9 | 680 | |
2017263e BG |
681 | return 0; |
682 | } | |
683 | ||
b2223497 | 684 | static void i915_ring_seqno_info(struct seq_file *m, |
0bc40be8 | 685 | struct intel_engine_cs *engine) |
b2223497 | 686 | { |
688e6c72 CW |
687 | struct intel_breadcrumbs *b = &engine->breadcrumbs; |
688 | struct rb_node *rb; | |
689 | ||
12471ba8 | 690 | seq_printf(m, "Current sequence (%s): %x\n", |
1b7744e7 | 691 | engine->name, intel_engine_get_seqno(engine)); |
688e6c72 CW |
692 | |
693 | spin_lock(&b->lock); | |
694 | for (rb = rb_first(&b->waiters); rb; rb = rb_next(rb)) { | |
695 | struct intel_wait *w = container_of(rb, typeof(*w), node); | |
696 | ||
697 | seq_printf(m, "Waiting (%s): %s [%d] on %x\n", | |
698 | engine->name, w->tsk->comm, w->tsk->pid, w->seqno); | |
699 | } | |
700 | spin_unlock(&b->lock); | |
b2223497 CW |
701 | } |
702 | ||
2017263e BG |
703 | static int i915_gem_seqno_info(struct seq_file *m, void *data) |
704 | { | |
36cdd013 | 705 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
e2f80391 | 706 | struct intel_engine_cs *engine; |
3b3f1650 | 707 | enum intel_engine_id id; |
2017263e | 708 | |
3b3f1650 | 709 | for_each_engine(engine, dev_priv, id) |
e2f80391 | 710 | i915_ring_seqno_info(m, engine); |
de227ef0 | 711 | |
2017263e BG |
712 | return 0; |
713 | } | |
714 | ||
715 | ||
716 | static int i915_interrupt_info(struct seq_file *m, void *data) | |
717 | { | |
36cdd013 | 718 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
e2f80391 | 719 | struct intel_engine_cs *engine; |
3b3f1650 | 720 | enum intel_engine_id id; |
4bb05040 | 721 | int i, pipe; |
de227ef0 | 722 | |
c8c8fb33 | 723 | intel_runtime_pm_get(dev_priv); |
2017263e | 724 | |
36cdd013 | 725 | if (IS_CHERRYVIEW(dev_priv)) { |
74e1ca8c VS |
726 | seq_printf(m, "Master Interrupt Control:\t%08x\n", |
727 | I915_READ(GEN8_MASTER_IRQ)); | |
728 | ||
729 | seq_printf(m, "Display IER:\t%08x\n", | |
730 | I915_READ(VLV_IER)); | |
731 | seq_printf(m, "Display IIR:\t%08x\n", | |
732 | I915_READ(VLV_IIR)); | |
733 | seq_printf(m, "Display IIR_RW:\t%08x\n", | |
734 | I915_READ(VLV_IIR_RW)); | |
735 | seq_printf(m, "Display IMR:\t%08x\n", | |
736 | I915_READ(VLV_IMR)); | |
9c870d03 CW |
737 | for_each_pipe(dev_priv, pipe) { |
738 | enum intel_display_power_domain power_domain; | |
739 | ||
740 | power_domain = POWER_DOMAIN_PIPE(pipe); | |
741 | if (!intel_display_power_get_if_enabled(dev_priv, | |
742 | power_domain)) { | |
743 | seq_printf(m, "Pipe %c power disabled\n", | |
744 | pipe_name(pipe)); | |
745 | continue; | |
746 | } | |
747 | ||
74e1ca8c VS |
748 | seq_printf(m, "Pipe %c stat:\t%08x\n", |
749 | pipe_name(pipe), | |
750 | I915_READ(PIPESTAT(pipe))); | |
751 | ||
9c870d03 CW |
752 | intel_display_power_put(dev_priv, power_domain); |
753 | } | |
754 | ||
755 | intel_display_power_get(dev_priv, POWER_DOMAIN_INIT); | |
74e1ca8c VS |
756 | seq_printf(m, "Port hotplug:\t%08x\n", |
757 | I915_READ(PORT_HOTPLUG_EN)); | |
758 | seq_printf(m, "DPFLIPSTAT:\t%08x\n", | |
759 | I915_READ(VLV_DPFLIPSTAT)); | |
760 | seq_printf(m, "DPINVGTT:\t%08x\n", | |
761 | I915_READ(DPINVGTT)); | |
9c870d03 | 762 | intel_display_power_put(dev_priv, POWER_DOMAIN_INIT); |
74e1ca8c VS |
763 | |
764 | for (i = 0; i < 4; i++) { | |
765 | seq_printf(m, "GT Interrupt IMR %d:\t%08x\n", | |
766 | i, I915_READ(GEN8_GT_IMR(i))); | |
767 | seq_printf(m, "GT Interrupt IIR %d:\t%08x\n", | |
768 | i, I915_READ(GEN8_GT_IIR(i))); | |
769 | seq_printf(m, "GT Interrupt IER %d:\t%08x\n", | |
770 | i, I915_READ(GEN8_GT_IER(i))); | |
771 | } | |
772 | ||
773 | seq_printf(m, "PCU interrupt mask:\t%08x\n", | |
774 | I915_READ(GEN8_PCU_IMR)); | |
775 | seq_printf(m, "PCU interrupt identity:\t%08x\n", | |
776 | I915_READ(GEN8_PCU_IIR)); | |
777 | seq_printf(m, "PCU interrupt enable:\t%08x\n", | |
778 | I915_READ(GEN8_PCU_IER)); | |
36cdd013 | 779 | } else if (INTEL_GEN(dev_priv) >= 8) { |
a123f157 BW |
780 | seq_printf(m, "Master Interrupt Control:\t%08x\n", |
781 | I915_READ(GEN8_MASTER_IRQ)); | |
782 | ||
783 | for (i = 0; i < 4; i++) { | |
784 | seq_printf(m, "GT Interrupt IMR %d:\t%08x\n", | |
785 | i, I915_READ(GEN8_GT_IMR(i))); | |
786 | seq_printf(m, "GT Interrupt IIR %d:\t%08x\n", | |
787 | i, I915_READ(GEN8_GT_IIR(i))); | |
788 | seq_printf(m, "GT Interrupt IER %d:\t%08x\n", | |
789 | i, I915_READ(GEN8_GT_IER(i))); | |
790 | } | |
791 | ||
055e393f | 792 | for_each_pipe(dev_priv, pipe) { |
e129649b ID |
793 | enum intel_display_power_domain power_domain; |
794 | ||
795 | power_domain = POWER_DOMAIN_PIPE(pipe); | |
796 | if (!intel_display_power_get_if_enabled(dev_priv, | |
797 | power_domain)) { | |
22c59960 PZ |
798 | seq_printf(m, "Pipe %c power disabled\n", |
799 | pipe_name(pipe)); | |
800 | continue; | |
801 | } | |
a123f157 | 802 | seq_printf(m, "Pipe %c IMR:\t%08x\n", |
07d27e20 DL |
803 | pipe_name(pipe), |
804 | I915_READ(GEN8_DE_PIPE_IMR(pipe))); | |
a123f157 | 805 | seq_printf(m, "Pipe %c IIR:\t%08x\n", |
07d27e20 DL |
806 | pipe_name(pipe), |
807 | I915_READ(GEN8_DE_PIPE_IIR(pipe))); | |
a123f157 | 808 | seq_printf(m, "Pipe %c IER:\t%08x\n", |
07d27e20 DL |
809 | pipe_name(pipe), |
810 | I915_READ(GEN8_DE_PIPE_IER(pipe))); | |
e129649b ID |
811 | |
812 | intel_display_power_put(dev_priv, power_domain); | |
a123f157 BW |
813 | } |
814 | ||
815 | seq_printf(m, "Display Engine port interrupt mask:\t%08x\n", | |
816 | I915_READ(GEN8_DE_PORT_IMR)); | |
817 | seq_printf(m, "Display Engine port interrupt identity:\t%08x\n", | |
818 | I915_READ(GEN8_DE_PORT_IIR)); | |
819 | seq_printf(m, "Display Engine port interrupt enable:\t%08x\n", | |
820 | I915_READ(GEN8_DE_PORT_IER)); | |
821 | ||
822 | seq_printf(m, "Display Engine misc interrupt mask:\t%08x\n", | |
823 | I915_READ(GEN8_DE_MISC_IMR)); | |
824 | seq_printf(m, "Display Engine misc interrupt identity:\t%08x\n", | |
825 | I915_READ(GEN8_DE_MISC_IIR)); | |
826 | seq_printf(m, "Display Engine misc interrupt enable:\t%08x\n", | |
827 | I915_READ(GEN8_DE_MISC_IER)); | |
828 | ||
829 | seq_printf(m, "PCU interrupt mask:\t%08x\n", | |
830 | I915_READ(GEN8_PCU_IMR)); | |
831 | seq_printf(m, "PCU interrupt identity:\t%08x\n", | |
832 | I915_READ(GEN8_PCU_IIR)); | |
833 | seq_printf(m, "PCU interrupt enable:\t%08x\n", | |
834 | I915_READ(GEN8_PCU_IER)); | |
36cdd013 | 835 | } else if (IS_VALLEYVIEW(dev_priv)) { |
7e231dbe JB |
836 | seq_printf(m, "Display IER:\t%08x\n", |
837 | I915_READ(VLV_IER)); | |
838 | seq_printf(m, "Display IIR:\t%08x\n", | |
839 | I915_READ(VLV_IIR)); | |
840 | seq_printf(m, "Display IIR_RW:\t%08x\n", | |
841 | I915_READ(VLV_IIR_RW)); | |
842 | seq_printf(m, "Display IMR:\t%08x\n", | |
843 | I915_READ(VLV_IMR)); | |
055e393f | 844 | for_each_pipe(dev_priv, pipe) |
7e231dbe JB |
845 | seq_printf(m, "Pipe %c stat:\t%08x\n", |
846 | pipe_name(pipe), | |
847 | I915_READ(PIPESTAT(pipe))); | |
848 | ||
849 | seq_printf(m, "Master IER:\t%08x\n", | |
850 | I915_READ(VLV_MASTER_IER)); | |
851 | ||
852 | seq_printf(m, "Render IER:\t%08x\n", | |
853 | I915_READ(GTIER)); | |
854 | seq_printf(m, "Render IIR:\t%08x\n", | |
855 | I915_READ(GTIIR)); | |
856 | seq_printf(m, "Render IMR:\t%08x\n", | |
857 | I915_READ(GTIMR)); | |
858 | ||
859 | seq_printf(m, "PM IER:\t\t%08x\n", | |
860 | I915_READ(GEN6_PMIER)); | |
861 | seq_printf(m, "PM IIR:\t\t%08x\n", | |
862 | I915_READ(GEN6_PMIIR)); | |
863 | seq_printf(m, "PM IMR:\t\t%08x\n", | |
864 | I915_READ(GEN6_PMIMR)); | |
865 | ||
866 | seq_printf(m, "Port hotplug:\t%08x\n", | |
867 | I915_READ(PORT_HOTPLUG_EN)); | |
868 | seq_printf(m, "DPFLIPSTAT:\t%08x\n", | |
869 | I915_READ(VLV_DPFLIPSTAT)); | |
870 | seq_printf(m, "DPINVGTT:\t%08x\n", | |
871 | I915_READ(DPINVGTT)); | |
872 | ||
36cdd013 | 873 | } else if (!HAS_PCH_SPLIT(dev_priv)) { |
5f6a1695 ZW |
874 | seq_printf(m, "Interrupt enable: %08x\n", |
875 | I915_READ(IER)); | |
876 | seq_printf(m, "Interrupt identity: %08x\n", | |
877 | I915_READ(IIR)); | |
878 | seq_printf(m, "Interrupt mask: %08x\n", | |
879 | I915_READ(IMR)); | |
055e393f | 880 | for_each_pipe(dev_priv, pipe) |
9db4a9c7 JB |
881 | seq_printf(m, "Pipe %c stat: %08x\n", |
882 | pipe_name(pipe), | |
883 | I915_READ(PIPESTAT(pipe))); | |
5f6a1695 ZW |
884 | } else { |
885 | seq_printf(m, "North Display Interrupt enable: %08x\n", | |
886 | I915_READ(DEIER)); | |
887 | seq_printf(m, "North Display Interrupt identity: %08x\n", | |
888 | I915_READ(DEIIR)); | |
889 | seq_printf(m, "North Display Interrupt mask: %08x\n", | |
890 | I915_READ(DEIMR)); | |
891 | seq_printf(m, "South Display Interrupt enable: %08x\n", | |
892 | I915_READ(SDEIER)); | |
893 | seq_printf(m, "South Display Interrupt identity: %08x\n", | |
894 | I915_READ(SDEIIR)); | |
895 | seq_printf(m, "South Display Interrupt mask: %08x\n", | |
896 | I915_READ(SDEIMR)); | |
897 | seq_printf(m, "Graphics Interrupt enable: %08x\n", | |
898 | I915_READ(GTIER)); | |
899 | seq_printf(m, "Graphics Interrupt identity: %08x\n", | |
900 | I915_READ(GTIIR)); | |
901 | seq_printf(m, "Graphics Interrupt mask: %08x\n", | |
902 | I915_READ(GTIMR)); | |
903 | } | |
3b3f1650 | 904 | for_each_engine(engine, dev_priv, id) { |
36cdd013 | 905 | if (INTEL_GEN(dev_priv) >= 6) { |
a2c7f6fd CW |
906 | seq_printf(m, |
907 | "Graphics Interrupt mask (%s): %08x\n", | |
e2f80391 | 908 | engine->name, I915_READ_IMR(engine)); |
9862e600 | 909 | } |
e2f80391 | 910 | i915_ring_seqno_info(m, engine); |
9862e600 | 911 | } |
c8c8fb33 | 912 | intel_runtime_pm_put(dev_priv); |
de227ef0 | 913 | |
2017263e BG |
914 | return 0; |
915 | } | |
916 | ||
a6172a80 CW |
917 | static int i915_gem_fence_regs_info(struct seq_file *m, void *data) |
918 | { | |
36cdd013 DW |
919 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
920 | struct drm_device *dev = &dev_priv->drm; | |
de227ef0 CW |
921 | int i, ret; |
922 | ||
923 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
924 | if (ret) | |
925 | return ret; | |
a6172a80 | 926 | |
a6172a80 CW |
927 | seq_printf(m, "Total fences = %d\n", dev_priv->num_fence_regs); |
928 | for (i = 0; i < dev_priv->num_fence_regs; i++) { | |
49ef5294 | 929 | struct i915_vma *vma = dev_priv->fence_regs[i].vma; |
a6172a80 | 930 | |
6c085a72 CW |
931 | seq_printf(m, "Fence %d, pin count = %d, object = ", |
932 | i, dev_priv->fence_regs[i].pin_count); | |
49ef5294 | 933 | if (!vma) |
267f0c90 | 934 | seq_puts(m, "unused"); |
c2c347a9 | 935 | else |
49ef5294 | 936 | describe_obj(m, vma->obj); |
267f0c90 | 937 | seq_putc(m, '\n'); |
a6172a80 CW |
938 | } |
939 | ||
05394f39 | 940 | mutex_unlock(&dev->struct_mutex); |
a6172a80 CW |
941 | return 0; |
942 | } | |
943 | ||
2017263e BG |
944 | static int i915_hws_info(struct seq_file *m, void *data) |
945 | { | |
9f25d007 | 946 | struct drm_info_node *node = m->private; |
36cdd013 | 947 | struct drm_i915_private *dev_priv = node_to_i915(node); |
e2f80391 | 948 | struct intel_engine_cs *engine; |
1a240d4d | 949 | const u32 *hws; |
4066c0ae CW |
950 | int i; |
951 | ||
3b3f1650 | 952 | engine = dev_priv->engine[(uintptr_t)node->info_ent->data]; |
e2f80391 | 953 | hws = engine->status_page.page_addr; |
2017263e BG |
954 | if (hws == NULL) |
955 | return 0; | |
956 | ||
957 | for (i = 0; i < 4096 / sizeof(u32) / 4; i += 4) { | |
958 | seq_printf(m, "0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x\n", | |
959 | i * 4, | |
960 | hws[i], hws[i + 1], hws[i + 2], hws[i + 3]); | |
961 | } | |
962 | return 0; | |
963 | } | |
964 | ||
98a2f411 CW |
965 | #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR) |
966 | ||
d5442303 DV |
967 | static ssize_t |
968 | i915_error_state_write(struct file *filp, | |
969 | const char __user *ubuf, | |
970 | size_t cnt, | |
971 | loff_t *ppos) | |
972 | { | |
edc3d884 | 973 | struct i915_error_state_file_priv *error_priv = filp->private_data; |
d5442303 DV |
974 | |
975 | DRM_DEBUG_DRIVER("Resetting error state\n"); | |
662d19e7 | 976 | i915_destroy_error_state(error_priv->dev); |
d5442303 DV |
977 | |
978 | return cnt; | |
979 | } | |
980 | ||
981 | static int i915_error_state_open(struct inode *inode, struct file *file) | |
982 | { | |
36cdd013 | 983 | struct drm_i915_private *dev_priv = inode->i_private; |
d5442303 | 984 | struct i915_error_state_file_priv *error_priv; |
d5442303 DV |
985 | |
986 | error_priv = kzalloc(sizeof(*error_priv), GFP_KERNEL); | |
987 | if (!error_priv) | |
988 | return -ENOMEM; | |
989 | ||
36cdd013 | 990 | error_priv->dev = &dev_priv->drm; |
d5442303 | 991 | |
36cdd013 | 992 | i915_error_state_get(&dev_priv->drm, error_priv); |
d5442303 | 993 | |
edc3d884 MK |
994 | file->private_data = error_priv; |
995 | ||
996 | return 0; | |
d5442303 DV |
997 | } |
998 | ||
999 | static int i915_error_state_release(struct inode *inode, struct file *file) | |
1000 | { | |
edc3d884 | 1001 | struct i915_error_state_file_priv *error_priv = file->private_data; |
d5442303 | 1002 | |
95d5bfb3 | 1003 | i915_error_state_put(error_priv); |
d5442303 DV |
1004 | kfree(error_priv); |
1005 | ||
edc3d884 MK |
1006 | return 0; |
1007 | } | |
1008 | ||
4dc955f7 MK |
1009 | static ssize_t i915_error_state_read(struct file *file, char __user *userbuf, |
1010 | size_t count, loff_t *pos) | |
1011 | { | |
1012 | struct i915_error_state_file_priv *error_priv = file->private_data; | |
1013 | struct drm_i915_error_state_buf error_str; | |
1014 | loff_t tmp_pos = 0; | |
1015 | ssize_t ret_count = 0; | |
1016 | int ret; | |
1017 | ||
36cdd013 DW |
1018 | ret = i915_error_state_buf_init(&error_str, |
1019 | to_i915(error_priv->dev), count, *pos); | |
4dc955f7 MK |
1020 | if (ret) |
1021 | return ret; | |
edc3d884 | 1022 | |
fc16b48b | 1023 | ret = i915_error_state_to_str(&error_str, error_priv); |
edc3d884 MK |
1024 | if (ret) |
1025 | goto out; | |
1026 | ||
edc3d884 MK |
1027 | ret_count = simple_read_from_buffer(userbuf, count, &tmp_pos, |
1028 | error_str.buf, | |
1029 | error_str.bytes); | |
1030 | ||
1031 | if (ret_count < 0) | |
1032 | ret = ret_count; | |
1033 | else | |
1034 | *pos = error_str.start + ret_count; | |
1035 | out: | |
4dc955f7 | 1036 | i915_error_state_buf_release(&error_str); |
edc3d884 | 1037 | return ret ?: ret_count; |
d5442303 DV |
1038 | } |
1039 | ||
1040 | static const struct file_operations i915_error_state_fops = { | |
1041 | .owner = THIS_MODULE, | |
1042 | .open = i915_error_state_open, | |
edc3d884 | 1043 | .read = i915_error_state_read, |
d5442303 DV |
1044 | .write = i915_error_state_write, |
1045 | .llseek = default_llseek, | |
1046 | .release = i915_error_state_release, | |
1047 | }; | |
1048 | ||
98a2f411 CW |
1049 | #endif |
1050 | ||
647416f9 KC |
1051 | static int |
1052 | i915_next_seqno_get(void *data, u64 *val) | |
40633219 | 1053 | { |
36cdd013 | 1054 | struct drm_i915_private *dev_priv = data; |
40633219 MK |
1055 | int ret; |
1056 | ||
36cdd013 | 1057 | ret = mutex_lock_interruptible(&dev_priv->drm.struct_mutex); |
40633219 MK |
1058 | if (ret) |
1059 | return ret; | |
1060 | ||
647416f9 | 1061 | *val = dev_priv->next_seqno; |
36cdd013 | 1062 | mutex_unlock(&dev_priv->drm.struct_mutex); |
40633219 | 1063 | |
647416f9 | 1064 | return 0; |
40633219 MK |
1065 | } |
1066 | ||
647416f9 KC |
1067 | static int |
1068 | i915_next_seqno_set(void *data, u64 val) | |
1069 | { | |
36cdd013 DW |
1070 | struct drm_i915_private *dev_priv = data; |
1071 | struct drm_device *dev = &dev_priv->drm; | |
40633219 MK |
1072 | int ret; |
1073 | ||
40633219 MK |
1074 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
1075 | if (ret) | |
1076 | return ret; | |
1077 | ||
e94fbaa8 | 1078 | ret = i915_gem_set_seqno(dev, val); |
40633219 MK |
1079 | mutex_unlock(&dev->struct_mutex); |
1080 | ||
647416f9 | 1081 | return ret; |
40633219 MK |
1082 | } |
1083 | ||
647416f9 KC |
1084 | DEFINE_SIMPLE_ATTRIBUTE(i915_next_seqno_fops, |
1085 | i915_next_seqno_get, i915_next_seqno_set, | |
3a3b4f98 | 1086 | "0x%llx\n"); |
40633219 | 1087 | |
adb4bd12 | 1088 | static int i915_frequency_info(struct seq_file *m, void *unused) |
f97108d1 | 1089 | { |
36cdd013 DW |
1090 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
1091 | struct drm_device *dev = &dev_priv->drm; | |
c8c8fb33 PZ |
1092 | int ret = 0; |
1093 | ||
1094 | intel_runtime_pm_get(dev_priv); | |
3b8d8d91 | 1095 | |
36cdd013 | 1096 | if (IS_GEN5(dev_priv)) { |
3b8d8d91 JB |
1097 | u16 rgvswctl = I915_READ16(MEMSWCTL); |
1098 | u16 rgvstat = I915_READ16(MEMSTAT_ILK); | |
1099 | ||
1100 | seq_printf(m, "Requested P-state: %d\n", (rgvswctl >> 8) & 0xf); | |
1101 | seq_printf(m, "Requested VID: %d\n", rgvswctl & 0x3f); | |
1102 | seq_printf(m, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK) >> | |
1103 | MEMSTAT_VID_SHIFT); | |
1104 | seq_printf(m, "Current P-state: %d\n", | |
1105 | (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT); | |
36cdd013 | 1106 | } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { |
666a4537 WB |
1107 | u32 freq_sts; |
1108 | ||
1109 | mutex_lock(&dev_priv->rps.hw_lock); | |
1110 | freq_sts = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS); | |
1111 | seq_printf(m, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts); | |
1112 | seq_printf(m, "DDR freq: %d MHz\n", dev_priv->mem_freq); | |
1113 | ||
1114 | seq_printf(m, "actual GPU freq: %d MHz\n", | |
1115 | intel_gpu_freq(dev_priv, (freq_sts >> 8) & 0xff)); | |
1116 | ||
1117 | seq_printf(m, "current GPU freq: %d MHz\n", | |
1118 | intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq)); | |
1119 | ||
1120 | seq_printf(m, "max GPU freq: %d MHz\n", | |
1121 | intel_gpu_freq(dev_priv, dev_priv->rps.max_freq)); | |
1122 | ||
1123 | seq_printf(m, "min GPU freq: %d MHz\n", | |
1124 | intel_gpu_freq(dev_priv, dev_priv->rps.min_freq)); | |
1125 | ||
1126 | seq_printf(m, "idle GPU freq: %d MHz\n", | |
1127 | intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq)); | |
1128 | ||
1129 | seq_printf(m, | |
1130 | "efficient (RPe) frequency: %d MHz\n", | |
1131 | intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq)); | |
1132 | mutex_unlock(&dev_priv->rps.hw_lock); | |
36cdd013 | 1133 | } else if (INTEL_GEN(dev_priv) >= 6) { |
35040562 BP |
1134 | u32 rp_state_limits; |
1135 | u32 gt_perf_status; | |
1136 | u32 rp_state_cap; | |
0d8f9491 | 1137 | u32 rpmodectl, rpinclimit, rpdeclimit; |
8e8c06cd | 1138 | u32 rpstat, cagf, reqf; |
ccab5c82 JB |
1139 | u32 rpupei, rpcurup, rpprevup; |
1140 | u32 rpdownei, rpcurdown, rpprevdown; | |
9dd3c605 | 1141 | u32 pm_ier, pm_imr, pm_isr, pm_iir, pm_mask; |
3b8d8d91 JB |
1142 | int max_freq; |
1143 | ||
35040562 | 1144 | rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS); |
36cdd013 | 1145 | if (IS_BROXTON(dev_priv)) { |
35040562 BP |
1146 | rp_state_cap = I915_READ(BXT_RP_STATE_CAP); |
1147 | gt_perf_status = I915_READ(BXT_GT_PERF_STATUS); | |
1148 | } else { | |
1149 | rp_state_cap = I915_READ(GEN6_RP_STATE_CAP); | |
1150 | gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS); | |
1151 | } | |
1152 | ||
3b8d8d91 | 1153 | /* RPSTAT1 is in the GT power well */ |
d1ebd816 BW |
1154 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
1155 | if (ret) | |
c8c8fb33 | 1156 | goto out; |
d1ebd816 | 1157 | |
59bad947 | 1158 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); |
3b8d8d91 | 1159 | |
8e8c06cd | 1160 | reqf = I915_READ(GEN6_RPNSWREQ); |
36cdd013 | 1161 | if (IS_GEN9(dev_priv)) |
60260a5b AG |
1162 | reqf >>= 23; |
1163 | else { | |
1164 | reqf &= ~GEN6_TURBO_DISABLE; | |
36cdd013 | 1165 | if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) |
60260a5b AG |
1166 | reqf >>= 24; |
1167 | else | |
1168 | reqf >>= 25; | |
1169 | } | |
7c59a9c1 | 1170 | reqf = intel_gpu_freq(dev_priv, reqf); |
8e8c06cd | 1171 | |
0d8f9491 CW |
1172 | rpmodectl = I915_READ(GEN6_RP_CONTROL); |
1173 | rpinclimit = I915_READ(GEN6_RP_UP_THRESHOLD); | |
1174 | rpdeclimit = I915_READ(GEN6_RP_DOWN_THRESHOLD); | |
1175 | ||
ccab5c82 | 1176 | rpstat = I915_READ(GEN6_RPSTAT1); |
d6cda9c7 AG |
1177 | rpupei = I915_READ(GEN6_RP_CUR_UP_EI) & GEN6_CURICONT_MASK; |
1178 | rpcurup = I915_READ(GEN6_RP_CUR_UP) & GEN6_CURBSYTAVG_MASK; | |
1179 | rpprevup = I915_READ(GEN6_RP_PREV_UP) & GEN6_CURBSYTAVG_MASK; | |
1180 | rpdownei = I915_READ(GEN6_RP_CUR_DOWN_EI) & GEN6_CURIAVG_MASK; | |
1181 | rpcurdown = I915_READ(GEN6_RP_CUR_DOWN) & GEN6_CURBSYTAVG_MASK; | |
1182 | rpprevdown = I915_READ(GEN6_RP_PREV_DOWN) & GEN6_CURBSYTAVG_MASK; | |
36cdd013 | 1183 | if (IS_GEN9(dev_priv)) |
60260a5b | 1184 | cagf = (rpstat & GEN9_CAGF_MASK) >> GEN9_CAGF_SHIFT; |
36cdd013 | 1185 | else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) |
f82855d3 BW |
1186 | cagf = (rpstat & HSW_CAGF_MASK) >> HSW_CAGF_SHIFT; |
1187 | else | |
1188 | cagf = (rpstat & GEN6_CAGF_MASK) >> GEN6_CAGF_SHIFT; | |
7c59a9c1 | 1189 | cagf = intel_gpu_freq(dev_priv, cagf); |
ccab5c82 | 1190 | |
59bad947 | 1191 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); |
d1ebd816 BW |
1192 | mutex_unlock(&dev->struct_mutex); |
1193 | ||
36cdd013 | 1194 | if (IS_GEN6(dev_priv) || IS_GEN7(dev_priv)) { |
9dd3c605 PZ |
1195 | pm_ier = I915_READ(GEN6_PMIER); |
1196 | pm_imr = I915_READ(GEN6_PMIMR); | |
1197 | pm_isr = I915_READ(GEN6_PMISR); | |
1198 | pm_iir = I915_READ(GEN6_PMIIR); | |
1199 | pm_mask = I915_READ(GEN6_PMINTRMSK); | |
1200 | } else { | |
1201 | pm_ier = I915_READ(GEN8_GT_IER(2)); | |
1202 | pm_imr = I915_READ(GEN8_GT_IMR(2)); | |
1203 | pm_isr = I915_READ(GEN8_GT_ISR(2)); | |
1204 | pm_iir = I915_READ(GEN8_GT_IIR(2)); | |
1205 | pm_mask = I915_READ(GEN6_PMINTRMSK); | |
1206 | } | |
0d8f9491 | 1207 | seq_printf(m, "PM IER=0x%08x IMR=0x%08x ISR=0x%08x IIR=0x%08x, MASK=0x%08x\n", |
9dd3c605 | 1208 | pm_ier, pm_imr, pm_isr, pm_iir, pm_mask); |
1800ad25 | 1209 | seq_printf(m, "pm_intr_keep: 0x%08x\n", dev_priv->rps.pm_intr_keep); |
3b8d8d91 | 1210 | seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status); |
3b8d8d91 | 1211 | seq_printf(m, "Render p-state ratio: %d\n", |
36cdd013 | 1212 | (gt_perf_status & (IS_GEN9(dev_priv) ? 0x1ff00 : 0xff00)) >> 8); |
3b8d8d91 JB |
1213 | seq_printf(m, "Render p-state VID: %d\n", |
1214 | gt_perf_status & 0xff); | |
1215 | seq_printf(m, "Render p-state limit: %d\n", | |
1216 | rp_state_limits & 0xff); | |
0d8f9491 CW |
1217 | seq_printf(m, "RPSTAT1: 0x%08x\n", rpstat); |
1218 | seq_printf(m, "RPMODECTL: 0x%08x\n", rpmodectl); | |
1219 | seq_printf(m, "RPINCLIMIT: 0x%08x\n", rpinclimit); | |
1220 | seq_printf(m, "RPDECLIMIT: 0x%08x\n", rpdeclimit); | |
8e8c06cd | 1221 | seq_printf(m, "RPNSWREQ: %dMHz\n", reqf); |
f82855d3 | 1222 | seq_printf(m, "CAGF: %dMHz\n", cagf); |
d6cda9c7 AG |
1223 | seq_printf(m, "RP CUR UP EI: %d (%dus)\n", |
1224 | rpupei, GT_PM_INTERVAL_TO_US(dev_priv, rpupei)); | |
1225 | seq_printf(m, "RP CUR UP: %d (%dus)\n", | |
1226 | rpcurup, GT_PM_INTERVAL_TO_US(dev_priv, rpcurup)); | |
1227 | seq_printf(m, "RP PREV UP: %d (%dus)\n", | |
1228 | rpprevup, GT_PM_INTERVAL_TO_US(dev_priv, rpprevup)); | |
d86ed34a CW |
1229 | seq_printf(m, "Up threshold: %d%%\n", |
1230 | dev_priv->rps.up_threshold); | |
1231 | ||
d6cda9c7 AG |
1232 | seq_printf(m, "RP CUR DOWN EI: %d (%dus)\n", |
1233 | rpdownei, GT_PM_INTERVAL_TO_US(dev_priv, rpdownei)); | |
1234 | seq_printf(m, "RP CUR DOWN: %d (%dus)\n", | |
1235 | rpcurdown, GT_PM_INTERVAL_TO_US(dev_priv, rpcurdown)); | |
1236 | seq_printf(m, "RP PREV DOWN: %d (%dus)\n", | |
1237 | rpprevdown, GT_PM_INTERVAL_TO_US(dev_priv, rpprevdown)); | |
d86ed34a CW |
1238 | seq_printf(m, "Down threshold: %d%%\n", |
1239 | dev_priv->rps.down_threshold); | |
3b8d8d91 | 1240 | |
36cdd013 | 1241 | max_freq = (IS_BROXTON(dev_priv) ? rp_state_cap >> 0 : |
35040562 | 1242 | rp_state_cap >> 16) & 0xff; |
36cdd013 | 1243 | max_freq *= (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv) ? |
ef11bdb3 | 1244 | GEN9_FREQ_SCALER : 1); |
3b8d8d91 | 1245 | seq_printf(m, "Lowest (RPN) frequency: %dMHz\n", |
7c59a9c1 | 1246 | intel_gpu_freq(dev_priv, max_freq)); |
3b8d8d91 JB |
1247 | |
1248 | max_freq = (rp_state_cap & 0xff00) >> 8; | |
36cdd013 | 1249 | max_freq *= (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv) ? |
ef11bdb3 | 1250 | GEN9_FREQ_SCALER : 1); |
3b8d8d91 | 1251 | seq_printf(m, "Nominal (RP1) frequency: %dMHz\n", |
7c59a9c1 | 1252 | intel_gpu_freq(dev_priv, max_freq)); |
3b8d8d91 | 1253 | |
36cdd013 | 1254 | max_freq = (IS_BROXTON(dev_priv) ? rp_state_cap >> 16 : |
35040562 | 1255 | rp_state_cap >> 0) & 0xff; |
36cdd013 | 1256 | max_freq *= (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv) ? |
ef11bdb3 | 1257 | GEN9_FREQ_SCALER : 1); |
3b8d8d91 | 1258 | seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n", |
7c59a9c1 | 1259 | intel_gpu_freq(dev_priv, max_freq)); |
31c77388 | 1260 | seq_printf(m, "Max overclocked frequency: %dMHz\n", |
7c59a9c1 | 1261 | intel_gpu_freq(dev_priv, dev_priv->rps.max_freq)); |
aed242ff | 1262 | |
d86ed34a CW |
1263 | seq_printf(m, "Current freq: %d MHz\n", |
1264 | intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq)); | |
1265 | seq_printf(m, "Actual freq: %d MHz\n", cagf); | |
aed242ff CW |
1266 | seq_printf(m, "Idle freq: %d MHz\n", |
1267 | intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq)); | |
d86ed34a CW |
1268 | seq_printf(m, "Min freq: %d MHz\n", |
1269 | intel_gpu_freq(dev_priv, dev_priv->rps.min_freq)); | |
29ecd78d CW |
1270 | seq_printf(m, "Boost freq: %d MHz\n", |
1271 | intel_gpu_freq(dev_priv, dev_priv->rps.boost_freq)); | |
d86ed34a CW |
1272 | seq_printf(m, "Max freq: %d MHz\n", |
1273 | intel_gpu_freq(dev_priv, dev_priv->rps.max_freq)); | |
1274 | seq_printf(m, | |
1275 | "efficient (RPe) frequency: %d MHz\n", | |
1276 | intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq)); | |
3b8d8d91 | 1277 | } else { |
267f0c90 | 1278 | seq_puts(m, "no P-state info available\n"); |
3b8d8d91 | 1279 | } |
f97108d1 | 1280 | |
1170f28c MK |
1281 | seq_printf(m, "Current CD clock frequency: %d kHz\n", dev_priv->cdclk_freq); |
1282 | seq_printf(m, "Max CD clock frequency: %d kHz\n", dev_priv->max_cdclk_freq); | |
1283 | seq_printf(m, "Max pixel clock frequency: %d kHz\n", dev_priv->max_dotclk_freq); | |
1284 | ||
c8c8fb33 PZ |
1285 | out: |
1286 | intel_runtime_pm_put(dev_priv); | |
1287 | return ret; | |
f97108d1 JB |
1288 | } |
1289 | ||
d636951e BW |
1290 | static void i915_instdone_info(struct drm_i915_private *dev_priv, |
1291 | struct seq_file *m, | |
1292 | struct intel_instdone *instdone) | |
1293 | { | |
f9e61372 BW |
1294 | int slice; |
1295 | int subslice; | |
1296 | ||
d636951e BW |
1297 | seq_printf(m, "\t\tINSTDONE: 0x%08x\n", |
1298 | instdone->instdone); | |
1299 | ||
1300 | if (INTEL_GEN(dev_priv) <= 3) | |
1301 | return; | |
1302 | ||
1303 | seq_printf(m, "\t\tSC_INSTDONE: 0x%08x\n", | |
1304 | instdone->slice_common); | |
1305 | ||
1306 | if (INTEL_GEN(dev_priv) <= 6) | |
1307 | return; | |
1308 | ||
f9e61372 BW |
1309 | for_each_instdone_slice_subslice(dev_priv, slice, subslice) |
1310 | seq_printf(m, "\t\tSAMPLER_INSTDONE[%d][%d]: 0x%08x\n", | |
1311 | slice, subslice, instdone->sampler[slice][subslice]); | |
1312 | ||
1313 | for_each_instdone_slice_subslice(dev_priv, slice, subslice) | |
1314 | seq_printf(m, "\t\tROW_INSTDONE[%d][%d]: 0x%08x\n", | |
1315 | slice, subslice, instdone->row[slice][subslice]); | |
d636951e BW |
1316 | } |
1317 | ||
f654449a CW |
1318 | static int i915_hangcheck_info(struct seq_file *m, void *unused) |
1319 | { | |
36cdd013 | 1320 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
e2f80391 | 1321 | struct intel_engine_cs *engine; |
666796da TU |
1322 | u64 acthd[I915_NUM_ENGINES]; |
1323 | u32 seqno[I915_NUM_ENGINES]; | |
d636951e | 1324 | struct intel_instdone instdone; |
c3232b18 | 1325 | enum intel_engine_id id; |
f654449a | 1326 | |
8af29b0c CW |
1327 | if (test_bit(I915_WEDGED, &dev_priv->gpu_error.flags)) |
1328 | seq_printf(m, "Wedged\n"); | |
1329 | if (test_bit(I915_RESET_IN_PROGRESS, &dev_priv->gpu_error.flags)) | |
1330 | seq_printf(m, "Reset in progress\n"); | |
1331 | if (waitqueue_active(&dev_priv->gpu_error.wait_queue)) | |
1332 | seq_printf(m, "Waiter holding struct mutex\n"); | |
1333 | if (waitqueue_active(&dev_priv->gpu_error.reset_queue)) | |
1334 | seq_printf(m, "struct_mutex blocked for reset\n"); | |
1335 | ||
f654449a CW |
1336 | if (!i915.enable_hangcheck) { |
1337 | seq_printf(m, "Hangcheck disabled\n"); | |
1338 | return 0; | |
1339 | } | |
1340 | ||
ebbc7546 MK |
1341 | intel_runtime_pm_get(dev_priv); |
1342 | ||
3b3f1650 | 1343 | for_each_engine(engine, dev_priv, id) { |
7e37f889 | 1344 | acthd[id] = intel_engine_get_active_head(engine); |
1b7744e7 | 1345 | seqno[id] = intel_engine_get_seqno(engine); |
ebbc7546 MK |
1346 | } |
1347 | ||
3b3f1650 | 1348 | intel_engine_get_instdone(dev_priv->engine[RCS], &instdone); |
61642ff0 | 1349 | |
ebbc7546 MK |
1350 | intel_runtime_pm_put(dev_priv); |
1351 | ||
f654449a CW |
1352 | if (delayed_work_pending(&dev_priv->gpu_error.hangcheck_work)) { |
1353 | seq_printf(m, "Hangcheck active, fires in %dms\n", | |
1354 | jiffies_to_msecs(dev_priv->gpu_error.hangcheck_work.timer.expires - | |
1355 | jiffies)); | |
1356 | } else | |
1357 | seq_printf(m, "Hangcheck inactive\n"); | |
1358 | ||
3b3f1650 | 1359 | for_each_engine(engine, dev_priv, id) { |
33f53719 CW |
1360 | struct intel_breadcrumbs *b = &engine->breadcrumbs; |
1361 | struct rb_node *rb; | |
1362 | ||
e2f80391 | 1363 | seq_printf(m, "%s:\n", engine->name); |
14fd0d6d CW |
1364 | seq_printf(m, "\tseqno = %x [current %x, last %x]\n", |
1365 | engine->hangcheck.seqno, | |
1366 | seqno[id], | |
1367 | engine->last_submitted_seqno); | |
83348ba8 CW |
1368 | seq_printf(m, "\twaiters? %s, fake irq active? %s\n", |
1369 | yesno(intel_engine_has_waiter(engine)), | |
1370 | yesno(test_bit(engine->id, | |
1371 | &dev_priv->gpu_error.missed_irq_rings))); | |
33f53719 CW |
1372 | spin_lock(&b->lock); |
1373 | for (rb = rb_first(&b->waiters); rb; rb = rb_next(rb)) { | |
1374 | struct intel_wait *w = container_of(rb, typeof(*w), node); | |
1375 | ||
1376 | seq_printf(m, "\t%s [%d] waiting for %x\n", | |
1377 | w->tsk->comm, w->tsk->pid, w->seqno); | |
1378 | } | |
1379 | spin_unlock(&b->lock); | |
1380 | ||
f654449a | 1381 | seq_printf(m, "\tACTHD = 0x%08llx [current 0x%08llx]\n", |
e2f80391 | 1382 | (long long)engine->hangcheck.acthd, |
c3232b18 | 1383 | (long long)acthd[id]); |
e2f80391 TU |
1384 | seq_printf(m, "\tscore = %d\n", engine->hangcheck.score); |
1385 | seq_printf(m, "\taction = %d\n", engine->hangcheck.action); | |
61642ff0 | 1386 | |
e2f80391 | 1387 | if (engine->id == RCS) { |
d636951e | 1388 | seq_puts(m, "\tinstdone read =\n"); |
61642ff0 | 1389 | |
d636951e | 1390 | i915_instdone_info(dev_priv, m, &instdone); |
61642ff0 | 1391 | |
d636951e | 1392 | seq_puts(m, "\tinstdone accu =\n"); |
61642ff0 | 1393 | |
d636951e BW |
1394 | i915_instdone_info(dev_priv, m, |
1395 | &engine->hangcheck.instdone); | |
61642ff0 | 1396 | } |
f654449a CW |
1397 | } |
1398 | ||
1399 | return 0; | |
1400 | } | |
1401 | ||
4d85529d | 1402 | static int ironlake_drpc_info(struct seq_file *m) |
f97108d1 | 1403 | { |
36cdd013 | 1404 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
616fdb5a BW |
1405 | u32 rgvmodectl, rstdbyctl; |
1406 | u16 crstandvid; | |
616fdb5a | 1407 | |
c8c8fb33 | 1408 | intel_runtime_pm_get(dev_priv); |
616fdb5a BW |
1409 | |
1410 | rgvmodectl = I915_READ(MEMMODECTL); | |
1411 | rstdbyctl = I915_READ(RSTDBYCTL); | |
1412 | crstandvid = I915_READ16(CRSTANDVID); | |
1413 | ||
c8c8fb33 | 1414 | intel_runtime_pm_put(dev_priv); |
f97108d1 | 1415 | |
742f491d | 1416 | seq_printf(m, "HD boost: %s\n", yesno(rgvmodectl & MEMMODE_BOOST_EN)); |
f97108d1 JB |
1417 | seq_printf(m, "Boost freq: %d\n", |
1418 | (rgvmodectl & MEMMODE_BOOST_FREQ_MASK) >> | |
1419 | MEMMODE_BOOST_FREQ_SHIFT); | |
1420 | seq_printf(m, "HW control enabled: %s\n", | |
742f491d | 1421 | yesno(rgvmodectl & MEMMODE_HWIDLE_EN)); |
f97108d1 | 1422 | seq_printf(m, "SW control enabled: %s\n", |
742f491d | 1423 | yesno(rgvmodectl & MEMMODE_SWMODE_EN)); |
f97108d1 | 1424 | seq_printf(m, "Gated voltage change: %s\n", |
742f491d | 1425 | yesno(rgvmodectl & MEMMODE_RCLK_GATE)); |
f97108d1 JB |
1426 | seq_printf(m, "Starting frequency: P%d\n", |
1427 | (rgvmodectl & MEMMODE_FSTART_MASK) >> MEMMODE_FSTART_SHIFT); | |
7648fa99 | 1428 | seq_printf(m, "Max P-state: P%d\n", |
f97108d1 | 1429 | (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT); |
7648fa99 JB |
1430 | seq_printf(m, "Min P-state: P%d\n", (rgvmodectl & MEMMODE_FMIN_MASK)); |
1431 | seq_printf(m, "RS1 VID: %d\n", (crstandvid & 0x3f)); | |
1432 | seq_printf(m, "RS2 VID: %d\n", ((crstandvid >> 8) & 0x3f)); | |
1433 | seq_printf(m, "Render standby enabled: %s\n", | |
742f491d | 1434 | yesno(!(rstdbyctl & RCX_SW_EXIT))); |
267f0c90 | 1435 | seq_puts(m, "Current RS state: "); |
88271da3 JB |
1436 | switch (rstdbyctl & RSX_STATUS_MASK) { |
1437 | case RSX_STATUS_ON: | |
267f0c90 | 1438 | seq_puts(m, "on\n"); |
88271da3 JB |
1439 | break; |
1440 | case RSX_STATUS_RC1: | |
267f0c90 | 1441 | seq_puts(m, "RC1\n"); |
88271da3 JB |
1442 | break; |
1443 | case RSX_STATUS_RC1E: | |
267f0c90 | 1444 | seq_puts(m, "RC1E\n"); |
88271da3 JB |
1445 | break; |
1446 | case RSX_STATUS_RS1: | |
267f0c90 | 1447 | seq_puts(m, "RS1\n"); |
88271da3 JB |
1448 | break; |
1449 | case RSX_STATUS_RS2: | |
267f0c90 | 1450 | seq_puts(m, "RS2 (RC6)\n"); |
88271da3 JB |
1451 | break; |
1452 | case RSX_STATUS_RS3: | |
267f0c90 | 1453 | seq_puts(m, "RC3 (RC6+)\n"); |
88271da3 JB |
1454 | break; |
1455 | default: | |
267f0c90 | 1456 | seq_puts(m, "unknown\n"); |
88271da3 JB |
1457 | break; |
1458 | } | |
f97108d1 JB |
1459 | |
1460 | return 0; | |
1461 | } | |
1462 | ||
f65367b5 | 1463 | static int i915_forcewake_domains(struct seq_file *m, void *data) |
669ab5aa | 1464 | { |
36cdd013 | 1465 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
b2cff0db | 1466 | struct intel_uncore_forcewake_domain *fw_domain; |
b2cff0db CW |
1467 | |
1468 | spin_lock_irq(&dev_priv->uncore.lock); | |
33c582c1 | 1469 | for_each_fw_domain(fw_domain, dev_priv) { |
b2cff0db | 1470 | seq_printf(m, "%s.wake_count = %u\n", |
33c582c1 | 1471 | intel_uncore_forcewake_domain_to_str(fw_domain->id), |
b2cff0db CW |
1472 | fw_domain->wake_count); |
1473 | } | |
1474 | spin_unlock_irq(&dev_priv->uncore.lock); | |
669ab5aa | 1475 | |
b2cff0db CW |
1476 | return 0; |
1477 | } | |
1478 | ||
1479 | static int vlv_drpc_info(struct seq_file *m) | |
1480 | { | |
36cdd013 | 1481 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
6b312cd3 | 1482 | u32 rpmodectl1, rcctl1, pw_status; |
669ab5aa | 1483 | |
d46c0517 ID |
1484 | intel_runtime_pm_get(dev_priv); |
1485 | ||
6b312cd3 | 1486 | pw_status = I915_READ(VLV_GTLC_PW_STATUS); |
669ab5aa D |
1487 | rpmodectl1 = I915_READ(GEN6_RP_CONTROL); |
1488 | rcctl1 = I915_READ(GEN6_RC_CONTROL); | |
1489 | ||
d46c0517 ID |
1490 | intel_runtime_pm_put(dev_priv); |
1491 | ||
669ab5aa D |
1492 | seq_printf(m, "Video Turbo Mode: %s\n", |
1493 | yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO)); | |
1494 | seq_printf(m, "Turbo enabled: %s\n", | |
1495 | yesno(rpmodectl1 & GEN6_RP_ENABLE)); | |
1496 | seq_printf(m, "HW control enabled: %s\n", | |
1497 | yesno(rpmodectl1 & GEN6_RP_ENABLE)); | |
1498 | seq_printf(m, "SW control enabled: %s\n", | |
1499 | yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) == | |
1500 | GEN6_RP_MEDIA_SW_MODE)); | |
1501 | seq_printf(m, "RC6 Enabled: %s\n", | |
1502 | yesno(rcctl1 & (GEN7_RC_CTL_TO_MODE | | |
1503 | GEN6_RC_CTL_EI_MODE(1)))); | |
1504 | seq_printf(m, "Render Power Well: %s\n", | |
6b312cd3 | 1505 | (pw_status & VLV_GTLC_PW_RENDER_STATUS_MASK) ? "Up" : "Down"); |
669ab5aa | 1506 | seq_printf(m, "Media Power Well: %s\n", |
6b312cd3 | 1507 | (pw_status & VLV_GTLC_PW_MEDIA_STATUS_MASK) ? "Up" : "Down"); |
669ab5aa | 1508 | |
9cc19be5 ID |
1509 | seq_printf(m, "Render RC6 residency since boot: %u\n", |
1510 | I915_READ(VLV_GT_RENDER_RC6)); | |
1511 | seq_printf(m, "Media RC6 residency since boot: %u\n", | |
1512 | I915_READ(VLV_GT_MEDIA_RC6)); | |
1513 | ||
f65367b5 | 1514 | return i915_forcewake_domains(m, NULL); |
669ab5aa D |
1515 | } |
1516 | ||
4d85529d BW |
1517 | static int gen6_drpc_info(struct seq_file *m) |
1518 | { | |
36cdd013 DW |
1519 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
1520 | struct drm_device *dev = &dev_priv->drm; | |
ecd8faea | 1521 | u32 rpmodectl1, gt_core_status, rcctl1, rc6vids = 0; |
f2dd7578 | 1522 | u32 gen9_powergate_enable = 0, gen9_powergate_status = 0; |
93b525dc | 1523 | unsigned forcewake_count; |
aee56cff | 1524 | int count = 0, ret; |
4d85529d BW |
1525 | |
1526 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
1527 | if (ret) | |
1528 | return ret; | |
c8c8fb33 | 1529 | intel_runtime_pm_get(dev_priv); |
4d85529d | 1530 | |
907b28c5 | 1531 | spin_lock_irq(&dev_priv->uncore.lock); |
b2cff0db | 1532 | forcewake_count = dev_priv->uncore.fw_domain[FW_DOMAIN_ID_RENDER].wake_count; |
907b28c5 | 1533 | spin_unlock_irq(&dev_priv->uncore.lock); |
93b525dc DV |
1534 | |
1535 | if (forcewake_count) { | |
267f0c90 DL |
1536 | seq_puts(m, "RC information inaccurate because somebody " |
1537 | "holds a forcewake reference \n"); | |
4d85529d BW |
1538 | } else { |
1539 | /* NB: we cannot use forcewake, else we read the wrong values */ | |
1540 | while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1)) | |
1541 | udelay(10); | |
1542 | seq_printf(m, "RC information accurate: %s\n", yesno(count < 51)); | |
1543 | } | |
1544 | ||
75aa3f63 | 1545 | gt_core_status = I915_READ_FW(GEN6_GT_CORE_STATUS); |
ed71f1b4 | 1546 | trace_i915_reg_rw(false, GEN6_GT_CORE_STATUS, gt_core_status, 4, true); |
4d85529d BW |
1547 | |
1548 | rpmodectl1 = I915_READ(GEN6_RP_CONTROL); | |
1549 | rcctl1 = I915_READ(GEN6_RC_CONTROL); | |
36cdd013 | 1550 | if (INTEL_GEN(dev_priv) >= 9) { |
f2dd7578 AG |
1551 | gen9_powergate_enable = I915_READ(GEN9_PG_ENABLE); |
1552 | gen9_powergate_status = I915_READ(GEN9_PWRGT_DOMAIN_STATUS); | |
1553 | } | |
4d85529d | 1554 | mutex_unlock(&dev->struct_mutex); |
44cbd338 BW |
1555 | mutex_lock(&dev_priv->rps.hw_lock); |
1556 | sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids); | |
1557 | mutex_unlock(&dev_priv->rps.hw_lock); | |
4d85529d | 1558 | |
c8c8fb33 PZ |
1559 | intel_runtime_pm_put(dev_priv); |
1560 | ||
4d85529d BW |
1561 | seq_printf(m, "Video Turbo Mode: %s\n", |
1562 | yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO)); | |
1563 | seq_printf(m, "HW control enabled: %s\n", | |
1564 | yesno(rpmodectl1 & GEN6_RP_ENABLE)); | |
1565 | seq_printf(m, "SW control enabled: %s\n", | |
1566 | yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) == | |
1567 | GEN6_RP_MEDIA_SW_MODE)); | |
fff24e21 | 1568 | seq_printf(m, "RC1e Enabled: %s\n", |
4d85529d BW |
1569 | yesno(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE)); |
1570 | seq_printf(m, "RC6 Enabled: %s\n", | |
1571 | yesno(rcctl1 & GEN6_RC_CTL_RC6_ENABLE)); | |
36cdd013 | 1572 | if (INTEL_GEN(dev_priv) >= 9) { |
f2dd7578 AG |
1573 | seq_printf(m, "Render Well Gating Enabled: %s\n", |
1574 | yesno(gen9_powergate_enable & GEN9_RENDER_PG_ENABLE)); | |
1575 | seq_printf(m, "Media Well Gating Enabled: %s\n", | |
1576 | yesno(gen9_powergate_enable & GEN9_MEDIA_PG_ENABLE)); | |
1577 | } | |
4d85529d BW |
1578 | seq_printf(m, "Deep RC6 Enabled: %s\n", |
1579 | yesno(rcctl1 & GEN6_RC_CTL_RC6p_ENABLE)); | |
1580 | seq_printf(m, "Deepest RC6 Enabled: %s\n", | |
1581 | yesno(rcctl1 & GEN6_RC_CTL_RC6pp_ENABLE)); | |
267f0c90 | 1582 | seq_puts(m, "Current RC state: "); |
4d85529d BW |
1583 | switch (gt_core_status & GEN6_RCn_MASK) { |
1584 | case GEN6_RC0: | |
1585 | if (gt_core_status & GEN6_CORE_CPD_STATE_MASK) | |
267f0c90 | 1586 | seq_puts(m, "Core Power Down\n"); |
4d85529d | 1587 | else |
267f0c90 | 1588 | seq_puts(m, "on\n"); |
4d85529d BW |
1589 | break; |
1590 | case GEN6_RC3: | |
267f0c90 | 1591 | seq_puts(m, "RC3\n"); |
4d85529d BW |
1592 | break; |
1593 | case GEN6_RC6: | |
267f0c90 | 1594 | seq_puts(m, "RC6\n"); |
4d85529d BW |
1595 | break; |
1596 | case GEN6_RC7: | |
267f0c90 | 1597 | seq_puts(m, "RC7\n"); |
4d85529d BW |
1598 | break; |
1599 | default: | |
267f0c90 | 1600 | seq_puts(m, "Unknown\n"); |
4d85529d BW |
1601 | break; |
1602 | } | |
1603 | ||
1604 | seq_printf(m, "Core Power Down: %s\n", | |
1605 | yesno(gt_core_status & GEN6_CORE_CPD_STATE_MASK)); | |
36cdd013 | 1606 | if (INTEL_GEN(dev_priv) >= 9) { |
f2dd7578 AG |
1607 | seq_printf(m, "Render Power Well: %s\n", |
1608 | (gen9_powergate_status & | |
1609 | GEN9_PWRGT_RENDER_STATUS_MASK) ? "Up" : "Down"); | |
1610 | seq_printf(m, "Media Power Well: %s\n", | |
1611 | (gen9_powergate_status & | |
1612 | GEN9_PWRGT_MEDIA_STATUS_MASK) ? "Up" : "Down"); | |
1613 | } | |
cce66a28 BW |
1614 | |
1615 | /* Not exactly sure what this is */ | |
1616 | seq_printf(m, "RC6 \"Locked to RPn\" residency since boot: %u\n", | |
1617 | I915_READ(GEN6_GT_GFX_RC6_LOCKED)); | |
1618 | seq_printf(m, "RC6 residency since boot: %u\n", | |
1619 | I915_READ(GEN6_GT_GFX_RC6)); | |
1620 | seq_printf(m, "RC6+ residency since boot: %u\n", | |
1621 | I915_READ(GEN6_GT_GFX_RC6p)); | |
1622 | seq_printf(m, "RC6++ residency since boot: %u\n", | |
1623 | I915_READ(GEN6_GT_GFX_RC6pp)); | |
1624 | ||
ecd8faea BW |
1625 | seq_printf(m, "RC6 voltage: %dmV\n", |
1626 | GEN6_DECODE_RC6_VID(((rc6vids >> 0) & 0xff))); | |
1627 | seq_printf(m, "RC6+ voltage: %dmV\n", | |
1628 | GEN6_DECODE_RC6_VID(((rc6vids >> 8) & 0xff))); | |
1629 | seq_printf(m, "RC6++ voltage: %dmV\n", | |
1630 | GEN6_DECODE_RC6_VID(((rc6vids >> 16) & 0xff))); | |
f2dd7578 | 1631 | return i915_forcewake_domains(m, NULL); |
4d85529d BW |
1632 | } |
1633 | ||
1634 | static int i915_drpc_info(struct seq_file *m, void *unused) | |
1635 | { | |
36cdd013 | 1636 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
4d85529d | 1637 | |
36cdd013 | 1638 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) |
669ab5aa | 1639 | return vlv_drpc_info(m); |
36cdd013 | 1640 | else if (INTEL_GEN(dev_priv) >= 6) |
4d85529d BW |
1641 | return gen6_drpc_info(m); |
1642 | else | |
1643 | return ironlake_drpc_info(m); | |
1644 | } | |
1645 | ||
9a851789 DV |
1646 | static int i915_frontbuffer_tracking(struct seq_file *m, void *unused) |
1647 | { | |
36cdd013 | 1648 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
9a851789 DV |
1649 | |
1650 | seq_printf(m, "FB tracking busy bits: 0x%08x\n", | |
1651 | dev_priv->fb_tracking.busy_bits); | |
1652 | ||
1653 | seq_printf(m, "FB tracking flip bits: 0x%08x\n", | |
1654 | dev_priv->fb_tracking.flip_bits); | |
1655 | ||
1656 | return 0; | |
1657 | } | |
1658 | ||
b5e50c3f JB |
1659 | static int i915_fbc_status(struct seq_file *m, void *unused) |
1660 | { | |
36cdd013 | 1661 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
b5e50c3f | 1662 | |
36cdd013 | 1663 | if (!HAS_FBC(dev_priv)) { |
267f0c90 | 1664 | seq_puts(m, "FBC unsupported on this chipset\n"); |
b5e50c3f JB |
1665 | return 0; |
1666 | } | |
1667 | ||
36623ef8 | 1668 | intel_runtime_pm_get(dev_priv); |
25ad93fd | 1669 | mutex_lock(&dev_priv->fbc.lock); |
36623ef8 | 1670 | |
0e631adc | 1671 | if (intel_fbc_is_active(dev_priv)) |
267f0c90 | 1672 | seq_puts(m, "FBC enabled\n"); |
2e8144a5 PZ |
1673 | else |
1674 | seq_printf(m, "FBC disabled: %s\n", | |
bf6189c6 | 1675 | dev_priv->fbc.no_fbc_reason); |
36623ef8 | 1676 | |
0fc6a9dc PZ |
1677 | if (intel_fbc_is_active(dev_priv) && INTEL_GEN(dev_priv) >= 7) { |
1678 | uint32_t mask = INTEL_GEN(dev_priv) >= 8 ? | |
1679 | BDW_FBC_COMPRESSION_MASK : | |
1680 | IVB_FBC_COMPRESSION_MASK; | |
31b9df10 | 1681 | seq_printf(m, "Compressing: %s\n", |
0fc6a9dc PZ |
1682 | yesno(I915_READ(FBC_STATUS2) & mask)); |
1683 | } | |
31b9df10 | 1684 | |
25ad93fd | 1685 | mutex_unlock(&dev_priv->fbc.lock); |
36623ef8 PZ |
1686 | intel_runtime_pm_put(dev_priv); |
1687 | ||
b5e50c3f JB |
1688 | return 0; |
1689 | } | |
1690 | ||
da46f936 RV |
1691 | static int i915_fbc_fc_get(void *data, u64 *val) |
1692 | { | |
36cdd013 | 1693 | struct drm_i915_private *dev_priv = data; |
da46f936 | 1694 | |
36cdd013 | 1695 | if (INTEL_GEN(dev_priv) < 7 || !HAS_FBC(dev_priv)) |
da46f936 RV |
1696 | return -ENODEV; |
1697 | ||
da46f936 | 1698 | *val = dev_priv->fbc.false_color; |
da46f936 RV |
1699 | |
1700 | return 0; | |
1701 | } | |
1702 | ||
1703 | static int i915_fbc_fc_set(void *data, u64 val) | |
1704 | { | |
36cdd013 | 1705 | struct drm_i915_private *dev_priv = data; |
da46f936 RV |
1706 | u32 reg; |
1707 | ||
36cdd013 | 1708 | if (INTEL_GEN(dev_priv) < 7 || !HAS_FBC(dev_priv)) |
da46f936 RV |
1709 | return -ENODEV; |
1710 | ||
25ad93fd | 1711 | mutex_lock(&dev_priv->fbc.lock); |
da46f936 RV |
1712 | |
1713 | reg = I915_READ(ILK_DPFC_CONTROL); | |
1714 | dev_priv->fbc.false_color = val; | |
1715 | ||
1716 | I915_WRITE(ILK_DPFC_CONTROL, val ? | |
1717 | (reg | FBC_CTL_FALSE_COLOR) : | |
1718 | (reg & ~FBC_CTL_FALSE_COLOR)); | |
1719 | ||
25ad93fd | 1720 | mutex_unlock(&dev_priv->fbc.lock); |
da46f936 RV |
1721 | return 0; |
1722 | } | |
1723 | ||
1724 | DEFINE_SIMPLE_ATTRIBUTE(i915_fbc_fc_fops, | |
1725 | i915_fbc_fc_get, i915_fbc_fc_set, | |
1726 | "%llu\n"); | |
1727 | ||
92d44621 PZ |
1728 | static int i915_ips_status(struct seq_file *m, void *unused) |
1729 | { | |
36cdd013 | 1730 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
92d44621 | 1731 | |
36cdd013 | 1732 | if (!HAS_IPS(dev_priv)) { |
92d44621 PZ |
1733 | seq_puts(m, "not supported\n"); |
1734 | return 0; | |
1735 | } | |
1736 | ||
36623ef8 PZ |
1737 | intel_runtime_pm_get(dev_priv); |
1738 | ||
0eaa53f0 RV |
1739 | seq_printf(m, "Enabled by kernel parameter: %s\n", |
1740 | yesno(i915.enable_ips)); | |
1741 | ||
36cdd013 | 1742 | if (INTEL_GEN(dev_priv) >= 8) { |
0eaa53f0 RV |
1743 | seq_puts(m, "Currently: unknown\n"); |
1744 | } else { | |
1745 | if (I915_READ(IPS_CTL) & IPS_ENABLE) | |
1746 | seq_puts(m, "Currently: enabled\n"); | |
1747 | else | |
1748 | seq_puts(m, "Currently: disabled\n"); | |
1749 | } | |
92d44621 | 1750 | |
36623ef8 PZ |
1751 | intel_runtime_pm_put(dev_priv); |
1752 | ||
92d44621 PZ |
1753 | return 0; |
1754 | } | |
1755 | ||
4a9bef37 JB |
1756 | static int i915_sr_status(struct seq_file *m, void *unused) |
1757 | { | |
36cdd013 | 1758 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
4a9bef37 JB |
1759 | bool sr_enabled = false; |
1760 | ||
36623ef8 | 1761 | intel_runtime_pm_get(dev_priv); |
9c870d03 | 1762 | intel_display_power_get(dev_priv, POWER_DOMAIN_INIT); |
36623ef8 | 1763 | |
36cdd013 | 1764 | if (HAS_PCH_SPLIT(dev_priv)) |
5ba2aaaa | 1765 | sr_enabled = I915_READ(WM1_LP_ILK) & WM1_LP_SR_EN; |
36cdd013 DW |
1766 | else if (IS_CRESTLINE(dev_priv) || IS_G4X(dev_priv) || |
1767 | IS_I945G(dev_priv) || IS_I945GM(dev_priv)) | |
4a9bef37 | 1768 | sr_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN; |
36cdd013 | 1769 | else if (IS_I915GM(dev_priv)) |
4a9bef37 | 1770 | sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN; |
36cdd013 | 1771 | else if (IS_PINEVIEW(dev_priv)) |
4a9bef37 | 1772 | sr_enabled = I915_READ(DSPFW3) & PINEVIEW_SELF_REFRESH_EN; |
36cdd013 | 1773 | else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) |
77b64555 | 1774 | sr_enabled = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN; |
4a9bef37 | 1775 | |
9c870d03 | 1776 | intel_display_power_put(dev_priv, POWER_DOMAIN_INIT); |
36623ef8 PZ |
1777 | intel_runtime_pm_put(dev_priv); |
1778 | ||
5ba2aaaa CW |
1779 | seq_printf(m, "self-refresh: %s\n", |
1780 | sr_enabled ? "enabled" : "disabled"); | |
4a9bef37 JB |
1781 | |
1782 | return 0; | |
1783 | } | |
1784 | ||
7648fa99 JB |
1785 | static int i915_emon_status(struct seq_file *m, void *unused) |
1786 | { | |
36cdd013 DW |
1787 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
1788 | struct drm_device *dev = &dev_priv->drm; | |
7648fa99 | 1789 | unsigned long temp, chipset, gfx; |
de227ef0 CW |
1790 | int ret; |
1791 | ||
36cdd013 | 1792 | if (!IS_GEN5(dev_priv)) |
582be6b4 CW |
1793 | return -ENODEV; |
1794 | ||
de227ef0 CW |
1795 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
1796 | if (ret) | |
1797 | return ret; | |
7648fa99 JB |
1798 | |
1799 | temp = i915_mch_val(dev_priv); | |
1800 | chipset = i915_chipset_val(dev_priv); | |
1801 | gfx = i915_gfx_val(dev_priv); | |
de227ef0 | 1802 | mutex_unlock(&dev->struct_mutex); |
7648fa99 JB |
1803 | |
1804 | seq_printf(m, "GMCH temp: %ld\n", temp); | |
1805 | seq_printf(m, "Chipset power: %ld\n", chipset); | |
1806 | seq_printf(m, "GFX power: %ld\n", gfx); | |
1807 | seq_printf(m, "Total power: %ld\n", chipset + gfx); | |
1808 | ||
1809 | return 0; | |
1810 | } | |
1811 | ||
23b2f8bb JB |
1812 | static int i915_ring_freq_table(struct seq_file *m, void *unused) |
1813 | { | |
36cdd013 | 1814 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
5bfa0199 | 1815 | int ret = 0; |
23b2f8bb | 1816 | int gpu_freq, ia_freq; |
f936ec34 | 1817 | unsigned int max_gpu_freq, min_gpu_freq; |
23b2f8bb | 1818 | |
26310346 | 1819 | if (!HAS_LLC(dev_priv)) { |
267f0c90 | 1820 | seq_puts(m, "unsupported on this chipset\n"); |
23b2f8bb JB |
1821 | return 0; |
1822 | } | |
1823 | ||
5bfa0199 PZ |
1824 | intel_runtime_pm_get(dev_priv); |
1825 | ||
4fc688ce | 1826 | ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock); |
23b2f8bb | 1827 | if (ret) |
5bfa0199 | 1828 | goto out; |
23b2f8bb | 1829 | |
36cdd013 | 1830 | if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) { |
f936ec34 AG |
1831 | /* Convert GT frequency to 50 HZ units */ |
1832 | min_gpu_freq = | |
1833 | dev_priv->rps.min_freq_softlimit / GEN9_FREQ_SCALER; | |
1834 | max_gpu_freq = | |
1835 | dev_priv->rps.max_freq_softlimit / GEN9_FREQ_SCALER; | |
1836 | } else { | |
1837 | min_gpu_freq = dev_priv->rps.min_freq_softlimit; | |
1838 | max_gpu_freq = dev_priv->rps.max_freq_softlimit; | |
1839 | } | |
1840 | ||
267f0c90 | 1841 | seq_puts(m, "GPU freq (MHz)\tEffective CPU freq (MHz)\tEffective Ring freq (MHz)\n"); |
23b2f8bb | 1842 | |
f936ec34 | 1843 | for (gpu_freq = min_gpu_freq; gpu_freq <= max_gpu_freq; gpu_freq++) { |
42c0526c BW |
1844 | ia_freq = gpu_freq; |
1845 | sandybridge_pcode_read(dev_priv, | |
1846 | GEN6_PCODE_READ_MIN_FREQ_TABLE, | |
1847 | &ia_freq); | |
3ebecd07 | 1848 | seq_printf(m, "%d\t\t%d\t\t\t\t%d\n", |
f936ec34 | 1849 | intel_gpu_freq(dev_priv, (gpu_freq * |
36cdd013 | 1850 | (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv) ? |
ef11bdb3 | 1851 | GEN9_FREQ_SCALER : 1))), |
3ebecd07 CW |
1852 | ((ia_freq >> 0) & 0xff) * 100, |
1853 | ((ia_freq >> 8) & 0xff) * 100); | |
23b2f8bb JB |
1854 | } |
1855 | ||
4fc688ce | 1856 | mutex_unlock(&dev_priv->rps.hw_lock); |
23b2f8bb | 1857 | |
5bfa0199 PZ |
1858 | out: |
1859 | intel_runtime_pm_put(dev_priv); | |
1860 | return ret; | |
23b2f8bb JB |
1861 | } |
1862 | ||
44834a67 CW |
1863 | static int i915_opregion(struct seq_file *m, void *unused) |
1864 | { | |
36cdd013 DW |
1865 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
1866 | struct drm_device *dev = &dev_priv->drm; | |
44834a67 CW |
1867 | struct intel_opregion *opregion = &dev_priv->opregion; |
1868 | int ret; | |
1869 | ||
1870 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
1871 | if (ret) | |
0d38f009 | 1872 | goto out; |
44834a67 | 1873 | |
2455a8e4 JN |
1874 | if (opregion->header) |
1875 | seq_write(m, opregion->header, OPREGION_SIZE); | |
44834a67 CW |
1876 | |
1877 | mutex_unlock(&dev->struct_mutex); | |
1878 | ||
0d38f009 | 1879 | out: |
44834a67 CW |
1880 | return 0; |
1881 | } | |
1882 | ||
ada8f955 JN |
1883 | static int i915_vbt(struct seq_file *m, void *unused) |
1884 | { | |
36cdd013 | 1885 | struct intel_opregion *opregion = &node_to_i915(m->private)->opregion; |
ada8f955 JN |
1886 | |
1887 | if (opregion->vbt) | |
1888 | seq_write(m, opregion->vbt, opregion->vbt_size); | |
1889 | ||
1890 | return 0; | |
1891 | } | |
1892 | ||
37811fcc CW |
1893 | static int i915_gem_framebuffer_info(struct seq_file *m, void *data) |
1894 | { | |
36cdd013 DW |
1895 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
1896 | struct drm_device *dev = &dev_priv->drm; | |
b13b8402 | 1897 | struct intel_framebuffer *fbdev_fb = NULL; |
3a58ee10 | 1898 | struct drm_framebuffer *drm_fb; |
188c1ab7 CW |
1899 | int ret; |
1900 | ||
1901 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
1902 | if (ret) | |
1903 | return ret; | |
37811fcc | 1904 | |
0695726e | 1905 | #ifdef CONFIG_DRM_FBDEV_EMULATION |
36cdd013 DW |
1906 | if (dev_priv->fbdev) { |
1907 | fbdev_fb = to_intel_framebuffer(dev_priv->fbdev->helper.fb); | |
25bcce94 CW |
1908 | |
1909 | seq_printf(m, "fbcon size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ", | |
1910 | fbdev_fb->base.width, | |
1911 | fbdev_fb->base.height, | |
1912 | fbdev_fb->base.depth, | |
1913 | fbdev_fb->base.bits_per_pixel, | |
1914 | fbdev_fb->base.modifier[0], | |
1915 | drm_framebuffer_read_refcount(&fbdev_fb->base)); | |
1916 | describe_obj(m, fbdev_fb->obj); | |
1917 | seq_putc(m, '\n'); | |
1918 | } | |
4520f53a | 1919 | #endif |
37811fcc | 1920 | |
4b096ac1 | 1921 | mutex_lock(&dev->mode_config.fb_lock); |
3a58ee10 | 1922 | drm_for_each_fb(drm_fb, dev) { |
b13b8402 NS |
1923 | struct intel_framebuffer *fb = to_intel_framebuffer(drm_fb); |
1924 | if (fb == fbdev_fb) | |
37811fcc CW |
1925 | continue; |
1926 | ||
c1ca506d | 1927 | seq_printf(m, "user size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ", |
37811fcc CW |
1928 | fb->base.width, |
1929 | fb->base.height, | |
1930 | fb->base.depth, | |
623f9783 | 1931 | fb->base.bits_per_pixel, |
c1ca506d | 1932 | fb->base.modifier[0], |
747a598f | 1933 | drm_framebuffer_read_refcount(&fb->base)); |
05394f39 | 1934 | describe_obj(m, fb->obj); |
267f0c90 | 1935 | seq_putc(m, '\n'); |
37811fcc | 1936 | } |
4b096ac1 | 1937 | mutex_unlock(&dev->mode_config.fb_lock); |
188c1ab7 | 1938 | mutex_unlock(&dev->struct_mutex); |
37811fcc CW |
1939 | |
1940 | return 0; | |
1941 | } | |
1942 | ||
7e37f889 | 1943 | static void describe_ctx_ring(struct seq_file *m, struct intel_ring *ring) |
c9fe99bd OM |
1944 | { |
1945 | seq_printf(m, " (ringbuffer, space: %d, head: %u, tail: %u, last head: %d)", | |
7e37f889 CW |
1946 | ring->space, ring->head, ring->tail, |
1947 | ring->last_retired_head); | |
c9fe99bd OM |
1948 | } |
1949 | ||
e76d3630 BW |
1950 | static int i915_context_status(struct seq_file *m, void *unused) |
1951 | { | |
36cdd013 DW |
1952 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
1953 | struct drm_device *dev = &dev_priv->drm; | |
e2f80391 | 1954 | struct intel_engine_cs *engine; |
e2efd130 | 1955 | struct i915_gem_context *ctx; |
3b3f1650 | 1956 | enum intel_engine_id id; |
c3232b18 | 1957 | int ret; |
e76d3630 | 1958 | |
f3d28878 | 1959 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
e76d3630 BW |
1960 | if (ret) |
1961 | return ret; | |
1962 | ||
a33afea5 | 1963 | list_for_each_entry(ctx, &dev_priv->context_list, link) { |
5d1808ec | 1964 | seq_printf(m, "HW context %u ", ctx->hw_id); |
c84455b4 | 1965 | if (ctx->pid) { |
d28b99ab CW |
1966 | struct task_struct *task; |
1967 | ||
c84455b4 | 1968 | task = get_pid_task(ctx->pid, PIDTYPE_PID); |
d28b99ab CW |
1969 | if (task) { |
1970 | seq_printf(m, "(%s [%d]) ", | |
1971 | task->comm, task->pid); | |
1972 | put_task_struct(task); | |
1973 | } | |
c84455b4 CW |
1974 | } else if (IS_ERR(ctx->file_priv)) { |
1975 | seq_puts(m, "(deleted) "); | |
d28b99ab CW |
1976 | } else { |
1977 | seq_puts(m, "(kernel) "); | |
1978 | } | |
1979 | ||
bca44d80 CW |
1980 | seq_putc(m, ctx->remap_slice ? 'R' : 'r'); |
1981 | seq_putc(m, '\n'); | |
c9fe99bd | 1982 | |
3b3f1650 | 1983 | for_each_engine(engine, dev_priv, id) { |
bca44d80 CW |
1984 | struct intel_context *ce = &ctx->engine[engine->id]; |
1985 | ||
1986 | seq_printf(m, "%s: ", engine->name); | |
1987 | seq_putc(m, ce->initialised ? 'I' : 'i'); | |
1988 | if (ce->state) | |
bf3783e5 | 1989 | describe_obj(m, ce->state->obj); |
dca33ecc | 1990 | if (ce->ring) |
7e37f889 | 1991 | describe_ctx_ring(m, ce->ring); |
c9fe99bd | 1992 | seq_putc(m, '\n'); |
c9fe99bd | 1993 | } |
a33afea5 | 1994 | |
a33afea5 | 1995 | seq_putc(m, '\n'); |
a168c293 BW |
1996 | } |
1997 | ||
f3d28878 | 1998 | mutex_unlock(&dev->struct_mutex); |
e76d3630 BW |
1999 | |
2000 | return 0; | |
2001 | } | |
2002 | ||
064ca1d2 | 2003 | static void i915_dump_lrc_obj(struct seq_file *m, |
e2efd130 | 2004 | struct i915_gem_context *ctx, |
0bc40be8 | 2005 | struct intel_engine_cs *engine) |
064ca1d2 | 2006 | { |
bf3783e5 | 2007 | struct i915_vma *vma = ctx->engine[engine->id].state; |
064ca1d2 | 2008 | struct page *page; |
064ca1d2 | 2009 | int j; |
064ca1d2 | 2010 | |
7069b144 CW |
2011 | seq_printf(m, "CONTEXT: %s %u\n", engine->name, ctx->hw_id); |
2012 | ||
bf3783e5 CW |
2013 | if (!vma) { |
2014 | seq_puts(m, "\tFake context\n"); | |
064ca1d2 TD |
2015 | return; |
2016 | } | |
2017 | ||
bf3783e5 CW |
2018 | if (vma->flags & I915_VMA_GLOBAL_BIND) |
2019 | seq_printf(m, "\tBound in GGTT at 0x%08x\n", | |
bde13ebd | 2020 | i915_ggtt_offset(vma)); |
064ca1d2 | 2021 | |
a4f5ea64 | 2022 | if (i915_gem_object_pin_pages(vma->obj)) { |
bf3783e5 | 2023 | seq_puts(m, "\tFailed to get pages for context object\n\n"); |
064ca1d2 TD |
2024 | return; |
2025 | } | |
2026 | ||
bf3783e5 CW |
2027 | page = i915_gem_object_get_page(vma->obj, LRC_STATE_PN); |
2028 | if (page) { | |
2029 | u32 *reg_state = kmap_atomic(page); | |
064ca1d2 TD |
2030 | |
2031 | for (j = 0; j < 0x600 / sizeof(u32) / 4; j += 4) { | |
bf3783e5 CW |
2032 | seq_printf(m, |
2033 | "\t[0x%04x] 0x%08x 0x%08x 0x%08x 0x%08x\n", | |
2034 | j * 4, | |
064ca1d2 TD |
2035 | reg_state[j], reg_state[j + 1], |
2036 | reg_state[j + 2], reg_state[j + 3]); | |
2037 | } | |
2038 | kunmap_atomic(reg_state); | |
2039 | } | |
2040 | ||
a4f5ea64 | 2041 | i915_gem_object_unpin_pages(vma->obj); |
064ca1d2 TD |
2042 | seq_putc(m, '\n'); |
2043 | } | |
2044 | ||
c0ab1ae9 BW |
2045 | static int i915_dump_lrc(struct seq_file *m, void *unused) |
2046 | { | |
36cdd013 DW |
2047 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
2048 | struct drm_device *dev = &dev_priv->drm; | |
e2f80391 | 2049 | struct intel_engine_cs *engine; |
e2efd130 | 2050 | struct i915_gem_context *ctx; |
3b3f1650 | 2051 | enum intel_engine_id id; |
b4ac5afc | 2052 | int ret; |
c0ab1ae9 BW |
2053 | |
2054 | if (!i915.enable_execlists) { | |
2055 | seq_printf(m, "Logical Ring Contexts are disabled\n"); | |
2056 | return 0; | |
2057 | } | |
2058 | ||
2059 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
2060 | if (ret) | |
2061 | return ret; | |
2062 | ||
e28e404c | 2063 | list_for_each_entry(ctx, &dev_priv->context_list, link) |
3b3f1650 | 2064 | for_each_engine(engine, dev_priv, id) |
24f1d3cc | 2065 | i915_dump_lrc_obj(m, ctx, engine); |
c0ab1ae9 BW |
2066 | |
2067 | mutex_unlock(&dev->struct_mutex); | |
2068 | ||
2069 | return 0; | |
2070 | } | |
2071 | ||
ea16a3cd DV |
2072 | static const char *swizzle_string(unsigned swizzle) |
2073 | { | |
aee56cff | 2074 | switch (swizzle) { |
ea16a3cd DV |
2075 | case I915_BIT_6_SWIZZLE_NONE: |
2076 | return "none"; | |
2077 | case I915_BIT_6_SWIZZLE_9: | |
2078 | return "bit9"; | |
2079 | case I915_BIT_6_SWIZZLE_9_10: | |
2080 | return "bit9/bit10"; | |
2081 | case I915_BIT_6_SWIZZLE_9_11: | |
2082 | return "bit9/bit11"; | |
2083 | case I915_BIT_6_SWIZZLE_9_10_11: | |
2084 | return "bit9/bit10/bit11"; | |
2085 | case I915_BIT_6_SWIZZLE_9_17: | |
2086 | return "bit9/bit17"; | |
2087 | case I915_BIT_6_SWIZZLE_9_10_17: | |
2088 | return "bit9/bit10/bit17"; | |
2089 | case I915_BIT_6_SWIZZLE_UNKNOWN: | |
8a168ca7 | 2090 | return "unknown"; |
ea16a3cd DV |
2091 | } |
2092 | ||
2093 | return "bug"; | |
2094 | } | |
2095 | ||
2096 | static int i915_swizzle_info(struct seq_file *m, void *data) | |
2097 | { | |
36cdd013 | 2098 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
22bcfc6a | 2099 | |
c8c8fb33 | 2100 | intel_runtime_pm_get(dev_priv); |
ea16a3cd | 2101 | |
ea16a3cd DV |
2102 | seq_printf(m, "bit6 swizzle for X-tiling = %s\n", |
2103 | swizzle_string(dev_priv->mm.bit_6_swizzle_x)); | |
2104 | seq_printf(m, "bit6 swizzle for Y-tiling = %s\n", | |
2105 | swizzle_string(dev_priv->mm.bit_6_swizzle_y)); | |
2106 | ||
36cdd013 | 2107 | if (IS_GEN3(dev_priv) || IS_GEN4(dev_priv)) { |
ea16a3cd DV |
2108 | seq_printf(m, "DDC = 0x%08x\n", |
2109 | I915_READ(DCC)); | |
656bfa3a DV |
2110 | seq_printf(m, "DDC2 = 0x%08x\n", |
2111 | I915_READ(DCC2)); | |
ea16a3cd DV |
2112 | seq_printf(m, "C0DRB3 = 0x%04x\n", |
2113 | I915_READ16(C0DRB3)); | |
2114 | seq_printf(m, "C1DRB3 = 0x%04x\n", | |
2115 | I915_READ16(C1DRB3)); | |
36cdd013 | 2116 | } else if (INTEL_GEN(dev_priv) >= 6) { |
3fa7d235 DV |
2117 | seq_printf(m, "MAD_DIMM_C0 = 0x%08x\n", |
2118 | I915_READ(MAD_DIMM_C0)); | |
2119 | seq_printf(m, "MAD_DIMM_C1 = 0x%08x\n", | |
2120 | I915_READ(MAD_DIMM_C1)); | |
2121 | seq_printf(m, "MAD_DIMM_C2 = 0x%08x\n", | |
2122 | I915_READ(MAD_DIMM_C2)); | |
2123 | seq_printf(m, "TILECTL = 0x%08x\n", | |
2124 | I915_READ(TILECTL)); | |
36cdd013 | 2125 | if (INTEL_GEN(dev_priv) >= 8) |
9d3203e1 BW |
2126 | seq_printf(m, "GAMTARBMODE = 0x%08x\n", |
2127 | I915_READ(GAMTARBMODE)); | |
2128 | else | |
2129 | seq_printf(m, "ARB_MODE = 0x%08x\n", | |
2130 | I915_READ(ARB_MODE)); | |
3fa7d235 DV |
2131 | seq_printf(m, "DISP_ARB_CTL = 0x%08x\n", |
2132 | I915_READ(DISP_ARB_CTL)); | |
ea16a3cd | 2133 | } |
656bfa3a DV |
2134 | |
2135 | if (dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES) | |
2136 | seq_puts(m, "L-shaped memory detected\n"); | |
2137 | ||
c8c8fb33 | 2138 | intel_runtime_pm_put(dev_priv); |
ea16a3cd DV |
2139 | |
2140 | return 0; | |
2141 | } | |
2142 | ||
1c60fef5 BW |
2143 | static int per_file_ctx(int id, void *ptr, void *data) |
2144 | { | |
e2efd130 | 2145 | struct i915_gem_context *ctx = ptr; |
1c60fef5 | 2146 | struct seq_file *m = data; |
ae6c4806 DV |
2147 | struct i915_hw_ppgtt *ppgtt = ctx->ppgtt; |
2148 | ||
2149 | if (!ppgtt) { | |
2150 | seq_printf(m, " no ppgtt for context %d\n", | |
2151 | ctx->user_handle); | |
2152 | return 0; | |
2153 | } | |
1c60fef5 | 2154 | |
f83d6518 OM |
2155 | if (i915_gem_context_is_default(ctx)) |
2156 | seq_puts(m, " default context:\n"); | |
2157 | else | |
821d66dd | 2158 | seq_printf(m, " context %d:\n", ctx->user_handle); |
1c60fef5 BW |
2159 | ppgtt->debug_dump(ppgtt, m); |
2160 | ||
2161 | return 0; | |
2162 | } | |
2163 | ||
36cdd013 DW |
2164 | static void gen8_ppgtt_info(struct seq_file *m, |
2165 | struct drm_i915_private *dev_priv) | |
3cf17fc5 | 2166 | { |
77df6772 | 2167 | struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt; |
3b3f1650 AG |
2168 | struct intel_engine_cs *engine; |
2169 | enum intel_engine_id id; | |
b4ac5afc | 2170 | int i; |
3cf17fc5 | 2171 | |
77df6772 BW |
2172 | if (!ppgtt) |
2173 | return; | |
2174 | ||
3b3f1650 | 2175 | for_each_engine(engine, dev_priv, id) { |
e2f80391 | 2176 | seq_printf(m, "%s\n", engine->name); |
77df6772 | 2177 | for (i = 0; i < 4; i++) { |
e2f80391 | 2178 | u64 pdp = I915_READ(GEN8_RING_PDP_UDW(engine, i)); |
77df6772 | 2179 | pdp <<= 32; |
e2f80391 | 2180 | pdp |= I915_READ(GEN8_RING_PDP_LDW(engine, i)); |
a2a5b15c | 2181 | seq_printf(m, "\tPDP%d 0x%016llx\n", i, pdp); |
77df6772 BW |
2182 | } |
2183 | } | |
2184 | } | |
2185 | ||
36cdd013 DW |
2186 | static void gen6_ppgtt_info(struct seq_file *m, |
2187 | struct drm_i915_private *dev_priv) | |
77df6772 | 2188 | { |
e2f80391 | 2189 | struct intel_engine_cs *engine; |
3b3f1650 | 2190 | enum intel_engine_id id; |
3cf17fc5 | 2191 | |
7e22dbbb | 2192 | if (IS_GEN6(dev_priv)) |
3cf17fc5 DV |
2193 | seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(GFX_MODE)); |
2194 | ||
3b3f1650 | 2195 | for_each_engine(engine, dev_priv, id) { |
e2f80391 | 2196 | seq_printf(m, "%s\n", engine->name); |
7e22dbbb | 2197 | if (IS_GEN7(dev_priv)) |
e2f80391 TU |
2198 | seq_printf(m, "GFX_MODE: 0x%08x\n", |
2199 | I915_READ(RING_MODE_GEN7(engine))); | |
2200 | seq_printf(m, "PP_DIR_BASE: 0x%08x\n", | |
2201 | I915_READ(RING_PP_DIR_BASE(engine))); | |
2202 | seq_printf(m, "PP_DIR_BASE_READ: 0x%08x\n", | |
2203 | I915_READ(RING_PP_DIR_BASE_READ(engine))); | |
2204 | seq_printf(m, "PP_DIR_DCLV: 0x%08x\n", | |
2205 | I915_READ(RING_PP_DIR_DCLV(engine))); | |
3cf17fc5 DV |
2206 | } |
2207 | if (dev_priv->mm.aliasing_ppgtt) { | |
2208 | struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt; | |
2209 | ||
267f0c90 | 2210 | seq_puts(m, "aliasing PPGTT:\n"); |
44159ddb | 2211 | seq_printf(m, "pd gtt offset: 0x%08x\n", ppgtt->pd.base.ggtt_offset); |
1c60fef5 | 2212 | |
87d60b63 | 2213 | ppgtt->debug_dump(ppgtt, m); |
ae6c4806 | 2214 | } |
1c60fef5 | 2215 | |
3cf17fc5 | 2216 | seq_printf(m, "ECOCHK: 0x%08x\n", I915_READ(GAM_ECOCHK)); |
77df6772 BW |
2217 | } |
2218 | ||
2219 | static int i915_ppgtt_info(struct seq_file *m, void *data) | |
2220 | { | |
36cdd013 DW |
2221 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
2222 | struct drm_device *dev = &dev_priv->drm; | |
ea91e401 | 2223 | struct drm_file *file; |
637ee29e | 2224 | int ret; |
77df6772 | 2225 | |
637ee29e CW |
2226 | mutex_lock(&dev->filelist_mutex); |
2227 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
77df6772 | 2228 | if (ret) |
637ee29e CW |
2229 | goto out_unlock; |
2230 | ||
c8c8fb33 | 2231 | intel_runtime_pm_get(dev_priv); |
77df6772 | 2232 | |
36cdd013 DW |
2233 | if (INTEL_GEN(dev_priv) >= 8) |
2234 | gen8_ppgtt_info(m, dev_priv); | |
2235 | else if (INTEL_GEN(dev_priv) >= 6) | |
2236 | gen6_ppgtt_info(m, dev_priv); | |
77df6772 | 2237 | |
ea91e401 MT |
2238 | list_for_each_entry_reverse(file, &dev->filelist, lhead) { |
2239 | struct drm_i915_file_private *file_priv = file->driver_priv; | |
7cb5dff8 | 2240 | struct task_struct *task; |
ea91e401 | 2241 | |
7cb5dff8 | 2242 | task = get_pid_task(file->pid, PIDTYPE_PID); |
06812760 DC |
2243 | if (!task) { |
2244 | ret = -ESRCH; | |
637ee29e | 2245 | goto out_rpm; |
06812760 | 2246 | } |
7cb5dff8 GT |
2247 | seq_printf(m, "\nproc: %s\n", task->comm); |
2248 | put_task_struct(task); | |
ea91e401 MT |
2249 | idr_for_each(&file_priv->context_idr, per_file_ctx, |
2250 | (void *)(unsigned long)m); | |
2251 | } | |
2252 | ||
637ee29e | 2253 | out_rpm: |
c8c8fb33 | 2254 | intel_runtime_pm_put(dev_priv); |
3cf17fc5 | 2255 | mutex_unlock(&dev->struct_mutex); |
637ee29e CW |
2256 | out_unlock: |
2257 | mutex_unlock(&dev->filelist_mutex); | |
06812760 | 2258 | return ret; |
3cf17fc5 DV |
2259 | } |
2260 | ||
f5a4c67d CW |
2261 | static int count_irq_waiters(struct drm_i915_private *i915) |
2262 | { | |
e2f80391 | 2263 | struct intel_engine_cs *engine; |
3b3f1650 | 2264 | enum intel_engine_id id; |
f5a4c67d | 2265 | int count = 0; |
f5a4c67d | 2266 | |
3b3f1650 | 2267 | for_each_engine(engine, i915, id) |
688e6c72 | 2268 | count += intel_engine_has_waiter(engine); |
f5a4c67d CW |
2269 | |
2270 | return count; | |
2271 | } | |
2272 | ||
7466c291 CW |
2273 | static const char *rps_power_to_str(unsigned int power) |
2274 | { | |
2275 | static const char * const strings[] = { | |
2276 | [LOW_POWER] = "low power", | |
2277 | [BETWEEN] = "mixed", | |
2278 | [HIGH_POWER] = "high power", | |
2279 | }; | |
2280 | ||
2281 | if (power >= ARRAY_SIZE(strings) || !strings[power]) | |
2282 | return "unknown"; | |
2283 | ||
2284 | return strings[power]; | |
2285 | } | |
2286 | ||
1854d5ca CW |
2287 | static int i915_rps_boost_info(struct seq_file *m, void *data) |
2288 | { | |
36cdd013 DW |
2289 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
2290 | struct drm_device *dev = &dev_priv->drm; | |
1854d5ca | 2291 | struct drm_file *file; |
1854d5ca | 2292 | |
f5a4c67d | 2293 | seq_printf(m, "RPS enabled? %d\n", dev_priv->rps.enabled); |
67d97da3 CW |
2294 | seq_printf(m, "GPU busy? %s [%x]\n", |
2295 | yesno(dev_priv->gt.awake), dev_priv->gt.active_engines); | |
f5a4c67d | 2296 | seq_printf(m, "CPU waiting? %d\n", count_irq_waiters(dev_priv)); |
7466c291 CW |
2297 | seq_printf(m, "Frequency requested %d\n", |
2298 | intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq)); | |
2299 | seq_printf(m, " min hard:%d, soft:%d; max soft:%d, hard:%d\n", | |
f5a4c67d CW |
2300 | intel_gpu_freq(dev_priv, dev_priv->rps.min_freq), |
2301 | intel_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit), | |
2302 | intel_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit), | |
2303 | intel_gpu_freq(dev_priv, dev_priv->rps.max_freq)); | |
7466c291 CW |
2304 | seq_printf(m, " idle:%d, efficient:%d, boost:%d\n", |
2305 | intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq), | |
2306 | intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq), | |
2307 | intel_gpu_freq(dev_priv, dev_priv->rps.boost_freq)); | |
1d2ac403 DV |
2308 | |
2309 | mutex_lock(&dev->filelist_mutex); | |
8d3afd7d | 2310 | spin_lock(&dev_priv->rps.client_lock); |
1854d5ca CW |
2311 | list_for_each_entry_reverse(file, &dev->filelist, lhead) { |
2312 | struct drm_i915_file_private *file_priv = file->driver_priv; | |
2313 | struct task_struct *task; | |
2314 | ||
2315 | rcu_read_lock(); | |
2316 | task = pid_task(file->pid, PIDTYPE_PID); | |
2317 | seq_printf(m, "%s [%d]: %d boosts%s\n", | |
2318 | task ? task->comm : "<unknown>", | |
2319 | task ? task->pid : -1, | |
2e1b8730 CW |
2320 | file_priv->rps.boosts, |
2321 | list_empty(&file_priv->rps.link) ? "" : ", active"); | |
1854d5ca CW |
2322 | rcu_read_unlock(); |
2323 | } | |
197be2ae | 2324 | seq_printf(m, "Kernel (anonymous) boosts: %d\n", dev_priv->rps.boosts); |
8d3afd7d | 2325 | spin_unlock(&dev_priv->rps.client_lock); |
1d2ac403 | 2326 | mutex_unlock(&dev->filelist_mutex); |
1854d5ca | 2327 | |
7466c291 CW |
2328 | if (INTEL_GEN(dev_priv) >= 6 && |
2329 | dev_priv->rps.enabled && | |
2330 | dev_priv->gt.active_engines) { | |
2331 | u32 rpup, rpupei; | |
2332 | u32 rpdown, rpdownei; | |
2333 | ||
2334 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); | |
2335 | rpup = I915_READ_FW(GEN6_RP_CUR_UP) & GEN6_RP_EI_MASK; | |
2336 | rpupei = I915_READ_FW(GEN6_RP_CUR_UP_EI) & GEN6_RP_EI_MASK; | |
2337 | rpdown = I915_READ_FW(GEN6_RP_CUR_DOWN) & GEN6_RP_EI_MASK; | |
2338 | rpdownei = I915_READ_FW(GEN6_RP_CUR_DOWN_EI) & GEN6_RP_EI_MASK; | |
2339 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); | |
2340 | ||
2341 | seq_printf(m, "\nRPS Autotuning (current \"%s\" window):\n", | |
2342 | rps_power_to_str(dev_priv->rps.power)); | |
2343 | seq_printf(m, " Avg. up: %d%% [above threshold? %d%%]\n", | |
2344 | 100 * rpup / rpupei, | |
2345 | dev_priv->rps.up_threshold); | |
2346 | seq_printf(m, " Avg. down: %d%% [below threshold? %d%%]\n", | |
2347 | 100 * rpdown / rpdownei, | |
2348 | dev_priv->rps.down_threshold); | |
2349 | } else { | |
2350 | seq_puts(m, "\nRPS Autotuning inactive\n"); | |
2351 | } | |
2352 | ||
8d3afd7d | 2353 | return 0; |
1854d5ca CW |
2354 | } |
2355 | ||
63573eb7 BW |
2356 | static int i915_llc(struct seq_file *m, void *data) |
2357 | { | |
36cdd013 | 2358 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
3accaf7e | 2359 | const bool edram = INTEL_GEN(dev_priv) > 8; |
63573eb7 | 2360 | |
36cdd013 | 2361 | seq_printf(m, "LLC: %s\n", yesno(HAS_LLC(dev_priv))); |
3accaf7e MK |
2362 | seq_printf(m, "%s: %lluMB\n", edram ? "eDRAM" : "eLLC", |
2363 | intel_uncore_edram_size(dev_priv)/1024/1024); | |
63573eb7 BW |
2364 | |
2365 | return 0; | |
2366 | } | |
2367 | ||
fdf5d357 AD |
2368 | static int i915_guc_load_status_info(struct seq_file *m, void *data) |
2369 | { | |
36cdd013 | 2370 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
fdf5d357 AD |
2371 | struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw; |
2372 | u32 tmp, i; | |
2373 | ||
2d1fe073 | 2374 | if (!HAS_GUC_UCODE(dev_priv)) |
fdf5d357 AD |
2375 | return 0; |
2376 | ||
2377 | seq_printf(m, "GuC firmware status:\n"); | |
2378 | seq_printf(m, "\tpath: %s\n", | |
2379 | guc_fw->guc_fw_path); | |
2380 | seq_printf(m, "\tfetch: %s\n", | |
2381 | intel_guc_fw_status_repr(guc_fw->guc_fw_fetch_status)); | |
2382 | seq_printf(m, "\tload: %s\n", | |
2383 | intel_guc_fw_status_repr(guc_fw->guc_fw_load_status)); | |
2384 | seq_printf(m, "\tversion wanted: %d.%d\n", | |
2385 | guc_fw->guc_fw_major_wanted, guc_fw->guc_fw_minor_wanted); | |
2386 | seq_printf(m, "\tversion found: %d.%d\n", | |
2387 | guc_fw->guc_fw_major_found, guc_fw->guc_fw_minor_found); | |
feda33ef AD |
2388 | seq_printf(m, "\theader: offset is %d; size = %d\n", |
2389 | guc_fw->header_offset, guc_fw->header_size); | |
2390 | seq_printf(m, "\tuCode: offset is %d; size = %d\n", | |
2391 | guc_fw->ucode_offset, guc_fw->ucode_size); | |
2392 | seq_printf(m, "\tRSA: offset is %d; size = %d\n", | |
2393 | guc_fw->rsa_offset, guc_fw->rsa_size); | |
fdf5d357 AD |
2394 | |
2395 | tmp = I915_READ(GUC_STATUS); | |
2396 | ||
2397 | seq_printf(m, "\nGuC status 0x%08x:\n", tmp); | |
2398 | seq_printf(m, "\tBootrom status = 0x%x\n", | |
2399 | (tmp & GS_BOOTROM_MASK) >> GS_BOOTROM_SHIFT); | |
2400 | seq_printf(m, "\tuKernel status = 0x%x\n", | |
2401 | (tmp & GS_UKERNEL_MASK) >> GS_UKERNEL_SHIFT); | |
2402 | seq_printf(m, "\tMIA Core status = 0x%x\n", | |
2403 | (tmp & GS_MIA_MASK) >> GS_MIA_SHIFT); | |
2404 | seq_puts(m, "\nScratch registers:\n"); | |
2405 | for (i = 0; i < 16; i++) | |
2406 | seq_printf(m, "\t%2d: \t0x%x\n", i, I915_READ(SOFT_SCRATCH(i))); | |
2407 | ||
2408 | return 0; | |
2409 | } | |
2410 | ||
5aa1ee4b AG |
2411 | static void i915_guc_log_info(struct seq_file *m, |
2412 | struct drm_i915_private *dev_priv) | |
2413 | { | |
2414 | struct intel_guc *guc = &dev_priv->guc; | |
2415 | ||
2416 | seq_puts(m, "\nGuC logging stats:\n"); | |
2417 | ||
2418 | seq_printf(m, "\tISR: flush count %10u, overflow count %10u\n", | |
2419 | guc->log.flush_count[GUC_ISR_LOG_BUFFER], | |
2420 | guc->log.total_overflow_count[GUC_ISR_LOG_BUFFER]); | |
2421 | ||
2422 | seq_printf(m, "\tDPC: flush count %10u, overflow count %10u\n", | |
2423 | guc->log.flush_count[GUC_DPC_LOG_BUFFER], | |
2424 | guc->log.total_overflow_count[GUC_DPC_LOG_BUFFER]); | |
2425 | ||
2426 | seq_printf(m, "\tCRASH: flush count %10u, overflow count %10u\n", | |
2427 | guc->log.flush_count[GUC_CRASH_DUMP_LOG_BUFFER], | |
2428 | guc->log.total_overflow_count[GUC_CRASH_DUMP_LOG_BUFFER]); | |
2429 | ||
2430 | seq_printf(m, "\tTotal flush interrupt count: %u\n", | |
2431 | guc->log.flush_interrupt_count); | |
2432 | ||
2433 | seq_printf(m, "\tCapture miss count: %u\n", | |
2434 | guc->log.capture_miss_count); | |
2435 | } | |
2436 | ||
8b417c26 DG |
2437 | static void i915_guc_client_info(struct seq_file *m, |
2438 | struct drm_i915_private *dev_priv, | |
2439 | struct i915_guc_client *client) | |
2440 | { | |
e2f80391 | 2441 | struct intel_engine_cs *engine; |
c18468c4 | 2442 | enum intel_engine_id id; |
8b417c26 | 2443 | uint64_t tot = 0; |
8b417c26 DG |
2444 | |
2445 | seq_printf(m, "\tPriority %d, GuC ctx index: %u, PD offset 0x%x\n", | |
2446 | client->priority, client->ctx_index, client->proc_desc_offset); | |
2447 | seq_printf(m, "\tDoorbell id %d, offset: 0x%x, cookie 0x%x\n", | |
2448 | client->doorbell_id, client->doorbell_offset, client->cookie); | |
2449 | seq_printf(m, "\tWQ size %d, offset: 0x%x, tail %d\n", | |
2450 | client->wq_size, client->wq_offset, client->wq_tail); | |
2451 | ||
551aaecd | 2452 | seq_printf(m, "\tWork queue full: %u\n", client->no_wq_space); |
8b417c26 DG |
2453 | seq_printf(m, "\tFailed doorbell: %u\n", client->b_fail); |
2454 | seq_printf(m, "\tLast submission result: %d\n", client->retcode); | |
2455 | ||
3b3f1650 | 2456 | for_each_engine(engine, dev_priv, id) { |
c18468c4 DG |
2457 | u64 submissions = client->submissions[id]; |
2458 | tot += submissions; | |
8b417c26 | 2459 | seq_printf(m, "\tSubmissions: %llu %s\n", |
c18468c4 | 2460 | submissions, engine->name); |
8b417c26 DG |
2461 | } |
2462 | seq_printf(m, "\tTotal: %llu\n", tot); | |
2463 | } | |
2464 | ||
2465 | static int i915_guc_info(struct seq_file *m, void *data) | |
2466 | { | |
36cdd013 DW |
2467 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
2468 | struct drm_device *dev = &dev_priv->drm; | |
8b417c26 | 2469 | struct intel_guc guc; |
0a0b457f | 2470 | struct i915_guc_client client = {}; |
e2f80391 | 2471 | struct intel_engine_cs *engine; |
c18468c4 | 2472 | enum intel_engine_id id; |
8b417c26 DG |
2473 | u64 total = 0; |
2474 | ||
2d1fe073 | 2475 | if (!HAS_GUC_SCHED(dev_priv)) |
8b417c26 DG |
2476 | return 0; |
2477 | ||
5a843307 AD |
2478 | if (mutex_lock_interruptible(&dev->struct_mutex)) |
2479 | return 0; | |
2480 | ||
8b417c26 | 2481 | /* Take a local copy of the GuC data, so we can dump it at leisure */ |
8b417c26 | 2482 | guc = dev_priv->guc; |
5a843307 | 2483 | if (guc.execbuf_client) |
8b417c26 | 2484 | client = *guc.execbuf_client; |
5a843307 AD |
2485 | |
2486 | mutex_unlock(&dev->struct_mutex); | |
8b417c26 | 2487 | |
9636f6db DG |
2488 | seq_printf(m, "Doorbell map:\n"); |
2489 | seq_printf(m, "\t%*pb\n", GUC_MAX_DOORBELLS, guc.doorbell_bitmap); | |
2490 | seq_printf(m, "Doorbell next cacheline: 0x%x\n\n", guc.db_cacheline); | |
2491 | ||
8b417c26 DG |
2492 | seq_printf(m, "GuC total action count: %llu\n", guc.action_count); |
2493 | seq_printf(m, "GuC action failure count: %u\n", guc.action_fail); | |
2494 | seq_printf(m, "GuC last action command: 0x%x\n", guc.action_cmd); | |
2495 | seq_printf(m, "GuC last action status: 0x%x\n", guc.action_status); | |
2496 | seq_printf(m, "GuC last action error code: %d\n", guc.action_err); | |
2497 | ||
2498 | seq_printf(m, "\nGuC submissions:\n"); | |
3b3f1650 | 2499 | for_each_engine(engine, dev_priv, id) { |
c18468c4 DG |
2500 | u64 submissions = guc.submissions[id]; |
2501 | total += submissions; | |
397097b0 | 2502 | seq_printf(m, "\t%-24s: %10llu, last seqno 0x%08x\n", |
c18468c4 | 2503 | engine->name, submissions, guc.last_seqno[id]); |
8b417c26 DG |
2504 | } |
2505 | seq_printf(m, "\t%s: %llu\n", "Total", total); | |
2506 | ||
2507 | seq_printf(m, "\nGuC execbuf client @ %p:\n", guc.execbuf_client); | |
2508 | i915_guc_client_info(m, dev_priv, &client); | |
2509 | ||
5aa1ee4b AG |
2510 | i915_guc_log_info(m, dev_priv); |
2511 | ||
8b417c26 DG |
2512 | /* Add more as required ... */ |
2513 | ||
2514 | return 0; | |
2515 | } | |
2516 | ||
4c7e77fc AD |
2517 | static int i915_guc_log_dump(struct seq_file *m, void *data) |
2518 | { | |
36cdd013 | 2519 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
8b797af1 | 2520 | struct drm_i915_gem_object *obj; |
4c7e77fc AD |
2521 | int i = 0, pg; |
2522 | ||
d6b40b4b | 2523 | if (!dev_priv->guc.log.vma) |
4c7e77fc AD |
2524 | return 0; |
2525 | ||
d6b40b4b | 2526 | obj = dev_priv->guc.log.vma->obj; |
8b797af1 CW |
2527 | for (pg = 0; pg < obj->base.size / PAGE_SIZE; pg++) { |
2528 | u32 *log = kmap_atomic(i915_gem_object_get_page(obj, pg)); | |
4c7e77fc AD |
2529 | |
2530 | for (i = 0; i < PAGE_SIZE / sizeof(u32); i += 4) | |
2531 | seq_printf(m, "0x%08x 0x%08x 0x%08x 0x%08x\n", | |
2532 | *(log + i), *(log + i + 1), | |
2533 | *(log + i + 2), *(log + i + 3)); | |
2534 | ||
2535 | kunmap_atomic(log); | |
2536 | } | |
2537 | ||
2538 | seq_putc(m, '\n'); | |
2539 | ||
2540 | return 0; | |
2541 | } | |
2542 | ||
685534ef SAK |
2543 | static int i915_guc_log_control_get(void *data, u64 *val) |
2544 | { | |
2545 | struct drm_device *dev = data; | |
2546 | struct drm_i915_private *dev_priv = to_i915(dev); | |
2547 | ||
2548 | if (!dev_priv->guc.log.vma) | |
2549 | return -EINVAL; | |
2550 | ||
2551 | *val = i915.guc_log_level; | |
2552 | ||
2553 | return 0; | |
2554 | } | |
2555 | ||
2556 | static int i915_guc_log_control_set(void *data, u64 val) | |
2557 | { | |
2558 | struct drm_device *dev = data; | |
2559 | struct drm_i915_private *dev_priv = to_i915(dev); | |
2560 | int ret; | |
2561 | ||
2562 | if (!dev_priv->guc.log.vma) | |
2563 | return -EINVAL; | |
2564 | ||
2565 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
2566 | if (ret) | |
2567 | return ret; | |
2568 | ||
2569 | intel_runtime_pm_get(dev_priv); | |
2570 | ret = i915_guc_log_control(dev_priv, val); | |
2571 | intel_runtime_pm_put(dev_priv); | |
2572 | ||
2573 | mutex_unlock(&dev->struct_mutex); | |
2574 | return ret; | |
2575 | } | |
2576 | ||
2577 | DEFINE_SIMPLE_ATTRIBUTE(i915_guc_log_control_fops, | |
2578 | i915_guc_log_control_get, i915_guc_log_control_set, | |
2579 | "%lld\n"); | |
2580 | ||
e91fd8c6 RV |
2581 | static int i915_edp_psr_status(struct seq_file *m, void *data) |
2582 | { | |
36cdd013 | 2583 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
a031d709 | 2584 | u32 psrperf = 0; |
a6cbdb8e RV |
2585 | u32 stat[3]; |
2586 | enum pipe pipe; | |
a031d709 | 2587 | bool enabled = false; |
e91fd8c6 | 2588 | |
36cdd013 | 2589 | if (!HAS_PSR(dev_priv)) { |
3553a8ea DL |
2590 | seq_puts(m, "PSR not supported\n"); |
2591 | return 0; | |
2592 | } | |
2593 | ||
c8c8fb33 PZ |
2594 | intel_runtime_pm_get(dev_priv); |
2595 | ||
fa128fa6 | 2596 | mutex_lock(&dev_priv->psr.lock); |
a031d709 RV |
2597 | seq_printf(m, "Sink_Support: %s\n", yesno(dev_priv->psr.sink_support)); |
2598 | seq_printf(m, "Source_OK: %s\n", yesno(dev_priv->psr.source_ok)); | |
2807cf69 | 2599 | seq_printf(m, "Enabled: %s\n", yesno((bool)dev_priv->psr.enabled)); |
5755c78f | 2600 | seq_printf(m, "Active: %s\n", yesno(dev_priv->psr.active)); |
fa128fa6 DV |
2601 | seq_printf(m, "Busy frontbuffer bits: 0x%03x\n", |
2602 | dev_priv->psr.busy_frontbuffer_bits); | |
2603 | seq_printf(m, "Re-enable work scheduled: %s\n", | |
2604 | yesno(work_busy(&dev_priv->psr.work.work))); | |
e91fd8c6 | 2605 | |
36cdd013 | 2606 | if (HAS_DDI(dev_priv)) |
443a389f | 2607 | enabled = I915_READ(EDP_PSR_CTL) & EDP_PSR_ENABLE; |
3553a8ea DL |
2608 | else { |
2609 | for_each_pipe(dev_priv, pipe) { | |
9c870d03 CW |
2610 | enum transcoder cpu_transcoder = |
2611 | intel_pipe_to_cpu_transcoder(dev_priv, pipe); | |
2612 | enum intel_display_power_domain power_domain; | |
2613 | ||
2614 | power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder); | |
2615 | if (!intel_display_power_get_if_enabled(dev_priv, | |
2616 | power_domain)) | |
2617 | continue; | |
2618 | ||
3553a8ea DL |
2619 | stat[pipe] = I915_READ(VLV_PSRSTAT(pipe)) & |
2620 | VLV_EDP_PSR_CURR_STATE_MASK; | |
2621 | if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) || | |
2622 | (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE)) | |
2623 | enabled = true; | |
9c870d03 CW |
2624 | |
2625 | intel_display_power_put(dev_priv, power_domain); | |
a6cbdb8e RV |
2626 | } |
2627 | } | |
60e5ffe3 RV |
2628 | |
2629 | seq_printf(m, "Main link in standby mode: %s\n", | |
2630 | yesno(dev_priv->psr.link_standby)); | |
2631 | ||
a6cbdb8e RV |
2632 | seq_printf(m, "HW Enabled & Active bit: %s", yesno(enabled)); |
2633 | ||
36cdd013 | 2634 | if (!HAS_DDI(dev_priv)) |
a6cbdb8e RV |
2635 | for_each_pipe(dev_priv, pipe) { |
2636 | if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) || | |
2637 | (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE)) | |
2638 | seq_printf(m, " pipe %c", pipe_name(pipe)); | |
2639 | } | |
2640 | seq_puts(m, "\n"); | |
e91fd8c6 | 2641 | |
05eec3c2 RV |
2642 | /* |
2643 | * VLV/CHV PSR has no kind of performance counter | |
2644 | * SKL+ Perf counter is reset to 0 everytime DC state is entered | |
2645 | */ | |
36cdd013 | 2646 | if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) { |
443a389f | 2647 | psrperf = I915_READ(EDP_PSR_PERF_CNT) & |
a031d709 | 2648 | EDP_PSR_PERF_CNT_MASK; |
a6cbdb8e RV |
2649 | |
2650 | seq_printf(m, "Performance_Counter: %u\n", psrperf); | |
2651 | } | |
fa128fa6 | 2652 | mutex_unlock(&dev_priv->psr.lock); |
e91fd8c6 | 2653 | |
c8c8fb33 | 2654 | intel_runtime_pm_put(dev_priv); |
e91fd8c6 RV |
2655 | return 0; |
2656 | } | |
2657 | ||
d2e216d0 RV |
2658 | static int i915_sink_crc(struct seq_file *m, void *data) |
2659 | { | |
36cdd013 DW |
2660 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
2661 | struct drm_device *dev = &dev_priv->drm; | |
d2e216d0 RV |
2662 | struct intel_connector *connector; |
2663 | struct intel_dp *intel_dp = NULL; | |
2664 | int ret; | |
2665 | u8 crc[6]; | |
2666 | ||
2667 | drm_modeset_lock_all(dev); | |
aca5e361 | 2668 | for_each_intel_connector(dev, connector) { |
26c17cf6 | 2669 | struct drm_crtc *crtc; |
d2e216d0 | 2670 | |
26c17cf6 | 2671 | if (!connector->base.state->best_encoder) |
d2e216d0 RV |
2672 | continue; |
2673 | ||
26c17cf6 ML |
2674 | crtc = connector->base.state->crtc; |
2675 | if (!crtc->state->active) | |
b6ae3c7c PZ |
2676 | continue; |
2677 | ||
26c17cf6 | 2678 | if (connector->base.connector_type != DRM_MODE_CONNECTOR_eDP) |
d2e216d0 RV |
2679 | continue; |
2680 | ||
26c17cf6 | 2681 | intel_dp = enc_to_intel_dp(connector->base.state->best_encoder); |
d2e216d0 RV |
2682 | |
2683 | ret = intel_dp_sink_crc(intel_dp, crc); | |
2684 | if (ret) | |
2685 | goto out; | |
2686 | ||
2687 | seq_printf(m, "%02x%02x%02x%02x%02x%02x\n", | |
2688 | crc[0], crc[1], crc[2], | |
2689 | crc[3], crc[4], crc[5]); | |
2690 | goto out; | |
2691 | } | |
2692 | ret = -ENODEV; | |
2693 | out: | |
2694 | drm_modeset_unlock_all(dev); | |
2695 | return ret; | |
2696 | } | |
2697 | ||
ec013e7f JB |
2698 | static int i915_energy_uJ(struct seq_file *m, void *data) |
2699 | { | |
36cdd013 | 2700 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
ec013e7f JB |
2701 | u64 power; |
2702 | u32 units; | |
2703 | ||
36cdd013 | 2704 | if (INTEL_GEN(dev_priv) < 6) |
ec013e7f JB |
2705 | return -ENODEV; |
2706 | ||
36623ef8 PZ |
2707 | intel_runtime_pm_get(dev_priv); |
2708 | ||
ec013e7f JB |
2709 | rdmsrl(MSR_RAPL_POWER_UNIT, power); |
2710 | power = (power & 0x1f00) >> 8; | |
2711 | units = 1000000 / (1 << power); /* convert to uJ */ | |
2712 | power = I915_READ(MCH_SECP_NRG_STTS); | |
2713 | power *= units; | |
2714 | ||
36623ef8 PZ |
2715 | intel_runtime_pm_put(dev_priv); |
2716 | ||
ec013e7f | 2717 | seq_printf(m, "%llu", (long long unsigned)power); |
371db66a PZ |
2718 | |
2719 | return 0; | |
2720 | } | |
2721 | ||
6455c870 | 2722 | static int i915_runtime_pm_status(struct seq_file *m, void *unused) |
371db66a | 2723 | { |
36cdd013 | 2724 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
52a05c30 | 2725 | struct pci_dev *pdev = dev_priv->drm.pdev; |
371db66a | 2726 | |
a156e64d CW |
2727 | if (!HAS_RUNTIME_PM(dev_priv)) |
2728 | seq_puts(m, "Runtime power management not supported\n"); | |
371db66a | 2729 | |
67d97da3 | 2730 | seq_printf(m, "GPU idle: %s\n", yesno(!dev_priv->gt.awake)); |
371db66a | 2731 | seq_printf(m, "IRQs disabled: %s\n", |
9df7575f | 2732 | yesno(!intel_irqs_enabled(dev_priv))); |
0d804184 | 2733 | #ifdef CONFIG_PM |
a6aaec8b | 2734 | seq_printf(m, "Usage count: %d\n", |
36cdd013 | 2735 | atomic_read(&dev_priv->drm.dev->power.usage_count)); |
0d804184 CW |
2736 | #else |
2737 | seq_printf(m, "Device Power Management (CONFIG_PM) disabled\n"); | |
2738 | #endif | |
a156e64d | 2739 | seq_printf(m, "PCI device power state: %s [%d]\n", |
52a05c30 DW |
2740 | pci_power_name(pdev->current_state), |
2741 | pdev->current_state); | |
371db66a | 2742 | |
ec013e7f JB |
2743 | return 0; |
2744 | } | |
2745 | ||
1da51581 ID |
2746 | static int i915_power_domain_info(struct seq_file *m, void *unused) |
2747 | { | |
36cdd013 | 2748 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
1da51581 ID |
2749 | struct i915_power_domains *power_domains = &dev_priv->power_domains; |
2750 | int i; | |
2751 | ||
2752 | mutex_lock(&power_domains->lock); | |
2753 | ||
2754 | seq_printf(m, "%-25s %s\n", "Power well/domain", "Use count"); | |
2755 | for (i = 0; i < power_domains->power_well_count; i++) { | |
2756 | struct i915_power_well *power_well; | |
2757 | enum intel_display_power_domain power_domain; | |
2758 | ||
2759 | power_well = &power_domains->power_wells[i]; | |
2760 | seq_printf(m, "%-25s %d\n", power_well->name, | |
2761 | power_well->count); | |
2762 | ||
2763 | for (power_domain = 0; power_domain < POWER_DOMAIN_NUM; | |
2764 | power_domain++) { | |
2765 | if (!(BIT(power_domain) & power_well->domains)) | |
2766 | continue; | |
2767 | ||
2768 | seq_printf(m, " %-23s %d\n", | |
9895ad03 | 2769 | intel_display_power_domain_str(power_domain), |
1da51581 ID |
2770 | power_domains->domain_use_count[power_domain]); |
2771 | } | |
2772 | } | |
2773 | ||
2774 | mutex_unlock(&power_domains->lock); | |
2775 | ||
2776 | return 0; | |
2777 | } | |
2778 | ||
b7cec66d DL |
2779 | static int i915_dmc_info(struct seq_file *m, void *unused) |
2780 | { | |
36cdd013 | 2781 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
b7cec66d DL |
2782 | struct intel_csr *csr; |
2783 | ||
36cdd013 | 2784 | if (!HAS_CSR(dev_priv)) { |
b7cec66d DL |
2785 | seq_puts(m, "not supported\n"); |
2786 | return 0; | |
2787 | } | |
2788 | ||
2789 | csr = &dev_priv->csr; | |
2790 | ||
6fb403de MK |
2791 | intel_runtime_pm_get(dev_priv); |
2792 | ||
b7cec66d DL |
2793 | seq_printf(m, "fw loaded: %s\n", yesno(csr->dmc_payload != NULL)); |
2794 | seq_printf(m, "path: %s\n", csr->fw_path); | |
2795 | ||
2796 | if (!csr->dmc_payload) | |
6fb403de | 2797 | goto out; |
b7cec66d DL |
2798 | |
2799 | seq_printf(m, "version: %d.%d\n", CSR_VERSION_MAJOR(csr->version), | |
2800 | CSR_VERSION_MINOR(csr->version)); | |
2801 | ||
36cdd013 | 2802 | if (IS_SKYLAKE(dev_priv) && csr->version >= CSR_VERSION(1, 6)) { |
8337206d DL |
2803 | seq_printf(m, "DC3 -> DC5 count: %d\n", |
2804 | I915_READ(SKL_CSR_DC3_DC5_COUNT)); | |
2805 | seq_printf(m, "DC5 -> DC6 count: %d\n", | |
2806 | I915_READ(SKL_CSR_DC5_DC6_COUNT)); | |
36cdd013 | 2807 | } else if (IS_BROXTON(dev_priv) && csr->version >= CSR_VERSION(1, 4)) { |
16e11b99 MK |
2808 | seq_printf(m, "DC3 -> DC5 count: %d\n", |
2809 | I915_READ(BXT_CSR_DC3_DC5_COUNT)); | |
8337206d DL |
2810 | } |
2811 | ||
6fb403de MK |
2812 | out: |
2813 | seq_printf(m, "program base: 0x%08x\n", I915_READ(CSR_PROGRAM(0))); | |
2814 | seq_printf(m, "ssp base: 0x%08x\n", I915_READ(CSR_SSP_BASE)); | |
2815 | seq_printf(m, "htp: 0x%08x\n", I915_READ(CSR_HTP_SKL)); | |
2816 | ||
8337206d DL |
2817 | intel_runtime_pm_put(dev_priv); |
2818 | ||
b7cec66d DL |
2819 | return 0; |
2820 | } | |
2821 | ||
53f5e3ca JB |
2822 | static void intel_seq_print_mode(struct seq_file *m, int tabs, |
2823 | struct drm_display_mode *mode) | |
2824 | { | |
2825 | int i; | |
2826 | ||
2827 | for (i = 0; i < tabs; i++) | |
2828 | seq_putc(m, '\t'); | |
2829 | ||
2830 | seq_printf(m, "id %d:\"%s\" freq %d clock %d hdisp %d hss %d hse %d htot %d vdisp %d vss %d vse %d vtot %d type 0x%x flags 0x%x\n", | |
2831 | mode->base.id, mode->name, | |
2832 | mode->vrefresh, mode->clock, | |
2833 | mode->hdisplay, mode->hsync_start, | |
2834 | mode->hsync_end, mode->htotal, | |
2835 | mode->vdisplay, mode->vsync_start, | |
2836 | mode->vsync_end, mode->vtotal, | |
2837 | mode->type, mode->flags); | |
2838 | } | |
2839 | ||
2840 | static void intel_encoder_info(struct seq_file *m, | |
2841 | struct intel_crtc *intel_crtc, | |
2842 | struct intel_encoder *intel_encoder) | |
2843 | { | |
36cdd013 DW |
2844 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
2845 | struct drm_device *dev = &dev_priv->drm; | |
53f5e3ca JB |
2846 | struct drm_crtc *crtc = &intel_crtc->base; |
2847 | struct intel_connector *intel_connector; | |
2848 | struct drm_encoder *encoder; | |
2849 | ||
2850 | encoder = &intel_encoder->base; | |
2851 | seq_printf(m, "\tencoder %d: type: %s, connectors:\n", | |
8e329a03 | 2852 | encoder->base.id, encoder->name); |
53f5e3ca JB |
2853 | for_each_connector_on_encoder(dev, encoder, intel_connector) { |
2854 | struct drm_connector *connector = &intel_connector->base; | |
2855 | seq_printf(m, "\t\tconnector %d: type: %s, status: %s", | |
2856 | connector->base.id, | |
c23cc417 | 2857 | connector->name, |
53f5e3ca JB |
2858 | drm_get_connector_status_name(connector->status)); |
2859 | if (connector->status == connector_status_connected) { | |
2860 | struct drm_display_mode *mode = &crtc->mode; | |
2861 | seq_printf(m, ", mode:\n"); | |
2862 | intel_seq_print_mode(m, 2, mode); | |
2863 | } else { | |
2864 | seq_putc(m, '\n'); | |
2865 | } | |
2866 | } | |
2867 | } | |
2868 | ||
2869 | static void intel_crtc_info(struct seq_file *m, struct intel_crtc *intel_crtc) | |
2870 | { | |
36cdd013 DW |
2871 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
2872 | struct drm_device *dev = &dev_priv->drm; | |
53f5e3ca JB |
2873 | struct drm_crtc *crtc = &intel_crtc->base; |
2874 | struct intel_encoder *intel_encoder; | |
23a48d53 ML |
2875 | struct drm_plane_state *plane_state = crtc->primary->state; |
2876 | struct drm_framebuffer *fb = plane_state->fb; | |
53f5e3ca | 2877 | |
23a48d53 | 2878 | if (fb) |
5aa8a937 | 2879 | seq_printf(m, "\tfb: %d, pos: %dx%d, size: %dx%d\n", |
23a48d53 ML |
2880 | fb->base.id, plane_state->src_x >> 16, |
2881 | plane_state->src_y >> 16, fb->width, fb->height); | |
5aa8a937 MR |
2882 | else |
2883 | seq_puts(m, "\tprimary plane disabled\n"); | |
53f5e3ca JB |
2884 | for_each_encoder_on_crtc(dev, crtc, intel_encoder) |
2885 | intel_encoder_info(m, intel_crtc, intel_encoder); | |
2886 | } | |
2887 | ||
2888 | static void intel_panel_info(struct seq_file *m, struct intel_panel *panel) | |
2889 | { | |
2890 | struct drm_display_mode *mode = panel->fixed_mode; | |
2891 | ||
2892 | seq_printf(m, "\tfixed mode:\n"); | |
2893 | intel_seq_print_mode(m, 2, mode); | |
2894 | } | |
2895 | ||
2896 | static void intel_dp_info(struct seq_file *m, | |
2897 | struct intel_connector *intel_connector) | |
2898 | { | |
2899 | struct intel_encoder *intel_encoder = intel_connector->encoder; | |
2900 | struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base); | |
2901 | ||
2902 | seq_printf(m, "\tDPCD rev: %x\n", intel_dp->dpcd[DP_DPCD_REV]); | |
742f491d | 2903 | seq_printf(m, "\taudio support: %s\n", yesno(intel_dp->has_audio)); |
b6dabe3b | 2904 | if (intel_connector->base.connector_type == DRM_MODE_CONNECTOR_eDP) |
53f5e3ca | 2905 | intel_panel_info(m, &intel_connector->panel); |
80209e5f MK |
2906 | |
2907 | drm_dp_downstream_debug(m, intel_dp->dpcd, intel_dp->downstream_ports, | |
2908 | &intel_dp->aux); | |
53f5e3ca JB |
2909 | } |
2910 | ||
2911 | static void intel_hdmi_info(struct seq_file *m, | |
2912 | struct intel_connector *intel_connector) | |
2913 | { | |
2914 | struct intel_encoder *intel_encoder = intel_connector->encoder; | |
2915 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&intel_encoder->base); | |
2916 | ||
742f491d | 2917 | seq_printf(m, "\taudio support: %s\n", yesno(intel_hdmi->has_audio)); |
53f5e3ca JB |
2918 | } |
2919 | ||
2920 | static void intel_lvds_info(struct seq_file *m, | |
2921 | struct intel_connector *intel_connector) | |
2922 | { | |
2923 | intel_panel_info(m, &intel_connector->panel); | |
2924 | } | |
2925 | ||
2926 | static void intel_connector_info(struct seq_file *m, | |
2927 | struct drm_connector *connector) | |
2928 | { | |
2929 | struct intel_connector *intel_connector = to_intel_connector(connector); | |
2930 | struct intel_encoder *intel_encoder = intel_connector->encoder; | |
f103fc7d | 2931 | struct drm_display_mode *mode; |
53f5e3ca JB |
2932 | |
2933 | seq_printf(m, "connector %d: type %s, status: %s\n", | |
c23cc417 | 2934 | connector->base.id, connector->name, |
53f5e3ca JB |
2935 | drm_get_connector_status_name(connector->status)); |
2936 | if (connector->status == connector_status_connected) { | |
2937 | seq_printf(m, "\tname: %s\n", connector->display_info.name); | |
2938 | seq_printf(m, "\tphysical dimensions: %dx%dmm\n", | |
2939 | connector->display_info.width_mm, | |
2940 | connector->display_info.height_mm); | |
2941 | seq_printf(m, "\tsubpixel order: %s\n", | |
2942 | drm_get_subpixel_order_name(connector->display_info.subpixel_order)); | |
2943 | seq_printf(m, "\tCEA rev: %d\n", | |
2944 | connector->display_info.cea_rev); | |
2945 | } | |
ee648a74 ML |
2946 | |
2947 | if (!intel_encoder || intel_encoder->type == INTEL_OUTPUT_DP_MST) | |
2948 | return; | |
2949 | ||
2950 | switch (connector->connector_type) { | |
2951 | case DRM_MODE_CONNECTOR_DisplayPort: | |
2952 | case DRM_MODE_CONNECTOR_eDP: | |
be754b10 | 2953 | intel_dp_info(m, intel_connector); |
ee648a74 ML |
2954 | break; |
2955 | case DRM_MODE_CONNECTOR_LVDS: | |
2956 | if (intel_encoder->type == INTEL_OUTPUT_LVDS) | |
36cd7444 | 2957 | intel_lvds_info(m, intel_connector); |
ee648a74 ML |
2958 | break; |
2959 | case DRM_MODE_CONNECTOR_HDMIA: | |
2960 | if (intel_encoder->type == INTEL_OUTPUT_HDMI || | |
2961 | intel_encoder->type == INTEL_OUTPUT_UNKNOWN) | |
2962 | intel_hdmi_info(m, intel_connector); | |
2963 | break; | |
2964 | default: | |
2965 | break; | |
36cd7444 | 2966 | } |
53f5e3ca | 2967 | |
f103fc7d JB |
2968 | seq_printf(m, "\tmodes:\n"); |
2969 | list_for_each_entry(mode, &connector->modes, head) | |
2970 | intel_seq_print_mode(m, 2, mode); | |
53f5e3ca JB |
2971 | } |
2972 | ||
36cdd013 | 2973 | static bool cursor_active(struct drm_i915_private *dev_priv, int pipe) |
065f2ec2 | 2974 | { |
065f2ec2 CW |
2975 | u32 state; |
2976 | ||
36cdd013 | 2977 | if (IS_845G(dev_priv) || IS_I865G(dev_priv)) |
0b87c24e | 2978 | state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE; |
065f2ec2 | 2979 | else |
5efb3e28 | 2980 | state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE; |
065f2ec2 CW |
2981 | |
2982 | return state; | |
2983 | } | |
2984 | ||
36cdd013 DW |
2985 | static bool cursor_position(struct drm_i915_private *dev_priv, |
2986 | int pipe, int *x, int *y) | |
065f2ec2 | 2987 | { |
065f2ec2 CW |
2988 | u32 pos; |
2989 | ||
5efb3e28 | 2990 | pos = I915_READ(CURPOS(pipe)); |
065f2ec2 CW |
2991 | |
2992 | *x = (pos >> CURSOR_X_SHIFT) & CURSOR_POS_MASK; | |
2993 | if (pos & (CURSOR_POS_SIGN << CURSOR_X_SHIFT)) | |
2994 | *x = -*x; | |
2995 | ||
2996 | *y = (pos >> CURSOR_Y_SHIFT) & CURSOR_POS_MASK; | |
2997 | if (pos & (CURSOR_POS_SIGN << CURSOR_Y_SHIFT)) | |
2998 | *y = -*y; | |
2999 | ||
36cdd013 | 3000 | return cursor_active(dev_priv, pipe); |
065f2ec2 CW |
3001 | } |
3002 | ||
3abc4e09 RF |
3003 | static const char *plane_type(enum drm_plane_type type) |
3004 | { | |
3005 | switch (type) { | |
3006 | case DRM_PLANE_TYPE_OVERLAY: | |
3007 | return "OVL"; | |
3008 | case DRM_PLANE_TYPE_PRIMARY: | |
3009 | return "PRI"; | |
3010 | case DRM_PLANE_TYPE_CURSOR: | |
3011 | return "CUR"; | |
3012 | /* | |
3013 | * Deliberately omitting default: to generate compiler warnings | |
3014 | * when a new drm_plane_type gets added. | |
3015 | */ | |
3016 | } | |
3017 | ||
3018 | return "unknown"; | |
3019 | } | |
3020 | ||
3021 | static const char *plane_rotation(unsigned int rotation) | |
3022 | { | |
3023 | static char buf[48]; | |
3024 | /* | |
3025 | * According to doc only one DRM_ROTATE_ is allowed but this | |
3026 | * will print them all to visualize if the values are misused | |
3027 | */ | |
3028 | snprintf(buf, sizeof(buf), | |
3029 | "%s%s%s%s%s%s(0x%08x)", | |
31ad61e4 JL |
3030 | (rotation & DRM_ROTATE_0) ? "0 " : "", |
3031 | (rotation & DRM_ROTATE_90) ? "90 " : "", | |
3032 | (rotation & DRM_ROTATE_180) ? "180 " : "", | |
3033 | (rotation & DRM_ROTATE_270) ? "270 " : "", | |
3034 | (rotation & DRM_REFLECT_X) ? "FLIPX " : "", | |
3035 | (rotation & DRM_REFLECT_Y) ? "FLIPY " : "", | |
3abc4e09 RF |
3036 | rotation); |
3037 | ||
3038 | return buf; | |
3039 | } | |
3040 | ||
3041 | static void intel_plane_info(struct seq_file *m, struct intel_crtc *intel_crtc) | |
3042 | { | |
36cdd013 DW |
3043 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
3044 | struct drm_device *dev = &dev_priv->drm; | |
3abc4e09 RF |
3045 | struct intel_plane *intel_plane; |
3046 | ||
3047 | for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) { | |
3048 | struct drm_plane_state *state; | |
3049 | struct drm_plane *plane = &intel_plane->base; | |
d3828147 | 3050 | char *format_name; |
3abc4e09 RF |
3051 | |
3052 | if (!plane->state) { | |
3053 | seq_puts(m, "plane->state is NULL!\n"); | |
3054 | continue; | |
3055 | } | |
3056 | ||
3057 | state = plane->state; | |
3058 | ||
90844f00 EE |
3059 | if (state->fb) { |
3060 | format_name = drm_get_format_name(state->fb->pixel_format); | |
3061 | } else { | |
3062 | format_name = kstrdup("N/A", GFP_KERNEL); | |
3063 | } | |
3064 | ||
3abc4e09 RF |
3065 | seq_printf(m, "\t--Plane id %d: type=%s, crtc_pos=%4dx%4d, crtc_size=%4dx%4d, src_pos=%d.%04ux%d.%04u, src_size=%d.%04ux%d.%04u, format=%s, rotation=%s\n", |
3066 | plane->base.id, | |
3067 | plane_type(intel_plane->base.type), | |
3068 | state->crtc_x, state->crtc_y, | |
3069 | state->crtc_w, state->crtc_h, | |
3070 | (state->src_x >> 16), | |
3071 | ((state->src_x & 0xffff) * 15625) >> 10, | |
3072 | (state->src_y >> 16), | |
3073 | ((state->src_y & 0xffff) * 15625) >> 10, | |
3074 | (state->src_w >> 16), | |
3075 | ((state->src_w & 0xffff) * 15625) >> 10, | |
3076 | (state->src_h >> 16), | |
3077 | ((state->src_h & 0xffff) * 15625) >> 10, | |
90844f00 | 3078 | format_name, |
3abc4e09 | 3079 | plane_rotation(state->rotation)); |
90844f00 EE |
3080 | |
3081 | kfree(format_name); | |
3abc4e09 RF |
3082 | } |
3083 | } | |
3084 | ||
3085 | static void intel_scaler_info(struct seq_file *m, struct intel_crtc *intel_crtc) | |
3086 | { | |
3087 | struct intel_crtc_state *pipe_config; | |
3088 | int num_scalers = intel_crtc->num_scalers; | |
3089 | int i; | |
3090 | ||
3091 | pipe_config = to_intel_crtc_state(intel_crtc->base.state); | |
3092 | ||
3093 | /* Not all platformas have a scaler */ | |
3094 | if (num_scalers) { | |
3095 | seq_printf(m, "\tnum_scalers=%d, scaler_users=%x scaler_id=%d", | |
3096 | num_scalers, | |
3097 | pipe_config->scaler_state.scaler_users, | |
3098 | pipe_config->scaler_state.scaler_id); | |
3099 | ||
3100 | for (i = 0; i < SKL_NUM_SCALERS; i++) { | |
3101 | struct intel_scaler *sc = | |
3102 | &pipe_config->scaler_state.scalers[i]; | |
3103 | ||
3104 | seq_printf(m, ", scalers[%d]: use=%s, mode=%x", | |
3105 | i, yesno(sc->in_use), sc->mode); | |
3106 | } | |
3107 | seq_puts(m, "\n"); | |
3108 | } else { | |
3109 | seq_puts(m, "\tNo scalers available on this platform\n"); | |
3110 | } | |
3111 | } | |
3112 | ||
53f5e3ca JB |
3113 | static int i915_display_info(struct seq_file *m, void *unused) |
3114 | { | |
36cdd013 DW |
3115 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
3116 | struct drm_device *dev = &dev_priv->drm; | |
065f2ec2 | 3117 | struct intel_crtc *crtc; |
53f5e3ca JB |
3118 | struct drm_connector *connector; |
3119 | ||
b0e5ddf3 | 3120 | intel_runtime_pm_get(dev_priv); |
53f5e3ca JB |
3121 | drm_modeset_lock_all(dev); |
3122 | seq_printf(m, "CRTC info\n"); | |
3123 | seq_printf(m, "---------\n"); | |
d3fcc808 | 3124 | for_each_intel_crtc(dev, crtc) { |
065f2ec2 | 3125 | bool active; |
f77076c9 | 3126 | struct intel_crtc_state *pipe_config; |
065f2ec2 | 3127 | int x, y; |
53f5e3ca | 3128 | |
f77076c9 ML |
3129 | pipe_config = to_intel_crtc_state(crtc->base.state); |
3130 | ||
3abc4e09 | 3131 | seq_printf(m, "CRTC %d: pipe: %c, active=%s, (size=%dx%d), dither=%s, bpp=%d\n", |
065f2ec2 | 3132 | crtc->base.base.id, pipe_name(crtc->pipe), |
f77076c9 | 3133 | yesno(pipe_config->base.active), |
3abc4e09 RF |
3134 | pipe_config->pipe_src_w, pipe_config->pipe_src_h, |
3135 | yesno(pipe_config->dither), pipe_config->pipe_bpp); | |
3136 | ||
f77076c9 | 3137 | if (pipe_config->base.active) { |
065f2ec2 CW |
3138 | intel_crtc_info(m, crtc); |
3139 | ||
36cdd013 | 3140 | active = cursor_position(dev_priv, crtc->pipe, &x, &y); |
57127efa | 3141 | seq_printf(m, "\tcursor visible? %s, position (%d, %d), size %dx%d, addr 0x%08x, active? %s\n", |
4b0e333e | 3142 | yesno(crtc->cursor_base), |
3dd512fb MR |
3143 | x, y, crtc->base.cursor->state->crtc_w, |
3144 | crtc->base.cursor->state->crtc_h, | |
57127efa | 3145 | crtc->cursor_addr, yesno(active)); |
3abc4e09 RF |
3146 | intel_scaler_info(m, crtc); |
3147 | intel_plane_info(m, crtc); | |
a23dc658 | 3148 | } |
cace841c DV |
3149 | |
3150 | seq_printf(m, "\tunderrun reporting: cpu=%s pch=%s \n", | |
3151 | yesno(!crtc->cpu_fifo_underrun_disabled), | |
3152 | yesno(!crtc->pch_fifo_underrun_disabled)); | |
53f5e3ca JB |
3153 | } |
3154 | ||
3155 | seq_printf(m, "\n"); | |
3156 | seq_printf(m, "Connector info\n"); | |
3157 | seq_printf(m, "--------------\n"); | |
3158 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
3159 | intel_connector_info(m, connector); | |
3160 | } | |
3161 | drm_modeset_unlock_all(dev); | |
b0e5ddf3 | 3162 | intel_runtime_pm_put(dev_priv); |
53f5e3ca JB |
3163 | |
3164 | return 0; | |
3165 | } | |
3166 | ||
1b36595f CW |
3167 | static int i915_engine_info(struct seq_file *m, void *unused) |
3168 | { | |
3169 | struct drm_i915_private *dev_priv = node_to_i915(m->private); | |
3170 | struct intel_engine_cs *engine; | |
3b3f1650 | 3171 | enum intel_engine_id id; |
1b36595f | 3172 | |
9c870d03 CW |
3173 | intel_runtime_pm_get(dev_priv); |
3174 | ||
3b3f1650 | 3175 | for_each_engine(engine, dev_priv, id) { |
1b36595f CW |
3176 | struct intel_breadcrumbs *b = &engine->breadcrumbs; |
3177 | struct drm_i915_gem_request *rq; | |
3178 | struct rb_node *rb; | |
3179 | u64 addr; | |
3180 | ||
3181 | seq_printf(m, "%s\n", engine->name); | |
3182 | seq_printf(m, "\tcurrent seqno %x, last %x, hangcheck %x [score %d]\n", | |
3183 | intel_engine_get_seqno(engine), | |
3184 | engine->last_submitted_seqno, | |
3185 | engine->hangcheck.seqno, | |
3186 | engine->hangcheck.score); | |
3187 | ||
3188 | rcu_read_lock(); | |
3189 | ||
3190 | seq_printf(m, "\tRequests:\n"); | |
3191 | ||
3192 | rq = list_first_entry(&engine->request_list, | |
3193 | struct drm_i915_gem_request, link); | |
3194 | if (&rq->link != &engine->request_list) | |
3195 | print_request(m, rq, "\t\tfirst "); | |
3196 | ||
3197 | rq = list_last_entry(&engine->request_list, | |
3198 | struct drm_i915_gem_request, link); | |
3199 | if (&rq->link != &engine->request_list) | |
3200 | print_request(m, rq, "\t\tlast "); | |
3201 | ||
3202 | rq = i915_gem_find_active_request(engine); | |
3203 | if (rq) { | |
3204 | print_request(m, rq, "\t\tactive "); | |
3205 | seq_printf(m, | |
3206 | "\t\t[head %04x, postfix %04x, tail %04x, batch 0x%08x_%08x]\n", | |
3207 | rq->head, rq->postfix, rq->tail, | |
3208 | rq->batch ? upper_32_bits(rq->batch->node.start) : ~0u, | |
3209 | rq->batch ? lower_32_bits(rq->batch->node.start) : ~0u); | |
3210 | } | |
3211 | ||
3212 | seq_printf(m, "\tRING_START: 0x%08x [0x%08x]\n", | |
3213 | I915_READ(RING_START(engine->mmio_base)), | |
3214 | rq ? i915_ggtt_offset(rq->ring->vma) : 0); | |
3215 | seq_printf(m, "\tRING_HEAD: 0x%08x [0x%08x]\n", | |
3216 | I915_READ(RING_HEAD(engine->mmio_base)) & HEAD_ADDR, | |
3217 | rq ? rq->ring->head : 0); | |
3218 | seq_printf(m, "\tRING_TAIL: 0x%08x [0x%08x]\n", | |
3219 | I915_READ(RING_TAIL(engine->mmio_base)) & TAIL_ADDR, | |
3220 | rq ? rq->ring->tail : 0); | |
3221 | seq_printf(m, "\tRING_CTL: 0x%08x [%s]\n", | |
3222 | I915_READ(RING_CTL(engine->mmio_base)), | |
3223 | I915_READ(RING_CTL(engine->mmio_base)) & (RING_WAIT | RING_WAIT_SEMAPHORE) ? "waiting" : ""); | |
3224 | ||
3225 | rcu_read_unlock(); | |
3226 | ||
3227 | addr = intel_engine_get_active_head(engine); | |
3228 | seq_printf(m, "\tACTHD: 0x%08x_%08x\n", | |
3229 | upper_32_bits(addr), lower_32_bits(addr)); | |
3230 | addr = intel_engine_get_last_batch_head(engine); | |
3231 | seq_printf(m, "\tBBADDR: 0x%08x_%08x\n", | |
3232 | upper_32_bits(addr), lower_32_bits(addr)); | |
3233 | ||
3234 | if (i915.enable_execlists) { | |
3235 | u32 ptr, read, write; | |
3236 | ||
3237 | seq_printf(m, "\tExeclist status: 0x%08x %08x\n", | |
3238 | I915_READ(RING_EXECLIST_STATUS_LO(engine)), | |
3239 | I915_READ(RING_EXECLIST_STATUS_HI(engine))); | |
3240 | ||
3241 | ptr = I915_READ(RING_CONTEXT_STATUS_PTR(engine)); | |
3242 | read = GEN8_CSB_READ_PTR(ptr); | |
3243 | write = GEN8_CSB_WRITE_PTR(ptr); | |
3244 | seq_printf(m, "\tExeclist CSB read %d, write %d\n", | |
3245 | read, write); | |
3246 | if (read >= GEN8_CSB_ENTRIES) | |
3247 | read = 0; | |
3248 | if (write >= GEN8_CSB_ENTRIES) | |
3249 | write = 0; | |
3250 | if (read > write) | |
3251 | write += GEN8_CSB_ENTRIES; | |
3252 | while (read < write) { | |
3253 | unsigned int idx = ++read % GEN8_CSB_ENTRIES; | |
3254 | ||
3255 | seq_printf(m, "\tExeclist CSB[%d]: 0x%08x, context: %d\n", | |
3256 | idx, | |
3257 | I915_READ(RING_CONTEXT_STATUS_BUF_LO(engine, idx)), | |
3258 | I915_READ(RING_CONTEXT_STATUS_BUF_HI(engine, idx))); | |
3259 | } | |
3260 | ||
3261 | rcu_read_lock(); | |
3262 | rq = READ_ONCE(engine->execlist_port[0].request); | |
3263 | if (rq) | |
3264 | print_request(m, rq, "\t\tELSP[0] "); | |
3265 | else | |
3266 | seq_printf(m, "\t\tELSP[0] idle\n"); | |
3267 | rq = READ_ONCE(engine->execlist_port[1].request); | |
3268 | if (rq) | |
3269 | print_request(m, rq, "\t\tELSP[1] "); | |
3270 | else | |
3271 | seq_printf(m, "\t\tELSP[1] idle\n"); | |
3272 | rcu_read_unlock(); | |
3273 | } else if (INTEL_GEN(dev_priv) > 6) { | |
3274 | seq_printf(m, "\tPP_DIR_BASE: 0x%08x\n", | |
3275 | I915_READ(RING_PP_DIR_BASE(engine))); | |
3276 | seq_printf(m, "\tPP_DIR_BASE_READ: 0x%08x\n", | |
3277 | I915_READ(RING_PP_DIR_BASE_READ(engine))); | |
3278 | seq_printf(m, "\tPP_DIR_DCLV: 0x%08x\n", | |
3279 | I915_READ(RING_PP_DIR_DCLV(engine))); | |
3280 | } | |
3281 | ||
3282 | spin_lock(&b->lock); | |
3283 | for (rb = rb_first(&b->waiters); rb; rb = rb_next(rb)) { | |
3284 | struct intel_wait *w = container_of(rb, typeof(*w), node); | |
3285 | ||
3286 | seq_printf(m, "\t%s [%d] waiting for %x\n", | |
3287 | w->tsk->comm, w->tsk->pid, w->seqno); | |
3288 | } | |
3289 | spin_unlock(&b->lock); | |
3290 | ||
3291 | seq_puts(m, "\n"); | |
3292 | } | |
3293 | ||
9c870d03 CW |
3294 | intel_runtime_pm_put(dev_priv); |
3295 | ||
1b36595f CW |
3296 | return 0; |
3297 | } | |
3298 | ||
e04934cf BW |
3299 | static int i915_semaphore_status(struct seq_file *m, void *unused) |
3300 | { | |
36cdd013 DW |
3301 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
3302 | struct drm_device *dev = &dev_priv->drm; | |
e2f80391 | 3303 | struct intel_engine_cs *engine; |
36cdd013 | 3304 | int num_rings = INTEL_INFO(dev_priv)->num_rings; |
c3232b18 DG |
3305 | enum intel_engine_id id; |
3306 | int j, ret; | |
e04934cf | 3307 | |
39df9190 | 3308 | if (!i915.semaphores) { |
e04934cf BW |
3309 | seq_puts(m, "Semaphores are disabled\n"); |
3310 | return 0; | |
3311 | } | |
3312 | ||
3313 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
3314 | if (ret) | |
3315 | return ret; | |
03872064 | 3316 | intel_runtime_pm_get(dev_priv); |
e04934cf | 3317 | |
36cdd013 | 3318 | if (IS_BROADWELL(dev_priv)) { |
e04934cf BW |
3319 | struct page *page; |
3320 | uint64_t *seqno; | |
3321 | ||
51d545d0 | 3322 | page = i915_gem_object_get_page(dev_priv->semaphore->obj, 0); |
e04934cf BW |
3323 | |
3324 | seqno = (uint64_t *)kmap_atomic(page); | |
3b3f1650 | 3325 | for_each_engine(engine, dev_priv, id) { |
e04934cf BW |
3326 | uint64_t offset; |
3327 | ||
e2f80391 | 3328 | seq_printf(m, "%s\n", engine->name); |
e04934cf BW |
3329 | |
3330 | seq_puts(m, " Last signal:"); | |
3331 | for (j = 0; j < num_rings; j++) { | |
c3232b18 | 3332 | offset = id * I915_NUM_ENGINES + j; |
e04934cf BW |
3333 | seq_printf(m, "0x%08llx (0x%02llx) ", |
3334 | seqno[offset], offset * 8); | |
3335 | } | |
3336 | seq_putc(m, '\n'); | |
3337 | ||
3338 | seq_puts(m, " Last wait: "); | |
3339 | for (j = 0; j < num_rings; j++) { | |
c3232b18 | 3340 | offset = id + (j * I915_NUM_ENGINES); |
e04934cf BW |
3341 | seq_printf(m, "0x%08llx (0x%02llx) ", |
3342 | seqno[offset], offset * 8); | |
3343 | } | |
3344 | seq_putc(m, '\n'); | |
3345 | ||
3346 | } | |
3347 | kunmap_atomic(seqno); | |
3348 | } else { | |
3349 | seq_puts(m, " Last signal:"); | |
3b3f1650 | 3350 | for_each_engine(engine, dev_priv, id) |
e04934cf BW |
3351 | for (j = 0; j < num_rings; j++) |
3352 | seq_printf(m, "0x%08x\n", | |
e2f80391 | 3353 | I915_READ(engine->semaphore.mbox.signal[j])); |
e04934cf BW |
3354 | seq_putc(m, '\n'); |
3355 | } | |
3356 | ||
3357 | seq_puts(m, "\nSync seqno:\n"); | |
3b3f1650 | 3358 | for_each_engine(engine, dev_priv, id) { |
b4ac5afc | 3359 | for (j = 0; j < num_rings; j++) |
e2f80391 TU |
3360 | seq_printf(m, " 0x%08x ", |
3361 | engine->semaphore.sync_seqno[j]); | |
e04934cf BW |
3362 | seq_putc(m, '\n'); |
3363 | } | |
3364 | seq_putc(m, '\n'); | |
3365 | ||
03872064 | 3366 | intel_runtime_pm_put(dev_priv); |
e04934cf BW |
3367 | mutex_unlock(&dev->struct_mutex); |
3368 | return 0; | |
3369 | } | |
3370 | ||
728e29d7 DV |
3371 | static int i915_shared_dplls_info(struct seq_file *m, void *unused) |
3372 | { | |
36cdd013 DW |
3373 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
3374 | struct drm_device *dev = &dev_priv->drm; | |
728e29d7 DV |
3375 | int i; |
3376 | ||
3377 | drm_modeset_lock_all(dev); | |
3378 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { | |
3379 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; | |
3380 | ||
3381 | seq_printf(m, "DPLL%i: %s, id: %i\n", i, pll->name, pll->id); | |
2dd66ebd ML |
3382 | seq_printf(m, " crtc_mask: 0x%08x, active: 0x%x, on: %s\n", |
3383 | pll->config.crtc_mask, pll->active_mask, yesno(pll->on)); | |
728e29d7 | 3384 | seq_printf(m, " tracked hardware state:\n"); |
3e369b76 ACO |
3385 | seq_printf(m, " dpll: 0x%08x\n", pll->config.hw_state.dpll); |
3386 | seq_printf(m, " dpll_md: 0x%08x\n", | |
3387 | pll->config.hw_state.dpll_md); | |
3388 | seq_printf(m, " fp0: 0x%08x\n", pll->config.hw_state.fp0); | |
3389 | seq_printf(m, " fp1: 0x%08x\n", pll->config.hw_state.fp1); | |
3390 | seq_printf(m, " wrpll: 0x%08x\n", pll->config.hw_state.wrpll); | |
728e29d7 DV |
3391 | } |
3392 | drm_modeset_unlock_all(dev); | |
3393 | ||
3394 | return 0; | |
3395 | } | |
3396 | ||
1ed1ef9d | 3397 | static int i915_wa_registers(struct seq_file *m, void *unused) |
888b5995 AS |
3398 | { |
3399 | int i; | |
3400 | int ret; | |
e2f80391 | 3401 | struct intel_engine_cs *engine; |
36cdd013 DW |
3402 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
3403 | struct drm_device *dev = &dev_priv->drm; | |
33136b06 | 3404 | struct i915_workarounds *workarounds = &dev_priv->workarounds; |
c3232b18 | 3405 | enum intel_engine_id id; |
888b5995 | 3406 | |
888b5995 AS |
3407 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
3408 | if (ret) | |
3409 | return ret; | |
3410 | ||
3411 | intel_runtime_pm_get(dev_priv); | |
3412 | ||
33136b06 | 3413 | seq_printf(m, "Workarounds applied: %d\n", workarounds->count); |
3b3f1650 | 3414 | for_each_engine(engine, dev_priv, id) |
33136b06 | 3415 | seq_printf(m, "HW whitelist count for %s: %d\n", |
c3232b18 | 3416 | engine->name, workarounds->hw_whitelist_count[id]); |
33136b06 | 3417 | for (i = 0; i < workarounds->count; ++i) { |
f0f59a00 VS |
3418 | i915_reg_t addr; |
3419 | u32 mask, value, read; | |
2fa60f6d | 3420 | bool ok; |
888b5995 | 3421 | |
33136b06 AS |
3422 | addr = workarounds->reg[i].addr; |
3423 | mask = workarounds->reg[i].mask; | |
3424 | value = workarounds->reg[i].value; | |
2fa60f6d MK |
3425 | read = I915_READ(addr); |
3426 | ok = (value & mask) == (read & mask); | |
3427 | seq_printf(m, "0x%X: 0x%08X, mask: 0x%08X, read: 0x%08x, status: %s\n", | |
f0f59a00 | 3428 | i915_mmio_reg_offset(addr), value, mask, read, ok ? "OK" : "FAIL"); |
888b5995 AS |
3429 | } |
3430 | ||
3431 | intel_runtime_pm_put(dev_priv); | |
3432 | mutex_unlock(&dev->struct_mutex); | |
3433 | ||
3434 | return 0; | |
3435 | } | |
3436 | ||
c5511e44 DL |
3437 | static int i915_ddb_info(struct seq_file *m, void *unused) |
3438 | { | |
36cdd013 DW |
3439 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
3440 | struct drm_device *dev = &dev_priv->drm; | |
c5511e44 DL |
3441 | struct skl_ddb_allocation *ddb; |
3442 | struct skl_ddb_entry *entry; | |
3443 | enum pipe pipe; | |
3444 | int plane; | |
3445 | ||
36cdd013 | 3446 | if (INTEL_GEN(dev_priv) < 9) |
2fcffe19 DL |
3447 | return 0; |
3448 | ||
c5511e44 DL |
3449 | drm_modeset_lock_all(dev); |
3450 | ||
3451 | ddb = &dev_priv->wm.skl_hw.ddb; | |
3452 | ||
3453 | seq_printf(m, "%-15s%8s%8s%8s\n", "", "Start", "End", "Size"); | |
3454 | ||
3455 | for_each_pipe(dev_priv, pipe) { | |
3456 | seq_printf(m, "Pipe %c\n", pipe_name(pipe)); | |
3457 | ||
8b364b41 | 3458 | for_each_universal_plane(dev_priv, pipe, plane) { |
c5511e44 DL |
3459 | entry = &ddb->plane[pipe][plane]; |
3460 | seq_printf(m, " Plane%-8d%8u%8u%8u\n", plane + 1, | |
3461 | entry->start, entry->end, | |
3462 | skl_ddb_entry_size(entry)); | |
3463 | } | |
3464 | ||
4969d33e | 3465 | entry = &ddb->plane[pipe][PLANE_CURSOR]; |
c5511e44 DL |
3466 | seq_printf(m, " %-13s%8u%8u%8u\n", "Cursor", entry->start, |
3467 | entry->end, skl_ddb_entry_size(entry)); | |
3468 | } | |
3469 | ||
3470 | drm_modeset_unlock_all(dev); | |
3471 | ||
3472 | return 0; | |
3473 | } | |
3474 | ||
a54746e3 | 3475 | static void drrs_status_per_crtc(struct seq_file *m, |
36cdd013 DW |
3476 | struct drm_device *dev, |
3477 | struct intel_crtc *intel_crtc) | |
a54746e3 | 3478 | { |
fac5e23e | 3479 | struct drm_i915_private *dev_priv = to_i915(dev); |
a54746e3 VK |
3480 | struct i915_drrs *drrs = &dev_priv->drrs; |
3481 | int vrefresh = 0; | |
26875fe5 | 3482 | struct drm_connector *connector; |
a54746e3 | 3483 | |
26875fe5 ML |
3484 | drm_for_each_connector(connector, dev) { |
3485 | if (connector->state->crtc != &intel_crtc->base) | |
3486 | continue; | |
3487 | ||
3488 | seq_printf(m, "%s:\n", connector->name); | |
a54746e3 VK |
3489 | } |
3490 | ||
3491 | if (dev_priv->vbt.drrs_type == STATIC_DRRS_SUPPORT) | |
3492 | seq_puts(m, "\tVBT: DRRS_type: Static"); | |
3493 | else if (dev_priv->vbt.drrs_type == SEAMLESS_DRRS_SUPPORT) | |
3494 | seq_puts(m, "\tVBT: DRRS_type: Seamless"); | |
3495 | else if (dev_priv->vbt.drrs_type == DRRS_NOT_SUPPORTED) | |
3496 | seq_puts(m, "\tVBT: DRRS_type: None"); | |
3497 | else | |
3498 | seq_puts(m, "\tVBT: DRRS_type: FIXME: Unrecognized Value"); | |
3499 | ||
3500 | seq_puts(m, "\n\n"); | |
3501 | ||
f77076c9 | 3502 | if (to_intel_crtc_state(intel_crtc->base.state)->has_drrs) { |
a54746e3 VK |
3503 | struct intel_panel *panel; |
3504 | ||
3505 | mutex_lock(&drrs->mutex); | |
3506 | /* DRRS Supported */ | |
3507 | seq_puts(m, "\tDRRS Supported: Yes\n"); | |
3508 | ||
3509 | /* disable_drrs() will make drrs->dp NULL */ | |
3510 | if (!drrs->dp) { | |
3511 | seq_puts(m, "Idleness DRRS: Disabled"); | |
3512 | mutex_unlock(&drrs->mutex); | |
3513 | return; | |
3514 | } | |
3515 | ||
3516 | panel = &drrs->dp->attached_connector->panel; | |
3517 | seq_printf(m, "\t\tBusy_frontbuffer_bits: 0x%X", | |
3518 | drrs->busy_frontbuffer_bits); | |
3519 | ||
3520 | seq_puts(m, "\n\t\t"); | |
3521 | if (drrs->refresh_rate_type == DRRS_HIGH_RR) { | |
3522 | seq_puts(m, "DRRS_State: DRRS_HIGH_RR\n"); | |
3523 | vrefresh = panel->fixed_mode->vrefresh; | |
3524 | } else if (drrs->refresh_rate_type == DRRS_LOW_RR) { | |
3525 | seq_puts(m, "DRRS_State: DRRS_LOW_RR\n"); | |
3526 | vrefresh = panel->downclock_mode->vrefresh; | |
3527 | } else { | |
3528 | seq_printf(m, "DRRS_State: Unknown(%d)\n", | |
3529 | drrs->refresh_rate_type); | |
3530 | mutex_unlock(&drrs->mutex); | |
3531 | return; | |
3532 | } | |
3533 | seq_printf(m, "\t\tVrefresh: %d", vrefresh); | |
3534 | ||
3535 | seq_puts(m, "\n\t\t"); | |
3536 | mutex_unlock(&drrs->mutex); | |
3537 | } else { | |
3538 | /* DRRS not supported. Print the VBT parameter*/ | |
3539 | seq_puts(m, "\tDRRS Supported : No"); | |
3540 | } | |
3541 | seq_puts(m, "\n"); | |
3542 | } | |
3543 | ||
3544 | static int i915_drrs_status(struct seq_file *m, void *unused) | |
3545 | { | |
36cdd013 DW |
3546 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
3547 | struct drm_device *dev = &dev_priv->drm; | |
a54746e3 VK |
3548 | struct intel_crtc *intel_crtc; |
3549 | int active_crtc_cnt = 0; | |
3550 | ||
26875fe5 | 3551 | drm_modeset_lock_all(dev); |
a54746e3 | 3552 | for_each_intel_crtc(dev, intel_crtc) { |
f77076c9 | 3553 | if (intel_crtc->base.state->active) { |
a54746e3 VK |
3554 | active_crtc_cnt++; |
3555 | seq_printf(m, "\nCRTC %d: ", active_crtc_cnt); | |
3556 | ||
3557 | drrs_status_per_crtc(m, dev, intel_crtc); | |
3558 | } | |
a54746e3 | 3559 | } |
26875fe5 | 3560 | drm_modeset_unlock_all(dev); |
a54746e3 VK |
3561 | |
3562 | if (!active_crtc_cnt) | |
3563 | seq_puts(m, "No active crtc found\n"); | |
3564 | ||
3565 | return 0; | |
3566 | } | |
3567 | ||
07144428 DL |
3568 | struct pipe_crc_info { |
3569 | const char *name; | |
36cdd013 | 3570 | struct drm_i915_private *dev_priv; |
07144428 DL |
3571 | enum pipe pipe; |
3572 | }; | |
3573 | ||
11bed958 DA |
3574 | static int i915_dp_mst_info(struct seq_file *m, void *unused) |
3575 | { | |
36cdd013 DW |
3576 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
3577 | struct drm_device *dev = &dev_priv->drm; | |
11bed958 DA |
3578 | struct intel_encoder *intel_encoder; |
3579 | struct intel_digital_port *intel_dig_port; | |
b6dabe3b ML |
3580 | struct drm_connector *connector; |
3581 | ||
11bed958 | 3582 | drm_modeset_lock_all(dev); |
b6dabe3b ML |
3583 | drm_for_each_connector(connector, dev) { |
3584 | if (connector->connector_type != DRM_MODE_CONNECTOR_DisplayPort) | |
11bed958 | 3585 | continue; |
b6dabe3b ML |
3586 | |
3587 | intel_encoder = intel_attached_encoder(connector); | |
3588 | if (!intel_encoder || intel_encoder->type == INTEL_OUTPUT_DP_MST) | |
3589 | continue; | |
3590 | ||
3591 | intel_dig_port = enc_to_dig_port(&intel_encoder->base); | |
11bed958 DA |
3592 | if (!intel_dig_port->dp.can_mst) |
3593 | continue; | |
b6dabe3b | 3594 | |
40ae80cc JB |
3595 | seq_printf(m, "MST Source Port %c\n", |
3596 | port_name(intel_dig_port->port)); | |
11bed958 DA |
3597 | drm_dp_mst_dump_topology(m, &intel_dig_port->dp.mst_mgr); |
3598 | } | |
3599 | drm_modeset_unlock_all(dev); | |
3600 | return 0; | |
3601 | } | |
3602 | ||
07144428 DL |
3603 | static int i915_pipe_crc_open(struct inode *inode, struct file *filep) |
3604 | { | |
be5c7a90 | 3605 | struct pipe_crc_info *info = inode->i_private; |
36cdd013 | 3606 | struct drm_i915_private *dev_priv = info->dev_priv; |
be5c7a90 DL |
3607 | struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe]; |
3608 | ||
36cdd013 | 3609 | if (info->pipe >= INTEL_INFO(dev_priv)->num_pipes) |
7eb1c496 DV |
3610 | return -ENODEV; |
3611 | ||
d538bbdf DL |
3612 | spin_lock_irq(&pipe_crc->lock); |
3613 | ||
3614 | if (pipe_crc->opened) { | |
3615 | spin_unlock_irq(&pipe_crc->lock); | |
be5c7a90 DL |
3616 | return -EBUSY; /* already open */ |
3617 | } | |
3618 | ||
d538bbdf | 3619 | pipe_crc->opened = true; |
07144428 DL |
3620 | filep->private_data = inode->i_private; |
3621 | ||
d538bbdf DL |
3622 | spin_unlock_irq(&pipe_crc->lock); |
3623 | ||
07144428 DL |
3624 | return 0; |
3625 | } | |
3626 | ||
3627 | static int i915_pipe_crc_release(struct inode *inode, struct file *filep) | |
3628 | { | |
be5c7a90 | 3629 | struct pipe_crc_info *info = inode->i_private; |
36cdd013 | 3630 | struct drm_i915_private *dev_priv = info->dev_priv; |
be5c7a90 DL |
3631 | struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe]; |
3632 | ||
d538bbdf DL |
3633 | spin_lock_irq(&pipe_crc->lock); |
3634 | pipe_crc->opened = false; | |
3635 | spin_unlock_irq(&pipe_crc->lock); | |
be5c7a90 | 3636 | |
07144428 DL |
3637 | return 0; |
3638 | } | |
3639 | ||
3640 | /* (6 fields, 8 chars each, space separated (5) + '\n') */ | |
3641 | #define PIPE_CRC_LINE_LEN (6 * 8 + 5 + 1) | |
3642 | /* account for \'0' */ | |
3643 | #define PIPE_CRC_BUFFER_LEN (PIPE_CRC_LINE_LEN + 1) | |
3644 | ||
3645 | static int pipe_crc_data_count(struct intel_pipe_crc *pipe_crc) | |
8bf1e9f1 | 3646 | { |
d538bbdf DL |
3647 | assert_spin_locked(&pipe_crc->lock); |
3648 | return CIRC_CNT(pipe_crc->head, pipe_crc->tail, | |
3649 | INTEL_PIPE_CRC_ENTRIES_NR); | |
07144428 DL |
3650 | } |
3651 | ||
3652 | static ssize_t | |
3653 | i915_pipe_crc_read(struct file *filep, char __user *user_buf, size_t count, | |
3654 | loff_t *pos) | |
3655 | { | |
3656 | struct pipe_crc_info *info = filep->private_data; | |
36cdd013 | 3657 | struct drm_i915_private *dev_priv = info->dev_priv; |
07144428 DL |
3658 | struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe]; |
3659 | char buf[PIPE_CRC_BUFFER_LEN]; | |
9ad6d99f | 3660 | int n_entries; |
07144428 DL |
3661 | ssize_t bytes_read; |
3662 | ||
3663 | /* | |
3664 | * Don't allow user space to provide buffers not big enough to hold | |
3665 | * a line of data. | |
3666 | */ | |
3667 | if (count < PIPE_CRC_LINE_LEN) | |
3668 | return -EINVAL; | |
3669 | ||
3670 | if (pipe_crc->source == INTEL_PIPE_CRC_SOURCE_NONE) | |
8bf1e9f1 | 3671 | return 0; |
07144428 DL |
3672 | |
3673 | /* nothing to read */ | |
d538bbdf | 3674 | spin_lock_irq(&pipe_crc->lock); |
07144428 | 3675 | while (pipe_crc_data_count(pipe_crc) == 0) { |
d538bbdf DL |
3676 | int ret; |
3677 | ||
3678 | if (filep->f_flags & O_NONBLOCK) { | |
3679 | spin_unlock_irq(&pipe_crc->lock); | |
07144428 | 3680 | return -EAGAIN; |
d538bbdf | 3681 | } |
07144428 | 3682 | |
d538bbdf DL |
3683 | ret = wait_event_interruptible_lock_irq(pipe_crc->wq, |
3684 | pipe_crc_data_count(pipe_crc), pipe_crc->lock); | |
3685 | if (ret) { | |
3686 | spin_unlock_irq(&pipe_crc->lock); | |
3687 | return ret; | |
3688 | } | |
8bf1e9f1 SH |
3689 | } |
3690 | ||
07144428 | 3691 | /* We now have one or more entries to read */ |
9ad6d99f | 3692 | n_entries = count / PIPE_CRC_LINE_LEN; |
d538bbdf | 3693 | |
07144428 | 3694 | bytes_read = 0; |
9ad6d99f VS |
3695 | while (n_entries > 0) { |
3696 | struct intel_pipe_crc_entry *entry = | |
3697 | &pipe_crc->entries[pipe_crc->tail]; | |
8bf1e9f1 | 3698 | |
9ad6d99f VS |
3699 | if (CIRC_CNT(pipe_crc->head, pipe_crc->tail, |
3700 | INTEL_PIPE_CRC_ENTRIES_NR) < 1) | |
3701 | break; | |
3702 | ||
3703 | BUILD_BUG_ON_NOT_POWER_OF_2(INTEL_PIPE_CRC_ENTRIES_NR); | |
3704 | pipe_crc->tail = (pipe_crc->tail + 1) & (INTEL_PIPE_CRC_ENTRIES_NR - 1); | |
3705 | ||
07144428 DL |
3706 | bytes_read += snprintf(buf, PIPE_CRC_BUFFER_LEN, |
3707 | "%8u %8x %8x %8x %8x %8x\n", | |
3708 | entry->frame, entry->crc[0], | |
3709 | entry->crc[1], entry->crc[2], | |
3710 | entry->crc[3], entry->crc[4]); | |
3711 | ||
9ad6d99f VS |
3712 | spin_unlock_irq(&pipe_crc->lock); |
3713 | ||
4e9121e6 | 3714 | if (copy_to_user(user_buf, buf, PIPE_CRC_LINE_LEN)) |
07144428 | 3715 | return -EFAULT; |
b2c88f5b | 3716 | |
9ad6d99f VS |
3717 | user_buf += PIPE_CRC_LINE_LEN; |
3718 | n_entries--; | |
3719 | ||
3720 | spin_lock_irq(&pipe_crc->lock); | |
3721 | } | |
8bf1e9f1 | 3722 | |
d538bbdf DL |
3723 | spin_unlock_irq(&pipe_crc->lock); |
3724 | ||
07144428 DL |
3725 | return bytes_read; |
3726 | } | |
3727 | ||
3728 | static const struct file_operations i915_pipe_crc_fops = { | |
3729 | .owner = THIS_MODULE, | |
3730 | .open = i915_pipe_crc_open, | |
3731 | .read = i915_pipe_crc_read, | |
3732 | .release = i915_pipe_crc_release, | |
3733 | }; | |
3734 | ||
3735 | static struct pipe_crc_info i915_pipe_crc_data[I915_MAX_PIPES] = { | |
3736 | { | |
3737 | .name = "i915_pipe_A_crc", | |
3738 | .pipe = PIPE_A, | |
3739 | }, | |
3740 | { | |
3741 | .name = "i915_pipe_B_crc", | |
3742 | .pipe = PIPE_B, | |
3743 | }, | |
3744 | { | |
3745 | .name = "i915_pipe_C_crc", | |
3746 | .pipe = PIPE_C, | |
3747 | }, | |
3748 | }; | |
3749 | ||
3750 | static int i915_pipe_crc_create(struct dentry *root, struct drm_minor *minor, | |
3751 | enum pipe pipe) | |
3752 | { | |
36cdd013 | 3753 | struct drm_i915_private *dev_priv = to_i915(minor->dev); |
07144428 DL |
3754 | struct dentry *ent; |
3755 | struct pipe_crc_info *info = &i915_pipe_crc_data[pipe]; | |
3756 | ||
36cdd013 | 3757 | info->dev_priv = dev_priv; |
07144428 DL |
3758 | ent = debugfs_create_file(info->name, S_IRUGO, root, info, |
3759 | &i915_pipe_crc_fops); | |
f3c5fe97 WY |
3760 | if (!ent) |
3761 | return -ENOMEM; | |
07144428 DL |
3762 | |
3763 | return drm_add_fake_info_node(minor, ent, info); | |
8bf1e9f1 SH |
3764 | } |
3765 | ||
e8dfcf78 | 3766 | static const char * const pipe_crc_sources[] = { |
926321d5 DV |
3767 | "none", |
3768 | "plane1", | |
3769 | "plane2", | |
3770 | "pf", | |
5b3a856b | 3771 | "pipe", |
3d099a05 DV |
3772 | "TV", |
3773 | "DP-B", | |
3774 | "DP-C", | |
3775 | "DP-D", | |
46a19188 | 3776 | "auto", |
926321d5 DV |
3777 | }; |
3778 | ||
3779 | static const char *pipe_crc_source_name(enum intel_pipe_crc_source source) | |
3780 | { | |
3781 | BUILD_BUG_ON(ARRAY_SIZE(pipe_crc_sources) != INTEL_PIPE_CRC_SOURCE_MAX); | |
3782 | return pipe_crc_sources[source]; | |
3783 | } | |
3784 | ||
bd9db02f | 3785 | static int display_crc_ctl_show(struct seq_file *m, void *data) |
926321d5 | 3786 | { |
36cdd013 | 3787 | struct drm_i915_private *dev_priv = m->private; |
926321d5 DV |
3788 | int i; |
3789 | ||
3790 | for (i = 0; i < I915_MAX_PIPES; i++) | |
3791 | seq_printf(m, "%c %s\n", pipe_name(i), | |
3792 | pipe_crc_source_name(dev_priv->pipe_crc[i].source)); | |
3793 | ||
3794 | return 0; | |
3795 | } | |
3796 | ||
bd9db02f | 3797 | static int display_crc_ctl_open(struct inode *inode, struct file *file) |
926321d5 | 3798 | { |
36cdd013 | 3799 | return single_open(file, display_crc_ctl_show, inode->i_private); |
926321d5 DV |
3800 | } |
3801 | ||
46a19188 | 3802 | static int i8xx_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source, |
52f843f6 DV |
3803 | uint32_t *val) |
3804 | { | |
46a19188 DV |
3805 | if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) |
3806 | *source = INTEL_PIPE_CRC_SOURCE_PIPE; | |
3807 | ||
3808 | switch (*source) { | |
52f843f6 DV |
3809 | case INTEL_PIPE_CRC_SOURCE_PIPE: |
3810 | *val = PIPE_CRC_ENABLE | PIPE_CRC_INCLUDE_BORDER_I8XX; | |
3811 | break; | |
3812 | case INTEL_PIPE_CRC_SOURCE_NONE: | |
3813 | *val = 0; | |
3814 | break; | |
3815 | default: | |
3816 | return -EINVAL; | |
3817 | } | |
3818 | ||
3819 | return 0; | |
3820 | } | |
3821 | ||
36cdd013 DW |
3822 | static int i9xx_pipe_crc_auto_source(struct drm_i915_private *dev_priv, |
3823 | enum pipe pipe, | |
46a19188 DV |
3824 | enum intel_pipe_crc_source *source) |
3825 | { | |
36cdd013 | 3826 | struct drm_device *dev = &dev_priv->drm; |
46a19188 DV |
3827 | struct intel_encoder *encoder; |
3828 | struct intel_crtc *crtc; | |
26756809 | 3829 | struct intel_digital_port *dig_port; |
46a19188 DV |
3830 | int ret = 0; |
3831 | ||
3832 | *source = INTEL_PIPE_CRC_SOURCE_PIPE; | |
3833 | ||
6e9f798d | 3834 | drm_modeset_lock_all(dev); |
b2784e15 | 3835 | for_each_intel_encoder(dev, encoder) { |
46a19188 DV |
3836 | if (!encoder->base.crtc) |
3837 | continue; | |
3838 | ||
3839 | crtc = to_intel_crtc(encoder->base.crtc); | |
3840 | ||
3841 | if (crtc->pipe != pipe) | |
3842 | continue; | |
3843 | ||
3844 | switch (encoder->type) { | |
3845 | case INTEL_OUTPUT_TVOUT: | |
3846 | *source = INTEL_PIPE_CRC_SOURCE_TV; | |
3847 | break; | |
cca0502b | 3848 | case INTEL_OUTPUT_DP: |
46a19188 | 3849 | case INTEL_OUTPUT_EDP: |
26756809 DV |
3850 | dig_port = enc_to_dig_port(&encoder->base); |
3851 | switch (dig_port->port) { | |
3852 | case PORT_B: | |
3853 | *source = INTEL_PIPE_CRC_SOURCE_DP_B; | |
3854 | break; | |
3855 | case PORT_C: | |
3856 | *source = INTEL_PIPE_CRC_SOURCE_DP_C; | |
3857 | break; | |
3858 | case PORT_D: | |
3859 | *source = INTEL_PIPE_CRC_SOURCE_DP_D; | |
3860 | break; | |
3861 | default: | |
3862 | WARN(1, "nonexisting DP port %c\n", | |
3863 | port_name(dig_port->port)); | |
3864 | break; | |
3865 | } | |
46a19188 | 3866 | break; |
6847d71b PZ |
3867 | default: |
3868 | break; | |
46a19188 DV |
3869 | } |
3870 | } | |
6e9f798d | 3871 | drm_modeset_unlock_all(dev); |
46a19188 DV |
3872 | |
3873 | return ret; | |
3874 | } | |
3875 | ||
36cdd013 | 3876 | static int vlv_pipe_crc_ctl_reg(struct drm_i915_private *dev_priv, |
46a19188 DV |
3877 | enum pipe pipe, |
3878 | enum intel_pipe_crc_source *source, | |
7ac0129b DV |
3879 | uint32_t *val) |
3880 | { | |
8d2f24ca DV |
3881 | bool need_stable_symbols = false; |
3882 | ||
46a19188 | 3883 | if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) { |
36cdd013 | 3884 | int ret = i9xx_pipe_crc_auto_source(dev_priv, pipe, source); |
46a19188 DV |
3885 | if (ret) |
3886 | return ret; | |
3887 | } | |
3888 | ||
3889 | switch (*source) { | |
7ac0129b DV |
3890 | case INTEL_PIPE_CRC_SOURCE_PIPE: |
3891 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_VLV; | |
3892 | break; | |
3893 | case INTEL_PIPE_CRC_SOURCE_DP_B: | |
3894 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_VLV; | |
8d2f24ca | 3895 | need_stable_symbols = true; |
7ac0129b DV |
3896 | break; |
3897 | case INTEL_PIPE_CRC_SOURCE_DP_C: | |
3898 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_VLV; | |
8d2f24ca | 3899 | need_stable_symbols = true; |
7ac0129b | 3900 | break; |
2be57922 | 3901 | case INTEL_PIPE_CRC_SOURCE_DP_D: |
36cdd013 | 3902 | if (!IS_CHERRYVIEW(dev_priv)) |
2be57922 VS |
3903 | return -EINVAL; |
3904 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_VLV; | |
3905 | need_stable_symbols = true; | |
3906 | break; | |
7ac0129b DV |
3907 | case INTEL_PIPE_CRC_SOURCE_NONE: |
3908 | *val = 0; | |
3909 | break; | |
3910 | default: | |
3911 | return -EINVAL; | |
3912 | } | |
3913 | ||
8d2f24ca DV |
3914 | /* |
3915 | * When the pipe CRC tap point is after the transcoders we need | |
3916 | * to tweak symbol-level features to produce a deterministic series of | |
3917 | * symbols for a given frame. We need to reset those features only once | |
3918 | * a frame (instead of every nth symbol): | |
3919 | * - DC-balance: used to ensure a better clock recovery from the data | |
3920 | * link (SDVO) | |
3921 | * - DisplayPort scrambling: used for EMI reduction | |
3922 | */ | |
3923 | if (need_stable_symbols) { | |
3924 | uint32_t tmp = I915_READ(PORT_DFT2_G4X); | |
3925 | ||
8d2f24ca | 3926 | tmp |= DC_BALANCE_RESET_VLV; |
eb736679 VS |
3927 | switch (pipe) { |
3928 | case PIPE_A: | |
8d2f24ca | 3929 | tmp |= PIPE_A_SCRAMBLE_RESET; |
eb736679 VS |
3930 | break; |
3931 | case PIPE_B: | |
8d2f24ca | 3932 | tmp |= PIPE_B_SCRAMBLE_RESET; |
eb736679 VS |
3933 | break; |
3934 | case PIPE_C: | |
3935 | tmp |= PIPE_C_SCRAMBLE_RESET; | |
3936 | break; | |
3937 | default: | |
3938 | return -EINVAL; | |
3939 | } | |
8d2f24ca DV |
3940 | I915_WRITE(PORT_DFT2_G4X, tmp); |
3941 | } | |
3942 | ||
7ac0129b DV |
3943 | return 0; |
3944 | } | |
3945 | ||
36cdd013 | 3946 | static int i9xx_pipe_crc_ctl_reg(struct drm_i915_private *dev_priv, |
46a19188 DV |
3947 | enum pipe pipe, |
3948 | enum intel_pipe_crc_source *source, | |
4b79ebf7 DV |
3949 | uint32_t *val) |
3950 | { | |
84093603 DV |
3951 | bool need_stable_symbols = false; |
3952 | ||
46a19188 | 3953 | if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) { |
36cdd013 | 3954 | int ret = i9xx_pipe_crc_auto_source(dev_priv, pipe, source); |
46a19188 DV |
3955 | if (ret) |
3956 | return ret; | |
3957 | } | |
3958 | ||
3959 | switch (*source) { | |
4b79ebf7 DV |
3960 | case INTEL_PIPE_CRC_SOURCE_PIPE: |
3961 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_I9XX; | |
3962 | break; | |
3963 | case INTEL_PIPE_CRC_SOURCE_TV: | |
36cdd013 | 3964 | if (!SUPPORTS_TV(dev_priv)) |
4b79ebf7 DV |
3965 | return -EINVAL; |
3966 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_TV_PRE; | |
3967 | break; | |
3968 | case INTEL_PIPE_CRC_SOURCE_DP_B: | |
36cdd013 | 3969 | if (!IS_G4X(dev_priv)) |
4b79ebf7 DV |
3970 | return -EINVAL; |
3971 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_G4X; | |
84093603 | 3972 | need_stable_symbols = true; |
4b79ebf7 DV |
3973 | break; |
3974 | case INTEL_PIPE_CRC_SOURCE_DP_C: | |
36cdd013 | 3975 | if (!IS_G4X(dev_priv)) |
4b79ebf7 DV |
3976 | return -EINVAL; |
3977 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_G4X; | |
84093603 | 3978 | need_stable_symbols = true; |
4b79ebf7 DV |
3979 | break; |
3980 | case INTEL_PIPE_CRC_SOURCE_DP_D: | |
36cdd013 | 3981 | if (!IS_G4X(dev_priv)) |
4b79ebf7 DV |
3982 | return -EINVAL; |
3983 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_G4X; | |
84093603 | 3984 | need_stable_symbols = true; |
4b79ebf7 DV |
3985 | break; |
3986 | case INTEL_PIPE_CRC_SOURCE_NONE: | |
3987 | *val = 0; | |
3988 | break; | |
3989 | default: | |
3990 | return -EINVAL; | |
3991 | } | |
3992 | ||
84093603 DV |
3993 | /* |
3994 | * When the pipe CRC tap point is after the transcoders we need | |
3995 | * to tweak symbol-level features to produce a deterministic series of | |
3996 | * symbols for a given frame. We need to reset those features only once | |
3997 | * a frame (instead of every nth symbol): | |
3998 | * - DC-balance: used to ensure a better clock recovery from the data | |
3999 | * link (SDVO) | |
4000 | * - DisplayPort scrambling: used for EMI reduction | |
4001 | */ | |
4002 | if (need_stable_symbols) { | |
4003 | uint32_t tmp = I915_READ(PORT_DFT2_G4X); | |
4004 | ||
36cdd013 | 4005 | WARN_ON(!IS_G4X(dev_priv)); |
84093603 DV |
4006 | |
4007 | I915_WRITE(PORT_DFT_I9XX, | |
4008 | I915_READ(PORT_DFT_I9XX) | DC_BALANCE_RESET); | |
4009 | ||
4010 | if (pipe == PIPE_A) | |
4011 | tmp |= PIPE_A_SCRAMBLE_RESET; | |
4012 | else | |
4013 | tmp |= PIPE_B_SCRAMBLE_RESET; | |
4014 | ||
4015 | I915_WRITE(PORT_DFT2_G4X, tmp); | |
4016 | } | |
4017 | ||
4b79ebf7 DV |
4018 | return 0; |
4019 | } | |
4020 | ||
36cdd013 | 4021 | static void vlv_undo_pipe_scramble_reset(struct drm_i915_private *dev_priv, |
8d2f24ca DV |
4022 | enum pipe pipe) |
4023 | { | |
8d2f24ca DV |
4024 | uint32_t tmp = I915_READ(PORT_DFT2_G4X); |
4025 | ||
eb736679 VS |
4026 | switch (pipe) { |
4027 | case PIPE_A: | |
8d2f24ca | 4028 | tmp &= ~PIPE_A_SCRAMBLE_RESET; |
eb736679 VS |
4029 | break; |
4030 | case PIPE_B: | |
8d2f24ca | 4031 | tmp &= ~PIPE_B_SCRAMBLE_RESET; |
eb736679 VS |
4032 | break; |
4033 | case PIPE_C: | |
4034 | tmp &= ~PIPE_C_SCRAMBLE_RESET; | |
4035 | break; | |
4036 | default: | |
4037 | return; | |
4038 | } | |
8d2f24ca DV |
4039 | if (!(tmp & PIPE_SCRAMBLE_RESET_MASK)) |
4040 | tmp &= ~DC_BALANCE_RESET_VLV; | |
4041 | I915_WRITE(PORT_DFT2_G4X, tmp); | |
4042 | ||
4043 | } | |
4044 | ||
36cdd013 | 4045 | static void g4x_undo_pipe_scramble_reset(struct drm_i915_private *dev_priv, |
84093603 DV |
4046 | enum pipe pipe) |
4047 | { | |
84093603 DV |
4048 | uint32_t tmp = I915_READ(PORT_DFT2_G4X); |
4049 | ||
4050 | if (pipe == PIPE_A) | |
4051 | tmp &= ~PIPE_A_SCRAMBLE_RESET; | |
4052 | else | |
4053 | tmp &= ~PIPE_B_SCRAMBLE_RESET; | |
4054 | I915_WRITE(PORT_DFT2_G4X, tmp); | |
4055 | ||
4056 | if (!(tmp & PIPE_SCRAMBLE_RESET_MASK)) { | |
4057 | I915_WRITE(PORT_DFT_I9XX, | |
4058 | I915_READ(PORT_DFT_I9XX) & ~DC_BALANCE_RESET); | |
4059 | } | |
4060 | } | |
4061 | ||
46a19188 | 4062 | static int ilk_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source, |
5b3a856b DV |
4063 | uint32_t *val) |
4064 | { | |
46a19188 DV |
4065 | if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) |
4066 | *source = INTEL_PIPE_CRC_SOURCE_PIPE; | |
4067 | ||
4068 | switch (*source) { | |
5b3a856b DV |
4069 | case INTEL_PIPE_CRC_SOURCE_PLANE1: |
4070 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_ILK; | |
4071 | break; | |
4072 | case INTEL_PIPE_CRC_SOURCE_PLANE2: | |
4073 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_ILK; | |
4074 | break; | |
5b3a856b DV |
4075 | case INTEL_PIPE_CRC_SOURCE_PIPE: |
4076 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_ILK; | |
4077 | break; | |
3d099a05 | 4078 | case INTEL_PIPE_CRC_SOURCE_NONE: |
5b3a856b DV |
4079 | *val = 0; |
4080 | break; | |
3d099a05 DV |
4081 | default: |
4082 | return -EINVAL; | |
5b3a856b DV |
4083 | } |
4084 | ||
4085 | return 0; | |
4086 | } | |
4087 | ||
36cdd013 DW |
4088 | static void hsw_trans_edp_pipe_A_crc_wa(struct drm_i915_private *dev_priv, |
4089 | bool enable) | |
fabf6e51 | 4090 | { |
36cdd013 | 4091 | struct drm_device *dev = &dev_priv->drm; |
fabf6e51 DV |
4092 | struct intel_crtc *crtc = |
4093 | to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_A]); | |
f77076c9 | 4094 | struct intel_crtc_state *pipe_config; |
c4e2d043 ML |
4095 | struct drm_atomic_state *state; |
4096 | int ret = 0; | |
fabf6e51 DV |
4097 | |
4098 | drm_modeset_lock_all(dev); | |
c4e2d043 ML |
4099 | state = drm_atomic_state_alloc(dev); |
4100 | if (!state) { | |
4101 | ret = -ENOMEM; | |
4102 | goto out; | |
fabf6e51 | 4103 | } |
fabf6e51 | 4104 | |
c4e2d043 ML |
4105 | state->acquire_ctx = drm_modeset_legacy_acquire_ctx(&crtc->base); |
4106 | pipe_config = intel_atomic_get_crtc_state(state, crtc); | |
4107 | if (IS_ERR(pipe_config)) { | |
4108 | ret = PTR_ERR(pipe_config); | |
4109 | goto out; | |
4110 | } | |
fabf6e51 | 4111 | |
c4e2d043 ML |
4112 | pipe_config->pch_pfit.force_thru = enable; |
4113 | if (pipe_config->cpu_transcoder == TRANSCODER_EDP && | |
4114 | pipe_config->pch_pfit.enabled != enable) | |
4115 | pipe_config->base.connectors_changed = true; | |
1b509259 | 4116 | |
c4e2d043 ML |
4117 | ret = drm_atomic_commit(state); |
4118 | out: | |
c4e2d043 | 4119 | WARN(ret, "Toggling workaround to %i returns %i\n", enable, ret); |
0853695c CW |
4120 | drm_modeset_unlock_all(dev); |
4121 | drm_atomic_state_put(state); | |
fabf6e51 DV |
4122 | } |
4123 | ||
36cdd013 | 4124 | static int ivb_pipe_crc_ctl_reg(struct drm_i915_private *dev_priv, |
fabf6e51 DV |
4125 | enum pipe pipe, |
4126 | enum intel_pipe_crc_source *source, | |
5b3a856b DV |
4127 | uint32_t *val) |
4128 | { | |
46a19188 DV |
4129 | if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) |
4130 | *source = INTEL_PIPE_CRC_SOURCE_PF; | |
4131 | ||
4132 | switch (*source) { | |
5b3a856b DV |
4133 | case INTEL_PIPE_CRC_SOURCE_PLANE1: |
4134 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_IVB; | |
4135 | break; | |
4136 | case INTEL_PIPE_CRC_SOURCE_PLANE2: | |
4137 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_IVB; | |
4138 | break; | |
4139 | case INTEL_PIPE_CRC_SOURCE_PF: | |
36cdd013 DW |
4140 | if (IS_HASWELL(dev_priv) && pipe == PIPE_A) |
4141 | hsw_trans_edp_pipe_A_crc_wa(dev_priv, true); | |
fabf6e51 | 4142 | |
5b3a856b DV |
4143 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PF_IVB; |
4144 | break; | |
3d099a05 | 4145 | case INTEL_PIPE_CRC_SOURCE_NONE: |
5b3a856b DV |
4146 | *val = 0; |
4147 | break; | |
3d099a05 DV |
4148 | default: |
4149 | return -EINVAL; | |
5b3a856b DV |
4150 | } |
4151 | ||
4152 | return 0; | |
4153 | } | |
4154 | ||
36cdd013 DW |
4155 | static int pipe_crc_set_source(struct drm_i915_private *dev_priv, |
4156 | enum pipe pipe, | |
926321d5 DV |
4157 | enum intel_pipe_crc_source source) |
4158 | { | |
36cdd013 | 4159 | struct drm_device *dev = &dev_priv->drm; |
cc3da175 | 4160 | struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe]; |
36cdd013 DW |
4161 | struct intel_crtc *crtc = |
4162 | to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe)); | |
e129649b | 4163 | enum intel_display_power_domain power_domain; |
432f3342 | 4164 | u32 val = 0; /* shut up gcc */ |
5b3a856b | 4165 | int ret; |
926321d5 | 4166 | |
cc3da175 DL |
4167 | if (pipe_crc->source == source) |
4168 | return 0; | |
4169 | ||
ae676fcd DL |
4170 | /* forbid changing the source without going back to 'none' */ |
4171 | if (pipe_crc->source && source) | |
4172 | return -EINVAL; | |
4173 | ||
e129649b ID |
4174 | power_domain = POWER_DOMAIN_PIPE(pipe); |
4175 | if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) { | |
9d8b0588 DV |
4176 | DRM_DEBUG_KMS("Trying to capture CRC while pipe is off\n"); |
4177 | return -EIO; | |
4178 | } | |
4179 | ||
36cdd013 | 4180 | if (IS_GEN2(dev_priv)) |
46a19188 | 4181 | ret = i8xx_pipe_crc_ctl_reg(&source, &val); |
36cdd013 DW |
4182 | else if (INTEL_GEN(dev_priv) < 5) |
4183 | ret = i9xx_pipe_crc_ctl_reg(dev_priv, pipe, &source, &val); | |
4184 | else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) | |
4185 | ret = vlv_pipe_crc_ctl_reg(dev_priv, pipe, &source, &val); | |
4186 | else if (IS_GEN5(dev_priv) || IS_GEN6(dev_priv)) | |
46a19188 | 4187 | ret = ilk_pipe_crc_ctl_reg(&source, &val); |
5b3a856b | 4188 | else |
36cdd013 | 4189 | ret = ivb_pipe_crc_ctl_reg(dev_priv, pipe, &source, &val); |
5b3a856b DV |
4190 | |
4191 | if (ret != 0) | |
e129649b | 4192 | goto out; |
5b3a856b | 4193 | |
4b584369 DL |
4194 | /* none -> real source transition */ |
4195 | if (source) { | |
4252fbc3 VS |
4196 | struct intel_pipe_crc_entry *entries; |
4197 | ||
7cd6ccff DL |
4198 | DRM_DEBUG_DRIVER("collecting CRCs for pipe %c, %s\n", |
4199 | pipe_name(pipe), pipe_crc_source_name(source)); | |
4200 | ||
3cf54b34 VS |
4201 | entries = kcalloc(INTEL_PIPE_CRC_ENTRIES_NR, |
4202 | sizeof(pipe_crc->entries[0]), | |
4252fbc3 | 4203 | GFP_KERNEL); |
e129649b ID |
4204 | if (!entries) { |
4205 | ret = -ENOMEM; | |
4206 | goto out; | |
4207 | } | |
e5f75aca | 4208 | |
8c740dce PZ |
4209 | /* |
4210 | * When IPS gets enabled, the pipe CRC changes. Since IPS gets | |
4211 | * enabled and disabled dynamically based on package C states, | |
4212 | * user space can't make reliable use of the CRCs, so let's just | |
4213 | * completely disable it. | |
4214 | */ | |
4215 | hsw_disable_ips(crtc); | |
4216 | ||
d538bbdf | 4217 | spin_lock_irq(&pipe_crc->lock); |
64387b61 | 4218 | kfree(pipe_crc->entries); |
4252fbc3 | 4219 | pipe_crc->entries = entries; |
d538bbdf DL |
4220 | pipe_crc->head = 0; |
4221 | pipe_crc->tail = 0; | |
4222 | spin_unlock_irq(&pipe_crc->lock); | |
4b584369 DL |
4223 | } |
4224 | ||
cc3da175 | 4225 | pipe_crc->source = source; |
926321d5 | 4226 | |
926321d5 DV |
4227 | I915_WRITE(PIPE_CRC_CTL(pipe), val); |
4228 | POSTING_READ(PIPE_CRC_CTL(pipe)); | |
4229 | ||
e5f75aca DL |
4230 | /* real source -> none transition */ |
4231 | if (source == INTEL_PIPE_CRC_SOURCE_NONE) { | |
d538bbdf | 4232 | struct intel_pipe_crc_entry *entries; |
a33d7105 DV |
4233 | struct intel_crtc *crtc = |
4234 | to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); | |
d538bbdf | 4235 | |
7cd6ccff DL |
4236 | DRM_DEBUG_DRIVER("stopping CRCs for pipe %c\n", |
4237 | pipe_name(pipe)); | |
4238 | ||
a33d7105 | 4239 | drm_modeset_lock(&crtc->base.mutex, NULL); |
f77076c9 | 4240 | if (crtc->base.state->active) |
a33d7105 DV |
4241 | intel_wait_for_vblank(dev, pipe); |
4242 | drm_modeset_unlock(&crtc->base.mutex); | |
bcf17ab2 | 4243 | |
d538bbdf DL |
4244 | spin_lock_irq(&pipe_crc->lock); |
4245 | entries = pipe_crc->entries; | |
e5f75aca | 4246 | pipe_crc->entries = NULL; |
9ad6d99f VS |
4247 | pipe_crc->head = 0; |
4248 | pipe_crc->tail = 0; | |
d538bbdf DL |
4249 | spin_unlock_irq(&pipe_crc->lock); |
4250 | ||
4251 | kfree(entries); | |
84093603 | 4252 | |
36cdd013 DW |
4253 | if (IS_G4X(dev_priv)) |
4254 | g4x_undo_pipe_scramble_reset(dev_priv, pipe); | |
4255 | else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) | |
4256 | vlv_undo_pipe_scramble_reset(dev_priv, pipe); | |
4257 | else if (IS_HASWELL(dev_priv) && pipe == PIPE_A) | |
4258 | hsw_trans_edp_pipe_A_crc_wa(dev_priv, false); | |
8c740dce PZ |
4259 | |
4260 | hsw_enable_ips(crtc); | |
e5f75aca DL |
4261 | } |
4262 | ||
e129649b ID |
4263 | ret = 0; |
4264 | ||
4265 | out: | |
4266 | intel_display_power_put(dev_priv, power_domain); | |
4267 | ||
4268 | return ret; | |
926321d5 DV |
4269 | } |
4270 | ||
4271 | /* | |
4272 | * Parse pipe CRC command strings: | |
b94dec87 DL |
4273 | * command: wsp* object wsp+ name wsp+ source wsp* |
4274 | * object: 'pipe' | |
4275 | * name: (A | B | C) | |
926321d5 DV |
4276 | * source: (none | plane1 | plane2 | pf) |
4277 | * wsp: (#0x20 | #0x9 | #0xA)+ | |
4278 | * | |
4279 | * eg.: | |
b94dec87 DL |
4280 | * "pipe A plane1" -> Start CRC computations on plane1 of pipe A |
4281 | * "pipe A none" -> Stop CRC | |
926321d5 | 4282 | */ |
bd9db02f | 4283 | static int display_crc_ctl_tokenize(char *buf, char *words[], int max_words) |
926321d5 DV |
4284 | { |
4285 | int n_words = 0; | |
4286 | ||
4287 | while (*buf) { | |
4288 | char *end; | |
4289 | ||
4290 | /* skip leading white space */ | |
4291 | buf = skip_spaces(buf); | |
4292 | if (!*buf) | |
4293 | break; /* end of buffer */ | |
4294 | ||
4295 | /* find end of word */ | |
4296 | for (end = buf; *end && !isspace(*end); end++) | |
4297 | ; | |
4298 | ||
4299 | if (n_words == max_words) { | |
4300 | DRM_DEBUG_DRIVER("too many words, allowed <= %d\n", | |
4301 | max_words); | |
4302 | return -EINVAL; /* ran out of words[] before bytes */ | |
4303 | } | |
4304 | ||
4305 | if (*end) | |
4306 | *end++ = '\0'; | |
4307 | words[n_words++] = buf; | |
4308 | buf = end; | |
4309 | } | |
4310 | ||
4311 | return n_words; | |
4312 | } | |
4313 | ||
b94dec87 DL |
4314 | enum intel_pipe_crc_object { |
4315 | PIPE_CRC_OBJECT_PIPE, | |
4316 | }; | |
4317 | ||
e8dfcf78 | 4318 | static const char * const pipe_crc_objects[] = { |
b94dec87 DL |
4319 | "pipe", |
4320 | }; | |
4321 | ||
4322 | static int | |
bd9db02f | 4323 | display_crc_ctl_parse_object(const char *buf, enum intel_pipe_crc_object *o) |
b94dec87 DL |
4324 | { |
4325 | int i; | |
4326 | ||
4327 | for (i = 0; i < ARRAY_SIZE(pipe_crc_objects); i++) | |
4328 | if (!strcmp(buf, pipe_crc_objects[i])) { | |
bd9db02f | 4329 | *o = i; |
b94dec87 DL |
4330 | return 0; |
4331 | } | |
4332 | ||
4333 | return -EINVAL; | |
4334 | } | |
4335 | ||
bd9db02f | 4336 | static int display_crc_ctl_parse_pipe(const char *buf, enum pipe *pipe) |
926321d5 DV |
4337 | { |
4338 | const char name = buf[0]; | |
4339 | ||
4340 | if (name < 'A' || name >= pipe_name(I915_MAX_PIPES)) | |
4341 | return -EINVAL; | |
4342 | ||
4343 | *pipe = name - 'A'; | |
4344 | ||
4345 | return 0; | |
4346 | } | |
4347 | ||
4348 | static int | |
bd9db02f | 4349 | display_crc_ctl_parse_source(const char *buf, enum intel_pipe_crc_source *s) |
926321d5 DV |
4350 | { |
4351 | int i; | |
4352 | ||
4353 | for (i = 0; i < ARRAY_SIZE(pipe_crc_sources); i++) | |
4354 | if (!strcmp(buf, pipe_crc_sources[i])) { | |
bd9db02f | 4355 | *s = i; |
926321d5 DV |
4356 | return 0; |
4357 | } | |
4358 | ||
4359 | return -EINVAL; | |
4360 | } | |
4361 | ||
36cdd013 DW |
4362 | static int display_crc_ctl_parse(struct drm_i915_private *dev_priv, |
4363 | char *buf, size_t len) | |
926321d5 | 4364 | { |
b94dec87 | 4365 | #define N_WORDS 3 |
926321d5 | 4366 | int n_words; |
b94dec87 | 4367 | char *words[N_WORDS]; |
926321d5 | 4368 | enum pipe pipe; |
b94dec87 | 4369 | enum intel_pipe_crc_object object; |
926321d5 DV |
4370 | enum intel_pipe_crc_source source; |
4371 | ||
bd9db02f | 4372 | n_words = display_crc_ctl_tokenize(buf, words, N_WORDS); |
b94dec87 DL |
4373 | if (n_words != N_WORDS) { |
4374 | DRM_DEBUG_DRIVER("tokenize failed, a command is %d words\n", | |
4375 | N_WORDS); | |
4376 | return -EINVAL; | |
4377 | } | |
4378 | ||
bd9db02f | 4379 | if (display_crc_ctl_parse_object(words[0], &object) < 0) { |
b94dec87 | 4380 | DRM_DEBUG_DRIVER("unknown object %s\n", words[0]); |
926321d5 DV |
4381 | return -EINVAL; |
4382 | } | |
4383 | ||
bd9db02f | 4384 | if (display_crc_ctl_parse_pipe(words[1], &pipe) < 0) { |
b94dec87 | 4385 | DRM_DEBUG_DRIVER("unknown pipe %s\n", words[1]); |
926321d5 DV |
4386 | return -EINVAL; |
4387 | } | |
4388 | ||
bd9db02f | 4389 | if (display_crc_ctl_parse_source(words[2], &source) < 0) { |
b94dec87 | 4390 | DRM_DEBUG_DRIVER("unknown source %s\n", words[2]); |
926321d5 DV |
4391 | return -EINVAL; |
4392 | } | |
4393 | ||
36cdd013 | 4394 | return pipe_crc_set_source(dev_priv, pipe, source); |
926321d5 DV |
4395 | } |
4396 | ||
bd9db02f DL |
4397 | static ssize_t display_crc_ctl_write(struct file *file, const char __user *ubuf, |
4398 | size_t len, loff_t *offp) | |
926321d5 DV |
4399 | { |
4400 | struct seq_file *m = file->private_data; | |
36cdd013 | 4401 | struct drm_i915_private *dev_priv = m->private; |
926321d5 DV |
4402 | char *tmpbuf; |
4403 | int ret; | |
4404 | ||
4405 | if (len == 0) | |
4406 | return 0; | |
4407 | ||
4408 | if (len > PAGE_SIZE - 1) { | |
4409 | DRM_DEBUG_DRIVER("expected <%lu bytes into pipe crc control\n", | |
4410 | PAGE_SIZE); | |
4411 | return -E2BIG; | |
4412 | } | |
4413 | ||
4414 | tmpbuf = kmalloc(len + 1, GFP_KERNEL); | |
4415 | if (!tmpbuf) | |
4416 | return -ENOMEM; | |
4417 | ||
4418 | if (copy_from_user(tmpbuf, ubuf, len)) { | |
4419 | ret = -EFAULT; | |
4420 | goto out; | |
4421 | } | |
4422 | tmpbuf[len] = '\0'; | |
4423 | ||
36cdd013 | 4424 | ret = display_crc_ctl_parse(dev_priv, tmpbuf, len); |
926321d5 DV |
4425 | |
4426 | out: | |
4427 | kfree(tmpbuf); | |
4428 | if (ret < 0) | |
4429 | return ret; | |
4430 | ||
4431 | *offp += len; | |
4432 | return len; | |
4433 | } | |
4434 | ||
bd9db02f | 4435 | static const struct file_operations i915_display_crc_ctl_fops = { |
926321d5 | 4436 | .owner = THIS_MODULE, |
bd9db02f | 4437 | .open = display_crc_ctl_open, |
926321d5 DV |
4438 | .read = seq_read, |
4439 | .llseek = seq_lseek, | |
4440 | .release = single_release, | |
bd9db02f | 4441 | .write = display_crc_ctl_write |
926321d5 DV |
4442 | }; |
4443 | ||
eb3394fa | 4444 | static ssize_t i915_displayport_test_active_write(struct file *file, |
36cdd013 DW |
4445 | const char __user *ubuf, |
4446 | size_t len, loff_t *offp) | |
eb3394fa TP |
4447 | { |
4448 | char *input_buffer; | |
4449 | int status = 0; | |
eb3394fa TP |
4450 | struct drm_device *dev; |
4451 | struct drm_connector *connector; | |
4452 | struct list_head *connector_list; | |
4453 | struct intel_dp *intel_dp; | |
4454 | int val = 0; | |
4455 | ||
9aaffa34 | 4456 | dev = ((struct seq_file *)file->private_data)->private; |
eb3394fa | 4457 | |
eb3394fa TP |
4458 | connector_list = &dev->mode_config.connector_list; |
4459 | ||
4460 | if (len == 0) | |
4461 | return 0; | |
4462 | ||
4463 | input_buffer = kmalloc(len + 1, GFP_KERNEL); | |
4464 | if (!input_buffer) | |
4465 | return -ENOMEM; | |
4466 | ||
4467 | if (copy_from_user(input_buffer, ubuf, len)) { | |
4468 | status = -EFAULT; | |
4469 | goto out; | |
4470 | } | |
4471 | ||
4472 | input_buffer[len] = '\0'; | |
4473 | DRM_DEBUG_DRIVER("Copied %d bytes from user\n", (unsigned int)len); | |
4474 | ||
4475 | list_for_each_entry(connector, connector_list, head) { | |
eb3394fa TP |
4476 | if (connector->connector_type != |
4477 | DRM_MODE_CONNECTOR_DisplayPort) | |
4478 | continue; | |
4479 | ||
b8bb08ec | 4480 | if (connector->status == connector_status_connected && |
eb3394fa TP |
4481 | connector->encoder != NULL) { |
4482 | intel_dp = enc_to_intel_dp(connector->encoder); | |
4483 | status = kstrtoint(input_buffer, 10, &val); | |
4484 | if (status < 0) | |
4485 | goto out; | |
4486 | DRM_DEBUG_DRIVER("Got %d for test active\n", val); | |
4487 | /* To prevent erroneous activation of the compliance | |
4488 | * testing code, only accept an actual value of 1 here | |
4489 | */ | |
4490 | if (val == 1) | |
4491 | intel_dp->compliance_test_active = 1; | |
4492 | else | |
4493 | intel_dp->compliance_test_active = 0; | |
4494 | } | |
4495 | } | |
4496 | out: | |
4497 | kfree(input_buffer); | |
4498 | if (status < 0) | |
4499 | return status; | |
4500 | ||
4501 | *offp += len; | |
4502 | return len; | |
4503 | } | |
4504 | ||
4505 | static int i915_displayport_test_active_show(struct seq_file *m, void *data) | |
4506 | { | |
4507 | struct drm_device *dev = m->private; | |
4508 | struct drm_connector *connector; | |
4509 | struct list_head *connector_list = &dev->mode_config.connector_list; | |
4510 | struct intel_dp *intel_dp; | |
4511 | ||
eb3394fa | 4512 | list_for_each_entry(connector, connector_list, head) { |
eb3394fa TP |
4513 | if (connector->connector_type != |
4514 | DRM_MODE_CONNECTOR_DisplayPort) | |
4515 | continue; | |
4516 | ||
4517 | if (connector->status == connector_status_connected && | |
4518 | connector->encoder != NULL) { | |
4519 | intel_dp = enc_to_intel_dp(connector->encoder); | |
4520 | if (intel_dp->compliance_test_active) | |
4521 | seq_puts(m, "1"); | |
4522 | else | |
4523 | seq_puts(m, "0"); | |
4524 | } else | |
4525 | seq_puts(m, "0"); | |
4526 | } | |
4527 | ||
4528 | return 0; | |
4529 | } | |
4530 | ||
4531 | static int i915_displayport_test_active_open(struct inode *inode, | |
36cdd013 | 4532 | struct file *file) |
eb3394fa | 4533 | { |
36cdd013 | 4534 | struct drm_i915_private *dev_priv = inode->i_private; |
eb3394fa | 4535 | |
36cdd013 DW |
4536 | return single_open(file, i915_displayport_test_active_show, |
4537 | &dev_priv->drm); | |
eb3394fa TP |
4538 | } |
4539 | ||
4540 | static const struct file_operations i915_displayport_test_active_fops = { | |
4541 | .owner = THIS_MODULE, | |
4542 | .open = i915_displayport_test_active_open, | |
4543 | .read = seq_read, | |
4544 | .llseek = seq_lseek, | |
4545 | .release = single_release, | |
4546 | .write = i915_displayport_test_active_write | |
4547 | }; | |
4548 | ||
4549 | static int i915_displayport_test_data_show(struct seq_file *m, void *data) | |
4550 | { | |
4551 | struct drm_device *dev = m->private; | |
4552 | struct drm_connector *connector; | |
4553 | struct list_head *connector_list = &dev->mode_config.connector_list; | |
4554 | struct intel_dp *intel_dp; | |
4555 | ||
eb3394fa | 4556 | list_for_each_entry(connector, connector_list, head) { |
eb3394fa TP |
4557 | if (connector->connector_type != |
4558 | DRM_MODE_CONNECTOR_DisplayPort) | |
4559 | continue; | |
4560 | ||
4561 | if (connector->status == connector_status_connected && | |
4562 | connector->encoder != NULL) { | |
4563 | intel_dp = enc_to_intel_dp(connector->encoder); | |
4564 | seq_printf(m, "%lx", intel_dp->compliance_test_data); | |
4565 | } else | |
4566 | seq_puts(m, "0"); | |
4567 | } | |
4568 | ||
4569 | return 0; | |
4570 | } | |
4571 | static int i915_displayport_test_data_open(struct inode *inode, | |
36cdd013 | 4572 | struct file *file) |
eb3394fa | 4573 | { |
36cdd013 | 4574 | struct drm_i915_private *dev_priv = inode->i_private; |
eb3394fa | 4575 | |
36cdd013 DW |
4576 | return single_open(file, i915_displayport_test_data_show, |
4577 | &dev_priv->drm); | |
eb3394fa TP |
4578 | } |
4579 | ||
4580 | static const struct file_operations i915_displayport_test_data_fops = { | |
4581 | .owner = THIS_MODULE, | |
4582 | .open = i915_displayport_test_data_open, | |
4583 | .read = seq_read, | |
4584 | .llseek = seq_lseek, | |
4585 | .release = single_release | |
4586 | }; | |
4587 | ||
4588 | static int i915_displayport_test_type_show(struct seq_file *m, void *data) | |
4589 | { | |
4590 | struct drm_device *dev = m->private; | |
4591 | struct drm_connector *connector; | |
4592 | struct list_head *connector_list = &dev->mode_config.connector_list; | |
4593 | struct intel_dp *intel_dp; | |
4594 | ||
eb3394fa | 4595 | list_for_each_entry(connector, connector_list, head) { |
eb3394fa TP |
4596 | if (connector->connector_type != |
4597 | DRM_MODE_CONNECTOR_DisplayPort) | |
4598 | continue; | |
4599 | ||
4600 | if (connector->status == connector_status_connected && | |
4601 | connector->encoder != NULL) { | |
4602 | intel_dp = enc_to_intel_dp(connector->encoder); | |
4603 | seq_printf(m, "%02lx", intel_dp->compliance_test_type); | |
4604 | } else | |
4605 | seq_puts(m, "0"); | |
4606 | } | |
4607 | ||
4608 | return 0; | |
4609 | } | |
4610 | ||
4611 | static int i915_displayport_test_type_open(struct inode *inode, | |
4612 | struct file *file) | |
4613 | { | |
36cdd013 | 4614 | struct drm_i915_private *dev_priv = inode->i_private; |
eb3394fa | 4615 | |
36cdd013 DW |
4616 | return single_open(file, i915_displayport_test_type_show, |
4617 | &dev_priv->drm); | |
eb3394fa TP |
4618 | } |
4619 | ||
4620 | static const struct file_operations i915_displayport_test_type_fops = { | |
4621 | .owner = THIS_MODULE, | |
4622 | .open = i915_displayport_test_type_open, | |
4623 | .read = seq_read, | |
4624 | .llseek = seq_lseek, | |
4625 | .release = single_release | |
4626 | }; | |
4627 | ||
97e94b22 | 4628 | static void wm_latency_show(struct seq_file *m, const uint16_t wm[8]) |
369a1342 | 4629 | { |
36cdd013 DW |
4630 | struct drm_i915_private *dev_priv = m->private; |
4631 | struct drm_device *dev = &dev_priv->drm; | |
369a1342 | 4632 | int level; |
de38b95c VS |
4633 | int num_levels; |
4634 | ||
36cdd013 | 4635 | if (IS_CHERRYVIEW(dev_priv)) |
de38b95c | 4636 | num_levels = 3; |
36cdd013 | 4637 | else if (IS_VALLEYVIEW(dev_priv)) |
de38b95c VS |
4638 | num_levels = 1; |
4639 | else | |
5db94019 | 4640 | num_levels = ilk_wm_max_level(dev_priv) + 1; |
369a1342 VS |
4641 | |
4642 | drm_modeset_lock_all(dev); | |
4643 | ||
4644 | for (level = 0; level < num_levels; level++) { | |
4645 | unsigned int latency = wm[level]; | |
4646 | ||
97e94b22 DL |
4647 | /* |
4648 | * - WM1+ latency values in 0.5us units | |
de38b95c | 4649 | * - latencies are in us on gen9/vlv/chv |
97e94b22 | 4650 | */ |
36cdd013 DW |
4651 | if (INTEL_GEN(dev_priv) >= 9 || IS_VALLEYVIEW(dev_priv) || |
4652 | IS_CHERRYVIEW(dev_priv)) | |
97e94b22 DL |
4653 | latency *= 10; |
4654 | else if (level > 0) | |
369a1342 VS |
4655 | latency *= 5; |
4656 | ||
4657 | seq_printf(m, "WM%d %u (%u.%u usec)\n", | |
97e94b22 | 4658 | level, wm[level], latency / 10, latency % 10); |
369a1342 VS |
4659 | } |
4660 | ||
4661 | drm_modeset_unlock_all(dev); | |
4662 | } | |
4663 | ||
4664 | static int pri_wm_latency_show(struct seq_file *m, void *data) | |
4665 | { | |
36cdd013 | 4666 | struct drm_i915_private *dev_priv = m->private; |
97e94b22 DL |
4667 | const uint16_t *latencies; |
4668 | ||
36cdd013 | 4669 | if (INTEL_GEN(dev_priv) >= 9) |
97e94b22 DL |
4670 | latencies = dev_priv->wm.skl_latency; |
4671 | else | |
36cdd013 | 4672 | latencies = dev_priv->wm.pri_latency; |
369a1342 | 4673 | |
97e94b22 | 4674 | wm_latency_show(m, latencies); |
369a1342 VS |
4675 | |
4676 | return 0; | |
4677 | } | |
4678 | ||
4679 | static int spr_wm_latency_show(struct seq_file *m, void *data) | |
4680 | { | |
36cdd013 | 4681 | struct drm_i915_private *dev_priv = m->private; |
97e94b22 DL |
4682 | const uint16_t *latencies; |
4683 | ||
36cdd013 | 4684 | if (INTEL_GEN(dev_priv) >= 9) |
97e94b22 DL |
4685 | latencies = dev_priv->wm.skl_latency; |
4686 | else | |
36cdd013 | 4687 | latencies = dev_priv->wm.spr_latency; |
369a1342 | 4688 | |
97e94b22 | 4689 | wm_latency_show(m, latencies); |
369a1342 VS |
4690 | |
4691 | return 0; | |
4692 | } | |
4693 | ||
4694 | static int cur_wm_latency_show(struct seq_file *m, void *data) | |
4695 | { | |
36cdd013 | 4696 | struct drm_i915_private *dev_priv = m->private; |
97e94b22 DL |
4697 | const uint16_t *latencies; |
4698 | ||
36cdd013 | 4699 | if (INTEL_GEN(dev_priv) >= 9) |
97e94b22 DL |
4700 | latencies = dev_priv->wm.skl_latency; |
4701 | else | |
36cdd013 | 4702 | latencies = dev_priv->wm.cur_latency; |
369a1342 | 4703 | |
97e94b22 | 4704 | wm_latency_show(m, latencies); |
369a1342 VS |
4705 | |
4706 | return 0; | |
4707 | } | |
4708 | ||
4709 | static int pri_wm_latency_open(struct inode *inode, struct file *file) | |
4710 | { | |
36cdd013 | 4711 | struct drm_i915_private *dev_priv = inode->i_private; |
369a1342 | 4712 | |
36cdd013 | 4713 | if (INTEL_GEN(dev_priv) < 5) |
369a1342 VS |
4714 | return -ENODEV; |
4715 | ||
36cdd013 | 4716 | return single_open(file, pri_wm_latency_show, dev_priv); |
369a1342 VS |
4717 | } |
4718 | ||
4719 | static int spr_wm_latency_open(struct inode *inode, struct file *file) | |
4720 | { | |
36cdd013 | 4721 | struct drm_i915_private *dev_priv = inode->i_private; |
369a1342 | 4722 | |
36cdd013 | 4723 | if (HAS_GMCH_DISPLAY(dev_priv)) |
369a1342 VS |
4724 | return -ENODEV; |
4725 | ||
36cdd013 | 4726 | return single_open(file, spr_wm_latency_show, dev_priv); |
369a1342 VS |
4727 | } |
4728 | ||
4729 | static int cur_wm_latency_open(struct inode *inode, struct file *file) | |
4730 | { | |
36cdd013 | 4731 | struct drm_i915_private *dev_priv = inode->i_private; |
369a1342 | 4732 | |
36cdd013 | 4733 | if (HAS_GMCH_DISPLAY(dev_priv)) |
369a1342 VS |
4734 | return -ENODEV; |
4735 | ||
36cdd013 | 4736 | return single_open(file, cur_wm_latency_show, dev_priv); |
369a1342 VS |
4737 | } |
4738 | ||
4739 | static ssize_t wm_latency_write(struct file *file, const char __user *ubuf, | |
97e94b22 | 4740 | size_t len, loff_t *offp, uint16_t wm[8]) |
369a1342 VS |
4741 | { |
4742 | struct seq_file *m = file->private_data; | |
36cdd013 DW |
4743 | struct drm_i915_private *dev_priv = m->private; |
4744 | struct drm_device *dev = &dev_priv->drm; | |
97e94b22 | 4745 | uint16_t new[8] = { 0 }; |
de38b95c | 4746 | int num_levels; |
369a1342 VS |
4747 | int level; |
4748 | int ret; | |
4749 | char tmp[32]; | |
4750 | ||
36cdd013 | 4751 | if (IS_CHERRYVIEW(dev_priv)) |
de38b95c | 4752 | num_levels = 3; |
36cdd013 | 4753 | else if (IS_VALLEYVIEW(dev_priv)) |
de38b95c VS |
4754 | num_levels = 1; |
4755 | else | |
5db94019 | 4756 | num_levels = ilk_wm_max_level(dev_priv) + 1; |
de38b95c | 4757 | |
369a1342 VS |
4758 | if (len >= sizeof(tmp)) |
4759 | return -EINVAL; | |
4760 | ||
4761 | if (copy_from_user(tmp, ubuf, len)) | |
4762 | return -EFAULT; | |
4763 | ||
4764 | tmp[len] = '\0'; | |
4765 | ||
97e94b22 DL |
4766 | ret = sscanf(tmp, "%hu %hu %hu %hu %hu %hu %hu %hu", |
4767 | &new[0], &new[1], &new[2], &new[3], | |
4768 | &new[4], &new[5], &new[6], &new[7]); | |
369a1342 VS |
4769 | if (ret != num_levels) |
4770 | return -EINVAL; | |
4771 | ||
4772 | drm_modeset_lock_all(dev); | |
4773 | ||
4774 | for (level = 0; level < num_levels; level++) | |
4775 | wm[level] = new[level]; | |
4776 | ||
4777 | drm_modeset_unlock_all(dev); | |
4778 | ||
4779 | return len; | |
4780 | } | |
4781 | ||
4782 | ||
4783 | static ssize_t pri_wm_latency_write(struct file *file, const char __user *ubuf, | |
4784 | size_t len, loff_t *offp) | |
4785 | { | |
4786 | struct seq_file *m = file->private_data; | |
36cdd013 | 4787 | struct drm_i915_private *dev_priv = m->private; |
97e94b22 | 4788 | uint16_t *latencies; |
369a1342 | 4789 | |
36cdd013 | 4790 | if (INTEL_GEN(dev_priv) >= 9) |
97e94b22 DL |
4791 | latencies = dev_priv->wm.skl_latency; |
4792 | else | |
36cdd013 | 4793 | latencies = dev_priv->wm.pri_latency; |
97e94b22 DL |
4794 | |
4795 | return wm_latency_write(file, ubuf, len, offp, latencies); | |
369a1342 VS |
4796 | } |
4797 | ||
4798 | static ssize_t spr_wm_latency_write(struct file *file, const char __user *ubuf, | |
4799 | size_t len, loff_t *offp) | |
4800 | { | |
4801 | struct seq_file *m = file->private_data; | |
36cdd013 | 4802 | struct drm_i915_private *dev_priv = m->private; |
97e94b22 | 4803 | uint16_t *latencies; |
369a1342 | 4804 | |
36cdd013 | 4805 | if (INTEL_GEN(dev_priv) >= 9) |
97e94b22 DL |
4806 | latencies = dev_priv->wm.skl_latency; |
4807 | else | |
36cdd013 | 4808 | latencies = dev_priv->wm.spr_latency; |
97e94b22 DL |
4809 | |
4810 | return wm_latency_write(file, ubuf, len, offp, latencies); | |
369a1342 VS |
4811 | } |
4812 | ||
4813 | static ssize_t cur_wm_latency_write(struct file *file, const char __user *ubuf, | |
4814 | size_t len, loff_t *offp) | |
4815 | { | |
4816 | struct seq_file *m = file->private_data; | |
36cdd013 | 4817 | struct drm_i915_private *dev_priv = m->private; |
97e94b22 DL |
4818 | uint16_t *latencies; |
4819 | ||
36cdd013 | 4820 | if (INTEL_GEN(dev_priv) >= 9) |
97e94b22 DL |
4821 | latencies = dev_priv->wm.skl_latency; |
4822 | else | |
36cdd013 | 4823 | latencies = dev_priv->wm.cur_latency; |
369a1342 | 4824 | |
97e94b22 | 4825 | return wm_latency_write(file, ubuf, len, offp, latencies); |
369a1342 VS |
4826 | } |
4827 | ||
4828 | static const struct file_operations i915_pri_wm_latency_fops = { | |
4829 | .owner = THIS_MODULE, | |
4830 | .open = pri_wm_latency_open, | |
4831 | .read = seq_read, | |
4832 | .llseek = seq_lseek, | |
4833 | .release = single_release, | |
4834 | .write = pri_wm_latency_write | |
4835 | }; | |
4836 | ||
4837 | static const struct file_operations i915_spr_wm_latency_fops = { | |
4838 | .owner = THIS_MODULE, | |
4839 | .open = spr_wm_latency_open, | |
4840 | .read = seq_read, | |
4841 | .llseek = seq_lseek, | |
4842 | .release = single_release, | |
4843 | .write = spr_wm_latency_write | |
4844 | }; | |
4845 | ||
4846 | static const struct file_operations i915_cur_wm_latency_fops = { | |
4847 | .owner = THIS_MODULE, | |
4848 | .open = cur_wm_latency_open, | |
4849 | .read = seq_read, | |
4850 | .llseek = seq_lseek, | |
4851 | .release = single_release, | |
4852 | .write = cur_wm_latency_write | |
4853 | }; | |
4854 | ||
647416f9 KC |
4855 | static int |
4856 | i915_wedged_get(void *data, u64 *val) | |
f3cd474b | 4857 | { |
36cdd013 | 4858 | struct drm_i915_private *dev_priv = data; |
f3cd474b | 4859 | |
d98c52cf | 4860 | *val = i915_terminally_wedged(&dev_priv->gpu_error); |
f3cd474b | 4861 | |
647416f9 | 4862 | return 0; |
f3cd474b CW |
4863 | } |
4864 | ||
647416f9 KC |
4865 | static int |
4866 | i915_wedged_set(void *data, u64 val) | |
f3cd474b | 4867 | { |
36cdd013 | 4868 | struct drm_i915_private *dev_priv = data; |
d46c0517 | 4869 | |
b8d24a06 MK |
4870 | /* |
4871 | * There is no safeguard against this debugfs entry colliding | |
4872 | * with the hangcheck calling same i915_handle_error() in | |
4873 | * parallel, causing an explosion. For now we assume that the | |
4874 | * test harness is responsible enough not to inject gpu hangs | |
4875 | * while it is writing to 'i915_wedged' | |
4876 | */ | |
4877 | ||
d98c52cf | 4878 | if (i915_reset_in_progress(&dev_priv->gpu_error)) |
b8d24a06 MK |
4879 | return -EAGAIN; |
4880 | ||
c033666a | 4881 | i915_handle_error(dev_priv, val, |
58174462 | 4882 | "Manually setting wedged to %llu", val); |
d46c0517 | 4883 | |
647416f9 | 4884 | return 0; |
f3cd474b CW |
4885 | } |
4886 | ||
647416f9 KC |
4887 | DEFINE_SIMPLE_ATTRIBUTE(i915_wedged_fops, |
4888 | i915_wedged_get, i915_wedged_set, | |
3a3b4f98 | 4889 | "%llu\n"); |
f3cd474b | 4890 | |
094f9a54 CW |
4891 | static int |
4892 | i915_ring_missed_irq_get(void *data, u64 *val) | |
4893 | { | |
36cdd013 | 4894 | struct drm_i915_private *dev_priv = data; |
094f9a54 CW |
4895 | |
4896 | *val = dev_priv->gpu_error.missed_irq_rings; | |
4897 | return 0; | |
4898 | } | |
4899 | ||
4900 | static int | |
4901 | i915_ring_missed_irq_set(void *data, u64 val) | |
4902 | { | |
36cdd013 DW |
4903 | struct drm_i915_private *dev_priv = data; |
4904 | struct drm_device *dev = &dev_priv->drm; | |
094f9a54 CW |
4905 | int ret; |
4906 | ||
4907 | /* Lock against concurrent debugfs callers */ | |
4908 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
4909 | if (ret) | |
4910 | return ret; | |
4911 | dev_priv->gpu_error.missed_irq_rings = val; | |
4912 | mutex_unlock(&dev->struct_mutex); | |
4913 | ||
4914 | return 0; | |
4915 | } | |
4916 | ||
4917 | DEFINE_SIMPLE_ATTRIBUTE(i915_ring_missed_irq_fops, | |
4918 | i915_ring_missed_irq_get, i915_ring_missed_irq_set, | |
4919 | "0x%08llx\n"); | |
4920 | ||
4921 | static int | |
4922 | i915_ring_test_irq_get(void *data, u64 *val) | |
4923 | { | |
36cdd013 | 4924 | struct drm_i915_private *dev_priv = data; |
094f9a54 CW |
4925 | |
4926 | *val = dev_priv->gpu_error.test_irq_rings; | |
4927 | ||
4928 | return 0; | |
4929 | } | |
4930 | ||
4931 | static int | |
4932 | i915_ring_test_irq_set(void *data, u64 val) | |
4933 | { | |
36cdd013 | 4934 | struct drm_i915_private *dev_priv = data; |
094f9a54 | 4935 | |
3a122c27 | 4936 | val &= INTEL_INFO(dev_priv)->ring_mask; |
094f9a54 | 4937 | DRM_DEBUG_DRIVER("Masking interrupts on rings 0x%08llx\n", val); |
094f9a54 | 4938 | dev_priv->gpu_error.test_irq_rings = val; |
094f9a54 CW |
4939 | |
4940 | return 0; | |
4941 | } | |
4942 | ||
4943 | DEFINE_SIMPLE_ATTRIBUTE(i915_ring_test_irq_fops, | |
4944 | i915_ring_test_irq_get, i915_ring_test_irq_set, | |
4945 | "0x%08llx\n"); | |
4946 | ||
dd624afd CW |
4947 | #define DROP_UNBOUND 0x1 |
4948 | #define DROP_BOUND 0x2 | |
4949 | #define DROP_RETIRE 0x4 | |
4950 | #define DROP_ACTIVE 0x8 | |
fbbd37b3 CW |
4951 | #define DROP_FREED 0x10 |
4952 | #define DROP_ALL (DROP_UNBOUND | \ | |
4953 | DROP_BOUND | \ | |
4954 | DROP_RETIRE | \ | |
4955 | DROP_ACTIVE | \ | |
4956 | DROP_FREED) | |
647416f9 KC |
4957 | static int |
4958 | i915_drop_caches_get(void *data, u64 *val) | |
dd624afd | 4959 | { |
647416f9 | 4960 | *val = DROP_ALL; |
dd624afd | 4961 | |
647416f9 | 4962 | return 0; |
dd624afd CW |
4963 | } |
4964 | ||
647416f9 KC |
4965 | static int |
4966 | i915_drop_caches_set(void *data, u64 val) | |
dd624afd | 4967 | { |
36cdd013 DW |
4968 | struct drm_i915_private *dev_priv = data; |
4969 | struct drm_device *dev = &dev_priv->drm; | |
647416f9 | 4970 | int ret; |
dd624afd | 4971 | |
2f9fe5ff | 4972 | DRM_DEBUG("Dropping caches: 0x%08llx\n", val); |
dd624afd CW |
4973 | |
4974 | /* No need to check and wait for gpu resets, only libdrm auto-restarts | |
4975 | * on ioctls on -EAGAIN. */ | |
4976 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
4977 | if (ret) | |
4978 | return ret; | |
4979 | ||
4980 | if (val & DROP_ACTIVE) { | |
22dd3bb9 CW |
4981 | ret = i915_gem_wait_for_idle(dev_priv, |
4982 | I915_WAIT_INTERRUPTIBLE | | |
4983 | I915_WAIT_LOCKED); | |
dd624afd CW |
4984 | if (ret) |
4985 | goto unlock; | |
4986 | } | |
4987 | ||
4988 | if (val & (DROP_RETIRE | DROP_ACTIVE)) | |
c033666a | 4989 | i915_gem_retire_requests(dev_priv); |
dd624afd | 4990 | |
21ab4e74 CW |
4991 | if (val & DROP_BOUND) |
4992 | i915_gem_shrink(dev_priv, LONG_MAX, I915_SHRINK_BOUND); | |
4ad72b7f | 4993 | |
21ab4e74 CW |
4994 | if (val & DROP_UNBOUND) |
4995 | i915_gem_shrink(dev_priv, LONG_MAX, I915_SHRINK_UNBOUND); | |
dd624afd CW |
4996 | |
4997 | unlock: | |
4998 | mutex_unlock(&dev->struct_mutex); | |
4999 | ||
fbbd37b3 CW |
5000 | if (val & DROP_FREED) { |
5001 | synchronize_rcu(); | |
5002 | flush_work(&dev_priv->mm.free_work); | |
5003 | } | |
5004 | ||
647416f9 | 5005 | return ret; |
dd624afd CW |
5006 | } |
5007 | ||
647416f9 KC |
5008 | DEFINE_SIMPLE_ATTRIBUTE(i915_drop_caches_fops, |
5009 | i915_drop_caches_get, i915_drop_caches_set, | |
5010 | "0x%08llx\n"); | |
dd624afd | 5011 | |
647416f9 KC |
5012 | static int |
5013 | i915_max_freq_get(void *data, u64 *val) | |
358733e9 | 5014 | { |
36cdd013 | 5015 | struct drm_i915_private *dev_priv = data; |
004777cb | 5016 | |
36cdd013 | 5017 | if (INTEL_GEN(dev_priv) < 6) |
004777cb DV |
5018 | return -ENODEV; |
5019 | ||
7c59a9c1 | 5020 | *val = intel_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit); |
647416f9 | 5021 | return 0; |
358733e9 JB |
5022 | } |
5023 | ||
647416f9 KC |
5024 | static int |
5025 | i915_max_freq_set(void *data, u64 val) | |
358733e9 | 5026 | { |
36cdd013 | 5027 | struct drm_i915_private *dev_priv = data; |
bc4d91f6 | 5028 | u32 hw_max, hw_min; |
647416f9 | 5029 | int ret; |
004777cb | 5030 | |
36cdd013 | 5031 | if (INTEL_GEN(dev_priv) < 6) |
004777cb | 5032 | return -ENODEV; |
358733e9 | 5033 | |
647416f9 | 5034 | DRM_DEBUG_DRIVER("Manually setting max freq to %llu\n", val); |
358733e9 | 5035 | |
4fc688ce | 5036 | ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock); |
004777cb DV |
5037 | if (ret) |
5038 | return ret; | |
5039 | ||
358733e9 JB |
5040 | /* |
5041 | * Turbo will still be enabled, but won't go above the set value. | |
5042 | */ | |
bc4d91f6 | 5043 | val = intel_freq_opcode(dev_priv, val); |
dd0a1aa1 | 5044 | |
bc4d91f6 AG |
5045 | hw_max = dev_priv->rps.max_freq; |
5046 | hw_min = dev_priv->rps.min_freq; | |
dd0a1aa1 | 5047 | |
b39fb297 | 5048 | if (val < hw_min || val > hw_max || val < dev_priv->rps.min_freq_softlimit) { |
dd0a1aa1 JM |
5049 | mutex_unlock(&dev_priv->rps.hw_lock); |
5050 | return -EINVAL; | |
0a073b84 JB |
5051 | } |
5052 | ||
b39fb297 | 5053 | dev_priv->rps.max_freq_softlimit = val; |
dd0a1aa1 | 5054 | |
dc97997a | 5055 | intel_set_rps(dev_priv, val); |
dd0a1aa1 | 5056 | |
4fc688ce | 5057 | mutex_unlock(&dev_priv->rps.hw_lock); |
358733e9 | 5058 | |
647416f9 | 5059 | return 0; |
358733e9 JB |
5060 | } |
5061 | ||
647416f9 KC |
5062 | DEFINE_SIMPLE_ATTRIBUTE(i915_max_freq_fops, |
5063 | i915_max_freq_get, i915_max_freq_set, | |
3a3b4f98 | 5064 | "%llu\n"); |
358733e9 | 5065 | |
647416f9 KC |
5066 | static int |
5067 | i915_min_freq_get(void *data, u64 *val) | |
1523c310 | 5068 | { |
36cdd013 | 5069 | struct drm_i915_private *dev_priv = data; |
004777cb | 5070 | |
62e1baa1 | 5071 | if (INTEL_GEN(dev_priv) < 6) |
004777cb DV |
5072 | return -ENODEV; |
5073 | ||
7c59a9c1 | 5074 | *val = intel_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit); |
647416f9 | 5075 | return 0; |
1523c310 JB |
5076 | } |
5077 | ||
647416f9 KC |
5078 | static int |
5079 | i915_min_freq_set(void *data, u64 val) | |
1523c310 | 5080 | { |
36cdd013 | 5081 | struct drm_i915_private *dev_priv = data; |
bc4d91f6 | 5082 | u32 hw_max, hw_min; |
647416f9 | 5083 | int ret; |
004777cb | 5084 | |
62e1baa1 | 5085 | if (INTEL_GEN(dev_priv) < 6) |
004777cb | 5086 | return -ENODEV; |
1523c310 | 5087 | |
647416f9 | 5088 | DRM_DEBUG_DRIVER("Manually setting min freq to %llu\n", val); |
1523c310 | 5089 | |
4fc688ce | 5090 | ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock); |
004777cb DV |
5091 | if (ret) |
5092 | return ret; | |
5093 | ||
1523c310 JB |
5094 | /* |
5095 | * Turbo will still be enabled, but won't go below the set value. | |
5096 | */ | |
bc4d91f6 | 5097 | val = intel_freq_opcode(dev_priv, val); |
dd0a1aa1 | 5098 | |
bc4d91f6 AG |
5099 | hw_max = dev_priv->rps.max_freq; |
5100 | hw_min = dev_priv->rps.min_freq; | |
dd0a1aa1 | 5101 | |
36cdd013 DW |
5102 | if (val < hw_min || |
5103 | val > hw_max || val > dev_priv->rps.max_freq_softlimit) { | |
dd0a1aa1 JM |
5104 | mutex_unlock(&dev_priv->rps.hw_lock); |
5105 | return -EINVAL; | |
0a073b84 | 5106 | } |
dd0a1aa1 | 5107 | |
b39fb297 | 5108 | dev_priv->rps.min_freq_softlimit = val; |
dd0a1aa1 | 5109 | |
dc97997a | 5110 | intel_set_rps(dev_priv, val); |
dd0a1aa1 | 5111 | |
4fc688ce | 5112 | mutex_unlock(&dev_priv->rps.hw_lock); |
1523c310 | 5113 | |
647416f9 | 5114 | return 0; |
1523c310 JB |
5115 | } |
5116 | ||
647416f9 KC |
5117 | DEFINE_SIMPLE_ATTRIBUTE(i915_min_freq_fops, |
5118 | i915_min_freq_get, i915_min_freq_set, | |
3a3b4f98 | 5119 | "%llu\n"); |
1523c310 | 5120 | |
647416f9 KC |
5121 | static int |
5122 | i915_cache_sharing_get(void *data, u64 *val) | |
07b7ddd9 | 5123 | { |
36cdd013 | 5124 | struct drm_i915_private *dev_priv = data; |
07b7ddd9 | 5125 | u32 snpcr; |
07b7ddd9 | 5126 | |
36cdd013 | 5127 | if (!(IS_GEN6(dev_priv) || IS_GEN7(dev_priv))) |
004777cb DV |
5128 | return -ENODEV; |
5129 | ||
c8c8fb33 | 5130 | intel_runtime_pm_get(dev_priv); |
22bcfc6a | 5131 | |
07b7ddd9 | 5132 | snpcr = I915_READ(GEN6_MBCUNIT_SNPCR); |
c8c8fb33 PZ |
5133 | |
5134 | intel_runtime_pm_put(dev_priv); | |
07b7ddd9 | 5135 | |
647416f9 | 5136 | *val = (snpcr & GEN6_MBC_SNPCR_MASK) >> GEN6_MBC_SNPCR_SHIFT; |
07b7ddd9 | 5137 | |
647416f9 | 5138 | return 0; |
07b7ddd9 JB |
5139 | } |
5140 | ||
647416f9 KC |
5141 | static int |
5142 | i915_cache_sharing_set(void *data, u64 val) | |
07b7ddd9 | 5143 | { |
36cdd013 | 5144 | struct drm_i915_private *dev_priv = data; |
07b7ddd9 | 5145 | u32 snpcr; |
07b7ddd9 | 5146 | |
36cdd013 | 5147 | if (!(IS_GEN6(dev_priv) || IS_GEN7(dev_priv))) |
004777cb DV |
5148 | return -ENODEV; |
5149 | ||
647416f9 | 5150 | if (val > 3) |
07b7ddd9 JB |
5151 | return -EINVAL; |
5152 | ||
c8c8fb33 | 5153 | intel_runtime_pm_get(dev_priv); |
647416f9 | 5154 | DRM_DEBUG_DRIVER("Manually setting uncore sharing to %llu\n", val); |
07b7ddd9 JB |
5155 | |
5156 | /* Update the cache sharing policy here as well */ | |
5157 | snpcr = I915_READ(GEN6_MBCUNIT_SNPCR); | |
5158 | snpcr &= ~GEN6_MBC_SNPCR_MASK; | |
5159 | snpcr |= (val << GEN6_MBC_SNPCR_SHIFT); | |
5160 | I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr); | |
5161 | ||
c8c8fb33 | 5162 | intel_runtime_pm_put(dev_priv); |
647416f9 | 5163 | return 0; |
07b7ddd9 JB |
5164 | } |
5165 | ||
647416f9 KC |
5166 | DEFINE_SIMPLE_ATTRIBUTE(i915_cache_sharing_fops, |
5167 | i915_cache_sharing_get, i915_cache_sharing_set, | |
5168 | "%llu\n"); | |
07b7ddd9 | 5169 | |
36cdd013 | 5170 | static void cherryview_sseu_device_status(struct drm_i915_private *dev_priv, |
915490d5 | 5171 | struct sseu_dev_info *sseu) |
5d39525a | 5172 | { |
0a0b457f | 5173 | int ss_max = 2; |
5d39525a JM |
5174 | int ss; |
5175 | u32 sig1[ss_max], sig2[ss_max]; | |
5176 | ||
5177 | sig1[0] = I915_READ(CHV_POWER_SS0_SIG1); | |
5178 | sig1[1] = I915_READ(CHV_POWER_SS1_SIG1); | |
5179 | sig2[0] = I915_READ(CHV_POWER_SS0_SIG2); | |
5180 | sig2[1] = I915_READ(CHV_POWER_SS1_SIG2); | |
5181 | ||
5182 | for (ss = 0; ss < ss_max; ss++) { | |
5183 | unsigned int eu_cnt; | |
5184 | ||
5185 | if (sig1[ss] & CHV_SS_PG_ENABLE) | |
5186 | /* skip disabled subslice */ | |
5187 | continue; | |
5188 | ||
f08a0c92 | 5189 | sseu->slice_mask = BIT(0); |
57ec171e | 5190 | sseu->subslice_mask |= BIT(ss); |
5d39525a JM |
5191 | eu_cnt = ((sig1[ss] & CHV_EU08_PG_ENABLE) ? 0 : 2) + |
5192 | ((sig1[ss] & CHV_EU19_PG_ENABLE) ? 0 : 2) + | |
5193 | ((sig1[ss] & CHV_EU210_PG_ENABLE) ? 0 : 2) + | |
5194 | ((sig2[ss] & CHV_EU311_PG_ENABLE) ? 0 : 2); | |
915490d5 ID |
5195 | sseu->eu_total += eu_cnt; |
5196 | sseu->eu_per_subslice = max_t(unsigned int, | |
5197 | sseu->eu_per_subslice, eu_cnt); | |
5d39525a | 5198 | } |
5d39525a JM |
5199 | } |
5200 | ||
36cdd013 | 5201 | static void gen9_sseu_device_status(struct drm_i915_private *dev_priv, |
915490d5 | 5202 | struct sseu_dev_info *sseu) |
5d39525a | 5203 | { |
1c046bc1 | 5204 | int s_max = 3, ss_max = 4; |
5d39525a JM |
5205 | int s, ss; |
5206 | u32 s_reg[s_max], eu_reg[2*s_max], eu_mask[2]; | |
5207 | ||
1c046bc1 | 5208 | /* BXT has a single slice and at most 3 subslices. */ |
36cdd013 | 5209 | if (IS_BROXTON(dev_priv)) { |
1c046bc1 JM |
5210 | s_max = 1; |
5211 | ss_max = 3; | |
5212 | } | |
5213 | ||
5214 | for (s = 0; s < s_max; s++) { | |
5215 | s_reg[s] = I915_READ(GEN9_SLICE_PGCTL_ACK(s)); | |
5216 | eu_reg[2*s] = I915_READ(GEN9_SS01_EU_PGCTL_ACK(s)); | |
5217 | eu_reg[2*s + 1] = I915_READ(GEN9_SS23_EU_PGCTL_ACK(s)); | |
5218 | } | |
5219 | ||
5d39525a JM |
5220 | eu_mask[0] = GEN9_PGCTL_SSA_EU08_ACK | |
5221 | GEN9_PGCTL_SSA_EU19_ACK | | |
5222 | GEN9_PGCTL_SSA_EU210_ACK | | |
5223 | GEN9_PGCTL_SSA_EU311_ACK; | |
5224 | eu_mask[1] = GEN9_PGCTL_SSB_EU08_ACK | | |
5225 | GEN9_PGCTL_SSB_EU19_ACK | | |
5226 | GEN9_PGCTL_SSB_EU210_ACK | | |
5227 | GEN9_PGCTL_SSB_EU311_ACK; | |
5228 | ||
5229 | for (s = 0; s < s_max; s++) { | |
5230 | if ((s_reg[s] & GEN9_PGCTL_SLICE_ACK) == 0) | |
5231 | /* skip disabled slice */ | |
5232 | continue; | |
5233 | ||
f08a0c92 | 5234 | sseu->slice_mask |= BIT(s); |
1c046bc1 | 5235 | |
36cdd013 | 5236 | if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) |
57ec171e ID |
5237 | sseu->subslice_mask = |
5238 | INTEL_INFO(dev_priv)->sseu.subslice_mask; | |
1c046bc1 | 5239 | |
5d39525a JM |
5240 | for (ss = 0; ss < ss_max; ss++) { |
5241 | unsigned int eu_cnt; | |
5242 | ||
57ec171e ID |
5243 | if (IS_BROXTON(dev_priv)) { |
5244 | if (!(s_reg[s] & (GEN9_PGCTL_SS_ACK(ss)))) | |
5245 | /* skip disabled subslice */ | |
5246 | continue; | |
1c046bc1 | 5247 | |
57ec171e ID |
5248 | sseu->subslice_mask |= BIT(ss); |
5249 | } | |
1c046bc1 | 5250 | |
5d39525a JM |
5251 | eu_cnt = 2 * hweight32(eu_reg[2*s + ss/2] & |
5252 | eu_mask[ss%2]); | |
915490d5 ID |
5253 | sseu->eu_total += eu_cnt; |
5254 | sseu->eu_per_subslice = max_t(unsigned int, | |
5255 | sseu->eu_per_subslice, | |
5256 | eu_cnt); | |
5d39525a JM |
5257 | } |
5258 | } | |
5259 | } | |
5260 | ||
36cdd013 | 5261 | static void broadwell_sseu_device_status(struct drm_i915_private *dev_priv, |
915490d5 | 5262 | struct sseu_dev_info *sseu) |
91bedd34 | 5263 | { |
91bedd34 | 5264 | u32 slice_info = I915_READ(GEN8_GT_SLICE_INFO); |
36cdd013 | 5265 | int s; |
91bedd34 | 5266 | |
f08a0c92 | 5267 | sseu->slice_mask = slice_info & GEN8_LSLICESTAT_MASK; |
91bedd34 | 5268 | |
f08a0c92 | 5269 | if (sseu->slice_mask) { |
57ec171e | 5270 | sseu->subslice_mask = INTEL_INFO(dev_priv)->sseu.subslice_mask; |
43b67998 ID |
5271 | sseu->eu_per_subslice = |
5272 | INTEL_INFO(dev_priv)->sseu.eu_per_subslice; | |
57ec171e ID |
5273 | sseu->eu_total = sseu->eu_per_subslice * |
5274 | sseu_subslice_total(sseu); | |
91bedd34 ŁD |
5275 | |
5276 | /* subtract fused off EU(s) from enabled slice(s) */ | |
795b38b3 | 5277 | for (s = 0; s < fls(sseu->slice_mask); s++) { |
43b67998 ID |
5278 | u8 subslice_7eu = |
5279 | INTEL_INFO(dev_priv)->sseu.subslice_7eu[s]; | |
91bedd34 | 5280 | |
915490d5 | 5281 | sseu->eu_total -= hweight8(subslice_7eu); |
91bedd34 ŁD |
5282 | } |
5283 | } | |
5284 | } | |
5285 | ||
615d8908 ID |
5286 | static void i915_print_sseu_info(struct seq_file *m, bool is_available_info, |
5287 | const struct sseu_dev_info *sseu) | |
5288 | { | |
5289 | struct drm_i915_private *dev_priv = node_to_i915(m->private); | |
5290 | const char *type = is_available_info ? "Available" : "Enabled"; | |
5291 | ||
c67ba538 ID |
5292 | seq_printf(m, " %s Slice Mask: %04x\n", type, |
5293 | sseu->slice_mask); | |
615d8908 | 5294 | seq_printf(m, " %s Slice Total: %u\n", type, |
f08a0c92 | 5295 | hweight8(sseu->slice_mask)); |
615d8908 | 5296 | seq_printf(m, " %s Subslice Total: %u\n", type, |
57ec171e | 5297 | sseu_subslice_total(sseu)); |
c67ba538 ID |
5298 | seq_printf(m, " %s Subslice Mask: %04x\n", type, |
5299 | sseu->subslice_mask); | |
615d8908 | 5300 | seq_printf(m, " %s Subslice Per Slice: %u\n", type, |
57ec171e | 5301 | hweight8(sseu->subslice_mask)); |
615d8908 ID |
5302 | seq_printf(m, " %s EU Total: %u\n", type, |
5303 | sseu->eu_total); | |
5304 | seq_printf(m, " %s EU Per Subslice: %u\n", type, | |
5305 | sseu->eu_per_subslice); | |
5306 | ||
5307 | if (!is_available_info) | |
5308 | return; | |
5309 | ||
5310 | seq_printf(m, " Has Pooled EU: %s\n", yesno(HAS_POOLED_EU(dev_priv))); | |
5311 | if (HAS_POOLED_EU(dev_priv)) | |
5312 | seq_printf(m, " Min EU in pool: %u\n", sseu->min_eu_in_pool); | |
5313 | ||
5314 | seq_printf(m, " Has Slice Power Gating: %s\n", | |
5315 | yesno(sseu->has_slice_pg)); | |
5316 | seq_printf(m, " Has Subslice Power Gating: %s\n", | |
5317 | yesno(sseu->has_subslice_pg)); | |
5318 | seq_printf(m, " Has EU Power Gating: %s\n", | |
5319 | yesno(sseu->has_eu_pg)); | |
5320 | } | |
5321 | ||
3873218f JM |
5322 | static int i915_sseu_status(struct seq_file *m, void *unused) |
5323 | { | |
36cdd013 | 5324 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
915490d5 | 5325 | struct sseu_dev_info sseu; |
3873218f | 5326 | |
36cdd013 | 5327 | if (INTEL_GEN(dev_priv) < 8) |
3873218f JM |
5328 | return -ENODEV; |
5329 | ||
5330 | seq_puts(m, "SSEU Device Info\n"); | |
615d8908 | 5331 | i915_print_sseu_info(m, true, &INTEL_INFO(dev_priv)->sseu); |
3873218f | 5332 | |
7f992aba | 5333 | seq_puts(m, "SSEU Device Status\n"); |
915490d5 | 5334 | memset(&sseu, 0, sizeof(sseu)); |
238010ed DW |
5335 | |
5336 | intel_runtime_pm_get(dev_priv); | |
5337 | ||
36cdd013 | 5338 | if (IS_CHERRYVIEW(dev_priv)) { |
915490d5 | 5339 | cherryview_sseu_device_status(dev_priv, &sseu); |
36cdd013 | 5340 | } else if (IS_BROADWELL(dev_priv)) { |
915490d5 | 5341 | broadwell_sseu_device_status(dev_priv, &sseu); |
36cdd013 | 5342 | } else if (INTEL_GEN(dev_priv) >= 9) { |
915490d5 | 5343 | gen9_sseu_device_status(dev_priv, &sseu); |
7f992aba | 5344 | } |
238010ed DW |
5345 | |
5346 | intel_runtime_pm_put(dev_priv); | |
5347 | ||
615d8908 | 5348 | i915_print_sseu_info(m, false, &sseu); |
7f992aba | 5349 | |
3873218f JM |
5350 | return 0; |
5351 | } | |
5352 | ||
6d794d42 BW |
5353 | static int i915_forcewake_open(struct inode *inode, struct file *file) |
5354 | { | |
36cdd013 | 5355 | struct drm_i915_private *dev_priv = inode->i_private; |
6d794d42 | 5356 | |
36cdd013 | 5357 | if (INTEL_GEN(dev_priv) < 6) |
6d794d42 BW |
5358 | return 0; |
5359 | ||
6daccb0b | 5360 | intel_runtime_pm_get(dev_priv); |
59bad947 | 5361 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); |
6d794d42 BW |
5362 | |
5363 | return 0; | |
5364 | } | |
5365 | ||
c43b5634 | 5366 | static int i915_forcewake_release(struct inode *inode, struct file *file) |
6d794d42 | 5367 | { |
36cdd013 | 5368 | struct drm_i915_private *dev_priv = inode->i_private; |
6d794d42 | 5369 | |
36cdd013 | 5370 | if (INTEL_GEN(dev_priv) < 6) |
6d794d42 BW |
5371 | return 0; |
5372 | ||
59bad947 | 5373 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); |
6daccb0b | 5374 | intel_runtime_pm_put(dev_priv); |
6d794d42 BW |
5375 | |
5376 | return 0; | |
5377 | } | |
5378 | ||
5379 | static const struct file_operations i915_forcewake_fops = { | |
5380 | .owner = THIS_MODULE, | |
5381 | .open = i915_forcewake_open, | |
5382 | .release = i915_forcewake_release, | |
5383 | }; | |
5384 | ||
5385 | static int i915_forcewake_create(struct dentry *root, struct drm_minor *minor) | |
5386 | { | |
6d794d42 BW |
5387 | struct dentry *ent; |
5388 | ||
5389 | ent = debugfs_create_file("i915_forcewake_user", | |
8eb57294 | 5390 | S_IRUSR, |
36cdd013 | 5391 | root, to_i915(minor->dev), |
6d794d42 | 5392 | &i915_forcewake_fops); |
f3c5fe97 WY |
5393 | if (!ent) |
5394 | return -ENOMEM; | |
6d794d42 | 5395 | |
8eb57294 | 5396 | return drm_add_fake_info_node(minor, ent, &i915_forcewake_fops); |
6d794d42 BW |
5397 | } |
5398 | ||
6a9c308d DV |
5399 | static int i915_debugfs_create(struct dentry *root, |
5400 | struct drm_minor *minor, | |
5401 | const char *name, | |
5402 | const struct file_operations *fops) | |
07b7ddd9 | 5403 | { |
07b7ddd9 JB |
5404 | struct dentry *ent; |
5405 | ||
6a9c308d | 5406 | ent = debugfs_create_file(name, |
07b7ddd9 | 5407 | S_IRUGO | S_IWUSR, |
36cdd013 | 5408 | root, to_i915(minor->dev), |
6a9c308d | 5409 | fops); |
f3c5fe97 WY |
5410 | if (!ent) |
5411 | return -ENOMEM; | |
07b7ddd9 | 5412 | |
6a9c308d | 5413 | return drm_add_fake_info_node(minor, ent, fops); |
07b7ddd9 JB |
5414 | } |
5415 | ||
06c5bf8c | 5416 | static const struct drm_info_list i915_debugfs_list[] = { |
311bd68e | 5417 | {"i915_capabilities", i915_capabilities, 0}, |
73aa808f | 5418 | {"i915_gem_objects", i915_gem_object_info, 0}, |
08c18323 | 5419 | {"i915_gem_gtt", i915_gem_gtt_info, 0}, |
6da84829 | 5420 | {"i915_gem_pin_display", i915_gem_gtt_info, 0, (void *)1}, |
6d2b8885 | 5421 | {"i915_gem_stolen", i915_gem_stolen_list_info }, |
4e5359cd | 5422 | {"i915_gem_pageflip", i915_gem_pageflip_info, 0}, |
2017263e BG |
5423 | {"i915_gem_request", i915_gem_request_info, 0}, |
5424 | {"i915_gem_seqno", i915_gem_seqno_info, 0}, | |
a6172a80 | 5425 | {"i915_gem_fence_regs", i915_gem_fence_regs_info, 0}, |
2017263e | 5426 | {"i915_gem_interrupt", i915_interrupt_info, 0}, |
1ec14ad3 CW |
5427 | {"i915_gem_hws", i915_hws_info, 0, (void *)RCS}, |
5428 | {"i915_gem_hws_blt", i915_hws_info, 0, (void *)BCS}, | |
5429 | {"i915_gem_hws_bsd", i915_hws_info, 0, (void *)VCS}, | |
9010ebfd | 5430 | {"i915_gem_hws_vebox", i915_hws_info, 0, (void *)VECS}, |
493018dc | 5431 | {"i915_gem_batch_pool", i915_gem_batch_pool_info, 0}, |
8b417c26 | 5432 | {"i915_guc_info", i915_guc_info, 0}, |
fdf5d357 | 5433 | {"i915_guc_load_status", i915_guc_load_status_info, 0}, |
4c7e77fc | 5434 | {"i915_guc_log_dump", i915_guc_log_dump, 0}, |
adb4bd12 | 5435 | {"i915_frequency_info", i915_frequency_info, 0}, |
f654449a | 5436 | {"i915_hangcheck_info", i915_hangcheck_info, 0}, |
f97108d1 | 5437 | {"i915_drpc_info", i915_drpc_info, 0}, |
7648fa99 | 5438 | {"i915_emon_status", i915_emon_status, 0}, |
23b2f8bb | 5439 | {"i915_ring_freq_table", i915_ring_freq_table, 0}, |
9a851789 | 5440 | {"i915_frontbuffer_tracking", i915_frontbuffer_tracking, 0}, |
b5e50c3f | 5441 | {"i915_fbc_status", i915_fbc_status, 0}, |
92d44621 | 5442 | {"i915_ips_status", i915_ips_status, 0}, |
4a9bef37 | 5443 | {"i915_sr_status", i915_sr_status, 0}, |
44834a67 | 5444 | {"i915_opregion", i915_opregion, 0}, |
ada8f955 | 5445 | {"i915_vbt", i915_vbt, 0}, |
37811fcc | 5446 | {"i915_gem_framebuffer", i915_gem_framebuffer_info, 0}, |
e76d3630 | 5447 | {"i915_context_status", i915_context_status, 0}, |
c0ab1ae9 | 5448 | {"i915_dump_lrc", i915_dump_lrc, 0}, |
f65367b5 | 5449 | {"i915_forcewake_domains", i915_forcewake_domains, 0}, |
ea16a3cd | 5450 | {"i915_swizzle_info", i915_swizzle_info, 0}, |
3cf17fc5 | 5451 | {"i915_ppgtt_info", i915_ppgtt_info, 0}, |
63573eb7 | 5452 | {"i915_llc", i915_llc, 0}, |
e91fd8c6 | 5453 | {"i915_edp_psr_status", i915_edp_psr_status, 0}, |
d2e216d0 | 5454 | {"i915_sink_crc_eDP1", i915_sink_crc, 0}, |
ec013e7f | 5455 | {"i915_energy_uJ", i915_energy_uJ, 0}, |
6455c870 | 5456 | {"i915_runtime_pm_status", i915_runtime_pm_status, 0}, |
1da51581 | 5457 | {"i915_power_domain_info", i915_power_domain_info, 0}, |
b7cec66d | 5458 | {"i915_dmc_info", i915_dmc_info, 0}, |
53f5e3ca | 5459 | {"i915_display_info", i915_display_info, 0}, |
1b36595f | 5460 | {"i915_engine_info", i915_engine_info, 0}, |
e04934cf | 5461 | {"i915_semaphore_status", i915_semaphore_status, 0}, |
728e29d7 | 5462 | {"i915_shared_dplls_info", i915_shared_dplls_info, 0}, |
11bed958 | 5463 | {"i915_dp_mst_info", i915_dp_mst_info, 0}, |
1ed1ef9d | 5464 | {"i915_wa_registers", i915_wa_registers, 0}, |
c5511e44 | 5465 | {"i915_ddb_info", i915_ddb_info, 0}, |
3873218f | 5466 | {"i915_sseu_status", i915_sseu_status, 0}, |
a54746e3 | 5467 | {"i915_drrs_status", i915_drrs_status, 0}, |
1854d5ca | 5468 | {"i915_rps_boost_info", i915_rps_boost_info, 0}, |
2017263e | 5469 | }; |
27c202ad | 5470 | #define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list) |
2017263e | 5471 | |
06c5bf8c | 5472 | static const struct i915_debugfs_files { |
34b9674c DV |
5473 | const char *name; |
5474 | const struct file_operations *fops; | |
5475 | } i915_debugfs_files[] = { | |
5476 | {"i915_wedged", &i915_wedged_fops}, | |
5477 | {"i915_max_freq", &i915_max_freq_fops}, | |
5478 | {"i915_min_freq", &i915_min_freq_fops}, | |
5479 | {"i915_cache_sharing", &i915_cache_sharing_fops}, | |
094f9a54 CW |
5480 | {"i915_ring_missed_irq", &i915_ring_missed_irq_fops}, |
5481 | {"i915_ring_test_irq", &i915_ring_test_irq_fops}, | |
34b9674c | 5482 | {"i915_gem_drop_caches", &i915_drop_caches_fops}, |
98a2f411 | 5483 | #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR) |
34b9674c | 5484 | {"i915_error_state", &i915_error_state_fops}, |
98a2f411 | 5485 | #endif |
34b9674c | 5486 | {"i915_next_seqno", &i915_next_seqno_fops}, |
bd9db02f | 5487 | {"i915_display_crc_ctl", &i915_display_crc_ctl_fops}, |
369a1342 VS |
5488 | {"i915_pri_wm_latency", &i915_pri_wm_latency_fops}, |
5489 | {"i915_spr_wm_latency", &i915_spr_wm_latency_fops}, | |
5490 | {"i915_cur_wm_latency", &i915_cur_wm_latency_fops}, | |
da46f936 | 5491 | {"i915_fbc_false_color", &i915_fbc_fc_fops}, |
eb3394fa TP |
5492 | {"i915_dp_test_data", &i915_displayport_test_data_fops}, |
5493 | {"i915_dp_test_type", &i915_displayport_test_type_fops}, | |
685534ef SAK |
5494 | {"i915_dp_test_active", &i915_displayport_test_active_fops}, |
5495 | {"i915_guc_log_control", &i915_guc_log_control_fops} | |
34b9674c DV |
5496 | }; |
5497 | ||
36cdd013 | 5498 | void intel_display_crc_init(struct drm_i915_private *dev_priv) |
07144428 | 5499 | { |
b378360e | 5500 | enum pipe pipe; |
07144428 | 5501 | |
055e393f | 5502 | for_each_pipe(dev_priv, pipe) { |
b378360e | 5503 | struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe]; |
07144428 | 5504 | |
d538bbdf DL |
5505 | pipe_crc->opened = false; |
5506 | spin_lock_init(&pipe_crc->lock); | |
07144428 DL |
5507 | init_waitqueue_head(&pipe_crc->wq); |
5508 | } | |
5509 | } | |
5510 | ||
1dac891c | 5511 | int i915_debugfs_register(struct drm_i915_private *dev_priv) |
2017263e | 5512 | { |
91c8a326 | 5513 | struct drm_minor *minor = dev_priv->drm.primary; |
34b9674c | 5514 | int ret, i; |
f3cd474b | 5515 | |
6d794d42 | 5516 | ret = i915_forcewake_create(minor->debugfs_root, minor); |
358733e9 JB |
5517 | if (ret) |
5518 | return ret; | |
6a9c308d | 5519 | |
07144428 DL |
5520 | for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) { |
5521 | ret = i915_pipe_crc_create(minor->debugfs_root, minor, i); | |
5522 | if (ret) | |
5523 | return ret; | |
5524 | } | |
5525 | ||
34b9674c DV |
5526 | for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) { |
5527 | ret = i915_debugfs_create(minor->debugfs_root, minor, | |
5528 | i915_debugfs_files[i].name, | |
5529 | i915_debugfs_files[i].fops); | |
5530 | if (ret) | |
5531 | return ret; | |
5532 | } | |
40633219 | 5533 | |
27c202ad BG |
5534 | return drm_debugfs_create_files(i915_debugfs_list, |
5535 | I915_DEBUGFS_ENTRIES, | |
2017263e BG |
5536 | minor->debugfs_root, minor); |
5537 | } | |
5538 | ||
1dac891c | 5539 | void i915_debugfs_unregister(struct drm_i915_private *dev_priv) |
2017263e | 5540 | { |
91c8a326 | 5541 | struct drm_minor *minor = dev_priv->drm.primary; |
34b9674c DV |
5542 | int i; |
5543 | ||
27c202ad BG |
5544 | drm_debugfs_remove_files(i915_debugfs_list, |
5545 | I915_DEBUGFS_ENTRIES, minor); | |
07144428 | 5546 | |
36cdd013 | 5547 | drm_debugfs_remove_files((struct drm_info_list *)&i915_forcewake_fops, |
6d794d42 | 5548 | 1, minor); |
07144428 | 5549 | |
e309a997 | 5550 | for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) { |
07144428 DL |
5551 | struct drm_info_list *info_list = |
5552 | (struct drm_info_list *)&i915_pipe_crc_data[i]; | |
5553 | ||
5554 | drm_debugfs_remove_files(info_list, 1, minor); | |
5555 | } | |
5556 | ||
34b9674c DV |
5557 | for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) { |
5558 | struct drm_info_list *info_list = | |
36cdd013 | 5559 | (struct drm_info_list *)i915_debugfs_files[i].fops; |
34b9674c DV |
5560 | |
5561 | drm_debugfs_remove_files(info_list, 1, minor); | |
5562 | } | |
2017263e | 5563 | } |
aa7471d2 JN |
5564 | |
5565 | struct dpcd_block { | |
5566 | /* DPCD dump start address. */ | |
5567 | unsigned int offset; | |
5568 | /* DPCD dump end address, inclusive. If unset, .size will be used. */ | |
5569 | unsigned int end; | |
5570 | /* DPCD dump size. Used if .end is unset. If unset, defaults to 1. */ | |
5571 | size_t size; | |
5572 | /* Only valid for eDP. */ | |
5573 | bool edp; | |
5574 | }; | |
5575 | ||
5576 | static const struct dpcd_block i915_dpcd_debug[] = { | |
5577 | { .offset = DP_DPCD_REV, .size = DP_RECEIVER_CAP_SIZE }, | |
5578 | { .offset = DP_PSR_SUPPORT, .end = DP_PSR_CAPS }, | |
5579 | { .offset = DP_DOWNSTREAM_PORT_0, .size = 16 }, | |
5580 | { .offset = DP_LINK_BW_SET, .end = DP_EDP_CONFIGURATION_SET }, | |
5581 | { .offset = DP_SINK_COUNT, .end = DP_ADJUST_REQUEST_LANE2_3 }, | |
5582 | { .offset = DP_SET_POWER }, | |
5583 | { .offset = DP_EDP_DPCD_REV }, | |
5584 | { .offset = DP_EDP_GENERAL_CAP_1, .end = DP_EDP_GENERAL_CAP_3 }, | |
5585 | { .offset = DP_EDP_DISPLAY_CONTROL_REGISTER, .end = DP_EDP_BACKLIGHT_FREQ_CAP_MAX_LSB }, | |
5586 | { .offset = DP_EDP_DBC_MINIMUM_BRIGHTNESS_SET, .end = DP_EDP_DBC_MAXIMUM_BRIGHTNESS_SET }, | |
5587 | }; | |
5588 | ||
5589 | static int i915_dpcd_show(struct seq_file *m, void *data) | |
5590 | { | |
5591 | struct drm_connector *connector = m->private; | |
5592 | struct intel_dp *intel_dp = | |
5593 | enc_to_intel_dp(&intel_attached_encoder(connector)->base); | |
5594 | uint8_t buf[16]; | |
5595 | ssize_t err; | |
5596 | int i; | |
5597 | ||
5c1a8875 MK |
5598 | if (connector->status != connector_status_connected) |
5599 | return -ENODEV; | |
5600 | ||
aa7471d2 JN |
5601 | for (i = 0; i < ARRAY_SIZE(i915_dpcd_debug); i++) { |
5602 | const struct dpcd_block *b = &i915_dpcd_debug[i]; | |
5603 | size_t size = b->end ? b->end - b->offset + 1 : (b->size ?: 1); | |
5604 | ||
5605 | if (b->edp && | |
5606 | connector->connector_type != DRM_MODE_CONNECTOR_eDP) | |
5607 | continue; | |
5608 | ||
5609 | /* low tech for now */ | |
5610 | if (WARN_ON(size > sizeof(buf))) | |
5611 | continue; | |
5612 | ||
5613 | err = drm_dp_dpcd_read(&intel_dp->aux, b->offset, buf, size); | |
5614 | if (err <= 0) { | |
5615 | DRM_ERROR("dpcd read (%zu bytes at %u) failed (%zd)\n", | |
5616 | size, b->offset, err); | |
5617 | continue; | |
5618 | } | |
5619 | ||
5620 | seq_printf(m, "%04x: %*ph\n", b->offset, (int) size, buf); | |
b3f9d7d7 | 5621 | } |
aa7471d2 JN |
5622 | |
5623 | return 0; | |
5624 | } | |
5625 | ||
5626 | static int i915_dpcd_open(struct inode *inode, struct file *file) | |
5627 | { | |
5628 | return single_open(file, i915_dpcd_show, inode->i_private); | |
5629 | } | |
5630 | ||
5631 | static const struct file_operations i915_dpcd_fops = { | |
5632 | .owner = THIS_MODULE, | |
5633 | .open = i915_dpcd_open, | |
5634 | .read = seq_read, | |
5635 | .llseek = seq_lseek, | |
5636 | .release = single_release, | |
5637 | }; | |
5638 | ||
ecbd6781 DW |
5639 | static int i915_panel_show(struct seq_file *m, void *data) |
5640 | { | |
5641 | struct drm_connector *connector = m->private; | |
5642 | struct intel_dp *intel_dp = | |
5643 | enc_to_intel_dp(&intel_attached_encoder(connector)->base); | |
5644 | ||
5645 | if (connector->status != connector_status_connected) | |
5646 | return -ENODEV; | |
5647 | ||
5648 | seq_printf(m, "Panel power up delay: %d\n", | |
5649 | intel_dp->panel_power_up_delay); | |
5650 | seq_printf(m, "Panel power down delay: %d\n", | |
5651 | intel_dp->panel_power_down_delay); | |
5652 | seq_printf(m, "Backlight on delay: %d\n", | |
5653 | intel_dp->backlight_on_delay); | |
5654 | seq_printf(m, "Backlight off delay: %d\n", | |
5655 | intel_dp->backlight_off_delay); | |
5656 | ||
5657 | return 0; | |
5658 | } | |
5659 | ||
5660 | static int i915_panel_open(struct inode *inode, struct file *file) | |
5661 | { | |
5662 | return single_open(file, i915_panel_show, inode->i_private); | |
5663 | } | |
5664 | ||
5665 | static const struct file_operations i915_panel_fops = { | |
5666 | .owner = THIS_MODULE, | |
5667 | .open = i915_panel_open, | |
5668 | .read = seq_read, | |
5669 | .llseek = seq_lseek, | |
5670 | .release = single_release, | |
5671 | }; | |
5672 | ||
aa7471d2 JN |
5673 | /** |
5674 | * i915_debugfs_connector_add - add i915 specific connector debugfs files | |
5675 | * @connector: pointer to a registered drm_connector | |
5676 | * | |
5677 | * Cleanup will be done by drm_connector_unregister() through a call to | |
5678 | * drm_debugfs_connector_remove(). | |
5679 | * | |
5680 | * Returns 0 on success, negative error codes on error. | |
5681 | */ | |
5682 | int i915_debugfs_connector_add(struct drm_connector *connector) | |
5683 | { | |
5684 | struct dentry *root = connector->debugfs_entry; | |
5685 | ||
5686 | /* The connector must have been registered beforehands. */ | |
5687 | if (!root) | |
5688 | return -ENODEV; | |
5689 | ||
5690 | if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort || | |
5691 | connector->connector_type == DRM_MODE_CONNECTOR_eDP) | |
ecbd6781 DW |
5692 | debugfs_create_file("i915_dpcd", S_IRUGO, root, |
5693 | connector, &i915_dpcd_fops); | |
5694 | ||
5695 | if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) | |
5696 | debugfs_create_file("i915_panel_timings", S_IRUGO, root, | |
5697 | connector, &i915_panel_fops); | |
aa7471d2 JN |
5698 | |
5699 | return 0; | |
5700 | } |