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Commit | Line | Data |
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2017263e BG |
1 | /* |
2 | * Copyright © 2008 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | * Keith Packard <keithp@keithp.com> | |
26 | * | |
27 | */ | |
28 | ||
29 | #include <linux/seq_file.h> | |
b2c88f5b | 30 | #include <linux/circ_buf.h> |
926321d5 | 31 | #include <linux/ctype.h> |
f3cd474b | 32 | #include <linux/debugfs.h> |
5a0e3ad6 | 33 | #include <linux/slab.h> |
2d1a8a48 | 34 | #include <linux/export.h> |
6d2b8885 | 35 | #include <linux/list_sort.h> |
ec013e7f | 36 | #include <asm/msr-index.h> |
760285e7 | 37 | #include <drm/drmP.h> |
4e5359cd | 38 | #include "intel_drv.h" |
e5c65260 | 39 | #include "intel_ringbuffer.h" |
760285e7 | 40 | #include <drm/i915_drm.h> |
2017263e BG |
41 | #include "i915_drv.h" |
42 | ||
36cdd013 DW |
43 | static inline struct drm_i915_private *node_to_i915(struct drm_info_node *node) |
44 | { | |
45 | return to_i915(node->minor->dev); | |
46 | } | |
47 | ||
497666d8 DL |
48 | /* As the drm_debugfs_init() routines are called before dev->dev_private is |
49 | * allocated we need to hook into the minor for release. */ | |
50 | static int | |
51 | drm_add_fake_info_node(struct drm_minor *minor, | |
52 | struct dentry *ent, | |
53 | const void *key) | |
54 | { | |
55 | struct drm_info_node *node; | |
56 | ||
57 | node = kmalloc(sizeof(*node), GFP_KERNEL); | |
58 | if (node == NULL) { | |
59 | debugfs_remove(ent); | |
60 | return -ENOMEM; | |
61 | } | |
62 | ||
63 | node->minor = minor; | |
64 | node->dent = ent; | |
36cdd013 | 65 | node->info_ent = (void *)key; |
497666d8 DL |
66 | |
67 | mutex_lock(&minor->debugfs_lock); | |
68 | list_add(&node->list, &minor->debugfs_list); | |
69 | mutex_unlock(&minor->debugfs_lock); | |
70 | ||
71 | return 0; | |
72 | } | |
73 | ||
70d39fe4 CW |
74 | static int i915_capabilities(struct seq_file *m, void *data) |
75 | { | |
36cdd013 DW |
76 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
77 | const struct intel_device_info *info = INTEL_INFO(dev_priv); | |
70d39fe4 | 78 | |
36cdd013 DW |
79 | seq_printf(m, "gen: %d\n", INTEL_GEN(dev_priv)); |
80 | seq_printf(m, "pch: %d\n", INTEL_PCH_TYPE(dev_priv)); | |
79fc46df DL |
81 | #define PRINT_FLAG(x) seq_printf(m, #x ": %s\n", yesno(info->x)) |
82 | #define SEP_SEMICOLON ; | |
83 | DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG, SEP_SEMICOLON); | |
84 | #undef PRINT_FLAG | |
85 | #undef SEP_SEMICOLON | |
70d39fe4 CW |
86 | |
87 | return 0; | |
88 | } | |
2017263e | 89 | |
a7363de7 | 90 | static char get_active_flag(struct drm_i915_gem_object *obj) |
a6172a80 | 91 | { |
573adb39 | 92 | return i915_gem_object_is_active(obj) ? '*' : ' '; |
a6172a80 CW |
93 | } |
94 | ||
a7363de7 | 95 | static char get_pin_flag(struct drm_i915_gem_object *obj) |
be12a86b TU |
96 | { |
97 | return obj->pin_display ? 'p' : ' '; | |
98 | } | |
99 | ||
a7363de7 | 100 | static char get_tiling_flag(struct drm_i915_gem_object *obj) |
a6172a80 | 101 | { |
3e510a8e | 102 | switch (i915_gem_object_get_tiling(obj)) { |
0206e353 | 103 | default: |
be12a86b TU |
104 | case I915_TILING_NONE: return ' '; |
105 | case I915_TILING_X: return 'X'; | |
106 | case I915_TILING_Y: return 'Y'; | |
0206e353 | 107 | } |
a6172a80 CW |
108 | } |
109 | ||
a7363de7 | 110 | static char get_global_flag(struct drm_i915_gem_object *obj) |
be12a86b | 111 | { |
058d88c4 | 112 | return i915_gem_object_to_ggtt(obj, NULL) ? 'g' : ' '; |
be12a86b TU |
113 | } |
114 | ||
a7363de7 | 115 | static char get_pin_mapped_flag(struct drm_i915_gem_object *obj) |
1d693bcc | 116 | { |
be12a86b | 117 | return obj->mapping ? 'M' : ' '; |
1d693bcc BW |
118 | } |
119 | ||
ca1543be TU |
120 | static u64 i915_gem_obj_total_ggtt_size(struct drm_i915_gem_object *obj) |
121 | { | |
122 | u64 size = 0; | |
123 | struct i915_vma *vma; | |
124 | ||
1c7f4bca | 125 | list_for_each_entry(vma, &obj->vma_list, obj_link) { |
3272db53 | 126 | if (i915_vma_is_ggtt(vma) && drm_mm_node_allocated(&vma->node)) |
ca1543be TU |
127 | size += vma->node.size; |
128 | } | |
129 | ||
130 | return size; | |
131 | } | |
132 | ||
37811fcc CW |
133 | static void |
134 | describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj) | |
135 | { | |
b4716185 | 136 | struct drm_i915_private *dev_priv = to_i915(obj->base.dev); |
e2f80391 | 137 | struct intel_engine_cs *engine; |
1d693bcc | 138 | struct i915_vma *vma; |
faf5bf0a | 139 | unsigned int frontbuffer_bits; |
d7f46fc4 | 140 | int pin_count = 0; |
c3232b18 | 141 | enum intel_engine_id id; |
d7f46fc4 | 142 | |
188c1ab7 CW |
143 | lockdep_assert_held(&obj->base.dev->struct_mutex); |
144 | ||
be12a86b | 145 | seq_printf(m, "%pK: %c%c%c%c%c %8zdKiB %02x %02x [ ", |
37811fcc | 146 | &obj->base, |
be12a86b | 147 | get_active_flag(obj), |
37811fcc CW |
148 | get_pin_flag(obj), |
149 | get_tiling_flag(obj), | |
1d693bcc | 150 | get_global_flag(obj), |
be12a86b | 151 | get_pin_mapped_flag(obj), |
a05a5862 | 152 | obj->base.size / 1024, |
37811fcc | 153 | obj->base.read_domains, |
b4716185 | 154 | obj->base.write_domain); |
c3232b18 | 155 | for_each_engine_id(engine, dev_priv, id) |
b4716185 | 156 | seq_printf(m, "%x ", |
d72d908b CW |
157 | i915_gem_active_get_seqno(&obj->last_read[id], |
158 | &obj->base.dev->struct_mutex)); | |
49ef5294 | 159 | seq_printf(m, "] %x %s%s%s", |
d72d908b CW |
160 | i915_gem_active_get_seqno(&obj->last_write, |
161 | &obj->base.dev->struct_mutex), | |
36cdd013 | 162 | i915_cache_level_str(dev_priv, obj->cache_level), |
37811fcc CW |
163 | obj->dirty ? " dirty" : "", |
164 | obj->madv == I915_MADV_DONTNEED ? " purgeable" : ""); | |
165 | if (obj->base.name) | |
166 | seq_printf(m, " (name: %d)", obj->base.name); | |
1c7f4bca | 167 | list_for_each_entry(vma, &obj->vma_list, obj_link) { |
20dfbde4 | 168 | if (i915_vma_is_pinned(vma)) |
d7f46fc4 | 169 | pin_count++; |
ba0635ff DC |
170 | } |
171 | seq_printf(m, " (pinned x %d)", pin_count); | |
cc98b413 CW |
172 | if (obj->pin_display) |
173 | seq_printf(m, " (display)"); | |
1c7f4bca | 174 | list_for_each_entry(vma, &obj->vma_list, obj_link) { |
15717de2 CW |
175 | if (!drm_mm_node_allocated(&vma->node)) |
176 | continue; | |
177 | ||
8d2fdc3f | 178 | seq_printf(m, " (%sgtt offset: %08llx, size: %08llx", |
3272db53 | 179 | i915_vma_is_ggtt(vma) ? "g" : "pp", |
8d2fdc3f | 180 | vma->node.start, vma->node.size); |
3272db53 | 181 | if (i915_vma_is_ggtt(vma)) |
596c5923 | 182 | seq_printf(m, ", type: %u", vma->ggtt_view.type); |
49ef5294 CW |
183 | if (vma->fence) |
184 | seq_printf(m, " , fence: %d%s", | |
185 | vma->fence->id, | |
186 | i915_gem_active_isset(&vma->last_fence) ? "*" : ""); | |
596c5923 | 187 | seq_puts(m, ")"); |
1d693bcc | 188 | } |
c1ad11fc | 189 | if (obj->stolen) |
440fd528 | 190 | seq_printf(m, " (stolen: %08llx)", obj->stolen->start); |
30154650 | 191 | if (obj->pin_display || obj->fault_mappable) { |
6299f992 | 192 | char s[3], *t = s; |
30154650 | 193 | if (obj->pin_display) |
6299f992 CW |
194 | *t++ = 'p'; |
195 | if (obj->fault_mappable) | |
196 | *t++ = 'f'; | |
197 | *t = '\0'; | |
198 | seq_printf(m, " (%s mappable)", s); | |
199 | } | |
27c01aae | 200 | |
d72d908b | 201 | engine = i915_gem_active_get_engine(&obj->last_write, |
36cdd013 | 202 | &dev_priv->drm.struct_mutex); |
27c01aae CW |
203 | if (engine) |
204 | seq_printf(m, " (%s)", engine->name); | |
205 | ||
faf5bf0a CW |
206 | frontbuffer_bits = atomic_read(&obj->frontbuffer_bits); |
207 | if (frontbuffer_bits) | |
208 | seq_printf(m, " (frontbuffer: 0x%03x)", frontbuffer_bits); | |
37811fcc CW |
209 | } |
210 | ||
6d2b8885 CW |
211 | static int obj_rank_by_stolen(void *priv, |
212 | struct list_head *A, struct list_head *B) | |
213 | { | |
214 | struct drm_i915_gem_object *a = | |
b25cb2f8 | 215 | container_of(A, struct drm_i915_gem_object, obj_exec_link); |
6d2b8885 | 216 | struct drm_i915_gem_object *b = |
b25cb2f8 | 217 | container_of(B, struct drm_i915_gem_object, obj_exec_link); |
6d2b8885 | 218 | |
2d05fa16 RV |
219 | if (a->stolen->start < b->stolen->start) |
220 | return -1; | |
221 | if (a->stolen->start > b->stolen->start) | |
222 | return 1; | |
223 | return 0; | |
6d2b8885 CW |
224 | } |
225 | ||
226 | static int i915_gem_stolen_list_info(struct seq_file *m, void *data) | |
227 | { | |
36cdd013 DW |
228 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
229 | struct drm_device *dev = &dev_priv->drm; | |
6d2b8885 | 230 | struct drm_i915_gem_object *obj; |
c44ef60e | 231 | u64 total_obj_size, total_gtt_size; |
6d2b8885 CW |
232 | LIST_HEAD(stolen); |
233 | int count, ret; | |
234 | ||
235 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
236 | if (ret) | |
237 | return ret; | |
238 | ||
239 | total_obj_size = total_gtt_size = count = 0; | |
240 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) { | |
241 | if (obj->stolen == NULL) | |
242 | continue; | |
243 | ||
b25cb2f8 | 244 | list_add(&obj->obj_exec_link, &stolen); |
6d2b8885 CW |
245 | |
246 | total_obj_size += obj->base.size; | |
ca1543be | 247 | total_gtt_size += i915_gem_obj_total_ggtt_size(obj); |
6d2b8885 CW |
248 | count++; |
249 | } | |
250 | list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) { | |
251 | if (obj->stolen == NULL) | |
252 | continue; | |
253 | ||
b25cb2f8 | 254 | list_add(&obj->obj_exec_link, &stolen); |
6d2b8885 CW |
255 | |
256 | total_obj_size += obj->base.size; | |
257 | count++; | |
258 | } | |
259 | list_sort(NULL, &stolen, obj_rank_by_stolen); | |
260 | seq_puts(m, "Stolen:\n"); | |
261 | while (!list_empty(&stolen)) { | |
b25cb2f8 | 262 | obj = list_first_entry(&stolen, typeof(*obj), obj_exec_link); |
6d2b8885 CW |
263 | seq_puts(m, " "); |
264 | describe_obj(m, obj); | |
265 | seq_putc(m, '\n'); | |
b25cb2f8 | 266 | list_del_init(&obj->obj_exec_link); |
6d2b8885 CW |
267 | } |
268 | mutex_unlock(&dev->struct_mutex); | |
269 | ||
c44ef60e | 270 | seq_printf(m, "Total %d objects, %llu bytes, %llu GTT size\n", |
6d2b8885 CW |
271 | count, total_obj_size, total_gtt_size); |
272 | return 0; | |
273 | } | |
274 | ||
2db8e9d6 | 275 | struct file_stats { |
6313c204 | 276 | struct drm_i915_file_private *file_priv; |
c44ef60e MK |
277 | unsigned long count; |
278 | u64 total, unbound; | |
279 | u64 global, shared; | |
280 | u64 active, inactive; | |
2db8e9d6 CW |
281 | }; |
282 | ||
283 | static int per_file_stats(int id, void *ptr, void *data) | |
284 | { | |
285 | struct drm_i915_gem_object *obj = ptr; | |
286 | struct file_stats *stats = data; | |
6313c204 | 287 | struct i915_vma *vma; |
2db8e9d6 CW |
288 | |
289 | stats->count++; | |
290 | stats->total += obj->base.size; | |
15717de2 CW |
291 | if (!obj->bind_count) |
292 | stats->unbound += obj->base.size; | |
c67a17e9 CW |
293 | if (obj->base.name || obj->base.dma_buf) |
294 | stats->shared += obj->base.size; | |
295 | ||
894eeecc CW |
296 | list_for_each_entry(vma, &obj->vma_list, obj_link) { |
297 | if (!drm_mm_node_allocated(&vma->node)) | |
298 | continue; | |
6313c204 | 299 | |
3272db53 | 300 | if (i915_vma_is_ggtt(vma)) { |
894eeecc CW |
301 | stats->global += vma->node.size; |
302 | } else { | |
303 | struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vma->vm); | |
6313c204 | 304 | |
2bfa996e | 305 | if (ppgtt->base.file != stats->file_priv) |
6313c204 | 306 | continue; |
6313c204 | 307 | } |
894eeecc | 308 | |
b0decaf7 | 309 | if (i915_vma_is_active(vma)) |
894eeecc CW |
310 | stats->active += vma->node.size; |
311 | else | |
312 | stats->inactive += vma->node.size; | |
2db8e9d6 CW |
313 | } |
314 | ||
315 | return 0; | |
316 | } | |
317 | ||
b0da1b79 CW |
318 | #define print_file_stats(m, name, stats) do { \ |
319 | if (stats.count) \ | |
c44ef60e | 320 | seq_printf(m, "%s: %lu objects, %llu bytes (%llu active, %llu inactive, %llu global, %llu shared, %llu unbound)\n", \ |
b0da1b79 CW |
321 | name, \ |
322 | stats.count, \ | |
323 | stats.total, \ | |
324 | stats.active, \ | |
325 | stats.inactive, \ | |
326 | stats.global, \ | |
327 | stats.shared, \ | |
328 | stats.unbound); \ | |
329 | } while (0) | |
493018dc BV |
330 | |
331 | static void print_batch_pool_stats(struct seq_file *m, | |
332 | struct drm_i915_private *dev_priv) | |
333 | { | |
334 | struct drm_i915_gem_object *obj; | |
335 | struct file_stats stats; | |
e2f80391 | 336 | struct intel_engine_cs *engine; |
b4ac5afc | 337 | int j; |
493018dc BV |
338 | |
339 | memset(&stats, 0, sizeof(stats)); | |
340 | ||
b4ac5afc | 341 | for_each_engine(engine, dev_priv) { |
e2f80391 | 342 | for (j = 0; j < ARRAY_SIZE(engine->batch_pool.cache_list); j++) { |
8d9d5744 | 343 | list_for_each_entry(obj, |
e2f80391 | 344 | &engine->batch_pool.cache_list[j], |
8d9d5744 CW |
345 | batch_pool_link) |
346 | per_file_stats(0, obj, &stats); | |
347 | } | |
06fbca71 | 348 | } |
493018dc | 349 | |
b0da1b79 | 350 | print_file_stats(m, "[k]batch pool", stats); |
493018dc BV |
351 | } |
352 | ||
15da9565 CW |
353 | static int per_file_ctx_stats(int id, void *ptr, void *data) |
354 | { | |
355 | struct i915_gem_context *ctx = ptr; | |
356 | int n; | |
357 | ||
358 | for (n = 0; n < ARRAY_SIZE(ctx->engine); n++) { | |
359 | if (ctx->engine[n].state) | |
bf3783e5 | 360 | per_file_stats(0, ctx->engine[n].state->obj, data); |
dca33ecc | 361 | if (ctx->engine[n].ring) |
57e88531 | 362 | per_file_stats(0, ctx->engine[n].ring->vma->obj, data); |
15da9565 CW |
363 | } |
364 | ||
365 | return 0; | |
366 | } | |
367 | ||
368 | static void print_context_stats(struct seq_file *m, | |
369 | struct drm_i915_private *dev_priv) | |
370 | { | |
36cdd013 | 371 | struct drm_device *dev = &dev_priv->drm; |
15da9565 CW |
372 | struct file_stats stats; |
373 | struct drm_file *file; | |
374 | ||
375 | memset(&stats, 0, sizeof(stats)); | |
376 | ||
36cdd013 | 377 | mutex_lock(&dev->struct_mutex); |
15da9565 CW |
378 | if (dev_priv->kernel_context) |
379 | per_file_ctx_stats(0, dev_priv->kernel_context, &stats); | |
380 | ||
36cdd013 | 381 | list_for_each_entry(file, &dev->filelist, lhead) { |
15da9565 CW |
382 | struct drm_i915_file_private *fpriv = file->driver_priv; |
383 | idr_for_each(&fpriv->context_idr, per_file_ctx_stats, &stats); | |
384 | } | |
36cdd013 | 385 | mutex_unlock(&dev->struct_mutex); |
15da9565 CW |
386 | |
387 | print_file_stats(m, "[k]contexts", stats); | |
388 | } | |
389 | ||
36cdd013 | 390 | static int i915_gem_object_info(struct seq_file *m, void *data) |
73aa808f | 391 | { |
36cdd013 DW |
392 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
393 | struct drm_device *dev = &dev_priv->drm; | |
72e96d64 | 394 | struct i915_ggtt *ggtt = &dev_priv->ggtt; |
2bd160a1 CW |
395 | u32 count, mapped_count, purgeable_count, dpy_count; |
396 | u64 size, mapped_size, purgeable_size, dpy_size; | |
6299f992 | 397 | struct drm_i915_gem_object *obj; |
2db8e9d6 | 398 | struct drm_file *file; |
73aa808f CW |
399 | int ret; |
400 | ||
401 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
402 | if (ret) | |
403 | return ret; | |
404 | ||
6299f992 CW |
405 | seq_printf(m, "%u objects, %zu bytes\n", |
406 | dev_priv->mm.object_count, | |
407 | dev_priv->mm.object_memory); | |
408 | ||
1544c42e CW |
409 | size = count = 0; |
410 | mapped_size = mapped_count = 0; | |
411 | purgeable_size = purgeable_count = 0; | |
35c20a60 | 412 | list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) { |
2bd160a1 CW |
413 | size += obj->base.size; |
414 | ++count; | |
415 | ||
416 | if (obj->madv == I915_MADV_DONTNEED) { | |
417 | purgeable_size += obj->base.size; | |
418 | ++purgeable_count; | |
419 | } | |
420 | ||
be19b10d | 421 | if (obj->mapping) { |
2bd160a1 CW |
422 | mapped_count++; |
423 | mapped_size += obj->base.size; | |
be19b10d | 424 | } |
b7abb714 | 425 | } |
c44ef60e | 426 | seq_printf(m, "%u unbound objects, %llu bytes\n", count, size); |
6c085a72 | 427 | |
2bd160a1 | 428 | size = count = dpy_size = dpy_count = 0; |
35c20a60 | 429 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) { |
2bd160a1 CW |
430 | size += obj->base.size; |
431 | ++count; | |
432 | ||
30154650 | 433 | if (obj->pin_display) { |
2bd160a1 CW |
434 | dpy_size += obj->base.size; |
435 | ++dpy_count; | |
6299f992 | 436 | } |
2bd160a1 | 437 | |
b7abb714 CW |
438 | if (obj->madv == I915_MADV_DONTNEED) { |
439 | purgeable_size += obj->base.size; | |
440 | ++purgeable_count; | |
441 | } | |
2bd160a1 | 442 | |
be19b10d | 443 | if (obj->mapping) { |
2bd160a1 CW |
444 | mapped_count++; |
445 | mapped_size += obj->base.size; | |
be19b10d | 446 | } |
6299f992 | 447 | } |
2bd160a1 CW |
448 | seq_printf(m, "%u bound objects, %llu bytes\n", |
449 | count, size); | |
c44ef60e | 450 | seq_printf(m, "%u purgeable objects, %llu bytes\n", |
b7abb714 | 451 | purgeable_count, purgeable_size); |
2bd160a1 CW |
452 | seq_printf(m, "%u mapped objects, %llu bytes\n", |
453 | mapped_count, mapped_size); | |
454 | seq_printf(m, "%u display objects (pinned), %llu bytes\n", | |
455 | dpy_count, dpy_size); | |
6299f992 | 456 | |
c44ef60e | 457 | seq_printf(m, "%llu [%llu] gtt total\n", |
72e96d64 | 458 | ggtt->base.total, ggtt->mappable_end - ggtt->base.start); |
73aa808f | 459 | |
493018dc BV |
460 | seq_putc(m, '\n'); |
461 | print_batch_pool_stats(m, dev_priv); | |
1d2ac403 DV |
462 | mutex_unlock(&dev->struct_mutex); |
463 | ||
464 | mutex_lock(&dev->filelist_mutex); | |
15da9565 | 465 | print_context_stats(m, dev_priv); |
2db8e9d6 CW |
466 | list_for_each_entry_reverse(file, &dev->filelist, lhead) { |
467 | struct file_stats stats; | |
c84455b4 CW |
468 | struct drm_i915_file_private *file_priv = file->driver_priv; |
469 | struct drm_i915_gem_request *request; | |
3ec2f427 | 470 | struct task_struct *task; |
2db8e9d6 CW |
471 | |
472 | memset(&stats, 0, sizeof(stats)); | |
6313c204 | 473 | stats.file_priv = file->driver_priv; |
5b5ffff0 | 474 | spin_lock(&file->table_lock); |
2db8e9d6 | 475 | idr_for_each(&file->object_idr, per_file_stats, &stats); |
5b5ffff0 | 476 | spin_unlock(&file->table_lock); |
3ec2f427 TH |
477 | /* |
478 | * Although we have a valid reference on file->pid, that does | |
479 | * not guarantee that the task_struct who called get_pid() is | |
480 | * still alive (e.g. get_pid(current) => fork() => exit()). | |
481 | * Therefore, we need to protect this ->comm access using RCU. | |
482 | */ | |
c84455b4 CW |
483 | mutex_lock(&dev->struct_mutex); |
484 | request = list_first_entry_or_null(&file_priv->mm.request_list, | |
485 | struct drm_i915_gem_request, | |
486 | client_list); | |
3ec2f427 | 487 | rcu_read_lock(); |
c84455b4 CW |
488 | task = pid_task(request && request->ctx->pid ? |
489 | request->ctx->pid : file->pid, | |
490 | PIDTYPE_PID); | |
493018dc | 491 | print_file_stats(m, task ? task->comm : "<unknown>", stats); |
3ec2f427 | 492 | rcu_read_unlock(); |
c84455b4 | 493 | mutex_unlock(&dev->struct_mutex); |
2db8e9d6 | 494 | } |
1d2ac403 | 495 | mutex_unlock(&dev->filelist_mutex); |
73aa808f CW |
496 | |
497 | return 0; | |
498 | } | |
499 | ||
aee56cff | 500 | static int i915_gem_gtt_info(struct seq_file *m, void *data) |
08c18323 | 501 | { |
9f25d007 | 502 | struct drm_info_node *node = m->private; |
36cdd013 DW |
503 | struct drm_i915_private *dev_priv = node_to_i915(node); |
504 | struct drm_device *dev = &dev_priv->drm; | |
5f4b091a | 505 | bool show_pin_display_only = !!node->info_ent->data; |
08c18323 | 506 | struct drm_i915_gem_object *obj; |
c44ef60e | 507 | u64 total_obj_size, total_gtt_size; |
08c18323 CW |
508 | int count, ret; |
509 | ||
510 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
511 | if (ret) | |
512 | return ret; | |
513 | ||
514 | total_obj_size = total_gtt_size = count = 0; | |
35c20a60 | 515 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) { |
6da84829 | 516 | if (show_pin_display_only && !obj->pin_display) |
1b50247a CW |
517 | continue; |
518 | ||
267f0c90 | 519 | seq_puts(m, " "); |
08c18323 | 520 | describe_obj(m, obj); |
267f0c90 | 521 | seq_putc(m, '\n'); |
08c18323 | 522 | total_obj_size += obj->base.size; |
ca1543be | 523 | total_gtt_size += i915_gem_obj_total_ggtt_size(obj); |
08c18323 CW |
524 | count++; |
525 | } | |
526 | ||
527 | mutex_unlock(&dev->struct_mutex); | |
528 | ||
c44ef60e | 529 | seq_printf(m, "Total %d objects, %llu bytes, %llu GTT size\n", |
08c18323 CW |
530 | count, total_obj_size, total_gtt_size); |
531 | ||
532 | return 0; | |
533 | } | |
534 | ||
4e5359cd SF |
535 | static int i915_gem_pageflip_info(struct seq_file *m, void *data) |
536 | { | |
36cdd013 DW |
537 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
538 | struct drm_device *dev = &dev_priv->drm; | |
4e5359cd | 539 | struct intel_crtc *crtc; |
8a270ebf DV |
540 | int ret; |
541 | ||
542 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
543 | if (ret) | |
544 | return ret; | |
4e5359cd | 545 | |
d3fcc808 | 546 | for_each_intel_crtc(dev, crtc) { |
9db4a9c7 JB |
547 | const char pipe = pipe_name(crtc->pipe); |
548 | const char plane = plane_name(crtc->plane); | |
51cbaf01 | 549 | struct intel_flip_work *work; |
4e5359cd | 550 | |
5e2d7afc | 551 | spin_lock_irq(&dev->event_lock); |
5a21b665 DV |
552 | work = crtc->flip_work; |
553 | if (work == NULL) { | |
9db4a9c7 | 554 | seq_printf(m, "No flip due on pipe %c (plane %c)\n", |
4e5359cd SF |
555 | pipe, plane); |
556 | } else { | |
5a21b665 DV |
557 | u32 pending; |
558 | u32 addr; | |
559 | ||
560 | pending = atomic_read(&work->pending); | |
561 | if (pending) { | |
562 | seq_printf(m, "Flip ioctl preparing on pipe %c (plane %c)\n", | |
563 | pipe, plane); | |
564 | } else { | |
565 | seq_printf(m, "Flip pending (waiting for vsync) on pipe %c (plane %c)\n", | |
566 | pipe, plane); | |
567 | } | |
568 | if (work->flip_queued_req) { | |
569 | struct intel_engine_cs *engine = i915_gem_request_get_engine(work->flip_queued_req); | |
570 | ||
571 | seq_printf(m, "Flip queued on %s at seqno %x, next seqno %x [current breadcrumb %x], completed? %d\n", | |
572 | engine->name, | |
573 | i915_gem_request_get_seqno(work->flip_queued_req), | |
574 | dev_priv->next_seqno, | |
1b7744e7 | 575 | intel_engine_get_seqno(engine), |
f69a02c9 | 576 | i915_gem_request_completed(work->flip_queued_req)); |
5a21b665 DV |
577 | } else |
578 | seq_printf(m, "Flip not associated with any ring\n"); | |
579 | seq_printf(m, "Flip queued on frame %d, (was ready on frame %d), now %d\n", | |
580 | work->flip_queued_vblank, | |
581 | work->flip_ready_vblank, | |
582 | intel_crtc_get_vblank_counter(crtc)); | |
583 | seq_printf(m, "%d prepares\n", atomic_read(&work->pending)); | |
584 | ||
36cdd013 | 585 | if (INTEL_GEN(dev_priv) >= 4) |
5a21b665 DV |
586 | addr = I915_HI_DISPBASE(I915_READ(DSPSURF(crtc->plane))); |
587 | else | |
588 | addr = I915_READ(DSPADDR(crtc->plane)); | |
589 | seq_printf(m, "Current scanout address 0x%08x\n", addr); | |
590 | ||
591 | if (work->pending_flip_obj) { | |
592 | seq_printf(m, "New framebuffer address 0x%08lx\n", (long)work->gtt_offset); | |
593 | seq_printf(m, "MMIO update completed? %d\n", addr == work->gtt_offset); | |
4e5359cd SF |
594 | } |
595 | } | |
5e2d7afc | 596 | spin_unlock_irq(&dev->event_lock); |
4e5359cd SF |
597 | } |
598 | ||
8a270ebf DV |
599 | mutex_unlock(&dev->struct_mutex); |
600 | ||
4e5359cd SF |
601 | return 0; |
602 | } | |
603 | ||
493018dc BV |
604 | static int i915_gem_batch_pool_info(struct seq_file *m, void *data) |
605 | { | |
36cdd013 DW |
606 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
607 | struct drm_device *dev = &dev_priv->drm; | |
493018dc | 608 | struct drm_i915_gem_object *obj; |
e2f80391 | 609 | struct intel_engine_cs *engine; |
8d9d5744 | 610 | int total = 0; |
b4ac5afc | 611 | int ret, j; |
493018dc BV |
612 | |
613 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
614 | if (ret) | |
615 | return ret; | |
616 | ||
b4ac5afc | 617 | for_each_engine(engine, dev_priv) { |
e2f80391 | 618 | for (j = 0; j < ARRAY_SIZE(engine->batch_pool.cache_list); j++) { |
8d9d5744 CW |
619 | int count; |
620 | ||
621 | count = 0; | |
622 | list_for_each_entry(obj, | |
e2f80391 | 623 | &engine->batch_pool.cache_list[j], |
8d9d5744 CW |
624 | batch_pool_link) |
625 | count++; | |
626 | seq_printf(m, "%s cache[%d]: %d objects\n", | |
e2f80391 | 627 | engine->name, j, count); |
8d9d5744 CW |
628 | |
629 | list_for_each_entry(obj, | |
e2f80391 | 630 | &engine->batch_pool.cache_list[j], |
8d9d5744 CW |
631 | batch_pool_link) { |
632 | seq_puts(m, " "); | |
633 | describe_obj(m, obj); | |
634 | seq_putc(m, '\n'); | |
635 | } | |
636 | ||
637 | total += count; | |
06fbca71 | 638 | } |
493018dc BV |
639 | } |
640 | ||
8d9d5744 | 641 | seq_printf(m, "total: %d\n", total); |
493018dc BV |
642 | |
643 | mutex_unlock(&dev->struct_mutex); | |
644 | ||
645 | return 0; | |
646 | } | |
647 | ||
2017263e BG |
648 | static int i915_gem_request_info(struct seq_file *m, void *data) |
649 | { | |
36cdd013 DW |
650 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
651 | struct drm_device *dev = &dev_priv->drm; | |
e2f80391 | 652 | struct intel_engine_cs *engine; |
eed29a5b | 653 | struct drm_i915_gem_request *req; |
b4ac5afc | 654 | int ret, any; |
de227ef0 CW |
655 | |
656 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
657 | if (ret) | |
658 | return ret; | |
2017263e | 659 | |
2d1070b2 | 660 | any = 0; |
b4ac5afc | 661 | for_each_engine(engine, dev_priv) { |
2d1070b2 CW |
662 | int count; |
663 | ||
664 | count = 0; | |
efdf7c06 | 665 | list_for_each_entry(req, &engine->request_list, link) |
2d1070b2 CW |
666 | count++; |
667 | if (count == 0) | |
a2c7f6fd CW |
668 | continue; |
669 | ||
e2f80391 | 670 | seq_printf(m, "%s requests: %d\n", engine->name, count); |
efdf7c06 | 671 | list_for_each_entry(req, &engine->request_list, link) { |
c84455b4 | 672 | struct pid *pid = req->ctx->pid; |
2d1070b2 CW |
673 | struct task_struct *task; |
674 | ||
675 | rcu_read_lock(); | |
c84455b4 | 676 | task = pid ? pid_task(pid, PIDTYPE_PID) : NULL; |
2d1070b2 | 677 | seq_printf(m, " %x @ %d: %s [%d]\n", |
04769652 | 678 | req->fence.seqno, |
eed29a5b | 679 | (int) (jiffies - req->emitted_jiffies), |
2d1070b2 CW |
680 | task ? task->comm : "<unknown>", |
681 | task ? task->pid : -1); | |
682 | rcu_read_unlock(); | |
c2c347a9 | 683 | } |
2d1070b2 CW |
684 | |
685 | any++; | |
2017263e | 686 | } |
de227ef0 CW |
687 | mutex_unlock(&dev->struct_mutex); |
688 | ||
2d1070b2 | 689 | if (any == 0) |
267f0c90 | 690 | seq_puts(m, "No requests\n"); |
c2c347a9 | 691 | |
2017263e BG |
692 | return 0; |
693 | } | |
694 | ||
b2223497 | 695 | static void i915_ring_seqno_info(struct seq_file *m, |
0bc40be8 | 696 | struct intel_engine_cs *engine) |
b2223497 | 697 | { |
688e6c72 CW |
698 | struct intel_breadcrumbs *b = &engine->breadcrumbs; |
699 | struct rb_node *rb; | |
700 | ||
12471ba8 | 701 | seq_printf(m, "Current sequence (%s): %x\n", |
1b7744e7 | 702 | engine->name, intel_engine_get_seqno(engine)); |
688e6c72 CW |
703 | |
704 | spin_lock(&b->lock); | |
705 | for (rb = rb_first(&b->waiters); rb; rb = rb_next(rb)) { | |
706 | struct intel_wait *w = container_of(rb, typeof(*w), node); | |
707 | ||
708 | seq_printf(m, "Waiting (%s): %s [%d] on %x\n", | |
709 | engine->name, w->tsk->comm, w->tsk->pid, w->seqno); | |
710 | } | |
711 | spin_unlock(&b->lock); | |
b2223497 CW |
712 | } |
713 | ||
2017263e BG |
714 | static int i915_gem_seqno_info(struct seq_file *m, void *data) |
715 | { | |
36cdd013 | 716 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
e2f80391 | 717 | struct intel_engine_cs *engine; |
2017263e | 718 | |
b4ac5afc | 719 | for_each_engine(engine, dev_priv) |
e2f80391 | 720 | i915_ring_seqno_info(m, engine); |
de227ef0 | 721 | |
2017263e BG |
722 | return 0; |
723 | } | |
724 | ||
725 | ||
726 | static int i915_interrupt_info(struct seq_file *m, void *data) | |
727 | { | |
36cdd013 | 728 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
e2f80391 | 729 | struct intel_engine_cs *engine; |
4bb05040 | 730 | int i, pipe; |
de227ef0 | 731 | |
c8c8fb33 | 732 | intel_runtime_pm_get(dev_priv); |
2017263e | 733 | |
36cdd013 | 734 | if (IS_CHERRYVIEW(dev_priv)) { |
74e1ca8c VS |
735 | seq_printf(m, "Master Interrupt Control:\t%08x\n", |
736 | I915_READ(GEN8_MASTER_IRQ)); | |
737 | ||
738 | seq_printf(m, "Display IER:\t%08x\n", | |
739 | I915_READ(VLV_IER)); | |
740 | seq_printf(m, "Display IIR:\t%08x\n", | |
741 | I915_READ(VLV_IIR)); | |
742 | seq_printf(m, "Display IIR_RW:\t%08x\n", | |
743 | I915_READ(VLV_IIR_RW)); | |
744 | seq_printf(m, "Display IMR:\t%08x\n", | |
745 | I915_READ(VLV_IMR)); | |
055e393f | 746 | for_each_pipe(dev_priv, pipe) |
74e1ca8c VS |
747 | seq_printf(m, "Pipe %c stat:\t%08x\n", |
748 | pipe_name(pipe), | |
749 | I915_READ(PIPESTAT(pipe))); | |
750 | ||
751 | seq_printf(m, "Port hotplug:\t%08x\n", | |
752 | I915_READ(PORT_HOTPLUG_EN)); | |
753 | seq_printf(m, "DPFLIPSTAT:\t%08x\n", | |
754 | I915_READ(VLV_DPFLIPSTAT)); | |
755 | seq_printf(m, "DPINVGTT:\t%08x\n", | |
756 | I915_READ(DPINVGTT)); | |
757 | ||
758 | for (i = 0; i < 4; i++) { | |
759 | seq_printf(m, "GT Interrupt IMR %d:\t%08x\n", | |
760 | i, I915_READ(GEN8_GT_IMR(i))); | |
761 | seq_printf(m, "GT Interrupt IIR %d:\t%08x\n", | |
762 | i, I915_READ(GEN8_GT_IIR(i))); | |
763 | seq_printf(m, "GT Interrupt IER %d:\t%08x\n", | |
764 | i, I915_READ(GEN8_GT_IER(i))); | |
765 | } | |
766 | ||
767 | seq_printf(m, "PCU interrupt mask:\t%08x\n", | |
768 | I915_READ(GEN8_PCU_IMR)); | |
769 | seq_printf(m, "PCU interrupt identity:\t%08x\n", | |
770 | I915_READ(GEN8_PCU_IIR)); | |
771 | seq_printf(m, "PCU interrupt enable:\t%08x\n", | |
772 | I915_READ(GEN8_PCU_IER)); | |
36cdd013 | 773 | } else if (INTEL_GEN(dev_priv) >= 8) { |
a123f157 BW |
774 | seq_printf(m, "Master Interrupt Control:\t%08x\n", |
775 | I915_READ(GEN8_MASTER_IRQ)); | |
776 | ||
777 | for (i = 0; i < 4; i++) { | |
778 | seq_printf(m, "GT Interrupt IMR %d:\t%08x\n", | |
779 | i, I915_READ(GEN8_GT_IMR(i))); | |
780 | seq_printf(m, "GT Interrupt IIR %d:\t%08x\n", | |
781 | i, I915_READ(GEN8_GT_IIR(i))); | |
782 | seq_printf(m, "GT Interrupt IER %d:\t%08x\n", | |
783 | i, I915_READ(GEN8_GT_IER(i))); | |
784 | } | |
785 | ||
055e393f | 786 | for_each_pipe(dev_priv, pipe) { |
e129649b ID |
787 | enum intel_display_power_domain power_domain; |
788 | ||
789 | power_domain = POWER_DOMAIN_PIPE(pipe); | |
790 | if (!intel_display_power_get_if_enabled(dev_priv, | |
791 | power_domain)) { | |
22c59960 PZ |
792 | seq_printf(m, "Pipe %c power disabled\n", |
793 | pipe_name(pipe)); | |
794 | continue; | |
795 | } | |
a123f157 | 796 | seq_printf(m, "Pipe %c IMR:\t%08x\n", |
07d27e20 DL |
797 | pipe_name(pipe), |
798 | I915_READ(GEN8_DE_PIPE_IMR(pipe))); | |
a123f157 | 799 | seq_printf(m, "Pipe %c IIR:\t%08x\n", |
07d27e20 DL |
800 | pipe_name(pipe), |
801 | I915_READ(GEN8_DE_PIPE_IIR(pipe))); | |
a123f157 | 802 | seq_printf(m, "Pipe %c IER:\t%08x\n", |
07d27e20 DL |
803 | pipe_name(pipe), |
804 | I915_READ(GEN8_DE_PIPE_IER(pipe))); | |
e129649b ID |
805 | |
806 | intel_display_power_put(dev_priv, power_domain); | |
a123f157 BW |
807 | } |
808 | ||
809 | seq_printf(m, "Display Engine port interrupt mask:\t%08x\n", | |
810 | I915_READ(GEN8_DE_PORT_IMR)); | |
811 | seq_printf(m, "Display Engine port interrupt identity:\t%08x\n", | |
812 | I915_READ(GEN8_DE_PORT_IIR)); | |
813 | seq_printf(m, "Display Engine port interrupt enable:\t%08x\n", | |
814 | I915_READ(GEN8_DE_PORT_IER)); | |
815 | ||
816 | seq_printf(m, "Display Engine misc interrupt mask:\t%08x\n", | |
817 | I915_READ(GEN8_DE_MISC_IMR)); | |
818 | seq_printf(m, "Display Engine misc interrupt identity:\t%08x\n", | |
819 | I915_READ(GEN8_DE_MISC_IIR)); | |
820 | seq_printf(m, "Display Engine misc interrupt enable:\t%08x\n", | |
821 | I915_READ(GEN8_DE_MISC_IER)); | |
822 | ||
823 | seq_printf(m, "PCU interrupt mask:\t%08x\n", | |
824 | I915_READ(GEN8_PCU_IMR)); | |
825 | seq_printf(m, "PCU interrupt identity:\t%08x\n", | |
826 | I915_READ(GEN8_PCU_IIR)); | |
827 | seq_printf(m, "PCU interrupt enable:\t%08x\n", | |
828 | I915_READ(GEN8_PCU_IER)); | |
36cdd013 | 829 | } else if (IS_VALLEYVIEW(dev_priv)) { |
7e231dbe JB |
830 | seq_printf(m, "Display IER:\t%08x\n", |
831 | I915_READ(VLV_IER)); | |
832 | seq_printf(m, "Display IIR:\t%08x\n", | |
833 | I915_READ(VLV_IIR)); | |
834 | seq_printf(m, "Display IIR_RW:\t%08x\n", | |
835 | I915_READ(VLV_IIR_RW)); | |
836 | seq_printf(m, "Display IMR:\t%08x\n", | |
837 | I915_READ(VLV_IMR)); | |
055e393f | 838 | for_each_pipe(dev_priv, pipe) |
7e231dbe JB |
839 | seq_printf(m, "Pipe %c stat:\t%08x\n", |
840 | pipe_name(pipe), | |
841 | I915_READ(PIPESTAT(pipe))); | |
842 | ||
843 | seq_printf(m, "Master IER:\t%08x\n", | |
844 | I915_READ(VLV_MASTER_IER)); | |
845 | ||
846 | seq_printf(m, "Render IER:\t%08x\n", | |
847 | I915_READ(GTIER)); | |
848 | seq_printf(m, "Render IIR:\t%08x\n", | |
849 | I915_READ(GTIIR)); | |
850 | seq_printf(m, "Render IMR:\t%08x\n", | |
851 | I915_READ(GTIMR)); | |
852 | ||
853 | seq_printf(m, "PM IER:\t\t%08x\n", | |
854 | I915_READ(GEN6_PMIER)); | |
855 | seq_printf(m, "PM IIR:\t\t%08x\n", | |
856 | I915_READ(GEN6_PMIIR)); | |
857 | seq_printf(m, "PM IMR:\t\t%08x\n", | |
858 | I915_READ(GEN6_PMIMR)); | |
859 | ||
860 | seq_printf(m, "Port hotplug:\t%08x\n", | |
861 | I915_READ(PORT_HOTPLUG_EN)); | |
862 | seq_printf(m, "DPFLIPSTAT:\t%08x\n", | |
863 | I915_READ(VLV_DPFLIPSTAT)); | |
864 | seq_printf(m, "DPINVGTT:\t%08x\n", | |
865 | I915_READ(DPINVGTT)); | |
866 | ||
36cdd013 | 867 | } else if (!HAS_PCH_SPLIT(dev_priv)) { |
5f6a1695 ZW |
868 | seq_printf(m, "Interrupt enable: %08x\n", |
869 | I915_READ(IER)); | |
870 | seq_printf(m, "Interrupt identity: %08x\n", | |
871 | I915_READ(IIR)); | |
872 | seq_printf(m, "Interrupt mask: %08x\n", | |
873 | I915_READ(IMR)); | |
055e393f | 874 | for_each_pipe(dev_priv, pipe) |
9db4a9c7 JB |
875 | seq_printf(m, "Pipe %c stat: %08x\n", |
876 | pipe_name(pipe), | |
877 | I915_READ(PIPESTAT(pipe))); | |
5f6a1695 ZW |
878 | } else { |
879 | seq_printf(m, "North Display Interrupt enable: %08x\n", | |
880 | I915_READ(DEIER)); | |
881 | seq_printf(m, "North Display Interrupt identity: %08x\n", | |
882 | I915_READ(DEIIR)); | |
883 | seq_printf(m, "North Display Interrupt mask: %08x\n", | |
884 | I915_READ(DEIMR)); | |
885 | seq_printf(m, "South Display Interrupt enable: %08x\n", | |
886 | I915_READ(SDEIER)); | |
887 | seq_printf(m, "South Display Interrupt identity: %08x\n", | |
888 | I915_READ(SDEIIR)); | |
889 | seq_printf(m, "South Display Interrupt mask: %08x\n", | |
890 | I915_READ(SDEIMR)); | |
891 | seq_printf(m, "Graphics Interrupt enable: %08x\n", | |
892 | I915_READ(GTIER)); | |
893 | seq_printf(m, "Graphics Interrupt identity: %08x\n", | |
894 | I915_READ(GTIIR)); | |
895 | seq_printf(m, "Graphics Interrupt mask: %08x\n", | |
896 | I915_READ(GTIMR)); | |
897 | } | |
b4ac5afc | 898 | for_each_engine(engine, dev_priv) { |
36cdd013 | 899 | if (INTEL_GEN(dev_priv) >= 6) { |
a2c7f6fd CW |
900 | seq_printf(m, |
901 | "Graphics Interrupt mask (%s): %08x\n", | |
e2f80391 | 902 | engine->name, I915_READ_IMR(engine)); |
9862e600 | 903 | } |
e2f80391 | 904 | i915_ring_seqno_info(m, engine); |
9862e600 | 905 | } |
c8c8fb33 | 906 | intel_runtime_pm_put(dev_priv); |
de227ef0 | 907 | |
2017263e BG |
908 | return 0; |
909 | } | |
910 | ||
a6172a80 CW |
911 | static int i915_gem_fence_regs_info(struct seq_file *m, void *data) |
912 | { | |
36cdd013 DW |
913 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
914 | struct drm_device *dev = &dev_priv->drm; | |
de227ef0 CW |
915 | int i, ret; |
916 | ||
917 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
918 | if (ret) | |
919 | return ret; | |
a6172a80 | 920 | |
a6172a80 CW |
921 | seq_printf(m, "Total fences = %d\n", dev_priv->num_fence_regs); |
922 | for (i = 0; i < dev_priv->num_fence_regs; i++) { | |
49ef5294 | 923 | struct i915_vma *vma = dev_priv->fence_regs[i].vma; |
a6172a80 | 924 | |
6c085a72 CW |
925 | seq_printf(m, "Fence %d, pin count = %d, object = ", |
926 | i, dev_priv->fence_regs[i].pin_count); | |
49ef5294 | 927 | if (!vma) |
267f0c90 | 928 | seq_puts(m, "unused"); |
c2c347a9 | 929 | else |
49ef5294 | 930 | describe_obj(m, vma->obj); |
267f0c90 | 931 | seq_putc(m, '\n'); |
a6172a80 CW |
932 | } |
933 | ||
05394f39 | 934 | mutex_unlock(&dev->struct_mutex); |
a6172a80 CW |
935 | return 0; |
936 | } | |
937 | ||
2017263e BG |
938 | static int i915_hws_info(struct seq_file *m, void *data) |
939 | { | |
9f25d007 | 940 | struct drm_info_node *node = m->private; |
36cdd013 | 941 | struct drm_i915_private *dev_priv = node_to_i915(node); |
e2f80391 | 942 | struct intel_engine_cs *engine; |
1a240d4d | 943 | const u32 *hws; |
4066c0ae CW |
944 | int i; |
945 | ||
4a570db5 | 946 | engine = &dev_priv->engine[(uintptr_t)node->info_ent->data]; |
e2f80391 | 947 | hws = engine->status_page.page_addr; |
2017263e BG |
948 | if (hws == NULL) |
949 | return 0; | |
950 | ||
951 | for (i = 0; i < 4096 / sizeof(u32) / 4; i += 4) { | |
952 | seq_printf(m, "0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x\n", | |
953 | i * 4, | |
954 | hws[i], hws[i + 1], hws[i + 2], hws[i + 3]); | |
955 | } | |
956 | return 0; | |
957 | } | |
958 | ||
d5442303 DV |
959 | static ssize_t |
960 | i915_error_state_write(struct file *filp, | |
961 | const char __user *ubuf, | |
962 | size_t cnt, | |
963 | loff_t *ppos) | |
964 | { | |
edc3d884 | 965 | struct i915_error_state_file_priv *error_priv = filp->private_data; |
d5442303 DV |
966 | |
967 | DRM_DEBUG_DRIVER("Resetting error state\n"); | |
662d19e7 | 968 | i915_destroy_error_state(error_priv->dev); |
d5442303 DV |
969 | |
970 | return cnt; | |
971 | } | |
972 | ||
973 | static int i915_error_state_open(struct inode *inode, struct file *file) | |
974 | { | |
36cdd013 | 975 | struct drm_i915_private *dev_priv = inode->i_private; |
d5442303 | 976 | struct i915_error_state_file_priv *error_priv; |
d5442303 DV |
977 | |
978 | error_priv = kzalloc(sizeof(*error_priv), GFP_KERNEL); | |
979 | if (!error_priv) | |
980 | return -ENOMEM; | |
981 | ||
36cdd013 | 982 | error_priv->dev = &dev_priv->drm; |
d5442303 | 983 | |
36cdd013 | 984 | i915_error_state_get(&dev_priv->drm, error_priv); |
d5442303 | 985 | |
edc3d884 MK |
986 | file->private_data = error_priv; |
987 | ||
988 | return 0; | |
d5442303 DV |
989 | } |
990 | ||
991 | static int i915_error_state_release(struct inode *inode, struct file *file) | |
992 | { | |
edc3d884 | 993 | struct i915_error_state_file_priv *error_priv = file->private_data; |
d5442303 | 994 | |
95d5bfb3 | 995 | i915_error_state_put(error_priv); |
d5442303 DV |
996 | kfree(error_priv); |
997 | ||
edc3d884 MK |
998 | return 0; |
999 | } | |
1000 | ||
4dc955f7 MK |
1001 | static ssize_t i915_error_state_read(struct file *file, char __user *userbuf, |
1002 | size_t count, loff_t *pos) | |
1003 | { | |
1004 | struct i915_error_state_file_priv *error_priv = file->private_data; | |
1005 | struct drm_i915_error_state_buf error_str; | |
1006 | loff_t tmp_pos = 0; | |
1007 | ssize_t ret_count = 0; | |
1008 | int ret; | |
1009 | ||
36cdd013 DW |
1010 | ret = i915_error_state_buf_init(&error_str, |
1011 | to_i915(error_priv->dev), count, *pos); | |
4dc955f7 MK |
1012 | if (ret) |
1013 | return ret; | |
edc3d884 | 1014 | |
fc16b48b | 1015 | ret = i915_error_state_to_str(&error_str, error_priv); |
edc3d884 MK |
1016 | if (ret) |
1017 | goto out; | |
1018 | ||
edc3d884 MK |
1019 | ret_count = simple_read_from_buffer(userbuf, count, &tmp_pos, |
1020 | error_str.buf, | |
1021 | error_str.bytes); | |
1022 | ||
1023 | if (ret_count < 0) | |
1024 | ret = ret_count; | |
1025 | else | |
1026 | *pos = error_str.start + ret_count; | |
1027 | out: | |
4dc955f7 | 1028 | i915_error_state_buf_release(&error_str); |
edc3d884 | 1029 | return ret ?: ret_count; |
d5442303 DV |
1030 | } |
1031 | ||
1032 | static const struct file_operations i915_error_state_fops = { | |
1033 | .owner = THIS_MODULE, | |
1034 | .open = i915_error_state_open, | |
edc3d884 | 1035 | .read = i915_error_state_read, |
d5442303 DV |
1036 | .write = i915_error_state_write, |
1037 | .llseek = default_llseek, | |
1038 | .release = i915_error_state_release, | |
1039 | }; | |
1040 | ||
647416f9 KC |
1041 | static int |
1042 | i915_next_seqno_get(void *data, u64 *val) | |
40633219 | 1043 | { |
36cdd013 | 1044 | struct drm_i915_private *dev_priv = data; |
40633219 MK |
1045 | int ret; |
1046 | ||
36cdd013 | 1047 | ret = mutex_lock_interruptible(&dev_priv->drm.struct_mutex); |
40633219 MK |
1048 | if (ret) |
1049 | return ret; | |
1050 | ||
647416f9 | 1051 | *val = dev_priv->next_seqno; |
36cdd013 | 1052 | mutex_unlock(&dev_priv->drm.struct_mutex); |
40633219 | 1053 | |
647416f9 | 1054 | return 0; |
40633219 MK |
1055 | } |
1056 | ||
647416f9 KC |
1057 | static int |
1058 | i915_next_seqno_set(void *data, u64 val) | |
1059 | { | |
36cdd013 DW |
1060 | struct drm_i915_private *dev_priv = data; |
1061 | struct drm_device *dev = &dev_priv->drm; | |
40633219 MK |
1062 | int ret; |
1063 | ||
40633219 MK |
1064 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
1065 | if (ret) | |
1066 | return ret; | |
1067 | ||
e94fbaa8 | 1068 | ret = i915_gem_set_seqno(dev, val); |
40633219 MK |
1069 | mutex_unlock(&dev->struct_mutex); |
1070 | ||
647416f9 | 1071 | return ret; |
40633219 MK |
1072 | } |
1073 | ||
647416f9 KC |
1074 | DEFINE_SIMPLE_ATTRIBUTE(i915_next_seqno_fops, |
1075 | i915_next_seqno_get, i915_next_seqno_set, | |
3a3b4f98 | 1076 | "0x%llx\n"); |
40633219 | 1077 | |
adb4bd12 | 1078 | static int i915_frequency_info(struct seq_file *m, void *unused) |
f97108d1 | 1079 | { |
36cdd013 DW |
1080 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
1081 | struct drm_device *dev = &dev_priv->drm; | |
c8c8fb33 PZ |
1082 | int ret = 0; |
1083 | ||
1084 | intel_runtime_pm_get(dev_priv); | |
3b8d8d91 | 1085 | |
36cdd013 | 1086 | if (IS_GEN5(dev_priv)) { |
3b8d8d91 JB |
1087 | u16 rgvswctl = I915_READ16(MEMSWCTL); |
1088 | u16 rgvstat = I915_READ16(MEMSTAT_ILK); | |
1089 | ||
1090 | seq_printf(m, "Requested P-state: %d\n", (rgvswctl >> 8) & 0xf); | |
1091 | seq_printf(m, "Requested VID: %d\n", rgvswctl & 0x3f); | |
1092 | seq_printf(m, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK) >> | |
1093 | MEMSTAT_VID_SHIFT); | |
1094 | seq_printf(m, "Current P-state: %d\n", | |
1095 | (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT); | |
36cdd013 | 1096 | } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { |
666a4537 WB |
1097 | u32 freq_sts; |
1098 | ||
1099 | mutex_lock(&dev_priv->rps.hw_lock); | |
1100 | freq_sts = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS); | |
1101 | seq_printf(m, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts); | |
1102 | seq_printf(m, "DDR freq: %d MHz\n", dev_priv->mem_freq); | |
1103 | ||
1104 | seq_printf(m, "actual GPU freq: %d MHz\n", | |
1105 | intel_gpu_freq(dev_priv, (freq_sts >> 8) & 0xff)); | |
1106 | ||
1107 | seq_printf(m, "current GPU freq: %d MHz\n", | |
1108 | intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq)); | |
1109 | ||
1110 | seq_printf(m, "max GPU freq: %d MHz\n", | |
1111 | intel_gpu_freq(dev_priv, dev_priv->rps.max_freq)); | |
1112 | ||
1113 | seq_printf(m, "min GPU freq: %d MHz\n", | |
1114 | intel_gpu_freq(dev_priv, dev_priv->rps.min_freq)); | |
1115 | ||
1116 | seq_printf(m, "idle GPU freq: %d MHz\n", | |
1117 | intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq)); | |
1118 | ||
1119 | seq_printf(m, | |
1120 | "efficient (RPe) frequency: %d MHz\n", | |
1121 | intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq)); | |
1122 | mutex_unlock(&dev_priv->rps.hw_lock); | |
36cdd013 | 1123 | } else if (INTEL_GEN(dev_priv) >= 6) { |
35040562 BP |
1124 | u32 rp_state_limits; |
1125 | u32 gt_perf_status; | |
1126 | u32 rp_state_cap; | |
0d8f9491 | 1127 | u32 rpmodectl, rpinclimit, rpdeclimit; |
8e8c06cd | 1128 | u32 rpstat, cagf, reqf; |
ccab5c82 JB |
1129 | u32 rpupei, rpcurup, rpprevup; |
1130 | u32 rpdownei, rpcurdown, rpprevdown; | |
9dd3c605 | 1131 | u32 pm_ier, pm_imr, pm_isr, pm_iir, pm_mask; |
3b8d8d91 JB |
1132 | int max_freq; |
1133 | ||
35040562 | 1134 | rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS); |
36cdd013 | 1135 | if (IS_BROXTON(dev_priv)) { |
35040562 BP |
1136 | rp_state_cap = I915_READ(BXT_RP_STATE_CAP); |
1137 | gt_perf_status = I915_READ(BXT_GT_PERF_STATUS); | |
1138 | } else { | |
1139 | rp_state_cap = I915_READ(GEN6_RP_STATE_CAP); | |
1140 | gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS); | |
1141 | } | |
1142 | ||
3b8d8d91 | 1143 | /* RPSTAT1 is in the GT power well */ |
d1ebd816 BW |
1144 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
1145 | if (ret) | |
c8c8fb33 | 1146 | goto out; |
d1ebd816 | 1147 | |
59bad947 | 1148 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); |
3b8d8d91 | 1149 | |
8e8c06cd | 1150 | reqf = I915_READ(GEN6_RPNSWREQ); |
36cdd013 | 1151 | if (IS_GEN9(dev_priv)) |
60260a5b AG |
1152 | reqf >>= 23; |
1153 | else { | |
1154 | reqf &= ~GEN6_TURBO_DISABLE; | |
36cdd013 | 1155 | if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) |
60260a5b AG |
1156 | reqf >>= 24; |
1157 | else | |
1158 | reqf >>= 25; | |
1159 | } | |
7c59a9c1 | 1160 | reqf = intel_gpu_freq(dev_priv, reqf); |
8e8c06cd | 1161 | |
0d8f9491 CW |
1162 | rpmodectl = I915_READ(GEN6_RP_CONTROL); |
1163 | rpinclimit = I915_READ(GEN6_RP_UP_THRESHOLD); | |
1164 | rpdeclimit = I915_READ(GEN6_RP_DOWN_THRESHOLD); | |
1165 | ||
ccab5c82 | 1166 | rpstat = I915_READ(GEN6_RPSTAT1); |
d6cda9c7 AG |
1167 | rpupei = I915_READ(GEN6_RP_CUR_UP_EI) & GEN6_CURICONT_MASK; |
1168 | rpcurup = I915_READ(GEN6_RP_CUR_UP) & GEN6_CURBSYTAVG_MASK; | |
1169 | rpprevup = I915_READ(GEN6_RP_PREV_UP) & GEN6_CURBSYTAVG_MASK; | |
1170 | rpdownei = I915_READ(GEN6_RP_CUR_DOWN_EI) & GEN6_CURIAVG_MASK; | |
1171 | rpcurdown = I915_READ(GEN6_RP_CUR_DOWN) & GEN6_CURBSYTAVG_MASK; | |
1172 | rpprevdown = I915_READ(GEN6_RP_PREV_DOWN) & GEN6_CURBSYTAVG_MASK; | |
36cdd013 | 1173 | if (IS_GEN9(dev_priv)) |
60260a5b | 1174 | cagf = (rpstat & GEN9_CAGF_MASK) >> GEN9_CAGF_SHIFT; |
36cdd013 | 1175 | else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) |
f82855d3 BW |
1176 | cagf = (rpstat & HSW_CAGF_MASK) >> HSW_CAGF_SHIFT; |
1177 | else | |
1178 | cagf = (rpstat & GEN6_CAGF_MASK) >> GEN6_CAGF_SHIFT; | |
7c59a9c1 | 1179 | cagf = intel_gpu_freq(dev_priv, cagf); |
ccab5c82 | 1180 | |
59bad947 | 1181 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); |
d1ebd816 BW |
1182 | mutex_unlock(&dev->struct_mutex); |
1183 | ||
36cdd013 | 1184 | if (IS_GEN6(dev_priv) || IS_GEN7(dev_priv)) { |
9dd3c605 PZ |
1185 | pm_ier = I915_READ(GEN6_PMIER); |
1186 | pm_imr = I915_READ(GEN6_PMIMR); | |
1187 | pm_isr = I915_READ(GEN6_PMISR); | |
1188 | pm_iir = I915_READ(GEN6_PMIIR); | |
1189 | pm_mask = I915_READ(GEN6_PMINTRMSK); | |
1190 | } else { | |
1191 | pm_ier = I915_READ(GEN8_GT_IER(2)); | |
1192 | pm_imr = I915_READ(GEN8_GT_IMR(2)); | |
1193 | pm_isr = I915_READ(GEN8_GT_ISR(2)); | |
1194 | pm_iir = I915_READ(GEN8_GT_IIR(2)); | |
1195 | pm_mask = I915_READ(GEN6_PMINTRMSK); | |
1196 | } | |
0d8f9491 | 1197 | seq_printf(m, "PM IER=0x%08x IMR=0x%08x ISR=0x%08x IIR=0x%08x, MASK=0x%08x\n", |
9dd3c605 | 1198 | pm_ier, pm_imr, pm_isr, pm_iir, pm_mask); |
1800ad25 | 1199 | seq_printf(m, "pm_intr_keep: 0x%08x\n", dev_priv->rps.pm_intr_keep); |
3b8d8d91 | 1200 | seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status); |
3b8d8d91 | 1201 | seq_printf(m, "Render p-state ratio: %d\n", |
36cdd013 | 1202 | (gt_perf_status & (IS_GEN9(dev_priv) ? 0x1ff00 : 0xff00)) >> 8); |
3b8d8d91 JB |
1203 | seq_printf(m, "Render p-state VID: %d\n", |
1204 | gt_perf_status & 0xff); | |
1205 | seq_printf(m, "Render p-state limit: %d\n", | |
1206 | rp_state_limits & 0xff); | |
0d8f9491 CW |
1207 | seq_printf(m, "RPSTAT1: 0x%08x\n", rpstat); |
1208 | seq_printf(m, "RPMODECTL: 0x%08x\n", rpmodectl); | |
1209 | seq_printf(m, "RPINCLIMIT: 0x%08x\n", rpinclimit); | |
1210 | seq_printf(m, "RPDECLIMIT: 0x%08x\n", rpdeclimit); | |
8e8c06cd | 1211 | seq_printf(m, "RPNSWREQ: %dMHz\n", reqf); |
f82855d3 | 1212 | seq_printf(m, "CAGF: %dMHz\n", cagf); |
d6cda9c7 AG |
1213 | seq_printf(m, "RP CUR UP EI: %d (%dus)\n", |
1214 | rpupei, GT_PM_INTERVAL_TO_US(dev_priv, rpupei)); | |
1215 | seq_printf(m, "RP CUR UP: %d (%dus)\n", | |
1216 | rpcurup, GT_PM_INTERVAL_TO_US(dev_priv, rpcurup)); | |
1217 | seq_printf(m, "RP PREV UP: %d (%dus)\n", | |
1218 | rpprevup, GT_PM_INTERVAL_TO_US(dev_priv, rpprevup)); | |
d86ed34a CW |
1219 | seq_printf(m, "Up threshold: %d%%\n", |
1220 | dev_priv->rps.up_threshold); | |
1221 | ||
d6cda9c7 AG |
1222 | seq_printf(m, "RP CUR DOWN EI: %d (%dus)\n", |
1223 | rpdownei, GT_PM_INTERVAL_TO_US(dev_priv, rpdownei)); | |
1224 | seq_printf(m, "RP CUR DOWN: %d (%dus)\n", | |
1225 | rpcurdown, GT_PM_INTERVAL_TO_US(dev_priv, rpcurdown)); | |
1226 | seq_printf(m, "RP PREV DOWN: %d (%dus)\n", | |
1227 | rpprevdown, GT_PM_INTERVAL_TO_US(dev_priv, rpprevdown)); | |
d86ed34a CW |
1228 | seq_printf(m, "Down threshold: %d%%\n", |
1229 | dev_priv->rps.down_threshold); | |
3b8d8d91 | 1230 | |
36cdd013 | 1231 | max_freq = (IS_BROXTON(dev_priv) ? rp_state_cap >> 0 : |
35040562 | 1232 | rp_state_cap >> 16) & 0xff; |
36cdd013 | 1233 | max_freq *= (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv) ? |
ef11bdb3 | 1234 | GEN9_FREQ_SCALER : 1); |
3b8d8d91 | 1235 | seq_printf(m, "Lowest (RPN) frequency: %dMHz\n", |
7c59a9c1 | 1236 | intel_gpu_freq(dev_priv, max_freq)); |
3b8d8d91 JB |
1237 | |
1238 | max_freq = (rp_state_cap & 0xff00) >> 8; | |
36cdd013 | 1239 | max_freq *= (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv) ? |
ef11bdb3 | 1240 | GEN9_FREQ_SCALER : 1); |
3b8d8d91 | 1241 | seq_printf(m, "Nominal (RP1) frequency: %dMHz\n", |
7c59a9c1 | 1242 | intel_gpu_freq(dev_priv, max_freq)); |
3b8d8d91 | 1243 | |
36cdd013 | 1244 | max_freq = (IS_BROXTON(dev_priv) ? rp_state_cap >> 16 : |
35040562 | 1245 | rp_state_cap >> 0) & 0xff; |
36cdd013 | 1246 | max_freq *= (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv) ? |
ef11bdb3 | 1247 | GEN9_FREQ_SCALER : 1); |
3b8d8d91 | 1248 | seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n", |
7c59a9c1 | 1249 | intel_gpu_freq(dev_priv, max_freq)); |
31c77388 | 1250 | seq_printf(m, "Max overclocked frequency: %dMHz\n", |
7c59a9c1 | 1251 | intel_gpu_freq(dev_priv, dev_priv->rps.max_freq)); |
aed242ff | 1252 | |
d86ed34a CW |
1253 | seq_printf(m, "Current freq: %d MHz\n", |
1254 | intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq)); | |
1255 | seq_printf(m, "Actual freq: %d MHz\n", cagf); | |
aed242ff CW |
1256 | seq_printf(m, "Idle freq: %d MHz\n", |
1257 | intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq)); | |
d86ed34a CW |
1258 | seq_printf(m, "Min freq: %d MHz\n", |
1259 | intel_gpu_freq(dev_priv, dev_priv->rps.min_freq)); | |
29ecd78d CW |
1260 | seq_printf(m, "Boost freq: %d MHz\n", |
1261 | intel_gpu_freq(dev_priv, dev_priv->rps.boost_freq)); | |
d86ed34a CW |
1262 | seq_printf(m, "Max freq: %d MHz\n", |
1263 | intel_gpu_freq(dev_priv, dev_priv->rps.max_freq)); | |
1264 | seq_printf(m, | |
1265 | "efficient (RPe) frequency: %d MHz\n", | |
1266 | intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq)); | |
3b8d8d91 | 1267 | } else { |
267f0c90 | 1268 | seq_puts(m, "no P-state info available\n"); |
3b8d8d91 | 1269 | } |
f97108d1 | 1270 | |
1170f28c MK |
1271 | seq_printf(m, "Current CD clock frequency: %d kHz\n", dev_priv->cdclk_freq); |
1272 | seq_printf(m, "Max CD clock frequency: %d kHz\n", dev_priv->max_cdclk_freq); | |
1273 | seq_printf(m, "Max pixel clock frequency: %d kHz\n", dev_priv->max_dotclk_freq); | |
1274 | ||
c8c8fb33 PZ |
1275 | out: |
1276 | intel_runtime_pm_put(dev_priv); | |
1277 | return ret; | |
f97108d1 JB |
1278 | } |
1279 | ||
d636951e BW |
1280 | static void i915_instdone_info(struct drm_i915_private *dev_priv, |
1281 | struct seq_file *m, | |
1282 | struct intel_instdone *instdone) | |
1283 | { | |
f9e61372 BW |
1284 | int slice; |
1285 | int subslice; | |
1286 | ||
d636951e BW |
1287 | seq_printf(m, "\t\tINSTDONE: 0x%08x\n", |
1288 | instdone->instdone); | |
1289 | ||
1290 | if (INTEL_GEN(dev_priv) <= 3) | |
1291 | return; | |
1292 | ||
1293 | seq_printf(m, "\t\tSC_INSTDONE: 0x%08x\n", | |
1294 | instdone->slice_common); | |
1295 | ||
1296 | if (INTEL_GEN(dev_priv) <= 6) | |
1297 | return; | |
1298 | ||
f9e61372 BW |
1299 | for_each_instdone_slice_subslice(dev_priv, slice, subslice) |
1300 | seq_printf(m, "\t\tSAMPLER_INSTDONE[%d][%d]: 0x%08x\n", | |
1301 | slice, subslice, instdone->sampler[slice][subslice]); | |
1302 | ||
1303 | for_each_instdone_slice_subslice(dev_priv, slice, subslice) | |
1304 | seq_printf(m, "\t\tROW_INSTDONE[%d][%d]: 0x%08x\n", | |
1305 | slice, subslice, instdone->row[slice][subslice]); | |
d636951e BW |
1306 | } |
1307 | ||
f654449a CW |
1308 | static int i915_hangcheck_info(struct seq_file *m, void *unused) |
1309 | { | |
36cdd013 | 1310 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
e2f80391 | 1311 | struct intel_engine_cs *engine; |
666796da TU |
1312 | u64 acthd[I915_NUM_ENGINES]; |
1313 | u32 seqno[I915_NUM_ENGINES]; | |
d636951e | 1314 | struct intel_instdone instdone; |
c3232b18 | 1315 | enum intel_engine_id id; |
f654449a | 1316 | |
8af29b0c CW |
1317 | if (test_bit(I915_WEDGED, &dev_priv->gpu_error.flags)) |
1318 | seq_printf(m, "Wedged\n"); | |
1319 | if (test_bit(I915_RESET_IN_PROGRESS, &dev_priv->gpu_error.flags)) | |
1320 | seq_printf(m, "Reset in progress\n"); | |
1321 | if (waitqueue_active(&dev_priv->gpu_error.wait_queue)) | |
1322 | seq_printf(m, "Waiter holding struct mutex\n"); | |
1323 | if (waitqueue_active(&dev_priv->gpu_error.reset_queue)) | |
1324 | seq_printf(m, "struct_mutex blocked for reset\n"); | |
1325 | ||
f654449a CW |
1326 | if (!i915.enable_hangcheck) { |
1327 | seq_printf(m, "Hangcheck disabled\n"); | |
1328 | return 0; | |
1329 | } | |
1330 | ||
ebbc7546 MK |
1331 | intel_runtime_pm_get(dev_priv); |
1332 | ||
c3232b18 | 1333 | for_each_engine_id(engine, dev_priv, id) { |
7e37f889 | 1334 | acthd[id] = intel_engine_get_active_head(engine); |
1b7744e7 | 1335 | seqno[id] = intel_engine_get_seqno(engine); |
ebbc7546 MK |
1336 | } |
1337 | ||
d636951e | 1338 | i915_get_engine_instdone(dev_priv, RCS, &instdone); |
61642ff0 | 1339 | |
ebbc7546 MK |
1340 | intel_runtime_pm_put(dev_priv); |
1341 | ||
f654449a CW |
1342 | if (delayed_work_pending(&dev_priv->gpu_error.hangcheck_work)) { |
1343 | seq_printf(m, "Hangcheck active, fires in %dms\n", | |
1344 | jiffies_to_msecs(dev_priv->gpu_error.hangcheck_work.timer.expires - | |
1345 | jiffies)); | |
1346 | } else | |
1347 | seq_printf(m, "Hangcheck inactive\n"); | |
1348 | ||
c3232b18 | 1349 | for_each_engine_id(engine, dev_priv, id) { |
e2f80391 | 1350 | seq_printf(m, "%s:\n", engine->name); |
14fd0d6d CW |
1351 | seq_printf(m, "\tseqno = %x [current %x, last %x]\n", |
1352 | engine->hangcheck.seqno, | |
1353 | seqno[id], | |
1354 | engine->last_submitted_seqno); | |
83348ba8 CW |
1355 | seq_printf(m, "\twaiters? %s, fake irq active? %s\n", |
1356 | yesno(intel_engine_has_waiter(engine)), | |
1357 | yesno(test_bit(engine->id, | |
1358 | &dev_priv->gpu_error.missed_irq_rings))); | |
f654449a | 1359 | seq_printf(m, "\tACTHD = 0x%08llx [current 0x%08llx]\n", |
e2f80391 | 1360 | (long long)engine->hangcheck.acthd, |
c3232b18 | 1361 | (long long)acthd[id]); |
e2f80391 TU |
1362 | seq_printf(m, "\tscore = %d\n", engine->hangcheck.score); |
1363 | seq_printf(m, "\taction = %d\n", engine->hangcheck.action); | |
61642ff0 | 1364 | |
e2f80391 | 1365 | if (engine->id == RCS) { |
d636951e | 1366 | seq_puts(m, "\tinstdone read =\n"); |
61642ff0 | 1367 | |
d636951e | 1368 | i915_instdone_info(dev_priv, m, &instdone); |
61642ff0 | 1369 | |
d636951e | 1370 | seq_puts(m, "\tinstdone accu =\n"); |
61642ff0 | 1371 | |
d636951e BW |
1372 | i915_instdone_info(dev_priv, m, |
1373 | &engine->hangcheck.instdone); | |
61642ff0 | 1374 | } |
f654449a CW |
1375 | } |
1376 | ||
1377 | return 0; | |
1378 | } | |
1379 | ||
4d85529d | 1380 | static int ironlake_drpc_info(struct seq_file *m) |
f97108d1 | 1381 | { |
36cdd013 DW |
1382 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
1383 | struct drm_device *dev = &dev_priv->drm; | |
616fdb5a BW |
1384 | u32 rgvmodectl, rstdbyctl; |
1385 | u16 crstandvid; | |
1386 | int ret; | |
1387 | ||
1388 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
1389 | if (ret) | |
1390 | return ret; | |
c8c8fb33 | 1391 | intel_runtime_pm_get(dev_priv); |
616fdb5a BW |
1392 | |
1393 | rgvmodectl = I915_READ(MEMMODECTL); | |
1394 | rstdbyctl = I915_READ(RSTDBYCTL); | |
1395 | crstandvid = I915_READ16(CRSTANDVID); | |
1396 | ||
c8c8fb33 | 1397 | intel_runtime_pm_put(dev_priv); |
616fdb5a | 1398 | mutex_unlock(&dev->struct_mutex); |
f97108d1 | 1399 | |
742f491d | 1400 | seq_printf(m, "HD boost: %s\n", yesno(rgvmodectl & MEMMODE_BOOST_EN)); |
f97108d1 JB |
1401 | seq_printf(m, "Boost freq: %d\n", |
1402 | (rgvmodectl & MEMMODE_BOOST_FREQ_MASK) >> | |
1403 | MEMMODE_BOOST_FREQ_SHIFT); | |
1404 | seq_printf(m, "HW control enabled: %s\n", | |
742f491d | 1405 | yesno(rgvmodectl & MEMMODE_HWIDLE_EN)); |
f97108d1 | 1406 | seq_printf(m, "SW control enabled: %s\n", |
742f491d | 1407 | yesno(rgvmodectl & MEMMODE_SWMODE_EN)); |
f97108d1 | 1408 | seq_printf(m, "Gated voltage change: %s\n", |
742f491d | 1409 | yesno(rgvmodectl & MEMMODE_RCLK_GATE)); |
f97108d1 JB |
1410 | seq_printf(m, "Starting frequency: P%d\n", |
1411 | (rgvmodectl & MEMMODE_FSTART_MASK) >> MEMMODE_FSTART_SHIFT); | |
7648fa99 | 1412 | seq_printf(m, "Max P-state: P%d\n", |
f97108d1 | 1413 | (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT); |
7648fa99 JB |
1414 | seq_printf(m, "Min P-state: P%d\n", (rgvmodectl & MEMMODE_FMIN_MASK)); |
1415 | seq_printf(m, "RS1 VID: %d\n", (crstandvid & 0x3f)); | |
1416 | seq_printf(m, "RS2 VID: %d\n", ((crstandvid >> 8) & 0x3f)); | |
1417 | seq_printf(m, "Render standby enabled: %s\n", | |
742f491d | 1418 | yesno(!(rstdbyctl & RCX_SW_EXIT))); |
267f0c90 | 1419 | seq_puts(m, "Current RS state: "); |
88271da3 JB |
1420 | switch (rstdbyctl & RSX_STATUS_MASK) { |
1421 | case RSX_STATUS_ON: | |
267f0c90 | 1422 | seq_puts(m, "on\n"); |
88271da3 JB |
1423 | break; |
1424 | case RSX_STATUS_RC1: | |
267f0c90 | 1425 | seq_puts(m, "RC1\n"); |
88271da3 JB |
1426 | break; |
1427 | case RSX_STATUS_RC1E: | |
267f0c90 | 1428 | seq_puts(m, "RC1E\n"); |
88271da3 JB |
1429 | break; |
1430 | case RSX_STATUS_RS1: | |
267f0c90 | 1431 | seq_puts(m, "RS1\n"); |
88271da3 JB |
1432 | break; |
1433 | case RSX_STATUS_RS2: | |
267f0c90 | 1434 | seq_puts(m, "RS2 (RC6)\n"); |
88271da3 JB |
1435 | break; |
1436 | case RSX_STATUS_RS3: | |
267f0c90 | 1437 | seq_puts(m, "RC3 (RC6+)\n"); |
88271da3 JB |
1438 | break; |
1439 | default: | |
267f0c90 | 1440 | seq_puts(m, "unknown\n"); |
88271da3 JB |
1441 | break; |
1442 | } | |
f97108d1 JB |
1443 | |
1444 | return 0; | |
1445 | } | |
1446 | ||
f65367b5 | 1447 | static int i915_forcewake_domains(struct seq_file *m, void *data) |
669ab5aa | 1448 | { |
36cdd013 | 1449 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
b2cff0db | 1450 | struct intel_uncore_forcewake_domain *fw_domain; |
b2cff0db CW |
1451 | |
1452 | spin_lock_irq(&dev_priv->uncore.lock); | |
33c582c1 | 1453 | for_each_fw_domain(fw_domain, dev_priv) { |
b2cff0db | 1454 | seq_printf(m, "%s.wake_count = %u\n", |
33c582c1 | 1455 | intel_uncore_forcewake_domain_to_str(fw_domain->id), |
b2cff0db CW |
1456 | fw_domain->wake_count); |
1457 | } | |
1458 | spin_unlock_irq(&dev_priv->uncore.lock); | |
669ab5aa | 1459 | |
b2cff0db CW |
1460 | return 0; |
1461 | } | |
1462 | ||
1463 | static int vlv_drpc_info(struct seq_file *m) | |
1464 | { | |
36cdd013 | 1465 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
6b312cd3 | 1466 | u32 rpmodectl1, rcctl1, pw_status; |
669ab5aa | 1467 | |
d46c0517 ID |
1468 | intel_runtime_pm_get(dev_priv); |
1469 | ||
6b312cd3 | 1470 | pw_status = I915_READ(VLV_GTLC_PW_STATUS); |
669ab5aa D |
1471 | rpmodectl1 = I915_READ(GEN6_RP_CONTROL); |
1472 | rcctl1 = I915_READ(GEN6_RC_CONTROL); | |
1473 | ||
d46c0517 ID |
1474 | intel_runtime_pm_put(dev_priv); |
1475 | ||
669ab5aa D |
1476 | seq_printf(m, "Video Turbo Mode: %s\n", |
1477 | yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO)); | |
1478 | seq_printf(m, "Turbo enabled: %s\n", | |
1479 | yesno(rpmodectl1 & GEN6_RP_ENABLE)); | |
1480 | seq_printf(m, "HW control enabled: %s\n", | |
1481 | yesno(rpmodectl1 & GEN6_RP_ENABLE)); | |
1482 | seq_printf(m, "SW control enabled: %s\n", | |
1483 | yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) == | |
1484 | GEN6_RP_MEDIA_SW_MODE)); | |
1485 | seq_printf(m, "RC6 Enabled: %s\n", | |
1486 | yesno(rcctl1 & (GEN7_RC_CTL_TO_MODE | | |
1487 | GEN6_RC_CTL_EI_MODE(1)))); | |
1488 | seq_printf(m, "Render Power Well: %s\n", | |
6b312cd3 | 1489 | (pw_status & VLV_GTLC_PW_RENDER_STATUS_MASK) ? "Up" : "Down"); |
669ab5aa | 1490 | seq_printf(m, "Media Power Well: %s\n", |
6b312cd3 | 1491 | (pw_status & VLV_GTLC_PW_MEDIA_STATUS_MASK) ? "Up" : "Down"); |
669ab5aa | 1492 | |
9cc19be5 ID |
1493 | seq_printf(m, "Render RC6 residency since boot: %u\n", |
1494 | I915_READ(VLV_GT_RENDER_RC6)); | |
1495 | seq_printf(m, "Media RC6 residency since boot: %u\n", | |
1496 | I915_READ(VLV_GT_MEDIA_RC6)); | |
1497 | ||
f65367b5 | 1498 | return i915_forcewake_domains(m, NULL); |
669ab5aa D |
1499 | } |
1500 | ||
4d85529d BW |
1501 | static int gen6_drpc_info(struct seq_file *m) |
1502 | { | |
36cdd013 DW |
1503 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
1504 | struct drm_device *dev = &dev_priv->drm; | |
ecd8faea | 1505 | u32 rpmodectl1, gt_core_status, rcctl1, rc6vids = 0; |
f2dd7578 | 1506 | u32 gen9_powergate_enable = 0, gen9_powergate_status = 0; |
93b525dc | 1507 | unsigned forcewake_count; |
aee56cff | 1508 | int count = 0, ret; |
4d85529d BW |
1509 | |
1510 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
1511 | if (ret) | |
1512 | return ret; | |
c8c8fb33 | 1513 | intel_runtime_pm_get(dev_priv); |
4d85529d | 1514 | |
907b28c5 | 1515 | spin_lock_irq(&dev_priv->uncore.lock); |
b2cff0db | 1516 | forcewake_count = dev_priv->uncore.fw_domain[FW_DOMAIN_ID_RENDER].wake_count; |
907b28c5 | 1517 | spin_unlock_irq(&dev_priv->uncore.lock); |
93b525dc DV |
1518 | |
1519 | if (forcewake_count) { | |
267f0c90 DL |
1520 | seq_puts(m, "RC information inaccurate because somebody " |
1521 | "holds a forcewake reference \n"); | |
4d85529d BW |
1522 | } else { |
1523 | /* NB: we cannot use forcewake, else we read the wrong values */ | |
1524 | while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1)) | |
1525 | udelay(10); | |
1526 | seq_printf(m, "RC information accurate: %s\n", yesno(count < 51)); | |
1527 | } | |
1528 | ||
75aa3f63 | 1529 | gt_core_status = I915_READ_FW(GEN6_GT_CORE_STATUS); |
ed71f1b4 | 1530 | trace_i915_reg_rw(false, GEN6_GT_CORE_STATUS, gt_core_status, 4, true); |
4d85529d BW |
1531 | |
1532 | rpmodectl1 = I915_READ(GEN6_RP_CONTROL); | |
1533 | rcctl1 = I915_READ(GEN6_RC_CONTROL); | |
36cdd013 | 1534 | if (INTEL_GEN(dev_priv) >= 9) { |
f2dd7578 AG |
1535 | gen9_powergate_enable = I915_READ(GEN9_PG_ENABLE); |
1536 | gen9_powergate_status = I915_READ(GEN9_PWRGT_DOMAIN_STATUS); | |
1537 | } | |
4d85529d | 1538 | mutex_unlock(&dev->struct_mutex); |
44cbd338 BW |
1539 | mutex_lock(&dev_priv->rps.hw_lock); |
1540 | sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids); | |
1541 | mutex_unlock(&dev_priv->rps.hw_lock); | |
4d85529d | 1542 | |
c8c8fb33 PZ |
1543 | intel_runtime_pm_put(dev_priv); |
1544 | ||
4d85529d BW |
1545 | seq_printf(m, "Video Turbo Mode: %s\n", |
1546 | yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO)); | |
1547 | seq_printf(m, "HW control enabled: %s\n", | |
1548 | yesno(rpmodectl1 & GEN6_RP_ENABLE)); | |
1549 | seq_printf(m, "SW control enabled: %s\n", | |
1550 | yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) == | |
1551 | GEN6_RP_MEDIA_SW_MODE)); | |
fff24e21 | 1552 | seq_printf(m, "RC1e Enabled: %s\n", |
4d85529d BW |
1553 | yesno(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE)); |
1554 | seq_printf(m, "RC6 Enabled: %s\n", | |
1555 | yesno(rcctl1 & GEN6_RC_CTL_RC6_ENABLE)); | |
36cdd013 | 1556 | if (INTEL_GEN(dev_priv) >= 9) { |
f2dd7578 AG |
1557 | seq_printf(m, "Render Well Gating Enabled: %s\n", |
1558 | yesno(gen9_powergate_enable & GEN9_RENDER_PG_ENABLE)); | |
1559 | seq_printf(m, "Media Well Gating Enabled: %s\n", | |
1560 | yesno(gen9_powergate_enable & GEN9_MEDIA_PG_ENABLE)); | |
1561 | } | |
4d85529d BW |
1562 | seq_printf(m, "Deep RC6 Enabled: %s\n", |
1563 | yesno(rcctl1 & GEN6_RC_CTL_RC6p_ENABLE)); | |
1564 | seq_printf(m, "Deepest RC6 Enabled: %s\n", | |
1565 | yesno(rcctl1 & GEN6_RC_CTL_RC6pp_ENABLE)); | |
267f0c90 | 1566 | seq_puts(m, "Current RC state: "); |
4d85529d BW |
1567 | switch (gt_core_status & GEN6_RCn_MASK) { |
1568 | case GEN6_RC0: | |
1569 | if (gt_core_status & GEN6_CORE_CPD_STATE_MASK) | |
267f0c90 | 1570 | seq_puts(m, "Core Power Down\n"); |
4d85529d | 1571 | else |
267f0c90 | 1572 | seq_puts(m, "on\n"); |
4d85529d BW |
1573 | break; |
1574 | case GEN6_RC3: | |
267f0c90 | 1575 | seq_puts(m, "RC3\n"); |
4d85529d BW |
1576 | break; |
1577 | case GEN6_RC6: | |
267f0c90 | 1578 | seq_puts(m, "RC6\n"); |
4d85529d BW |
1579 | break; |
1580 | case GEN6_RC7: | |
267f0c90 | 1581 | seq_puts(m, "RC7\n"); |
4d85529d BW |
1582 | break; |
1583 | default: | |
267f0c90 | 1584 | seq_puts(m, "Unknown\n"); |
4d85529d BW |
1585 | break; |
1586 | } | |
1587 | ||
1588 | seq_printf(m, "Core Power Down: %s\n", | |
1589 | yesno(gt_core_status & GEN6_CORE_CPD_STATE_MASK)); | |
36cdd013 | 1590 | if (INTEL_GEN(dev_priv) >= 9) { |
f2dd7578 AG |
1591 | seq_printf(m, "Render Power Well: %s\n", |
1592 | (gen9_powergate_status & | |
1593 | GEN9_PWRGT_RENDER_STATUS_MASK) ? "Up" : "Down"); | |
1594 | seq_printf(m, "Media Power Well: %s\n", | |
1595 | (gen9_powergate_status & | |
1596 | GEN9_PWRGT_MEDIA_STATUS_MASK) ? "Up" : "Down"); | |
1597 | } | |
cce66a28 BW |
1598 | |
1599 | /* Not exactly sure what this is */ | |
1600 | seq_printf(m, "RC6 \"Locked to RPn\" residency since boot: %u\n", | |
1601 | I915_READ(GEN6_GT_GFX_RC6_LOCKED)); | |
1602 | seq_printf(m, "RC6 residency since boot: %u\n", | |
1603 | I915_READ(GEN6_GT_GFX_RC6)); | |
1604 | seq_printf(m, "RC6+ residency since boot: %u\n", | |
1605 | I915_READ(GEN6_GT_GFX_RC6p)); | |
1606 | seq_printf(m, "RC6++ residency since boot: %u\n", | |
1607 | I915_READ(GEN6_GT_GFX_RC6pp)); | |
1608 | ||
ecd8faea BW |
1609 | seq_printf(m, "RC6 voltage: %dmV\n", |
1610 | GEN6_DECODE_RC6_VID(((rc6vids >> 0) & 0xff))); | |
1611 | seq_printf(m, "RC6+ voltage: %dmV\n", | |
1612 | GEN6_DECODE_RC6_VID(((rc6vids >> 8) & 0xff))); | |
1613 | seq_printf(m, "RC6++ voltage: %dmV\n", | |
1614 | GEN6_DECODE_RC6_VID(((rc6vids >> 16) & 0xff))); | |
f2dd7578 | 1615 | return i915_forcewake_domains(m, NULL); |
4d85529d BW |
1616 | } |
1617 | ||
1618 | static int i915_drpc_info(struct seq_file *m, void *unused) | |
1619 | { | |
36cdd013 | 1620 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
4d85529d | 1621 | |
36cdd013 | 1622 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) |
669ab5aa | 1623 | return vlv_drpc_info(m); |
36cdd013 | 1624 | else if (INTEL_GEN(dev_priv) >= 6) |
4d85529d BW |
1625 | return gen6_drpc_info(m); |
1626 | else | |
1627 | return ironlake_drpc_info(m); | |
1628 | } | |
1629 | ||
9a851789 DV |
1630 | static int i915_frontbuffer_tracking(struct seq_file *m, void *unused) |
1631 | { | |
36cdd013 | 1632 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
9a851789 DV |
1633 | |
1634 | seq_printf(m, "FB tracking busy bits: 0x%08x\n", | |
1635 | dev_priv->fb_tracking.busy_bits); | |
1636 | ||
1637 | seq_printf(m, "FB tracking flip bits: 0x%08x\n", | |
1638 | dev_priv->fb_tracking.flip_bits); | |
1639 | ||
1640 | return 0; | |
1641 | } | |
1642 | ||
b5e50c3f JB |
1643 | static int i915_fbc_status(struct seq_file *m, void *unused) |
1644 | { | |
36cdd013 | 1645 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
b5e50c3f | 1646 | |
36cdd013 | 1647 | if (!HAS_FBC(dev_priv)) { |
267f0c90 | 1648 | seq_puts(m, "FBC unsupported on this chipset\n"); |
b5e50c3f JB |
1649 | return 0; |
1650 | } | |
1651 | ||
36623ef8 | 1652 | intel_runtime_pm_get(dev_priv); |
25ad93fd | 1653 | mutex_lock(&dev_priv->fbc.lock); |
36623ef8 | 1654 | |
0e631adc | 1655 | if (intel_fbc_is_active(dev_priv)) |
267f0c90 | 1656 | seq_puts(m, "FBC enabled\n"); |
2e8144a5 PZ |
1657 | else |
1658 | seq_printf(m, "FBC disabled: %s\n", | |
bf6189c6 | 1659 | dev_priv->fbc.no_fbc_reason); |
36623ef8 | 1660 | |
bc4ec7c8 NV |
1661 | if (intel_fbc_is_active(dev_priv) && |
1662 | INTEL_GEN(dev_priv) >= 7) | |
31b9df10 PZ |
1663 | seq_printf(m, "Compressing: %s\n", |
1664 | yesno(I915_READ(FBC_STATUS2) & | |
1665 | FBC_COMPRESSION_MASK)); | |
1666 | ||
25ad93fd | 1667 | mutex_unlock(&dev_priv->fbc.lock); |
36623ef8 PZ |
1668 | intel_runtime_pm_put(dev_priv); |
1669 | ||
b5e50c3f JB |
1670 | return 0; |
1671 | } | |
1672 | ||
da46f936 RV |
1673 | static int i915_fbc_fc_get(void *data, u64 *val) |
1674 | { | |
36cdd013 | 1675 | struct drm_i915_private *dev_priv = data; |
da46f936 | 1676 | |
36cdd013 | 1677 | if (INTEL_GEN(dev_priv) < 7 || !HAS_FBC(dev_priv)) |
da46f936 RV |
1678 | return -ENODEV; |
1679 | ||
da46f936 | 1680 | *val = dev_priv->fbc.false_color; |
da46f936 RV |
1681 | |
1682 | return 0; | |
1683 | } | |
1684 | ||
1685 | static int i915_fbc_fc_set(void *data, u64 val) | |
1686 | { | |
36cdd013 | 1687 | struct drm_i915_private *dev_priv = data; |
da46f936 RV |
1688 | u32 reg; |
1689 | ||
36cdd013 | 1690 | if (INTEL_GEN(dev_priv) < 7 || !HAS_FBC(dev_priv)) |
da46f936 RV |
1691 | return -ENODEV; |
1692 | ||
25ad93fd | 1693 | mutex_lock(&dev_priv->fbc.lock); |
da46f936 RV |
1694 | |
1695 | reg = I915_READ(ILK_DPFC_CONTROL); | |
1696 | dev_priv->fbc.false_color = val; | |
1697 | ||
1698 | I915_WRITE(ILK_DPFC_CONTROL, val ? | |
1699 | (reg | FBC_CTL_FALSE_COLOR) : | |
1700 | (reg & ~FBC_CTL_FALSE_COLOR)); | |
1701 | ||
25ad93fd | 1702 | mutex_unlock(&dev_priv->fbc.lock); |
da46f936 RV |
1703 | return 0; |
1704 | } | |
1705 | ||
1706 | DEFINE_SIMPLE_ATTRIBUTE(i915_fbc_fc_fops, | |
1707 | i915_fbc_fc_get, i915_fbc_fc_set, | |
1708 | "%llu\n"); | |
1709 | ||
92d44621 PZ |
1710 | static int i915_ips_status(struct seq_file *m, void *unused) |
1711 | { | |
36cdd013 | 1712 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
92d44621 | 1713 | |
36cdd013 | 1714 | if (!HAS_IPS(dev_priv)) { |
92d44621 PZ |
1715 | seq_puts(m, "not supported\n"); |
1716 | return 0; | |
1717 | } | |
1718 | ||
36623ef8 PZ |
1719 | intel_runtime_pm_get(dev_priv); |
1720 | ||
0eaa53f0 RV |
1721 | seq_printf(m, "Enabled by kernel parameter: %s\n", |
1722 | yesno(i915.enable_ips)); | |
1723 | ||
36cdd013 | 1724 | if (INTEL_GEN(dev_priv) >= 8) { |
0eaa53f0 RV |
1725 | seq_puts(m, "Currently: unknown\n"); |
1726 | } else { | |
1727 | if (I915_READ(IPS_CTL) & IPS_ENABLE) | |
1728 | seq_puts(m, "Currently: enabled\n"); | |
1729 | else | |
1730 | seq_puts(m, "Currently: disabled\n"); | |
1731 | } | |
92d44621 | 1732 | |
36623ef8 PZ |
1733 | intel_runtime_pm_put(dev_priv); |
1734 | ||
92d44621 PZ |
1735 | return 0; |
1736 | } | |
1737 | ||
4a9bef37 JB |
1738 | static int i915_sr_status(struct seq_file *m, void *unused) |
1739 | { | |
36cdd013 | 1740 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
4a9bef37 JB |
1741 | bool sr_enabled = false; |
1742 | ||
36623ef8 PZ |
1743 | intel_runtime_pm_get(dev_priv); |
1744 | ||
36cdd013 | 1745 | if (HAS_PCH_SPLIT(dev_priv)) |
5ba2aaaa | 1746 | sr_enabled = I915_READ(WM1_LP_ILK) & WM1_LP_SR_EN; |
36cdd013 DW |
1747 | else if (IS_CRESTLINE(dev_priv) || IS_G4X(dev_priv) || |
1748 | IS_I945G(dev_priv) || IS_I945GM(dev_priv)) | |
4a9bef37 | 1749 | sr_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN; |
36cdd013 | 1750 | else if (IS_I915GM(dev_priv)) |
4a9bef37 | 1751 | sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN; |
36cdd013 | 1752 | else if (IS_PINEVIEW(dev_priv)) |
4a9bef37 | 1753 | sr_enabled = I915_READ(DSPFW3) & PINEVIEW_SELF_REFRESH_EN; |
36cdd013 | 1754 | else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) |
77b64555 | 1755 | sr_enabled = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN; |
4a9bef37 | 1756 | |
36623ef8 PZ |
1757 | intel_runtime_pm_put(dev_priv); |
1758 | ||
5ba2aaaa CW |
1759 | seq_printf(m, "self-refresh: %s\n", |
1760 | sr_enabled ? "enabled" : "disabled"); | |
4a9bef37 JB |
1761 | |
1762 | return 0; | |
1763 | } | |
1764 | ||
7648fa99 JB |
1765 | static int i915_emon_status(struct seq_file *m, void *unused) |
1766 | { | |
36cdd013 DW |
1767 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
1768 | struct drm_device *dev = &dev_priv->drm; | |
7648fa99 | 1769 | unsigned long temp, chipset, gfx; |
de227ef0 CW |
1770 | int ret; |
1771 | ||
36cdd013 | 1772 | if (!IS_GEN5(dev_priv)) |
582be6b4 CW |
1773 | return -ENODEV; |
1774 | ||
de227ef0 CW |
1775 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
1776 | if (ret) | |
1777 | return ret; | |
7648fa99 JB |
1778 | |
1779 | temp = i915_mch_val(dev_priv); | |
1780 | chipset = i915_chipset_val(dev_priv); | |
1781 | gfx = i915_gfx_val(dev_priv); | |
de227ef0 | 1782 | mutex_unlock(&dev->struct_mutex); |
7648fa99 JB |
1783 | |
1784 | seq_printf(m, "GMCH temp: %ld\n", temp); | |
1785 | seq_printf(m, "Chipset power: %ld\n", chipset); | |
1786 | seq_printf(m, "GFX power: %ld\n", gfx); | |
1787 | seq_printf(m, "Total power: %ld\n", chipset + gfx); | |
1788 | ||
1789 | return 0; | |
1790 | } | |
1791 | ||
23b2f8bb JB |
1792 | static int i915_ring_freq_table(struct seq_file *m, void *unused) |
1793 | { | |
36cdd013 | 1794 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
5bfa0199 | 1795 | int ret = 0; |
23b2f8bb | 1796 | int gpu_freq, ia_freq; |
f936ec34 | 1797 | unsigned int max_gpu_freq, min_gpu_freq; |
23b2f8bb | 1798 | |
26310346 | 1799 | if (!HAS_LLC(dev_priv)) { |
267f0c90 | 1800 | seq_puts(m, "unsupported on this chipset\n"); |
23b2f8bb JB |
1801 | return 0; |
1802 | } | |
1803 | ||
5bfa0199 PZ |
1804 | intel_runtime_pm_get(dev_priv); |
1805 | ||
4fc688ce | 1806 | ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock); |
23b2f8bb | 1807 | if (ret) |
5bfa0199 | 1808 | goto out; |
23b2f8bb | 1809 | |
36cdd013 | 1810 | if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) { |
f936ec34 AG |
1811 | /* Convert GT frequency to 50 HZ units */ |
1812 | min_gpu_freq = | |
1813 | dev_priv->rps.min_freq_softlimit / GEN9_FREQ_SCALER; | |
1814 | max_gpu_freq = | |
1815 | dev_priv->rps.max_freq_softlimit / GEN9_FREQ_SCALER; | |
1816 | } else { | |
1817 | min_gpu_freq = dev_priv->rps.min_freq_softlimit; | |
1818 | max_gpu_freq = dev_priv->rps.max_freq_softlimit; | |
1819 | } | |
1820 | ||
267f0c90 | 1821 | seq_puts(m, "GPU freq (MHz)\tEffective CPU freq (MHz)\tEffective Ring freq (MHz)\n"); |
23b2f8bb | 1822 | |
f936ec34 | 1823 | for (gpu_freq = min_gpu_freq; gpu_freq <= max_gpu_freq; gpu_freq++) { |
42c0526c BW |
1824 | ia_freq = gpu_freq; |
1825 | sandybridge_pcode_read(dev_priv, | |
1826 | GEN6_PCODE_READ_MIN_FREQ_TABLE, | |
1827 | &ia_freq); | |
3ebecd07 | 1828 | seq_printf(m, "%d\t\t%d\t\t\t\t%d\n", |
f936ec34 | 1829 | intel_gpu_freq(dev_priv, (gpu_freq * |
36cdd013 | 1830 | (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv) ? |
ef11bdb3 | 1831 | GEN9_FREQ_SCALER : 1))), |
3ebecd07 CW |
1832 | ((ia_freq >> 0) & 0xff) * 100, |
1833 | ((ia_freq >> 8) & 0xff) * 100); | |
23b2f8bb JB |
1834 | } |
1835 | ||
4fc688ce | 1836 | mutex_unlock(&dev_priv->rps.hw_lock); |
23b2f8bb | 1837 | |
5bfa0199 PZ |
1838 | out: |
1839 | intel_runtime_pm_put(dev_priv); | |
1840 | return ret; | |
23b2f8bb JB |
1841 | } |
1842 | ||
44834a67 CW |
1843 | static int i915_opregion(struct seq_file *m, void *unused) |
1844 | { | |
36cdd013 DW |
1845 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
1846 | struct drm_device *dev = &dev_priv->drm; | |
44834a67 CW |
1847 | struct intel_opregion *opregion = &dev_priv->opregion; |
1848 | int ret; | |
1849 | ||
1850 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
1851 | if (ret) | |
0d38f009 | 1852 | goto out; |
44834a67 | 1853 | |
2455a8e4 JN |
1854 | if (opregion->header) |
1855 | seq_write(m, opregion->header, OPREGION_SIZE); | |
44834a67 CW |
1856 | |
1857 | mutex_unlock(&dev->struct_mutex); | |
1858 | ||
0d38f009 | 1859 | out: |
44834a67 CW |
1860 | return 0; |
1861 | } | |
1862 | ||
ada8f955 JN |
1863 | static int i915_vbt(struct seq_file *m, void *unused) |
1864 | { | |
36cdd013 | 1865 | struct intel_opregion *opregion = &node_to_i915(m->private)->opregion; |
ada8f955 JN |
1866 | |
1867 | if (opregion->vbt) | |
1868 | seq_write(m, opregion->vbt, opregion->vbt_size); | |
1869 | ||
1870 | return 0; | |
1871 | } | |
1872 | ||
37811fcc CW |
1873 | static int i915_gem_framebuffer_info(struct seq_file *m, void *data) |
1874 | { | |
36cdd013 DW |
1875 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
1876 | struct drm_device *dev = &dev_priv->drm; | |
b13b8402 | 1877 | struct intel_framebuffer *fbdev_fb = NULL; |
3a58ee10 | 1878 | struct drm_framebuffer *drm_fb; |
188c1ab7 CW |
1879 | int ret; |
1880 | ||
1881 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
1882 | if (ret) | |
1883 | return ret; | |
37811fcc | 1884 | |
0695726e | 1885 | #ifdef CONFIG_DRM_FBDEV_EMULATION |
36cdd013 DW |
1886 | if (dev_priv->fbdev) { |
1887 | fbdev_fb = to_intel_framebuffer(dev_priv->fbdev->helper.fb); | |
25bcce94 CW |
1888 | |
1889 | seq_printf(m, "fbcon size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ", | |
1890 | fbdev_fb->base.width, | |
1891 | fbdev_fb->base.height, | |
1892 | fbdev_fb->base.depth, | |
1893 | fbdev_fb->base.bits_per_pixel, | |
1894 | fbdev_fb->base.modifier[0], | |
1895 | drm_framebuffer_read_refcount(&fbdev_fb->base)); | |
1896 | describe_obj(m, fbdev_fb->obj); | |
1897 | seq_putc(m, '\n'); | |
1898 | } | |
4520f53a | 1899 | #endif |
37811fcc | 1900 | |
4b096ac1 | 1901 | mutex_lock(&dev->mode_config.fb_lock); |
3a58ee10 | 1902 | drm_for_each_fb(drm_fb, dev) { |
b13b8402 NS |
1903 | struct intel_framebuffer *fb = to_intel_framebuffer(drm_fb); |
1904 | if (fb == fbdev_fb) | |
37811fcc CW |
1905 | continue; |
1906 | ||
c1ca506d | 1907 | seq_printf(m, "user size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ", |
37811fcc CW |
1908 | fb->base.width, |
1909 | fb->base.height, | |
1910 | fb->base.depth, | |
623f9783 | 1911 | fb->base.bits_per_pixel, |
c1ca506d | 1912 | fb->base.modifier[0], |
747a598f | 1913 | drm_framebuffer_read_refcount(&fb->base)); |
05394f39 | 1914 | describe_obj(m, fb->obj); |
267f0c90 | 1915 | seq_putc(m, '\n'); |
37811fcc | 1916 | } |
4b096ac1 | 1917 | mutex_unlock(&dev->mode_config.fb_lock); |
188c1ab7 | 1918 | mutex_unlock(&dev->struct_mutex); |
37811fcc CW |
1919 | |
1920 | return 0; | |
1921 | } | |
1922 | ||
7e37f889 | 1923 | static void describe_ctx_ring(struct seq_file *m, struct intel_ring *ring) |
c9fe99bd OM |
1924 | { |
1925 | seq_printf(m, " (ringbuffer, space: %d, head: %u, tail: %u, last head: %d)", | |
7e37f889 CW |
1926 | ring->space, ring->head, ring->tail, |
1927 | ring->last_retired_head); | |
c9fe99bd OM |
1928 | } |
1929 | ||
e76d3630 BW |
1930 | static int i915_context_status(struct seq_file *m, void *unused) |
1931 | { | |
36cdd013 DW |
1932 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
1933 | struct drm_device *dev = &dev_priv->drm; | |
e2f80391 | 1934 | struct intel_engine_cs *engine; |
e2efd130 | 1935 | struct i915_gem_context *ctx; |
c3232b18 | 1936 | int ret; |
e76d3630 | 1937 | |
f3d28878 | 1938 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
e76d3630 BW |
1939 | if (ret) |
1940 | return ret; | |
1941 | ||
a33afea5 | 1942 | list_for_each_entry(ctx, &dev_priv->context_list, link) { |
5d1808ec | 1943 | seq_printf(m, "HW context %u ", ctx->hw_id); |
c84455b4 | 1944 | if (ctx->pid) { |
d28b99ab CW |
1945 | struct task_struct *task; |
1946 | ||
c84455b4 | 1947 | task = get_pid_task(ctx->pid, PIDTYPE_PID); |
d28b99ab CW |
1948 | if (task) { |
1949 | seq_printf(m, "(%s [%d]) ", | |
1950 | task->comm, task->pid); | |
1951 | put_task_struct(task); | |
1952 | } | |
c84455b4 CW |
1953 | } else if (IS_ERR(ctx->file_priv)) { |
1954 | seq_puts(m, "(deleted) "); | |
d28b99ab CW |
1955 | } else { |
1956 | seq_puts(m, "(kernel) "); | |
1957 | } | |
1958 | ||
bca44d80 CW |
1959 | seq_putc(m, ctx->remap_slice ? 'R' : 'r'); |
1960 | seq_putc(m, '\n'); | |
c9fe99bd | 1961 | |
bca44d80 CW |
1962 | for_each_engine(engine, dev_priv) { |
1963 | struct intel_context *ce = &ctx->engine[engine->id]; | |
1964 | ||
1965 | seq_printf(m, "%s: ", engine->name); | |
1966 | seq_putc(m, ce->initialised ? 'I' : 'i'); | |
1967 | if (ce->state) | |
bf3783e5 | 1968 | describe_obj(m, ce->state->obj); |
dca33ecc | 1969 | if (ce->ring) |
7e37f889 | 1970 | describe_ctx_ring(m, ce->ring); |
c9fe99bd | 1971 | seq_putc(m, '\n'); |
c9fe99bd | 1972 | } |
a33afea5 | 1973 | |
a33afea5 | 1974 | seq_putc(m, '\n'); |
a168c293 BW |
1975 | } |
1976 | ||
f3d28878 | 1977 | mutex_unlock(&dev->struct_mutex); |
e76d3630 BW |
1978 | |
1979 | return 0; | |
1980 | } | |
1981 | ||
064ca1d2 | 1982 | static void i915_dump_lrc_obj(struct seq_file *m, |
e2efd130 | 1983 | struct i915_gem_context *ctx, |
0bc40be8 | 1984 | struct intel_engine_cs *engine) |
064ca1d2 | 1985 | { |
bf3783e5 | 1986 | struct i915_vma *vma = ctx->engine[engine->id].state; |
064ca1d2 | 1987 | struct page *page; |
064ca1d2 | 1988 | int j; |
064ca1d2 | 1989 | |
7069b144 CW |
1990 | seq_printf(m, "CONTEXT: %s %u\n", engine->name, ctx->hw_id); |
1991 | ||
bf3783e5 CW |
1992 | if (!vma) { |
1993 | seq_puts(m, "\tFake context\n"); | |
064ca1d2 TD |
1994 | return; |
1995 | } | |
1996 | ||
bf3783e5 CW |
1997 | if (vma->flags & I915_VMA_GLOBAL_BIND) |
1998 | seq_printf(m, "\tBound in GGTT at 0x%08x\n", | |
bde13ebd | 1999 | i915_ggtt_offset(vma)); |
064ca1d2 | 2000 | |
bf3783e5 CW |
2001 | if (i915_gem_object_get_pages(vma->obj)) { |
2002 | seq_puts(m, "\tFailed to get pages for context object\n\n"); | |
064ca1d2 TD |
2003 | return; |
2004 | } | |
2005 | ||
bf3783e5 CW |
2006 | page = i915_gem_object_get_page(vma->obj, LRC_STATE_PN); |
2007 | if (page) { | |
2008 | u32 *reg_state = kmap_atomic(page); | |
064ca1d2 TD |
2009 | |
2010 | for (j = 0; j < 0x600 / sizeof(u32) / 4; j += 4) { | |
bf3783e5 CW |
2011 | seq_printf(m, |
2012 | "\t[0x%04x] 0x%08x 0x%08x 0x%08x 0x%08x\n", | |
2013 | j * 4, | |
064ca1d2 TD |
2014 | reg_state[j], reg_state[j + 1], |
2015 | reg_state[j + 2], reg_state[j + 3]); | |
2016 | } | |
2017 | kunmap_atomic(reg_state); | |
2018 | } | |
2019 | ||
2020 | seq_putc(m, '\n'); | |
2021 | } | |
2022 | ||
c0ab1ae9 BW |
2023 | static int i915_dump_lrc(struct seq_file *m, void *unused) |
2024 | { | |
36cdd013 DW |
2025 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
2026 | struct drm_device *dev = &dev_priv->drm; | |
e2f80391 | 2027 | struct intel_engine_cs *engine; |
e2efd130 | 2028 | struct i915_gem_context *ctx; |
b4ac5afc | 2029 | int ret; |
c0ab1ae9 BW |
2030 | |
2031 | if (!i915.enable_execlists) { | |
2032 | seq_printf(m, "Logical Ring Contexts are disabled\n"); | |
2033 | return 0; | |
2034 | } | |
2035 | ||
2036 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
2037 | if (ret) | |
2038 | return ret; | |
2039 | ||
e28e404c | 2040 | list_for_each_entry(ctx, &dev_priv->context_list, link) |
24f1d3cc CW |
2041 | for_each_engine(engine, dev_priv) |
2042 | i915_dump_lrc_obj(m, ctx, engine); | |
c0ab1ae9 BW |
2043 | |
2044 | mutex_unlock(&dev->struct_mutex); | |
2045 | ||
2046 | return 0; | |
2047 | } | |
2048 | ||
4ba70e44 OM |
2049 | static int i915_execlists(struct seq_file *m, void *data) |
2050 | { | |
36cdd013 DW |
2051 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
2052 | struct drm_device *dev = &dev_priv->drm; | |
e2f80391 | 2053 | struct intel_engine_cs *engine; |
4ba70e44 OM |
2054 | u32 status_pointer; |
2055 | u8 read_pointer; | |
2056 | u8 write_pointer; | |
2057 | u32 status; | |
2058 | u32 ctx_id; | |
2059 | struct list_head *cursor; | |
b4ac5afc | 2060 | int i, ret; |
4ba70e44 OM |
2061 | |
2062 | if (!i915.enable_execlists) { | |
2063 | seq_puts(m, "Logical Ring Contexts are disabled\n"); | |
2064 | return 0; | |
2065 | } | |
2066 | ||
2067 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
2068 | if (ret) | |
2069 | return ret; | |
2070 | ||
fc0412ec MT |
2071 | intel_runtime_pm_get(dev_priv); |
2072 | ||
b4ac5afc | 2073 | for_each_engine(engine, dev_priv) { |
6d3d8274 | 2074 | struct drm_i915_gem_request *head_req = NULL; |
4ba70e44 | 2075 | int count = 0; |
4ba70e44 | 2076 | |
e2f80391 | 2077 | seq_printf(m, "%s\n", engine->name); |
4ba70e44 | 2078 | |
e2f80391 TU |
2079 | status = I915_READ(RING_EXECLIST_STATUS_LO(engine)); |
2080 | ctx_id = I915_READ(RING_EXECLIST_STATUS_HI(engine)); | |
4ba70e44 OM |
2081 | seq_printf(m, "\tExeclist status: 0x%08X, context: %u\n", |
2082 | status, ctx_id); | |
2083 | ||
e2f80391 | 2084 | status_pointer = I915_READ(RING_CONTEXT_STATUS_PTR(engine)); |
4ba70e44 OM |
2085 | seq_printf(m, "\tStatus pointer: 0x%08X\n", status_pointer); |
2086 | ||
70c2a24d | 2087 | read_pointer = GEN8_CSB_READ_PTR(status_pointer); |
5590a5f0 | 2088 | write_pointer = GEN8_CSB_WRITE_PTR(status_pointer); |
4ba70e44 | 2089 | if (read_pointer > write_pointer) |
5590a5f0 | 2090 | write_pointer += GEN8_CSB_ENTRIES; |
4ba70e44 OM |
2091 | seq_printf(m, "\tRead pointer: 0x%08X, write pointer 0x%08X\n", |
2092 | read_pointer, write_pointer); | |
2093 | ||
5590a5f0 | 2094 | for (i = 0; i < GEN8_CSB_ENTRIES; i++) { |
e2f80391 TU |
2095 | status = I915_READ(RING_CONTEXT_STATUS_BUF_LO(engine, i)); |
2096 | ctx_id = I915_READ(RING_CONTEXT_STATUS_BUF_HI(engine, i)); | |
4ba70e44 OM |
2097 | |
2098 | seq_printf(m, "\tStatus buffer %d: 0x%08X, context: %u\n", | |
2099 | i, status, ctx_id); | |
2100 | } | |
2101 | ||
27af5eea | 2102 | spin_lock_bh(&engine->execlist_lock); |
e2f80391 | 2103 | list_for_each(cursor, &engine->execlist_queue) |
4ba70e44 | 2104 | count++; |
e2f80391 TU |
2105 | head_req = list_first_entry_or_null(&engine->execlist_queue, |
2106 | struct drm_i915_gem_request, | |
2107 | execlist_link); | |
27af5eea | 2108 | spin_unlock_bh(&engine->execlist_lock); |
4ba70e44 OM |
2109 | |
2110 | seq_printf(m, "\t%d requests in queue\n", count); | |
2111 | if (head_req) { | |
7069b144 CW |
2112 | seq_printf(m, "\tHead request context: %u\n", |
2113 | head_req->ctx->hw_id); | |
4ba70e44 | 2114 | seq_printf(m, "\tHead request tail: %u\n", |
6d3d8274 | 2115 | head_req->tail); |
4ba70e44 OM |
2116 | } |
2117 | ||
2118 | seq_putc(m, '\n'); | |
2119 | } | |
2120 | ||
fc0412ec | 2121 | intel_runtime_pm_put(dev_priv); |
4ba70e44 OM |
2122 | mutex_unlock(&dev->struct_mutex); |
2123 | ||
2124 | return 0; | |
2125 | } | |
2126 | ||
ea16a3cd DV |
2127 | static const char *swizzle_string(unsigned swizzle) |
2128 | { | |
aee56cff | 2129 | switch (swizzle) { |
ea16a3cd DV |
2130 | case I915_BIT_6_SWIZZLE_NONE: |
2131 | return "none"; | |
2132 | case I915_BIT_6_SWIZZLE_9: | |
2133 | return "bit9"; | |
2134 | case I915_BIT_6_SWIZZLE_9_10: | |
2135 | return "bit9/bit10"; | |
2136 | case I915_BIT_6_SWIZZLE_9_11: | |
2137 | return "bit9/bit11"; | |
2138 | case I915_BIT_6_SWIZZLE_9_10_11: | |
2139 | return "bit9/bit10/bit11"; | |
2140 | case I915_BIT_6_SWIZZLE_9_17: | |
2141 | return "bit9/bit17"; | |
2142 | case I915_BIT_6_SWIZZLE_9_10_17: | |
2143 | return "bit9/bit10/bit17"; | |
2144 | case I915_BIT_6_SWIZZLE_UNKNOWN: | |
8a168ca7 | 2145 | return "unknown"; |
ea16a3cd DV |
2146 | } |
2147 | ||
2148 | return "bug"; | |
2149 | } | |
2150 | ||
2151 | static int i915_swizzle_info(struct seq_file *m, void *data) | |
2152 | { | |
36cdd013 DW |
2153 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
2154 | struct drm_device *dev = &dev_priv->drm; | |
22bcfc6a DV |
2155 | int ret; |
2156 | ||
2157 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
2158 | if (ret) | |
2159 | return ret; | |
c8c8fb33 | 2160 | intel_runtime_pm_get(dev_priv); |
ea16a3cd | 2161 | |
ea16a3cd DV |
2162 | seq_printf(m, "bit6 swizzle for X-tiling = %s\n", |
2163 | swizzle_string(dev_priv->mm.bit_6_swizzle_x)); | |
2164 | seq_printf(m, "bit6 swizzle for Y-tiling = %s\n", | |
2165 | swizzle_string(dev_priv->mm.bit_6_swizzle_y)); | |
2166 | ||
36cdd013 | 2167 | if (IS_GEN3(dev_priv) || IS_GEN4(dev_priv)) { |
ea16a3cd DV |
2168 | seq_printf(m, "DDC = 0x%08x\n", |
2169 | I915_READ(DCC)); | |
656bfa3a DV |
2170 | seq_printf(m, "DDC2 = 0x%08x\n", |
2171 | I915_READ(DCC2)); | |
ea16a3cd DV |
2172 | seq_printf(m, "C0DRB3 = 0x%04x\n", |
2173 | I915_READ16(C0DRB3)); | |
2174 | seq_printf(m, "C1DRB3 = 0x%04x\n", | |
2175 | I915_READ16(C1DRB3)); | |
36cdd013 | 2176 | } else if (INTEL_GEN(dev_priv) >= 6) { |
3fa7d235 DV |
2177 | seq_printf(m, "MAD_DIMM_C0 = 0x%08x\n", |
2178 | I915_READ(MAD_DIMM_C0)); | |
2179 | seq_printf(m, "MAD_DIMM_C1 = 0x%08x\n", | |
2180 | I915_READ(MAD_DIMM_C1)); | |
2181 | seq_printf(m, "MAD_DIMM_C2 = 0x%08x\n", | |
2182 | I915_READ(MAD_DIMM_C2)); | |
2183 | seq_printf(m, "TILECTL = 0x%08x\n", | |
2184 | I915_READ(TILECTL)); | |
36cdd013 | 2185 | if (INTEL_GEN(dev_priv) >= 8) |
9d3203e1 BW |
2186 | seq_printf(m, "GAMTARBMODE = 0x%08x\n", |
2187 | I915_READ(GAMTARBMODE)); | |
2188 | else | |
2189 | seq_printf(m, "ARB_MODE = 0x%08x\n", | |
2190 | I915_READ(ARB_MODE)); | |
3fa7d235 DV |
2191 | seq_printf(m, "DISP_ARB_CTL = 0x%08x\n", |
2192 | I915_READ(DISP_ARB_CTL)); | |
ea16a3cd | 2193 | } |
656bfa3a DV |
2194 | |
2195 | if (dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES) | |
2196 | seq_puts(m, "L-shaped memory detected\n"); | |
2197 | ||
c8c8fb33 | 2198 | intel_runtime_pm_put(dev_priv); |
ea16a3cd DV |
2199 | mutex_unlock(&dev->struct_mutex); |
2200 | ||
2201 | return 0; | |
2202 | } | |
2203 | ||
1c60fef5 BW |
2204 | static int per_file_ctx(int id, void *ptr, void *data) |
2205 | { | |
e2efd130 | 2206 | struct i915_gem_context *ctx = ptr; |
1c60fef5 | 2207 | struct seq_file *m = data; |
ae6c4806 DV |
2208 | struct i915_hw_ppgtt *ppgtt = ctx->ppgtt; |
2209 | ||
2210 | if (!ppgtt) { | |
2211 | seq_printf(m, " no ppgtt for context %d\n", | |
2212 | ctx->user_handle); | |
2213 | return 0; | |
2214 | } | |
1c60fef5 | 2215 | |
f83d6518 OM |
2216 | if (i915_gem_context_is_default(ctx)) |
2217 | seq_puts(m, " default context:\n"); | |
2218 | else | |
821d66dd | 2219 | seq_printf(m, " context %d:\n", ctx->user_handle); |
1c60fef5 BW |
2220 | ppgtt->debug_dump(ppgtt, m); |
2221 | ||
2222 | return 0; | |
2223 | } | |
2224 | ||
36cdd013 DW |
2225 | static void gen8_ppgtt_info(struct seq_file *m, |
2226 | struct drm_i915_private *dev_priv) | |
3cf17fc5 | 2227 | { |
e2f80391 | 2228 | struct intel_engine_cs *engine; |
77df6772 | 2229 | struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt; |
b4ac5afc | 2230 | int i; |
3cf17fc5 | 2231 | |
77df6772 BW |
2232 | if (!ppgtt) |
2233 | return; | |
2234 | ||
b4ac5afc | 2235 | for_each_engine(engine, dev_priv) { |
e2f80391 | 2236 | seq_printf(m, "%s\n", engine->name); |
77df6772 | 2237 | for (i = 0; i < 4; i++) { |
e2f80391 | 2238 | u64 pdp = I915_READ(GEN8_RING_PDP_UDW(engine, i)); |
77df6772 | 2239 | pdp <<= 32; |
e2f80391 | 2240 | pdp |= I915_READ(GEN8_RING_PDP_LDW(engine, i)); |
a2a5b15c | 2241 | seq_printf(m, "\tPDP%d 0x%016llx\n", i, pdp); |
77df6772 BW |
2242 | } |
2243 | } | |
2244 | } | |
2245 | ||
36cdd013 DW |
2246 | static void gen6_ppgtt_info(struct seq_file *m, |
2247 | struct drm_i915_private *dev_priv) | |
77df6772 | 2248 | { |
e2f80391 | 2249 | struct intel_engine_cs *engine; |
3cf17fc5 | 2250 | |
7e22dbbb | 2251 | if (IS_GEN6(dev_priv)) |
3cf17fc5 DV |
2252 | seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(GFX_MODE)); |
2253 | ||
b4ac5afc | 2254 | for_each_engine(engine, dev_priv) { |
e2f80391 | 2255 | seq_printf(m, "%s\n", engine->name); |
7e22dbbb | 2256 | if (IS_GEN7(dev_priv)) |
e2f80391 TU |
2257 | seq_printf(m, "GFX_MODE: 0x%08x\n", |
2258 | I915_READ(RING_MODE_GEN7(engine))); | |
2259 | seq_printf(m, "PP_DIR_BASE: 0x%08x\n", | |
2260 | I915_READ(RING_PP_DIR_BASE(engine))); | |
2261 | seq_printf(m, "PP_DIR_BASE_READ: 0x%08x\n", | |
2262 | I915_READ(RING_PP_DIR_BASE_READ(engine))); | |
2263 | seq_printf(m, "PP_DIR_DCLV: 0x%08x\n", | |
2264 | I915_READ(RING_PP_DIR_DCLV(engine))); | |
3cf17fc5 DV |
2265 | } |
2266 | if (dev_priv->mm.aliasing_ppgtt) { | |
2267 | struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt; | |
2268 | ||
267f0c90 | 2269 | seq_puts(m, "aliasing PPGTT:\n"); |
44159ddb | 2270 | seq_printf(m, "pd gtt offset: 0x%08x\n", ppgtt->pd.base.ggtt_offset); |
1c60fef5 | 2271 | |
87d60b63 | 2272 | ppgtt->debug_dump(ppgtt, m); |
ae6c4806 | 2273 | } |
1c60fef5 | 2274 | |
3cf17fc5 | 2275 | seq_printf(m, "ECOCHK: 0x%08x\n", I915_READ(GAM_ECOCHK)); |
77df6772 BW |
2276 | } |
2277 | ||
2278 | static int i915_ppgtt_info(struct seq_file *m, void *data) | |
2279 | { | |
36cdd013 DW |
2280 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
2281 | struct drm_device *dev = &dev_priv->drm; | |
ea91e401 | 2282 | struct drm_file *file; |
637ee29e | 2283 | int ret; |
77df6772 | 2284 | |
637ee29e CW |
2285 | mutex_lock(&dev->filelist_mutex); |
2286 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
77df6772 | 2287 | if (ret) |
637ee29e CW |
2288 | goto out_unlock; |
2289 | ||
c8c8fb33 | 2290 | intel_runtime_pm_get(dev_priv); |
77df6772 | 2291 | |
36cdd013 DW |
2292 | if (INTEL_GEN(dev_priv) >= 8) |
2293 | gen8_ppgtt_info(m, dev_priv); | |
2294 | else if (INTEL_GEN(dev_priv) >= 6) | |
2295 | gen6_ppgtt_info(m, dev_priv); | |
77df6772 | 2296 | |
ea91e401 MT |
2297 | list_for_each_entry_reverse(file, &dev->filelist, lhead) { |
2298 | struct drm_i915_file_private *file_priv = file->driver_priv; | |
7cb5dff8 | 2299 | struct task_struct *task; |
ea91e401 | 2300 | |
7cb5dff8 | 2301 | task = get_pid_task(file->pid, PIDTYPE_PID); |
06812760 DC |
2302 | if (!task) { |
2303 | ret = -ESRCH; | |
637ee29e | 2304 | goto out_rpm; |
06812760 | 2305 | } |
7cb5dff8 GT |
2306 | seq_printf(m, "\nproc: %s\n", task->comm); |
2307 | put_task_struct(task); | |
ea91e401 MT |
2308 | idr_for_each(&file_priv->context_idr, per_file_ctx, |
2309 | (void *)(unsigned long)m); | |
2310 | } | |
2311 | ||
637ee29e | 2312 | out_rpm: |
c8c8fb33 | 2313 | intel_runtime_pm_put(dev_priv); |
3cf17fc5 | 2314 | mutex_unlock(&dev->struct_mutex); |
637ee29e CW |
2315 | out_unlock: |
2316 | mutex_unlock(&dev->filelist_mutex); | |
06812760 | 2317 | return ret; |
3cf17fc5 DV |
2318 | } |
2319 | ||
f5a4c67d CW |
2320 | static int count_irq_waiters(struct drm_i915_private *i915) |
2321 | { | |
e2f80391 | 2322 | struct intel_engine_cs *engine; |
f5a4c67d | 2323 | int count = 0; |
f5a4c67d | 2324 | |
b4ac5afc | 2325 | for_each_engine(engine, i915) |
688e6c72 | 2326 | count += intel_engine_has_waiter(engine); |
f5a4c67d CW |
2327 | |
2328 | return count; | |
2329 | } | |
2330 | ||
7466c291 CW |
2331 | static const char *rps_power_to_str(unsigned int power) |
2332 | { | |
2333 | static const char * const strings[] = { | |
2334 | [LOW_POWER] = "low power", | |
2335 | [BETWEEN] = "mixed", | |
2336 | [HIGH_POWER] = "high power", | |
2337 | }; | |
2338 | ||
2339 | if (power >= ARRAY_SIZE(strings) || !strings[power]) | |
2340 | return "unknown"; | |
2341 | ||
2342 | return strings[power]; | |
2343 | } | |
2344 | ||
1854d5ca CW |
2345 | static int i915_rps_boost_info(struct seq_file *m, void *data) |
2346 | { | |
36cdd013 DW |
2347 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
2348 | struct drm_device *dev = &dev_priv->drm; | |
1854d5ca | 2349 | struct drm_file *file; |
1854d5ca | 2350 | |
f5a4c67d | 2351 | seq_printf(m, "RPS enabled? %d\n", dev_priv->rps.enabled); |
67d97da3 CW |
2352 | seq_printf(m, "GPU busy? %s [%x]\n", |
2353 | yesno(dev_priv->gt.awake), dev_priv->gt.active_engines); | |
f5a4c67d | 2354 | seq_printf(m, "CPU waiting? %d\n", count_irq_waiters(dev_priv)); |
7466c291 CW |
2355 | seq_printf(m, "Frequency requested %d\n", |
2356 | intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq)); | |
2357 | seq_printf(m, " min hard:%d, soft:%d; max soft:%d, hard:%d\n", | |
f5a4c67d CW |
2358 | intel_gpu_freq(dev_priv, dev_priv->rps.min_freq), |
2359 | intel_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit), | |
2360 | intel_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit), | |
2361 | intel_gpu_freq(dev_priv, dev_priv->rps.max_freq)); | |
7466c291 CW |
2362 | seq_printf(m, " idle:%d, efficient:%d, boost:%d\n", |
2363 | intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq), | |
2364 | intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq), | |
2365 | intel_gpu_freq(dev_priv, dev_priv->rps.boost_freq)); | |
1d2ac403 DV |
2366 | |
2367 | mutex_lock(&dev->filelist_mutex); | |
8d3afd7d | 2368 | spin_lock(&dev_priv->rps.client_lock); |
1854d5ca CW |
2369 | list_for_each_entry_reverse(file, &dev->filelist, lhead) { |
2370 | struct drm_i915_file_private *file_priv = file->driver_priv; | |
2371 | struct task_struct *task; | |
2372 | ||
2373 | rcu_read_lock(); | |
2374 | task = pid_task(file->pid, PIDTYPE_PID); | |
2375 | seq_printf(m, "%s [%d]: %d boosts%s\n", | |
2376 | task ? task->comm : "<unknown>", | |
2377 | task ? task->pid : -1, | |
2e1b8730 CW |
2378 | file_priv->rps.boosts, |
2379 | list_empty(&file_priv->rps.link) ? "" : ", active"); | |
1854d5ca CW |
2380 | rcu_read_unlock(); |
2381 | } | |
197be2ae | 2382 | seq_printf(m, "Kernel (anonymous) boosts: %d\n", dev_priv->rps.boosts); |
8d3afd7d | 2383 | spin_unlock(&dev_priv->rps.client_lock); |
1d2ac403 | 2384 | mutex_unlock(&dev->filelist_mutex); |
1854d5ca | 2385 | |
7466c291 CW |
2386 | if (INTEL_GEN(dev_priv) >= 6 && |
2387 | dev_priv->rps.enabled && | |
2388 | dev_priv->gt.active_engines) { | |
2389 | u32 rpup, rpupei; | |
2390 | u32 rpdown, rpdownei; | |
2391 | ||
2392 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); | |
2393 | rpup = I915_READ_FW(GEN6_RP_CUR_UP) & GEN6_RP_EI_MASK; | |
2394 | rpupei = I915_READ_FW(GEN6_RP_CUR_UP_EI) & GEN6_RP_EI_MASK; | |
2395 | rpdown = I915_READ_FW(GEN6_RP_CUR_DOWN) & GEN6_RP_EI_MASK; | |
2396 | rpdownei = I915_READ_FW(GEN6_RP_CUR_DOWN_EI) & GEN6_RP_EI_MASK; | |
2397 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); | |
2398 | ||
2399 | seq_printf(m, "\nRPS Autotuning (current \"%s\" window):\n", | |
2400 | rps_power_to_str(dev_priv->rps.power)); | |
2401 | seq_printf(m, " Avg. up: %d%% [above threshold? %d%%]\n", | |
2402 | 100 * rpup / rpupei, | |
2403 | dev_priv->rps.up_threshold); | |
2404 | seq_printf(m, " Avg. down: %d%% [below threshold? %d%%]\n", | |
2405 | 100 * rpdown / rpdownei, | |
2406 | dev_priv->rps.down_threshold); | |
2407 | } else { | |
2408 | seq_puts(m, "\nRPS Autotuning inactive\n"); | |
2409 | } | |
2410 | ||
8d3afd7d | 2411 | return 0; |
1854d5ca CW |
2412 | } |
2413 | ||
63573eb7 BW |
2414 | static int i915_llc(struct seq_file *m, void *data) |
2415 | { | |
36cdd013 | 2416 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
3accaf7e | 2417 | const bool edram = INTEL_GEN(dev_priv) > 8; |
63573eb7 | 2418 | |
36cdd013 | 2419 | seq_printf(m, "LLC: %s\n", yesno(HAS_LLC(dev_priv))); |
3accaf7e MK |
2420 | seq_printf(m, "%s: %lluMB\n", edram ? "eDRAM" : "eLLC", |
2421 | intel_uncore_edram_size(dev_priv)/1024/1024); | |
63573eb7 BW |
2422 | |
2423 | return 0; | |
2424 | } | |
2425 | ||
fdf5d357 AD |
2426 | static int i915_guc_load_status_info(struct seq_file *m, void *data) |
2427 | { | |
36cdd013 | 2428 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
fdf5d357 AD |
2429 | struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw; |
2430 | u32 tmp, i; | |
2431 | ||
2d1fe073 | 2432 | if (!HAS_GUC_UCODE(dev_priv)) |
fdf5d357 AD |
2433 | return 0; |
2434 | ||
2435 | seq_printf(m, "GuC firmware status:\n"); | |
2436 | seq_printf(m, "\tpath: %s\n", | |
2437 | guc_fw->guc_fw_path); | |
2438 | seq_printf(m, "\tfetch: %s\n", | |
2439 | intel_guc_fw_status_repr(guc_fw->guc_fw_fetch_status)); | |
2440 | seq_printf(m, "\tload: %s\n", | |
2441 | intel_guc_fw_status_repr(guc_fw->guc_fw_load_status)); | |
2442 | seq_printf(m, "\tversion wanted: %d.%d\n", | |
2443 | guc_fw->guc_fw_major_wanted, guc_fw->guc_fw_minor_wanted); | |
2444 | seq_printf(m, "\tversion found: %d.%d\n", | |
2445 | guc_fw->guc_fw_major_found, guc_fw->guc_fw_minor_found); | |
feda33ef AD |
2446 | seq_printf(m, "\theader: offset is %d; size = %d\n", |
2447 | guc_fw->header_offset, guc_fw->header_size); | |
2448 | seq_printf(m, "\tuCode: offset is %d; size = %d\n", | |
2449 | guc_fw->ucode_offset, guc_fw->ucode_size); | |
2450 | seq_printf(m, "\tRSA: offset is %d; size = %d\n", | |
2451 | guc_fw->rsa_offset, guc_fw->rsa_size); | |
fdf5d357 AD |
2452 | |
2453 | tmp = I915_READ(GUC_STATUS); | |
2454 | ||
2455 | seq_printf(m, "\nGuC status 0x%08x:\n", tmp); | |
2456 | seq_printf(m, "\tBootrom status = 0x%x\n", | |
2457 | (tmp & GS_BOOTROM_MASK) >> GS_BOOTROM_SHIFT); | |
2458 | seq_printf(m, "\tuKernel status = 0x%x\n", | |
2459 | (tmp & GS_UKERNEL_MASK) >> GS_UKERNEL_SHIFT); | |
2460 | seq_printf(m, "\tMIA Core status = 0x%x\n", | |
2461 | (tmp & GS_MIA_MASK) >> GS_MIA_SHIFT); | |
2462 | seq_puts(m, "\nScratch registers:\n"); | |
2463 | for (i = 0; i < 16; i++) | |
2464 | seq_printf(m, "\t%2d: \t0x%x\n", i, I915_READ(SOFT_SCRATCH(i))); | |
2465 | ||
2466 | return 0; | |
2467 | } | |
2468 | ||
8b417c26 DG |
2469 | static void i915_guc_client_info(struct seq_file *m, |
2470 | struct drm_i915_private *dev_priv, | |
2471 | struct i915_guc_client *client) | |
2472 | { | |
e2f80391 | 2473 | struct intel_engine_cs *engine; |
c18468c4 | 2474 | enum intel_engine_id id; |
8b417c26 | 2475 | uint64_t tot = 0; |
8b417c26 DG |
2476 | |
2477 | seq_printf(m, "\tPriority %d, GuC ctx index: %u, PD offset 0x%x\n", | |
2478 | client->priority, client->ctx_index, client->proc_desc_offset); | |
2479 | seq_printf(m, "\tDoorbell id %d, offset: 0x%x, cookie 0x%x\n", | |
2480 | client->doorbell_id, client->doorbell_offset, client->cookie); | |
2481 | seq_printf(m, "\tWQ size %d, offset: 0x%x, tail %d\n", | |
2482 | client->wq_size, client->wq_offset, client->wq_tail); | |
2483 | ||
551aaecd | 2484 | seq_printf(m, "\tWork queue full: %u\n", client->no_wq_space); |
8b417c26 DG |
2485 | seq_printf(m, "\tFailed doorbell: %u\n", client->b_fail); |
2486 | seq_printf(m, "\tLast submission result: %d\n", client->retcode); | |
2487 | ||
c18468c4 DG |
2488 | for_each_engine_id(engine, dev_priv, id) { |
2489 | u64 submissions = client->submissions[id]; | |
2490 | tot += submissions; | |
8b417c26 | 2491 | seq_printf(m, "\tSubmissions: %llu %s\n", |
c18468c4 | 2492 | submissions, engine->name); |
8b417c26 DG |
2493 | } |
2494 | seq_printf(m, "\tTotal: %llu\n", tot); | |
2495 | } | |
2496 | ||
2497 | static int i915_guc_info(struct seq_file *m, void *data) | |
2498 | { | |
36cdd013 DW |
2499 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
2500 | struct drm_device *dev = &dev_priv->drm; | |
8b417c26 | 2501 | struct intel_guc guc; |
0a0b457f | 2502 | struct i915_guc_client client = {}; |
e2f80391 | 2503 | struct intel_engine_cs *engine; |
c18468c4 | 2504 | enum intel_engine_id id; |
8b417c26 DG |
2505 | u64 total = 0; |
2506 | ||
2d1fe073 | 2507 | if (!HAS_GUC_SCHED(dev_priv)) |
8b417c26 DG |
2508 | return 0; |
2509 | ||
5a843307 AD |
2510 | if (mutex_lock_interruptible(&dev->struct_mutex)) |
2511 | return 0; | |
2512 | ||
8b417c26 | 2513 | /* Take a local copy of the GuC data, so we can dump it at leisure */ |
8b417c26 | 2514 | guc = dev_priv->guc; |
5a843307 | 2515 | if (guc.execbuf_client) |
8b417c26 | 2516 | client = *guc.execbuf_client; |
5a843307 AD |
2517 | |
2518 | mutex_unlock(&dev->struct_mutex); | |
8b417c26 | 2519 | |
9636f6db DG |
2520 | seq_printf(m, "Doorbell map:\n"); |
2521 | seq_printf(m, "\t%*pb\n", GUC_MAX_DOORBELLS, guc.doorbell_bitmap); | |
2522 | seq_printf(m, "Doorbell next cacheline: 0x%x\n\n", guc.db_cacheline); | |
2523 | ||
8b417c26 DG |
2524 | seq_printf(m, "GuC total action count: %llu\n", guc.action_count); |
2525 | seq_printf(m, "GuC action failure count: %u\n", guc.action_fail); | |
2526 | seq_printf(m, "GuC last action command: 0x%x\n", guc.action_cmd); | |
2527 | seq_printf(m, "GuC last action status: 0x%x\n", guc.action_status); | |
2528 | seq_printf(m, "GuC last action error code: %d\n", guc.action_err); | |
2529 | ||
2530 | seq_printf(m, "\nGuC submissions:\n"); | |
c18468c4 DG |
2531 | for_each_engine_id(engine, dev_priv, id) { |
2532 | u64 submissions = guc.submissions[id]; | |
2533 | total += submissions; | |
397097b0 | 2534 | seq_printf(m, "\t%-24s: %10llu, last seqno 0x%08x\n", |
c18468c4 | 2535 | engine->name, submissions, guc.last_seqno[id]); |
8b417c26 DG |
2536 | } |
2537 | seq_printf(m, "\t%s: %llu\n", "Total", total); | |
2538 | ||
2539 | seq_printf(m, "\nGuC execbuf client @ %p:\n", guc.execbuf_client); | |
2540 | i915_guc_client_info(m, dev_priv, &client); | |
2541 | ||
2542 | /* Add more as required ... */ | |
2543 | ||
2544 | return 0; | |
2545 | } | |
2546 | ||
4c7e77fc AD |
2547 | static int i915_guc_log_dump(struct seq_file *m, void *data) |
2548 | { | |
36cdd013 | 2549 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
8b797af1 | 2550 | struct drm_i915_gem_object *obj; |
4c7e77fc AD |
2551 | int i = 0, pg; |
2552 | ||
8b797af1 | 2553 | if (!dev_priv->guc.log_vma) |
4c7e77fc AD |
2554 | return 0; |
2555 | ||
8b797af1 CW |
2556 | obj = dev_priv->guc.log_vma->obj; |
2557 | for (pg = 0; pg < obj->base.size / PAGE_SIZE; pg++) { | |
2558 | u32 *log = kmap_atomic(i915_gem_object_get_page(obj, pg)); | |
4c7e77fc AD |
2559 | |
2560 | for (i = 0; i < PAGE_SIZE / sizeof(u32); i += 4) | |
2561 | seq_printf(m, "0x%08x 0x%08x 0x%08x 0x%08x\n", | |
2562 | *(log + i), *(log + i + 1), | |
2563 | *(log + i + 2), *(log + i + 3)); | |
2564 | ||
2565 | kunmap_atomic(log); | |
2566 | } | |
2567 | ||
2568 | seq_putc(m, '\n'); | |
2569 | ||
2570 | return 0; | |
2571 | } | |
2572 | ||
e91fd8c6 RV |
2573 | static int i915_edp_psr_status(struct seq_file *m, void *data) |
2574 | { | |
36cdd013 | 2575 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
a031d709 | 2576 | u32 psrperf = 0; |
a6cbdb8e RV |
2577 | u32 stat[3]; |
2578 | enum pipe pipe; | |
a031d709 | 2579 | bool enabled = false; |
e91fd8c6 | 2580 | |
36cdd013 | 2581 | if (!HAS_PSR(dev_priv)) { |
3553a8ea DL |
2582 | seq_puts(m, "PSR not supported\n"); |
2583 | return 0; | |
2584 | } | |
2585 | ||
c8c8fb33 PZ |
2586 | intel_runtime_pm_get(dev_priv); |
2587 | ||
fa128fa6 | 2588 | mutex_lock(&dev_priv->psr.lock); |
a031d709 RV |
2589 | seq_printf(m, "Sink_Support: %s\n", yesno(dev_priv->psr.sink_support)); |
2590 | seq_printf(m, "Source_OK: %s\n", yesno(dev_priv->psr.source_ok)); | |
2807cf69 | 2591 | seq_printf(m, "Enabled: %s\n", yesno((bool)dev_priv->psr.enabled)); |
5755c78f | 2592 | seq_printf(m, "Active: %s\n", yesno(dev_priv->psr.active)); |
fa128fa6 DV |
2593 | seq_printf(m, "Busy frontbuffer bits: 0x%03x\n", |
2594 | dev_priv->psr.busy_frontbuffer_bits); | |
2595 | seq_printf(m, "Re-enable work scheduled: %s\n", | |
2596 | yesno(work_busy(&dev_priv->psr.work.work))); | |
e91fd8c6 | 2597 | |
36cdd013 | 2598 | if (HAS_DDI(dev_priv)) |
443a389f | 2599 | enabled = I915_READ(EDP_PSR_CTL) & EDP_PSR_ENABLE; |
3553a8ea DL |
2600 | else { |
2601 | for_each_pipe(dev_priv, pipe) { | |
2602 | stat[pipe] = I915_READ(VLV_PSRSTAT(pipe)) & | |
2603 | VLV_EDP_PSR_CURR_STATE_MASK; | |
2604 | if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) || | |
2605 | (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE)) | |
2606 | enabled = true; | |
a6cbdb8e RV |
2607 | } |
2608 | } | |
60e5ffe3 RV |
2609 | |
2610 | seq_printf(m, "Main link in standby mode: %s\n", | |
2611 | yesno(dev_priv->psr.link_standby)); | |
2612 | ||
a6cbdb8e RV |
2613 | seq_printf(m, "HW Enabled & Active bit: %s", yesno(enabled)); |
2614 | ||
36cdd013 | 2615 | if (!HAS_DDI(dev_priv)) |
a6cbdb8e RV |
2616 | for_each_pipe(dev_priv, pipe) { |
2617 | if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) || | |
2618 | (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE)) | |
2619 | seq_printf(m, " pipe %c", pipe_name(pipe)); | |
2620 | } | |
2621 | seq_puts(m, "\n"); | |
e91fd8c6 | 2622 | |
05eec3c2 RV |
2623 | /* |
2624 | * VLV/CHV PSR has no kind of performance counter | |
2625 | * SKL+ Perf counter is reset to 0 everytime DC state is entered | |
2626 | */ | |
36cdd013 | 2627 | if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) { |
443a389f | 2628 | psrperf = I915_READ(EDP_PSR_PERF_CNT) & |
a031d709 | 2629 | EDP_PSR_PERF_CNT_MASK; |
a6cbdb8e RV |
2630 | |
2631 | seq_printf(m, "Performance_Counter: %u\n", psrperf); | |
2632 | } | |
fa128fa6 | 2633 | mutex_unlock(&dev_priv->psr.lock); |
e91fd8c6 | 2634 | |
c8c8fb33 | 2635 | intel_runtime_pm_put(dev_priv); |
e91fd8c6 RV |
2636 | return 0; |
2637 | } | |
2638 | ||
d2e216d0 RV |
2639 | static int i915_sink_crc(struct seq_file *m, void *data) |
2640 | { | |
36cdd013 DW |
2641 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
2642 | struct drm_device *dev = &dev_priv->drm; | |
d2e216d0 RV |
2643 | struct intel_connector *connector; |
2644 | struct intel_dp *intel_dp = NULL; | |
2645 | int ret; | |
2646 | u8 crc[6]; | |
2647 | ||
2648 | drm_modeset_lock_all(dev); | |
aca5e361 | 2649 | for_each_intel_connector(dev, connector) { |
26c17cf6 | 2650 | struct drm_crtc *crtc; |
d2e216d0 | 2651 | |
26c17cf6 | 2652 | if (!connector->base.state->best_encoder) |
d2e216d0 RV |
2653 | continue; |
2654 | ||
26c17cf6 ML |
2655 | crtc = connector->base.state->crtc; |
2656 | if (!crtc->state->active) | |
b6ae3c7c PZ |
2657 | continue; |
2658 | ||
26c17cf6 | 2659 | if (connector->base.connector_type != DRM_MODE_CONNECTOR_eDP) |
d2e216d0 RV |
2660 | continue; |
2661 | ||
26c17cf6 | 2662 | intel_dp = enc_to_intel_dp(connector->base.state->best_encoder); |
d2e216d0 RV |
2663 | |
2664 | ret = intel_dp_sink_crc(intel_dp, crc); | |
2665 | if (ret) | |
2666 | goto out; | |
2667 | ||
2668 | seq_printf(m, "%02x%02x%02x%02x%02x%02x\n", | |
2669 | crc[0], crc[1], crc[2], | |
2670 | crc[3], crc[4], crc[5]); | |
2671 | goto out; | |
2672 | } | |
2673 | ret = -ENODEV; | |
2674 | out: | |
2675 | drm_modeset_unlock_all(dev); | |
2676 | return ret; | |
2677 | } | |
2678 | ||
ec013e7f JB |
2679 | static int i915_energy_uJ(struct seq_file *m, void *data) |
2680 | { | |
36cdd013 | 2681 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
ec013e7f JB |
2682 | u64 power; |
2683 | u32 units; | |
2684 | ||
36cdd013 | 2685 | if (INTEL_GEN(dev_priv) < 6) |
ec013e7f JB |
2686 | return -ENODEV; |
2687 | ||
36623ef8 PZ |
2688 | intel_runtime_pm_get(dev_priv); |
2689 | ||
ec013e7f JB |
2690 | rdmsrl(MSR_RAPL_POWER_UNIT, power); |
2691 | power = (power & 0x1f00) >> 8; | |
2692 | units = 1000000 / (1 << power); /* convert to uJ */ | |
2693 | power = I915_READ(MCH_SECP_NRG_STTS); | |
2694 | power *= units; | |
2695 | ||
36623ef8 PZ |
2696 | intel_runtime_pm_put(dev_priv); |
2697 | ||
ec013e7f | 2698 | seq_printf(m, "%llu", (long long unsigned)power); |
371db66a PZ |
2699 | |
2700 | return 0; | |
2701 | } | |
2702 | ||
6455c870 | 2703 | static int i915_runtime_pm_status(struct seq_file *m, void *unused) |
371db66a | 2704 | { |
36cdd013 | 2705 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
52a05c30 | 2706 | struct pci_dev *pdev = dev_priv->drm.pdev; |
371db66a | 2707 | |
a156e64d CW |
2708 | if (!HAS_RUNTIME_PM(dev_priv)) |
2709 | seq_puts(m, "Runtime power management not supported\n"); | |
371db66a | 2710 | |
67d97da3 | 2711 | seq_printf(m, "GPU idle: %s\n", yesno(!dev_priv->gt.awake)); |
371db66a | 2712 | seq_printf(m, "IRQs disabled: %s\n", |
9df7575f | 2713 | yesno(!intel_irqs_enabled(dev_priv))); |
0d804184 | 2714 | #ifdef CONFIG_PM |
a6aaec8b | 2715 | seq_printf(m, "Usage count: %d\n", |
36cdd013 | 2716 | atomic_read(&dev_priv->drm.dev->power.usage_count)); |
0d804184 CW |
2717 | #else |
2718 | seq_printf(m, "Device Power Management (CONFIG_PM) disabled\n"); | |
2719 | #endif | |
a156e64d | 2720 | seq_printf(m, "PCI device power state: %s [%d]\n", |
52a05c30 DW |
2721 | pci_power_name(pdev->current_state), |
2722 | pdev->current_state); | |
371db66a | 2723 | |
ec013e7f JB |
2724 | return 0; |
2725 | } | |
2726 | ||
1da51581 ID |
2727 | static int i915_power_domain_info(struct seq_file *m, void *unused) |
2728 | { | |
36cdd013 | 2729 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
1da51581 ID |
2730 | struct i915_power_domains *power_domains = &dev_priv->power_domains; |
2731 | int i; | |
2732 | ||
2733 | mutex_lock(&power_domains->lock); | |
2734 | ||
2735 | seq_printf(m, "%-25s %s\n", "Power well/domain", "Use count"); | |
2736 | for (i = 0; i < power_domains->power_well_count; i++) { | |
2737 | struct i915_power_well *power_well; | |
2738 | enum intel_display_power_domain power_domain; | |
2739 | ||
2740 | power_well = &power_domains->power_wells[i]; | |
2741 | seq_printf(m, "%-25s %d\n", power_well->name, | |
2742 | power_well->count); | |
2743 | ||
2744 | for (power_domain = 0; power_domain < POWER_DOMAIN_NUM; | |
2745 | power_domain++) { | |
2746 | if (!(BIT(power_domain) & power_well->domains)) | |
2747 | continue; | |
2748 | ||
2749 | seq_printf(m, " %-23s %d\n", | |
9895ad03 | 2750 | intel_display_power_domain_str(power_domain), |
1da51581 ID |
2751 | power_domains->domain_use_count[power_domain]); |
2752 | } | |
2753 | } | |
2754 | ||
2755 | mutex_unlock(&power_domains->lock); | |
2756 | ||
2757 | return 0; | |
2758 | } | |
2759 | ||
b7cec66d DL |
2760 | static int i915_dmc_info(struct seq_file *m, void *unused) |
2761 | { | |
36cdd013 | 2762 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
b7cec66d DL |
2763 | struct intel_csr *csr; |
2764 | ||
36cdd013 | 2765 | if (!HAS_CSR(dev_priv)) { |
b7cec66d DL |
2766 | seq_puts(m, "not supported\n"); |
2767 | return 0; | |
2768 | } | |
2769 | ||
2770 | csr = &dev_priv->csr; | |
2771 | ||
6fb403de MK |
2772 | intel_runtime_pm_get(dev_priv); |
2773 | ||
b7cec66d DL |
2774 | seq_printf(m, "fw loaded: %s\n", yesno(csr->dmc_payload != NULL)); |
2775 | seq_printf(m, "path: %s\n", csr->fw_path); | |
2776 | ||
2777 | if (!csr->dmc_payload) | |
6fb403de | 2778 | goto out; |
b7cec66d DL |
2779 | |
2780 | seq_printf(m, "version: %d.%d\n", CSR_VERSION_MAJOR(csr->version), | |
2781 | CSR_VERSION_MINOR(csr->version)); | |
2782 | ||
36cdd013 | 2783 | if (IS_SKYLAKE(dev_priv) && csr->version >= CSR_VERSION(1, 6)) { |
8337206d DL |
2784 | seq_printf(m, "DC3 -> DC5 count: %d\n", |
2785 | I915_READ(SKL_CSR_DC3_DC5_COUNT)); | |
2786 | seq_printf(m, "DC5 -> DC6 count: %d\n", | |
2787 | I915_READ(SKL_CSR_DC5_DC6_COUNT)); | |
36cdd013 | 2788 | } else if (IS_BROXTON(dev_priv) && csr->version >= CSR_VERSION(1, 4)) { |
16e11b99 MK |
2789 | seq_printf(m, "DC3 -> DC5 count: %d\n", |
2790 | I915_READ(BXT_CSR_DC3_DC5_COUNT)); | |
8337206d DL |
2791 | } |
2792 | ||
6fb403de MK |
2793 | out: |
2794 | seq_printf(m, "program base: 0x%08x\n", I915_READ(CSR_PROGRAM(0))); | |
2795 | seq_printf(m, "ssp base: 0x%08x\n", I915_READ(CSR_SSP_BASE)); | |
2796 | seq_printf(m, "htp: 0x%08x\n", I915_READ(CSR_HTP_SKL)); | |
2797 | ||
8337206d DL |
2798 | intel_runtime_pm_put(dev_priv); |
2799 | ||
b7cec66d DL |
2800 | return 0; |
2801 | } | |
2802 | ||
53f5e3ca JB |
2803 | static void intel_seq_print_mode(struct seq_file *m, int tabs, |
2804 | struct drm_display_mode *mode) | |
2805 | { | |
2806 | int i; | |
2807 | ||
2808 | for (i = 0; i < tabs; i++) | |
2809 | seq_putc(m, '\t'); | |
2810 | ||
2811 | seq_printf(m, "id %d:\"%s\" freq %d clock %d hdisp %d hss %d hse %d htot %d vdisp %d vss %d vse %d vtot %d type 0x%x flags 0x%x\n", | |
2812 | mode->base.id, mode->name, | |
2813 | mode->vrefresh, mode->clock, | |
2814 | mode->hdisplay, mode->hsync_start, | |
2815 | mode->hsync_end, mode->htotal, | |
2816 | mode->vdisplay, mode->vsync_start, | |
2817 | mode->vsync_end, mode->vtotal, | |
2818 | mode->type, mode->flags); | |
2819 | } | |
2820 | ||
2821 | static void intel_encoder_info(struct seq_file *m, | |
2822 | struct intel_crtc *intel_crtc, | |
2823 | struct intel_encoder *intel_encoder) | |
2824 | { | |
36cdd013 DW |
2825 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
2826 | struct drm_device *dev = &dev_priv->drm; | |
53f5e3ca JB |
2827 | struct drm_crtc *crtc = &intel_crtc->base; |
2828 | struct intel_connector *intel_connector; | |
2829 | struct drm_encoder *encoder; | |
2830 | ||
2831 | encoder = &intel_encoder->base; | |
2832 | seq_printf(m, "\tencoder %d: type: %s, connectors:\n", | |
8e329a03 | 2833 | encoder->base.id, encoder->name); |
53f5e3ca JB |
2834 | for_each_connector_on_encoder(dev, encoder, intel_connector) { |
2835 | struct drm_connector *connector = &intel_connector->base; | |
2836 | seq_printf(m, "\t\tconnector %d: type: %s, status: %s", | |
2837 | connector->base.id, | |
c23cc417 | 2838 | connector->name, |
53f5e3ca JB |
2839 | drm_get_connector_status_name(connector->status)); |
2840 | if (connector->status == connector_status_connected) { | |
2841 | struct drm_display_mode *mode = &crtc->mode; | |
2842 | seq_printf(m, ", mode:\n"); | |
2843 | intel_seq_print_mode(m, 2, mode); | |
2844 | } else { | |
2845 | seq_putc(m, '\n'); | |
2846 | } | |
2847 | } | |
2848 | } | |
2849 | ||
2850 | static void intel_crtc_info(struct seq_file *m, struct intel_crtc *intel_crtc) | |
2851 | { | |
36cdd013 DW |
2852 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
2853 | struct drm_device *dev = &dev_priv->drm; | |
53f5e3ca JB |
2854 | struct drm_crtc *crtc = &intel_crtc->base; |
2855 | struct intel_encoder *intel_encoder; | |
23a48d53 ML |
2856 | struct drm_plane_state *plane_state = crtc->primary->state; |
2857 | struct drm_framebuffer *fb = plane_state->fb; | |
53f5e3ca | 2858 | |
23a48d53 | 2859 | if (fb) |
5aa8a937 | 2860 | seq_printf(m, "\tfb: %d, pos: %dx%d, size: %dx%d\n", |
23a48d53 ML |
2861 | fb->base.id, plane_state->src_x >> 16, |
2862 | plane_state->src_y >> 16, fb->width, fb->height); | |
5aa8a937 MR |
2863 | else |
2864 | seq_puts(m, "\tprimary plane disabled\n"); | |
53f5e3ca JB |
2865 | for_each_encoder_on_crtc(dev, crtc, intel_encoder) |
2866 | intel_encoder_info(m, intel_crtc, intel_encoder); | |
2867 | } | |
2868 | ||
2869 | static void intel_panel_info(struct seq_file *m, struct intel_panel *panel) | |
2870 | { | |
2871 | struct drm_display_mode *mode = panel->fixed_mode; | |
2872 | ||
2873 | seq_printf(m, "\tfixed mode:\n"); | |
2874 | intel_seq_print_mode(m, 2, mode); | |
2875 | } | |
2876 | ||
2877 | static void intel_dp_info(struct seq_file *m, | |
2878 | struct intel_connector *intel_connector) | |
2879 | { | |
2880 | struct intel_encoder *intel_encoder = intel_connector->encoder; | |
2881 | struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base); | |
2882 | ||
2883 | seq_printf(m, "\tDPCD rev: %x\n", intel_dp->dpcd[DP_DPCD_REV]); | |
742f491d | 2884 | seq_printf(m, "\taudio support: %s\n", yesno(intel_dp->has_audio)); |
b6dabe3b | 2885 | if (intel_connector->base.connector_type == DRM_MODE_CONNECTOR_eDP) |
53f5e3ca | 2886 | intel_panel_info(m, &intel_connector->panel); |
80209e5f MK |
2887 | |
2888 | drm_dp_downstream_debug(m, intel_dp->dpcd, intel_dp->downstream_ports, | |
2889 | &intel_dp->aux); | |
53f5e3ca JB |
2890 | } |
2891 | ||
2892 | static void intel_hdmi_info(struct seq_file *m, | |
2893 | struct intel_connector *intel_connector) | |
2894 | { | |
2895 | struct intel_encoder *intel_encoder = intel_connector->encoder; | |
2896 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&intel_encoder->base); | |
2897 | ||
742f491d | 2898 | seq_printf(m, "\taudio support: %s\n", yesno(intel_hdmi->has_audio)); |
53f5e3ca JB |
2899 | } |
2900 | ||
2901 | static void intel_lvds_info(struct seq_file *m, | |
2902 | struct intel_connector *intel_connector) | |
2903 | { | |
2904 | intel_panel_info(m, &intel_connector->panel); | |
2905 | } | |
2906 | ||
2907 | static void intel_connector_info(struct seq_file *m, | |
2908 | struct drm_connector *connector) | |
2909 | { | |
2910 | struct intel_connector *intel_connector = to_intel_connector(connector); | |
2911 | struct intel_encoder *intel_encoder = intel_connector->encoder; | |
f103fc7d | 2912 | struct drm_display_mode *mode; |
53f5e3ca JB |
2913 | |
2914 | seq_printf(m, "connector %d: type %s, status: %s\n", | |
c23cc417 | 2915 | connector->base.id, connector->name, |
53f5e3ca JB |
2916 | drm_get_connector_status_name(connector->status)); |
2917 | if (connector->status == connector_status_connected) { | |
2918 | seq_printf(m, "\tname: %s\n", connector->display_info.name); | |
2919 | seq_printf(m, "\tphysical dimensions: %dx%dmm\n", | |
2920 | connector->display_info.width_mm, | |
2921 | connector->display_info.height_mm); | |
2922 | seq_printf(m, "\tsubpixel order: %s\n", | |
2923 | drm_get_subpixel_order_name(connector->display_info.subpixel_order)); | |
2924 | seq_printf(m, "\tCEA rev: %d\n", | |
2925 | connector->display_info.cea_rev); | |
2926 | } | |
ee648a74 ML |
2927 | |
2928 | if (!intel_encoder || intel_encoder->type == INTEL_OUTPUT_DP_MST) | |
2929 | return; | |
2930 | ||
2931 | switch (connector->connector_type) { | |
2932 | case DRM_MODE_CONNECTOR_DisplayPort: | |
2933 | case DRM_MODE_CONNECTOR_eDP: | |
be754b10 | 2934 | intel_dp_info(m, intel_connector); |
ee648a74 ML |
2935 | break; |
2936 | case DRM_MODE_CONNECTOR_LVDS: | |
2937 | if (intel_encoder->type == INTEL_OUTPUT_LVDS) | |
36cd7444 | 2938 | intel_lvds_info(m, intel_connector); |
ee648a74 ML |
2939 | break; |
2940 | case DRM_MODE_CONNECTOR_HDMIA: | |
2941 | if (intel_encoder->type == INTEL_OUTPUT_HDMI || | |
2942 | intel_encoder->type == INTEL_OUTPUT_UNKNOWN) | |
2943 | intel_hdmi_info(m, intel_connector); | |
2944 | break; | |
2945 | default: | |
2946 | break; | |
36cd7444 | 2947 | } |
53f5e3ca | 2948 | |
f103fc7d JB |
2949 | seq_printf(m, "\tmodes:\n"); |
2950 | list_for_each_entry(mode, &connector->modes, head) | |
2951 | intel_seq_print_mode(m, 2, mode); | |
53f5e3ca JB |
2952 | } |
2953 | ||
36cdd013 | 2954 | static bool cursor_active(struct drm_i915_private *dev_priv, int pipe) |
065f2ec2 | 2955 | { |
065f2ec2 CW |
2956 | u32 state; |
2957 | ||
36cdd013 | 2958 | if (IS_845G(dev_priv) || IS_I865G(dev_priv)) |
0b87c24e | 2959 | state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE; |
065f2ec2 | 2960 | else |
5efb3e28 | 2961 | state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE; |
065f2ec2 CW |
2962 | |
2963 | return state; | |
2964 | } | |
2965 | ||
36cdd013 DW |
2966 | static bool cursor_position(struct drm_i915_private *dev_priv, |
2967 | int pipe, int *x, int *y) | |
065f2ec2 | 2968 | { |
065f2ec2 CW |
2969 | u32 pos; |
2970 | ||
5efb3e28 | 2971 | pos = I915_READ(CURPOS(pipe)); |
065f2ec2 CW |
2972 | |
2973 | *x = (pos >> CURSOR_X_SHIFT) & CURSOR_POS_MASK; | |
2974 | if (pos & (CURSOR_POS_SIGN << CURSOR_X_SHIFT)) | |
2975 | *x = -*x; | |
2976 | ||
2977 | *y = (pos >> CURSOR_Y_SHIFT) & CURSOR_POS_MASK; | |
2978 | if (pos & (CURSOR_POS_SIGN << CURSOR_Y_SHIFT)) | |
2979 | *y = -*y; | |
2980 | ||
36cdd013 | 2981 | return cursor_active(dev_priv, pipe); |
065f2ec2 CW |
2982 | } |
2983 | ||
3abc4e09 RF |
2984 | static const char *plane_type(enum drm_plane_type type) |
2985 | { | |
2986 | switch (type) { | |
2987 | case DRM_PLANE_TYPE_OVERLAY: | |
2988 | return "OVL"; | |
2989 | case DRM_PLANE_TYPE_PRIMARY: | |
2990 | return "PRI"; | |
2991 | case DRM_PLANE_TYPE_CURSOR: | |
2992 | return "CUR"; | |
2993 | /* | |
2994 | * Deliberately omitting default: to generate compiler warnings | |
2995 | * when a new drm_plane_type gets added. | |
2996 | */ | |
2997 | } | |
2998 | ||
2999 | return "unknown"; | |
3000 | } | |
3001 | ||
3002 | static const char *plane_rotation(unsigned int rotation) | |
3003 | { | |
3004 | static char buf[48]; | |
3005 | /* | |
3006 | * According to doc only one DRM_ROTATE_ is allowed but this | |
3007 | * will print them all to visualize if the values are misused | |
3008 | */ | |
3009 | snprintf(buf, sizeof(buf), | |
3010 | "%s%s%s%s%s%s(0x%08x)", | |
31ad61e4 JL |
3011 | (rotation & DRM_ROTATE_0) ? "0 " : "", |
3012 | (rotation & DRM_ROTATE_90) ? "90 " : "", | |
3013 | (rotation & DRM_ROTATE_180) ? "180 " : "", | |
3014 | (rotation & DRM_ROTATE_270) ? "270 " : "", | |
3015 | (rotation & DRM_REFLECT_X) ? "FLIPX " : "", | |
3016 | (rotation & DRM_REFLECT_Y) ? "FLIPY " : "", | |
3abc4e09 RF |
3017 | rotation); |
3018 | ||
3019 | return buf; | |
3020 | } | |
3021 | ||
3022 | static void intel_plane_info(struct seq_file *m, struct intel_crtc *intel_crtc) | |
3023 | { | |
36cdd013 DW |
3024 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
3025 | struct drm_device *dev = &dev_priv->drm; | |
3abc4e09 RF |
3026 | struct intel_plane *intel_plane; |
3027 | ||
3028 | for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) { | |
3029 | struct drm_plane_state *state; | |
3030 | struct drm_plane *plane = &intel_plane->base; | |
3031 | ||
3032 | if (!plane->state) { | |
3033 | seq_puts(m, "plane->state is NULL!\n"); | |
3034 | continue; | |
3035 | } | |
3036 | ||
3037 | state = plane->state; | |
3038 | ||
3039 | seq_printf(m, "\t--Plane id %d: type=%s, crtc_pos=%4dx%4d, crtc_size=%4dx%4d, src_pos=%d.%04ux%d.%04u, src_size=%d.%04ux%d.%04u, format=%s, rotation=%s\n", | |
3040 | plane->base.id, | |
3041 | plane_type(intel_plane->base.type), | |
3042 | state->crtc_x, state->crtc_y, | |
3043 | state->crtc_w, state->crtc_h, | |
3044 | (state->src_x >> 16), | |
3045 | ((state->src_x & 0xffff) * 15625) >> 10, | |
3046 | (state->src_y >> 16), | |
3047 | ((state->src_y & 0xffff) * 15625) >> 10, | |
3048 | (state->src_w >> 16), | |
3049 | ((state->src_w & 0xffff) * 15625) >> 10, | |
3050 | (state->src_h >> 16), | |
3051 | ((state->src_h & 0xffff) * 15625) >> 10, | |
3052 | state->fb ? drm_get_format_name(state->fb->pixel_format) : "N/A", | |
3053 | plane_rotation(state->rotation)); | |
3054 | } | |
3055 | } | |
3056 | ||
3057 | static void intel_scaler_info(struct seq_file *m, struct intel_crtc *intel_crtc) | |
3058 | { | |
3059 | struct intel_crtc_state *pipe_config; | |
3060 | int num_scalers = intel_crtc->num_scalers; | |
3061 | int i; | |
3062 | ||
3063 | pipe_config = to_intel_crtc_state(intel_crtc->base.state); | |
3064 | ||
3065 | /* Not all platformas have a scaler */ | |
3066 | if (num_scalers) { | |
3067 | seq_printf(m, "\tnum_scalers=%d, scaler_users=%x scaler_id=%d", | |
3068 | num_scalers, | |
3069 | pipe_config->scaler_state.scaler_users, | |
3070 | pipe_config->scaler_state.scaler_id); | |
3071 | ||
3072 | for (i = 0; i < SKL_NUM_SCALERS; i++) { | |
3073 | struct intel_scaler *sc = | |
3074 | &pipe_config->scaler_state.scalers[i]; | |
3075 | ||
3076 | seq_printf(m, ", scalers[%d]: use=%s, mode=%x", | |
3077 | i, yesno(sc->in_use), sc->mode); | |
3078 | } | |
3079 | seq_puts(m, "\n"); | |
3080 | } else { | |
3081 | seq_puts(m, "\tNo scalers available on this platform\n"); | |
3082 | } | |
3083 | } | |
3084 | ||
53f5e3ca JB |
3085 | static int i915_display_info(struct seq_file *m, void *unused) |
3086 | { | |
36cdd013 DW |
3087 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
3088 | struct drm_device *dev = &dev_priv->drm; | |
065f2ec2 | 3089 | struct intel_crtc *crtc; |
53f5e3ca JB |
3090 | struct drm_connector *connector; |
3091 | ||
b0e5ddf3 | 3092 | intel_runtime_pm_get(dev_priv); |
53f5e3ca JB |
3093 | drm_modeset_lock_all(dev); |
3094 | seq_printf(m, "CRTC info\n"); | |
3095 | seq_printf(m, "---------\n"); | |
d3fcc808 | 3096 | for_each_intel_crtc(dev, crtc) { |
065f2ec2 | 3097 | bool active; |
f77076c9 | 3098 | struct intel_crtc_state *pipe_config; |
065f2ec2 | 3099 | int x, y; |
53f5e3ca | 3100 | |
f77076c9 ML |
3101 | pipe_config = to_intel_crtc_state(crtc->base.state); |
3102 | ||
3abc4e09 | 3103 | seq_printf(m, "CRTC %d: pipe: %c, active=%s, (size=%dx%d), dither=%s, bpp=%d\n", |
065f2ec2 | 3104 | crtc->base.base.id, pipe_name(crtc->pipe), |
f77076c9 | 3105 | yesno(pipe_config->base.active), |
3abc4e09 RF |
3106 | pipe_config->pipe_src_w, pipe_config->pipe_src_h, |
3107 | yesno(pipe_config->dither), pipe_config->pipe_bpp); | |
3108 | ||
f77076c9 | 3109 | if (pipe_config->base.active) { |
065f2ec2 CW |
3110 | intel_crtc_info(m, crtc); |
3111 | ||
36cdd013 | 3112 | active = cursor_position(dev_priv, crtc->pipe, &x, &y); |
57127efa | 3113 | seq_printf(m, "\tcursor visible? %s, position (%d, %d), size %dx%d, addr 0x%08x, active? %s\n", |
4b0e333e | 3114 | yesno(crtc->cursor_base), |
3dd512fb MR |
3115 | x, y, crtc->base.cursor->state->crtc_w, |
3116 | crtc->base.cursor->state->crtc_h, | |
57127efa | 3117 | crtc->cursor_addr, yesno(active)); |
3abc4e09 RF |
3118 | intel_scaler_info(m, crtc); |
3119 | intel_plane_info(m, crtc); | |
a23dc658 | 3120 | } |
cace841c DV |
3121 | |
3122 | seq_printf(m, "\tunderrun reporting: cpu=%s pch=%s \n", | |
3123 | yesno(!crtc->cpu_fifo_underrun_disabled), | |
3124 | yesno(!crtc->pch_fifo_underrun_disabled)); | |
53f5e3ca JB |
3125 | } |
3126 | ||
3127 | seq_printf(m, "\n"); | |
3128 | seq_printf(m, "Connector info\n"); | |
3129 | seq_printf(m, "--------------\n"); | |
3130 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
3131 | intel_connector_info(m, connector); | |
3132 | } | |
3133 | drm_modeset_unlock_all(dev); | |
b0e5ddf3 | 3134 | intel_runtime_pm_put(dev_priv); |
53f5e3ca JB |
3135 | |
3136 | return 0; | |
3137 | } | |
3138 | ||
e04934cf BW |
3139 | static int i915_semaphore_status(struct seq_file *m, void *unused) |
3140 | { | |
36cdd013 DW |
3141 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
3142 | struct drm_device *dev = &dev_priv->drm; | |
e2f80391 | 3143 | struct intel_engine_cs *engine; |
36cdd013 | 3144 | int num_rings = INTEL_INFO(dev_priv)->num_rings; |
c3232b18 DG |
3145 | enum intel_engine_id id; |
3146 | int j, ret; | |
e04934cf | 3147 | |
39df9190 | 3148 | if (!i915.semaphores) { |
e04934cf BW |
3149 | seq_puts(m, "Semaphores are disabled\n"); |
3150 | return 0; | |
3151 | } | |
3152 | ||
3153 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
3154 | if (ret) | |
3155 | return ret; | |
03872064 | 3156 | intel_runtime_pm_get(dev_priv); |
e04934cf | 3157 | |
36cdd013 | 3158 | if (IS_BROADWELL(dev_priv)) { |
e04934cf BW |
3159 | struct page *page; |
3160 | uint64_t *seqno; | |
3161 | ||
51d545d0 | 3162 | page = i915_gem_object_get_page(dev_priv->semaphore->obj, 0); |
e04934cf BW |
3163 | |
3164 | seqno = (uint64_t *)kmap_atomic(page); | |
c3232b18 | 3165 | for_each_engine_id(engine, dev_priv, id) { |
e04934cf BW |
3166 | uint64_t offset; |
3167 | ||
e2f80391 | 3168 | seq_printf(m, "%s\n", engine->name); |
e04934cf BW |
3169 | |
3170 | seq_puts(m, " Last signal:"); | |
3171 | for (j = 0; j < num_rings; j++) { | |
c3232b18 | 3172 | offset = id * I915_NUM_ENGINES + j; |
e04934cf BW |
3173 | seq_printf(m, "0x%08llx (0x%02llx) ", |
3174 | seqno[offset], offset * 8); | |
3175 | } | |
3176 | seq_putc(m, '\n'); | |
3177 | ||
3178 | seq_puts(m, " Last wait: "); | |
3179 | for (j = 0; j < num_rings; j++) { | |
c3232b18 | 3180 | offset = id + (j * I915_NUM_ENGINES); |
e04934cf BW |
3181 | seq_printf(m, "0x%08llx (0x%02llx) ", |
3182 | seqno[offset], offset * 8); | |
3183 | } | |
3184 | seq_putc(m, '\n'); | |
3185 | ||
3186 | } | |
3187 | kunmap_atomic(seqno); | |
3188 | } else { | |
3189 | seq_puts(m, " Last signal:"); | |
b4ac5afc | 3190 | for_each_engine(engine, dev_priv) |
e04934cf BW |
3191 | for (j = 0; j < num_rings; j++) |
3192 | seq_printf(m, "0x%08x\n", | |
e2f80391 | 3193 | I915_READ(engine->semaphore.mbox.signal[j])); |
e04934cf BW |
3194 | seq_putc(m, '\n'); |
3195 | } | |
3196 | ||
3197 | seq_puts(m, "\nSync seqno:\n"); | |
b4ac5afc DG |
3198 | for_each_engine(engine, dev_priv) { |
3199 | for (j = 0; j < num_rings; j++) | |
e2f80391 TU |
3200 | seq_printf(m, " 0x%08x ", |
3201 | engine->semaphore.sync_seqno[j]); | |
e04934cf BW |
3202 | seq_putc(m, '\n'); |
3203 | } | |
3204 | seq_putc(m, '\n'); | |
3205 | ||
03872064 | 3206 | intel_runtime_pm_put(dev_priv); |
e04934cf BW |
3207 | mutex_unlock(&dev->struct_mutex); |
3208 | return 0; | |
3209 | } | |
3210 | ||
728e29d7 DV |
3211 | static int i915_shared_dplls_info(struct seq_file *m, void *unused) |
3212 | { | |
36cdd013 DW |
3213 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
3214 | struct drm_device *dev = &dev_priv->drm; | |
728e29d7 DV |
3215 | int i; |
3216 | ||
3217 | drm_modeset_lock_all(dev); | |
3218 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { | |
3219 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; | |
3220 | ||
3221 | seq_printf(m, "DPLL%i: %s, id: %i\n", i, pll->name, pll->id); | |
2dd66ebd ML |
3222 | seq_printf(m, " crtc_mask: 0x%08x, active: 0x%x, on: %s\n", |
3223 | pll->config.crtc_mask, pll->active_mask, yesno(pll->on)); | |
728e29d7 | 3224 | seq_printf(m, " tracked hardware state:\n"); |
3e369b76 ACO |
3225 | seq_printf(m, " dpll: 0x%08x\n", pll->config.hw_state.dpll); |
3226 | seq_printf(m, " dpll_md: 0x%08x\n", | |
3227 | pll->config.hw_state.dpll_md); | |
3228 | seq_printf(m, " fp0: 0x%08x\n", pll->config.hw_state.fp0); | |
3229 | seq_printf(m, " fp1: 0x%08x\n", pll->config.hw_state.fp1); | |
3230 | seq_printf(m, " wrpll: 0x%08x\n", pll->config.hw_state.wrpll); | |
728e29d7 DV |
3231 | } |
3232 | drm_modeset_unlock_all(dev); | |
3233 | ||
3234 | return 0; | |
3235 | } | |
3236 | ||
1ed1ef9d | 3237 | static int i915_wa_registers(struct seq_file *m, void *unused) |
888b5995 AS |
3238 | { |
3239 | int i; | |
3240 | int ret; | |
e2f80391 | 3241 | struct intel_engine_cs *engine; |
36cdd013 DW |
3242 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
3243 | struct drm_device *dev = &dev_priv->drm; | |
33136b06 | 3244 | struct i915_workarounds *workarounds = &dev_priv->workarounds; |
c3232b18 | 3245 | enum intel_engine_id id; |
888b5995 | 3246 | |
888b5995 AS |
3247 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
3248 | if (ret) | |
3249 | return ret; | |
3250 | ||
3251 | intel_runtime_pm_get(dev_priv); | |
3252 | ||
33136b06 | 3253 | seq_printf(m, "Workarounds applied: %d\n", workarounds->count); |
c3232b18 | 3254 | for_each_engine_id(engine, dev_priv, id) |
33136b06 | 3255 | seq_printf(m, "HW whitelist count for %s: %d\n", |
c3232b18 | 3256 | engine->name, workarounds->hw_whitelist_count[id]); |
33136b06 | 3257 | for (i = 0; i < workarounds->count; ++i) { |
f0f59a00 VS |
3258 | i915_reg_t addr; |
3259 | u32 mask, value, read; | |
2fa60f6d | 3260 | bool ok; |
888b5995 | 3261 | |
33136b06 AS |
3262 | addr = workarounds->reg[i].addr; |
3263 | mask = workarounds->reg[i].mask; | |
3264 | value = workarounds->reg[i].value; | |
2fa60f6d MK |
3265 | read = I915_READ(addr); |
3266 | ok = (value & mask) == (read & mask); | |
3267 | seq_printf(m, "0x%X: 0x%08X, mask: 0x%08X, read: 0x%08x, status: %s\n", | |
f0f59a00 | 3268 | i915_mmio_reg_offset(addr), value, mask, read, ok ? "OK" : "FAIL"); |
888b5995 AS |
3269 | } |
3270 | ||
3271 | intel_runtime_pm_put(dev_priv); | |
3272 | mutex_unlock(&dev->struct_mutex); | |
3273 | ||
3274 | return 0; | |
3275 | } | |
3276 | ||
c5511e44 DL |
3277 | static int i915_ddb_info(struct seq_file *m, void *unused) |
3278 | { | |
36cdd013 DW |
3279 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
3280 | struct drm_device *dev = &dev_priv->drm; | |
c5511e44 DL |
3281 | struct skl_ddb_allocation *ddb; |
3282 | struct skl_ddb_entry *entry; | |
3283 | enum pipe pipe; | |
3284 | int plane; | |
3285 | ||
36cdd013 | 3286 | if (INTEL_GEN(dev_priv) < 9) |
2fcffe19 DL |
3287 | return 0; |
3288 | ||
c5511e44 DL |
3289 | drm_modeset_lock_all(dev); |
3290 | ||
3291 | ddb = &dev_priv->wm.skl_hw.ddb; | |
3292 | ||
3293 | seq_printf(m, "%-15s%8s%8s%8s\n", "", "Start", "End", "Size"); | |
3294 | ||
3295 | for_each_pipe(dev_priv, pipe) { | |
3296 | seq_printf(m, "Pipe %c\n", pipe_name(pipe)); | |
3297 | ||
dd740780 | 3298 | for_each_plane(dev_priv, pipe, plane) { |
c5511e44 DL |
3299 | entry = &ddb->plane[pipe][plane]; |
3300 | seq_printf(m, " Plane%-8d%8u%8u%8u\n", plane + 1, | |
3301 | entry->start, entry->end, | |
3302 | skl_ddb_entry_size(entry)); | |
3303 | } | |
3304 | ||
4969d33e | 3305 | entry = &ddb->plane[pipe][PLANE_CURSOR]; |
c5511e44 DL |
3306 | seq_printf(m, " %-13s%8u%8u%8u\n", "Cursor", entry->start, |
3307 | entry->end, skl_ddb_entry_size(entry)); | |
3308 | } | |
3309 | ||
3310 | drm_modeset_unlock_all(dev); | |
3311 | ||
3312 | return 0; | |
3313 | } | |
3314 | ||
a54746e3 | 3315 | static void drrs_status_per_crtc(struct seq_file *m, |
36cdd013 DW |
3316 | struct drm_device *dev, |
3317 | struct intel_crtc *intel_crtc) | |
a54746e3 | 3318 | { |
fac5e23e | 3319 | struct drm_i915_private *dev_priv = to_i915(dev); |
a54746e3 VK |
3320 | struct i915_drrs *drrs = &dev_priv->drrs; |
3321 | int vrefresh = 0; | |
26875fe5 | 3322 | struct drm_connector *connector; |
a54746e3 | 3323 | |
26875fe5 ML |
3324 | drm_for_each_connector(connector, dev) { |
3325 | if (connector->state->crtc != &intel_crtc->base) | |
3326 | continue; | |
3327 | ||
3328 | seq_printf(m, "%s:\n", connector->name); | |
a54746e3 VK |
3329 | } |
3330 | ||
3331 | if (dev_priv->vbt.drrs_type == STATIC_DRRS_SUPPORT) | |
3332 | seq_puts(m, "\tVBT: DRRS_type: Static"); | |
3333 | else if (dev_priv->vbt.drrs_type == SEAMLESS_DRRS_SUPPORT) | |
3334 | seq_puts(m, "\tVBT: DRRS_type: Seamless"); | |
3335 | else if (dev_priv->vbt.drrs_type == DRRS_NOT_SUPPORTED) | |
3336 | seq_puts(m, "\tVBT: DRRS_type: None"); | |
3337 | else | |
3338 | seq_puts(m, "\tVBT: DRRS_type: FIXME: Unrecognized Value"); | |
3339 | ||
3340 | seq_puts(m, "\n\n"); | |
3341 | ||
f77076c9 | 3342 | if (to_intel_crtc_state(intel_crtc->base.state)->has_drrs) { |
a54746e3 VK |
3343 | struct intel_panel *panel; |
3344 | ||
3345 | mutex_lock(&drrs->mutex); | |
3346 | /* DRRS Supported */ | |
3347 | seq_puts(m, "\tDRRS Supported: Yes\n"); | |
3348 | ||
3349 | /* disable_drrs() will make drrs->dp NULL */ | |
3350 | if (!drrs->dp) { | |
3351 | seq_puts(m, "Idleness DRRS: Disabled"); | |
3352 | mutex_unlock(&drrs->mutex); | |
3353 | return; | |
3354 | } | |
3355 | ||
3356 | panel = &drrs->dp->attached_connector->panel; | |
3357 | seq_printf(m, "\t\tBusy_frontbuffer_bits: 0x%X", | |
3358 | drrs->busy_frontbuffer_bits); | |
3359 | ||
3360 | seq_puts(m, "\n\t\t"); | |
3361 | if (drrs->refresh_rate_type == DRRS_HIGH_RR) { | |
3362 | seq_puts(m, "DRRS_State: DRRS_HIGH_RR\n"); | |
3363 | vrefresh = panel->fixed_mode->vrefresh; | |
3364 | } else if (drrs->refresh_rate_type == DRRS_LOW_RR) { | |
3365 | seq_puts(m, "DRRS_State: DRRS_LOW_RR\n"); | |
3366 | vrefresh = panel->downclock_mode->vrefresh; | |
3367 | } else { | |
3368 | seq_printf(m, "DRRS_State: Unknown(%d)\n", | |
3369 | drrs->refresh_rate_type); | |
3370 | mutex_unlock(&drrs->mutex); | |
3371 | return; | |
3372 | } | |
3373 | seq_printf(m, "\t\tVrefresh: %d", vrefresh); | |
3374 | ||
3375 | seq_puts(m, "\n\t\t"); | |
3376 | mutex_unlock(&drrs->mutex); | |
3377 | } else { | |
3378 | /* DRRS not supported. Print the VBT parameter*/ | |
3379 | seq_puts(m, "\tDRRS Supported : No"); | |
3380 | } | |
3381 | seq_puts(m, "\n"); | |
3382 | } | |
3383 | ||
3384 | static int i915_drrs_status(struct seq_file *m, void *unused) | |
3385 | { | |
36cdd013 DW |
3386 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
3387 | struct drm_device *dev = &dev_priv->drm; | |
a54746e3 VK |
3388 | struct intel_crtc *intel_crtc; |
3389 | int active_crtc_cnt = 0; | |
3390 | ||
26875fe5 | 3391 | drm_modeset_lock_all(dev); |
a54746e3 | 3392 | for_each_intel_crtc(dev, intel_crtc) { |
f77076c9 | 3393 | if (intel_crtc->base.state->active) { |
a54746e3 VK |
3394 | active_crtc_cnt++; |
3395 | seq_printf(m, "\nCRTC %d: ", active_crtc_cnt); | |
3396 | ||
3397 | drrs_status_per_crtc(m, dev, intel_crtc); | |
3398 | } | |
a54746e3 | 3399 | } |
26875fe5 | 3400 | drm_modeset_unlock_all(dev); |
a54746e3 VK |
3401 | |
3402 | if (!active_crtc_cnt) | |
3403 | seq_puts(m, "No active crtc found\n"); | |
3404 | ||
3405 | return 0; | |
3406 | } | |
3407 | ||
07144428 DL |
3408 | struct pipe_crc_info { |
3409 | const char *name; | |
36cdd013 | 3410 | struct drm_i915_private *dev_priv; |
07144428 DL |
3411 | enum pipe pipe; |
3412 | }; | |
3413 | ||
11bed958 DA |
3414 | static int i915_dp_mst_info(struct seq_file *m, void *unused) |
3415 | { | |
36cdd013 DW |
3416 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
3417 | struct drm_device *dev = &dev_priv->drm; | |
11bed958 DA |
3418 | struct intel_encoder *intel_encoder; |
3419 | struct intel_digital_port *intel_dig_port; | |
b6dabe3b ML |
3420 | struct drm_connector *connector; |
3421 | ||
11bed958 | 3422 | drm_modeset_lock_all(dev); |
b6dabe3b ML |
3423 | drm_for_each_connector(connector, dev) { |
3424 | if (connector->connector_type != DRM_MODE_CONNECTOR_DisplayPort) | |
11bed958 | 3425 | continue; |
b6dabe3b ML |
3426 | |
3427 | intel_encoder = intel_attached_encoder(connector); | |
3428 | if (!intel_encoder || intel_encoder->type == INTEL_OUTPUT_DP_MST) | |
3429 | continue; | |
3430 | ||
3431 | intel_dig_port = enc_to_dig_port(&intel_encoder->base); | |
11bed958 DA |
3432 | if (!intel_dig_port->dp.can_mst) |
3433 | continue; | |
b6dabe3b | 3434 | |
40ae80cc JB |
3435 | seq_printf(m, "MST Source Port %c\n", |
3436 | port_name(intel_dig_port->port)); | |
11bed958 DA |
3437 | drm_dp_mst_dump_topology(m, &intel_dig_port->dp.mst_mgr); |
3438 | } | |
3439 | drm_modeset_unlock_all(dev); | |
3440 | return 0; | |
3441 | } | |
3442 | ||
07144428 DL |
3443 | static int i915_pipe_crc_open(struct inode *inode, struct file *filep) |
3444 | { | |
be5c7a90 | 3445 | struct pipe_crc_info *info = inode->i_private; |
36cdd013 | 3446 | struct drm_i915_private *dev_priv = info->dev_priv; |
be5c7a90 DL |
3447 | struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe]; |
3448 | ||
36cdd013 | 3449 | if (info->pipe >= INTEL_INFO(dev_priv)->num_pipes) |
7eb1c496 DV |
3450 | return -ENODEV; |
3451 | ||
d538bbdf DL |
3452 | spin_lock_irq(&pipe_crc->lock); |
3453 | ||
3454 | if (pipe_crc->opened) { | |
3455 | spin_unlock_irq(&pipe_crc->lock); | |
be5c7a90 DL |
3456 | return -EBUSY; /* already open */ |
3457 | } | |
3458 | ||
d538bbdf | 3459 | pipe_crc->opened = true; |
07144428 DL |
3460 | filep->private_data = inode->i_private; |
3461 | ||
d538bbdf DL |
3462 | spin_unlock_irq(&pipe_crc->lock); |
3463 | ||
07144428 DL |
3464 | return 0; |
3465 | } | |
3466 | ||
3467 | static int i915_pipe_crc_release(struct inode *inode, struct file *filep) | |
3468 | { | |
be5c7a90 | 3469 | struct pipe_crc_info *info = inode->i_private; |
36cdd013 | 3470 | struct drm_i915_private *dev_priv = info->dev_priv; |
be5c7a90 DL |
3471 | struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe]; |
3472 | ||
d538bbdf DL |
3473 | spin_lock_irq(&pipe_crc->lock); |
3474 | pipe_crc->opened = false; | |
3475 | spin_unlock_irq(&pipe_crc->lock); | |
be5c7a90 | 3476 | |
07144428 DL |
3477 | return 0; |
3478 | } | |
3479 | ||
3480 | /* (6 fields, 8 chars each, space separated (5) + '\n') */ | |
3481 | #define PIPE_CRC_LINE_LEN (6 * 8 + 5 + 1) | |
3482 | /* account for \'0' */ | |
3483 | #define PIPE_CRC_BUFFER_LEN (PIPE_CRC_LINE_LEN + 1) | |
3484 | ||
3485 | static int pipe_crc_data_count(struct intel_pipe_crc *pipe_crc) | |
8bf1e9f1 | 3486 | { |
d538bbdf DL |
3487 | assert_spin_locked(&pipe_crc->lock); |
3488 | return CIRC_CNT(pipe_crc->head, pipe_crc->tail, | |
3489 | INTEL_PIPE_CRC_ENTRIES_NR); | |
07144428 DL |
3490 | } |
3491 | ||
3492 | static ssize_t | |
3493 | i915_pipe_crc_read(struct file *filep, char __user *user_buf, size_t count, | |
3494 | loff_t *pos) | |
3495 | { | |
3496 | struct pipe_crc_info *info = filep->private_data; | |
36cdd013 | 3497 | struct drm_i915_private *dev_priv = info->dev_priv; |
07144428 DL |
3498 | struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe]; |
3499 | char buf[PIPE_CRC_BUFFER_LEN]; | |
9ad6d99f | 3500 | int n_entries; |
07144428 DL |
3501 | ssize_t bytes_read; |
3502 | ||
3503 | /* | |
3504 | * Don't allow user space to provide buffers not big enough to hold | |
3505 | * a line of data. | |
3506 | */ | |
3507 | if (count < PIPE_CRC_LINE_LEN) | |
3508 | return -EINVAL; | |
3509 | ||
3510 | if (pipe_crc->source == INTEL_PIPE_CRC_SOURCE_NONE) | |
8bf1e9f1 | 3511 | return 0; |
07144428 DL |
3512 | |
3513 | /* nothing to read */ | |
d538bbdf | 3514 | spin_lock_irq(&pipe_crc->lock); |
07144428 | 3515 | while (pipe_crc_data_count(pipe_crc) == 0) { |
d538bbdf DL |
3516 | int ret; |
3517 | ||
3518 | if (filep->f_flags & O_NONBLOCK) { | |
3519 | spin_unlock_irq(&pipe_crc->lock); | |
07144428 | 3520 | return -EAGAIN; |
d538bbdf | 3521 | } |
07144428 | 3522 | |
d538bbdf DL |
3523 | ret = wait_event_interruptible_lock_irq(pipe_crc->wq, |
3524 | pipe_crc_data_count(pipe_crc), pipe_crc->lock); | |
3525 | if (ret) { | |
3526 | spin_unlock_irq(&pipe_crc->lock); | |
3527 | return ret; | |
3528 | } | |
8bf1e9f1 SH |
3529 | } |
3530 | ||
07144428 | 3531 | /* We now have one or more entries to read */ |
9ad6d99f | 3532 | n_entries = count / PIPE_CRC_LINE_LEN; |
d538bbdf | 3533 | |
07144428 | 3534 | bytes_read = 0; |
9ad6d99f VS |
3535 | while (n_entries > 0) { |
3536 | struct intel_pipe_crc_entry *entry = | |
3537 | &pipe_crc->entries[pipe_crc->tail]; | |
8bf1e9f1 | 3538 | |
9ad6d99f VS |
3539 | if (CIRC_CNT(pipe_crc->head, pipe_crc->tail, |
3540 | INTEL_PIPE_CRC_ENTRIES_NR) < 1) | |
3541 | break; | |
3542 | ||
3543 | BUILD_BUG_ON_NOT_POWER_OF_2(INTEL_PIPE_CRC_ENTRIES_NR); | |
3544 | pipe_crc->tail = (pipe_crc->tail + 1) & (INTEL_PIPE_CRC_ENTRIES_NR - 1); | |
3545 | ||
07144428 DL |
3546 | bytes_read += snprintf(buf, PIPE_CRC_BUFFER_LEN, |
3547 | "%8u %8x %8x %8x %8x %8x\n", | |
3548 | entry->frame, entry->crc[0], | |
3549 | entry->crc[1], entry->crc[2], | |
3550 | entry->crc[3], entry->crc[4]); | |
3551 | ||
9ad6d99f VS |
3552 | spin_unlock_irq(&pipe_crc->lock); |
3553 | ||
4e9121e6 | 3554 | if (copy_to_user(user_buf, buf, PIPE_CRC_LINE_LEN)) |
07144428 | 3555 | return -EFAULT; |
b2c88f5b | 3556 | |
9ad6d99f VS |
3557 | user_buf += PIPE_CRC_LINE_LEN; |
3558 | n_entries--; | |
3559 | ||
3560 | spin_lock_irq(&pipe_crc->lock); | |
3561 | } | |
8bf1e9f1 | 3562 | |
d538bbdf DL |
3563 | spin_unlock_irq(&pipe_crc->lock); |
3564 | ||
07144428 DL |
3565 | return bytes_read; |
3566 | } | |
3567 | ||
3568 | static const struct file_operations i915_pipe_crc_fops = { | |
3569 | .owner = THIS_MODULE, | |
3570 | .open = i915_pipe_crc_open, | |
3571 | .read = i915_pipe_crc_read, | |
3572 | .release = i915_pipe_crc_release, | |
3573 | }; | |
3574 | ||
3575 | static struct pipe_crc_info i915_pipe_crc_data[I915_MAX_PIPES] = { | |
3576 | { | |
3577 | .name = "i915_pipe_A_crc", | |
3578 | .pipe = PIPE_A, | |
3579 | }, | |
3580 | { | |
3581 | .name = "i915_pipe_B_crc", | |
3582 | .pipe = PIPE_B, | |
3583 | }, | |
3584 | { | |
3585 | .name = "i915_pipe_C_crc", | |
3586 | .pipe = PIPE_C, | |
3587 | }, | |
3588 | }; | |
3589 | ||
3590 | static int i915_pipe_crc_create(struct dentry *root, struct drm_minor *minor, | |
3591 | enum pipe pipe) | |
3592 | { | |
36cdd013 | 3593 | struct drm_i915_private *dev_priv = to_i915(minor->dev); |
07144428 DL |
3594 | struct dentry *ent; |
3595 | struct pipe_crc_info *info = &i915_pipe_crc_data[pipe]; | |
3596 | ||
36cdd013 | 3597 | info->dev_priv = dev_priv; |
07144428 DL |
3598 | ent = debugfs_create_file(info->name, S_IRUGO, root, info, |
3599 | &i915_pipe_crc_fops); | |
f3c5fe97 WY |
3600 | if (!ent) |
3601 | return -ENOMEM; | |
07144428 DL |
3602 | |
3603 | return drm_add_fake_info_node(minor, ent, info); | |
8bf1e9f1 SH |
3604 | } |
3605 | ||
e8dfcf78 | 3606 | static const char * const pipe_crc_sources[] = { |
926321d5 DV |
3607 | "none", |
3608 | "plane1", | |
3609 | "plane2", | |
3610 | "pf", | |
5b3a856b | 3611 | "pipe", |
3d099a05 DV |
3612 | "TV", |
3613 | "DP-B", | |
3614 | "DP-C", | |
3615 | "DP-D", | |
46a19188 | 3616 | "auto", |
926321d5 DV |
3617 | }; |
3618 | ||
3619 | static const char *pipe_crc_source_name(enum intel_pipe_crc_source source) | |
3620 | { | |
3621 | BUILD_BUG_ON(ARRAY_SIZE(pipe_crc_sources) != INTEL_PIPE_CRC_SOURCE_MAX); | |
3622 | return pipe_crc_sources[source]; | |
3623 | } | |
3624 | ||
bd9db02f | 3625 | static int display_crc_ctl_show(struct seq_file *m, void *data) |
926321d5 | 3626 | { |
36cdd013 | 3627 | struct drm_i915_private *dev_priv = m->private; |
926321d5 DV |
3628 | int i; |
3629 | ||
3630 | for (i = 0; i < I915_MAX_PIPES; i++) | |
3631 | seq_printf(m, "%c %s\n", pipe_name(i), | |
3632 | pipe_crc_source_name(dev_priv->pipe_crc[i].source)); | |
3633 | ||
3634 | return 0; | |
3635 | } | |
3636 | ||
bd9db02f | 3637 | static int display_crc_ctl_open(struct inode *inode, struct file *file) |
926321d5 | 3638 | { |
36cdd013 | 3639 | return single_open(file, display_crc_ctl_show, inode->i_private); |
926321d5 DV |
3640 | } |
3641 | ||
46a19188 | 3642 | static int i8xx_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source, |
52f843f6 DV |
3643 | uint32_t *val) |
3644 | { | |
46a19188 DV |
3645 | if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) |
3646 | *source = INTEL_PIPE_CRC_SOURCE_PIPE; | |
3647 | ||
3648 | switch (*source) { | |
52f843f6 DV |
3649 | case INTEL_PIPE_CRC_SOURCE_PIPE: |
3650 | *val = PIPE_CRC_ENABLE | PIPE_CRC_INCLUDE_BORDER_I8XX; | |
3651 | break; | |
3652 | case INTEL_PIPE_CRC_SOURCE_NONE: | |
3653 | *val = 0; | |
3654 | break; | |
3655 | default: | |
3656 | return -EINVAL; | |
3657 | } | |
3658 | ||
3659 | return 0; | |
3660 | } | |
3661 | ||
36cdd013 DW |
3662 | static int i9xx_pipe_crc_auto_source(struct drm_i915_private *dev_priv, |
3663 | enum pipe pipe, | |
46a19188 DV |
3664 | enum intel_pipe_crc_source *source) |
3665 | { | |
36cdd013 | 3666 | struct drm_device *dev = &dev_priv->drm; |
46a19188 DV |
3667 | struct intel_encoder *encoder; |
3668 | struct intel_crtc *crtc; | |
26756809 | 3669 | struct intel_digital_port *dig_port; |
46a19188 DV |
3670 | int ret = 0; |
3671 | ||
3672 | *source = INTEL_PIPE_CRC_SOURCE_PIPE; | |
3673 | ||
6e9f798d | 3674 | drm_modeset_lock_all(dev); |
b2784e15 | 3675 | for_each_intel_encoder(dev, encoder) { |
46a19188 DV |
3676 | if (!encoder->base.crtc) |
3677 | continue; | |
3678 | ||
3679 | crtc = to_intel_crtc(encoder->base.crtc); | |
3680 | ||
3681 | if (crtc->pipe != pipe) | |
3682 | continue; | |
3683 | ||
3684 | switch (encoder->type) { | |
3685 | case INTEL_OUTPUT_TVOUT: | |
3686 | *source = INTEL_PIPE_CRC_SOURCE_TV; | |
3687 | break; | |
cca0502b | 3688 | case INTEL_OUTPUT_DP: |
46a19188 | 3689 | case INTEL_OUTPUT_EDP: |
26756809 DV |
3690 | dig_port = enc_to_dig_port(&encoder->base); |
3691 | switch (dig_port->port) { | |
3692 | case PORT_B: | |
3693 | *source = INTEL_PIPE_CRC_SOURCE_DP_B; | |
3694 | break; | |
3695 | case PORT_C: | |
3696 | *source = INTEL_PIPE_CRC_SOURCE_DP_C; | |
3697 | break; | |
3698 | case PORT_D: | |
3699 | *source = INTEL_PIPE_CRC_SOURCE_DP_D; | |
3700 | break; | |
3701 | default: | |
3702 | WARN(1, "nonexisting DP port %c\n", | |
3703 | port_name(dig_port->port)); | |
3704 | break; | |
3705 | } | |
46a19188 | 3706 | break; |
6847d71b PZ |
3707 | default: |
3708 | break; | |
46a19188 DV |
3709 | } |
3710 | } | |
6e9f798d | 3711 | drm_modeset_unlock_all(dev); |
46a19188 DV |
3712 | |
3713 | return ret; | |
3714 | } | |
3715 | ||
36cdd013 | 3716 | static int vlv_pipe_crc_ctl_reg(struct drm_i915_private *dev_priv, |
46a19188 DV |
3717 | enum pipe pipe, |
3718 | enum intel_pipe_crc_source *source, | |
7ac0129b DV |
3719 | uint32_t *val) |
3720 | { | |
8d2f24ca DV |
3721 | bool need_stable_symbols = false; |
3722 | ||
46a19188 | 3723 | if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) { |
36cdd013 | 3724 | int ret = i9xx_pipe_crc_auto_source(dev_priv, pipe, source); |
46a19188 DV |
3725 | if (ret) |
3726 | return ret; | |
3727 | } | |
3728 | ||
3729 | switch (*source) { | |
7ac0129b DV |
3730 | case INTEL_PIPE_CRC_SOURCE_PIPE: |
3731 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_VLV; | |
3732 | break; | |
3733 | case INTEL_PIPE_CRC_SOURCE_DP_B: | |
3734 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_VLV; | |
8d2f24ca | 3735 | need_stable_symbols = true; |
7ac0129b DV |
3736 | break; |
3737 | case INTEL_PIPE_CRC_SOURCE_DP_C: | |
3738 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_VLV; | |
8d2f24ca | 3739 | need_stable_symbols = true; |
7ac0129b | 3740 | break; |
2be57922 | 3741 | case INTEL_PIPE_CRC_SOURCE_DP_D: |
36cdd013 | 3742 | if (!IS_CHERRYVIEW(dev_priv)) |
2be57922 VS |
3743 | return -EINVAL; |
3744 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_VLV; | |
3745 | need_stable_symbols = true; | |
3746 | break; | |
7ac0129b DV |
3747 | case INTEL_PIPE_CRC_SOURCE_NONE: |
3748 | *val = 0; | |
3749 | break; | |
3750 | default: | |
3751 | return -EINVAL; | |
3752 | } | |
3753 | ||
8d2f24ca DV |
3754 | /* |
3755 | * When the pipe CRC tap point is after the transcoders we need | |
3756 | * to tweak symbol-level features to produce a deterministic series of | |
3757 | * symbols for a given frame. We need to reset those features only once | |
3758 | * a frame (instead of every nth symbol): | |
3759 | * - DC-balance: used to ensure a better clock recovery from the data | |
3760 | * link (SDVO) | |
3761 | * - DisplayPort scrambling: used for EMI reduction | |
3762 | */ | |
3763 | if (need_stable_symbols) { | |
3764 | uint32_t tmp = I915_READ(PORT_DFT2_G4X); | |
3765 | ||
8d2f24ca | 3766 | tmp |= DC_BALANCE_RESET_VLV; |
eb736679 VS |
3767 | switch (pipe) { |
3768 | case PIPE_A: | |
8d2f24ca | 3769 | tmp |= PIPE_A_SCRAMBLE_RESET; |
eb736679 VS |
3770 | break; |
3771 | case PIPE_B: | |
8d2f24ca | 3772 | tmp |= PIPE_B_SCRAMBLE_RESET; |
eb736679 VS |
3773 | break; |
3774 | case PIPE_C: | |
3775 | tmp |= PIPE_C_SCRAMBLE_RESET; | |
3776 | break; | |
3777 | default: | |
3778 | return -EINVAL; | |
3779 | } | |
8d2f24ca DV |
3780 | I915_WRITE(PORT_DFT2_G4X, tmp); |
3781 | } | |
3782 | ||
7ac0129b DV |
3783 | return 0; |
3784 | } | |
3785 | ||
36cdd013 | 3786 | static int i9xx_pipe_crc_ctl_reg(struct drm_i915_private *dev_priv, |
46a19188 DV |
3787 | enum pipe pipe, |
3788 | enum intel_pipe_crc_source *source, | |
4b79ebf7 DV |
3789 | uint32_t *val) |
3790 | { | |
84093603 DV |
3791 | bool need_stable_symbols = false; |
3792 | ||
46a19188 | 3793 | if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) { |
36cdd013 | 3794 | int ret = i9xx_pipe_crc_auto_source(dev_priv, pipe, source); |
46a19188 DV |
3795 | if (ret) |
3796 | return ret; | |
3797 | } | |
3798 | ||
3799 | switch (*source) { | |
4b79ebf7 DV |
3800 | case INTEL_PIPE_CRC_SOURCE_PIPE: |
3801 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_I9XX; | |
3802 | break; | |
3803 | case INTEL_PIPE_CRC_SOURCE_TV: | |
36cdd013 | 3804 | if (!SUPPORTS_TV(dev_priv)) |
4b79ebf7 DV |
3805 | return -EINVAL; |
3806 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_TV_PRE; | |
3807 | break; | |
3808 | case INTEL_PIPE_CRC_SOURCE_DP_B: | |
36cdd013 | 3809 | if (!IS_G4X(dev_priv)) |
4b79ebf7 DV |
3810 | return -EINVAL; |
3811 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_G4X; | |
84093603 | 3812 | need_stable_symbols = true; |
4b79ebf7 DV |
3813 | break; |
3814 | case INTEL_PIPE_CRC_SOURCE_DP_C: | |
36cdd013 | 3815 | if (!IS_G4X(dev_priv)) |
4b79ebf7 DV |
3816 | return -EINVAL; |
3817 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_G4X; | |
84093603 | 3818 | need_stable_symbols = true; |
4b79ebf7 DV |
3819 | break; |
3820 | case INTEL_PIPE_CRC_SOURCE_DP_D: | |
36cdd013 | 3821 | if (!IS_G4X(dev_priv)) |
4b79ebf7 DV |
3822 | return -EINVAL; |
3823 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_G4X; | |
84093603 | 3824 | need_stable_symbols = true; |
4b79ebf7 DV |
3825 | break; |
3826 | case INTEL_PIPE_CRC_SOURCE_NONE: | |
3827 | *val = 0; | |
3828 | break; | |
3829 | default: | |
3830 | return -EINVAL; | |
3831 | } | |
3832 | ||
84093603 DV |
3833 | /* |
3834 | * When the pipe CRC tap point is after the transcoders we need | |
3835 | * to tweak symbol-level features to produce a deterministic series of | |
3836 | * symbols for a given frame. We need to reset those features only once | |
3837 | * a frame (instead of every nth symbol): | |
3838 | * - DC-balance: used to ensure a better clock recovery from the data | |
3839 | * link (SDVO) | |
3840 | * - DisplayPort scrambling: used for EMI reduction | |
3841 | */ | |
3842 | if (need_stable_symbols) { | |
3843 | uint32_t tmp = I915_READ(PORT_DFT2_G4X); | |
3844 | ||
36cdd013 | 3845 | WARN_ON(!IS_G4X(dev_priv)); |
84093603 DV |
3846 | |
3847 | I915_WRITE(PORT_DFT_I9XX, | |
3848 | I915_READ(PORT_DFT_I9XX) | DC_BALANCE_RESET); | |
3849 | ||
3850 | if (pipe == PIPE_A) | |
3851 | tmp |= PIPE_A_SCRAMBLE_RESET; | |
3852 | else | |
3853 | tmp |= PIPE_B_SCRAMBLE_RESET; | |
3854 | ||
3855 | I915_WRITE(PORT_DFT2_G4X, tmp); | |
3856 | } | |
3857 | ||
4b79ebf7 DV |
3858 | return 0; |
3859 | } | |
3860 | ||
36cdd013 | 3861 | static void vlv_undo_pipe_scramble_reset(struct drm_i915_private *dev_priv, |
8d2f24ca DV |
3862 | enum pipe pipe) |
3863 | { | |
8d2f24ca DV |
3864 | uint32_t tmp = I915_READ(PORT_DFT2_G4X); |
3865 | ||
eb736679 VS |
3866 | switch (pipe) { |
3867 | case PIPE_A: | |
8d2f24ca | 3868 | tmp &= ~PIPE_A_SCRAMBLE_RESET; |
eb736679 VS |
3869 | break; |
3870 | case PIPE_B: | |
8d2f24ca | 3871 | tmp &= ~PIPE_B_SCRAMBLE_RESET; |
eb736679 VS |
3872 | break; |
3873 | case PIPE_C: | |
3874 | tmp &= ~PIPE_C_SCRAMBLE_RESET; | |
3875 | break; | |
3876 | default: | |
3877 | return; | |
3878 | } | |
8d2f24ca DV |
3879 | if (!(tmp & PIPE_SCRAMBLE_RESET_MASK)) |
3880 | tmp &= ~DC_BALANCE_RESET_VLV; | |
3881 | I915_WRITE(PORT_DFT2_G4X, tmp); | |
3882 | ||
3883 | } | |
3884 | ||
36cdd013 | 3885 | static void g4x_undo_pipe_scramble_reset(struct drm_i915_private *dev_priv, |
84093603 DV |
3886 | enum pipe pipe) |
3887 | { | |
84093603 DV |
3888 | uint32_t tmp = I915_READ(PORT_DFT2_G4X); |
3889 | ||
3890 | if (pipe == PIPE_A) | |
3891 | tmp &= ~PIPE_A_SCRAMBLE_RESET; | |
3892 | else | |
3893 | tmp &= ~PIPE_B_SCRAMBLE_RESET; | |
3894 | I915_WRITE(PORT_DFT2_G4X, tmp); | |
3895 | ||
3896 | if (!(tmp & PIPE_SCRAMBLE_RESET_MASK)) { | |
3897 | I915_WRITE(PORT_DFT_I9XX, | |
3898 | I915_READ(PORT_DFT_I9XX) & ~DC_BALANCE_RESET); | |
3899 | } | |
3900 | } | |
3901 | ||
46a19188 | 3902 | static int ilk_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source, |
5b3a856b DV |
3903 | uint32_t *val) |
3904 | { | |
46a19188 DV |
3905 | if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) |
3906 | *source = INTEL_PIPE_CRC_SOURCE_PIPE; | |
3907 | ||
3908 | switch (*source) { | |
5b3a856b DV |
3909 | case INTEL_PIPE_CRC_SOURCE_PLANE1: |
3910 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_ILK; | |
3911 | break; | |
3912 | case INTEL_PIPE_CRC_SOURCE_PLANE2: | |
3913 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_ILK; | |
3914 | break; | |
5b3a856b DV |
3915 | case INTEL_PIPE_CRC_SOURCE_PIPE: |
3916 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_ILK; | |
3917 | break; | |
3d099a05 | 3918 | case INTEL_PIPE_CRC_SOURCE_NONE: |
5b3a856b DV |
3919 | *val = 0; |
3920 | break; | |
3d099a05 DV |
3921 | default: |
3922 | return -EINVAL; | |
5b3a856b DV |
3923 | } |
3924 | ||
3925 | return 0; | |
3926 | } | |
3927 | ||
36cdd013 DW |
3928 | static void hsw_trans_edp_pipe_A_crc_wa(struct drm_i915_private *dev_priv, |
3929 | bool enable) | |
fabf6e51 | 3930 | { |
36cdd013 | 3931 | struct drm_device *dev = &dev_priv->drm; |
fabf6e51 DV |
3932 | struct intel_crtc *crtc = |
3933 | to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_A]); | |
f77076c9 | 3934 | struct intel_crtc_state *pipe_config; |
c4e2d043 ML |
3935 | struct drm_atomic_state *state; |
3936 | int ret = 0; | |
fabf6e51 DV |
3937 | |
3938 | drm_modeset_lock_all(dev); | |
c4e2d043 ML |
3939 | state = drm_atomic_state_alloc(dev); |
3940 | if (!state) { | |
3941 | ret = -ENOMEM; | |
3942 | goto out; | |
fabf6e51 | 3943 | } |
fabf6e51 | 3944 | |
c4e2d043 ML |
3945 | state->acquire_ctx = drm_modeset_legacy_acquire_ctx(&crtc->base); |
3946 | pipe_config = intel_atomic_get_crtc_state(state, crtc); | |
3947 | if (IS_ERR(pipe_config)) { | |
3948 | ret = PTR_ERR(pipe_config); | |
3949 | goto out; | |
3950 | } | |
fabf6e51 | 3951 | |
c4e2d043 ML |
3952 | pipe_config->pch_pfit.force_thru = enable; |
3953 | if (pipe_config->cpu_transcoder == TRANSCODER_EDP && | |
3954 | pipe_config->pch_pfit.enabled != enable) | |
3955 | pipe_config->base.connectors_changed = true; | |
1b509259 | 3956 | |
c4e2d043 ML |
3957 | ret = drm_atomic_commit(state); |
3958 | out: | |
fabf6e51 | 3959 | drm_modeset_unlock_all(dev); |
c4e2d043 ML |
3960 | WARN(ret, "Toggling workaround to %i returns %i\n", enable, ret); |
3961 | if (ret) | |
3962 | drm_atomic_state_free(state); | |
fabf6e51 DV |
3963 | } |
3964 | ||
36cdd013 | 3965 | static int ivb_pipe_crc_ctl_reg(struct drm_i915_private *dev_priv, |
fabf6e51 DV |
3966 | enum pipe pipe, |
3967 | enum intel_pipe_crc_source *source, | |
5b3a856b DV |
3968 | uint32_t *val) |
3969 | { | |
46a19188 DV |
3970 | if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) |
3971 | *source = INTEL_PIPE_CRC_SOURCE_PF; | |
3972 | ||
3973 | switch (*source) { | |
5b3a856b DV |
3974 | case INTEL_PIPE_CRC_SOURCE_PLANE1: |
3975 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_IVB; | |
3976 | break; | |
3977 | case INTEL_PIPE_CRC_SOURCE_PLANE2: | |
3978 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_IVB; | |
3979 | break; | |
3980 | case INTEL_PIPE_CRC_SOURCE_PF: | |
36cdd013 DW |
3981 | if (IS_HASWELL(dev_priv) && pipe == PIPE_A) |
3982 | hsw_trans_edp_pipe_A_crc_wa(dev_priv, true); | |
fabf6e51 | 3983 | |
5b3a856b DV |
3984 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PF_IVB; |
3985 | break; | |
3d099a05 | 3986 | case INTEL_PIPE_CRC_SOURCE_NONE: |
5b3a856b DV |
3987 | *val = 0; |
3988 | break; | |
3d099a05 DV |
3989 | default: |
3990 | return -EINVAL; | |
5b3a856b DV |
3991 | } |
3992 | ||
3993 | return 0; | |
3994 | } | |
3995 | ||
36cdd013 DW |
3996 | static int pipe_crc_set_source(struct drm_i915_private *dev_priv, |
3997 | enum pipe pipe, | |
926321d5 DV |
3998 | enum intel_pipe_crc_source source) |
3999 | { | |
36cdd013 | 4000 | struct drm_device *dev = &dev_priv->drm; |
cc3da175 | 4001 | struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe]; |
36cdd013 DW |
4002 | struct intel_crtc *crtc = |
4003 | to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe)); | |
e129649b | 4004 | enum intel_display_power_domain power_domain; |
432f3342 | 4005 | u32 val = 0; /* shut up gcc */ |
5b3a856b | 4006 | int ret; |
926321d5 | 4007 | |
cc3da175 DL |
4008 | if (pipe_crc->source == source) |
4009 | return 0; | |
4010 | ||
ae676fcd DL |
4011 | /* forbid changing the source without going back to 'none' */ |
4012 | if (pipe_crc->source && source) | |
4013 | return -EINVAL; | |
4014 | ||
e129649b ID |
4015 | power_domain = POWER_DOMAIN_PIPE(pipe); |
4016 | if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) { | |
9d8b0588 DV |
4017 | DRM_DEBUG_KMS("Trying to capture CRC while pipe is off\n"); |
4018 | return -EIO; | |
4019 | } | |
4020 | ||
36cdd013 | 4021 | if (IS_GEN2(dev_priv)) |
46a19188 | 4022 | ret = i8xx_pipe_crc_ctl_reg(&source, &val); |
36cdd013 DW |
4023 | else if (INTEL_GEN(dev_priv) < 5) |
4024 | ret = i9xx_pipe_crc_ctl_reg(dev_priv, pipe, &source, &val); | |
4025 | else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) | |
4026 | ret = vlv_pipe_crc_ctl_reg(dev_priv, pipe, &source, &val); | |
4027 | else if (IS_GEN5(dev_priv) || IS_GEN6(dev_priv)) | |
46a19188 | 4028 | ret = ilk_pipe_crc_ctl_reg(&source, &val); |
5b3a856b | 4029 | else |
36cdd013 | 4030 | ret = ivb_pipe_crc_ctl_reg(dev_priv, pipe, &source, &val); |
5b3a856b DV |
4031 | |
4032 | if (ret != 0) | |
e129649b | 4033 | goto out; |
5b3a856b | 4034 | |
4b584369 DL |
4035 | /* none -> real source transition */ |
4036 | if (source) { | |
4252fbc3 VS |
4037 | struct intel_pipe_crc_entry *entries; |
4038 | ||
7cd6ccff DL |
4039 | DRM_DEBUG_DRIVER("collecting CRCs for pipe %c, %s\n", |
4040 | pipe_name(pipe), pipe_crc_source_name(source)); | |
4041 | ||
3cf54b34 VS |
4042 | entries = kcalloc(INTEL_PIPE_CRC_ENTRIES_NR, |
4043 | sizeof(pipe_crc->entries[0]), | |
4252fbc3 | 4044 | GFP_KERNEL); |
e129649b ID |
4045 | if (!entries) { |
4046 | ret = -ENOMEM; | |
4047 | goto out; | |
4048 | } | |
e5f75aca | 4049 | |
8c740dce PZ |
4050 | /* |
4051 | * When IPS gets enabled, the pipe CRC changes. Since IPS gets | |
4052 | * enabled and disabled dynamically based on package C states, | |
4053 | * user space can't make reliable use of the CRCs, so let's just | |
4054 | * completely disable it. | |
4055 | */ | |
4056 | hsw_disable_ips(crtc); | |
4057 | ||
d538bbdf | 4058 | spin_lock_irq(&pipe_crc->lock); |
64387b61 | 4059 | kfree(pipe_crc->entries); |
4252fbc3 | 4060 | pipe_crc->entries = entries; |
d538bbdf DL |
4061 | pipe_crc->head = 0; |
4062 | pipe_crc->tail = 0; | |
4063 | spin_unlock_irq(&pipe_crc->lock); | |
4b584369 DL |
4064 | } |
4065 | ||
cc3da175 | 4066 | pipe_crc->source = source; |
926321d5 | 4067 | |
926321d5 DV |
4068 | I915_WRITE(PIPE_CRC_CTL(pipe), val); |
4069 | POSTING_READ(PIPE_CRC_CTL(pipe)); | |
4070 | ||
e5f75aca DL |
4071 | /* real source -> none transition */ |
4072 | if (source == INTEL_PIPE_CRC_SOURCE_NONE) { | |
d538bbdf | 4073 | struct intel_pipe_crc_entry *entries; |
a33d7105 DV |
4074 | struct intel_crtc *crtc = |
4075 | to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); | |
d538bbdf | 4076 | |
7cd6ccff DL |
4077 | DRM_DEBUG_DRIVER("stopping CRCs for pipe %c\n", |
4078 | pipe_name(pipe)); | |
4079 | ||
a33d7105 | 4080 | drm_modeset_lock(&crtc->base.mutex, NULL); |
f77076c9 | 4081 | if (crtc->base.state->active) |
a33d7105 DV |
4082 | intel_wait_for_vblank(dev, pipe); |
4083 | drm_modeset_unlock(&crtc->base.mutex); | |
bcf17ab2 | 4084 | |
d538bbdf DL |
4085 | spin_lock_irq(&pipe_crc->lock); |
4086 | entries = pipe_crc->entries; | |
e5f75aca | 4087 | pipe_crc->entries = NULL; |
9ad6d99f VS |
4088 | pipe_crc->head = 0; |
4089 | pipe_crc->tail = 0; | |
d538bbdf DL |
4090 | spin_unlock_irq(&pipe_crc->lock); |
4091 | ||
4092 | kfree(entries); | |
84093603 | 4093 | |
36cdd013 DW |
4094 | if (IS_G4X(dev_priv)) |
4095 | g4x_undo_pipe_scramble_reset(dev_priv, pipe); | |
4096 | else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) | |
4097 | vlv_undo_pipe_scramble_reset(dev_priv, pipe); | |
4098 | else if (IS_HASWELL(dev_priv) && pipe == PIPE_A) | |
4099 | hsw_trans_edp_pipe_A_crc_wa(dev_priv, false); | |
8c740dce PZ |
4100 | |
4101 | hsw_enable_ips(crtc); | |
e5f75aca DL |
4102 | } |
4103 | ||
e129649b ID |
4104 | ret = 0; |
4105 | ||
4106 | out: | |
4107 | intel_display_power_put(dev_priv, power_domain); | |
4108 | ||
4109 | return ret; | |
926321d5 DV |
4110 | } |
4111 | ||
4112 | /* | |
4113 | * Parse pipe CRC command strings: | |
b94dec87 DL |
4114 | * command: wsp* object wsp+ name wsp+ source wsp* |
4115 | * object: 'pipe' | |
4116 | * name: (A | B | C) | |
926321d5 DV |
4117 | * source: (none | plane1 | plane2 | pf) |
4118 | * wsp: (#0x20 | #0x9 | #0xA)+ | |
4119 | * | |
4120 | * eg.: | |
b94dec87 DL |
4121 | * "pipe A plane1" -> Start CRC computations on plane1 of pipe A |
4122 | * "pipe A none" -> Stop CRC | |
926321d5 | 4123 | */ |
bd9db02f | 4124 | static int display_crc_ctl_tokenize(char *buf, char *words[], int max_words) |
926321d5 DV |
4125 | { |
4126 | int n_words = 0; | |
4127 | ||
4128 | while (*buf) { | |
4129 | char *end; | |
4130 | ||
4131 | /* skip leading white space */ | |
4132 | buf = skip_spaces(buf); | |
4133 | if (!*buf) | |
4134 | break; /* end of buffer */ | |
4135 | ||
4136 | /* find end of word */ | |
4137 | for (end = buf; *end && !isspace(*end); end++) | |
4138 | ; | |
4139 | ||
4140 | if (n_words == max_words) { | |
4141 | DRM_DEBUG_DRIVER("too many words, allowed <= %d\n", | |
4142 | max_words); | |
4143 | return -EINVAL; /* ran out of words[] before bytes */ | |
4144 | } | |
4145 | ||
4146 | if (*end) | |
4147 | *end++ = '\0'; | |
4148 | words[n_words++] = buf; | |
4149 | buf = end; | |
4150 | } | |
4151 | ||
4152 | return n_words; | |
4153 | } | |
4154 | ||
b94dec87 DL |
4155 | enum intel_pipe_crc_object { |
4156 | PIPE_CRC_OBJECT_PIPE, | |
4157 | }; | |
4158 | ||
e8dfcf78 | 4159 | static const char * const pipe_crc_objects[] = { |
b94dec87 DL |
4160 | "pipe", |
4161 | }; | |
4162 | ||
4163 | static int | |
bd9db02f | 4164 | display_crc_ctl_parse_object(const char *buf, enum intel_pipe_crc_object *o) |
b94dec87 DL |
4165 | { |
4166 | int i; | |
4167 | ||
4168 | for (i = 0; i < ARRAY_SIZE(pipe_crc_objects); i++) | |
4169 | if (!strcmp(buf, pipe_crc_objects[i])) { | |
bd9db02f | 4170 | *o = i; |
b94dec87 DL |
4171 | return 0; |
4172 | } | |
4173 | ||
4174 | return -EINVAL; | |
4175 | } | |
4176 | ||
bd9db02f | 4177 | static int display_crc_ctl_parse_pipe(const char *buf, enum pipe *pipe) |
926321d5 DV |
4178 | { |
4179 | const char name = buf[0]; | |
4180 | ||
4181 | if (name < 'A' || name >= pipe_name(I915_MAX_PIPES)) | |
4182 | return -EINVAL; | |
4183 | ||
4184 | *pipe = name - 'A'; | |
4185 | ||
4186 | return 0; | |
4187 | } | |
4188 | ||
4189 | static int | |
bd9db02f | 4190 | display_crc_ctl_parse_source(const char *buf, enum intel_pipe_crc_source *s) |
926321d5 DV |
4191 | { |
4192 | int i; | |
4193 | ||
4194 | for (i = 0; i < ARRAY_SIZE(pipe_crc_sources); i++) | |
4195 | if (!strcmp(buf, pipe_crc_sources[i])) { | |
bd9db02f | 4196 | *s = i; |
926321d5 DV |
4197 | return 0; |
4198 | } | |
4199 | ||
4200 | return -EINVAL; | |
4201 | } | |
4202 | ||
36cdd013 DW |
4203 | static int display_crc_ctl_parse(struct drm_i915_private *dev_priv, |
4204 | char *buf, size_t len) | |
926321d5 | 4205 | { |
b94dec87 | 4206 | #define N_WORDS 3 |
926321d5 | 4207 | int n_words; |
b94dec87 | 4208 | char *words[N_WORDS]; |
926321d5 | 4209 | enum pipe pipe; |
b94dec87 | 4210 | enum intel_pipe_crc_object object; |
926321d5 DV |
4211 | enum intel_pipe_crc_source source; |
4212 | ||
bd9db02f | 4213 | n_words = display_crc_ctl_tokenize(buf, words, N_WORDS); |
b94dec87 DL |
4214 | if (n_words != N_WORDS) { |
4215 | DRM_DEBUG_DRIVER("tokenize failed, a command is %d words\n", | |
4216 | N_WORDS); | |
4217 | return -EINVAL; | |
4218 | } | |
4219 | ||
bd9db02f | 4220 | if (display_crc_ctl_parse_object(words[0], &object) < 0) { |
b94dec87 | 4221 | DRM_DEBUG_DRIVER("unknown object %s\n", words[0]); |
926321d5 DV |
4222 | return -EINVAL; |
4223 | } | |
4224 | ||
bd9db02f | 4225 | if (display_crc_ctl_parse_pipe(words[1], &pipe) < 0) { |
b94dec87 | 4226 | DRM_DEBUG_DRIVER("unknown pipe %s\n", words[1]); |
926321d5 DV |
4227 | return -EINVAL; |
4228 | } | |
4229 | ||
bd9db02f | 4230 | if (display_crc_ctl_parse_source(words[2], &source) < 0) { |
b94dec87 | 4231 | DRM_DEBUG_DRIVER("unknown source %s\n", words[2]); |
926321d5 DV |
4232 | return -EINVAL; |
4233 | } | |
4234 | ||
36cdd013 | 4235 | return pipe_crc_set_source(dev_priv, pipe, source); |
926321d5 DV |
4236 | } |
4237 | ||
bd9db02f DL |
4238 | static ssize_t display_crc_ctl_write(struct file *file, const char __user *ubuf, |
4239 | size_t len, loff_t *offp) | |
926321d5 DV |
4240 | { |
4241 | struct seq_file *m = file->private_data; | |
36cdd013 | 4242 | struct drm_i915_private *dev_priv = m->private; |
926321d5 DV |
4243 | char *tmpbuf; |
4244 | int ret; | |
4245 | ||
4246 | if (len == 0) | |
4247 | return 0; | |
4248 | ||
4249 | if (len > PAGE_SIZE - 1) { | |
4250 | DRM_DEBUG_DRIVER("expected <%lu bytes into pipe crc control\n", | |
4251 | PAGE_SIZE); | |
4252 | return -E2BIG; | |
4253 | } | |
4254 | ||
4255 | tmpbuf = kmalloc(len + 1, GFP_KERNEL); | |
4256 | if (!tmpbuf) | |
4257 | return -ENOMEM; | |
4258 | ||
4259 | if (copy_from_user(tmpbuf, ubuf, len)) { | |
4260 | ret = -EFAULT; | |
4261 | goto out; | |
4262 | } | |
4263 | tmpbuf[len] = '\0'; | |
4264 | ||
36cdd013 | 4265 | ret = display_crc_ctl_parse(dev_priv, tmpbuf, len); |
926321d5 DV |
4266 | |
4267 | out: | |
4268 | kfree(tmpbuf); | |
4269 | if (ret < 0) | |
4270 | return ret; | |
4271 | ||
4272 | *offp += len; | |
4273 | return len; | |
4274 | } | |
4275 | ||
bd9db02f | 4276 | static const struct file_operations i915_display_crc_ctl_fops = { |
926321d5 | 4277 | .owner = THIS_MODULE, |
bd9db02f | 4278 | .open = display_crc_ctl_open, |
926321d5 DV |
4279 | .read = seq_read, |
4280 | .llseek = seq_lseek, | |
4281 | .release = single_release, | |
bd9db02f | 4282 | .write = display_crc_ctl_write |
926321d5 DV |
4283 | }; |
4284 | ||
eb3394fa | 4285 | static ssize_t i915_displayport_test_active_write(struct file *file, |
36cdd013 DW |
4286 | const char __user *ubuf, |
4287 | size_t len, loff_t *offp) | |
eb3394fa TP |
4288 | { |
4289 | char *input_buffer; | |
4290 | int status = 0; | |
eb3394fa TP |
4291 | struct drm_device *dev; |
4292 | struct drm_connector *connector; | |
4293 | struct list_head *connector_list; | |
4294 | struct intel_dp *intel_dp; | |
4295 | int val = 0; | |
4296 | ||
9aaffa34 | 4297 | dev = ((struct seq_file *)file->private_data)->private; |
eb3394fa | 4298 | |
eb3394fa TP |
4299 | connector_list = &dev->mode_config.connector_list; |
4300 | ||
4301 | if (len == 0) | |
4302 | return 0; | |
4303 | ||
4304 | input_buffer = kmalloc(len + 1, GFP_KERNEL); | |
4305 | if (!input_buffer) | |
4306 | return -ENOMEM; | |
4307 | ||
4308 | if (copy_from_user(input_buffer, ubuf, len)) { | |
4309 | status = -EFAULT; | |
4310 | goto out; | |
4311 | } | |
4312 | ||
4313 | input_buffer[len] = '\0'; | |
4314 | DRM_DEBUG_DRIVER("Copied %d bytes from user\n", (unsigned int)len); | |
4315 | ||
4316 | list_for_each_entry(connector, connector_list, head) { | |
eb3394fa TP |
4317 | if (connector->connector_type != |
4318 | DRM_MODE_CONNECTOR_DisplayPort) | |
4319 | continue; | |
4320 | ||
b8bb08ec | 4321 | if (connector->status == connector_status_connected && |
eb3394fa TP |
4322 | connector->encoder != NULL) { |
4323 | intel_dp = enc_to_intel_dp(connector->encoder); | |
4324 | status = kstrtoint(input_buffer, 10, &val); | |
4325 | if (status < 0) | |
4326 | goto out; | |
4327 | DRM_DEBUG_DRIVER("Got %d for test active\n", val); | |
4328 | /* To prevent erroneous activation of the compliance | |
4329 | * testing code, only accept an actual value of 1 here | |
4330 | */ | |
4331 | if (val == 1) | |
4332 | intel_dp->compliance_test_active = 1; | |
4333 | else | |
4334 | intel_dp->compliance_test_active = 0; | |
4335 | } | |
4336 | } | |
4337 | out: | |
4338 | kfree(input_buffer); | |
4339 | if (status < 0) | |
4340 | return status; | |
4341 | ||
4342 | *offp += len; | |
4343 | return len; | |
4344 | } | |
4345 | ||
4346 | static int i915_displayport_test_active_show(struct seq_file *m, void *data) | |
4347 | { | |
4348 | struct drm_device *dev = m->private; | |
4349 | struct drm_connector *connector; | |
4350 | struct list_head *connector_list = &dev->mode_config.connector_list; | |
4351 | struct intel_dp *intel_dp; | |
4352 | ||
eb3394fa | 4353 | list_for_each_entry(connector, connector_list, head) { |
eb3394fa TP |
4354 | if (connector->connector_type != |
4355 | DRM_MODE_CONNECTOR_DisplayPort) | |
4356 | continue; | |
4357 | ||
4358 | if (connector->status == connector_status_connected && | |
4359 | connector->encoder != NULL) { | |
4360 | intel_dp = enc_to_intel_dp(connector->encoder); | |
4361 | if (intel_dp->compliance_test_active) | |
4362 | seq_puts(m, "1"); | |
4363 | else | |
4364 | seq_puts(m, "0"); | |
4365 | } else | |
4366 | seq_puts(m, "0"); | |
4367 | } | |
4368 | ||
4369 | return 0; | |
4370 | } | |
4371 | ||
4372 | static int i915_displayport_test_active_open(struct inode *inode, | |
36cdd013 | 4373 | struct file *file) |
eb3394fa | 4374 | { |
36cdd013 | 4375 | struct drm_i915_private *dev_priv = inode->i_private; |
eb3394fa | 4376 | |
36cdd013 DW |
4377 | return single_open(file, i915_displayport_test_active_show, |
4378 | &dev_priv->drm); | |
eb3394fa TP |
4379 | } |
4380 | ||
4381 | static const struct file_operations i915_displayport_test_active_fops = { | |
4382 | .owner = THIS_MODULE, | |
4383 | .open = i915_displayport_test_active_open, | |
4384 | .read = seq_read, | |
4385 | .llseek = seq_lseek, | |
4386 | .release = single_release, | |
4387 | .write = i915_displayport_test_active_write | |
4388 | }; | |
4389 | ||
4390 | static int i915_displayport_test_data_show(struct seq_file *m, void *data) | |
4391 | { | |
4392 | struct drm_device *dev = m->private; | |
4393 | struct drm_connector *connector; | |
4394 | struct list_head *connector_list = &dev->mode_config.connector_list; | |
4395 | struct intel_dp *intel_dp; | |
4396 | ||
eb3394fa | 4397 | list_for_each_entry(connector, connector_list, head) { |
eb3394fa TP |
4398 | if (connector->connector_type != |
4399 | DRM_MODE_CONNECTOR_DisplayPort) | |
4400 | continue; | |
4401 | ||
4402 | if (connector->status == connector_status_connected && | |
4403 | connector->encoder != NULL) { | |
4404 | intel_dp = enc_to_intel_dp(connector->encoder); | |
4405 | seq_printf(m, "%lx", intel_dp->compliance_test_data); | |
4406 | } else | |
4407 | seq_puts(m, "0"); | |
4408 | } | |
4409 | ||
4410 | return 0; | |
4411 | } | |
4412 | static int i915_displayport_test_data_open(struct inode *inode, | |
36cdd013 | 4413 | struct file *file) |
eb3394fa | 4414 | { |
36cdd013 | 4415 | struct drm_i915_private *dev_priv = inode->i_private; |
eb3394fa | 4416 | |
36cdd013 DW |
4417 | return single_open(file, i915_displayport_test_data_show, |
4418 | &dev_priv->drm); | |
eb3394fa TP |
4419 | } |
4420 | ||
4421 | static const struct file_operations i915_displayport_test_data_fops = { | |
4422 | .owner = THIS_MODULE, | |
4423 | .open = i915_displayport_test_data_open, | |
4424 | .read = seq_read, | |
4425 | .llseek = seq_lseek, | |
4426 | .release = single_release | |
4427 | }; | |
4428 | ||
4429 | static int i915_displayport_test_type_show(struct seq_file *m, void *data) | |
4430 | { | |
4431 | struct drm_device *dev = m->private; | |
4432 | struct drm_connector *connector; | |
4433 | struct list_head *connector_list = &dev->mode_config.connector_list; | |
4434 | struct intel_dp *intel_dp; | |
4435 | ||
eb3394fa | 4436 | list_for_each_entry(connector, connector_list, head) { |
eb3394fa TP |
4437 | if (connector->connector_type != |
4438 | DRM_MODE_CONNECTOR_DisplayPort) | |
4439 | continue; | |
4440 | ||
4441 | if (connector->status == connector_status_connected && | |
4442 | connector->encoder != NULL) { | |
4443 | intel_dp = enc_to_intel_dp(connector->encoder); | |
4444 | seq_printf(m, "%02lx", intel_dp->compliance_test_type); | |
4445 | } else | |
4446 | seq_puts(m, "0"); | |
4447 | } | |
4448 | ||
4449 | return 0; | |
4450 | } | |
4451 | ||
4452 | static int i915_displayport_test_type_open(struct inode *inode, | |
4453 | struct file *file) | |
4454 | { | |
36cdd013 | 4455 | struct drm_i915_private *dev_priv = inode->i_private; |
eb3394fa | 4456 | |
36cdd013 DW |
4457 | return single_open(file, i915_displayport_test_type_show, |
4458 | &dev_priv->drm); | |
eb3394fa TP |
4459 | } |
4460 | ||
4461 | static const struct file_operations i915_displayport_test_type_fops = { | |
4462 | .owner = THIS_MODULE, | |
4463 | .open = i915_displayport_test_type_open, | |
4464 | .read = seq_read, | |
4465 | .llseek = seq_lseek, | |
4466 | .release = single_release | |
4467 | }; | |
4468 | ||
97e94b22 | 4469 | static void wm_latency_show(struct seq_file *m, const uint16_t wm[8]) |
369a1342 | 4470 | { |
36cdd013 DW |
4471 | struct drm_i915_private *dev_priv = m->private; |
4472 | struct drm_device *dev = &dev_priv->drm; | |
369a1342 | 4473 | int level; |
de38b95c VS |
4474 | int num_levels; |
4475 | ||
36cdd013 | 4476 | if (IS_CHERRYVIEW(dev_priv)) |
de38b95c | 4477 | num_levels = 3; |
36cdd013 | 4478 | else if (IS_VALLEYVIEW(dev_priv)) |
de38b95c VS |
4479 | num_levels = 1; |
4480 | else | |
4481 | num_levels = ilk_wm_max_level(dev) + 1; | |
369a1342 VS |
4482 | |
4483 | drm_modeset_lock_all(dev); | |
4484 | ||
4485 | for (level = 0; level < num_levels; level++) { | |
4486 | unsigned int latency = wm[level]; | |
4487 | ||
97e94b22 DL |
4488 | /* |
4489 | * - WM1+ latency values in 0.5us units | |
de38b95c | 4490 | * - latencies are in us on gen9/vlv/chv |
97e94b22 | 4491 | */ |
36cdd013 DW |
4492 | if (INTEL_GEN(dev_priv) >= 9 || IS_VALLEYVIEW(dev_priv) || |
4493 | IS_CHERRYVIEW(dev_priv)) | |
97e94b22 DL |
4494 | latency *= 10; |
4495 | else if (level > 0) | |
369a1342 VS |
4496 | latency *= 5; |
4497 | ||
4498 | seq_printf(m, "WM%d %u (%u.%u usec)\n", | |
97e94b22 | 4499 | level, wm[level], latency / 10, latency % 10); |
369a1342 VS |
4500 | } |
4501 | ||
4502 | drm_modeset_unlock_all(dev); | |
4503 | } | |
4504 | ||
4505 | static int pri_wm_latency_show(struct seq_file *m, void *data) | |
4506 | { | |
36cdd013 | 4507 | struct drm_i915_private *dev_priv = m->private; |
97e94b22 DL |
4508 | const uint16_t *latencies; |
4509 | ||
36cdd013 | 4510 | if (INTEL_GEN(dev_priv) >= 9) |
97e94b22 DL |
4511 | latencies = dev_priv->wm.skl_latency; |
4512 | else | |
36cdd013 | 4513 | latencies = dev_priv->wm.pri_latency; |
369a1342 | 4514 | |
97e94b22 | 4515 | wm_latency_show(m, latencies); |
369a1342 VS |
4516 | |
4517 | return 0; | |
4518 | } | |
4519 | ||
4520 | static int spr_wm_latency_show(struct seq_file *m, void *data) | |
4521 | { | |
36cdd013 | 4522 | struct drm_i915_private *dev_priv = m->private; |
97e94b22 DL |
4523 | const uint16_t *latencies; |
4524 | ||
36cdd013 | 4525 | if (INTEL_GEN(dev_priv) >= 9) |
97e94b22 DL |
4526 | latencies = dev_priv->wm.skl_latency; |
4527 | else | |
36cdd013 | 4528 | latencies = dev_priv->wm.spr_latency; |
369a1342 | 4529 | |
97e94b22 | 4530 | wm_latency_show(m, latencies); |
369a1342 VS |
4531 | |
4532 | return 0; | |
4533 | } | |
4534 | ||
4535 | static int cur_wm_latency_show(struct seq_file *m, void *data) | |
4536 | { | |
36cdd013 | 4537 | struct drm_i915_private *dev_priv = m->private; |
97e94b22 DL |
4538 | const uint16_t *latencies; |
4539 | ||
36cdd013 | 4540 | if (INTEL_GEN(dev_priv) >= 9) |
97e94b22 DL |
4541 | latencies = dev_priv->wm.skl_latency; |
4542 | else | |
36cdd013 | 4543 | latencies = dev_priv->wm.cur_latency; |
369a1342 | 4544 | |
97e94b22 | 4545 | wm_latency_show(m, latencies); |
369a1342 VS |
4546 | |
4547 | return 0; | |
4548 | } | |
4549 | ||
4550 | static int pri_wm_latency_open(struct inode *inode, struct file *file) | |
4551 | { | |
36cdd013 | 4552 | struct drm_i915_private *dev_priv = inode->i_private; |
369a1342 | 4553 | |
36cdd013 | 4554 | if (INTEL_GEN(dev_priv) < 5) |
369a1342 VS |
4555 | return -ENODEV; |
4556 | ||
36cdd013 | 4557 | return single_open(file, pri_wm_latency_show, dev_priv); |
369a1342 VS |
4558 | } |
4559 | ||
4560 | static int spr_wm_latency_open(struct inode *inode, struct file *file) | |
4561 | { | |
36cdd013 | 4562 | struct drm_i915_private *dev_priv = inode->i_private; |
369a1342 | 4563 | |
36cdd013 | 4564 | if (HAS_GMCH_DISPLAY(dev_priv)) |
369a1342 VS |
4565 | return -ENODEV; |
4566 | ||
36cdd013 | 4567 | return single_open(file, spr_wm_latency_show, dev_priv); |
369a1342 VS |
4568 | } |
4569 | ||
4570 | static int cur_wm_latency_open(struct inode *inode, struct file *file) | |
4571 | { | |
36cdd013 | 4572 | struct drm_i915_private *dev_priv = inode->i_private; |
369a1342 | 4573 | |
36cdd013 | 4574 | if (HAS_GMCH_DISPLAY(dev_priv)) |
369a1342 VS |
4575 | return -ENODEV; |
4576 | ||
36cdd013 | 4577 | return single_open(file, cur_wm_latency_show, dev_priv); |
369a1342 VS |
4578 | } |
4579 | ||
4580 | static ssize_t wm_latency_write(struct file *file, const char __user *ubuf, | |
97e94b22 | 4581 | size_t len, loff_t *offp, uint16_t wm[8]) |
369a1342 VS |
4582 | { |
4583 | struct seq_file *m = file->private_data; | |
36cdd013 DW |
4584 | struct drm_i915_private *dev_priv = m->private; |
4585 | struct drm_device *dev = &dev_priv->drm; | |
97e94b22 | 4586 | uint16_t new[8] = { 0 }; |
de38b95c | 4587 | int num_levels; |
369a1342 VS |
4588 | int level; |
4589 | int ret; | |
4590 | char tmp[32]; | |
4591 | ||
36cdd013 | 4592 | if (IS_CHERRYVIEW(dev_priv)) |
de38b95c | 4593 | num_levels = 3; |
36cdd013 | 4594 | else if (IS_VALLEYVIEW(dev_priv)) |
de38b95c VS |
4595 | num_levels = 1; |
4596 | else | |
4597 | num_levels = ilk_wm_max_level(dev) + 1; | |
4598 | ||
369a1342 VS |
4599 | if (len >= sizeof(tmp)) |
4600 | return -EINVAL; | |
4601 | ||
4602 | if (copy_from_user(tmp, ubuf, len)) | |
4603 | return -EFAULT; | |
4604 | ||
4605 | tmp[len] = '\0'; | |
4606 | ||
97e94b22 DL |
4607 | ret = sscanf(tmp, "%hu %hu %hu %hu %hu %hu %hu %hu", |
4608 | &new[0], &new[1], &new[2], &new[3], | |
4609 | &new[4], &new[5], &new[6], &new[7]); | |
369a1342 VS |
4610 | if (ret != num_levels) |
4611 | return -EINVAL; | |
4612 | ||
4613 | drm_modeset_lock_all(dev); | |
4614 | ||
4615 | for (level = 0; level < num_levels; level++) | |
4616 | wm[level] = new[level]; | |
4617 | ||
4618 | drm_modeset_unlock_all(dev); | |
4619 | ||
4620 | return len; | |
4621 | } | |
4622 | ||
4623 | ||
4624 | static ssize_t pri_wm_latency_write(struct file *file, const char __user *ubuf, | |
4625 | size_t len, loff_t *offp) | |
4626 | { | |
4627 | struct seq_file *m = file->private_data; | |
36cdd013 | 4628 | struct drm_i915_private *dev_priv = m->private; |
97e94b22 | 4629 | uint16_t *latencies; |
369a1342 | 4630 | |
36cdd013 | 4631 | if (INTEL_GEN(dev_priv) >= 9) |
97e94b22 DL |
4632 | latencies = dev_priv->wm.skl_latency; |
4633 | else | |
36cdd013 | 4634 | latencies = dev_priv->wm.pri_latency; |
97e94b22 DL |
4635 | |
4636 | return wm_latency_write(file, ubuf, len, offp, latencies); | |
369a1342 VS |
4637 | } |
4638 | ||
4639 | static ssize_t spr_wm_latency_write(struct file *file, const char __user *ubuf, | |
4640 | size_t len, loff_t *offp) | |
4641 | { | |
4642 | struct seq_file *m = file->private_data; | |
36cdd013 | 4643 | struct drm_i915_private *dev_priv = m->private; |
97e94b22 | 4644 | uint16_t *latencies; |
369a1342 | 4645 | |
36cdd013 | 4646 | if (INTEL_GEN(dev_priv) >= 9) |
97e94b22 DL |
4647 | latencies = dev_priv->wm.skl_latency; |
4648 | else | |
36cdd013 | 4649 | latencies = dev_priv->wm.spr_latency; |
97e94b22 DL |
4650 | |
4651 | return wm_latency_write(file, ubuf, len, offp, latencies); | |
369a1342 VS |
4652 | } |
4653 | ||
4654 | static ssize_t cur_wm_latency_write(struct file *file, const char __user *ubuf, | |
4655 | size_t len, loff_t *offp) | |
4656 | { | |
4657 | struct seq_file *m = file->private_data; | |
36cdd013 | 4658 | struct drm_i915_private *dev_priv = m->private; |
97e94b22 DL |
4659 | uint16_t *latencies; |
4660 | ||
36cdd013 | 4661 | if (INTEL_GEN(dev_priv) >= 9) |
97e94b22 DL |
4662 | latencies = dev_priv->wm.skl_latency; |
4663 | else | |
36cdd013 | 4664 | latencies = dev_priv->wm.cur_latency; |
369a1342 | 4665 | |
97e94b22 | 4666 | return wm_latency_write(file, ubuf, len, offp, latencies); |
369a1342 VS |
4667 | } |
4668 | ||
4669 | static const struct file_operations i915_pri_wm_latency_fops = { | |
4670 | .owner = THIS_MODULE, | |
4671 | .open = pri_wm_latency_open, | |
4672 | .read = seq_read, | |
4673 | .llseek = seq_lseek, | |
4674 | .release = single_release, | |
4675 | .write = pri_wm_latency_write | |
4676 | }; | |
4677 | ||
4678 | static const struct file_operations i915_spr_wm_latency_fops = { | |
4679 | .owner = THIS_MODULE, | |
4680 | .open = spr_wm_latency_open, | |
4681 | .read = seq_read, | |
4682 | .llseek = seq_lseek, | |
4683 | .release = single_release, | |
4684 | .write = spr_wm_latency_write | |
4685 | }; | |
4686 | ||
4687 | static const struct file_operations i915_cur_wm_latency_fops = { | |
4688 | .owner = THIS_MODULE, | |
4689 | .open = cur_wm_latency_open, | |
4690 | .read = seq_read, | |
4691 | .llseek = seq_lseek, | |
4692 | .release = single_release, | |
4693 | .write = cur_wm_latency_write | |
4694 | }; | |
4695 | ||
647416f9 KC |
4696 | static int |
4697 | i915_wedged_get(void *data, u64 *val) | |
f3cd474b | 4698 | { |
36cdd013 | 4699 | struct drm_i915_private *dev_priv = data; |
f3cd474b | 4700 | |
d98c52cf | 4701 | *val = i915_terminally_wedged(&dev_priv->gpu_error); |
f3cd474b | 4702 | |
647416f9 | 4703 | return 0; |
f3cd474b CW |
4704 | } |
4705 | ||
647416f9 KC |
4706 | static int |
4707 | i915_wedged_set(void *data, u64 val) | |
f3cd474b | 4708 | { |
36cdd013 | 4709 | struct drm_i915_private *dev_priv = data; |
d46c0517 | 4710 | |
b8d24a06 MK |
4711 | /* |
4712 | * There is no safeguard against this debugfs entry colliding | |
4713 | * with the hangcheck calling same i915_handle_error() in | |
4714 | * parallel, causing an explosion. For now we assume that the | |
4715 | * test harness is responsible enough not to inject gpu hangs | |
4716 | * while it is writing to 'i915_wedged' | |
4717 | */ | |
4718 | ||
d98c52cf | 4719 | if (i915_reset_in_progress(&dev_priv->gpu_error)) |
b8d24a06 MK |
4720 | return -EAGAIN; |
4721 | ||
d46c0517 | 4722 | intel_runtime_pm_get(dev_priv); |
f3cd474b | 4723 | |
c033666a | 4724 | i915_handle_error(dev_priv, val, |
58174462 | 4725 | "Manually setting wedged to %llu", val); |
d46c0517 ID |
4726 | |
4727 | intel_runtime_pm_put(dev_priv); | |
4728 | ||
647416f9 | 4729 | return 0; |
f3cd474b CW |
4730 | } |
4731 | ||
647416f9 KC |
4732 | DEFINE_SIMPLE_ATTRIBUTE(i915_wedged_fops, |
4733 | i915_wedged_get, i915_wedged_set, | |
3a3b4f98 | 4734 | "%llu\n"); |
f3cd474b | 4735 | |
094f9a54 CW |
4736 | static int |
4737 | i915_ring_missed_irq_get(void *data, u64 *val) | |
4738 | { | |
36cdd013 | 4739 | struct drm_i915_private *dev_priv = data; |
094f9a54 CW |
4740 | |
4741 | *val = dev_priv->gpu_error.missed_irq_rings; | |
4742 | return 0; | |
4743 | } | |
4744 | ||
4745 | static int | |
4746 | i915_ring_missed_irq_set(void *data, u64 val) | |
4747 | { | |
36cdd013 DW |
4748 | struct drm_i915_private *dev_priv = data; |
4749 | struct drm_device *dev = &dev_priv->drm; | |
094f9a54 CW |
4750 | int ret; |
4751 | ||
4752 | /* Lock against concurrent debugfs callers */ | |
4753 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
4754 | if (ret) | |
4755 | return ret; | |
4756 | dev_priv->gpu_error.missed_irq_rings = val; | |
4757 | mutex_unlock(&dev->struct_mutex); | |
4758 | ||
4759 | return 0; | |
4760 | } | |
4761 | ||
4762 | DEFINE_SIMPLE_ATTRIBUTE(i915_ring_missed_irq_fops, | |
4763 | i915_ring_missed_irq_get, i915_ring_missed_irq_set, | |
4764 | "0x%08llx\n"); | |
4765 | ||
4766 | static int | |
4767 | i915_ring_test_irq_get(void *data, u64 *val) | |
4768 | { | |
36cdd013 | 4769 | struct drm_i915_private *dev_priv = data; |
094f9a54 CW |
4770 | |
4771 | *val = dev_priv->gpu_error.test_irq_rings; | |
4772 | ||
4773 | return 0; | |
4774 | } | |
4775 | ||
4776 | static int | |
4777 | i915_ring_test_irq_set(void *data, u64 val) | |
4778 | { | |
36cdd013 | 4779 | struct drm_i915_private *dev_priv = data; |
094f9a54 | 4780 | |
3a122c27 | 4781 | val &= INTEL_INFO(dev_priv)->ring_mask; |
094f9a54 | 4782 | DRM_DEBUG_DRIVER("Masking interrupts on rings 0x%08llx\n", val); |
094f9a54 | 4783 | dev_priv->gpu_error.test_irq_rings = val; |
094f9a54 CW |
4784 | |
4785 | return 0; | |
4786 | } | |
4787 | ||
4788 | DEFINE_SIMPLE_ATTRIBUTE(i915_ring_test_irq_fops, | |
4789 | i915_ring_test_irq_get, i915_ring_test_irq_set, | |
4790 | "0x%08llx\n"); | |
4791 | ||
dd624afd CW |
4792 | #define DROP_UNBOUND 0x1 |
4793 | #define DROP_BOUND 0x2 | |
4794 | #define DROP_RETIRE 0x4 | |
4795 | #define DROP_ACTIVE 0x8 | |
4796 | #define DROP_ALL (DROP_UNBOUND | \ | |
4797 | DROP_BOUND | \ | |
4798 | DROP_RETIRE | \ | |
4799 | DROP_ACTIVE) | |
647416f9 KC |
4800 | static int |
4801 | i915_drop_caches_get(void *data, u64 *val) | |
dd624afd | 4802 | { |
647416f9 | 4803 | *val = DROP_ALL; |
dd624afd | 4804 | |
647416f9 | 4805 | return 0; |
dd624afd CW |
4806 | } |
4807 | ||
647416f9 KC |
4808 | static int |
4809 | i915_drop_caches_set(void *data, u64 val) | |
dd624afd | 4810 | { |
36cdd013 DW |
4811 | struct drm_i915_private *dev_priv = data; |
4812 | struct drm_device *dev = &dev_priv->drm; | |
647416f9 | 4813 | int ret; |
dd624afd | 4814 | |
2f9fe5ff | 4815 | DRM_DEBUG("Dropping caches: 0x%08llx\n", val); |
dd624afd CW |
4816 | |
4817 | /* No need to check and wait for gpu resets, only libdrm auto-restarts | |
4818 | * on ioctls on -EAGAIN. */ | |
4819 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
4820 | if (ret) | |
4821 | return ret; | |
4822 | ||
4823 | if (val & DROP_ACTIVE) { | |
22dd3bb9 CW |
4824 | ret = i915_gem_wait_for_idle(dev_priv, |
4825 | I915_WAIT_INTERRUPTIBLE | | |
4826 | I915_WAIT_LOCKED); | |
dd624afd CW |
4827 | if (ret) |
4828 | goto unlock; | |
4829 | } | |
4830 | ||
4831 | if (val & (DROP_RETIRE | DROP_ACTIVE)) | |
c033666a | 4832 | i915_gem_retire_requests(dev_priv); |
dd624afd | 4833 | |
21ab4e74 CW |
4834 | if (val & DROP_BOUND) |
4835 | i915_gem_shrink(dev_priv, LONG_MAX, I915_SHRINK_BOUND); | |
4ad72b7f | 4836 | |
21ab4e74 CW |
4837 | if (val & DROP_UNBOUND) |
4838 | i915_gem_shrink(dev_priv, LONG_MAX, I915_SHRINK_UNBOUND); | |
dd624afd CW |
4839 | |
4840 | unlock: | |
4841 | mutex_unlock(&dev->struct_mutex); | |
4842 | ||
647416f9 | 4843 | return ret; |
dd624afd CW |
4844 | } |
4845 | ||
647416f9 KC |
4846 | DEFINE_SIMPLE_ATTRIBUTE(i915_drop_caches_fops, |
4847 | i915_drop_caches_get, i915_drop_caches_set, | |
4848 | "0x%08llx\n"); | |
dd624afd | 4849 | |
647416f9 KC |
4850 | static int |
4851 | i915_max_freq_get(void *data, u64 *val) | |
358733e9 | 4852 | { |
36cdd013 | 4853 | struct drm_i915_private *dev_priv = data; |
004777cb | 4854 | |
36cdd013 | 4855 | if (INTEL_GEN(dev_priv) < 6) |
004777cb DV |
4856 | return -ENODEV; |
4857 | ||
7c59a9c1 | 4858 | *val = intel_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit); |
647416f9 | 4859 | return 0; |
358733e9 JB |
4860 | } |
4861 | ||
647416f9 KC |
4862 | static int |
4863 | i915_max_freq_set(void *data, u64 val) | |
358733e9 | 4864 | { |
36cdd013 | 4865 | struct drm_i915_private *dev_priv = data; |
bc4d91f6 | 4866 | u32 hw_max, hw_min; |
647416f9 | 4867 | int ret; |
004777cb | 4868 | |
36cdd013 | 4869 | if (INTEL_GEN(dev_priv) < 6) |
004777cb | 4870 | return -ENODEV; |
358733e9 | 4871 | |
647416f9 | 4872 | DRM_DEBUG_DRIVER("Manually setting max freq to %llu\n", val); |
358733e9 | 4873 | |
4fc688ce | 4874 | ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock); |
004777cb DV |
4875 | if (ret) |
4876 | return ret; | |
4877 | ||
358733e9 JB |
4878 | /* |
4879 | * Turbo will still be enabled, but won't go above the set value. | |
4880 | */ | |
bc4d91f6 | 4881 | val = intel_freq_opcode(dev_priv, val); |
dd0a1aa1 | 4882 | |
bc4d91f6 AG |
4883 | hw_max = dev_priv->rps.max_freq; |
4884 | hw_min = dev_priv->rps.min_freq; | |
dd0a1aa1 | 4885 | |
b39fb297 | 4886 | if (val < hw_min || val > hw_max || val < dev_priv->rps.min_freq_softlimit) { |
dd0a1aa1 JM |
4887 | mutex_unlock(&dev_priv->rps.hw_lock); |
4888 | return -EINVAL; | |
0a073b84 JB |
4889 | } |
4890 | ||
b39fb297 | 4891 | dev_priv->rps.max_freq_softlimit = val; |
dd0a1aa1 | 4892 | |
dc97997a | 4893 | intel_set_rps(dev_priv, val); |
dd0a1aa1 | 4894 | |
4fc688ce | 4895 | mutex_unlock(&dev_priv->rps.hw_lock); |
358733e9 | 4896 | |
647416f9 | 4897 | return 0; |
358733e9 JB |
4898 | } |
4899 | ||
647416f9 KC |
4900 | DEFINE_SIMPLE_ATTRIBUTE(i915_max_freq_fops, |
4901 | i915_max_freq_get, i915_max_freq_set, | |
3a3b4f98 | 4902 | "%llu\n"); |
358733e9 | 4903 | |
647416f9 KC |
4904 | static int |
4905 | i915_min_freq_get(void *data, u64 *val) | |
1523c310 | 4906 | { |
36cdd013 | 4907 | struct drm_i915_private *dev_priv = data; |
004777cb | 4908 | |
62e1baa1 | 4909 | if (INTEL_GEN(dev_priv) < 6) |
004777cb DV |
4910 | return -ENODEV; |
4911 | ||
7c59a9c1 | 4912 | *val = intel_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit); |
647416f9 | 4913 | return 0; |
1523c310 JB |
4914 | } |
4915 | ||
647416f9 KC |
4916 | static int |
4917 | i915_min_freq_set(void *data, u64 val) | |
1523c310 | 4918 | { |
36cdd013 | 4919 | struct drm_i915_private *dev_priv = data; |
bc4d91f6 | 4920 | u32 hw_max, hw_min; |
647416f9 | 4921 | int ret; |
004777cb | 4922 | |
62e1baa1 | 4923 | if (INTEL_GEN(dev_priv) < 6) |
004777cb | 4924 | return -ENODEV; |
1523c310 | 4925 | |
647416f9 | 4926 | DRM_DEBUG_DRIVER("Manually setting min freq to %llu\n", val); |
1523c310 | 4927 | |
4fc688ce | 4928 | ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock); |
004777cb DV |
4929 | if (ret) |
4930 | return ret; | |
4931 | ||
1523c310 JB |
4932 | /* |
4933 | * Turbo will still be enabled, but won't go below the set value. | |
4934 | */ | |
bc4d91f6 | 4935 | val = intel_freq_opcode(dev_priv, val); |
dd0a1aa1 | 4936 | |
bc4d91f6 AG |
4937 | hw_max = dev_priv->rps.max_freq; |
4938 | hw_min = dev_priv->rps.min_freq; | |
dd0a1aa1 | 4939 | |
36cdd013 DW |
4940 | if (val < hw_min || |
4941 | val > hw_max || val > dev_priv->rps.max_freq_softlimit) { | |
dd0a1aa1 JM |
4942 | mutex_unlock(&dev_priv->rps.hw_lock); |
4943 | return -EINVAL; | |
0a073b84 | 4944 | } |
dd0a1aa1 | 4945 | |
b39fb297 | 4946 | dev_priv->rps.min_freq_softlimit = val; |
dd0a1aa1 | 4947 | |
dc97997a | 4948 | intel_set_rps(dev_priv, val); |
dd0a1aa1 | 4949 | |
4fc688ce | 4950 | mutex_unlock(&dev_priv->rps.hw_lock); |
1523c310 | 4951 | |
647416f9 | 4952 | return 0; |
1523c310 JB |
4953 | } |
4954 | ||
647416f9 KC |
4955 | DEFINE_SIMPLE_ATTRIBUTE(i915_min_freq_fops, |
4956 | i915_min_freq_get, i915_min_freq_set, | |
3a3b4f98 | 4957 | "%llu\n"); |
1523c310 | 4958 | |
647416f9 KC |
4959 | static int |
4960 | i915_cache_sharing_get(void *data, u64 *val) | |
07b7ddd9 | 4961 | { |
36cdd013 DW |
4962 | struct drm_i915_private *dev_priv = data; |
4963 | struct drm_device *dev = &dev_priv->drm; | |
07b7ddd9 | 4964 | u32 snpcr; |
647416f9 | 4965 | int ret; |
07b7ddd9 | 4966 | |
36cdd013 | 4967 | if (!(IS_GEN6(dev_priv) || IS_GEN7(dev_priv))) |
004777cb DV |
4968 | return -ENODEV; |
4969 | ||
22bcfc6a DV |
4970 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
4971 | if (ret) | |
4972 | return ret; | |
c8c8fb33 | 4973 | intel_runtime_pm_get(dev_priv); |
22bcfc6a | 4974 | |
07b7ddd9 | 4975 | snpcr = I915_READ(GEN6_MBCUNIT_SNPCR); |
c8c8fb33 PZ |
4976 | |
4977 | intel_runtime_pm_put(dev_priv); | |
36cdd013 | 4978 | mutex_unlock(&dev->struct_mutex); |
07b7ddd9 | 4979 | |
647416f9 | 4980 | *val = (snpcr & GEN6_MBC_SNPCR_MASK) >> GEN6_MBC_SNPCR_SHIFT; |
07b7ddd9 | 4981 | |
647416f9 | 4982 | return 0; |
07b7ddd9 JB |
4983 | } |
4984 | ||
647416f9 KC |
4985 | static int |
4986 | i915_cache_sharing_set(void *data, u64 val) | |
07b7ddd9 | 4987 | { |
36cdd013 | 4988 | struct drm_i915_private *dev_priv = data; |
07b7ddd9 | 4989 | u32 snpcr; |
07b7ddd9 | 4990 | |
36cdd013 | 4991 | if (!(IS_GEN6(dev_priv) || IS_GEN7(dev_priv))) |
004777cb DV |
4992 | return -ENODEV; |
4993 | ||
647416f9 | 4994 | if (val > 3) |
07b7ddd9 JB |
4995 | return -EINVAL; |
4996 | ||
c8c8fb33 | 4997 | intel_runtime_pm_get(dev_priv); |
647416f9 | 4998 | DRM_DEBUG_DRIVER("Manually setting uncore sharing to %llu\n", val); |
07b7ddd9 JB |
4999 | |
5000 | /* Update the cache sharing policy here as well */ | |
5001 | snpcr = I915_READ(GEN6_MBCUNIT_SNPCR); | |
5002 | snpcr &= ~GEN6_MBC_SNPCR_MASK; | |
5003 | snpcr |= (val << GEN6_MBC_SNPCR_SHIFT); | |
5004 | I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr); | |
5005 | ||
c8c8fb33 | 5006 | intel_runtime_pm_put(dev_priv); |
647416f9 | 5007 | return 0; |
07b7ddd9 JB |
5008 | } |
5009 | ||
647416f9 KC |
5010 | DEFINE_SIMPLE_ATTRIBUTE(i915_cache_sharing_fops, |
5011 | i915_cache_sharing_get, i915_cache_sharing_set, | |
5012 | "%llu\n"); | |
07b7ddd9 | 5013 | |
36cdd013 | 5014 | static void cherryview_sseu_device_status(struct drm_i915_private *dev_priv, |
915490d5 | 5015 | struct sseu_dev_info *sseu) |
5d39525a | 5016 | { |
0a0b457f | 5017 | int ss_max = 2; |
5d39525a JM |
5018 | int ss; |
5019 | u32 sig1[ss_max], sig2[ss_max]; | |
5020 | ||
5021 | sig1[0] = I915_READ(CHV_POWER_SS0_SIG1); | |
5022 | sig1[1] = I915_READ(CHV_POWER_SS1_SIG1); | |
5023 | sig2[0] = I915_READ(CHV_POWER_SS0_SIG2); | |
5024 | sig2[1] = I915_READ(CHV_POWER_SS1_SIG2); | |
5025 | ||
5026 | for (ss = 0; ss < ss_max; ss++) { | |
5027 | unsigned int eu_cnt; | |
5028 | ||
5029 | if (sig1[ss] & CHV_SS_PG_ENABLE) | |
5030 | /* skip disabled subslice */ | |
5031 | continue; | |
5032 | ||
f08a0c92 | 5033 | sseu->slice_mask = BIT(0); |
57ec171e | 5034 | sseu->subslice_mask |= BIT(ss); |
5d39525a JM |
5035 | eu_cnt = ((sig1[ss] & CHV_EU08_PG_ENABLE) ? 0 : 2) + |
5036 | ((sig1[ss] & CHV_EU19_PG_ENABLE) ? 0 : 2) + | |
5037 | ((sig1[ss] & CHV_EU210_PG_ENABLE) ? 0 : 2) + | |
5038 | ((sig2[ss] & CHV_EU311_PG_ENABLE) ? 0 : 2); | |
915490d5 ID |
5039 | sseu->eu_total += eu_cnt; |
5040 | sseu->eu_per_subslice = max_t(unsigned int, | |
5041 | sseu->eu_per_subslice, eu_cnt); | |
5d39525a | 5042 | } |
5d39525a JM |
5043 | } |
5044 | ||
36cdd013 | 5045 | static void gen9_sseu_device_status(struct drm_i915_private *dev_priv, |
915490d5 | 5046 | struct sseu_dev_info *sseu) |
5d39525a | 5047 | { |
1c046bc1 | 5048 | int s_max = 3, ss_max = 4; |
5d39525a JM |
5049 | int s, ss; |
5050 | u32 s_reg[s_max], eu_reg[2*s_max], eu_mask[2]; | |
5051 | ||
1c046bc1 | 5052 | /* BXT has a single slice and at most 3 subslices. */ |
36cdd013 | 5053 | if (IS_BROXTON(dev_priv)) { |
1c046bc1 JM |
5054 | s_max = 1; |
5055 | ss_max = 3; | |
5056 | } | |
5057 | ||
5058 | for (s = 0; s < s_max; s++) { | |
5059 | s_reg[s] = I915_READ(GEN9_SLICE_PGCTL_ACK(s)); | |
5060 | eu_reg[2*s] = I915_READ(GEN9_SS01_EU_PGCTL_ACK(s)); | |
5061 | eu_reg[2*s + 1] = I915_READ(GEN9_SS23_EU_PGCTL_ACK(s)); | |
5062 | } | |
5063 | ||
5d39525a JM |
5064 | eu_mask[0] = GEN9_PGCTL_SSA_EU08_ACK | |
5065 | GEN9_PGCTL_SSA_EU19_ACK | | |
5066 | GEN9_PGCTL_SSA_EU210_ACK | | |
5067 | GEN9_PGCTL_SSA_EU311_ACK; | |
5068 | eu_mask[1] = GEN9_PGCTL_SSB_EU08_ACK | | |
5069 | GEN9_PGCTL_SSB_EU19_ACK | | |
5070 | GEN9_PGCTL_SSB_EU210_ACK | | |
5071 | GEN9_PGCTL_SSB_EU311_ACK; | |
5072 | ||
5073 | for (s = 0; s < s_max; s++) { | |
5074 | if ((s_reg[s] & GEN9_PGCTL_SLICE_ACK) == 0) | |
5075 | /* skip disabled slice */ | |
5076 | continue; | |
5077 | ||
f08a0c92 | 5078 | sseu->slice_mask |= BIT(s); |
1c046bc1 | 5079 | |
36cdd013 | 5080 | if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) |
57ec171e ID |
5081 | sseu->subslice_mask = |
5082 | INTEL_INFO(dev_priv)->sseu.subslice_mask; | |
1c046bc1 | 5083 | |
5d39525a JM |
5084 | for (ss = 0; ss < ss_max; ss++) { |
5085 | unsigned int eu_cnt; | |
5086 | ||
57ec171e ID |
5087 | if (IS_BROXTON(dev_priv)) { |
5088 | if (!(s_reg[s] & (GEN9_PGCTL_SS_ACK(ss)))) | |
5089 | /* skip disabled subslice */ | |
5090 | continue; | |
1c046bc1 | 5091 | |
57ec171e ID |
5092 | sseu->subslice_mask |= BIT(ss); |
5093 | } | |
1c046bc1 | 5094 | |
5d39525a JM |
5095 | eu_cnt = 2 * hweight32(eu_reg[2*s + ss/2] & |
5096 | eu_mask[ss%2]); | |
915490d5 ID |
5097 | sseu->eu_total += eu_cnt; |
5098 | sseu->eu_per_subslice = max_t(unsigned int, | |
5099 | sseu->eu_per_subslice, | |
5100 | eu_cnt); | |
5d39525a JM |
5101 | } |
5102 | } | |
5103 | } | |
5104 | ||
36cdd013 | 5105 | static void broadwell_sseu_device_status(struct drm_i915_private *dev_priv, |
915490d5 | 5106 | struct sseu_dev_info *sseu) |
91bedd34 | 5107 | { |
91bedd34 | 5108 | u32 slice_info = I915_READ(GEN8_GT_SLICE_INFO); |
36cdd013 | 5109 | int s; |
91bedd34 | 5110 | |
f08a0c92 | 5111 | sseu->slice_mask = slice_info & GEN8_LSLICESTAT_MASK; |
91bedd34 | 5112 | |
f08a0c92 | 5113 | if (sseu->slice_mask) { |
57ec171e | 5114 | sseu->subslice_mask = INTEL_INFO(dev_priv)->sseu.subslice_mask; |
43b67998 ID |
5115 | sseu->eu_per_subslice = |
5116 | INTEL_INFO(dev_priv)->sseu.eu_per_subslice; | |
57ec171e ID |
5117 | sseu->eu_total = sseu->eu_per_subslice * |
5118 | sseu_subslice_total(sseu); | |
91bedd34 ŁD |
5119 | |
5120 | /* subtract fused off EU(s) from enabled slice(s) */ | |
795b38b3 | 5121 | for (s = 0; s < fls(sseu->slice_mask); s++) { |
43b67998 ID |
5122 | u8 subslice_7eu = |
5123 | INTEL_INFO(dev_priv)->sseu.subslice_7eu[s]; | |
91bedd34 | 5124 | |
915490d5 | 5125 | sseu->eu_total -= hweight8(subslice_7eu); |
91bedd34 ŁD |
5126 | } |
5127 | } | |
5128 | } | |
5129 | ||
615d8908 ID |
5130 | static void i915_print_sseu_info(struct seq_file *m, bool is_available_info, |
5131 | const struct sseu_dev_info *sseu) | |
5132 | { | |
5133 | struct drm_i915_private *dev_priv = node_to_i915(m->private); | |
5134 | const char *type = is_available_info ? "Available" : "Enabled"; | |
5135 | ||
c67ba538 ID |
5136 | seq_printf(m, " %s Slice Mask: %04x\n", type, |
5137 | sseu->slice_mask); | |
615d8908 | 5138 | seq_printf(m, " %s Slice Total: %u\n", type, |
f08a0c92 | 5139 | hweight8(sseu->slice_mask)); |
615d8908 | 5140 | seq_printf(m, " %s Subslice Total: %u\n", type, |
57ec171e | 5141 | sseu_subslice_total(sseu)); |
c67ba538 ID |
5142 | seq_printf(m, " %s Subslice Mask: %04x\n", type, |
5143 | sseu->subslice_mask); | |
615d8908 | 5144 | seq_printf(m, " %s Subslice Per Slice: %u\n", type, |
57ec171e | 5145 | hweight8(sseu->subslice_mask)); |
615d8908 ID |
5146 | seq_printf(m, " %s EU Total: %u\n", type, |
5147 | sseu->eu_total); | |
5148 | seq_printf(m, " %s EU Per Subslice: %u\n", type, | |
5149 | sseu->eu_per_subslice); | |
5150 | ||
5151 | if (!is_available_info) | |
5152 | return; | |
5153 | ||
5154 | seq_printf(m, " Has Pooled EU: %s\n", yesno(HAS_POOLED_EU(dev_priv))); | |
5155 | if (HAS_POOLED_EU(dev_priv)) | |
5156 | seq_printf(m, " Min EU in pool: %u\n", sseu->min_eu_in_pool); | |
5157 | ||
5158 | seq_printf(m, " Has Slice Power Gating: %s\n", | |
5159 | yesno(sseu->has_slice_pg)); | |
5160 | seq_printf(m, " Has Subslice Power Gating: %s\n", | |
5161 | yesno(sseu->has_subslice_pg)); | |
5162 | seq_printf(m, " Has EU Power Gating: %s\n", | |
5163 | yesno(sseu->has_eu_pg)); | |
5164 | } | |
5165 | ||
3873218f JM |
5166 | static int i915_sseu_status(struct seq_file *m, void *unused) |
5167 | { | |
36cdd013 | 5168 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
915490d5 | 5169 | struct sseu_dev_info sseu; |
3873218f | 5170 | |
36cdd013 | 5171 | if (INTEL_GEN(dev_priv) < 8) |
3873218f JM |
5172 | return -ENODEV; |
5173 | ||
5174 | seq_puts(m, "SSEU Device Info\n"); | |
615d8908 | 5175 | i915_print_sseu_info(m, true, &INTEL_INFO(dev_priv)->sseu); |
3873218f | 5176 | |
7f992aba | 5177 | seq_puts(m, "SSEU Device Status\n"); |
915490d5 | 5178 | memset(&sseu, 0, sizeof(sseu)); |
238010ed DW |
5179 | |
5180 | intel_runtime_pm_get(dev_priv); | |
5181 | ||
36cdd013 | 5182 | if (IS_CHERRYVIEW(dev_priv)) { |
915490d5 | 5183 | cherryview_sseu_device_status(dev_priv, &sseu); |
36cdd013 | 5184 | } else if (IS_BROADWELL(dev_priv)) { |
915490d5 | 5185 | broadwell_sseu_device_status(dev_priv, &sseu); |
36cdd013 | 5186 | } else if (INTEL_GEN(dev_priv) >= 9) { |
915490d5 | 5187 | gen9_sseu_device_status(dev_priv, &sseu); |
7f992aba | 5188 | } |
238010ed DW |
5189 | |
5190 | intel_runtime_pm_put(dev_priv); | |
5191 | ||
615d8908 | 5192 | i915_print_sseu_info(m, false, &sseu); |
7f992aba | 5193 | |
3873218f JM |
5194 | return 0; |
5195 | } | |
5196 | ||
6d794d42 BW |
5197 | static int i915_forcewake_open(struct inode *inode, struct file *file) |
5198 | { | |
36cdd013 | 5199 | struct drm_i915_private *dev_priv = inode->i_private; |
6d794d42 | 5200 | |
36cdd013 | 5201 | if (INTEL_GEN(dev_priv) < 6) |
6d794d42 BW |
5202 | return 0; |
5203 | ||
6daccb0b | 5204 | intel_runtime_pm_get(dev_priv); |
59bad947 | 5205 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); |
6d794d42 BW |
5206 | |
5207 | return 0; | |
5208 | } | |
5209 | ||
c43b5634 | 5210 | static int i915_forcewake_release(struct inode *inode, struct file *file) |
6d794d42 | 5211 | { |
36cdd013 | 5212 | struct drm_i915_private *dev_priv = inode->i_private; |
6d794d42 | 5213 | |
36cdd013 | 5214 | if (INTEL_GEN(dev_priv) < 6) |
6d794d42 BW |
5215 | return 0; |
5216 | ||
59bad947 | 5217 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); |
6daccb0b | 5218 | intel_runtime_pm_put(dev_priv); |
6d794d42 BW |
5219 | |
5220 | return 0; | |
5221 | } | |
5222 | ||
5223 | static const struct file_operations i915_forcewake_fops = { | |
5224 | .owner = THIS_MODULE, | |
5225 | .open = i915_forcewake_open, | |
5226 | .release = i915_forcewake_release, | |
5227 | }; | |
5228 | ||
5229 | static int i915_forcewake_create(struct dentry *root, struct drm_minor *minor) | |
5230 | { | |
6d794d42 BW |
5231 | struct dentry *ent; |
5232 | ||
5233 | ent = debugfs_create_file("i915_forcewake_user", | |
8eb57294 | 5234 | S_IRUSR, |
36cdd013 | 5235 | root, to_i915(minor->dev), |
6d794d42 | 5236 | &i915_forcewake_fops); |
f3c5fe97 WY |
5237 | if (!ent) |
5238 | return -ENOMEM; | |
6d794d42 | 5239 | |
8eb57294 | 5240 | return drm_add_fake_info_node(minor, ent, &i915_forcewake_fops); |
6d794d42 BW |
5241 | } |
5242 | ||
6a9c308d DV |
5243 | static int i915_debugfs_create(struct dentry *root, |
5244 | struct drm_minor *minor, | |
5245 | const char *name, | |
5246 | const struct file_operations *fops) | |
07b7ddd9 | 5247 | { |
07b7ddd9 JB |
5248 | struct dentry *ent; |
5249 | ||
6a9c308d | 5250 | ent = debugfs_create_file(name, |
07b7ddd9 | 5251 | S_IRUGO | S_IWUSR, |
36cdd013 | 5252 | root, to_i915(minor->dev), |
6a9c308d | 5253 | fops); |
f3c5fe97 WY |
5254 | if (!ent) |
5255 | return -ENOMEM; | |
07b7ddd9 | 5256 | |
6a9c308d | 5257 | return drm_add_fake_info_node(minor, ent, fops); |
07b7ddd9 JB |
5258 | } |
5259 | ||
06c5bf8c | 5260 | static const struct drm_info_list i915_debugfs_list[] = { |
311bd68e | 5261 | {"i915_capabilities", i915_capabilities, 0}, |
73aa808f | 5262 | {"i915_gem_objects", i915_gem_object_info, 0}, |
08c18323 | 5263 | {"i915_gem_gtt", i915_gem_gtt_info, 0}, |
6da84829 | 5264 | {"i915_gem_pin_display", i915_gem_gtt_info, 0, (void *)1}, |
6d2b8885 | 5265 | {"i915_gem_stolen", i915_gem_stolen_list_info }, |
4e5359cd | 5266 | {"i915_gem_pageflip", i915_gem_pageflip_info, 0}, |
2017263e BG |
5267 | {"i915_gem_request", i915_gem_request_info, 0}, |
5268 | {"i915_gem_seqno", i915_gem_seqno_info, 0}, | |
a6172a80 | 5269 | {"i915_gem_fence_regs", i915_gem_fence_regs_info, 0}, |
2017263e | 5270 | {"i915_gem_interrupt", i915_interrupt_info, 0}, |
1ec14ad3 CW |
5271 | {"i915_gem_hws", i915_hws_info, 0, (void *)RCS}, |
5272 | {"i915_gem_hws_blt", i915_hws_info, 0, (void *)BCS}, | |
5273 | {"i915_gem_hws_bsd", i915_hws_info, 0, (void *)VCS}, | |
9010ebfd | 5274 | {"i915_gem_hws_vebox", i915_hws_info, 0, (void *)VECS}, |
493018dc | 5275 | {"i915_gem_batch_pool", i915_gem_batch_pool_info, 0}, |
8b417c26 | 5276 | {"i915_guc_info", i915_guc_info, 0}, |
fdf5d357 | 5277 | {"i915_guc_load_status", i915_guc_load_status_info, 0}, |
4c7e77fc | 5278 | {"i915_guc_log_dump", i915_guc_log_dump, 0}, |
adb4bd12 | 5279 | {"i915_frequency_info", i915_frequency_info, 0}, |
f654449a | 5280 | {"i915_hangcheck_info", i915_hangcheck_info, 0}, |
f97108d1 | 5281 | {"i915_drpc_info", i915_drpc_info, 0}, |
7648fa99 | 5282 | {"i915_emon_status", i915_emon_status, 0}, |
23b2f8bb | 5283 | {"i915_ring_freq_table", i915_ring_freq_table, 0}, |
9a851789 | 5284 | {"i915_frontbuffer_tracking", i915_frontbuffer_tracking, 0}, |
b5e50c3f | 5285 | {"i915_fbc_status", i915_fbc_status, 0}, |
92d44621 | 5286 | {"i915_ips_status", i915_ips_status, 0}, |
4a9bef37 | 5287 | {"i915_sr_status", i915_sr_status, 0}, |
44834a67 | 5288 | {"i915_opregion", i915_opregion, 0}, |
ada8f955 | 5289 | {"i915_vbt", i915_vbt, 0}, |
37811fcc | 5290 | {"i915_gem_framebuffer", i915_gem_framebuffer_info, 0}, |
e76d3630 | 5291 | {"i915_context_status", i915_context_status, 0}, |
c0ab1ae9 | 5292 | {"i915_dump_lrc", i915_dump_lrc, 0}, |
4ba70e44 | 5293 | {"i915_execlists", i915_execlists, 0}, |
f65367b5 | 5294 | {"i915_forcewake_domains", i915_forcewake_domains, 0}, |
ea16a3cd | 5295 | {"i915_swizzle_info", i915_swizzle_info, 0}, |
3cf17fc5 | 5296 | {"i915_ppgtt_info", i915_ppgtt_info, 0}, |
63573eb7 | 5297 | {"i915_llc", i915_llc, 0}, |
e91fd8c6 | 5298 | {"i915_edp_psr_status", i915_edp_psr_status, 0}, |
d2e216d0 | 5299 | {"i915_sink_crc_eDP1", i915_sink_crc, 0}, |
ec013e7f | 5300 | {"i915_energy_uJ", i915_energy_uJ, 0}, |
6455c870 | 5301 | {"i915_runtime_pm_status", i915_runtime_pm_status, 0}, |
1da51581 | 5302 | {"i915_power_domain_info", i915_power_domain_info, 0}, |
b7cec66d | 5303 | {"i915_dmc_info", i915_dmc_info, 0}, |
53f5e3ca | 5304 | {"i915_display_info", i915_display_info, 0}, |
e04934cf | 5305 | {"i915_semaphore_status", i915_semaphore_status, 0}, |
728e29d7 | 5306 | {"i915_shared_dplls_info", i915_shared_dplls_info, 0}, |
11bed958 | 5307 | {"i915_dp_mst_info", i915_dp_mst_info, 0}, |
1ed1ef9d | 5308 | {"i915_wa_registers", i915_wa_registers, 0}, |
c5511e44 | 5309 | {"i915_ddb_info", i915_ddb_info, 0}, |
3873218f | 5310 | {"i915_sseu_status", i915_sseu_status, 0}, |
a54746e3 | 5311 | {"i915_drrs_status", i915_drrs_status, 0}, |
1854d5ca | 5312 | {"i915_rps_boost_info", i915_rps_boost_info, 0}, |
2017263e | 5313 | }; |
27c202ad | 5314 | #define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list) |
2017263e | 5315 | |
06c5bf8c | 5316 | static const struct i915_debugfs_files { |
34b9674c DV |
5317 | const char *name; |
5318 | const struct file_operations *fops; | |
5319 | } i915_debugfs_files[] = { | |
5320 | {"i915_wedged", &i915_wedged_fops}, | |
5321 | {"i915_max_freq", &i915_max_freq_fops}, | |
5322 | {"i915_min_freq", &i915_min_freq_fops}, | |
5323 | {"i915_cache_sharing", &i915_cache_sharing_fops}, | |
094f9a54 CW |
5324 | {"i915_ring_missed_irq", &i915_ring_missed_irq_fops}, |
5325 | {"i915_ring_test_irq", &i915_ring_test_irq_fops}, | |
34b9674c DV |
5326 | {"i915_gem_drop_caches", &i915_drop_caches_fops}, |
5327 | {"i915_error_state", &i915_error_state_fops}, | |
5328 | {"i915_next_seqno", &i915_next_seqno_fops}, | |
bd9db02f | 5329 | {"i915_display_crc_ctl", &i915_display_crc_ctl_fops}, |
369a1342 VS |
5330 | {"i915_pri_wm_latency", &i915_pri_wm_latency_fops}, |
5331 | {"i915_spr_wm_latency", &i915_spr_wm_latency_fops}, | |
5332 | {"i915_cur_wm_latency", &i915_cur_wm_latency_fops}, | |
da46f936 | 5333 | {"i915_fbc_false_color", &i915_fbc_fc_fops}, |
eb3394fa TP |
5334 | {"i915_dp_test_data", &i915_displayport_test_data_fops}, |
5335 | {"i915_dp_test_type", &i915_displayport_test_type_fops}, | |
5336 | {"i915_dp_test_active", &i915_displayport_test_active_fops} | |
34b9674c DV |
5337 | }; |
5338 | ||
36cdd013 | 5339 | void intel_display_crc_init(struct drm_i915_private *dev_priv) |
07144428 | 5340 | { |
b378360e | 5341 | enum pipe pipe; |
07144428 | 5342 | |
055e393f | 5343 | for_each_pipe(dev_priv, pipe) { |
b378360e | 5344 | struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe]; |
07144428 | 5345 | |
d538bbdf DL |
5346 | pipe_crc->opened = false; |
5347 | spin_lock_init(&pipe_crc->lock); | |
07144428 DL |
5348 | init_waitqueue_head(&pipe_crc->wq); |
5349 | } | |
5350 | } | |
5351 | ||
1dac891c | 5352 | int i915_debugfs_register(struct drm_i915_private *dev_priv) |
2017263e | 5353 | { |
91c8a326 | 5354 | struct drm_minor *minor = dev_priv->drm.primary; |
34b9674c | 5355 | int ret, i; |
f3cd474b | 5356 | |
6d794d42 | 5357 | ret = i915_forcewake_create(minor->debugfs_root, minor); |
358733e9 JB |
5358 | if (ret) |
5359 | return ret; | |
6a9c308d | 5360 | |
07144428 DL |
5361 | for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) { |
5362 | ret = i915_pipe_crc_create(minor->debugfs_root, minor, i); | |
5363 | if (ret) | |
5364 | return ret; | |
5365 | } | |
5366 | ||
34b9674c DV |
5367 | for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) { |
5368 | ret = i915_debugfs_create(minor->debugfs_root, minor, | |
5369 | i915_debugfs_files[i].name, | |
5370 | i915_debugfs_files[i].fops); | |
5371 | if (ret) | |
5372 | return ret; | |
5373 | } | |
40633219 | 5374 | |
27c202ad BG |
5375 | return drm_debugfs_create_files(i915_debugfs_list, |
5376 | I915_DEBUGFS_ENTRIES, | |
2017263e BG |
5377 | minor->debugfs_root, minor); |
5378 | } | |
5379 | ||
1dac891c | 5380 | void i915_debugfs_unregister(struct drm_i915_private *dev_priv) |
2017263e | 5381 | { |
91c8a326 | 5382 | struct drm_minor *minor = dev_priv->drm.primary; |
34b9674c DV |
5383 | int i; |
5384 | ||
27c202ad BG |
5385 | drm_debugfs_remove_files(i915_debugfs_list, |
5386 | I915_DEBUGFS_ENTRIES, minor); | |
07144428 | 5387 | |
36cdd013 | 5388 | drm_debugfs_remove_files((struct drm_info_list *)&i915_forcewake_fops, |
6d794d42 | 5389 | 1, minor); |
07144428 | 5390 | |
e309a997 | 5391 | for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) { |
07144428 DL |
5392 | struct drm_info_list *info_list = |
5393 | (struct drm_info_list *)&i915_pipe_crc_data[i]; | |
5394 | ||
5395 | drm_debugfs_remove_files(info_list, 1, minor); | |
5396 | } | |
5397 | ||
34b9674c DV |
5398 | for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) { |
5399 | struct drm_info_list *info_list = | |
36cdd013 | 5400 | (struct drm_info_list *)i915_debugfs_files[i].fops; |
34b9674c DV |
5401 | |
5402 | drm_debugfs_remove_files(info_list, 1, minor); | |
5403 | } | |
2017263e | 5404 | } |
aa7471d2 JN |
5405 | |
5406 | struct dpcd_block { | |
5407 | /* DPCD dump start address. */ | |
5408 | unsigned int offset; | |
5409 | /* DPCD dump end address, inclusive. If unset, .size will be used. */ | |
5410 | unsigned int end; | |
5411 | /* DPCD dump size. Used if .end is unset. If unset, defaults to 1. */ | |
5412 | size_t size; | |
5413 | /* Only valid for eDP. */ | |
5414 | bool edp; | |
5415 | }; | |
5416 | ||
5417 | static const struct dpcd_block i915_dpcd_debug[] = { | |
5418 | { .offset = DP_DPCD_REV, .size = DP_RECEIVER_CAP_SIZE }, | |
5419 | { .offset = DP_PSR_SUPPORT, .end = DP_PSR_CAPS }, | |
5420 | { .offset = DP_DOWNSTREAM_PORT_0, .size = 16 }, | |
5421 | { .offset = DP_LINK_BW_SET, .end = DP_EDP_CONFIGURATION_SET }, | |
5422 | { .offset = DP_SINK_COUNT, .end = DP_ADJUST_REQUEST_LANE2_3 }, | |
5423 | { .offset = DP_SET_POWER }, | |
5424 | { .offset = DP_EDP_DPCD_REV }, | |
5425 | { .offset = DP_EDP_GENERAL_CAP_1, .end = DP_EDP_GENERAL_CAP_3 }, | |
5426 | { .offset = DP_EDP_DISPLAY_CONTROL_REGISTER, .end = DP_EDP_BACKLIGHT_FREQ_CAP_MAX_LSB }, | |
5427 | { .offset = DP_EDP_DBC_MINIMUM_BRIGHTNESS_SET, .end = DP_EDP_DBC_MAXIMUM_BRIGHTNESS_SET }, | |
5428 | }; | |
5429 | ||
5430 | static int i915_dpcd_show(struct seq_file *m, void *data) | |
5431 | { | |
5432 | struct drm_connector *connector = m->private; | |
5433 | struct intel_dp *intel_dp = | |
5434 | enc_to_intel_dp(&intel_attached_encoder(connector)->base); | |
5435 | uint8_t buf[16]; | |
5436 | ssize_t err; | |
5437 | int i; | |
5438 | ||
5c1a8875 MK |
5439 | if (connector->status != connector_status_connected) |
5440 | return -ENODEV; | |
5441 | ||
aa7471d2 JN |
5442 | for (i = 0; i < ARRAY_SIZE(i915_dpcd_debug); i++) { |
5443 | const struct dpcd_block *b = &i915_dpcd_debug[i]; | |
5444 | size_t size = b->end ? b->end - b->offset + 1 : (b->size ?: 1); | |
5445 | ||
5446 | if (b->edp && | |
5447 | connector->connector_type != DRM_MODE_CONNECTOR_eDP) | |
5448 | continue; | |
5449 | ||
5450 | /* low tech for now */ | |
5451 | if (WARN_ON(size > sizeof(buf))) | |
5452 | continue; | |
5453 | ||
5454 | err = drm_dp_dpcd_read(&intel_dp->aux, b->offset, buf, size); | |
5455 | if (err <= 0) { | |
5456 | DRM_ERROR("dpcd read (%zu bytes at %u) failed (%zd)\n", | |
5457 | size, b->offset, err); | |
5458 | continue; | |
5459 | } | |
5460 | ||
5461 | seq_printf(m, "%04x: %*ph\n", b->offset, (int) size, buf); | |
b3f9d7d7 | 5462 | } |
aa7471d2 JN |
5463 | |
5464 | return 0; | |
5465 | } | |
5466 | ||
5467 | static int i915_dpcd_open(struct inode *inode, struct file *file) | |
5468 | { | |
5469 | return single_open(file, i915_dpcd_show, inode->i_private); | |
5470 | } | |
5471 | ||
5472 | static const struct file_operations i915_dpcd_fops = { | |
5473 | .owner = THIS_MODULE, | |
5474 | .open = i915_dpcd_open, | |
5475 | .read = seq_read, | |
5476 | .llseek = seq_lseek, | |
5477 | .release = single_release, | |
5478 | }; | |
5479 | ||
ecbd6781 DW |
5480 | static int i915_panel_show(struct seq_file *m, void *data) |
5481 | { | |
5482 | struct drm_connector *connector = m->private; | |
5483 | struct intel_dp *intel_dp = | |
5484 | enc_to_intel_dp(&intel_attached_encoder(connector)->base); | |
5485 | ||
5486 | if (connector->status != connector_status_connected) | |
5487 | return -ENODEV; | |
5488 | ||
5489 | seq_printf(m, "Panel power up delay: %d\n", | |
5490 | intel_dp->panel_power_up_delay); | |
5491 | seq_printf(m, "Panel power down delay: %d\n", | |
5492 | intel_dp->panel_power_down_delay); | |
5493 | seq_printf(m, "Backlight on delay: %d\n", | |
5494 | intel_dp->backlight_on_delay); | |
5495 | seq_printf(m, "Backlight off delay: %d\n", | |
5496 | intel_dp->backlight_off_delay); | |
5497 | ||
5498 | return 0; | |
5499 | } | |
5500 | ||
5501 | static int i915_panel_open(struct inode *inode, struct file *file) | |
5502 | { | |
5503 | return single_open(file, i915_panel_show, inode->i_private); | |
5504 | } | |
5505 | ||
5506 | static const struct file_operations i915_panel_fops = { | |
5507 | .owner = THIS_MODULE, | |
5508 | .open = i915_panel_open, | |
5509 | .read = seq_read, | |
5510 | .llseek = seq_lseek, | |
5511 | .release = single_release, | |
5512 | }; | |
5513 | ||
aa7471d2 JN |
5514 | /** |
5515 | * i915_debugfs_connector_add - add i915 specific connector debugfs files | |
5516 | * @connector: pointer to a registered drm_connector | |
5517 | * | |
5518 | * Cleanup will be done by drm_connector_unregister() through a call to | |
5519 | * drm_debugfs_connector_remove(). | |
5520 | * | |
5521 | * Returns 0 on success, negative error codes on error. | |
5522 | */ | |
5523 | int i915_debugfs_connector_add(struct drm_connector *connector) | |
5524 | { | |
5525 | struct dentry *root = connector->debugfs_entry; | |
5526 | ||
5527 | /* The connector must have been registered beforehands. */ | |
5528 | if (!root) | |
5529 | return -ENODEV; | |
5530 | ||
5531 | if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort || | |
5532 | connector->connector_type == DRM_MODE_CONNECTOR_eDP) | |
ecbd6781 DW |
5533 | debugfs_create_file("i915_dpcd", S_IRUGO, root, |
5534 | connector, &i915_dpcd_fops); | |
5535 | ||
5536 | if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) | |
5537 | debugfs_create_file("i915_panel_timings", S_IRUGO, root, | |
5538 | connector, &i915_panel_fops); | |
aa7471d2 JN |
5539 | |
5540 | return 0; | |
5541 | } |