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Commit | Line | Data |
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2017263e BG |
1 | /* |
2 | * Copyright © 2008 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | * Keith Packard <keithp@keithp.com> | |
26 | * | |
27 | */ | |
28 | ||
29 | #include <linux/seq_file.h> | |
b2c88f5b | 30 | #include <linux/circ_buf.h> |
926321d5 | 31 | #include <linux/ctype.h> |
f3cd474b | 32 | #include <linux/debugfs.h> |
5a0e3ad6 | 33 | #include <linux/slab.h> |
2d1a8a48 | 34 | #include <linux/export.h> |
6d2b8885 | 35 | #include <linux/list_sort.h> |
ec013e7f | 36 | #include <asm/msr-index.h> |
760285e7 | 37 | #include <drm/drmP.h> |
4e5359cd | 38 | #include "intel_drv.h" |
e5c65260 | 39 | #include "intel_ringbuffer.h" |
760285e7 | 40 | #include <drm/i915_drm.h> |
2017263e BG |
41 | #include "i915_drv.h" |
42 | ||
f13d3f73 | 43 | enum { |
69dc4987 | 44 | ACTIVE_LIST, |
f13d3f73 | 45 | INACTIVE_LIST, |
d21d5975 | 46 | PINNED_LIST, |
f13d3f73 | 47 | }; |
2017263e | 48 | |
70d39fe4 CW |
49 | static const char *yesno(int v) |
50 | { | |
51 | return v ? "yes" : "no"; | |
52 | } | |
53 | ||
497666d8 DL |
54 | /* As the drm_debugfs_init() routines are called before dev->dev_private is |
55 | * allocated we need to hook into the minor for release. */ | |
56 | static int | |
57 | drm_add_fake_info_node(struct drm_minor *minor, | |
58 | struct dentry *ent, | |
59 | const void *key) | |
60 | { | |
61 | struct drm_info_node *node; | |
62 | ||
63 | node = kmalloc(sizeof(*node), GFP_KERNEL); | |
64 | if (node == NULL) { | |
65 | debugfs_remove(ent); | |
66 | return -ENOMEM; | |
67 | } | |
68 | ||
69 | node->minor = minor; | |
70 | node->dent = ent; | |
71 | node->info_ent = (void *) key; | |
72 | ||
73 | mutex_lock(&minor->debugfs_lock); | |
74 | list_add(&node->list, &minor->debugfs_list); | |
75 | mutex_unlock(&minor->debugfs_lock); | |
76 | ||
77 | return 0; | |
78 | } | |
79 | ||
70d39fe4 CW |
80 | static int i915_capabilities(struct seq_file *m, void *data) |
81 | { | |
9f25d007 | 82 | struct drm_info_node *node = m->private; |
70d39fe4 CW |
83 | struct drm_device *dev = node->minor->dev; |
84 | const struct intel_device_info *info = INTEL_INFO(dev); | |
85 | ||
86 | seq_printf(m, "gen: %d\n", info->gen); | |
03d00ac5 | 87 | seq_printf(m, "pch: %d\n", INTEL_PCH_TYPE(dev)); |
79fc46df DL |
88 | #define PRINT_FLAG(x) seq_printf(m, #x ": %s\n", yesno(info->x)) |
89 | #define SEP_SEMICOLON ; | |
90 | DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG, SEP_SEMICOLON); | |
91 | #undef PRINT_FLAG | |
92 | #undef SEP_SEMICOLON | |
70d39fe4 CW |
93 | |
94 | return 0; | |
95 | } | |
2017263e | 96 | |
05394f39 | 97 | static const char *get_pin_flag(struct drm_i915_gem_object *obj) |
a6172a80 | 98 | { |
05394f39 | 99 | if (obj->user_pin_count > 0) |
a6172a80 | 100 | return "P"; |
d7f46fc4 | 101 | else if (i915_gem_obj_is_pinned(obj)) |
a6172a80 CW |
102 | return "p"; |
103 | else | |
104 | return " "; | |
105 | } | |
106 | ||
05394f39 | 107 | static const char *get_tiling_flag(struct drm_i915_gem_object *obj) |
a6172a80 | 108 | { |
0206e353 AJ |
109 | switch (obj->tiling_mode) { |
110 | default: | |
111 | case I915_TILING_NONE: return " "; | |
112 | case I915_TILING_X: return "X"; | |
113 | case I915_TILING_Y: return "Y"; | |
114 | } | |
a6172a80 CW |
115 | } |
116 | ||
1d693bcc BW |
117 | static inline const char *get_global_flag(struct drm_i915_gem_object *obj) |
118 | { | |
119 | return obj->has_global_gtt_mapping ? "g" : " "; | |
120 | } | |
121 | ||
37811fcc CW |
122 | static void |
123 | describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj) | |
124 | { | |
1d693bcc | 125 | struct i915_vma *vma; |
d7f46fc4 BW |
126 | int pin_count = 0; |
127 | ||
fb1ae911 | 128 | seq_printf(m, "%pK: %s%s%s %8zdKiB %02x %02x %u %u %u%s%s%s", |
37811fcc CW |
129 | &obj->base, |
130 | get_pin_flag(obj), | |
131 | get_tiling_flag(obj), | |
1d693bcc | 132 | get_global_flag(obj), |
a05a5862 | 133 | obj->base.size / 1024, |
37811fcc CW |
134 | obj->base.read_domains, |
135 | obj->base.write_domain, | |
0201f1ec CW |
136 | obj->last_read_seqno, |
137 | obj->last_write_seqno, | |
caea7476 | 138 | obj->last_fenced_seqno, |
84734a04 | 139 | i915_cache_level_str(obj->cache_level), |
37811fcc CW |
140 | obj->dirty ? " dirty" : "", |
141 | obj->madv == I915_MADV_DONTNEED ? " purgeable" : ""); | |
142 | if (obj->base.name) | |
143 | seq_printf(m, " (name: %d)", obj->base.name); | |
d7f46fc4 BW |
144 | list_for_each_entry(vma, &obj->vma_list, vma_link) |
145 | if (vma->pin_count > 0) | |
146 | pin_count++; | |
147 | seq_printf(m, " (pinned x %d)", pin_count); | |
cc98b413 CW |
148 | if (obj->pin_display) |
149 | seq_printf(m, " (display)"); | |
37811fcc CW |
150 | if (obj->fence_reg != I915_FENCE_REG_NONE) |
151 | seq_printf(m, " (fence: %d)", obj->fence_reg); | |
1d693bcc BW |
152 | list_for_each_entry(vma, &obj->vma_list, vma_link) { |
153 | if (!i915_is_ggtt(vma->vm)) | |
154 | seq_puts(m, " (pp"); | |
155 | else | |
156 | seq_puts(m, " (g"); | |
157 | seq_printf(m, "gtt offset: %08lx, size: %08lx)", | |
158 | vma->node.start, vma->node.size); | |
159 | } | |
c1ad11fc CW |
160 | if (obj->stolen) |
161 | seq_printf(m, " (stolen: %08lx)", obj->stolen->start); | |
6299f992 CW |
162 | if (obj->pin_mappable || obj->fault_mappable) { |
163 | char s[3], *t = s; | |
164 | if (obj->pin_mappable) | |
165 | *t++ = 'p'; | |
166 | if (obj->fault_mappable) | |
167 | *t++ = 'f'; | |
168 | *t = '\0'; | |
169 | seq_printf(m, " (%s mappable)", s); | |
170 | } | |
69dc4987 CW |
171 | if (obj->ring != NULL) |
172 | seq_printf(m, " (%s)", obj->ring->name); | |
d5a81ef1 DV |
173 | if (obj->frontbuffer_bits) |
174 | seq_printf(m, " (frontbuffer: 0x%03x)", obj->frontbuffer_bits); | |
37811fcc CW |
175 | } |
176 | ||
273497e5 | 177 | static void describe_ctx(struct seq_file *m, struct intel_context *ctx) |
3ccfd19d | 178 | { |
ea0c76f8 | 179 | seq_putc(m, ctx->legacy_hw_ctx.initialized ? 'I' : 'i'); |
3ccfd19d BW |
180 | seq_putc(m, ctx->remap_slice ? 'R' : 'r'); |
181 | seq_putc(m, ' '); | |
182 | } | |
183 | ||
433e12f7 | 184 | static int i915_gem_object_list_info(struct seq_file *m, void *data) |
2017263e | 185 | { |
9f25d007 | 186 | struct drm_info_node *node = m->private; |
433e12f7 BG |
187 | uintptr_t list = (uintptr_t) node->info_ent->data; |
188 | struct list_head *head; | |
2017263e | 189 | struct drm_device *dev = node->minor->dev; |
5cef07e1 BW |
190 | struct drm_i915_private *dev_priv = dev->dev_private; |
191 | struct i915_address_space *vm = &dev_priv->gtt.base; | |
ca191b13 | 192 | struct i915_vma *vma; |
8f2480fb CW |
193 | size_t total_obj_size, total_gtt_size; |
194 | int count, ret; | |
de227ef0 CW |
195 | |
196 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
197 | if (ret) | |
198 | return ret; | |
2017263e | 199 | |
ca191b13 | 200 | /* FIXME: the user of this interface might want more than just GGTT */ |
433e12f7 BG |
201 | switch (list) { |
202 | case ACTIVE_LIST: | |
267f0c90 | 203 | seq_puts(m, "Active:\n"); |
5cef07e1 | 204 | head = &vm->active_list; |
433e12f7 BG |
205 | break; |
206 | case INACTIVE_LIST: | |
267f0c90 | 207 | seq_puts(m, "Inactive:\n"); |
5cef07e1 | 208 | head = &vm->inactive_list; |
433e12f7 | 209 | break; |
433e12f7 | 210 | default: |
de227ef0 CW |
211 | mutex_unlock(&dev->struct_mutex); |
212 | return -EINVAL; | |
2017263e | 213 | } |
2017263e | 214 | |
8f2480fb | 215 | total_obj_size = total_gtt_size = count = 0; |
ca191b13 BW |
216 | list_for_each_entry(vma, head, mm_list) { |
217 | seq_printf(m, " "); | |
218 | describe_obj(m, vma->obj); | |
219 | seq_printf(m, "\n"); | |
220 | total_obj_size += vma->obj->base.size; | |
221 | total_gtt_size += vma->node.size; | |
8f2480fb | 222 | count++; |
2017263e | 223 | } |
de227ef0 | 224 | mutex_unlock(&dev->struct_mutex); |
5e118f41 | 225 | |
8f2480fb CW |
226 | seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n", |
227 | count, total_obj_size, total_gtt_size); | |
2017263e BG |
228 | return 0; |
229 | } | |
230 | ||
6d2b8885 CW |
231 | static int obj_rank_by_stolen(void *priv, |
232 | struct list_head *A, struct list_head *B) | |
233 | { | |
234 | struct drm_i915_gem_object *a = | |
b25cb2f8 | 235 | container_of(A, struct drm_i915_gem_object, obj_exec_link); |
6d2b8885 | 236 | struct drm_i915_gem_object *b = |
b25cb2f8 | 237 | container_of(B, struct drm_i915_gem_object, obj_exec_link); |
6d2b8885 CW |
238 | |
239 | return a->stolen->start - b->stolen->start; | |
240 | } | |
241 | ||
242 | static int i915_gem_stolen_list_info(struct seq_file *m, void *data) | |
243 | { | |
9f25d007 | 244 | struct drm_info_node *node = m->private; |
6d2b8885 CW |
245 | struct drm_device *dev = node->minor->dev; |
246 | struct drm_i915_private *dev_priv = dev->dev_private; | |
247 | struct drm_i915_gem_object *obj; | |
248 | size_t total_obj_size, total_gtt_size; | |
249 | LIST_HEAD(stolen); | |
250 | int count, ret; | |
251 | ||
252 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
253 | if (ret) | |
254 | return ret; | |
255 | ||
256 | total_obj_size = total_gtt_size = count = 0; | |
257 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) { | |
258 | if (obj->stolen == NULL) | |
259 | continue; | |
260 | ||
b25cb2f8 | 261 | list_add(&obj->obj_exec_link, &stolen); |
6d2b8885 CW |
262 | |
263 | total_obj_size += obj->base.size; | |
264 | total_gtt_size += i915_gem_obj_ggtt_size(obj); | |
265 | count++; | |
266 | } | |
267 | list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) { | |
268 | if (obj->stolen == NULL) | |
269 | continue; | |
270 | ||
b25cb2f8 | 271 | list_add(&obj->obj_exec_link, &stolen); |
6d2b8885 CW |
272 | |
273 | total_obj_size += obj->base.size; | |
274 | count++; | |
275 | } | |
276 | list_sort(NULL, &stolen, obj_rank_by_stolen); | |
277 | seq_puts(m, "Stolen:\n"); | |
278 | while (!list_empty(&stolen)) { | |
b25cb2f8 | 279 | obj = list_first_entry(&stolen, typeof(*obj), obj_exec_link); |
6d2b8885 CW |
280 | seq_puts(m, " "); |
281 | describe_obj(m, obj); | |
282 | seq_putc(m, '\n'); | |
b25cb2f8 | 283 | list_del_init(&obj->obj_exec_link); |
6d2b8885 CW |
284 | } |
285 | mutex_unlock(&dev->struct_mutex); | |
286 | ||
287 | seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n", | |
288 | count, total_obj_size, total_gtt_size); | |
289 | return 0; | |
290 | } | |
291 | ||
6299f992 CW |
292 | #define count_objects(list, member) do { \ |
293 | list_for_each_entry(obj, list, member) { \ | |
f343c5f6 | 294 | size += i915_gem_obj_ggtt_size(obj); \ |
6299f992 CW |
295 | ++count; \ |
296 | if (obj->map_and_fenceable) { \ | |
f343c5f6 | 297 | mappable_size += i915_gem_obj_ggtt_size(obj); \ |
6299f992 CW |
298 | ++mappable_count; \ |
299 | } \ | |
300 | } \ | |
0206e353 | 301 | } while (0) |
6299f992 | 302 | |
2db8e9d6 | 303 | struct file_stats { |
6313c204 | 304 | struct drm_i915_file_private *file_priv; |
2db8e9d6 | 305 | int count; |
c67a17e9 CW |
306 | size_t total, unbound; |
307 | size_t global, shared; | |
308 | size_t active, inactive; | |
2db8e9d6 CW |
309 | }; |
310 | ||
311 | static int per_file_stats(int id, void *ptr, void *data) | |
312 | { | |
313 | struct drm_i915_gem_object *obj = ptr; | |
314 | struct file_stats *stats = data; | |
6313c204 | 315 | struct i915_vma *vma; |
2db8e9d6 CW |
316 | |
317 | stats->count++; | |
318 | stats->total += obj->base.size; | |
319 | ||
c67a17e9 CW |
320 | if (obj->base.name || obj->base.dma_buf) |
321 | stats->shared += obj->base.size; | |
322 | ||
6313c204 CW |
323 | if (USES_FULL_PPGTT(obj->base.dev)) { |
324 | list_for_each_entry(vma, &obj->vma_list, vma_link) { | |
325 | struct i915_hw_ppgtt *ppgtt; | |
326 | ||
327 | if (!drm_mm_node_allocated(&vma->node)) | |
328 | continue; | |
329 | ||
330 | if (i915_is_ggtt(vma->vm)) { | |
331 | stats->global += obj->base.size; | |
332 | continue; | |
333 | } | |
334 | ||
335 | ppgtt = container_of(vma->vm, struct i915_hw_ppgtt, base); | |
4d884705 | 336 | if (ppgtt->file_priv != stats->file_priv) |
6313c204 CW |
337 | continue; |
338 | ||
339 | if (obj->ring) /* XXX per-vma statistic */ | |
340 | stats->active += obj->base.size; | |
341 | else | |
342 | stats->inactive += obj->base.size; | |
343 | ||
344 | return 0; | |
345 | } | |
2db8e9d6 | 346 | } else { |
6313c204 CW |
347 | if (i915_gem_obj_ggtt_bound(obj)) { |
348 | stats->global += obj->base.size; | |
349 | if (obj->ring) | |
350 | stats->active += obj->base.size; | |
351 | else | |
352 | stats->inactive += obj->base.size; | |
353 | return 0; | |
354 | } | |
2db8e9d6 CW |
355 | } |
356 | ||
6313c204 CW |
357 | if (!list_empty(&obj->global_list)) |
358 | stats->unbound += obj->base.size; | |
359 | ||
2db8e9d6 CW |
360 | return 0; |
361 | } | |
362 | ||
ca191b13 BW |
363 | #define count_vmas(list, member) do { \ |
364 | list_for_each_entry(vma, list, member) { \ | |
365 | size += i915_gem_obj_ggtt_size(vma->obj); \ | |
366 | ++count; \ | |
367 | if (vma->obj->map_and_fenceable) { \ | |
368 | mappable_size += i915_gem_obj_ggtt_size(vma->obj); \ | |
369 | ++mappable_count; \ | |
370 | } \ | |
371 | } \ | |
372 | } while (0) | |
373 | ||
374 | static int i915_gem_object_info(struct seq_file *m, void* data) | |
73aa808f | 375 | { |
9f25d007 | 376 | struct drm_info_node *node = m->private; |
73aa808f CW |
377 | struct drm_device *dev = node->minor->dev; |
378 | struct drm_i915_private *dev_priv = dev->dev_private; | |
b7abb714 CW |
379 | u32 count, mappable_count, purgeable_count; |
380 | size_t size, mappable_size, purgeable_size; | |
6299f992 | 381 | struct drm_i915_gem_object *obj; |
5cef07e1 | 382 | struct i915_address_space *vm = &dev_priv->gtt.base; |
2db8e9d6 | 383 | struct drm_file *file; |
ca191b13 | 384 | struct i915_vma *vma; |
73aa808f CW |
385 | int ret; |
386 | ||
387 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
388 | if (ret) | |
389 | return ret; | |
390 | ||
6299f992 CW |
391 | seq_printf(m, "%u objects, %zu bytes\n", |
392 | dev_priv->mm.object_count, | |
393 | dev_priv->mm.object_memory); | |
394 | ||
395 | size = count = mappable_size = mappable_count = 0; | |
35c20a60 | 396 | count_objects(&dev_priv->mm.bound_list, global_list); |
6299f992 CW |
397 | seq_printf(m, "%u [%u] objects, %zu [%zu] bytes in gtt\n", |
398 | count, mappable_count, size, mappable_size); | |
399 | ||
400 | size = count = mappable_size = mappable_count = 0; | |
ca191b13 | 401 | count_vmas(&vm->active_list, mm_list); |
6299f992 CW |
402 | seq_printf(m, " %u [%u] active objects, %zu [%zu] bytes\n", |
403 | count, mappable_count, size, mappable_size); | |
404 | ||
6299f992 | 405 | size = count = mappable_size = mappable_count = 0; |
ca191b13 | 406 | count_vmas(&vm->inactive_list, mm_list); |
6299f992 CW |
407 | seq_printf(m, " %u [%u] inactive objects, %zu [%zu] bytes\n", |
408 | count, mappable_count, size, mappable_size); | |
409 | ||
b7abb714 | 410 | size = count = purgeable_size = purgeable_count = 0; |
35c20a60 | 411 | list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) { |
6c085a72 | 412 | size += obj->base.size, ++count; |
b7abb714 CW |
413 | if (obj->madv == I915_MADV_DONTNEED) |
414 | purgeable_size += obj->base.size, ++purgeable_count; | |
415 | } | |
6c085a72 CW |
416 | seq_printf(m, "%u unbound objects, %zu bytes\n", count, size); |
417 | ||
6299f992 | 418 | size = count = mappable_size = mappable_count = 0; |
35c20a60 | 419 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) { |
6299f992 | 420 | if (obj->fault_mappable) { |
f343c5f6 | 421 | size += i915_gem_obj_ggtt_size(obj); |
6299f992 CW |
422 | ++count; |
423 | } | |
424 | if (obj->pin_mappable) { | |
f343c5f6 | 425 | mappable_size += i915_gem_obj_ggtt_size(obj); |
6299f992 CW |
426 | ++mappable_count; |
427 | } | |
b7abb714 CW |
428 | if (obj->madv == I915_MADV_DONTNEED) { |
429 | purgeable_size += obj->base.size; | |
430 | ++purgeable_count; | |
431 | } | |
6299f992 | 432 | } |
b7abb714 CW |
433 | seq_printf(m, "%u purgeable objects, %zu bytes\n", |
434 | purgeable_count, purgeable_size); | |
6299f992 CW |
435 | seq_printf(m, "%u pinned mappable objects, %zu bytes\n", |
436 | mappable_count, mappable_size); | |
437 | seq_printf(m, "%u fault mappable objects, %zu bytes\n", | |
438 | count, size); | |
439 | ||
93d18799 | 440 | seq_printf(m, "%zu [%lu] gtt total\n", |
853ba5d2 BW |
441 | dev_priv->gtt.base.total, |
442 | dev_priv->gtt.mappable_end - dev_priv->gtt.base.start); | |
73aa808f | 443 | |
267f0c90 | 444 | seq_putc(m, '\n'); |
2db8e9d6 CW |
445 | list_for_each_entry_reverse(file, &dev->filelist, lhead) { |
446 | struct file_stats stats; | |
3ec2f427 | 447 | struct task_struct *task; |
2db8e9d6 CW |
448 | |
449 | memset(&stats, 0, sizeof(stats)); | |
6313c204 | 450 | stats.file_priv = file->driver_priv; |
5b5ffff0 | 451 | spin_lock(&file->table_lock); |
2db8e9d6 | 452 | idr_for_each(&file->object_idr, per_file_stats, &stats); |
5b5ffff0 | 453 | spin_unlock(&file->table_lock); |
3ec2f427 TH |
454 | /* |
455 | * Although we have a valid reference on file->pid, that does | |
456 | * not guarantee that the task_struct who called get_pid() is | |
457 | * still alive (e.g. get_pid(current) => fork() => exit()). | |
458 | * Therefore, we need to protect this ->comm access using RCU. | |
459 | */ | |
460 | rcu_read_lock(); | |
461 | task = pid_task(file->pid, PIDTYPE_PID); | |
c67a17e9 | 462 | seq_printf(m, "%s: %u objects, %zu bytes (%zu active, %zu inactive, %zu global, %zu shared, %zu unbound)\n", |
3ec2f427 | 463 | task ? task->comm : "<unknown>", |
2db8e9d6 CW |
464 | stats.count, |
465 | stats.total, | |
466 | stats.active, | |
467 | stats.inactive, | |
6313c204 | 468 | stats.global, |
c67a17e9 | 469 | stats.shared, |
2db8e9d6 | 470 | stats.unbound); |
3ec2f427 | 471 | rcu_read_unlock(); |
2db8e9d6 CW |
472 | } |
473 | ||
73aa808f CW |
474 | mutex_unlock(&dev->struct_mutex); |
475 | ||
476 | return 0; | |
477 | } | |
478 | ||
aee56cff | 479 | static int i915_gem_gtt_info(struct seq_file *m, void *data) |
08c18323 | 480 | { |
9f25d007 | 481 | struct drm_info_node *node = m->private; |
08c18323 | 482 | struct drm_device *dev = node->minor->dev; |
1b50247a | 483 | uintptr_t list = (uintptr_t) node->info_ent->data; |
08c18323 CW |
484 | struct drm_i915_private *dev_priv = dev->dev_private; |
485 | struct drm_i915_gem_object *obj; | |
486 | size_t total_obj_size, total_gtt_size; | |
487 | int count, ret; | |
488 | ||
489 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
490 | if (ret) | |
491 | return ret; | |
492 | ||
493 | total_obj_size = total_gtt_size = count = 0; | |
35c20a60 | 494 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) { |
d7f46fc4 | 495 | if (list == PINNED_LIST && !i915_gem_obj_is_pinned(obj)) |
1b50247a CW |
496 | continue; |
497 | ||
267f0c90 | 498 | seq_puts(m, " "); |
08c18323 | 499 | describe_obj(m, obj); |
267f0c90 | 500 | seq_putc(m, '\n'); |
08c18323 | 501 | total_obj_size += obj->base.size; |
f343c5f6 | 502 | total_gtt_size += i915_gem_obj_ggtt_size(obj); |
08c18323 CW |
503 | count++; |
504 | } | |
505 | ||
506 | mutex_unlock(&dev->struct_mutex); | |
507 | ||
508 | seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n", | |
509 | count, total_obj_size, total_gtt_size); | |
510 | ||
511 | return 0; | |
512 | } | |
513 | ||
4e5359cd SF |
514 | static int i915_gem_pageflip_info(struct seq_file *m, void *data) |
515 | { | |
9f25d007 | 516 | struct drm_info_node *node = m->private; |
4e5359cd SF |
517 | struct drm_device *dev = node->minor->dev; |
518 | unsigned long flags; | |
519 | struct intel_crtc *crtc; | |
8a270ebf DV |
520 | int ret; |
521 | ||
522 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
523 | if (ret) | |
524 | return ret; | |
4e5359cd | 525 | |
d3fcc808 | 526 | for_each_intel_crtc(dev, crtc) { |
9db4a9c7 JB |
527 | const char pipe = pipe_name(crtc->pipe); |
528 | const char plane = plane_name(crtc->plane); | |
4e5359cd SF |
529 | struct intel_unpin_work *work; |
530 | ||
531 | spin_lock_irqsave(&dev->event_lock, flags); | |
532 | work = crtc->unpin_work; | |
533 | if (work == NULL) { | |
9db4a9c7 | 534 | seq_printf(m, "No flip due on pipe %c (plane %c)\n", |
4e5359cd SF |
535 | pipe, plane); |
536 | } else { | |
e7d841ca | 537 | if (atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) { |
9db4a9c7 | 538 | seq_printf(m, "Flip queued on pipe %c (plane %c)\n", |
4e5359cd SF |
539 | pipe, plane); |
540 | } else { | |
9db4a9c7 | 541 | seq_printf(m, "Flip pending (waiting for vsync) on pipe %c (plane %c)\n", |
4e5359cd SF |
542 | pipe, plane); |
543 | } | |
544 | if (work->enable_stall_check) | |
267f0c90 | 545 | seq_puts(m, "Stall check enabled, "); |
4e5359cd | 546 | else |
267f0c90 | 547 | seq_puts(m, "Stall check waiting for page flip ioctl, "); |
e7d841ca | 548 | seq_printf(m, "%d prepares\n", atomic_read(&work->pending)); |
4e5359cd SF |
549 | |
550 | if (work->old_fb_obj) { | |
05394f39 CW |
551 | struct drm_i915_gem_object *obj = work->old_fb_obj; |
552 | if (obj) | |
f343c5f6 BW |
553 | seq_printf(m, "Old framebuffer gtt_offset 0x%08lx\n", |
554 | i915_gem_obj_ggtt_offset(obj)); | |
4e5359cd SF |
555 | } |
556 | if (work->pending_flip_obj) { | |
05394f39 CW |
557 | struct drm_i915_gem_object *obj = work->pending_flip_obj; |
558 | if (obj) | |
f343c5f6 BW |
559 | seq_printf(m, "New framebuffer gtt_offset 0x%08lx\n", |
560 | i915_gem_obj_ggtt_offset(obj)); | |
4e5359cd SF |
561 | } |
562 | } | |
563 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
564 | } | |
565 | ||
8a270ebf DV |
566 | mutex_unlock(&dev->struct_mutex); |
567 | ||
4e5359cd SF |
568 | return 0; |
569 | } | |
570 | ||
2017263e BG |
571 | static int i915_gem_request_info(struct seq_file *m, void *data) |
572 | { | |
9f25d007 | 573 | struct drm_info_node *node = m->private; |
2017263e | 574 | struct drm_device *dev = node->minor->dev; |
e277a1f8 | 575 | struct drm_i915_private *dev_priv = dev->dev_private; |
a4872ba6 | 576 | struct intel_engine_cs *ring; |
2017263e | 577 | struct drm_i915_gem_request *gem_request; |
a2c7f6fd | 578 | int ret, count, i; |
de227ef0 CW |
579 | |
580 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
581 | if (ret) | |
582 | return ret; | |
2017263e | 583 | |
c2c347a9 | 584 | count = 0; |
a2c7f6fd CW |
585 | for_each_ring(ring, dev_priv, i) { |
586 | if (list_empty(&ring->request_list)) | |
587 | continue; | |
588 | ||
589 | seq_printf(m, "%s requests:\n", ring->name); | |
c2c347a9 | 590 | list_for_each_entry(gem_request, |
a2c7f6fd | 591 | &ring->request_list, |
c2c347a9 CW |
592 | list) { |
593 | seq_printf(m, " %d @ %d\n", | |
594 | gem_request->seqno, | |
595 | (int) (jiffies - gem_request->emitted_jiffies)); | |
596 | } | |
597 | count++; | |
2017263e | 598 | } |
de227ef0 CW |
599 | mutex_unlock(&dev->struct_mutex); |
600 | ||
c2c347a9 | 601 | if (count == 0) |
267f0c90 | 602 | seq_puts(m, "No requests\n"); |
c2c347a9 | 603 | |
2017263e BG |
604 | return 0; |
605 | } | |
606 | ||
b2223497 | 607 | static void i915_ring_seqno_info(struct seq_file *m, |
a4872ba6 | 608 | struct intel_engine_cs *ring) |
b2223497 CW |
609 | { |
610 | if (ring->get_seqno) { | |
43a7b924 | 611 | seq_printf(m, "Current sequence (%s): %u\n", |
b2eadbc8 | 612 | ring->name, ring->get_seqno(ring, false)); |
b2223497 CW |
613 | } |
614 | } | |
615 | ||
2017263e BG |
616 | static int i915_gem_seqno_info(struct seq_file *m, void *data) |
617 | { | |
9f25d007 | 618 | struct drm_info_node *node = m->private; |
2017263e | 619 | struct drm_device *dev = node->minor->dev; |
e277a1f8 | 620 | struct drm_i915_private *dev_priv = dev->dev_private; |
a4872ba6 | 621 | struct intel_engine_cs *ring; |
1ec14ad3 | 622 | int ret, i; |
de227ef0 CW |
623 | |
624 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
625 | if (ret) | |
626 | return ret; | |
c8c8fb33 | 627 | intel_runtime_pm_get(dev_priv); |
2017263e | 628 | |
a2c7f6fd CW |
629 | for_each_ring(ring, dev_priv, i) |
630 | i915_ring_seqno_info(m, ring); | |
de227ef0 | 631 | |
c8c8fb33 | 632 | intel_runtime_pm_put(dev_priv); |
de227ef0 CW |
633 | mutex_unlock(&dev->struct_mutex); |
634 | ||
2017263e BG |
635 | return 0; |
636 | } | |
637 | ||
638 | ||
639 | static int i915_interrupt_info(struct seq_file *m, void *data) | |
640 | { | |
9f25d007 | 641 | struct drm_info_node *node = m->private; |
2017263e | 642 | struct drm_device *dev = node->minor->dev; |
e277a1f8 | 643 | struct drm_i915_private *dev_priv = dev->dev_private; |
a4872ba6 | 644 | struct intel_engine_cs *ring; |
9db4a9c7 | 645 | int ret, i, pipe; |
de227ef0 CW |
646 | |
647 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
648 | if (ret) | |
649 | return ret; | |
c8c8fb33 | 650 | intel_runtime_pm_get(dev_priv); |
2017263e | 651 | |
74e1ca8c VS |
652 | if (IS_CHERRYVIEW(dev)) { |
653 | int i; | |
654 | seq_printf(m, "Master Interrupt Control:\t%08x\n", | |
655 | I915_READ(GEN8_MASTER_IRQ)); | |
656 | ||
657 | seq_printf(m, "Display IER:\t%08x\n", | |
658 | I915_READ(VLV_IER)); | |
659 | seq_printf(m, "Display IIR:\t%08x\n", | |
660 | I915_READ(VLV_IIR)); | |
661 | seq_printf(m, "Display IIR_RW:\t%08x\n", | |
662 | I915_READ(VLV_IIR_RW)); | |
663 | seq_printf(m, "Display IMR:\t%08x\n", | |
664 | I915_READ(VLV_IMR)); | |
665 | for_each_pipe(pipe) | |
666 | seq_printf(m, "Pipe %c stat:\t%08x\n", | |
667 | pipe_name(pipe), | |
668 | I915_READ(PIPESTAT(pipe))); | |
669 | ||
670 | seq_printf(m, "Port hotplug:\t%08x\n", | |
671 | I915_READ(PORT_HOTPLUG_EN)); | |
672 | seq_printf(m, "DPFLIPSTAT:\t%08x\n", | |
673 | I915_READ(VLV_DPFLIPSTAT)); | |
674 | seq_printf(m, "DPINVGTT:\t%08x\n", | |
675 | I915_READ(DPINVGTT)); | |
676 | ||
677 | for (i = 0; i < 4; i++) { | |
678 | seq_printf(m, "GT Interrupt IMR %d:\t%08x\n", | |
679 | i, I915_READ(GEN8_GT_IMR(i))); | |
680 | seq_printf(m, "GT Interrupt IIR %d:\t%08x\n", | |
681 | i, I915_READ(GEN8_GT_IIR(i))); | |
682 | seq_printf(m, "GT Interrupt IER %d:\t%08x\n", | |
683 | i, I915_READ(GEN8_GT_IER(i))); | |
684 | } | |
685 | ||
686 | seq_printf(m, "PCU interrupt mask:\t%08x\n", | |
687 | I915_READ(GEN8_PCU_IMR)); | |
688 | seq_printf(m, "PCU interrupt identity:\t%08x\n", | |
689 | I915_READ(GEN8_PCU_IIR)); | |
690 | seq_printf(m, "PCU interrupt enable:\t%08x\n", | |
691 | I915_READ(GEN8_PCU_IER)); | |
692 | } else if (INTEL_INFO(dev)->gen >= 8) { | |
a123f157 BW |
693 | seq_printf(m, "Master Interrupt Control:\t%08x\n", |
694 | I915_READ(GEN8_MASTER_IRQ)); | |
695 | ||
696 | for (i = 0; i < 4; i++) { | |
697 | seq_printf(m, "GT Interrupt IMR %d:\t%08x\n", | |
698 | i, I915_READ(GEN8_GT_IMR(i))); | |
699 | seq_printf(m, "GT Interrupt IIR %d:\t%08x\n", | |
700 | i, I915_READ(GEN8_GT_IIR(i))); | |
701 | seq_printf(m, "GT Interrupt IER %d:\t%08x\n", | |
702 | i, I915_READ(GEN8_GT_IER(i))); | |
703 | } | |
704 | ||
07d27e20 | 705 | for_each_pipe(pipe) { |
22c59960 PZ |
706 | if (!intel_display_power_enabled(dev_priv, |
707 | POWER_DOMAIN_PIPE(pipe))) { | |
708 | seq_printf(m, "Pipe %c power disabled\n", | |
709 | pipe_name(pipe)); | |
710 | continue; | |
711 | } | |
a123f157 | 712 | seq_printf(m, "Pipe %c IMR:\t%08x\n", |
07d27e20 DL |
713 | pipe_name(pipe), |
714 | I915_READ(GEN8_DE_PIPE_IMR(pipe))); | |
a123f157 | 715 | seq_printf(m, "Pipe %c IIR:\t%08x\n", |
07d27e20 DL |
716 | pipe_name(pipe), |
717 | I915_READ(GEN8_DE_PIPE_IIR(pipe))); | |
a123f157 | 718 | seq_printf(m, "Pipe %c IER:\t%08x\n", |
07d27e20 DL |
719 | pipe_name(pipe), |
720 | I915_READ(GEN8_DE_PIPE_IER(pipe))); | |
a123f157 BW |
721 | } |
722 | ||
723 | seq_printf(m, "Display Engine port interrupt mask:\t%08x\n", | |
724 | I915_READ(GEN8_DE_PORT_IMR)); | |
725 | seq_printf(m, "Display Engine port interrupt identity:\t%08x\n", | |
726 | I915_READ(GEN8_DE_PORT_IIR)); | |
727 | seq_printf(m, "Display Engine port interrupt enable:\t%08x\n", | |
728 | I915_READ(GEN8_DE_PORT_IER)); | |
729 | ||
730 | seq_printf(m, "Display Engine misc interrupt mask:\t%08x\n", | |
731 | I915_READ(GEN8_DE_MISC_IMR)); | |
732 | seq_printf(m, "Display Engine misc interrupt identity:\t%08x\n", | |
733 | I915_READ(GEN8_DE_MISC_IIR)); | |
734 | seq_printf(m, "Display Engine misc interrupt enable:\t%08x\n", | |
735 | I915_READ(GEN8_DE_MISC_IER)); | |
736 | ||
737 | seq_printf(m, "PCU interrupt mask:\t%08x\n", | |
738 | I915_READ(GEN8_PCU_IMR)); | |
739 | seq_printf(m, "PCU interrupt identity:\t%08x\n", | |
740 | I915_READ(GEN8_PCU_IIR)); | |
741 | seq_printf(m, "PCU interrupt enable:\t%08x\n", | |
742 | I915_READ(GEN8_PCU_IER)); | |
743 | } else if (IS_VALLEYVIEW(dev)) { | |
7e231dbe JB |
744 | seq_printf(m, "Display IER:\t%08x\n", |
745 | I915_READ(VLV_IER)); | |
746 | seq_printf(m, "Display IIR:\t%08x\n", | |
747 | I915_READ(VLV_IIR)); | |
748 | seq_printf(m, "Display IIR_RW:\t%08x\n", | |
749 | I915_READ(VLV_IIR_RW)); | |
750 | seq_printf(m, "Display IMR:\t%08x\n", | |
751 | I915_READ(VLV_IMR)); | |
752 | for_each_pipe(pipe) | |
753 | seq_printf(m, "Pipe %c stat:\t%08x\n", | |
754 | pipe_name(pipe), | |
755 | I915_READ(PIPESTAT(pipe))); | |
756 | ||
757 | seq_printf(m, "Master IER:\t%08x\n", | |
758 | I915_READ(VLV_MASTER_IER)); | |
759 | ||
760 | seq_printf(m, "Render IER:\t%08x\n", | |
761 | I915_READ(GTIER)); | |
762 | seq_printf(m, "Render IIR:\t%08x\n", | |
763 | I915_READ(GTIIR)); | |
764 | seq_printf(m, "Render IMR:\t%08x\n", | |
765 | I915_READ(GTIMR)); | |
766 | ||
767 | seq_printf(m, "PM IER:\t\t%08x\n", | |
768 | I915_READ(GEN6_PMIER)); | |
769 | seq_printf(m, "PM IIR:\t\t%08x\n", | |
770 | I915_READ(GEN6_PMIIR)); | |
771 | seq_printf(m, "PM IMR:\t\t%08x\n", | |
772 | I915_READ(GEN6_PMIMR)); | |
773 | ||
774 | seq_printf(m, "Port hotplug:\t%08x\n", | |
775 | I915_READ(PORT_HOTPLUG_EN)); | |
776 | seq_printf(m, "DPFLIPSTAT:\t%08x\n", | |
777 | I915_READ(VLV_DPFLIPSTAT)); | |
778 | seq_printf(m, "DPINVGTT:\t%08x\n", | |
779 | I915_READ(DPINVGTT)); | |
780 | ||
781 | } else if (!HAS_PCH_SPLIT(dev)) { | |
5f6a1695 ZW |
782 | seq_printf(m, "Interrupt enable: %08x\n", |
783 | I915_READ(IER)); | |
784 | seq_printf(m, "Interrupt identity: %08x\n", | |
785 | I915_READ(IIR)); | |
786 | seq_printf(m, "Interrupt mask: %08x\n", | |
787 | I915_READ(IMR)); | |
9db4a9c7 JB |
788 | for_each_pipe(pipe) |
789 | seq_printf(m, "Pipe %c stat: %08x\n", | |
790 | pipe_name(pipe), | |
791 | I915_READ(PIPESTAT(pipe))); | |
5f6a1695 ZW |
792 | } else { |
793 | seq_printf(m, "North Display Interrupt enable: %08x\n", | |
794 | I915_READ(DEIER)); | |
795 | seq_printf(m, "North Display Interrupt identity: %08x\n", | |
796 | I915_READ(DEIIR)); | |
797 | seq_printf(m, "North Display Interrupt mask: %08x\n", | |
798 | I915_READ(DEIMR)); | |
799 | seq_printf(m, "South Display Interrupt enable: %08x\n", | |
800 | I915_READ(SDEIER)); | |
801 | seq_printf(m, "South Display Interrupt identity: %08x\n", | |
802 | I915_READ(SDEIIR)); | |
803 | seq_printf(m, "South Display Interrupt mask: %08x\n", | |
804 | I915_READ(SDEIMR)); | |
805 | seq_printf(m, "Graphics Interrupt enable: %08x\n", | |
806 | I915_READ(GTIER)); | |
807 | seq_printf(m, "Graphics Interrupt identity: %08x\n", | |
808 | I915_READ(GTIIR)); | |
809 | seq_printf(m, "Graphics Interrupt mask: %08x\n", | |
810 | I915_READ(GTIMR)); | |
811 | } | |
a2c7f6fd | 812 | for_each_ring(ring, dev_priv, i) { |
a123f157 | 813 | if (INTEL_INFO(dev)->gen >= 6) { |
a2c7f6fd CW |
814 | seq_printf(m, |
815 | "Graphics Interrupt mask (%s): %08x\n", | |
816 | ring->name, I915_READ_IMR(ring)); | |
9862e600 | 817 | } |
a2c7f6fd | 818 | i915_ring_seqno_info(m, ring); |
9862e600 | 819 | } |
c8c8fb33 | 820 | intel_runtime_pm_put(dev_priv); |
de227ef0 CW |
821 | mutex_unlock(&dev->struct_mutex); |
822 | ||
2017263e BG |
823 | return 0; |
824 | } | |
825 | ||
a6172a80 CW |
826 | static int i915_gem_fence_regs_info(struct seq_file *m, void *data) |
827 | { | |
9f25d007 | 828 | struct drm_info_node *node = m->private; |
a6172a80 | 829 | struct drm_device *dev = node->minor->dev; |
e277a1f8 | 830 | struct drm_i915_private *dev_priv = dev->dev_private; |
de227ef0 CW |
831 | int i, ret; |
832 | ||
833 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
834 | if (ret) | |
835 | return ret; | |
a6172a80 CW |
836 | |
837 | seq_printf(m, "Reserved fences = %d\n", dev_priv->fence_reg_start); | |
838 | seq_printf(m, "Total fences = %d\n", dev_priv->num_fence_regs); | |
839 | for (i = 0; i < dev_priv->num_fence_regs; i++) { | |
05394f39 | 840 | struct drm_i915_gem_object *obj = dev_priv->fence_regs[i].obj; |
a6172a80 | 841 | |
6c085a72 CW |
842 | seq_printf(m, "Fence %d, pin count = %d, object = ", |
843 | i, dev_priv->fence_regs[i].pin_count); | |
c2c347a9 | 844 | if (obj == NULL) |
267f0c90 | 845 | seq_puts(m, "unused"); |
c2c347a9 | 846 | else |
05394f39 | 847 | describe_obj(m, obj); |
267f0c90 | 848 | seq_putc(m, '\n'); |
a6172a80 CW |
849 | } |
850 | ||
05394f39 | 851 | mutex_unlock(&dev->struct_mutex); |
a6172a80 CW |
852 | return 0; |
853 | } | |
854 | ||
2017263e BG |
855 | static int i915_hws_info(struct seq_file *m, void *data) |
856 | { | |
9f25d007 | 857 | struct drm_info_node *node = m->private; |
2017263e | 858 | struct drm_device *dev = node->minor->dev; |
e277a1f8 | 859 | struct drm_i915_private *dev_priv = dev->dev_private; |
a4872ba6 | 860 | struct intel_engine_cs *ring; |
1a240d4d | 861 | const u32 *hws; |
4066c0ae CW |
862 | int i; |
863 | ||
1ec14ad3 | 864 | ring = &dev_priv->ring[(uintptr_t)node->info_ent->data]; |
1a240d4d | 865 | hws = ring->status_page.page_addr; |
2017263e BG |
866 | if (hws == NULL) |
867 | return 0; | |
868 | ||
869 | for (i = 0; i < 4096 / sizeof(u32) / 4; i += 4) { | |
870 | seq_printf(m, "0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x\n", | |
871 | i * 4, | |
872 | hws[i], hws[i + 1], hws[i + 2], hws[i + 3]); | |
873 | } | |
874 | return 0; | |
875 | } | |
876 | ||
d5442303 DV |
877 | static ssize_t |
878 | i915_error_state_write(struct file *filp, | |
879 | const char __user *ubuf, | |
880 | size_t cnt, | |
881 | loff_t *ppos) | |
882 | { | |
edc3d884 | 883 | struct i915_error_state_file_priv *error_priv = filp->private_data; |
d5442303 | 884 | struct drm_device *dev = error_priv->dev; |
22bcfc6a | 885 | int ret; |
d5442303 DV |
886 | |
887 | DRM_DEBUG_DRIVER("Resetting error state\n"); | |
888 | ||
22bcfc6a DV |
889 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
890 | if (ret) | |
891 | return ret; | |
892 | ||
d5442303 DV |
893 | i915_destroy_error_state(dev); |
894 | mutex_unlock(&dev->struct_mutex); | |
895 | ||
896 | return cnt; | |
897 | } | |
898 | ||
899 | static int i915_error_state_open(struct inode *inode, struct file *file) | |
900 | { | |
901 | struct drm_device *dev = inode->i_private; | |
d5442303 | 902 | struct i915_error_state_file_priv *error_priv; |
d5442303 DV |
903 | |
904 | error_priv = kzalloc(sizeof(*error_priv), GFP_KERNEL); | |
905 | if (!error_priv) | |
906 | return -ENOMEM; | |
907 | ||
908 | error_priv->dev = dev; | |
909 | ||
95d5bfb3 | 910 | i915_error_state_get(dev, error_priv); |
d5442303 | 911 | |
edc3d884 MK |
912 | file->private_data = error_priv; |
913 | ||
914 | return 0; | |
d5442303 DV |
915 | } |
916 | ||
917 | static int i915_error_state_release(struct inode *inode, struct file *file) | |
918 | { | |
edc3d884 | 919 | struct i915_error_state_file_priv *error_priv = file->private_data; |
d5442303 | 920 | |
95d5bfb3 | 921 | i915_error_state_put(error_priv); |
d5442303 DV |
922 | kfree(error_priv); |
923 | ||
edc3d884 MK |
924 | return 0; |
925 | } | |
926 | ||
4dc955f7 MK |
927 | static ssize_t i915_error_state_read(struct file *file, char __user *userbuf, |
928 | size_t count, loff_t *pos) | |
929 | { | |
930 | struct i915_error_state_file_priv *error_priv = file->private_data; | |
931 | struct drm_i915_error_state_buf error_str; | |
932 | loff_t tmp_pos = 0; | |
933 | ssize_t ret_count = 0; | |
934 | int ret; | |
935 | ||
936 | ret = i915_error_state_buf_init(&error_str, count, *pos); | |
937 | if (ret) | |
938 | return ret; | |
edc3d884 | 939 | |
fc16b48b | 940 | ret = i915_error_state_to_str(&error_str, error_priv); |
edc3d884 MK |
941 | if (ret) |
942 | goto out; | |
943 | ||
edc3d884 MK |
944 | ret_count = simple_read_from_buffer(userbuf, count, &tmp_pos, |
945 | error_str.buf, | |
946 | error_str.bytes); | |
947 | ||
948 | if (ret_count < 0) | |
949 | ret = ret_count; | |
950 | else | |
951 | *pos = error_str.start + ret_count; | |
952 | out: | |
4dc955f7 | 953 | i915_error_state_buf_release(&error_str); |
edc3d884 | 954 | return ret ?: ret_count; |
d5442303 DV |
955 | } |
956 | ||
957 | static const struct file_operations i915_error_state_fops = { | |
958 | .owner = THIS_MODULE, | |
959 | .open = i915_error_state_open, | |
edc3d884 | 960 | .read = i915_error_state_read, |
d5442303 DV |
961 | .write = i915_error_state_write, |
962 | .llseek = default_llseek, | |
963 | .release = i915_error_state_release, | |
964 | }; | |
965 | ||
647416f9 KC |
966 | static int |
967 | i915_next_seqno_get(void *data, u64 *val) | |
40633219 | 968 | { |
647416f9 | 969 | struct drm_device *dev = data; |
e277a1f8 | 970 | struct drm_i915_private *dev_priv = dev->dev_private; |
40633219 MK |
971 | int ret; |
972 | ||
973 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
974 | if (ret) | |
975 | return ret; | |
976 | ||
647416f9 | 977 | *val = dev_priv->next_seqno; |
40633219 MK |
978 | mutex_unlock(&dev->struct_mutex); |
979 | ||
647416f9 | 980 | return 0; |
40633219 MK |
981 | } |
982 | ||
647416f9 KC |
983 | static int |
984 | i915_next_seqno_set(void *data, u64 val) | |
985 | { | |
986 | struct drm_device *dev = data; | |
40633219 MK |
987 | int ret; |
988 | ||
40633219 MK |
989 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
990 | if (ret) | |
991 | return ret; | |
992 | ||
e94fbaa8 | 993 | ret = i915_gem_set_seqno(dev, val); |
40633219 MK |
994 | mutex_unlock(&dev->struct_mutex); |
995 | ||
647416f9 | 996 | return ret; |
40633219 MK |
997 | } |
998 | ||
647416f9 KC |
999 | DEFINE_SIMPLE_ATTRIBUTE(i915_next_seqno_fops, |
1000 | i915_next_seqno_get, i915_next_seqno_set, | |
3a3b4f98 | 1001 | "0x%llx\n"); |
40633219 | 1002 | |
adb4bd12 | 1003 | static int i915_frequency_info(struct seq_file *m, void *unused) |
f97108d1 | 1004 | { |
9f25d007 | 1005 | struct drm_info_node *node = m->private; |
f97108d1 | 1006 | struct drm_device *dev = node->minor->dev; |
e277a1f8 | 1007 | struct drm_i915_private *dev_priv = dev->dev_private; |
c8c8fb33 PZ |
1008 | int ret = 0; |
1009 | ||
1010 | intel_runtime_pm_get(dev_priv); | |
3b8d8d91 | 1011 | |
5c9669ce TR |
1012 | flush_delayed_work(&dev_priv->rps.delayed_resume_work); |
1013 | ||
3b8d8d91 JB |
1014 | if (IS_GEN5(dev)) { |
1015 | u16 rgvswctl = I915_READ16(MEMSWCTL); | |
1016 | u16 rgvstat = I915_READ16(MEMSTAT_ILK); | |
1017 | ||
1018 | seq_printf(m, "Requested P-state: %d\n", (rgvswctl >> 8) & 0xf); | |
1019 | seq_printf(m, "Requested VID: %d\n", rgvswctl & 0x3f); | |
1020 | seq_printf(m, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK) >> | |
1021 | MEMSTAT_VID_SHIFT); | |
1022 | seq_printf(m, "Current P-state: %d\n", | |
1023 | (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT); | |
daa3afb2 TR |
1024 | } else if (IS_GEN6(dev) || (IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) || |
1025 | IS_BROADWELL(dev)) { | |
3b8d8d91 JB |
1026 | u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS); |
1027 | u32 rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS); | |
1028 | u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP); | |
0d8f9491 | 1029 | u32 rpmodectl, rpinclimit, rpdeclimit; |
8e8c06cd | 1030 | u32 rpstat, cagf, reqf; |
ccab5c82 JB |
1031 | u32 rpupei, rpcurup, rpprevup; |
1032 | u32 rpdownei, rpcurdown, rpprevdown; | |
3b8d8d91 JB |
1033 | int max_freq; |
1034 | ||
1035 | /* RPSTAT1 is in the GT power well */ | |
d1ebd816 BW |
1036 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
1037 | if (ret) | |
c8c8fb33 | 1038 | goto out; |
d1ebd816 | 1039 | |
c8d9a590 | 1040 | gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL); |
3b8d8d91 | 1041 | |
8e8c06cd CW |
1042 | reqf = I915_READ(GEN6_RPNSWREQ); |
1043 | reqf &= ~GEN6_TURBO_DISABLE; | |
daa3afb2 | 1044 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
8e8c06cd CW |
1045 | reqf >>= 24; |
1046 | else | |
1047 | reqf >>= 25; | |
1048 | reqf *= GT_FREQUENCY_MULTIPLIER; | |
1049 | ||
0d8f9491 CW |
1050 | rpmodectl = I915_READ(GEN6_RP_CONTROL); |
1051 | rpinclimit = I915_READ(GEN6_RP_UP_THRESHOLD); | |
1052 | rpdeclimit = I915_READ(GEN6_RP_DOWN_THRESHOLD); | |
1053 | ||
ccab5c82 JB |
1054 | rpstat = I915_READ(GEN6_RPSTAT1); |
1055 | rpupei = I915_READ(GEN6_RP_CUR_UP_EI); | |
1056 | rpcurup = I915_READ(GEN6_RP_CUR_UP); | |
1057 | rpprevup = I915_READ(GEN6_RP_PREV_UP); | |
1058 | rpdownei = I915_READ(GEN6_RP_CUR_DOWN_EI); | |
1059 | rpcurdown = I915_READ(GEN6_RP_CUR_DOWN); | |
1060 | rpprevdown = I915_READ(GEN6_RP_PREV_DOWN); | |
daa3afb2 | 1061 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
f82855d3 BW |
1062 | cagf = (rpstat & HSW_CAGF_MASK) >> HSW_CAGF_SHIFT; |
1063 | else | |
1064 | cagf = (rpstat & GEN6_CAGF_MASK) >> GEN6_CAGF_SHIFT; | |
1065 | cagf *= GT_FREQUENCY_MULTIPLIER; | |
ccab5c82 | 1066 | |
c8d9a590 | 1067 | gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL); |
d1ebd816 BW |
1068 | mutex_unlock(&dev->struct_mutex); |
1069 | ||
0d8f9491 CW |
1070 | seq_printf(m, "PM IER=0x%08x IMR=0x%08x ISR=0x%08x IIR=0x%08x, MASK=0x%08x\n", |
1071 | I915_READ(GEN6_PMIER), | |
1072 | I915_READ(GEN6_PMIMR), | |
1073 | I915_READ(GEN6_PMISR), | |
1074 | I915_READ(GEN6_PMIIR), | |
1075 | I915_READ(GEN6_PMINTRMSK)); | |
3b8d8d91 | 1076 | seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status); |
3b8d8d91 JB |
1077 | seq_printf(m, "Render p-state ratio: %d\n", |
1078 | (gt_perf_status & 0xff00) >> 8); | |
1079 | seq_printf(m, "Render p-state VID: %d\n", | |
1080 | gt_perf_status & 0xff); | |
1081 | seq_printf(m, "Render p-state limit: %d\n", | |
1082 | rp_state_limits & 0xff); | |
0d8f9491 CW |
1083 | seq_printf(m, "RPSTAT1: 0x%08x\n", rpstat); |
1084 | seq_printf(m, "RPMODECTL: 0x%08x\n", rpmodectl); | |
1085 | seq_printf(m, "RPINCLIMIT: 0x%08x\n", rpinclimit); | |
1086 | seq_printf(m, "RPDECLIMIT: 0x%08x\n", rpdeclimit); | |
8e8c06cd | 1087 | seq_printf(m, "RPNSWREQ: %dMHz\n", reqf); |
f82855d3 | 1088 | seq_printf(m, "CAGF: %dMHz\n", cagf); |
ccab5c82 JB |
1089 | seq_printf(m, "RP CUR UP EI: %dus\n", rpupei & |
1090 | GEN6_CURICONT_MASK); | |
1091 | seq_printf(m, "RP CUR UP: %dus\n", rpcurup & | |
1092 | GEN6_CURBSYTAVG_MASK); | |
1093 | seq_printf(m, "RP PREV UP: %dus\n", rpprevup & | |
1094 | GEN6_CURBSYTAVG_MASK); | |
1095 | seq_printf(m, "RP CUR DOWN EI: %dus\n", rpdownei & | |
1096 | GEN6_CURIAVG_MASK); | |
1097 | seq_printf(m, "RP CUR DOWN: %dus\n", rpcurdown & | |
1098 | GEN6_CURBSYTAVG_MASK); | |
1099 | seq_printf(m, "RP PREV DOWN: %dus\n", rpprevdown & | |
1100 | GEN6_CURBSYTAVG_MASK); | |
3b8d8d91 JB |
1101 | |
1102 | max_freq = (rp_state_cap & 0xff0000) >> 16; | |
1103 | seq_printf(m, "Lowest (RPN) frequency: %dMHz\n", | |
c8735b0c | 1104 | max_freq * GT_FREQUENCY_MULTIPLIER); |
3b8d8d91 JB |
1105 | |
1106 | max_freq = (rp_state_cap & 0xff00) >> 8; | |
1107 | seq_printf(m, "Nominal (RP1) frequency: %dMHz\n", | |
c8735b0c | 1108 | max_freq * GT_FREQUENCY_MULTIPLIER); |
3b8d8d91 JB |
1109 | |
1110 | max_freq = rp_state_cap & 0xff; | |
1111 | seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n", | |
c8735b0c | 1112 | max_freq * GT_FREQUENCY_MULTIPLIER); |
31c77388 BW |
1113 | |
1114 | seq_printf(m, "Max overclocked frequency: %dMHz\n", | |
b39fb297 | 1115 | dev_priv->rps.max_freq * GT_FREQUENCY_MULTIPLIER); |
0a073b84 | 1116 | } else if (IS_VALLEYVIEW(dev)) { |
03af2045 | 1117 | u32 freq_sts; |
0a073b84 | 1118 | |
259bd5d4 | 1119 | mutex_lock(&dev_priv->rps.hw_lock); |
64936258 | 1120 | freq_sts = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS); |
0a073b84 JB |
1121 | seq_printf(m, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts); |
1122 | seq_printf(m, "DDR freq: %d MHz\n", dev_priv->mem_freq); | |
1123 | ||
0a073b84 | 1124 | seq_printf(m, "max GPU freq: %d MHz\n", |
b2435c94 | 1125 | vlv_gpu_freq(dev_priv, dev_priv->rps.max_freq)); |
0a073b84 | 1126 | |
0a073b84 | 1127 | seq_printf(m, "min GPU freq: %d MHz\n", |
b2435c94 | 1128 | vlv_gpu_freq(dev_priv, dev_priv->rps.min_freq)); |
03af2045 VS |
1129 | |
1130 | seq_printf(m, "efficient (RPe) frequency: %d MHz\n", | |
b2435c94 | 1131 | vlv_gpu_freq(dev_priv, dev_priv->rps.efficient_freq)); |
0a073b84 JB |
1132 | |
1133 | seq_printf(m, "current GPU freq: %d MHz\n", | |
2ec3815f | 1134 | vlv_gpu_freq(dev_priv, (freq_sts >> 8) & 0xff)); |
259bd5d4 | 1135 | mutex_unlock(&dev_priv->rps.hw_lock); |
3b8d8d91 | 1136 | } else { |
267f0c90 | 1137 | seq_puts(m, "no P-state info available\n"); |
3b8d8d91 | 1138 | } |
f97108d1 | 1139 | |
c8c8fb33 PZ |
1140 | out: |
1141 | intel_runtime_pm_put(dev_priv); | |
1142 | return ret; | |
f97108d1 JB |
1143 | } |
1144 | ||
4d85529d | 1145 | static int ironlake_drpc_info(struct seq_file *m) |
f97108d1 | 1146 | { |
9f25d007 | 1147 | struct drm_info_node *node = m->private; |
f97108d1 | 1148 | struct drm_device *dev = node->minor->dev; |
e277a1f8 | 1149 | struct drm_i915_private *dev_priv = dev->dev_private; |
616fdb5a BW |
1150 | u32 rgvmodectl, rstdbyctl; |
1151 | u16 crstandvid; | |
1152 | int ret; | |
1153 | ||
1154 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
1155 | if (ret) | |
1156 | return ret; | |
c8c8fb33 | 1157 | intel_runtime_pm_get(dev_priv); |
616fdb5a BW |
1158 | |
1159 | rgvmodectl = I915_READ(MEMMODECTL); | |
1160 | rstdbyctl = I915_READ(RSTDBYCTL); | |
1161 | crstandvid = I915_READ16(CRSTANDVID); | |
1162 | ||
c8c8fb33 | 1163 | intel_runtime_pm_put(dev_priv); |
616fdb5a | 1164 | mutex_unlock(&dev->struct_mutex); |
f97108d1 JB |
1165 | |
1166 | seq_printf(m, "HD boost: %s\n", (rgvmodectl & MEMMODE_BOOST_EN) ? | |
1167 | "yes" : "no"); | |
1168 | seq_printf(m, "Boost freq: %d\n", | |
1169 | (rgvmodectl & MEMMODE_BOOST_FREQ_MASK) >> | |
1170 | MEMMODE_BOOST_FREQ_SHIFT); | |
1171 | seq_printf(m, "HW control enabled: %s\n", | |
1172 | rgvmodectl & MEMMODE_HWIDLE_EN ? "yes" : "no"); | |
1173 | seq_printf(m, "SW control enabled: %s\n", | |
1174 | rgvmodectl & MEMMODE_SWMODE_EN ? "yes" : "no"); | |
1175 | seq_printf(m, "Gated voltage change: %s\n", | |
1176 | rgvmodectl & MEMMODE_RCLK_GATE ? "yes" : "no"); | |
1177 | seq_printf(m, "Starting frequency: P%d\n", | |
1178 | (rgvmodectl & MEMMODE_FSTART_MASK) >> MEMMODE_FSTART_SHIFT); | |
7648fa99 | 1179 | seq_printf(m, "Max P-state: P%d\n", |
f97108d1 | 1180 | (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT); |
7648fa99 JB |
1181 | seq_printf(m, "Min P-state: P%d\n", (rgvmodectl & MEMMODE_FMIN_MASK)); |
1182 | seq_printf(m, "RS1 VID: %d\n", (crstandvid & 0x3f)); | |
1183 | seq_printf(m, "RS2 VID: %d\n", ((crstandvid >> 8) & 0x3f)); | |
1184 | seq_printf(m, "Render standby enabled: %s\n", | |
1185 | (rstdbyctl & RCX_SW_EXIT) ? "no" : "yes"); | |
267f0c90 | 1186 | seq_puts(m, "Current RS state: "); |
88271da3 JB |
1187 | switch (rstdbyctl & RSX_STATUS_MASK) { |
1188 | case RSX_STATUS_ON: | |
267f0c90 | 1189 | seq_puts(m, "on\n"); |
88271da3 JB |
1190 | break; |
1191 | case RSX_STATUS_RC1: | |
267f0c90 | 1192 | seq_puts(m, "RC1\n"); |
88271da3 JB |
1193 | break; |
1194 | case RSX_STATUS_RC1E: | |
267f0c90 | 1195 | seq_puts(m, "RC1E\n"); |
88271da3 JB |
1196 | break; |
1197 | case RSX_STATUS_RS1: | |
267f0c90 | 1198 | seq_puts(m, "RS1\n"); |
88271da3 JB |
1199 | break; |
1200 | case RSX_STATUS_RS2: | |
267f0c90 | 1201 | seq_puts(m, "RS2 (RC6)\n"); |
88271da3 JB |
1202 | break; |
1203 | case RSX_STATUS_RS3: | |
267f0c90 | 1204 | seq_puts(m, "RC3 (RC6+)\n"); |
88271da3 JB |
1205 | break; |
1206 | default: | |
267f0c90 | 1207 | seq_puts(m, "unknown\n"); |
88271da3 JB |
1208 | break; |
1209 | } | |
f97108d1 JB |
1210 | |
1211 | return 0; | |
1212 | } | |
1213 | ||
669ab5aa D |
1214 | static int vlv_drpc_info(struct seq_file *m) |
1215 | { | |
1216 | ||
9f25d007 | 1217 | struct drm_info_node *node = m->private; |
669ab5aa D |
1218 | struct drm_device *dev = node->minor->dev; |
1219 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1220 | u32 rpmodectl1, rcctl1; | |
1221 | unsigned fw_rendercount = 0, fw_mediacount = 0; | |
1222 | ||
d46c0517 ID |
1223 | intel_runtime_pm_get(dev_priv); |
1224 | ||
669ab5aa D |
1225 | rpmodectl1 = I915_READ(GEN6_RP_CONTROL); |
1226 | rcctl1 = I915_READ(GEN6_RC_CONTROL); | |
1227 | ||
d46c0517 ID |
1228 | intel_runtime_pm_put(dev_priv); |
1229 | ||
669ab5aa D |
1230 | seq_printf(m, "Video Turbo Mode: %s\n", |
1231 | yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO)); | |
1232 | seq_printf(m, "Turbo enabled: %s\n", | |
1233 | yesno(rpmodectl1 & GEN6_RP_ENABLE)); | |
1234 | seq_printf(m, "HW control enabled: %s\n", | |
1235 | yesno(rpmodectl1 & GEN6_RP_ENABLE)); | |
1236 | seq_printf(m, "SW control enabled: %s\n", | |
1237 | yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) == | |
1238 | GEN6_RP_MEDIA_SW_MODE)); | |
1239 | seq_printf(m, "RC6 Enabled: %s\n", | |
1240 | yesno(rcctl1 & (GEN7_RC_CTL_TO_MODE | | |
1241 | GEN6_RC_CTL_EI_MODE(1)))); | |
1242 | seq_printf(m, "Render Power Well: %s\n", | |
1243 | (I915_READ(VLV_GTLC_PW_STATUS) & | |
1244 | VLV_GTLC_PW_RENDER_STATUS_MASK) ? "Up" : "Down"); | |
1245 | seq_printf(m, "Media Power Well: %s\n", | |
1246 | (I915_READ(VLV_GTLC_PW_STATUS) & | |
1247 | VLV_GTLC_PW_MEDIA_STATUS_MASK) ? "Up" : "Down"); | |
1248 | ||
9cc19be5 ID |
1249 | seq_printf(m, "Render RC6 residency since boot: %u\n", |
1250 | I915_READ(VLV_GT_RENDER_RC6)); | |
1251 | seq_printf(m, "Media RC6 residency since boot: %u\n", | |
1252 | I915_READ(VLV_GT_MEDIA_RC6)); | |
1253 | ||
669ab5aa D |
1254 | spin_lock_irq(&dev_priv->uncore.lock); |
1255 | fw_rendercount = dev_priv->uncore.fw_rendercount; | |
1256 | fw_mediacount = dev_priv->uncore.fw_mediacount; | |
1257 | spin_unlock_irq(&dev_priv->uncore.lock); | |
1258 | ||
1259 | seq_printf(m, "Forcewake Render Count = %u\n", fw_rendercount); | |
1260 | seq_printf(m, "Forcewake Media Count = %u\n", fw_mediacount); | |
1261 | ||
1262 | ||
1263 | return 0; | |
1264 | } | |
1265 | ||
1266 | ||
4d85529d BW |
1267 | static int gen6_drpc_info(struct seq_file *m) |
1268 | { | |
1269 | ||
9f25d007 | 1270 | struct drm_info_node *node = m->private; |
4d85529d BW |
1271 | struct drm_device *dev = node->minor->dev; |
1272 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ecd8faea | 1273 | u32 rpmodectl1, gt_core_status, rcctl1, rc6vids = 0; |
93b525dc | 1274 | unsigned forcewake_count; |
aee56cff | 1275 | int count = 0, ret; |
4d85529d BW |
1276 | |
1277 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
1278 | if (ret) | |
1279 | return ret; | |
c8c8fb33 | 1280 | intel_runtime_pm_get(dev_priv); |
4d85529d | 1281 | |
907b28c5 CW |
1282 | spin_lock_irq(&dev_priv->uncore.lock); |
1283 | forcewake_count = dev_priv->uncore.forcewake_count; | |
1284 | spin_unlock_irq(&dev_priv->uncore.lock); | |
93b525dc DV |
1285 | |
1286 | if (forcewake_count) { | |
267f0c90 DL |
1287 | seq_puts(m, "RC information inaccurate because somebody " |
1288 | "holds a forcewake reference \n"); | |
4d85529d BW |
1289 | } else { |
1290 | /* NB: we cannot use forcewake, else we read the wrong values */ | |
1291 | while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1)) | |
1292 | udelay(10); | |
1293 | seq_printf(m, "RC information accurate: %s\n", yesno(count < 51)); | |
1294 | } | |
1295 | ||
1296 | gt_core_status = readl(dev_priv->regs + GEN6_GT_CORE_STATUS); | |
ed71f1b4 | 1297 | trace_i915_reg_rw(false, GEN6_GT_CORE_STATUS, gt_core_status, 4, true); |
4d85529d BW |
1298 | |
1299 | rpmodectl1 = I915_READ(GEN6_RP_CONTROL); | |
1300 | rcctl1 = I915_READ(GEN6_RC_CONTROL); | |
1301 | mutex_unlock(&dev->struct_mutex); | |
44cbd338 BW |
1302 | mutex_lock(&dev_priv->rps.hw_lock); |
1303 | sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids); | |
1304 | mutex_unlock(&dev_priv->rps.hw_lock); | |
4d85529d | 1305 | |
c8c8fb33 PZ |
1306 | intel_runtime_pm_put(dev_priv); |
1307 | ||
4d85529d BW |
1308 | seq_printf(m, "Video Turbo Mode: %s\n", |
1309 | yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO)); | |
1310 | seq_printf(m, "HW control enabled: %s\n", | |
1311 | yesno(rpmodectl1 & GEN6_RP_ENABLE)); | |
1312 | seq_printf(m, "SW control enabled: %s\n", | |
1313 | yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) == | |
1314 | GEN6_RP_MEDIA_SW_MODE)); | |
fff24e21 | 1315 | seq_printf(m, "RC1e Enabled: %s\n", |
4d85529d BW |
1316 | yesno(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE)); |
1317 | seq_printf(m, "RC6 Enabled: %s\n", | |
1318 | yesno(rcctl1 & GEN6_RC_CTL_RC6_ENABLE)); | |
1319 | seq_printf(m, "Deep RC6 Enabled: %s\n", | |
1320 | yesno(rcctl1 & GEN6_RC_CTL_RC6p_ENABLE)); | |
1321 | seq_printf(m, "Deepest RC6 Enabled: %s\n", | |
1322 | yesno(rcctl1 & GEN6_RC_CTL_RC6pp_ENABLE)); | |
267f0c90 | 1323 | seq_puts(m, "Current RC state: "); |
4d85529d BW |
1324 | switch (gt_core_status & GEN6_RCn_MASK) { |
1325 | case GEN6_RC0: | |
1326 | if (gt_core_status & GEN6_CORE_CPD_STATE_MASK) | |
267f0c90 | 1327 | seq_puts(m, "Core Power Down\n"); |
4d85529d | 1328 | else |
267f0c90 | 1329 | seq_puts(m, "on\n"); |
4d85529d BW |
1330 | break; |
1331 | case GEN6_RC3: | |
267f0c90 | 1332 | seq_puts(m, "RC3\n"); |
4d85529d BW |
1333 | break; |
1334 | case GEN6_RC6: | |
267f0c90 | 1335 | seq_puts(m, "RC6\n"); |
4d85529d BW |
1336 | break; |
1337 | case GEN6_RC7: | |
267f0c90 | 1338 | seq_puts(m, "RC7\n"); |
4d85529d BW |
1339 | break; |
1340 | default: | |
267f0c90 | 1341 | seq_puts(m, "Unknown\n"); |
4d85529d BW |
1342 | break; |
1343 | } | |
1344 | ||
1345 | seq_printf(m, "Core Power Down: %s\n", | |
1346 | yesno(gt_core_status & GEN6_CORE_CPD_STATE_MASK)); | |
cce66a28 BW |
1347 | |
1348 | /* Not exactly sure what this is */ | |
1349 | seq_printf(m, "RC6 \"Locked to RPn\" residency since boot: %u\n", | |
1350 | I915_READ(GEN6_GT_GFX_RC6_LOCKED)); | |
1351 | seq_printf(m, "RC6 residency since boot: %u\n", | |
1352 | I915_READ(GEN6_GT_GFX_RC6)); | |
1353 | seq_printf(m, "RC6+ residency since boot: %u\n", | |
1354 | I915_READ(GEN6_GT_GFX_RC6p)); | |
1355 | seq_printf(m, "RC6++ residency since boot: %u\n", | |
1356 | I915_READ(GEN6_GT_GFX_RC6pp)); | |
1357 | ||
ecd8faea BW |
1358 | seq_printf(m, "RC6 voltage: %dmV\n", |
1359 | GEN6_DECODE_RC6_VID(((rc6vids >> 0) & 0xff))); | |
1360 | seq_printf(m, "RC6+ voltage: %dmV\n", | |
1361 | GEN6_DECODE_RC6_VID(((rc6vids >> 8) & 0xff))); | |
1362 | seq_printf(m, "RC6++ voltage: %dmV\n", | |
1363 | GEN6_DECODE_RC6_VID(((rc6vids >> 16) & 0xff))); | |
4d85529d BW |
1364 | return 0; |
1365 | } | |
1366 | ||
1367 | static int i915_drpc_info(struct seq_file *m, void *unused) | |
1368 | { | |
9f25d007 | 1369 | struct drm_info_node *node = m->private; |
4d85529d BW |
1370 | struct drm_device *dev = node->minor->dev; |
1371 | ||
669ab5aa D |
1372 | if (IS_VALLEYVIEW(dev)) |
1373 | return vlv_drpc_info(m); | |
1374 | else if (IS_GEN6(dev) || IS_GEN7(dev)) | |
4d85529d BW |
1375 | return gen6_drpc_info(m); |
1376 | else | |
1377 | return ironlake_drpc_info(m); | |
1378 | } | |
1379 | ||
b5e50c3f JB |
1380 | static int i915_fbc_status(struct seq_file *m, void *unused) |
1381 | { | |
9f25d007 | 1382 | struct drm_info_node *node = m->private; |
b5e50c3f | 1383 | struct drm_device *dev = node->minor->dev; |
e277a1f8 | 1384 | struct drm_i915_private *dev_priv = dev->dev_private; |
b5e50c3f | 1385 | |
3a77c4c4 | 1386 | if (!HAS_FBC(dev)) { |
267f0c90 | 1387 | seq_puts(m, "FBC unsupported on this chipset\n"); |
b5e50c3f JB |
1388 | return 0; |
1389 | } | |
1390 | ||
36623ef8 PZ |
1391 | intel_runtime_pm_get(dev_priv); |
1392 | ||
ee5382ae | 1393 | if (intel_fbc_enabled(dev)) { |
267f0c90 | 1394 | seq_puts(m, "FBC enabled\n"); |
b5e50c3f | 1395 | } else { |
267f0c90 | 1396 | seq_puts(m, "FBC disabled: "); |
5c3fe8b0 | 1397 | switch (dev_priv->fbc.no_fbc_reason) { |
29ebf90f CW |
1398 | case FBC_OK: |
1399 | seq_puts(m, "FBC actived, but currently disabled in hardware"); | |
1400 | break; | |
1401 | case FBC_UNSUPPORTED: | |
1402 | seq_puts(m, "unsupported by this chipset"); | |
1403 | break; | |
bed4a673 | 1404 | case FBC_NO_OUTPUT: |
267f0c90 | 1405 | seq_puts(m, "no outputs"); |
bed4a673 | 1406 | break; |
b5e50c3f | 1407 | case FBC_STOLEN_TOO_SMALL: |
267f0c90 | 1408 | seq_puts(m, "not enough stolen memory"); |
b5e50c3f JB |
1409 | break; |
1410 | case FBC_UNSUPPORTED_MODE: | |
267f0c90 | 1411 | seq_puts(m, "mode not supported"); |
b5e50c3f JB |
1412 | break; |
1413 | case FBC_MODE_TOO_LARGE: | |
267f0c90 | 1414 | seq_puts(m, "mode too large"); |
b5e50c3f JB |
1415 | break; |
1416 | case FBC_BAD_PLANE: | |
267f0c90 | 1417 | seq_puts(m, "FBC unsupported on plane"); |
b5e50c3f JB |
1418 | break; |
1419 | case FBC_NOT_TILED: | |
267f0c90 | 1420 | seq_puts(m, "scanout buffer not tiled"); |
b5e50c3f | 1421 | break; |
9c928d16 | 1422 | case FBC_MULTIPLE_PIPES: |
267f0c90 | 1423 | seq_puts(m, "multiple pipes are enabled"); |
9c928d16 | 1424 | break; |
c1a9f047 | 1425 | case FBC_MODULE_PARAM: |
267f0c90 | 1426 | seq_puts(m, "disabled per module param (default off)"); |
c1a9f047 | 1427 | break; |
8a5729a3 | 1428 | case FBC_CHIP_DEFAULT: |
267f0c90 | 1429 | seq_puts(m, "disabled per chip default"); |
8a5729a3 | 1430 | break; |
b5e50c3f | 1431 | default: |
267f0c90 | 1432 | seq_puts(m, "unknown reason"); |
b5e50c3f | 1433 | } |
267f0c90 | 1434 | seq_putc(m, '\n'); |
b5e50c3f | 1435 | } |
36623ef8 PZ |
1436 | |
1437 | intel_runtime_pm_put(dev_priv); | |
1438 | ||
b5e50c3f JB |
1439 | return 0; |
1440 | } | |
1441 | ||
da46f936 RV |
1442 | static int i915_fbc_fc_get(void *data, u64 *val) |
1443 | { | |
1444 | struct drm_device *dev = data; | |
1445 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1446 | ||
1447 | if (INTEL_INFO(dev)->gen < 7 || !HAS_FBC(dev)) | |
1448 | return -ENODEV; | |
1449 | ||
1450 | drm_modeset_lock_all(dev); | |
1451 | *val = dev_priv->fbc.false_color; | |
1452 | drm_modeset_unlock_all(dev); | |
1453 | ||
1454 | return 0; | |
1455 | } | |
1456 | ||
1457 | static int i915_fbc_fc_set(void *data, u64 val) | |
1458 | { | |
1459 | struct drm_device *dev = data; | |
1460 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1461 | u32 reg; | |
1462 | ||
1463 | if (INTEL_INFO(dev)->gen < 7 || !HAS_FBC(dev)) | |
1464 | return -ENODEV; | |
1465 | ||
1466 | drm_modeset_lock_all(dev); | |
1467 | ||
1468 | reg = I915_READ(ILK_DPFC_CONTROL); | |
1469 | dev_priv->fbc.false_color = val; | |
1470 | ||
1471 | I915_WRITE(ILK_DPFC_CONTROL, val ? | |
1472 | (reg | FBC_CTL_FALSE_COLOR) : | |
1473 | (reg & ~FBC_CTL_FALSE_COLOR)); | |
1474 | ||
1475 | drm_modeset_unlock_all(dev); | |
1476 | return 0; | |
1477 | } | |
1478 | ||
1479 | DEFINE_SIMPLE_ATTRIBUTE(i915_fbc_fc_fops, | |
1480 | i915_fbc_fc_get, i915_fbc_fc_set, | |
1481 | "%llu\n"); | |
1482 | ||
92d44621 PZ |
1483 | static int i915_ips_status(struct seq_file *m, void *unused) |
1484 | { | |
9f25d007 | 1485 | struct drm_info_node *node = m->private; |
92d44621 PZ |
1486 | struct drm_device *dev = node->minor->dev; |
1487 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1488 | ||
f5adf94e | 1489 | if (!HAS_IPS(dev)) { |
92d44621 PZ |
1490 | seq_puts(m, "not supported\n"); |
1491 | return 0; | |
1492 | } | |
1493 | ||
36623ef8 PZ |
1494 | intel_runtime_pm_get(dev_priv); |
1495 | ||
0eaa53f0 RV |
1496 | seq_printf(m, "Enabled by kernel parameter: %s\n", |
1497 | yesno(i915.enable_ips)); | |
1498 | ||
1499 | if (INTEL_INFO(dev)->gen >= 8) { | |
1500 | seq_puts(m, "Currently: unknown\n"); | |
1501 | } else { | |
1502 | if (I915_READ(IPS_CTL) & IPS_ENABLE) | |
1503 | seq_puts(m, "Currently: enabled\n"); | |
1504 | else | |
1505 | seq_puts(m, "Currently: disabled\n"); | |
1506 | } | |
92d44621 | 1507 | |
36623ef8 PZ |
1508 | intel_runtime_pm_put(dev_priv); |
1509 | ||
92d44621 PZ |
1510 | return 0; |
1511 | } | |
1512 | ||
4a9bef37 JB |
1513 | static int i915_sr_status(struct seq_file *m, void *unused) |
1514 | { | |
9f25d007 | 1515 | struct drm_info_node *node = m->private; |
4a9bef37 | 1516 | struct drm_device *dev = node->minor->dev; |
e277a1f8 | 1517 | struct drm_i915_private *dev_priv = dev->dev_private; |
4a9bef37 JB |
1518 | bool sr_enabled = false; |
1519 | ||
36623ef8 PZ |
1520 | intel_runtime_pm_get(dev_priv); |
1521 | ||
1398261a | 1522 | if (HAS_PCH_SPLIT(dev)) |
5ba2aaaa | 1523 | sr_enabled = I915_READ(WM1_LP_ILK) & WM1_LP_SR_EN; |
a6c45cf0 | 1524 | else if (IS_CRESTLINE(dev) || IS_I945G(dev) || IS_I945GM(dev)) |
4a9bef37 JB |
1525 | sr_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN; |
1526 | else if (IS_I915GM(dev)) | |
1527 | sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN; | |
1528 | else if (IS_PINEVIEW(dev)) | |
1529 | sr_enabled = I915_READ(DSPFW3) & PINEVIEW_SELF_REFRESH_EN; | |
1530 | ||
36623ef8 PZ |
1531 | intel_runtime_pm_put(dev_priv); |
1532 | ||
5ba2aaaa CW |
1533 | seq_printf(m, "self-refresh: %s\n", |
1534 | sr_enabled ? "enabled" : "disabled"); | |
4a9bef37 JB |
1535 | |
1536 | return 0; | |
1537 | } | |
1538 | ||
7648fa99 JB |
1539 | static int i915_emon_status(struct seq_file *m, void *unused) |
1540 | { | |
9f25d007 | 1541 | struct drm_info_node *node = m->private; |
7648fa99 | 1542 | struct drm_device *dev = node->minor->dev; |
e277a1f8 | 1543 | struct drm_i915_private *dev_priv = dev->dev_private; |
7648fa99 | 1544 | unsigned long temp, chipset, gfx; |
de227ef0 CW |
1545 | int ret; |
1546 | ||
582be6b4 CW |
1547 | if (!IS_GEN5(dev)) |
1548 | return -ENODEV; | |
1549 | ||
de227ef0 CW |
1550 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
1551 | if (ret) | |
1552 | return ret; | |
7648fa99 JB |
1553 | |
1554 | temp = i915_mch_val(dev_priv); | |
1555 | chipset = i915_chipset_val(dev_priv); | |
1556 | gfx = i915_gfx_val(dev_priv); | |
de227ef0 | 1557 | mutex_unlock(&dev->struct_mutex); |
7648fa99 JB |
1558 | |
1559 | seq_printf(m, "GMCH temp: %ld\n", temp); | |
1560 | seq_printf(m, "Chipset power: %ld\n", chipset); | |
1561 | seq_printf(m, "GFX power: %ld\n", gfx); | |
1562 | seq_printf(m, "Total power: %ld\n", chipset + gfx); | |
1563 | ||
1564 | return 0; | |
1565 | } | |
1566 | ||
23b2f8bb JB |
1567 | static int i915_ring_freq_table(struct seq_file *m, void *unused) |
1568 | { | |
9f25d007 | 1569 | struct drm_info_node *node = m->private; |
23b2f8bb | 1570 | struct drm_device *dev = node->minor->dev; |
e277a1f8 | 1571 | struct drm_i915_private *dev_priv = dev->dev_private; |
5bfa0199 | 1572 | int ret = 0; |
23b2f8bb JB |
1573 | int gpu_freq, ia_freq; |
1574 | ||
1c70c0ce | 1575 | if (!(IS_GEN6(dev) || IS_GEN7(dev))) { |
267f0c90 | 1576 | seq_puts(m, "unsupported on this chipset\n"); |
23b2f8bb JB |
1577 | return 0; |
1578 | } | |
1579 | ||
5bfa0199 PZ |
1580 | intel_runtime_pm_get(dev_priv); |
1581 | ||
5c9669ce TR |
1582 | flush_delayed_work(&dev_priv->rps.delayed_resume_work); |
1583 | ||
4fc688ce | 1584 | ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock); |
23b2f8bb | 1585 | if (ret) |
5bfa0199 | 1586 | goto out; |
23b2f8bb | 1587 | |
267f0c90 | 1588 | seq_puts(m, "GPU freq (MHz)\tEffective CPU freq (MHz)\tEffective Ring freq (MHz)\n"); |
23b2f8bb | 1589 | |
b39fb297 BW |
1590 | for (gpu_freq = dev_priv->rps.min_freq_softlimit; |
1591 | gpu_freq <= dev_priv->rps.max_freq_softlimit; | |
23b2f8bb | 1592 | gpu_freq++) { |
42c0526c BW |
1593 | ia_freq = gpu_freq; |
1594 | sandybridge_pcode_read(dev_priv, | |
1595 | GEN6_PCODE_READ_MIN_FREQ_TABLE, | |
1596 | &ia_freq); | |
3ebecd07 CW |
1597 | seq_printf(m, "%d\t\t%d\t\t\t\t%d\n", |
1598 | gpu_freq * GT_FREQUENCY_MULTIPLIER, | |
1599 | ((ia_freq >> 0) & 0xff) * 100, | |
1600 | ((ia_freq >> 8) & 0xff) * 100); | |
23b2f8bb JB |
1601 | } |
1602 | ||
4fc688ce | 1603 | mutex_unlock(&dev_priv->rps.hw_lock); |
23b2f8bb | 1604 | |
5bfa0199 PZ |
1605 | out: |
1606 | intel_runtime_pm_put(dev_priv); | |
1607 | return ret; | |
23b2f8bb JB |
1608 | } |
1609 | ||
44834a67 CW |
1610 | static int i915_opregion(struct seq_file *m, void *unused) |
1611 | { | |
9f25d007 | 1612 | struct drm_info_node *node = m->private; |
44834a67 | 1613 | struct drm_device *dev = node->minor->dev; |
e277a1f8 | 1614 | struct drm_i915_private *dev_priv = dev->dev_private; |
44834a67 | 1615 | struct intel_opregion *opregion = &dev_priv->opregion; |
0d38f009 | 1616 | void *data = kmalloc(OPREGION_SIZE, GFP_KERNEL); |
44834a67 CW |
1617 | int ret; |
1618 | ||
0d38f009 DV |
1619 | if (data == NULL) |
1620 | return -ENOMEM; | |
1621 | ||
44834a67 CW |
1622 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
1623 | if (ret) | |
0d38f009 | 1624 | goto out; |
44834a67 | 1625 | |
0d38f009 DV |
1626 | if (opregion->header) { |
1627 | memcpy_fromio(data, opregion->header, OPREGION_SIZE); | |
1628 | seq_write(m, data, OPREGION_SIZE); | |
1629 | } | |
44834a67 CW |
1630 | |
1631 | mutex_unlock(&dev->struct_mutex); | |
1632 | ||
0d38f009 DV |
1633 | out: |
1634 | kfree(data); | |
44834a67 CW |
1635 | return 0; |
1636 | } | |
1637 | ||
37811fcc CW |
1638 | static int i915_gem_framebuffer_info(struct seq_file *m, void *data) |
1639 | { | |
9f25d007 | 1640 | struct drm_info_node *node = m->private; |
37811fcc | 1641 | struct drm_device *dev = node->minor->dev; |
4520f53a | 1642 | struct intel_fbdev *ifbdev = NULL; |
37811fcc | 1643 | struct intel_framebuffer *fb; |
37811fcc | 1644 | |
4520f53a DV |
1645 | #ifdef CONFIG_DRM_I915_FBDEV |
1646 | struct drm_i915_private *dev_priv = dev->dev_private; | |
37811fcc CW |
1647 | |
1648 | ifbdev = dev_priv->fbdev; | |
1649 | fb = to_intel_framebuffer(ifbdev->helper.fb); | |
1650 | ||
623f9783 | 1651 | seq_printf(m, "fbcon size: %d x %d, depth %d, %d bpp, refcount %d, obj ", |
37811fcc CW |
1652 | fb->base.width, |
1653 | fb->base.height, | |
1654 | fb->base.depth, | |
623f9783 DV |
1655 | fb->base.bits_per_pixel, |
1656 | atomic_read(&fb->base.refcount.refcount)); | |
05394f39 | 1657 | describe_obj(m, fb->obj); |
267f0c90 | 1658 | seq_putc(m, '\n'); |
4520f53a | 1659 | #endif |
37811fcc | 1660 | |
4b096ac1 | 1661 | mutex_lock(&dev->mode_config.fb_lock); |
37811fcc | 1662 | list_for_each_entry(fb, &dev->mode_config.fb_list, base.head) { |
131a56dc | 1663 | if (ifbdev && &fb->base == ifbdev->helper.fb) |
37811fcc CW |
1664 | continue; |
1665 | ||
623f9783 | 1666 | seq_printf(m, "user size: %d x %d, depth %d, %d bpp, refcount %d, obj ", |
37811fcc CW |
1667 | fb->base.width, |
1668 | fb->base.height, | |
1669 | fb->base.depth, | |
623f9783 DV |
1670 | fb->base.bits_per_pixel, |
1671 | atomic_read(&fb->base.refcount.refcount)); | |
05394f39 | 1672 | describe_obj(m, fb->obj); |
267f0c90 | 1673 | seq_putc(m, '\n'); |
37811fcc | 1674 | } |
4b096ac1 | 1675 | mutex_unlock(&dev->mode_config.fb_lock); |
37811fcc CW |
1676 | |
1677 | return 0; | |
1678 | } | |
1679 | ||
e76d3630 BW |
1680 | static int i915_context_status(struct seq_file *m, void *unused) |
1681 | { | |
9f25d007 | 1682 | struct drm_info_node *node = m->private; |
e76d3630 | 1683 | struct drm_device *dev = node->minor->dev; |
e277a1f8 | 1684 | struct drm_i915_private *dev_priv = dev->dev_private; |
a4872ba6 | 1685 | struct intel_engine_cs *ring; |
273497e5 | 1686 | struct intel_context *ctx; |
a168c293 | 1687 | int ret, i; |
e76d3630 | 1688 | |
f3d28878 | 1689 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
e76d3630 BW |
1690 | if (ret) |
1691 | return ret; | |
1692 | ||
3e373948 | 1693 | if (dev_priv->ips.pwrctx) { |
267f0c90 | 1694 | seq_puts(m, "power context "); |
3e373948 | 1695 | describe_obj(m, dev_priv->ips.pwrctx); |
267f0c90 | 1696 | seq_putc(m, '\n'); |
dc501fbc | 1697 | } |
e76d3630 | 1698 | |
3e373948 | 1699 | if (dev_priv->ips.renderctx) { |
267f0c90 | 1700 | seq_puts(m, "render context "); |
3e373948 | 1701 | describe_obj(m, dev_priv->ips.renderctx); |
267f0c90 | 1702 | seq_putc(m, '\n'); |
dc501fbc | 1703 | } |
e76d3630 | 1704 | |
a33afea5 | 1705 | list_for_each_entry(ctx, &dev_priv->context_list, link) { |
ea0c76f8 | 1706 | if (ctx->legacy_hw_ctx.rcs_state == NULL) |
b77f6997 CW |
1707 | continue; |
1708 | ||
a33afea5 | 1709 | seq_puts(m, "HW context "); |
3ccfd19d | 1710 | describe_ctx(m, ctx); |
a33afea5 BW |
1711 | for_each_ring(ring, dev_priv, i) |
1712 | if (ring->default_context == ctx) | |
1713 | seq_printf(m, "(default context %s) ", ring->name); | |
1714 | ||
ea0c76f8 | 1715 | describe_obj(m, ctx->legacy_hw_ctx.rcs_state); |
a33afea5 | 1716 | seq_putc(m, '\n'); |
a168c293 BW |
1717 | } |
1718 | ||
f3d28878 | 1719 | mutex_unlock(&dev->struct_mutex); |
e76d3630 BW |
1720 | |
1721 | return 0; | |
1722 | } | |
1723 | ||
6d794d42 BW |
1724 | static int i915_gen6_forcewake_count_info(struct seq_file *m, void *data) |
1725 | { | |
9f25d007 | 1726 | struct drm_info_node *node = m->private; |
6d794d42 BW |
1727 | struct drm_device *dev = node->minor->dev; |
1728 | struct drm_i915_private *dev_priv = dev->dev_private; | |
43709ba0 | 1729 | unsigned forcewake_count = 0, fw_rendercount = 0, fw_mediacount = 0; |
6d794d42 | 1730 | |
907b28c5 | 1731 | spin_lock_irq(&dev_priv->uncore.lock); |
43709ba0 D |
1732 | if (IS_VALLEYVIEW(dev)) { |
1733 | fw_rendercount = dev_priv->uncore.fw_rendercount; | |
1734 | fw_mediacount = dev_priv->uncore.fw_mediacount; | |
1735 | } else | |
1736 | forcewake_count = dev_priv->uncore.forcewake_count; | |
907b28c5 | 1737 | spin_unlock_irq(&dev_priv->uncore.lock); |
6d794d42 | 1738 | |
43709ba0 D |
1739 | if (IS_VALLEYVIEW(dev)) { |
1740 | seq_printf(m, "fw_rendercount = %u\n", fw_rendercount); | |
1741 | seq_printf(m, "fw_mediacount = %u\n", fw_mediacount); | |
1742 | } else | |
1743 | seq_printf(m, "forcewake count = %u\n", forcewake_count); | |
6d794d42 BW |
1744 | |
1745 | return 0; | |
1746 | } | |
1747 | ||
ea16a3cd DV |
1748 | static const char *swizzle_string(unsigned swizzle) |
1749 | { | |
aee56cff | 1750 | switch (swizzle) { |
ea16a3cd DV |
1751 | case I915_BIT_6_SWIZZLE_NONE: |
1752 | return "none"; | |
1753 | case I915_BIT_6_SWIZZLE_9: | |
1754 | return "bit9"; | |
1755 | case I915_BIT_6_SWIZZLE_9_10: | |
1756 | return "bit9/bit10"; | |
1757 | case I915_BIT_6_SWIZZLE_9_11: | |
1758 | return "bit9/bit11"; | |
1759 | case I915_BIT_6_SWIZZLE_9_10_11: | |
1760 | return "bit9/bit10/bit11"; | |
1761 | case I915_BIT_6_SWIZZLE_9_17: | |
1762 | return "bit9/bit17"; | |
1763 | case I915_BIT_6_SWIZZLE_9_10_17: | |
1764 | return "bit9/bit10/bit17"; | |
1765 | case I915_BIT_6_SWIZZLE_UNKNOWN: | |
8a168ca7 | 1766 | return "unknown"; |
ea16a3cd DV |
1767 | } |
1768 | ||
1769 | return "bug"; | |
1770 | } | |
1771 | ||
1772 | static int i915_swizzle_info(struct seq_file *m, void *data) | |
1773 | { | |
9f25d007 | 1774 | struct drm_info_node *node = m->private; |
ea16a3cd DV |
1775 | struct drm_device *dev = node->minor->dev; |
1776 | struct drm_i915_private *dev_priv = dev->dev_private; | |
22bcfc6a DV |
1777 | int ret; |
1778 | ||
1779 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
1780 | if (ret) | |
1781 | return ret; | |
c8c8fb33 | 1782 | intel_runtime_pm_get(dev_priv); |
ea16a3cd | 1783 | |
ea16a3cd DV |
1784 | seq_printf(m, "bit6 swizzle for X-tiling = %s\n", |
1785 | swizzle_string(dev_priv->mm.bit_6_swizzle_x)); | |
1786 | seq_printf(m, "bit6 swizzle for Y-tiling = %s\n", | |
1787 | swizzle_string(dev_priv->mm.bit_6_swizzle_y)); | |
1788 | ||
1789 | if (IS_GEN3(dev) || IS_GEN4(dev)) { | |
1790 | seq_printf(m, "DDC = 0x%08x\n", | |
1791 | I915_READ(DCC)); | |
1792 | seq_printf(m, "C0DRB3 = 0x%04x\n", | |
1793 | I915_READ16(C0DRB3)); | |
1794 | seq_printf(m, "C1DRB3 = 0x%04x\n", | |
1795 | I915_READ16(C1DRB3)); | |
9d3203e1 | 1796 | } else if (INTEL_INFO(dev)->gen >= 6) { |
3fa7d235 DV |
1797 | seq_printf(m, "MAD_DIMM_C0 = 0x%08x\n", |
1798 | I915_READ(MAD_DIMM_C0)); | |
1799 | seq_printf(m, "MAD_DIMM_C1 = 0x%08x\n", | |
1800 | I915_READ(MAD_DIMM_C1)); | |
1801 | seq_printf(m, "MAD_DIMM_C2 = 0x%08x\n", | |
1802 | I915_READ(MAD_DIMM_C2)); | |
1803 | seq_printf(m, "TILECTL = 0x%08x\n", | |
1804 | I915_READ(TILECTL)); | |
9d3203e1 BW |
1805 | if (IS_GEN8(dev)) |
1806 | seq_printf(m, "GAMTARBMODE = 0x%08x\n", | |
1807 | I915_READ(GAMTARBMODE)); | |
1808 | else | |
1809 | seq_printf(m, "ARB_MODE = 0x%08x\n", | |
1810 | I915_READ(ARB_MODE)); | |
3fa7d235 DV |
1811 | seq_printf(m, "DISP_ARB_CTL = 0x%08x\n", |
1812 | I915_READ(DISP_ARB_CTL)); | |
ea16a3cd | 1813 | } |
c8c8fb33 | 1814 | intel_runtime_pm_put(dev_priv); |
ea16a3cd DV |
1815 | mutex_unlock(&dev->struct_mutex); |
1816 | ||
1817 | return 0; | |
1818 | } | |
1819 | ||
1c60fef5 BW |
1820 | static int per_file_ctx(int id, void *ptr, void *data) |
1821 | { | |
273497e5 | 1822 | struct intel_context *ctx = ptr; |
1c60fef5 BW |
1823 | struct seq_file *m = data; |
1824 | struct i915_hw_ppgtt *ppgtt = ctx_to_ppgtt(ctx); | |
1825 | ||
f83d6518 OM |
1826 | if (i915_gem_context_is_default(ctx)) |
1827 | seq_puts(m, " default context:\n"); | |
1828 | else | |
821d66dd | 1829 | seq_printf(m, " context %d:\n", ctx->user_handle); |
1c60fef5 BW |
1830 | ppgtt->debug_dump(ppgtt, m); |
1831 | ||
1832 | return 0; | |
1833 | } | |
1834 | ||
77df6772 | 1835 | static void gen8_ppgtt_info(struct seq_file *m, struct drm_device *dev) |
3cf17fc5 | 1836 | { |
3cf17fc5 | 1837 | struct drm_i915_private *dev_priv = dev->dev_private; |
a4872ba6 | 1838 | struct intel_engine_cs *ring; |
77df6772 BW |
1839 | struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt; |
1840 | int unused, i; | |
3cf17fc5 | 1841 | |
77df6772 BW |
1842 | if (!ppgtt) |
1843 | return; | |
1844 | ||
1845 | seq_printf(m, "Page directories: %d\n", ppgtt->num_pd_pages); | |
5abbcca3 | 1846 | seq_printf(m, "Page tables: %d\n", ppgtt->num_pd_entries); |
77df6772 BW |
1847 | for_each_ring(ring, dev_priv, unused) { |
1848 | seq_printf(m, "%s\n", ring->name); | |
1849 | for (i = 0; i < 4; i++) { | |
1850 | u32 offset = 0x270 + i * 8; | |
1851 | u64 pdp = I915_READ(ring->mmio_base + offset + 4); | |
1852 | pdp <<= 32; | |
1853 | pdp |= I915_READ(ring->mmio_base + offset); | |
a2a5b15c | 1854 | seq_printf(m, "\tPDP%d 0x%016llx\n", i, pdp); |
77df6772 BW |
1855 | } |
1856 | } | |
1857 | } | |
1858 | ||
1859 | static void gen6_ppgtt_info(struct seq_file *m, struct drm_device *dev) | |
1860 | { | |
1861 | struct drm_i915_private *dev_priv = dev->dev_private; | |
a4872ba6 | 1862 | struct intel_engine_cs *ring; |
1c60fef5 | 1863 | struct drm_file *file; |
77df6772 | 1864 | int i; |
3cf17fc5 | 1865 | |
3cf17fc5 DV |
1866 | if (INTEL_INFO(dev)->gen == 6) |
1867 | seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(GFX_MODE)); | |
1868 | ||
a2c7f6fd | 1869 | for_each_ring(ring, dev_priv, i) { |
3cf17fc5 DV |
1870 | seq_printf(m, "%s\n", ring->name); |
1871 | if (INTEL_INFO(dev)->gen == 7) | |
1872 | seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(RING_MODE_GEN7(ring))); | |
1873 | seq_printf(m, "PP_DIR_BASE: 0x%08x\n", I915_READ(RING_PP_DIR_BASE(ring))); | |
1874 | seq_printf(m, "PP_DIR_BASE_READ: 0x%08x\n", I915_READ(RING_PP_DIR_BASE_READ(ring))); | |
1875 | seq_printf(m, "PP_DIR_DCLV: 0x%08x\n", I915_READ(RING_PP_DIR_DCLV(ring))); | |
1876 | } | |
1877 | if (dev_priv->mm.aliasing_ppgtt) { | |
1878 | struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt; | |
1879 | ||
267f0c90 | 1880 | seq_puts(m, "aliasing PPGTT:\n"); |
3cf17fc5 | 1881 | seq_printf(m, "pd gtt offset: 0x%08x\n", ppgtt->pd_offset); |
1c60fef5 | 1882 | |
87d60b63 | 1883 | ppgtt->debug_dump(ppgtt, m); |
1c60fef5 BW |
1884 | } else |
1885 | return; | |
1886 | ||
1887 | list_for_each_entry_reverse(file, &dev->filelist, lhead) { | |
1888 | struct drm_i915_file_private *file_priv = file->driver_priv; | |
1c60fef5 | 1889 | |
1c60fef5 BW |
1890 | seq_printf(m, "proc: %s\n", |
1891 | get_pid_task(file->pid, PIDTYPE_PID)->comm); | |
1c60fef5 | 1892 | idr_for_each(&file_priv->context_idr, per_file_ctx, m); |
3cf17fc5 DV |
1893 | } |
1894 | seq_printf(m, "ECOCHK: 0x%08x\n", I915_READ(GAM_ECOCHK)); | |
77df6772 BW |
1895 | } |
1896 | ||
1897 | static int i915_ppgtt_info(struct seq_file *m, void *data) | |
1898 | { | |
9f25d007 | 1899 | struct drm_info_node *node = m->private; |
77df6772 | 1900 | struct drm_device *dev = node->minor->dev; |
c8c8fb33 | 1901 | struct drm_i915_private *dev_priv = dev->dev_private; |
77df6772 BW |
1902 | |
1903 | int ret = mutex_lock_interruptible(&dev->struct_mutex); | |
1904 | if (ret) | |
1905 | return ret; | |
c8c8fb33 | 1906 | intel_runtime_pm_get(dev_priv); |
77df6772 BW |
1907 | |
1908 | if (INTEL_INFO(dev)->gen >= 8) | |
1909 | gen8_ppgtt_info(m, dev); | |
1910 | else if (INTEL_INFO(dev)->gen >= 6) | |
1911 | gen6_ppgtt_info(m, dev); | |
1912 | ||
c8c8fb33 | 1913 | intel_runtime_pm_put(dev_priv); |
3cf17fc5 DV |
1914 | mutex_unlock(&dev->struct_mutex); |
1915 | ||
1916 | return 0; | |
1917 | } | |
1918 | ||
63573eb7 BW |
1919 | static int i915_llc(struct seq_file *m, void *data) |
1920 | { | |
9f25d007 | 1921 | struct drm_info_node *node = m->private; |
63573eb7 BW |
1922 | struct drm_device *dev = node->minor->dev; |
1923 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1924 | ||
1925 | /* Size calculation for LLC is a bit of a pain. Ignore for now. */ | |
1926 | seq_printf(m, "LLC: %s\n", yesno(HAS_LLC(dev))); | |
1927 | seq_printf(m, "eLLC: %zuMB\n", dev_priv->ellc_size); | |
1928 | ||
1929 | return 0; | |
1930 | } | |
1931 | ||
e91fd8c6 RV |
1932 | static int i915_edp_psr_status(struct seq_file *m, void *data) |
1933 | { | |
1934 | struct drm_info_node *node = m->private; | |
1935 | struct drm_device *dev = node->minor->dev; | |
1936 | struct drm_i915_private *dev_priv = dev->dev_private; | |
a031d709 RV |
1937 | u32 psrperf = 0; |
1938 | bool enabled = false; | |
e91fd8c6 | 1939 | |
c8c8fb33 PZ |
1940 | intel_runtime_pm_get(dev_priv); |
1941 | ||
fa128fa6 | 1942 | mutex_lock(&dev_priv->psr.lock); |
a031d709 RV |
1943 | seq_printf(m, "Sink_Support: %s\n", yesno(dev_priv->psr.sink_support)); |
1944 | seq_printf(m, "Source_OK: %s\n", yesno(dev_priv->psr.source_ok)); | |
2807cf69 | 1945 | seq_printf(m, "Enabled: %s\n", yesno((bool)dev_priv->psr.enabled)); |
5755c78f | 1946 | seq_printf(m, "Active: %s\n", yesno(dev_priv->psr.active)); |
fa128fa6 DV |
1947 | seq_printf(m, "Busy frontbuffer bits: 0x%03x\n", |
1948 | dev_priv->psr.busy_frontbuffer_bits); | |
1949 | seq_printf(m, "Re-enable work scheduled: %s\n", | |
1950 | yesno(work_busy(&dev_priv->psr.work.work))); | |
e91fd8c6 | 1951 | |
a031d709 RV |
1952 | enabled = HAS_PSR(dev) && |
1953 | I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE; | |
5755c78f | 1954 | seq_printf(m, "HW Enabled & Active bit: %s\n", yesno(enabled)); |
e91fd8c6 | 1955 | |
a031d709 RV |
1956 | if (HAS_PSR(dev)) |
1957 | psrperf = I915_READ(EDP_PSR_PERF_CNT(dev)) & | |
1958 | EDP_PSR_PERF_CNT_MASK; | |
1959 | seq_printf(m, "Performance_Counter: %u\n", psrperf); | |
fa128fa6 | 1960 | mutex_unlock(&dev_priv->psr.lock); |
e91fd8c6 | 1961 | |
c8c8fb33 | 1962 | intel_runtime_pm_put(dev_priv); |
e91fd8c6 RV |
1963 | return 0; |
1964 | } | |
1965 | ||
d2e216d0 RV |
1966 | static int i915_sink_crc(struct seq_file *m, void *data) |
1967 | { | |
1968 | struct drm_info_node *node = m->private; | |
1969 | struct drm_device *dev = node->minor->dev; | |
1970 | struct intel_encoder *encoder; | |
1971 | struct intel_connector *connector; | |
1972 | struct intel_dp *intel_dp = NULL; | |
1973 | int ret; | |
1974 | u8 crc[6]; | |
1975 | ||
1976 | drm_modeset_lock_all(dev); | |
1977 | list_for_each_entry(connector, &dev->mode_config.connector_list, | |
1978 | base.head) { | |
1979 | ||
1980 | if (connector->base.dpms != DRM_MODE_DPMS_ON) | |
1981 | continue; | |
1982 | ||
b6ae3c7c PZ |
1983 | if (!connector->base.encoder) |
1984 | continue; | |
1985 | ||
d2e216d0 RV |
1986 | encoder = to_intel_encoder(connector->base.encoder); |
1987 | if (encoder->type != INTEL_OUTPUT_EDP) | |
1988 | continue; | |
1989 | ||
1990 | intel_dp = enc_to_intel_dp(&encoder->base); | |
1991 | ||
1992 | ret = intel_dp_sink_crc(intel_dp, crc); | |
1993 | if (ret) | |
1994 | goto out; | |
1995 | ||
1996 | seq_printf(m, "%02x%02x%02x%02x%02x%02x\n", | |
1997 | crc[0], crc[1], crc[2], | |
1998 | crc[3], crc[4], crc[5]); | |
1999 | goto out; | |
2000 | } | |
2001 | ret = -ENODEV; | |
2002 | out: | |
2003 | drm_modeset_unlock_all(dev); | |
2004 | return ret; | |
2005 | } | |
2006 | ||
ec013e7f JB |
2007 | static int i915_energy_uJ(struct seq_file *m, void *data) |
2008 | { | |
2009 | struct drm_info_node *node = m->private; | |
2010 | struct drm_device *dev = node->minor->dev; | |
2011 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2012 | u64 power; | |
2013 | u32 units; | |
2014 | ||
2015 | if (INTEL_INFO(dev)->gen < 6) | |
2016 | return -ENODEV; | |
2017 | ||
36623ef8 PZ |
2018 | intel_runtime_pm_get(dev_priv); |
2019 | ||
ec013e7f JB |
2020 | rdmsrl(MSR_RAPL_POWER_UNIT, power); |
2021 | power = (power & 0x1f00) >> 8; | |
2022 | units = 1000000 / (1 << power); /* convert to uJ */ | |
2023 | power = I915_READ(MCH_SECP_NRG_STTS); | |
2024 | power *= units; | |
2025 | ||
36623ef8 PZ |
2026 | intel_runtime_pm_put(dev_priv); |
2027 | ||
ec013e7f | 2028 | seq_printf(m, "%llu", (long long unsigned)power); |
371db66a PZ |
2029 | |
2030 | return 0; | |
2031 | } | |
2032 | ||
2033 | static int i915_pc8_status(struct seq_file *m, void *unused) | |
2034 | { | |
9f25d007 | 2035 | struct drm_info_node *node = m->private; |
371db66a PZ |
2036 | struct drm_device *dev = node->minor->dev; |
2037 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2038 | ||
85b8d5c2 | 2039 | if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) { |
371db66a PZ |
2040 | seq_puts(m, "not supported\n"); |
2041 | return 0; | |
2042 | } | |
2043 | ||
86c4ec0d | 2044 | seq_printf(m, "GPU idle: %s\n", yesno(!dev_priv->mm.busy)); |
371db66a | 2045 | seq_printf(m, "IRQs disabled: %s\n", |
9df7575f | 2046 | yesno(!intel_irqs_enabled(dev_priv))); |
371db66a | 2047 | |
ec013e7f JB |
2048 | return 0; |
2049 | } | |
2050 | ||
1da51581 ID |
2051 | static const char *power_domain_str(enum intel_display_power_domain domain) |
2052 | { | |
2053 | switch (domain) { | |
2054 | case POWER_DOMAIN_PIPE_A: | |
2055 | return "PIPE_A"; | |
2056 | case POWER_DOMAIN_PIPE_B: | |
2057 | return "PIPE_B"; | |
2058 | case POWER_DOMAIN_PIPE_C: | |
2059 | return "PIPE_C"; | |
2060 | case POWER_DOMAIN_PIPE_A_PANEL_FITTER: | |
2061 | return "PIPE_A_PANEL_FITTER"; | |
2062 | case POWER_DOMAIN_PIPE_B_PANEL_FITTER: | |
2063 | return "PIPE_B_PANEL_FITTER"; | |
2064 | case POWER_DOMAIN_PIPE_C_PANEL_FITTER: | |
2065 | return "PIPE_C_PANEL_FITTER"; | |
2066 | case POWER_DOMAIN_TRANSCODER_A: | |
2067 | return "TRANSCODER_A"; | |
2068 | case POWER_DOMAIN_TRANSCODER_B: | |
2069 | return "TRANSCODER_B"; | |
2070 | case POWER_DOMAIN_TRANSCODER_C: | |
2071 | return "TRANSCODER_C"; | |
2072 | case POWER_DOMAIN_TRANSCODER_EDP: | |
2073 | return "TRANSCODER_EDP"; | |
319be8ae ID |
2074 | case POWER_DOMAIN_PORT_DDI_A_2_LANES: |
2075 | return "PORT_DDI_A_2_LANES"; | |
2076 | case POWER_DOMAIN_PORT_DDI_A_4_LANES: | |
2077 | return "PORT_DDI_A_4_LANES"; | |
2078 | case POWER_DOMAIN_PORT_DDI_B_2_LANES: | |
2079 | return "PORT_DDI_B_2_LANES"; | |
2080 | case POWER_DOMAIN_PORT_DDI_B_4_LANES: | |
2081 | return "PORT_DDI_B_4_LANES"; | |
2082 | case POWER_DOMAIN_PORT_DDI_C_2_LANES: | |
2083 | return "PORT_DDI_C_2_LANES"; | |
2084 | case POWER_DOMAIN_PORT_DDI_C_4_LANES: | |
2085 | return "PORT_DDI_C_4_LANES"; | |
2086 | case POWER_DOMAIN_PORT_DDI_D_2_LANES: | |
2087 | return "PORT_DDI_D_2_LANES"; | |
2088 | case POWER_DOMAIN_PORT_DDI_D_4_LANES: | |
2089 | return "PORT_DDI_D_4_LANES"; | |
2090 | case POWER_DOMAIN_PORT_DSI: | |
2091 | return "PORT_DSI"; | |
2092 | case POWER_DOMAIN_PORT_CRT: | |
2093 | return "PORT_CRT"; | |
2094 | case POWER_DOMAIN_PORT_OTHER: | |
2095 | return "PORT_OTHER"; | |
1da51581 ID |
2096 | case POWER_DOMAIN_VGA: |
2097 | return "VGA"; | |
2098 | case POWER_DOMAIN_AUDIO: | |
2099 | return "AUDIO"; | |
bd2bb1b9 PZ |
2100 | case POWER_DOMAIN_PLLS: |
2101 | return "PLLS"; | |
1da51581 ID |
2102 | case POWER_DOMAIN_INIT: |
2103 | return "INIT"; | |
2104 | default: | |
2105 | WARN_ON(1); | |
2106 | return "?"; | |
2107 | } | |
2108 | } | |
2109 | ||
2110 | static int i915_power_domain_info(struct seq_file *m, void *unused) | |
2111 | { | |
9f25d007 | 2112 | struct drm_info_node *node = m->private; |
1da51581 ID |
2113 | struct drm_device *dev = node->minor->dev; |
2114 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2115 | struct i915_power_domains *power_domains = &dev_priv->power_domains; | |
2116 | int i; | |
2117 | ||
2118 | mutex_lock(&power_domains->lock); | |
2119 | ||
2120 | seq_printf(m, "%-25s %s\n", "Power well/domain", "Use count"); | |
2121 | for (i = 0; i < power_domains->power_well_count; i++) { | |
2122 | struct i915_power_well *power_well; | |
2123 | enum intel_display_power_domain power_domain; | |
2124 | ||
2125 | power_well = &power_domains->power_wells[i]; | |
2126 | seq_printf(m, "%-25s %d\n", power_well->name, | |
2127 | power_well->count); | |
2128 | ||
2129 | for (power_domain = 0; power_domain < POWER_DOMAIN_NUM; | |
2130 | power_domain++) { | |
2131 | if (!(BIT(power_domain) & power_well->domains)) | |
2132 | continue; | |
2133 | ||
2134 | seq_printf(m, " %-23s %d\n", | |
2135 | power_domain_str(power_domain), | |
2136 | power_domains->domain_use_count[power_domain]); | |
2137 | } | |
2138 | } | |
2139 | ||
2140 | mutex_unlock(&power_domains->lock); | |
2141 | ||
2142 | return 0; | |
2143 | } | |
2144 | ||
53f5e3ca JB |
2145 | static void intel_seq_print_mode(struct seq_file *m, int tabs, |
2146 | struct drm_display_mode *mode) | |
2147 | { | |
2148 | int i; | |
2149 | ||
2150 | for (i = 0; i < tabs; i++) | |
2151 | seq_putc(m, '\t'); | |
2152 | ||
2153 | seq_printf(m, "id %d:\"%s\" freq %d clock %d hdisp %d hss %d hse %d htot %d vdisp %d vss %d vse %d vtot %d type 0x%x flags 0x%x\n", | |
2154 | mode->base.id, mode->name, | |
2155 | mode->vrefresh, mode->clock, | |
2156 | mode->hdisplay, mode->hsync_start, | |
2157 | mode->hsync_end, mode->htotal, | |
2158 | mode->vdisplay, mode->vsync_start, | |
2159 | mode->vsync_end, mode->vtotal, | |
2160 | mode->type, mode->flags); | |
2161 | } | |
2162 | ||
2163 | static void intel_encoder_info(struct seq_file *m, | |
2164 | struct intel_crtc *intel_crtc, | |
2165 | struct intel_encoder *intel_encoder) | |
2166 | { | |
9f25d007 | 2167 | struct drm_info_node *node = m->private; |
53f5e3ca JB |
2168 | struct drm_device *dev = node->minor->dev; |
2169 | struct drm_crtc *crtc = &intel_crtc->base; | |
2170 | struct intel_connector *intel_connector; | |
2171 | struct drm_encoder *encoder; | |
2172 | ||
2173 | encoder = &intel_encoder->base; | |
2174 | seq_printf(m, "\tencoder %d: type: %s, connectors:\n", | |
8e329a03 | 2175 | encoder->base.id, encoder->name); |
53f5e3ca JB |
2176 | for_each_connector_on_encoder(dev, encoder, intel_connector) { |
2177 | struct drm_connector *connector = &intel_connector->base; | |
2178 | seq_printf(m, "\t\tconnector %d: type: %s, status: %s", | |
2179 | connector->base.id, | |
c23cc417 | 2180 | connector->name, |
53f5e3ca JB |
2181 | drm_get_connector_status_name(connector->status)); |
2182 | if (connector->status == connector_status_connected) { | |
2183 | struct drm_display_mode *mode = &crtc->mode; | |
2184 | seq_printf(m, ", mode:\n"); | |
2185 | intel_seq_print_mode(m, 2, mode); | |
2186 | } else { | |
2187 | seq_putc(m, '\n'); | |
2188 | } | |
2189 | } | |
2190 | } | |
2191 | ||
2192 | static void intel_crtc_info(struct seq_file *m, struct intel_crtc *intel_crtc) | |
2193 | { | |
9f25d007 | 2194 | struct drm_info_node *node = m->private; |
53f5e3ca JB |
2195 | struct drm_device *dev = node->minor->dev; |
2196 | struct drm_crtc *crtc = &intel_crtc->base; | |
2197 | struct intel_encoder *intel_encoder; | |
2198 | ||
5aa8a937 MR |
2199 | if (crtc->primary->fb) |
2200 | seq_printf(m, "\tfb: %d, pos: %dx%d, size: %dx%d\n", | |
2201 | crtc->primary->fb->base.id, crtc->x, crtc->y, | |
2202 | crtc->primary->fb->width, crtc->primary->fb->height); | |
2203 | else | |
2204 | seq_puts(m, "\tprimary plane disabled\n"); | |
53f5e3ca JB |
2205 | for_each_encoder_on_crtc(dev, crtc, intel_encoder) |
2206 | intel_encoder_info(m, intel_crtc, intel_encoder); | |
2207 | } | |
2208 | ||
2209 | static void intel_panel_info(struct seq_file *m, struct intel_panel *panel) | |
2210 | { | |
2211 | struct drm_display_mode *mode = panel->fixed_mode; | |
2212 | ||
2213 | seq_printf(m, "\tfixed mode:\n"); | |
2214 | intel_seq_print_mode(m, 2, mode); | |
2215 | } | |
2216 | ||
2217 | static void intel_dp_info(struct seq_file *m, | |
2218 | struct intel_connector *intel_connector) | |
2219 | { | |
2220 | struct intel_encoder *intel_encoder = intel_connector->encoder; | |
2221 | struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base); | |
2222 | ||
2223 | seq_printf(m, "\tDPCD rev: %x\n", intel_dp->dpcd[DP_DPCD_REV]); | |
2224 | seq_printf(m, "\taudio support: %s\n", intel_dp->has_audio ? "yes" : | |
2225 | "no"); | |
2226 | if (intel_encoder->type == INTEL_OUTPUT_EDP) | |
2227 | intel_panel_info(m, &intel_connector->panel); | |
2228 | } | |
2229 | ||
2230 | static void intel_hdmi_info(struct seq_file *m, | |
2231 | struct intel_connector *intel_connector) | |
2232 | { | |
2233 | struct intel_encoder *intel_encoder = intel_connector->encoder; | |
2234 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&intel_encoder->base); | |
2235 | ||
2236 | seq_printf(m, "\taudio support: %s\n", intel_hdmi->has_audio ? "yes" : | |
2237 | "no"); | |
2238 | } | |
2239 | ||
2240 | static void intel_lvds_info(struct seq_file *m, | |
2241 | struct intel_connector *intel_connector) | |
2242 | { | |
2243 | intel_panel_info(m, &intel_connector->panel); | |
2244 | } | |
2245 | ||
2246 | static void intel_connector_info(struct seq_file *m, | |
2247 | struct drm_connector *connector) | |
2248 | { | |
2249 | struct intel_connector *intel_connector = to_intel_connector(connector); | |
2250 | struct intel_encoder *intel_encoder = intel_connector->encoder; | |
f103fc7d | 2251 | struct drm_display_mode *mode; |
53f5e3ca JB |
2252 | |
2253 | seq_printf(m, "connector %d: type %s, status: %s\n", | |
c23cc417 | 2254 | connector->base.id, connector->name, |
53f5e3ca JB |
2255 | drm_get_connector_status_name(connector->status)); |
2256 | if (connector->status == connector_status_connected) { | |
2257 | seq_printf(m, "\tname: %s\n", connector->display_info.name); | |
2258 | seq_printf(m, "\tphysical dimensions: %dx%dmm\n", | |
2259 | connector->display_info.width_mm, | |
2260 | connector->display_info.height_mm); | |
2261 | seq_printf(m, "\tsubpixel order: %s\n", | |
2262 | drm_get_subpixel_order_name(connector->display_info.subpixel_order)); | |
2263 | seq_printf(m, "\tCEA rev: %d\n", | |
2264 | connector->display_info.cea_rev); | |
2265 | } | |
36cd7444 DA |
2266 | if (intel_encoder) { |
2267 | if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT || | |
2268 | intel_encoder->type == INTEL_OUTPUT_EDP) | |
2269 | intel_dp_info(m, intel_connector); | |
2270 | else if (intel_encoder->type == INTEL_OUTPUT_HDMI) | |
2271 | intel_hdmi_info(m, intel_connector); | |
2272 | else if (intel_encoder->type == INTEL_OUTPUT_LVDS) | |
2273 | intel_lvds_info(m, intel_connector); | |
2274 | } | |
53f5e3ca | 2275 | |
f103fc7d JB |
2276 | seq_printf(m, "\tmodes:\n"); |
2277 | list_for_each_entry(mode, &connector->modes, head) | |
2278 | intel_seq_print_mode(m, 2, mode); | |
53f5e3ca JB |
2279 | } |
2280 | ||
065f2ec2 CW |
2281 | static bool cursor_active(struct drm_device *dev, int pipe) |
2282 | { | |
2283 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2284 | u32 state; | |
2285 | ||
2286 | if (IS_845G(dev) || IS_I865G(dev)) | |
2287 | state = I915_READ(_CURACNTR) & CURSOR_ENABLE; | |
065f2ec2 | 2288 | else |
5efb3e28 | 2289 | state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE; |
065f2ec2 CW |
2290 | |
2291 | return state; | |
2292 | } | |
2293 | ||
2294 | static bool cursor_position(struct drm_device *dev, int pipe, int *x, int *y) | |
2295 | { | |
2296 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2297 | u32 pos; | |
2298 | ||
5efb3e28 | 2299 | pos = I915_READ(CURPOS(pipe)); |
065f2ec2 CW |
2300 | |
2301 | *x = (pos >> CURSOR_X_SHIFT) & CURSOR_POS_MASK; | |
2302 | if (pos & (CURSOR_POS_SIGN << CURSOR_X_SHIFT)) | |
2303 | *x = -*x; | |
2304 | ||
2305 | *y = (pos >> CURSOR_Y_SHIFT) & CURSOR_POS_MASK; | |
2306 | if (pos & (CURSOR_POS_SIGN << CURSOR_Y_SHIFT)) | |
2307 | *y = -*y; | |
2308 | ||
2309 | return cursor_active(dev, pipe); | |
2310 | } | |
2311 | ||
53f5e3ca JB |
2312 | static int i915_display_info(struct seq_file *m, void *unused) |
2313 | { | |
9f25d007 | 2314 | struct drm_info_node *node = m->private; |
53f5e3ca | 2315 | struct drm_device *dev = node->minor->dev; |
b0e5ddf3 | 2316 | struct drm_i915_private *dev_priv = dev->dev_private; |
065f2ec2 | 2317 | struct intel_crtc *crtc; |
53f5e3ca JB |
2318 | struct drm_connector *connector; |
2319 | ||
b0e5ddf3 | 2320 | intel_runtime_pm_get(dev_priv); |
53f5e3ca JB |
2321 | drm_modeset_lock_all(dev); |
2322 | seq_printf(m, "CRTC info\n"); | |
2323 | seq_printf(m, "---------\n"); | |
d3fcc808 | 2324 | for_each_intel_crtc(dev, crtc) { |
065f2ec2 CW |
2325 | bool active; |
2326 | int x, y; | |
53f5e3ca | 2327 | |
57127efa | 2328 | seq_printf(m, "CRTC %d: pipe: %c, active=%s (size=%dx%d)\n", |
065f2ec2 | 2329 | crtc->base.base.id, pipe_name(crtc->pipe), |
57127efa | 2330 | yesno(crtc->active), crtc->config.pipe_src_w, crtc->config.pipe_src_h); |
a23dc658 | 2331 | if (crtc->active) { |
065f2ec2 CW |
2332 | intel_crtc_info(m, crtc); |
2333 | ||
a23dc658 | 2334 | active = cursor_position(dev, crtc->pipe, &x, &y); |
57127efa | 2335 | seq_printf(m, "\tcursor visible? %s, position (%d, %d), size %dx%d, addr 0x%08x, active? %s\n", |
4b0e333e | 2336 | yesno(crtc->cursor_base), |
57127efa CW |
2337 | x, y, crtc->cursor_width, crtc->cursor_height, |
2338 | crtc->cursor_addr, yesno(active)); | |
a23dc658 | 2339 | } |
cace841c DV |
2340 | |
2341 | seq_printf(m, "\tunderrun reporting: cpu=%s pch=%s \n", | |
2342 | yesno(!crtc->cpu_fifo_underrun_disabled), | |
2343 | yesno(!crtc->pch_fifo_underrun_disabled)); | |
53f5e3ca JB |
2344 | } |
2345 | ||
2346 | seq_printf(m, "\n"); | |
2347 | seq_printf(m, "Connector info\n"); | |
2348 | seq_printf(m, "--------------\n"); | |
2349 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
2350 | intel_connector_info(m, connector); | |
2351 | } | |
2352 | drm_modeset_unlock_all(dev); | |
b0e5ddf3 | 2353 | intel_runtime_pm_put(dev_priv); |
53f5e3ca JB |
2354 | |
2355 | return 0; | |
2356 | } | |
2357 | ||
e04934cf BW |
2358 | static int i915_semaphore_status(struct seq_file *m, void *unused) |
2359 | { | |
2360 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
2361 | struct drm_device *dev = node->minor->dev; | |
2362 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2363 | struct intel_engine_cs *ring; | |
2364 | int num_rings = hweight32(INTEL_INFO(dev)->ring_mask); | |
2365 | int i, j, ret; | |
2366 | ||
2367 | if (!i915_semaphore_is_enabled(dev)) { | |
2368 | seq_puts(m, "Semaphores are disabled\n"); | |
2369 | return 0; | |
2370 | } | |
2371 | ||
2372 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
2373 | if (ret) | |
2374 | return ret; | |
03872064 | 2375 | intel_runtime_pm_get(dev_priv); |
e04934cf BW |
2376 | |
2377 | if (IS_BROADWELL(dev)) { | |
2378 | struct page *page; | |
2379 | uint64_t *seqno; | |
2380 | ||
2381 | page = i915_gem_object_get_page(dev_priv->semaphore_obj, 0); | |
2382 | ||
2383 | seqno = (uint64_t *)kmap_atomic(page); | |
2384 | for_each_ring(ring, dev_priv, i) { | |
2385 | uint64_t offset; | |
2386 | ||
2387 | seq_printf(m, "%s\n", ring->name); | |
2388 | ||
2389 | seq_puts(m, " Last signal:"); | |
2390 | for (j = 0; j < num_rings; j++) { | |
2391 | offset = i * I915_NUM_RINGS + j; | |
2392 | seq_printf(m, "0x%08llx (0x%02llx) ", | |
2393 | seqno[offset], offset * 8); | |
2394 | } | |
2395 | seq_putc(m, '\n'); | |
2396 | ||
2397 | seq_puts(m, " Last wait: "); | |
2398 | for (j = 0; j < num_rings; j++) { | |
2399 | offset = i + (j * I915_NUM_RINGS); | |
2400 | seq_printf(m, "0x%08llx (0x%02llx) ", | |
2401 | seqno[offset], offset * 8); | |
2402 | } | |
2403 | seq_putc(m, '\n'); | |
2404 | ||
2405 | } | |
2406 | kunmap_atomic(seqno); | |
2407 | } else { | |
2408 | seq_puts(m, " Last signal:"); | |
2409 | for_each_ring(ring, dev_priv, i) | |
2410 | for (j = 0; j < num_rings; j++) | |
2411 | seq_printf(m, "0x%08x\n", | |
2412 | I915_READ(ring->semaphore.mbox.signal[j])); | |
2413 | seq_putc(m, '\n'); | |
2414 | } | |
2415 | ||
2416 | seq_puts(m, "\nSync seqno:\n"); | |
2417 | for_each_ring(ring, dev_priv, i) { | |
2418 | for (j = 0; j < num_rings; j++) { | |
2419 | seq_printf(m, " 0x%08x ", ring->semaphore.sync_seqno[j]); | |
2420 | } | |
2421 | seq_putc(m, '\n'); | |
2422 | } | |
2423 | seq_putc(m, '\n'); | |
2424 | ||
03872064 | 2425 | intel_runtime_pm_put(dev_priv); |
e04934cf BW |
2426 | mutex_unlock(&dev->struct_mutex); |
2427 | return 0; | |
2428 | } | |
2429 | ||
728e29d7 DV |
2430 | static int i915_shared_dplls_info(struct seq_file *m, void *unused) |
2431 | { | |
2432 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
2433 | struct drm_device *dev = node->minor->dev; | |
2434 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2435 | int i; | |
2436 | ||
2437 | drm_modeset_lock_all(dev); | |
2438 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { | |
2439 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; | |
2440 | ||
2441 | seq_printf(m, "DPLL%i: %s, id: %i\n", i, pll->name, pll->id); | |
2442 | seq_printf(m, " refcount: %i, active: %i, on: %s\n", pll->refcount, | |
2443 | pll->active, yesno(pll->on)); | |
2444 | seq_printf(m, " tracked hardware state:\n"); | |
2445 | seq_printf(m, " dpll: 0x%08x\n", pll->hw_state.dpll); | |
2446 | seq_printf(m, " dpll_md: 0x%08x\n", pll->hw_state.dpll_md); | |
2447 | seq_printf(m, " fp0: 0x%08x\n", pll->hw_state.fp0); | |
2448 | seq_printf(m, " fp1: 0x%08x\n", pll->hw_state.fp1); | |
d452c5b6 | 2449 | seq_printf(m, " wrpll: 0x%08x\n", pll->hw_state.wrpll); |
728e29d7 DV |
2450 | } |
2451 | drm_modeset_unlock_all(dev); | |
2452 | ||
2453 | return 0; | |
2454 | } | |
2455 | ||
07144428 DL |
2456 | struct pipe_crc_info { |
2457 | const char *name; | |
2458 | struct drm_device *dev; | |
2459 | enum pipe pipe; | |
2460 | }; | |
2461 | ||
11bed958 DA |
2462 | static int i915_dp_mst_info(struct seq_file *m, void *unused) |
2463 | { | |
2464 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
2465 | struct drm_device *dev = node->minor->dev; | |
2466 | struct drm_encoder *encoder; | |
2467 | struct intel_encoder *intel_encoder; | |
2468 | struct intel_digital_port *intel_dig_port; | |
2469 | drm_modeset_lock_all(dev); | |
2470 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { | |
2471 | intel_encoder = to_intel_encoder(encoder); | |
2472 | if (intel_encoder->type != INTEL_OUTPUT_DISPLAYPORT) | |
2473 | continue; | |
2474 | intel_dig_port = enc_to_dig_port(encoder); | |
2475 | if (!intel_dig_port->dp.can_mst) | |
2476 | continue; | |
2477 | ||
2478 | drm_dp_mst_dump_topology(m, &intel_dig_port->dp.mst_mgr); | |
2479 | } | |
2480 | drm_modeset_unlock_all(dev); | |
2481 | return 0; | |
2482 | } | |
2483 | ||
07144428 DL |
2484 | static int i915_pipe_crc_open(struct inode *inode, struct file *filep) |
2485 | { | |
be5c7a90 DL |
2486 | struct pipe_crc_info *info = inode->i_private; |
2487 | struct drm_i915_private *dev_priv = info->dev->dev_private; | |
2488 | struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe]; | |
2489 | ||
7eb1c496 DV |
2490 | if (info->pipe >= INTEL_INFO(info->dev)->num_pipes) |
2491 | return -ENODEV; | |
2492 | ||
d538bbdf DL |
2493 | spin_lock_irq(&pipe_crc->lock); |
2494 | ||
2495 | if (pipe_crc->opened) { | |
2496 | spin_unlock_irq(&pipe_crc->lock); | |
be5c7a90 DL |
2497 | return -EBUSY; /* already open */ |
2498 | } | |
2499 | ||
d538bbdf | 2500 | pipe_crc->opened = true; |
07144428 DL |
2501 | filep->private_data = inode->i_private; |
2502 | ||
d538bbdf DL |
2503 | spin_unlock_irq(&pipe_crc->lock); |
2504 | ||
07144428 DL |
2505 | return 0; |
2506 | } | |
2507 | ||
2508 | static int i915_pipe_crc_release(struct inode *inode, struct file *filep) | |
2509 | { | |
be5c7a90 DL |
2510 | struct pipe_crc_info *info = inode->i_private; |
2511 | struct drm_i915_private *dev_priv = info->dev->dev_private; | |
2512 | struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe]; | |
2513 | ||
d538bbdf DL |
2514 | spin_lock_irq(&pipe_crc->lock); |
2515 | pipe_crc->opened = false; | |
2516 | spin_unlock_irq(&pipe_crc->lock); | |
be5c7a90 | 2517 | |
07144428 DL |
2518 | return 0; |
2519 | } | |
2520 | ||
2521 | /* (6 fields, 8 chars each, space separated (5) + '\n') */ | |
2522 | #define PIPE_CRC_LINE_LEN (6 * 8 + 5 + 1) | |
2523 | /* account for \'0' */ | |
2524 | #define PIPE_CRC_BUFFER_LEN (PIPE_CRC_LINE_LEN + 1) | |
2525 | ||
2526 | static int pipe_crc_data_count(struct intel_pipe_crc *pipe_crc) | |
8bf1e9f1 | 2527 | { |
d538bbdf DL |
2528 | assert_spin_locked(&pipe_crc->lock); |
2529 | return CIRC_CNT(pipe_crc->head, pipe_crc->tail, | |
2530 | INTEL_PIPE_CRC_ENTRIES_NR); | |
07144428 DL |
2531 | } |
2532 | ||
2533 | static ssize_t | |
2534 | i915_pipe_crc_read(struct file *filep, char __user *user_buf, size_t count, | |
2535 | loff_t *pos) | |
2536 | { | |
2537 | struct pipe_crc_info *info = filep->private_data; | |
2538 | struct drm_device *dev = info->dev; | |
2539 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2540 | struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe]; | |
2541 | char buf[PIPE_CRC_BUFFER_LEN]; | |
2542 | int head, tail, n_entries, n; | |
2543 | ssize_t bytes_read; | |
2544 | ||
2545 | /* | |
2546 | * Don't allow user space to provide buffers not big enough to hold | |
2547 | * a line of data. | |
2548 | */ | |
2549 | if (count < PIPE_CRC_LINE_LEN) | |
2550 | return -EINVAL; | |
2551 | ||
2552 | if (pipe_crc->source == INTEL_PIPE_CRC_SOURCE_NONE) | |
8bf1e9f1 | 2553 | return 0; |
07144428 DL |
2554 | |
2555 | /* nothing to read */ | |
d538bbdf | 2556 | spin_lock_irq(&pipe_crc->lock); |
07144428 | 2557 | while (pipe_crc_data_count(pipe_crc) == 0) { |
d538bbdf DL |
2558 | int ret; |
2559 | ||
2560 | if (filep->f_flags & O_NONBLOCK) { | |
2561 | spin_unlock_irq(&pipe_crc->lock); | |
07144428 | 2562 | return -EAGAIN; |
d538bbdf | 2563 | } |
07144428 | 2564 | |
d538bbdf DL |
2565 | ret = wait_event_interruptible_lock_irq(pipe_crc->wq, |
2566 | pipe_crc_data_count(pipe_crc), pipe_crc->lock); | |
2567 | if (ret) { | |
2568 | spin_unlock_irq(&pipe_crc->lock); | |
2569 | return ret; | |
2570 | } | |
8bf1e9f1 SH |
2571 | } |
2572 | ||
07144428 | 2573 | /* We now have one or more entries to read */ |
d538bbdf DL |
2574 | head = pipe_crc->head; |
2575 | tail = pipe_crc->tail; | |
07144428 DL |
2576 | n_entries = min((size_t)CIRC_CNT(head, tail, INTEL_PIPE_CRC_ENTRIES_NR), |
2577 | count / PIPE_CRC_LINE_LEN); | |
d538bbdf DL |
2578 | spin_unlock_irq(&pipe_crc->lock); |
2579 | ||
07144428 DL |
2580 | bytes_read = 0; |
2581 | n = 0; | |
2582 | do { | |
b2c88f5b | 2583 | struct intel_pipe_crc_entry *entry = &pipe_crc->entries[tail]; |
07144428 | 2584 | int ret; |
8bf1e9f1 | 2585 | |
07144428 DL |
2586 | bytes_read += snprintf(buf, PIPE_CRC_BUFFER_LEN, |
2587 | "%8u %8x %8x %8x %8x %8x\n", | |
2588 | entry->frame, entry->crc[0], | |
2589 | entry->crc[1], entry->crc[2], | |
2590 | entry->crc[3], entry->crc[4]); | |
2591 | ||
2592 | ret = copy_to_user(user_buf + n * PIPE_CRC_LINE_LEN, | |
2593 | buf, PIPE_CRC_LINE_LEN); | |
2594 | if (ret == PIPE_CRC_LINE_LEN) | |
2595 | return -EFAULT; | |
b2c88f5b DL |
2596 | |
2597 | BUILD_BUG_ON_NOT_POWER_OF_2(INTEL_PIPE_CRC_ENTRIES_NR); | |
2598 | tail = (tail + 1) & (INTEL_PIPE_CRC_ENTRIES_NR - 1); | |
07144428 DL |
2599 | n++; |
2600 | } while (--n_entries); | |
8bf1e9f1 | 2601 | |
d538bbdf DL |
2602 | spin_lock_irq(&pipe_crc->lock); |
2603 | pipe_crc->tail = tail; | |
2604 | spin_unlock_irq(&pipe_crc->lock); | |
2605 | ||
07144428 DL |
2606 | return bytes_read; |
2607 | } | |
2608 | ||
2609 | static const struct file_operations i915_pipe_crc_fops = { | |
2610 | .owner = THIS_MODULE, | |
2611 | .open = i915_pipe_crc_open, | |
2612 | .read = i915_pipe_crc_read, | |
2613 | .release = i915_pipe_crc_release, | |
2614 | }; | |
2615 | ||
2616 | static struct pipe_crc_info i915_pipe_crc_data[I915_MAX_PIPES] = { | |
2617 | { | |
2618 | .name = "i915_pipe_A_crc", | |
2619 | .pipe = PIPE_A, | |
2620 | }, | |
2621 | { | |
2622 | .name = "i915_pipe_B_crc", | |
2623 | .pipe = PIPE_B, | |
2624 | }, | |
2625 | { | |
2626 | .name = "i915_pipe_C_crc", | |
2627 | .pipe = PIPE_C, | |
2628 | }, | |
2629 | }; | |
2630 | ||
2631 | static int i915_pipe_crc_create(struct dentry *root, struct drm_minor *minor, | |
2632 | enum pipe pipe) | |
2633 | { | |
2634 | struct drm_device *dev = minor->dev; | |
2635 | struct dentry *ent; | |
2636 | struct pipe_crc_info *info = &i915_pipe_crc_data[pipe]; | |
2637 | ||
2638 | info->dev = dev; | |
2639 | ent = debugfs_create_file(info->name, S_IRUGO, root, info, | |
2640 | &i915_pipe_crc_fops); | |
f3c5fe97 WY |
2641 | if (!ent) |
2642 | return -ENOMEM; | |
07144428 DL |
2643 | |
2644 | return drm_add_fake_info_node(minor, ent, info); | |
8bf1e9f1 SH |
2645 | } |
2646 | ||
e8dfcf78 | 2647 | static const char * const pipe_crc_sources[] = { |
926321d5 DV |
2648 | "none", |
2649 | "plane1", | |
2650 | "plane2", | |
2651 | "pf", | |
5b3a856b | 2652 | "pipe", |
3d099a05 DV |
2653 | "TV", |
2654 | "DP-B", | |
2655 | "DP-C", | |
2656 | "DP-D", | |
46a19188 | 2657 | "auto", |
926321d5 DV |
2658 | }; |
2659 | ||
2660 | static const char *pipe_crc_source_name(enum intel_pipe_crc_source source) | |
2661 | { | |
2662 | BUILD_BUG_ON(ARRAY_SIZE(pipe_crc_sources) != INTEL_PIPE_CRC_SOURCE_MAX); | |
2663 | return pipe_crc_sources[source]; | |
2664 | } | |
2665 | ||
bd9db02f | 2666 | static int display_crc_ctl_show(struct seq_file *m, void *data) |
926321d5 DV |
2667 | { |
2668 | struct drm_device *dev = m->private; | |
2669 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2670 | int i; | |
2671 | ||
2672 | for (i = 0; i < I915_MAX_PIPES; i++) | |
2673 | seq_printf(m, "%c %s\n", pipe_name(i), | |
2674 | pipe_crc_source_name(dev_priv->pipe_crc[i].source)); | |
2675 | ||
2676 | return 0; | |
2677 | } | |
2678 | ||
bd9db02f | 2679 | static int display_crc_ctl_open(struct inode *inode, struct file *file) |
926321d5 DV |
2680 | { |
2681 | struct drm_device *dev = inode->i_private; | |
2682 | ||
bd9db02f | 2683 | return single_open(file, display_crc_ctl_show, dev); |
926321d5 DV |
2684 | } |
2685 | ||
46a19188 | 2686 | static int i8xx_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source, |
52f843f6 DV |
2687 | uint32_t *val) |
2688 | { | |
46a19188 DV |
2689 | if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) |
2690 | *source = INTEL_PIPE_CRC_SOURCE_PIPE; | |
2691 | ||
2692 | switch (*source) { | |
52f843f6 DV |
2693 | case INTEL_PIPE_CRC_SOURCE_PIPE: |
2694 | *val = PIPE_CRC_ENABLE | PIPE_CRC_INCLUDE_BORDER_I8XX; | |
2695 | break; | |
2696 | case INTEL_PIPE_CRC_SOURCE_NONE: | |
2697 | *val = 0; | |
2698 | break; | |
2699 | default: | |
2700 | return -EINVAL; | |
2701 | } | |
2702 | ||
2703 | return 0; | |
2704 | } | |
2705 | ||
46a19188 DV |
2706 | static int i9xx_pipe_crc_auto_source(struct drm_device *dev, enum pipe pipe, |
2707 | enum intel_pipe_crc_source *source) | |
2708 | { | |
2709 | struct intel_encoder *encoder; | |
2710 | struct intel_crtc *crtc; | |
26756809 | 2711 | struct intel_digital_port *dig_port; |
46a19188 DV |
2712 | int ret = 0; |
2713 | ||
2714 | *source = INTEL_PIPE_CRC_SOURCE_PIPE; | |
2715 | ||
6e9f798d | 2716 | drm_modeset_lock_all(dev); |
b2784e15 | 2717 | for_each_intel_encoder(dev, encoder) { |
46a19188 DV |
2718 | if (!encoder->base.crtc) |
2719 | continue; | |
2720 | ||
2721 | crtc = to_intel_crtc(encoder->base.crtc); | |
2722 | ||
2723 | if (crtc->pipe != pipe) | |
2724 | continue; | |
2725 | ||
2726 | switch (encoder->type) { | |
2727 | case INTEL_OUTPUT_TVOUT: | |
2728 | *source = INTEL_PIPE_CRC_SOURCE_TV; | |
2729 | break; | |
2730 | case INTEL_OUTPUT_DISPLAYPORT: | |
2731 | case INTEL_OUTPUT_EDP: | |
26756809 DV |
2732 | dig_port = enc_to_dig_port(&encoder->base); |
2733 | switch (dig_port->port) { | |
2734 | case PORT_B: | |
2735 | *source = INTEL_PIPE_CRC_SOURCE_DP_B; | |
2736 | break; | |
2737 | case PORT_C: | |
2738 | *source = INTEL_PIPE_CRC_SOURCE_DP_C; | |
2739 | break; | |
2740 | case PORT_D: | |
2741 | *source = INTEL_PIPE_CRC_SOURCE_DP_D; | |
2742 | break; | |
2743 | default: | |
2744 | WARN(1, "nonexisting DP port %c\n", | |
2745 | port_name(dig_port->port)); | |
2746 | break; | |
2747 | } | |
46a19188 DV |
2748 | break; |
2749 | } | |
2750 | } | |
6e9f798d | 2751 | drm_modeset_unlock_all(dev); |
46a19188 DV |
2752 | |
2753 | return ret; | |
2754 | } | |
2755 | ||
2756 | static int vlv_pipe_crc_ctl_reg(struct drm_device *dev, | |
2757 | enum pipe pipe, | |
2758 | enum intel_pipe_crc_source *source, | |
7ac0129b DV |
2759 | uint32_t *val) |
2760 | { | |
8d2f24ca DV |
2761 | struct drm_i915_private *dev_priv = dev->dev_private; |
2762 | bool need_stable_symbols = false; | |
2763 | ||
46a19188 DV |
2764 | if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) { |
2765 | int ret = i9xx_pipe_crc_auto_source(dev, pipe, source); | |
2766 | if (ret) | |
2767 | return ret; | |
2768 | } | |
2769 | ||
2770 | switch (*source) { | |
7ac0129b DV |
2771 | case INTEL_PIPE_CRC_SOURCE_PIPE: |
2772 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_VLV; | |
2773 | break; | |
2774 | case INTEL_PIPE_CRC_SOURCE_DP_B: | |
2775 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_VLV; | |
8d2f24ca | 2776 | need_stable_symbols = true; |
7ac0129b DV |
2777 | break; |
2778 | case INTEL_PIPE_CRC_SOURCE_DP_C: | |
2779 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_VLV; | |
8d2f24ca | 2780 | need_stable_symbols = true; |
7ac0129b DV |
2781 | break; |
2782 | case INTEL_PIPE_CRC_SOURCE_NONE: | |
2783 | *val = 0; | |
2784 | break; | |
2785 | default: | |
2786 | return -EINVAL; | |
2787 | } | |
2788 | ||
8d2f24ca DV |
2789 | /* |
2790 | * When the pipe CRC tap point is after the transcoders we need | |
2791 | * to tweak symbol-level features to produce a deterministic series of | |
2792 | * symbols for a given frame. We need to reset those features only once | |
2793 | * a frame (instead of every nth symbol): | |
2794 | * - DC-balance: used to ensure a better clock recovery from the data | |
2795 | * link (SDVO) | |
2796 | * - DisplayPort scrambling: used for EMI reduction | |
2797 | */ | |
2798 | if (need_stable_symbols) { | |
2799 | uint32_t tmp = I915_READ(PORT_DFT2_G4X); | |
2800 | ||
8d2f24ca DV |
2801 | tmp |= DC_BALANCE_RESET_VLV; |
2802 | if (pipe == PIPE_A) | |
2803 | tmp |= PIPE_A_SCRAMBLE_RESET; | |
2804 | else | |
2805 | tmp |= PIPE_B_SCRAMBLE_RESET; | |
2806 | ||
2807 | I915_WRITE(PORT_DFT2_G4X, tmp); | |
2808 | } | |
2809 | ||
7ac0129b DV |
2810 | return 0; |
2811 | } | |
2812 | ||
4b79ebf7 | 2813 | static int i9xx_pipe_crc_ctl_reg(struct drm_device *dev, |
46a19188 DV |
2814 | enum pipe pipe, |
2815 | enum intel_pipe_crc_source *source, | |
4b79ebf7 DV |
2816 | uint32_t *val) |
2817 | { | |
84093603 DV |
2818 | struct drm_i915_private *dev_priv = dev->dev_private; |
2819 | bool need_stable_symbols = false; | |
2820 | ||
46a19188 DV |
2821 | if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) { |
2822 | int ret = i9xx_pipe_crc_auto_source(dev, pipe, source); | |
2823 | if (ret) | |
2824 | return ret; | |
2825 | } | |
2826 | ||
2827 | switch (*source) { | |
4b79ebf7 DV |
2828 | case INTEL_PIPE_CRC_SOURCE_PIPE: |
2829 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_I9XX; | |
2830 | break; | |
2831 | case INTEL_PIPE_CRC_SOURCE_TV: | |
2832 | if (!SUPPORTS_TV(dev)) | |
2833 | return -EINVAL; | |
2834 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_TV_PRE; | |
2835 | break; | |
2836 | case INTEL_PIPE_CRC_SOURCE_DP_B: | |
2837 | if (!IS_G4X(dev)) | |
2838 | return -EINVAL; | |
2839 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_G4X; | |
84093603 | 2840 | need_stable_symbols = true; |
4b79ebf7 DV |
2841 | break; |
2842 | case INTEL_PIPE_CRC_SOURCE_DP_C: | |
2843 | if (!IS_G4X(dev)) | |
2844 | return -EINVAL; | |
2845 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_G4X; | |
84093603 | 2846 | need_stable_symbols = true; |
4b79ebf7 DV |
2847 | break; |
2848 | case INTEL_PIPE_CRC_SOURCE_DP_D: | |
2849 | if (!IS_G4X(dev)) | |
2850 | return -EINVAL; | |
2851 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_G4X; | |
84093603 | 2852 | need_stable_symbols = true; |
4b79ebf7 DV |
2853 | break; |
2854 | case INTEL_PIPE_CRC_SOURCE_NONE: | |
2855 | *val = 0; | |
2856 | break; | |
2857 | default: | |
2858 | return -EINVAL; | |
2859 | } | |
2860 | ||
84093603 DV |
2861 | /* |
2862 | * When the pipe CRC tap point is after the transcoders we need | |
2863 | * to tweak symbol-level features to produce a deterministic series of | |
2864 | * symbols for a given frame. We need to reset those features only once | |
2865 | * a frame (instead of every nth symbol): | |
2866 | * - DC-balance: used to ensure a better clock recovery from the data | |
2867 | * link (SDVO) | |
2868 | * - DisplayPort scrambling: used for EMI reduction | |
2869 | */ | |
2870 | if (need_stable_symbols) { | |
2871 | uint32_t tmp = I915_READ(PORT_DFT2_G4X); | |
2872 | ||
2873 | WARN_ON(!IS_G4X(dev)); | |
2874 | ||
2875 | I915_WRITE(PORT_DFT_I9XX, | |
2876 | I915_READ(PORT_DFT_I9XX) | DC_BALANCE_RESET); | |
2877 | ||
2878 | if (pipe == PIPE_A) | |
2879 | tmp |= PIPE_A_SCRAMBLE_RESET; | |
2880 | else | |
2881 | tmp |= PIPE_B_SCRAMBLE_RESET; | |
2882 | ||
2883 | I915_WRITE(PORT_DFT2_G4X, tmp); | |
2884 | } | |
2885 | ||
4b79ebf7 DV |
2886 | return 0; |
2887 | } | |
2888 | ||
8d2f24ca DV |
2889 | static void vlv_undo_pipe_scramble_reset(struct drm_device *dev, |
2890 | enum pipe pipe) | |
2891 | { | |
2892 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2893 | uint32_t tmp = I915_READ(PORT_DFT2_G4X); | |
2894 | ||
2895 | if (pipe == PIPE_A) | |
2896 | tmp &= ~PIPE_A_SCRAMBLE_RESET; | |
2897 | else | |
2898 | tmp &= ~PIPE_B_SCRAMBLE_RESET; | |
2899 | if (!(tmp & PIPE_SCRAMBLE_RESET_MASK)) | |
2900 | tmp &= ~DC_BALANCE_RESET_VLV; | |
2901 | I915_WRITE(PORT_DFT2_G4X, tmp); | |
2902 | ||
2903 | } | |
2904 | ||
84093603 DV |
2905 | static void g4x_undo_pipe_scramble_reset(struct drm_device *dev, |
2906 | enum pipe pipe) | |
2907 | { | |
2908 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2909 | uint32_t tmp = I915_READ(PORT_DFT2_G4X); | |
2910 | ||
2911 | if (pipe == PIPE_A) | |
2912 | tmp &= ~PIPE_A_SCRAMBLE_RESET; | |
2913 | else | |
2914 | tmp &= ~PIPE_B_SCRAMBLE_RESET; | |
2915 | I915_WRITE(PORT_DFT2_G4X, tmp); | |
2916 | ||
2917 | if (!(tmp & PIPE_SCRAMBLE_RESET_MASK)) { | |
2918 | I915_WRITE(PORT_DFT_I9XX, | |
2919 | I915_READ(PORT_DFT_I9XX) & ~DC_BALANCE_RESET); | |
2920 | } | |
2921 | } | |
2922 | ||
46a19188 | 2923 | static int ilk_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source, |
5b3a856b DV |
2924 | uint32_t *val) |
2925 | { | |
46a19188 DV |
2926 | if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) |
2927 | *source = INTEL_PIPE_CRC_SOURCE_PIPE; | |
2928 | ||
2929 | switch (*source) { | |
5b3a856b DV |
2930 | case INTEL_PIPE_CRC_SOURCE_PLANE1: |
2931 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_ILK; | |
2932 | break; | |
2933 | case INTEL_PIPE_CRC_SOURCE_PLANE2: | |
2934 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_ILK; | |
2935 | break; | |
5b3a856b DV |
2936 | case INTEL_PIPE_CRC_SOURCE_PIPE: |
2937 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_ILK; | |
2938 | break; | |
3d099a05 | 2939 | case INTEL_PIPE_CRC_SOURCE_NONE: |
5b3a856b DV |
2940 | *val = 0; |
2941 | break; | |
3d099a05 DV |
2942 | default: |
2943 | return -EINVAL; | |
5b3a856b DV |
2944 | } |
2945 | ||
2946 | return 0; | |
2947 | } | |
2948 | ||
fabf6e51 DV |
2949 | static void hsw_trans_edp_pipe_A_crc_wa(struct drm_device *dev) |
2950 | { | |
2951 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2952 | struct intel_crtc *crtc = | |
2953 | to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_A]); | |
2954 | ||
2955 | drm_modeset_lock_all(dev); | |
2956 | /* | |
2957 | * If we use the eDP transcoder we need to make sure that we don't | |
2958 | * bypass the pfit, since otherwise the pipe CRC source won't work. Only | |
2959 | * relevant on hsw with pipe A when using the always-on power well | |
2960 | * routing. | |
2961 | */ | |
2962 | if (crtc->config.cpu_transcoder == TRANSCODER_EDP && | |
2963 | !crtc->config.pch_pfit.enabled) { | |
2964 | crtc->config.pch_pfit.force_thru = true; | |
2965 | ||
2966 | intel_display_power_get(dev_priv, | |
2967 | POWER_DOMAIN_PIPE_PANEL_FITTER(PIPE_A)); | |
2968 | ||
2969 | dev_priv->display.crtc_disable(&crtc->base); | |
2970 | dev_priv->display.crtc_enable(&crtc->base); | |
2971 | } | |
2972 | drm_modeset_unlock_all(dev); | |
2973 | } | |
2974 | ||
2975 | static void hsw_undo_trans_edp_pipe_A_crc_wa(struct drm_device *dev) | |
2976 | { | |
2977 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2978 | struct intel_crtc *crtc = | |
2979 | to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_A]); | |
2980 | ||
2981 | drm_modeset_lock_all(dev); | |
2982 | /* | |
2983 | * If we use the eDP transcoder we need to make sure that we don't | |
2984 | * bypass the pfit, since otherwise the pipe CRC source won't work. Only | |
2985 | * relevant on hsw with pipe A when using the always-on power well | |
2986 | * routing. | |
2987 | */ | |
2988 | if (crtc->config.pch_pfit.force_thru) { | |
2989 | crtc->config.pch_pfit.force_thru = false; | |
2990 | ||
2991 | dev_priv->display.crtc_disable(&crtc->base); | |
2992 | dev_priv->display.crtc_enable(&crtc->base); | |
2993 | ||
2994 | intel_display_power_put(dev_priv, | |
2995 | POWER_DOMAIN_PIPE_PANEL_FITTER(PIPE_A)); | |
2996 | } | |
2997 | drm_modeset_unlock_all(dev); | |
2998 | } | |
2999 | ||
3000 | static int ivb_pipe_crc_ctl_reg(struct drm_device *dev, | |
3001 | enum pipe pipe, | |
3002 | enum intel_pipe_crc_source *source, | |
5b3a856b DV |
3003 | uint32_t *val) |
3004 | { | |
46a19188 DV |
3005 | if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) |
3006 | *source = INTEL_PIPE_CRC_SOURCE_PF; | |
3007 | ||
3008 | switch (*source) { | |
5b3a856b DV |
3009 | case INTEL_PIPE_CRC_SOURCE_PLANE1: |
3010 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_IVB; | |
3011 | break; | |
3012 | case INTEL_PIPE_CRC_SOURCE_PLANE2: | |
3013 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_IVB; | |
3014 | break; | |
3015 | case INTEL_PIPE_CRC_SOURCE_PF: | |
fabf6e51 DV |
3016 | if (IS_HASWELL(dev) && pipe == PIPE_A) |
3017 | hsw_trans_edp_pipe_A_crc_wa(dev); | |
3018 | ||
5b3a856b DV |
3019 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PF_IVB; |
3020 | break; | |
3d099a05 | 3021 | case INTEL_PIPE_CRC_SOURCE_NONE: |
5b3a856b DV |
3022 | *val = 0; |
3023 | break; | |
3d099a05 DV |
3024 | default: |
3025 | return -EINVAL; | |
5b3a856b DV |
3026 | } |
3027 | ||
3028 | return 0; | |
3029 | } | |
3030 | ||
926321d5 DV |
3031 | static int pipe_crc_set_source(struct drm_device *dev, enum pipe pipe, |
3032 | enum intel_pipe_crc_source source) | |
3033 | { | |
3034 | struct drm_i915_private *dev_priv = dev->dev_private; | |
cc3da175 | 3035 | struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe]; |
432f3342 | 3036 | u32 val = 0; /* shut up gcc */ |
5b3a856b | 3037 | int ret; |
926321d5 | 3038 | |
cc3da175 DL |
3039 | if (pipe_crc->source == source) |
3040 | return 0; | |
3041 | ||
ae676fcd DL |
3042 | /* forbid changing the source without going back to 'none' */ |
3043 | if (pipe_crc->source && source) | |
3044 | return -EINVAL; | |
3045 | ||
52f843f6 | 3046 | if (IS_GEN2(dev)) |
46a19188 | 3047 | ret = i8xx_pipe_crc_ctl_reg(&source, &val); |
52f843f6 | 3048 | else if (INTEL_INFO(dev)->gen < 5) |
46a19188 | 3049 | ret = i9xx_pipe_crc_ctl_reg(dev, pipe, &source, &val); |
7ac0129b | 3050 | else if (IS_VALLEYVIEW(dev)) |
fabf6e51 | 3051 | ret = vlv_pipe_crc_ctl_reg(dev, pipe, &source, &val); |
4b79ebf7 | 3052 | else if (IS_GEN5(dev) || IS_GEN6(dev)) |
46a19188 | 3053 | ret = ilk_pipe_crc_ctl_reg(&source, &val); |
5b3a856b | 3054 | else |
fabf6e51 | 3055 | ret = ivb_pipe_crc_ctl_reg(dev, pipe, &source, &val); |
5b3a856b DV |
3056 | |
3057 | if (ret != 0) | |
3058 | return ret; | |
3059 | ||
4b584369 DL |
3060 | /* none -> real source transition */ |
3061 | if (source) { | |
7cd6ccff DL |
3062 | DRM_DEBUG_DRIVER("collecting CRCs for pipe %c, %s\n", |
3063 | pipe_name(pipe), pipe_crc_source_name(source)); | |
3064 | ||
e5f75aca DL |
3065 | pipe_crc->entries = kzalloc(sizeof(*pipe_crc->entries) * |
3066 | INTEL_PIPE_CRC_ENTRIES_NR, | |
3067 | GFP_KERNEL); | |
3068 | if (!pipe_crc->entries) | |
3069 | return -ENOMEM; | |
3070 | ||
d538bbdf DL |
3071 | spin_lock_irq(&pipe_crc->lock); |
3072 | pipe_crc->head = 0; | |
3073 | pipe_crc->tail = 0; | |
3074 | spin_unlock_irq(&pipe_crc->lock); | |
4b584369 DL |
3075 | } |
3076 | ||
cc3da175 | 3077 | pipe_crc->source = source; |
926321d5 | 3078 | |
926321d5 DV |
3079 | I915_WRITE(PIPE_CRC_CTL(pipe), val); |
3080 | POSTING_READ(PIPE_CRC_CTL(pipe)); | |
3081 | ||
e5f75aca DL |
3082 | /* real source -> none transition */ |
3083 | if (source == INTEL_PIPE_CRC_SOURCE_NONE) { | |
d538bbdf | 3084 | struct intel_pipe_crc_entry *entries; |
a33d7105 DV |
3085 | struct intel_crtc *crtc = |
3086 | to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); | |
d538bbdf | 3087 | |
7cd6ccff DL |
3088 | DRM_DEBUG_DRIVER("stopping CRCs for pipe %c\n", |
3089 | pipe_name(pipe)); | |
3090 | ||
a33d7105 DV |
3091 | drm_modeset_lock(&crtc->base.mutex, NULL); |
3092 | if (crtc->active) | |
3093 | intel_wait_for_vblank(dev, pipe); | |
3094 | drm_modeset_unlock(&crtc->base.mutex); | |
bcf17ab2 | 3095 | |
d538bbdf DL |
3096 | spin_lock_irq(&pipe_crc->lock); |
3097 | entries = pipe_crc->entries; | |
e5f75aca | 3098 | pipe_crc->entries = NULL; |
d538bbdf DL |
3099 | spin_unlock_irq(&pipe_crc->lock); |
3100 | ||
3101 | kfree(entries); | |
84093603 DV |
3102 | |
3103 | if (IS_G4X(dev)) | |
3104 | g4x_undo_pipe_scramble_reset(dev, pipe); | |
8d2f24ca DV |
3105 | else if (IS_VALLEYVIEW(dev)) |
3106 | vlv_undo_pipe_scramble_reset(dev, pipe); | |
fabf6e51 DV |
3107 | else if (IS_HASWELL(dev) && pipe == PIPE_A) |
3108 | hsw_undo_trans_edp_pipe_A_crc_wa(dev); | |
e5f75aca DL |
3109 | } |
3110 | ||
926321d5 DV |
3111 | return 0; |
3112 | } | |
3113 | ||
3114 | /* | |
3115 | * Parse pipe CRC command strings: | |
b94dec87 DL |
3116 | * command: wsp* object wsp+ name wsp+ source wsp* |
3117 | * object: 'pipe' | |
3118 | * name: (A | B | C) | |
926321d5 DV |
3119 | * source: (none | plane1 | plane2 | pf) |
3120 | * wsp: (#0x20 | #0x9 | #0xA)+ | |
3121 | * | |
3122 | * eg.: | |
b94dec87 DL |
3123 | * "pipe A plane1" -> Start CRC computations on plane1 of pipe A |
3124 | * "pipe A none" -> Stop CRC | |
926321d5 | 3125 | */ |
bd9db02f | 3126 | static int display_crc_ctl_tokenize(char *buf, char *words[], int max_words) |
926321d5 DV |
3127 | { |
3128 | int n_words = 0; | |
3129 | ||
3130 | while (*buf) { | |
3131 | char *end; | |
3132 | ||
3133 | /* skip leading white space */ | |
3134 | buf = skip_spaces(buf); | |
3135 | if (!*buf) | |
3136 | break; /* end of buffer */ | |
3137 | ||
3138 | /* find end of word */ | |
3139 | for (end = buf; *end && !isspace(*end); end++) | |
3140 | ; | |
3141 | ||
3142 | if (n_words == max_words) { | |
3143 | DRM_DEBUG_DRIVER("too many words, allowed <= %d\n", | |
3144 | max_words); | |
3145 | return -EINVAL; /* ran out of words[] before bytes */ | |
3146 | } | |
3147 | ||
3148 | if (*end) | |
3149 | *end++ = '\0'; | |
3150 | words[n_words++] = buf; | |
3151 | buf = end; | |
3152 | } | |
3153 | ||
3154 | return n_words; | |
3155 | } | |
3156 | ||
b94dec87 DL |
3157 | enum intel_pipe_crc_object { |
3158 | PIPE_CRC_OBJECT_PIPE, | |
3159 | }; | |
3160 | ||
e8dfcf78 | 3161 | static const char * const pipe_crc_objects[] = { |
b94dec87 DL |
3162 | "pipe", |
3163 | }; | |
3164 | ||
3165 | static int | |
bd9db02f | 3166 | display_crc_ctl_parse_object(const char *buf, enum intel_pipe_crc_object *o) |
b94dec87 DL |
3167 | { |
3168 | int i; | |
3169 | ||
3170 | for (i = 0; i < ARRAY_SIZE(pipe_crc_objects); i++) | |
3171 | if (!strcmp(buf, pipe_crc_objects[i])) { | |
bd9db02f | 3172 | *o = i; |
b94dec87 DL |
3173 | return 0; |
3174 | } | |
3175 | ||
3176 | return -EINVAL; | |
3177 | } | |
3178 | ||
bd9db02f | 3179 | static int display_crc_ctl_parse_pipe(const char *buf, enum pipe *pipe) |
926321d5 DV |
3180 | { |
3181 | const char name = buf[0]; | |
3182 | ||
3183 | if (name < 'A' || name >= pipe_name(I915_MAX_PIPES)) | |
3184 | return -EINVAL; | |
3185 | ||
3186 | *pipe = name - 'A'; | |
3187 | ||
3188 | return 0; | |
3189 | } | |
3190 | ||
3191 | static int | |
bd9db02f | 3192 | display_crc_ctl_parse_source(const char *buf, enum intel_pipe_crc_source *s) |
926321d5 DV |
3193 | { |
3194 | int i; | |
3195 | ||
3196 | for (i = 0; i < ARRAY_SIZE(pipe_crc_sources); i++) | |
3197 | if (!strcmp(buf, pipe_crc_sources[i])) { | |
bd9db02f | 3198 | *s = i; |
926321d5 DV |
3199 | return 0; |
3200 | } | |
3201 | ||
3202 | return -EINVAL; | |
3203 | } | |
3204 | ||
bd9db02f | 3205 | static int display_crc_ctl_parse(struct drm_device *dev, char *buf, size_t len) |
926321d5 | 3206 | { |
b94dec87 | 3207 | #define N_WORDS 3 |
926321d5 | 3208 | int n_words; |
b94dec87 | 3209 | char *words[N_WORDS]; |
926321d5 | 3210 | enum pipe pipe; |
b94dec87 | 3211 | enum intel_pipe_crc_object object; |
926321d5 DV |
3212 | enum intel_pipe_crc_source source; |
3213 | ||
bd9db02f | 3214 | n_words = display_crc_ctl_tokenize(buf, words, N_WORDS); |
b94dec87 DL |
3215 | if (n_words != N_WORDS) { |
3216 | DRM_DEBUG_DRIVER("tokenize failed, a command is %d words\n", | |
3217 | N_WORDS); | |
3218 | return -EINVAL; | |
3219 | } | |
3220 | ||
bd9db02f | 3221 | if (display_crc_ctl_parse_object(words[0], &object) < 0) { |
b94dec87 | 3222 | DRM_DEBUG_DRIVER("unknown object %s\n", words[0]); |
926321d5 DV |
3223 | return -EINVAL; |
3224 | } | |
3225 | ||
bd9db02f | 3226 | if (display_crc_ctl_parse_pipe(words[1], &pipe) < 0) { |
b94dec87 | 3227 | DRM_DEBUG_DRIVER("unknown pipe %s\n", words[1]); |
926321d5 DV |
3228 | return -EINVAL; |
3229 | } | |
3230 | ||
bd9db02f | 3231 | if (display_crc_ctl_parse_source(words[2], &source) < 0) { |
b94dec87 | 3232 | DRM_DEBUG_DRIVER("unknown source %s\n", words[2]); |
926321d5 DV |
3233 | return -EINVAL; |
3234 | } | |
3235 | ||
3236 | return pipe_crc_set_source(dev, pipe, source); | |
3237 | } | |
3238 | ||
bd9db02f DL |
3239 | static ssize_t display_crc_ctl_write(struct file *file, const char __user *ubuf, |
3240 | size_t len, loff_t *offp) | |
926321d5 DV |
3241 | { |
3242 | struct seq_file *m = file->private_data; | |
3243 | struct drm_device *dev = m->private; | |
3244 | char *tmpbuf; | |
3245 | int ret; | |
3246 | ||
3247 | if (len == 0) | |
3248 | return 0; | |
3249 | ||
3250 | if (len > PAGE_SIZE - 1) { | |
3251 | DRM_DEBUG_DRIVER("expected <%lu bytes into pipe crc control\n", | |
3252 | PAGE_SIZE); | |
3253 | return -E2BIG; | |
3254 | } | |
3255 | ||
3256 | tmpbuf = kmalloc(len + 1, GFP_KERNEL); | |
3257 | if (!tmpbuf) | |
3258 | return -ENOMEM; | |
3259 | ||
3260 | if (copy_from_user(tmpbuf, ubuf, len)) { | |
3261 | ret = -EFAULT; | |
3262 | goto out; | |
3263 | } | |
3264 | tmpbuf[len] = '\0'; | |
3265 | ||
bd9db02f | 3266 | ret = display_crc_ctl_parse(dev, tmpbuf, len); |
926321d5 DV |
3267 | |
3268 | out: | |
3269 | kfree(tmpbuf); | |
3270 | if (ret < 0) | |
3271 | return ret; | |
3272 | ||
3273 | *offp += len; | |
3274 | return len; | |
3275 | } | |
3276 | ||
bd9db02f | 3277 | static const struct file_operations i915_display_crc_ctl_fops = { |
926321d5 | 3278 | .owner = THIS_MODULE, |
bd9db02f | 3279 | .open = display_crc_ctl_open, |
926321d5 DV |
3280 | .read = seq_read, |
3281 | .llseek = seq_lseek, | |
3282 | .release = single_release, | |
bd9db02f | 3283 | .write = display_crc_ctl_write |
926321d5 DV |
3284 | }; |
3285 | ||
369a1342 VS |
3286 | static void wm_latency_show(struct seq_file *m, const uint16_t wm[5]) |
3287 | { | |
3288 | struct drm_device *dev = m->private; | |
546c81fd | 3289 | int num_levels = ilk_wm_max_level(dev) + 1; |
369a1342 VS |
3290 | int level; |
3291 | ||
3292 | drm_modeset_lock_all(dev); | |
3293 | ||
3294 | for (level = 0; level < num_levels; level++) { | |
3295 | unsigned int latency = wm[level]; | |
3296 | ||
3297 | /* WM1+ latency values in 0.5us units */ | |
3298 | if (level > 0) | |
3299 | latency *= 5; | |
3300 | ||
3301 | seq_printf(m, "WM%d %u (%u.%u usec)\n", | |
3302 | level, wm[level], | |
3303 | latency / 10, latency % 10); | |
3304 | } | |
3305 | ||
3306 | drm_modeset_unlock_all(dev); | |
3307 | } | |
3308 | ||
3309 | static int pri_wm_latency_show(struct seq_file *m, void *data) | |
3310 | { | |
3311 | struct drm_device *dev = m->private; | |
3312 | ||
3313 | wm_latency_show(m, to_i915(dev)->wm.pri_latency); | |
3314 | ||
3315 | return 0; | |
3316 | } | |
3317 | ||
3318 | static int spr_wm_latency_show(struct seq_file *m, void *data) | |
3319 | { | |
3320 | struct drm_device *dev = m->private; | |
3321 | ||
3322 | wm_latency_show(m, to_i915(dev)->wm.spr_latency); | |
3323 | ||
3324 | return 0; | |
3325 | } | |
3326 | ||
3327 | static int cur_wm_latency_show(struct seq_file *m, void *data) | |
3328 | { | |
3329 | struct drm_device *dev = m->private; | |
3330 | ||
3331 | wm_latency_show(m, to_i915(dev)->wm.cur_latency); | |
3332 | ||
3333 | return 0; | |
3334 | } | |
3335 | ||
3336 | static int pri_wm_latency_open(struct inode *inode, struct file *file) | |
3337 | { | |
3338 | struct drm_device *dev = inode->i_private; | |
3339 | ||
9ad0257c | 3340 | if (HAS_GMCH_DISPLAY(dev)) |
369a1342 VS |
3341 | return -ENODEV; |
3342 | ||
3343 | return single_open(file, pri_wm_latency_show, dev); | |
3344 | } | |
3345 | ||
3346 | static int spr_wm_latency_open(struct inode *inode, struct file *file) | |
3347 | { | |
3348 | struct drm_device *dev = inode->i_private; | |
3349 | ||
9ad0257c | 3350 | if (HAS_GMCH_DISPLAY(dev)) |
369a1342 VS |
3351 | return -ENODEV; |
3352 | ||
3353 | return single_open(file, spr_wm_latency_show, dev); | |
3354 | } | |
3355 | ||
3356 | static int cur_wm_latency_open(struct inode *inode, struct file *file) | |
3357 | { | |
3358 | struct drm_device *dev = inode->i_private; | |
3359 | ||
9ad0257c | 3360 | if (HAS_GMCH_DISPLAY(dev)) |
369a1342 VS |
3361 | return -ENODEV; |
3362 | ||
3363 | return single_open(file, cur_wm_latency_show, dev); | |
3364 | } | |
3365 | ||
3366 | static ssize_t wm_latency_write(struct file *file, const char __user *ubuf, | |
3367 | size_t len, loff_t *offp, uint16_t wm[5]) | |
3368 | { | |
3369 | struct seq_file *m = file->private_data; | |
3370 | struct drm_device *dev = m->private; | |
3371 | uint16_t new[5] = { 0 }; | |
546c81fd | 3372 | int num_levels = ilk_wm_max_level(dev) + 1; |
369a1342 VS |
3373 | int level; |
3374 | int ret; | |
3375 | char tmp[32]; | |
3376 | ||
3377 | if (len >= sizeof(tmp)) | |
3378 | return -EINVAL; | |
3379 | ||
3380 | if (copy_from_user(tmp, ubuf, len)) | |
3381 | return -EFAULT; | |
3382 | ||
3383 | tmp[len] = '\0'; | |
3384 | ||
3385 | ret = sscanf(tmp, "%hu %hu %hu %hu %hu", &new[0], &new[1], &new[2], &new[3], &new[4]); | |
3386 | if (ret != num_levels) | |
3387 | return -EINVAL; | |
3388 | ||
3389 | drm_modeset_lock_all(dev); | |
3390 | ||
3391 | for (level = 0; level < num_levels; level++) | |
3392 | wm[level] = new[level]; | |
3393 | ||
3394 | drm_modeset_unlock_all(dev); | |
3395 | ||
3396 | return len; | |
3397 | } | |
3398 | ||
3399 | ||
3400 | static ssize_t pri_wm_latency_write(struct file *file, const char __user *ubuf, | |
3401 | size_t len, loff_t *offp) | |
3402 | { | |
3403 | struct seq_file *m = file->private_data; | |
3404 | struct drm_device *dev = m->private; | |
3405 | ||
3406 | return wm_latency_write(file, ubuf, len, offp, to_i915(dev)->wm.pri_latency); | |
3407 | } | |
3408 | ||
3409 | static ssize_t spr_wm_latency_write(struct file *file, const char __user *ubuf, | |
3410 | size_t len, loff_t *offp) | |
3411 | { | |
3412 | struct seq_file *m = file->private_data; | |
3413 | struct drm_device *dev = m->private; | |
3414 | ||
3415 | return wm_latency_write(file, ubuf, len, offp, to_i915(dev)->wm.spr_latency); | |
3416 | } | |
3417 | ||
3418 | static ssize_t cur_wm_latency_write(struct file *file, const char __user *ubuf, | |
3419 | size_t len, loff_t *offp) | |
3420 | { | |
3421 | struct seq_file *m = file->private_data; | |
3422 | struct drm_device *dev = m->private; | |
3423 | ||
3424 | return wm_latency_write(file, ubuf, len, offp, to_i915(dev)->wm.cur_latency); | |
3425 | } | |
3426 | ||
3427 | static const struct file_operations i915_pri_wm_latency_fops = { | |
3428 | .owner = THIS_MODULE, | |
3429 | .open = pri_wm_latency_open, | |
3430 | .read = seq_read, | |
3431 | .llseek = seq_lseek, | |
3432 | .release = single_release, | |
3433 | .write = pri_wm_latency_write | |
3434 | }; | |
3435 | ||
3436 | static const struct file_operations i915_spr_wm_latency_fops = { | |
3437 | .owner = THIS_MODULE, | |
3438 | .open = spr_wm_latency_open, | |
3439 | .read = seq_read, | |
3440 | .llseek = seq_lseek, | |
3441 | .release = single_release, | |
3442 | .write = spr_wm_latency_write | |
3443 | }; | |
3444 | ||
3445 | static const struct file_operations i915_cur_wm_latency_fops = { | |
3446 | .owner = THIS_MODULE, | |
3447 | .open = cur_wm_latency_open, | |
3448 | .read = seq_read, | |
3449 | .llseek = seq_lseek, | |
3450 | .release = single_release, | |
3451 | .write = cur_wm_latency_write | |
3452 | }; | |
3453 | ||
647416f9 KC |
3454 | static int |
3455 | i915_wedged_get(void *data, u64 *val) | |
f3cd474b | 3456 | { |
647416f9 | 3457 | struct drm_device *dev = data; |
e277a1f8 | 3458 | struct drm_i915_private *dev_priv = dev->dev_private; |
f3cd474b | 3459 | |
647416f9 | 3460 | *val = atomic_read(&dev_priv->gpu_error.reset_counter); |
f3cd474b | 3461 | |
647416f9 | 3462 | return 0; |
f3cd474b CW |
3463 | } |
3464 | ||
647416f9 KC |
3465 | static int |
3466 | i915_wedged_set(void *data, u64 val) | |
f3cd474b | 3467 | { |
647416f9 | 3468 | struct drm_device *dev = data; |
d46c0517 ID |
3469 | struct drm_i915_private *dev_priv = dev->dev_private; |
3470 | ||
3471 | intel_runtime_pm_get(dev_priv); | |
f3cd474b | 3472 | |
58174462 MK |
3473 | i915_handle_error(dev, val, |
3474 | "Manually setting wedged to %llu", val); | |
d46c0517 ID |
3475 | |
3476 | intel_runtime_pm_put(dev_priv); | |
3477 | ||
647416f9 | 3478 | return 0; |
f3cd474b CW |
3479 | } |
3480 | ||
647416f9 KC |
3481 | DEFINE_SIMPLE_ATTRIBUTE(i915_wedged_fops, |
3482 | i915_wedged_get, i915_wedged_set, | |
3a3b4f98 | 3483 | "%llu\n"); |
f3cd474b | 3484 | |
647416f9 KC |
3485 | static int |
3486 | i915_ring_stop_get(void *data, u64 *val) | |
e5eb3d63 | 3487 | { |
647416f9 | 3488 | struct drm_device *dev = data; |
e277a1f8 | 3489 | struct drm_i915_private *dev_priv = dev->dev_private; |
e5eb3d63 | 3490 | |
647416f9 | 3491 | *val = dev_priv->gpu_error.stop_rings; |
e5eb3d63 | 3492 | |
647416f9 | 3493 | return 0; |
e5eb3d63 DV |
3494 | } |
3495 | ||
647416f9 KC |
3496 | static int |
3497 | i915_ring_stop_set(void *data, u64 val) | |
e5eb3d63 | 3498 | { |
647416f9 | 3499 | struct drm_device *dev = data; |
e5eb3d63 | 3500 | struct drm_i915_private *dev_priv = dev->dev_private; |
647416f9 | 3501 | int ret; |
e5eb3d63 | 3502 | |
647416f9 | 3503 | DRM_DEBUG_DRIVER("Stopping rings 0x%08llx\n", val); |
e5eb3d63 | 3504 | |
22bcfc6a DV |
3505 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
3506 | if (ret) | |
3507 | return ret; | |
3508 | ||
99584db3 | 3509 | dev_priv->gpu_error.stop_rings = val; |
e5eb3d63 DV |
3510 | mutex_unlock(&dev->struct_mutex); |
3511 | ||
647416f9 | 3512 | return 0; |
e5eb3d63 DV |
3513 | } |
3514 | ||
647416f9 KC |
3515 | DEFINE_SIMPLE_ATTRIBUTE(i915_ring_stop_fops, |
3516 | i915_ring_stop_get, i915_ring_stop_set, | |
3517 | "0x%08llx\n"); | |
d5442303 | 3518 | |
094f9a54 CW |
3519 | static int |
3520 | i915_ring_missed_irq_get(void *data, u64 *val) | |
3521 | { | |
3522 | struct drm_device *dev = data; | |
3523 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3524 | ||
3525 | *val = dev_priv->gpu_error.missed_irq_rings; | |
3526 | return 0; | |
3527 | } | |
3528 | ||
3529 | static int | |
3530 | i915_ring_missed_irq_set(void *data, u64 val) | |
3531 | { | |
3532 | struct drm_device *dev = data; | |
3533 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3534 | int ret; | |
3535 | ||
3536 | /* Lock against concurrent debugfs callers */ | |
3537 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
3538 | if (ret) | |
3539 | return ret; | |
3540 | dev_priv->gpu_error.missed_irq_rings = val; | |
3541 | mutex_unlock(&dev->struct_mutex); | |
3542 | ||
3543 | return 0; | |
3544 | } | |
3545 | ||
3546 | DEFINE_SIMPLE_ATTRIBUTE(i915_ring_missed_irq_fops, | |
3547 | i915_ring_missed_irq_get, i915_ring_missed_irq_set, | |
3548 | "0x%08llx\n"); | |
3549 | ||
3550 | static int | |
3551 | i915_ring_test_irq_get(void *data, u64 *val) | |
3552 | { | |
3553 | struct drm_device *dev = data; | |
3554 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3555 | ||
3556 | *val = dev_priv->gpu_error.test_irq_rings; | |
3557 | ||
3558 | return 0; | |
3559 | } | |
3560 | ||
3561 | static int | |
3562 | i915_ring_test_irq_set(void *data, u64 val) | |
3563 | { | |
3564 | struct drm_device *dev = data; | |
3565 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3566 | int ret; | |
3567 | ||
3568 | DRM_DEBUG_DRIVER("Masking interrupts on rings 0x%08llx\n", val); | |
3569 | ||
3570 | /* Lock against concurrent debugfs callers */ | |
3571 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
3572 | if (ret) | |
3573 | return ret; | |
3574 | ||
3575 | dev_priv->gpu_error.test_irq_rings = val; | |
3576 | mutex_unlock(&dev->struct_mutex); | |
3577 | ||
3578 | return 0; | |
3579 | } | |
3580 | ||
3581 | DEFINE_SIMPLE_ATTRIBUTE(i915_ring_test_irq_fops, | |
3582 | i915_ring_test_irq_get, i915_ring_test_irq_set, | |
3583 | "0x%08llx\n"); | |
3584 | ||
dd624afd CW |
3585 | #define DROP_UNBOUND 0x1 |
3586 | #define DROP_BOUND 0x2 | |
3587 | #define DROP_RETIRE 0x4 | |
3588 | #define DROP_ACTIVE 0x8 | |
3589 | #define DROP_ALL (DROP_UNBOUND | \ | |
3590 | DROP_BOUND | \ | |
3591 | DROP_RETIRE | \ | |
3592 | DROP_ACTIVE) | |
647416f9 KC |
3593 | static int |
3594 | i915_drop_caches_get(void *data, u64 *val) | |
dd624afd | 3595 | { |
647416f9 | 3596 | *val = DROP_ALL; |
dd624afd | 3597 | |
647416f9 | 3598 | return 0; |
dd624afd CW |
3599 | } |
3600 | ||
647416f9 KC |
3601 | static int |
3602 | i915_drop_caches_set(void *data, u64 val) | |
dd624afd | 3603 | { |
647416f9 | 3604 | struct drm_device *dev = data; |
dd624afd CW |
3605 | struct drm_i915_private *dev_priv = dev->dev_private; |
3606 | struct drm_i915_gem_object *obj, *next; | |
ca191b13 BW |
3607 | struct i915_address_space *vm; |
3608 | struct i915_vma *vma, *x; | |
647416f9 | 3609 | int ret; |
dd624afd | 3610 | |
2f9fe5ff | 3611 | DRM_DEBUG("Dropping caches: 0x%08llx\n", val); |
dd624afd CW |
3612 | |
3613 | /* No need to check and wait for gpu resets, only libdrm auto-restarts | |
3614 | * on ioctls on -EAGAIN. */ | |
3615 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
3616 | if (ret) | |
3617 | return ret; | |
3618 | ||
3619 | if (val & DROP_ACTIVE) { | |
3620 | ret = i915_gpu_idle(dev); | |
3621 | if (ret) | |
3622 | goto unlock; | |
3623 | } | |
3624 | ||
3625 | if (val & (DROP_RETIRE | DROP_ACTIVE)) | |
3626 | i915_gem_retire_requests(dev); | |
3627 | ||
3628 | if (val & DROP_BOUND) { | |
ca191b13 BW |
3629 | list_for_each_entry(vm, &dev_priv->vm_list, global_link) { |
3630 | list_for_each_entry_safe(vma, x, &vm->inactive_list, | |
3631 | mm_list) { | |
d7f46fc4 | 3632 | if (vma->pin_count) |
ca191b13 BW |
3633 | continue; |
3634 | ||
3635 | ret = i915_vma_unbind(vma); | |
3636 | if (ret) | |
3637 | goto unlock; | |
3638 | } | |
31a46c9c | 3639 | } |
dd624afd CW |
3640 | } |
3641 | ||
3642 | if (val & DROP_UNBOUND) { | |
35c20a60 BW |
3643 | list_for_each_entry_safe(obj, next, &dev_priv->mm.unbound_list, |
3644 | global_list) | |
dd624afd CW |
3645 | if (obj->pages_pin_count == 0) { |
3646 | ret = i915_gem_object_put_pages(obj); | |
3647 | if (ret) | |
3648 | goto unlock; | |
3649 | } | |
3650 | } | |
3651 | ||
3652 | unlock: | |
3653 | mutex_unlock(&dev->struct_mutex); | |
3654 | ||
647416f9 | 3655 | return ret; |
dd624afd CW |
3656 | } |
3657 | ||
647416f9 KC |
3658 | DEFINE_SIMPLE_ATTRIBUTE(i915_drop_caches_fops, |
3659 | i915_drop_caches_get, i915_drop_caches_set, | |
3660 | "0x%08llx\n"); | |
dd624afd | 3661 | |
647416f9 KC |
3662 | static int |
3663 | i915_max_freq_get(void *data, u64 *val) | |
358733e9 | 3664 | { |
647416f9 | 3665 | struct drm_device *dev = data; |
e277a1f8 | 3666 | struct drm_i915_private *dev_priv = dev->dev_private; |
647416f9 | 3667 | int ret; |
004777cb | 3668 | |
daa3afb2 | 3669 | if (INTEL_INFO(dev)->gen < 6) |
004777cb DV |
3670 | return -ENODEV; |
3671 | ||
5c9669ce TR |
3672 | flush_delayed_work(&dev_priv->rps.delayed_resume_work); |
3673 | ||
4fc688ce | 3674 | ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock); |
004777cb DV |
3675 | if (ret) |
3676 | return ret; | |
358733e9 | 3677 | |
0a073b84 | 3678 | if (IS_VALLEYVIEW(dev)) |
b39fb297 | 3679 | *val = vlv_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit); |
0a073b84 | 3680 | else |
b39fb297 | 3681 | *val = dev_priv->rps.max_freq_softlimit * GT_FREQUENCY_MULTIPLIER; |
4fc688ce | 3682 | mutex_unlock(&dev_priv->rps.hw_lock); |
358733e9 | 3683 | |
647416f9 | 3684 | return 0; |
358733e9 JB |
3685 | } |
3686 | ||
647416f9 KC |
3687 | static int |
3688 | i915_max_freq_set(void *data, u64 val) | |
358733e9 | 3689 | { |
647416f9 | 3690 | struct drm_device *dev = data; |
358733e9 | 3691 | struct drm_i915_private *dev_priv = dev->dev_private; |
dd0a1aa1 | 3692 | u32 rp_state_cap, hw_max, hw_min; |
647416f9 | 3693 | int ret; |
004777cb | 3694 | |
daa3afb2 | 3695 | if (INTEL_INFO(dev)->gen < 6) |
004777cb | 3696 | return -ENODEV; |
358733e9 | 3697 | |
5c9669ce TR |
3698 | flush_delayed_work(&dev_priv->rps.delayed_resume_work); |
3699 | ||
647416f9 | 3700 | DRM_DEBUG_DRIVER("Manually setting max freq to %llu\n", val); |
358733e9 | 3701 | |
4fc688ce | 3702 | ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock); |
004777cb DV |
3703 | if (ret) |
3704 | return ret; | |
3705 | ||
358733e9 JB |
3706 | /* |
3707 | * Turbo will still be enabled, but won't go above the set value. | |
3708 | */ | |
0a073b84 | 3709 | if (IS_VALLEYVIEW(dev)) { |
2ec3815f | 3710 | val = vlv_freq_opcode(dev_priv, val); |
dd0a1aa1 | 3711 | |
03af2045 VS |
3712 | hw_max = dev_priv->rps.max_freq; |
3713 | hw_min = dev_priv->rps.min_freq; | |
0a073b84 JB |
3714 | } else { |
3715 | do_div(val, GT_FREQUENCY_MULTIPLIER); | |
dd0a1aa1 JM |
3716 | |
3717 | rp_state_cap = I915_READ(GEN6_RP_STATE_CAP); | |
b39fb297 | 3718 | hw_max = dev_priv->rps.max_freq; |
dd0a1aa1 JM |
3719 | hw_min = (rp_state_cap >> 16) & 0xff; |
3720 | } | |
3721 | ||
b39fb297 | 3722 | if (val < hw_min || val > hw_max || val < dev_priv->rps.min_freq_softlimit) { |
dd0a1aa1 JM |
3723 | mutex_unlock(&dev_priv->rps.hw_lock); |
3724 | return -EINVAL; | |
0a073b84 JB |
3725 | } |
3726 | ||
b39fb297 | 3727 | dev_priv->rps.max_freq_softlimit = val; |
dd0a1aa1 JM |
3728 | |
3729 | if (IS_VALLEYVIEW(dev)) | |
3730 | valleyview_set_rps(dev, val); | |
3731 | else | |
3732 | gen6_set_rps(dev, val); | |
3733 | ||
4fc688ce | 3734 | mutex_unlock(&dev_priv->rps.hw_lock); |
358733e9 | 3735 | |
647416f9 | 3736 | return 0; |
358733e9 JB |
3737 | } |
3738 | ||
647416f9 KC |
3739 | DEFINE_SIMPLE_ATTRIBUTE(i915_max_freq_fops, |
3740 | i915_max_freq_get, i915_max_freq_set, | |
3a3b4f98 | 3741 | "%llu\n"); |
358733e9 | 3742 | |
647416f9 KC |
3743 | static int |
3744 | i915_min_freq_get(void *data, u64 *val) | |
1523c310 | 3745 | { |
647416f9 | 3746 | struct drm_device *dev = data; |
e277a1f8 | 3747 | struct drm_i915_private *dev_priv = dev->dev_private; |
647416f9 | 3748 | int ret; |
004777cb | 3749 | |
daa3afb2 | 3750 | if (INTEL_INFO(dev)->gen < 6) |
004777cb DV |
3751 | return -ENODEV; |
3752 | ||
5c9669ce TR |
3753 | flush_delayed_work(&dev_priv->rps.delayed_resume_work); |
3754 | ||
4fc688ce | 3755 | ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock); |
004777cb DV |
3756 | if (ret) |
3757 | return ret; | |
1523c310 | 3758 | |
0a073b84 | 3759 | if (IS_VALLEYVIEW(dev)) |
b39fb297 | 3760 | *val = vlv_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit); |
0a073b84 | 3761 | else |
b39fb297 | 3762 | *val = dev_priv->rps.min_freq_softlimit * GT_FREQUENCY_MULTIPLIER; |
4fc688ce | 3763 | mutex_unlock(&dev_priv->rps.hw_lock); |
1523c310 | 3764 | |
647416f9 | 3765 | return 0; |
1523c310 JB |
3766 | } |
3767 | ||
647416f9 KC |
3768 | static int |
3769 | i915_min_freq_set(void *data, u64 val) | |
1523c310 | 3770 | { |
647416f9 | 3771 | struct drm_device *dev = data; |
1523c310 | 3772 | struct drm_i915_private *dev_priv = dev->dev_private; |
dd0a1aa1 | 3773 | u32 rp_state_cap, hw_max, hw_min; |
647416f9 | 3774 | int ret; |
004777cb | 3775 | |
daa3afb2 | 3776 | if (INTEL_INFO(dev)->gen < 6) |
004777cb | 3777 | return -ENODEV; |
1523c310 | 3778 | |
5c9669ce TR |
3779 | flush_delayed_work(&dev_priv->rps.delayed_resume_work); |
3780 | ||
647416f9 | 3781 | DRM_DEBUG_DRIVER("Manually setting min freq to %llu\n", val); |
1523c310 | 3782 | |
4fc688ce | 3783 | ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock); |
004777cb DV |
3784 | if (ret) |
3785 | return ret; | |
3786 | ||
1523c310 JB |
3787 | /* |
3788 | * Turbo will still be enabled, but won't go below the set value. | |
3789 | */ | |
0a073b84 | 3790 | if (IS_VALLEYVIEW(dev)) { |
2ec3815f | 3791 | val = vlv_freq_opcode(dev_priv, val); |
dd0a1aa1 | 3792 | |
03af2045 VS |
3793 | hw_max = dev_priv->rps.max_freq; |
3794 | hw_min = dev_priv->rps.min_freq; | |
0a073b84 JB |
3795 | } else { |
3796 | do_div(val, GT_FREQUENCY_MULTIPLIER); | |
dd0a1aa1 JM |
3797 | |
3798 | rp_state_cap = I915_READ(GEN6_RP_STATE_CAP); | |
b39fb297 | 3799 | hw_max = dev_priv->rps.max_freq; |
dd0a1aa1 JM |
3800 | hw_min = (rp_state_cap >> 16) & 0xff; |
3801 | } | |
3802 | ||
b39fb297 | 3803 | if (val < hw_min || val > hw_max || val > dev_priv->rps.max_freq_softlimit) { |
dd0a1aa1 JM |
3804 | mutex_unlock(&dev_priv->rps.hw_lock); |
3805 | return -EINVAL; | |
0a073b84 | 3806 | } |
dd0a1aa1 | 3807 | |
b39fb297 | 3808 | dev_priv->rps.min_freq_softlimit = val; |
dd0a1aa1 JM |
3809 | |
3810 | if (IS_VALLEYVIEW(dev)) | |
3811 | valleyview_set_rps(dev, val); | |
3812 | else | |
3813 | gen6_set_rps(dev, val); | |
3814 | ||
4fc688ce | 3815 | mutex_unlock(&dev_priv->rps.hw_lock); |
1523c310 | 3816 | |
647416f9 | 3817 | return 0; |
1523c310 JB |
3818 | } |
3819 | ||
647416f9 KC |
3820 | DEFINE_SIMPLE_ATTRIBUTE(i915_min_freq_fops, |
3821 | i915_min_freq_get, i915_min_freq_set, | |
3a3b4f98 | 3822 | "%llu\n"); |
1523c310 | 3823 | |
647416f9 KC |
3824 | static int |
3825 | i915_cache_sharing_get(void *data, u64 *val) | |
07b7ddd9 | 3826 | { |
647416f9 | 3827 | struct drm_device *dev = data; |
e277a1f8 | 3828 | struct drm_i915_private *dev_priv = dev->dev_private; |
07b7ddd9 | 3829 | u32 snpcr; |
647416f9 | 3830 | int ret; |
07b7ddd9 | 3831 | |
004777cb DV |
3832 | if (!(IS_GEN6(dev) || IS_GEN7(dev))) |
3833 | return -ENODEV; | |
3834 | ||
22bcfc6a DV |
3835 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
3836 | if (ret) | |
3837 | return ret; | |
c8c8fb33 | 3838 | intel_runtime_pm_get(dev_priv); |
22bcfc6a | 3839 | |
07b7ddd9 | 3840 | snpcr = I915_READ(GEN6_MBCUNIT_SNPCR); |
c8c8fb33 PZ |
3841 | |
3842 | intel_runtime_pm_put(dev_priv); | |
07b7ddd9 JB |
3843 | mutex_unlock(&dev_priv->dev->struct_mutex); |
3844 | ||
647416f9 | 3845 | *val = (snpcr & GEN6_MBC_SNPCR_MASK) >> GEN6_MBC_SNPCR_SHIFT; |
07b7ddd9 | 3846 | |
647416f9 | 3847 | return 0; |
07b7ddd9 JB |
3848 | } |
3849 | ||
647416f9 KC |
3850 | static int |
3851 | i915_cache_sharing_set(void *data, u64 val) | |
07b7ddd9 | 3852 | { |
647416f9 | 3853 | struct drm_device *dev = data; |
07b7ddd9 | 3854 | struct drm_i915_private *dev_priv = dev->dev_private; |
07b7ddd9 | 3855 | u32 snpcr; |
07b7ddd9 | 3856 | |
004777cb DV |
3857 | if (!(IS_GEN6(dev) || IS_GEN7(dev))) |
3858 | return -ENODEV; | |
3859 | ||
647416f9 | 3860 | if (val > 3) |
07b7ddd9 JB |
3861 | return -EINVAL; |
3862 | ||
c8c8fb33 | 3863 | intel_runtime_pm_get(dev_priv); |
647416f9 | 3864 | DRM_DEBUG_DRIVER("Manually setting uncore sharing to %llu\n", val); |
07b7ddd9 JB |
3865 | |
3866 | /* Update the cache sharing policy here as well */ | |
3867 | snpcr = I915_READ(GEN6_MBCUNIT_SNPCR); | |
3868 | snpcr &= ~GEN6_MBC_SNPCR_MASK; | |
3869 | snpcr |= (val << GEN6_MBC_SNPCR_SHIFT); | |
3870 | I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr); | |
3871 | ||
c8c8fb33 | 3872 | intel_runtime_pm_put(dev_priv); |
647416f9 | 3873 | return 0; |
07b7ddd9 JB |
3874 | } |
3875 | ||
647416f9 KC |
3876 | DEFINE_SIMPLE_ATTRIBUTE(i915_cache_sharing_fops, |
3877 | i915_cache_sharing_get, i915_cache_sharing_set, | |
3878 | "%llu\n"); | |
07b7ddd9 | 3879 | |
6d794d42 BW |
3880 | static int i915_forcewake_open(struct inode *inode, struct file *file) |
3881 | { | |
3882 | struct drm_device *dev = inode->i_private; | |
3883 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6d794d42 | 3884 | |
075edca4 | 3885 | if (INTEL_INFO(dev)->gen < 6) |
6d794d42 BW |
3886 | return 0; |
3887 | ||
c8d9a590 | 3888 | gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL); |
6d794d42 BW |
3889 | |
3890 | return 0; | |
3891 | } | |
3892 | ||
c43b5634 | 3893 | static int i915_forcewake_release(struct inode *inode, struct file *file) |
6d794d42 BW |
3894 | { |
3895 | struct drm_device *dev = inode->i_private; | |
3896 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3897 | ||
075edca4 | 3898 | if (INTEL_INFO(dev)->gen < 6) |
6d794d42 BW |
3899 | return 0; |
3900 | ||
c8d9a590 | 3901 | gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL); |
6d794d42 BW |
3902 | |
3903 | return 0; | |
3904 | } | |
3905 | ||
3906 | static const struct file_operations i915_forcewake_fops = { | |
3907 | .owner = THIS_MODULE, | |
3908 | .open = i915_forcewake_open, | |
3909 | .release = i915_forcewake_release, | |
3910 | }; | |
3911 | ||
3912 | static int i915_forcewake_create(struct dentry *root, struct drm_minor *minor) | |
3913 | { | |
3914 | struct drm_device *dev = minor->dev; | |
3915 | struct dentry *ent; | |
3916 | ||
3917 | ent = debugfs_create_file("i915_forcewake_user", | |
8eb57294 | 3918 | S_IRUSR, |
6d794d42 BW |
3919 | root, dev, |
3920 | &i915_forcewake_fops); | |
f3c5fe97 WY |
3921 | if (!ent) |
3922 | return -ENOMEM; | |
6d794d42 | 3923 | |
8eb57294 | 3924 | return drm_add_fake_info_node(minor, ent, &i915_forcewake_fops); |
6d794d42 BW |
3925 | } |
3926 | ||
6a9c308d DV |
3927 | static int i915_debugfs_create(struct dentry *root, |
3928 | struct drm_minor *minor, | |
3929 | const char *name, | |
3930 | const struct file_operations *fops) | |
07b7ddd9 JB |
3931 | { |
3932 | struct drm_device *dev = minor->dev; | |
3933 | struct dentry *ent; | |
3934 | ||
6a9c308d | 3935 | ent = debugfs_create_file(name, |
07b7ddd9 JB |
3936 | S_IRUGO | S_IWUSR, |
3937 | root, dev, | |
6a9c308d | 3938 | fops); |
f3c5fe97 WY |
3939 | if (!ent) |
3940 | return -ENOMEM; | |
07b7ddd9 | 3941 | |
6a9c308d | 3942 | return drm_add_fake_info_node(minor, ent, fops); |
07b7ddd9 JB |
3943 | } |
3944 | ||
06c5bf8c | 3945 | static const struct drm_info_list i915_debugfs_list[] = { |
311bd68e | 3946 | {"i915_capabilities", i915_capabilities, 0}, |
73aa808f | 3947 | {"i915_gem_objects", i915_gem_object_info, 0}, |
08c18323 | 3948 | {"i915_gem_gtt", i915_gem_gtt_info, 0}, |
1b50247a | 3949 | {"i915_gem_pinned", i915_gem_gtt_info, 0, (void *) PINNED_LIST}, |
433e12f7 | 3950 | {"i915_gem_active", i915_gem_object_list_info, 0, (void *) ACTIVE_LIST}, |
433e12f7 | 3951 | {"i915_gem_inactive", i915_gem_object_list_info, 0, (void *) INACTIVE_LIST}, |
6d2b8885 | 3952 | {"i915_gem_stolen", i915_gem_stolen_list_info }, |
4e5359cd | 3953 | {"i915_gem_pageflip", i915_gem_pageflip_info, 0}, |
2017263e BG |
3954 | {"i915_gem_request", i915_gem_request_info, 0}, |
3955 | {"i915_gem_seqno", i915_gem_seqno_info, 0}, | |
a6172a80 | 3956 | {"i915_gem_fence_regs", i915_gem_fence_regs_info, 0}, |
2017263e | 3957 | {"i915_gem_interrupt", i915_interrupt_info, 0}, |
1ec14ad3 CW |
3958 | {"i915_gem_hws", i915_hws_info, 0, (void *)RCS}, |
3959 | {"i915_gem_hws_blt", i915_hws_info, 0, (void *)BCS}, | |
3960 | {"i915_gem_hws_bsd", i915_hws_info, 0, (void *)VCS}, | |
9010ebfd | 3961 | {"i915_gem_hws_vebox", i915_hws_info, 0, (void *)VECS}, |
adb4bd12 | 3962 | {"i915_frequency_info", i915_frequency_info, 0}, |
f97108d1 | 3963 | {"i915_drpc_info", i915_drpc_info, 0}, |
7648fa99 | 3964 | {"i915_emon_status", i915_emon_status, 0}, |
23b2f8bb | 3965 | {"i915_ring_freq_table", i915_ring_freq_table, 0}, |
b5e50c3f | 3966 | {"i915_fbc_status", i915_fbc_status, 0}, |
92d44621 | 3967 | {"i915_ips_status", i915_ips_status, 0}, |
4a9bef37 | 3968 | {"i915_sr_status", i915_sr_status, 0}, |
44834a67 | 3969 | {"i915_opregion", i915_opregion, 0}, |
37811fcc | 3970 | {"i915_gem_framebuffer", i915_gem_framebuffer_info, 0}, |
e76d3630 | 3971 | {"i915_context_status", i915_context_status, 0}, |
6d794d42 | 3972 | {"i915_gen6_forcewake_count", i915_gen6_forcewake_count_info, 0}, |
ea16a3cd | 3973 | {"i915_swizzle_info", i915_swizzle_info, 0}, |
3cf17fc5 | 3974 | {"i915_ppgtt_info", i915_ppgtt_info, 0}, |
63573eb7 | 3975 | {"i915_llc", i915_llc, 0}, |
e91fd8c6 | 3976 | {"i915_edp_psr_status", i915_edp_psr_status, 0}, |
d2e216d0 | 3977 | {"i915_sink_crc_eDP1", i915_sink_crc, 0}, |
ec013e7f | 3978 | {"i915_energy_uJ", i915_energy_uJ, 0}, |
371db66a | 3979 | {"i915_pc8_status", i915_pc8_status, 0}, |
1da51581 | 3980 | {"i915_power_domain_info", i915_power_domain_info, 0}, |
53f5e3ca | 3981 | {"i915_display_info", i915_display_info, 0}, |
e04934cf | 3982 | {"i915_semaphore_status", i915_semaphore_status, 0}, |
728e29d7 | 3983 | {"i915_shared_dplls_info", i915_shared_dplls_info, 0}, |
11bed958 | 3984 | {"i915_dp_mst_info", i915_dp_mst_info, 0}, |
2017263e | 3985 | }; |
27c202ad | 3986 | #define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list) |
2017263e | 3987 | |
06c5bf8c | 3988 | static const struct i915_debugfs_files { |
34b9674c DV |
3989 | const char *name; |
3990 | const struct file_operations *fops; | |
3991 | } i915_debugfs_files[] = { | |
3992 | {"i915_wedged", &i915_wedged_fops}, | |
3993 | {"i915_max_freq", &i915_max_freq_fops}, | |
3994 | {"i915_min_freq", &i915_min_freq_fops}, | |
3995 | {"i915_cache_sharing", &i915_cache_sharing_fops}, | |
3996 | {"i915_ring_stop", &i915_ring_stop_fops}, | |
094f9a54 CW |
3997 | {"i915_ring_missed_irq", &i915_ring_missed_irq_fops}, |
3998 | {"i915_ring_test_irq", &i915_ring_test_irq_fops}, | |
34b9674c DV |
3999 | {"i915_gem_drop_caches", &i915_drop_caches_fops}, |
4000 | {"i915_error_state", &i915_error_state_fops}, | |
4001 | {"i915_next_seqno", &i915_next_seqno_fops}, | |
bd9db02f | 4002 | {"i915_display_crc_ctl", &i915_display_crc_ctl_fops}, |
369a1342 VS |
4003 | {"i915_pri_wm_latency", &i915_pri_wm_latency_fops}, |
4004 | {"i915_spr_wm_latency", &i915_spr_wm_latency_fops}, | |
4005 | {"i915_cur_wm_latency", &i915_cur_wm_latency_fops}, | |
da46f936 | 4006 | {"i915_fbc_false_color", &i915_fbc_fc_fops}, |
34b9674c DV |
4007 | }; |
4008 | ||
07144428 DL |
4009 | void intel_display_crc_init(struct drm_device *dev) |
4010 | { | |
4011 | struct drm_i915_private *dev_priv = dev->dev_private; | |
b378360e | 4012 | enum pipe pipe; |
07144428 | 4013 | |
b378360e DV |
4014 | for_each_pipe(pipe) { |
4015 | struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe]; | |
07144428 | 4016 | |
d538bbdf DL |
4017 | pipe_crc->opened = false; |
4018 | spin_lock_init(&pipe_crc->lock); | |
07144428 DL |
4019 | init_waitqueue_head(&pipe_crc->wq); |
4020 | } | |
4021 | } | |
4022 | ||
27c202ad | 4023 | int i915_debugfs_init(struct drm_minor *minor) |
2017263e | 4024 | { |
34b9674c | 4025 | int ret, i; |
f3cd474b | 4026 | |
6d794d42 | 4027 | ret = i915_forcewake_create(minor->debugfs_root, minor); |
358733e9 JB |
4028 | if (ret) |
4029 | return ret; | |
6a9c308d | 4030 | |
07144428 DL |
4031 | for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) { |
4032 | ret = i915_pipe_crc_create(minor->debugfs_root, minor, i); | |
4033 | if (ret) | |
4034 | return ret; | |
4035 | } | |
4036 | ||
34b9674c DV |
4037 | for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) { |
4038 | ret = i915_debugfs_create(minor->debugfs_root, minor, | |
4039 | i915_debugfs_files[i].name, | |
4040 | i915_debugfs_files[i].fops); | |
4041 | if (ret) | |
4042 | return ret; | |
4043 | } | |
40633219 | 4044 | |
27c202ad BG |
4045 | return drm_debugfs_create_files(i915_debugfs_list, |
4046 | I915_DEBUGFS_ENTRIES, | |
2017263e BG |
4047 | minor->debugfs_root, minor); |
4048 | } | |
4049 | ||
27c202ad | 4050 | void i915_debugfs_cleanup(struct drm_minor *minor) |
2017263e | 4051 | { |
34b9674c DV |
4052 | int i; |
4053 | ||
27c202ad BG |
4054 | drm_debugfs_remove_files(i915_debugfs_list, |
4055 | I915_DEBUGFS_ENTRIES, minor); | |
07144428 | 4056 | |
6d794d42 BW |
4057 | drm_debugfs_remove_files((struct drm_info_list *) &i915_forcewake_fops, |
4058 | 1, minor); | |
07144428 | 4059 | |
e309a997 | 4060 | for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) { |
07144428 DL |
4061 | struct drm_info_list *info_list = |
4062 | (struct drm_info_list *)&i915_pipe_crc_data[i]; | |
4063 | ||
4064 | drm_debugfs_remove_files(info_list, 1, minor); | |
4065 | } | |
4066 | ||
34b9674c DV |
4067 | for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) { |
4068 | struct drm_info_list *info_list = | |
4069 | (struct drm_info_list *) i915_debugfs_files[i].fops; | |
4070 | ||
4071 | drm_debugfs_remove_files(info_list, 1, minor); | |
4072 | } | |
2017263e | 4073 | } |