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1da177e4 LT |
1 | /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*- |
2 | */ | |
0d6aa60b | 3 | /* |
bc54fd1a | 4 | * |
1da177e4 LT |
5 | * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. |
6 | * All Rights Reserved. | |
bc54fd1a DA |
7 | * |
8 | * Permission is hereby granted, free of charge, to any person obtaining a | |
9 | * copy of this software and associated documentation files (the | |
10 | * "Software"), to deal in the Software without restriction, including | |
11 | * without limitation the rights to use, copy, modify, merge, publish, | |
12 | * distribute, sub license, and/or sell copies of the Software, and to | |
13 | * permit persons to whom the Software is furnished to do so, subject to | |
14 | * the following conditions: | |
15 | * | |
16 | * The above copyright notice and this permission notice (including the | |
17 | * next paragraph) shall be included in all copies or substantial portions | |
18 | * of the Software. | |
19 | * | |
20 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS | |
21 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
22 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. | |
23 | * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR | |
24 | * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, | |
25 | * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE | |
26 | * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. | |
27 | * | |
0d6aa60b | 28 | */ |
1da177e4 | 29 | |
5669fcac | 30 | #include <linux/device.h> |
1da177e4 LT |
31 | #include "drmP.h" |
32 | #include "drm.h" | |
33 | #include "i915_drm.h" | |
34 | #include "i915_drv.h" | |
f49f0586 | 35 | #include "intel_drv.h" |
1da177e4 | 36 | |
79e53945 | 37 | #include <linux/console.h> |
354ff967 | 38 | #include "drm_crtc_helper.h" |
79e53945 | 39 | |
d6073d77 | 40 | static int i915_modeset = -1; |
79e53945 JB |
41 | module_param_named(modeset, i915_modeset, int, 0400); |
42 | ||
43 | unsigned int i915_fbpercrtc = 0; | |
44 | module_param_named(fbpercrtc, i915_fbpercrtc, int, 0400); | |
1da177e4 | 45 | |
652c393a | 46 | unsigned int i915_powersave = 1; |
0aa99277 | 47 | module_param_named(powersave, i915_powersave, int, 0600); |
652c393a | 48 | |
33814341 JB |
49 | unsigned int i915_lvds_downclock = 0; |
50 | module_param_named(lvds_downclock, i915_lvds_downclock, int, 0400); | |
51 | ||
a7615030 CW |
52 | unsigned int i915_panel_use_ssc = 1; |
53 | module_param_named(lvds_use_ssc, i915_panel_use_ssc, int, 0600); | |
54 | ||
d78cb50b CW |
55 | bool i915_try_reset = true; |
56 | module_param_named(reset, i915_try_reset, bool, 0600); | |
57 | ||
112b715e | 58 | static struct drm_driver driver; |
1f7a6e37 | 59 | extern int intel_agp_enabled; |
112b715e | 60 | |
cfdf1fa2 | 61 | #define INTEL_VGA_DEVICE(id, info) { \ |
49ae35f2 | 62 | .class = PCI_CLASS_DISPLAY_VGA << 8, \ |
934f992c | 63 | .class_mask = 0xff0000, \ |
49ae35f2 KH |
64 | .vendor = 0x8086, \ |
65 | .device = id, \ | |
66 | .subvendor = PCI_ANY_ID, \ | |
67 | .subdevice = PCI_ANY_ID, \ | |
cfdf1fa2 KH |
68 | .driver_data = (unsigned long) info } |
69 | ||
9a7e8492 | 70 | static const struct intel_device_info intel_i830_info = { |
a6c45cf0 | 71 | .gen = 2, .is_mobile = 1, .cursor_needs_physical = 1, |
31578148 | 72 | .has_overlay = 1, .overlay_needs_physical = 1, |
cfdf1fa2 KH |
73 | }; |
74 | ||
9a7e8492 | 75 | static const struct intel_device_info intel_845g_info = { |
a6c45cf0 | 76 | .gen = 2, |
31578148 | 77 | .has_overlay = 1, .overlay_needs_physical = 1, |
cfdf1fa2 KH |
78 | }; |
79 | ||
9a7e8492 | 80 | static const struct intel_device_info intel_i85x_info = { |
a6c45cf0 | 81 | .gen = 2, .is_i85x = 1, .is_mobile = 1, |
5ce8ba7c | 82 | .cursor_needs_physical = 1, |
31578148 | 83 | .has_overlay = 1, .overlay_needs_physical = 1, |
cfdf1fa2 KH |
84 | }; |
85 | ||
9a7e8492 | 86 | static const struct intel_device_info intel_i865g_info = { |
a6c45cf0 | 87 | .gen = 2, |
31578148 | 88 | .has_overlay = 1, .overlay_needs_physical = 1, |
cfdf1fa2 KH |
89 | }; |
90 | ||
9a7e8492 | 91 | static const struct intel_device_info intel_i915g_info = { |
a6c45cf0 | 92 | .gen = 3, .is_i915g = 1, .cursor_needs_physical = 1, |
31578148 | 93 | .has_overlay = 1, .overlay_needs_physical = 1, |
cfdf1fa2 | 94 | }; |
9a7e8492 | 95 | static const struct intel_device_info intel_i915gm_info = { |
a6c45cf0 | 96 | .gen = 3, .is_mobile = 1, |
b295d1b6 | 97 | .cursor_needs_physical = 1, |
31578148 | 98 | .has_overlay = 1, .overlay_needs_physical = 1, |
a6c45cf0 | 99 | .supports_tv = 1, |
cfdf1fa2 | 100 | }; |
9a7e8492 | 101 | static const struct intel_device_info intel_i945g_info = { |
a6c45cf0 | 102 | .gen = 3, .has_hotplug = 1, .cursor_needs_physical = 1, |
31578148 | 103 | .has_overlay = 1, .overlay_needs_physical = 1, |
cfdf1fa2 | 104 | }; |
9a7e8492 | 105 | static const struct intel_device_info intel_i945gm_info = { |
a6c45cf0 | 106 | .gen = 3, .is_i945gm = 1, .is_mobile = 1, |
b295d1b6 | 107 | .has_hotplug = 1, .cursor_needs_physical = 1, |
31578148 | 108 | .has_overlay = 1, .overlay_needs_physical = 1, |
a6c45cf0 | 109 | .supports_tv = 1, |
cfdf1fa2 KH |
110 | }; |
111 | ||
9a7e8492 | 112 | static const struct intel_device_info intel_i965g_info = { |
a6c45cf0 | 113 | .gen = 4, .is_broadwater = 1, |
c96c3a8c | 114 | .has_hotplug = 1, |
31578148 | 115 | .has_overlay = 1, |
cfdf1fa2 KH |
116 | }; |
117 | ||
9a7e8492 | 118 | static const struct intel_device_info intel_i965gm_info = { |
a6c45cf0 | 119 | .gen = 4, .is_crestline = 1, |
e3c4e5dd | 120 | .is_mobile = 1, .has_fbc = 1, .has_hotplug = 1, |
31578148 | 121 | .has_overlay = 1, |
a6c45cf0 | 122 | .supports_tv = 1, |
cfdf1fa2 KH |
123 | }; |
124 | ||
9a7e8492 | 125 | static const struct intel_device_info intel_g33_info = { |
a6c45cf0 | 126 | .gen = 3, .is_g33 = 1, |
c96c3a8c | 127 | .need_gfx_hws = 1, .has_hotplug = 1, |
31578148 | 128 | .has_overlay = 1, |
cfdf1fa2 KH |
129 | }; |
130 | ||
9a7e8492 | 131 | static const struct intel_device_info intel_g45_info = { |
a6c45cf0 | 132 | .gen = 4, .is_g4x = 1, .need_gfx_hws = 1, |
c96c3a8c | 133 | .has_pipe_cxsr = 1, .has_hotplug = 1, |
92f49d9c | 134 | .has_bsd_ring = 1, |
cfdf1fa2 KH |
135 | }; |
136 | ||
9a7e8492 | 137 | static const struct intel_device_info intel_gm45_info = { |
a6c45cf0 | 138 | .gen = 4, .is_g4x = 1, |
e3c4e5dd | 139 | .is_mobile = 1, .need_gfx_hws = 1, .has_fbc = 1, |
c96c3a8c | 140 | .has_pipe_cxsr = 1, .has_hotplug = 1, |
a6c45cf0 | 141 | .supports_tv = 1, |
92f49d9c | 142 | .has_bsd_ring = 1, |
cfdf1fa2 KH |
143 | }; |
144 | ||
9a7e8492 | 145 | static const struct intel_device_info intel_pineview_info = { |
a6c45cf0 | 146 | .gen = 3, .is_g33 = 1, .is_pineview = 1, .is_mobile = 1, |
c96c3a8c | 147 | .need_gfx_hws = 1, .has_hotplug = 1, |
31578148 | 148 | .has_overlay = 1, |
cfdf1fa2 KH |
149 | }; |
150 | ||
9a7e8492 | 151 | static const struct intel_device_info intel_ironlake_d_info = { |
f00a3ddf | 152 | .gen = 5, |
c96c3a8c | 153 | .need_gfx_hws = 1, .has_pipe_cxsr = 1, .has_hotplug = 1, |
92f49d9c | 154 | .has_bsd_ring = 1, |
cfdf1fa2 KH |
155 | }; |
156 | ||
9a7e8492 | 157 | static const struct intel_device_info intel_ironlake_m_info = { |
f00a3ddf | 158 | .gen = 5, .is_mobile = 1, |
e3c4e5dd | 159 | .need_gfx_hws = 1, .has_hotplug = 1, |
16c59ef3 | 160 | .has_fbc = 0, /* disabled due to buggy hardware */ |
92f49d9c | 161 | .has_bsd_ring = 1, |
cfdf1fa2 KH |
162 | }; |
163 | ||
9a7e8492 | 164 | static const struct intel_device_info intel_sandybridge_d_info = { |
a6c45cf0 | 165 | .gen = 6, |
c96c3a8c | 166 | .need_gfx_hws = 1, .has_hotplug = 1, |
881f47b6 | 167 | .has_bsd_ring = 1, |
549f7365 | 168 | .has_blt_ring = 1, |
f6e450a6 EA |
169 | }; |
170 | ||
9a7e8492 | 171 | static const struct intel_device_info intel_sandybridge_m_info = { |
a6c45cf0 | 172 | .gen = 6, .is_mobile = 1, |
c96c3a8c | 173 | .need_gfx_hws = 1, .has_hotplug = 1, |
9c04f015 | 174 | .has_fbc = 1, |
881f47b6 | 175 | .has_bsd_ring = 1, |
549f7365 | 176 | .has_blt_ring = 1, |
a13e4093 EA |
177 | }; |
178 | ||
6103da0d CW |
179 | static const struct pci_device_id pciidlist[] = { /* aka */ |
180 | INTEL_VGA_DEVICE(0x3577, &intel_i830_info), /* I830_M */ | |
181 | INTEL_VGA_DEVICE(0x2562, &intel_845g_info), /* 845_G */ | |
182 | INTEL_VGA_DEVICE(0x3582, &intel_i85x_info), /* I855_GM */ | |
5ce8ba7c | 183 | INTEL_VGA_DEVICE(0x358e, &intel_i85x_info), |
6103da0d CW |
184 | INTEL_VGA_DEVICE(0x2572, &intel_i865g_info), /* I865_G */ |
185 | INTEL_VGA_DEVICE(0x2582, &intel_i915g_info), /* I915_G */ | |
186 | INTEL_VGA_DEVICE(0x258a, &intel_i915g_info), /* E7221_G */ | |
187 | INTEL_VGA_DEVICE(0x2592, &intel_i915gm_info), /* I915_GM */ | |
188 | INTEL_VGA_DEVICE(0x2772, &intel_i945g_info), /* I945_G */ | |
189 | INTEL_VGA_DEVICE(0x27a2, &intel_i945gm_info), /* I945_GM */ | |
190 | INTEL_VGA_DEVICE(0x27ae, &intel_i945gm_info), /* I945_GME */ | |
191 | INTEL_VGA_DEVICE(0x2972, &intel_i965g_info), /* I946_GZ */ | |
192 | INTEL_VGA_DEVICE(0x2982, &intel_i965g_info), /* G35_G */ | |
193 | INTEL_VGA_DEVICE(0x2992, &intel_i965g_info), /* I965_Q */ | |
194 | INTEL_VGA_DEVICE(0x29a2, &intel_i965g_info), /* I965_G */ | |
195 | INTEL_VGA_DEVICE(0x29b2, &intel_g33_info), /* Q35_G */ | |
196 | INTEL_VGA_DEVICE(0x29c2, &intel_g33_info), /* G33_G */ | |
197 | INTEL_VGA_DEVICE(0x29d2, &intel_g33_info), /* Q33_G */ | |
198 | INTEL_VGA_DEVICE(0x2a02, &intel_i965gm_info), /* I965_GM */ | |
199 | INTEL_VGA_DEVICE(0x2a12, &intel_i965gm_info), /* I965_GME */ | |
200 | INTEL_VGA_DEVICE(0x2a42, &intel_gm45_info), /* GM45_G */ | |
201 | INTEL_VGA_DEVICE(0x2e02, &intel_g45_info), /* IGD_E_G */ | |
202 | INTEL_VGA_DEVICE(0x2e12, &intel_g45_info), /* Q45_G */ | |
203 | INTEL_VGA_DEVICE(0x2e22, &intel_g45_info), /* G45_G */ | |
204 | INTEL_VGA_DEVICE(0x2e32, &intel_g45_info), /* G41_G */ | |
205 | INTEL_VGA_DEVICE(0x2e42, &intel_g45_info), /* B43_G */ | |
41a51428 | 206 | INTEL_VGA_DEVICE(0x2e92, &intel_g45_info), /* B43_G.1 */ |
cfdf1fa2 KH |
207 | INTEL_VGA_DEVICE(0xa001, &intel_pineview_info), |
208 | INTEL_VGA_DEVICE(0xa011, &intel_pineview_info), | |
209 | INTEL_VGA_DEVICE(0x0042, &intel_ironlake_d_info), | |
210 | INTEL_VGA_DEVICE(0x0046, &intel_ironlake_m_info), | |
f6e450a6 | 211 | INTEL_VGA_DEVICE(0x0102, &intel_sandybridge_d_info), |
85540480 ZW |
212 | INTEL_VGA_DEVICE(0x0112, &intel_sandybridge_d_info), |
213 | INTEL_VGA_DEVICE(0x0122, &intel_sandybridge_d_info), | |
a13e4093 | 214 | INTEL_VGA_DEVICE(0x0106, &intel_sandybridge_m_info), |
85540480 | 215 | INTEL_VGA_DEVICE(0x0116, &intel_sandybridge_m_info), |
4fefe435 | 216 | INTEL_VGA_DEVICE(0x0126, &intel_sandybridge_m_info), |
85540480 | 217 | INTEL_VGA_DEVICE(0x010A, &intel_sandybridge_d_info), |
49ae35f2 | 218 | {0, 0, 0} |
1da177e4 LT |
219 | }; |
220 | ||
79e53945 JB |
221 | #if defined(CONFIG_DRM_I915_KMS) |
222 | MODULE_DEVICE_TABLE(pci, pciidlist); | |
223 | #endif | |
224 | ||
3bad0781 ZW |
225 | #define INTEL_PCH_DEVICE_ID_MASK 0xff00 |
226 | #define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00 | |
227 | ||
228 | void intel_detect_pch (struct drm_device *dev) | |
229 | { | |
230 | struct drm_i915_private *dev_priv = dev->dev_private; | |
231 | struct pci_dev *pch; | |
232 | ||
233 | /* | |
234 | * The reason to probe ISA bridge instead of Dev31:Fun0 is to | |
235 | * make graphics device passthrough work easy for VMM, that only | |
236 | * need to expose ISA bridge to let driver know the real hardware | |
237 | * underneath. This is a requirement from virtualization team. | |
238 | */ | |
239 | pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, NULL); | |
240 | if (pch) { | |
241 | if (pch->vendor == PCI_VENDOR_ID_INTEL) { | |
242 | int id; | |
243 | id = pch->device & INTEL_PCH_DEVICE_ID_MASK; | |
244 | ||
245 | if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) { | |
246 | dev_priv->pch_type = PCH_CPT; | |
247 | DRM_DEBUG_KMS("Found CougarPoint PCH\n"); | |
248 | } | |
249 | } | |
250 | pci_dev_put(pch); | |
251 | } | |
252 | } | |
253 | ||
eb43f4af CW |
254 | void __gen6_force_wake_get(struct drm_i915_private *dev_priv) |
255 | { | |
256 | int count; | |
257 | ||
258 | count = 0; | |
259 | while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1)) | |
260 | udelay(10); | |
261 | ||
262 | I915_WRITE_NOTRACE(FORCEWAKE, 1); | |
263 | POSTING_READ(FORCEWAKE); | |
264 | ||
265 | count = 0; | |
266 | while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1) == 0) | |
267 | udelay(10); | |
268 | } | |
269 | ||
270 | void __gen6_force_wake_put(struct drm_i915_private *dev_priv) | |
271 | { | |
272 | I915_WRITE_NOTRACE(FORCEWAKE, 0); | |
273 | POSTING_READ(FORCEWAKE); | |
274 | } | |
275 | ||
84b79f8d | 276 | static int i915_drm_freeze(struct drm_device *dev) |
ba8bbcf6 | 277 | { |
61caf87c RW |
278 | struct drm_i915_private *dev_priv = dev->dev_private; |
279 | ||
5bcf719b DA |
280 | drm_kms_helper_poll_disable(dev); |
281 | ||
ba8bbcf6 | 282 | pci_save_state(dev->pdev); |
ba8bbcf6 | 283 | |
5669fcac | 284 | /* If KMS is active, we do the leavevt stuff here */ |
226485e9 | 285 | if (drm_core_check_feature(dev, DRIVER_MODESET)) { |
84b79f8d RW |
286 | int error = i915_gem_idle(dev); |
287 | if (error) { | |
226485e9 | 288 | dev_err(&dev->pdev->dev, |
84b79f8d RW |
289 | "GEM idle failed, resume might fail\n"); |
290 | return error; | |
291 | } | |
226485e9 | 292 | drm_irq_uninstall(dev); |
5669fcac JB |
293 | } |
294 | ||
9e06dd39 JB |
295 | i915_save_state(dev); |
296 | ||
44834a67 | 297 | intel_opregion_fini(dev); |
8ee1c3db | 298 | |
84b79f8d RW |
299 | /* Modeset on resume, not lid events */ |
300 | dev_priv->modeset_on_lid = 0; | |
61caf87c RW |
301 | |
302 | return 0; | |
84b79f8d RW |
303 | } |
304 | ||
6a9ee8af | 305 | int i915_suspend(struct drm_device *dev, pm_message_t state) |
84b79f8d RW |
306 | { |
307 | int error; | |
308 | ||
309 | if (!dev || !dev->dev_private) { | |
310 | DRM_ERROR("dev: %p\n", dev); | |
311 | DRM_ERROR("DRM not initialized, aborting suspend.\n"); | |
312 | return -ENODEV; | |
313 | } | |
314 | ||
315 | if (state.event == PM_EVENT_PRETHAW) | |
316 | return 0; | |
317 | ||
5bcf719b DA |
318 | |
319 | if (dev->switch_power_state == DRM_SWITCH_POWER_OFF) | |
320 | return 0; | |
6eecba33 | 321 | |
84b79f8d RW |
322 | error = i915_drm_freeze(dev); |
323 | if (error) | |
324 | return error; | |
325 | ||
b932ccb5 DA |
326 | if (state.event == PM_EVENT_SUSPEND) { |
327 | /* Shut down the device */ | |
328 | pci_disable_device(dev->pdev); | |
329 | pci_set_power_state(dev->pdev, PCI_D3hot); | |
330 | } | |
ba8bbcf6 JB |
331 | |
332 | return 0; | |
333 | } | |
334 | ||
84b79f8d | 335 | static int i915_drm_thaw(struct drm_device *dev) |
ba8bbcf6 | 336 | { |
5669fcac | 337 | struct drm_i915_private *dev_priv = dev->dev_private; |
84b79f8d | 338 | int error = 0; |
8ee1c3db | 339 | |
d1c3b177 CW |
340 | if (drm_core_check_feature(dev, DRIVER_MODESET)) { |
341 | mutex_lock(&dev->struct_mutex); | |
342 | i915_gem_restore_gtt_mappings(dev); | |
343 | mutex_unlock(&dev->struct_mutex); | |
344 | } | |
345 | ||
61caf87c | 346 | i915_restore_state(dev); |
44834a67 | 347 | intel_opregion_setup(dev); |
61caf87c | 348 | |
5669fcac JB |
349 | /* KMS EnterVT equivalent */ |
350 | if (drm_core_check_feature(dev, DRIVER_MODESET)) { | |
351 | mutex_lock(&dev->struct_mutex); | |
352 | dev_priv->mm.suspended = 0; | |
353 | ||
84b79f8d | 354 | error = i915_gem_init_ringbuffer(dev); |
5669fcac | 355 | mutex_unlock(&dev->struct_mutex); |
226485e9 JB |
356 | |
357 | drm_irq_install(dev); | |
84b79f8d | 358 | |
354ff967 ZY |
359 | /* Resume the modeset for every activated CRTC */ |
360 | drm_helper_resume_force_mode(dev); | |
5669fcac | 361 | |
d5bb081b JB |
362 | if (dev_priv->renderctx && dev_priv->pwrctx) |
363 | ironlake_enable_rc6(dev); | |
364 | } | |
1daed3fb | 365 | |
44834a67 CW |
366 | intel_opregion_init(dev); |
367 | ||
c9354c85 | 368 | dev_priv->modeset_on_lid = 0; |
06891e27 | 369 | |
84b79f8d RW |
370 | return error; |
371 | } | |
372 | ||
6a9ee8af | 373 | int i915_resume(struct drm_device *dev) |
84b79f8d | 374 | { |
6eecba33 CW |
375 | int ret; |
376 | ||
5bcf719b DA |
377 | if (dev->switch_power_state == DRM_SWITCH_POWER_OFF) |
378 | return 0; | |
379 | ||
84b79f8d RW |
380 | if (pci_enable_device(dev->pdev)) |
381 | return -EIO; | |
382 | ||
383 | pci_set_master(dev->pdev); | |
384 | ||
6eecba33 CW |
385 | ret = i915_drm_thaw(dev); |
386 | if (ret) | |
387 | return ret; | |
388 | ||
389 | drm_kms_helper_poll_enable(dev); | |
390 | return 0; | |
ba8bbcf6 JB |
391 | } |
392 | ||
dc96e9b8 CW |
393 | static int i8xx_do_reset(struct drm_device *dev, u8 flags) |
394 | { | |
395 | struct drm_i915_private *dev_priv = dev->dev_private; | |
396 | ||
397 | if (IS_I85X(dev)) | |
398 | return -ENODEV; | |
399 | ||
400 | I915_WRITE(D_STATE, I915_READ(D_STATE) | DSTATE_GFX_RESET_I830); | |
401 | POSTING_READ(D_STATE); | |
402 | ||
403 | if (IS_I830(dev) || IS_845G(dev)) { | |
404 | I915_WRITE(DEBUG_RESET_I830, | |
405 | DEBUG_RESET_DISPLAY | | |
406 | DEBUG_RESET_RENDER | | |
407 | DEBUG_RESET_FULL); | |
408 | POSTING_READ(DEBUG_RESET_I830); | |
409 | msleep(1); | |
410 | ||
411 | I915_WRITE(DEBUG_RESET_I830, 0); | |
412 | POSTING_READ(DEBUG_RESET_I830); | |
413 | } | |
414 | ||
415 | msleep(1); | |
416 | ||
417 | I915_WRITE(D_STATE, I915_READ(D_STATE) & ~DSTATE_GFX_RESET_I830); | |
418 | POSTING_READ(D_STATE); | |
419 | ||
420 | return 0; | |
421 | } | |
422 | ||
f49f0586 KG |
423 | static int i965_reset_complete(struct drm_device *dev) |
424 | { | |
425 | u8 gdrst; | |
eeccdcac | 426 | pci_read_config_byte(dev->pdev, I965_GDRST, &gdrst); |
f49f0586 KG |
427 | return gdrst & 0x1; |
428 | } | |
429 | ||
0573ed4a KG |
430 | static int i965_do_reset(struct drm_device *dev, u8 flags) |
431 | { | |
432 | u8 gdrst; | |
433 | ||
ae681d96 CW |
434 | /* |
435 | * Set the domains we want to reset (GRDOM/bits 2 and 3) as | |
436 | * well as the reset bit (GR/bit 0). Setting the GR bit | |
437 | * triggers the reset; when done, the hardware will clear it. | |
438 | */ | |
0573ed4a KG |
439 | pci_read_config_byte(dev->pdev, I965_GDRST, &gdrst); |
440 | pci_write_config_byte(dev->pdev, I965_GDRST, gdrst | flags | 0x1); | |
441 | ||
442 | return wait_for(i965_reset_complete(dev), 500); | |
443 | } | |
444 | ||
445 | static int ironlake_do_reset(struct drm_device *dev, u8 flags) | |
446 | { | |
447 | struct drm_i915_private *dev_priv = dev->dev_private; | |
448 | u32 gdrst = I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR); | |
449 | I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR, gdrst | flags | 0x1); | |
450 | return wait_for(I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) & 0x1, 500); | |
ba8bbcf6 JB |
451 | } |
452 | ||
cff458c2 EA |
453 | static int gen6_do_reset(struct drm_device *dev, u8 flags) |
454 | { | |
455 | struct drm_i915_private *dev_priv = dev->dev_private; | |
456 | ||
457 | I915_WRITE(GEN6_GDRST, GEN6_GRDOM_FULL); | |
458 | return wait_for((I915_READ(GEN6_GDRST) & GEN6_GRDOM_FULL) == 0, 500); | |
459 | } | |
460 | ||
11ed50ec BG |
461 | /** |
462 | * i965_reset - reset chip after a hang | |
463 | * @dev: drm device to reset | |
464 | * @flags: reset domains | |
465 | * | |
466 | * Reset the chip. Useful if a hang is detected. Returns zero on successful | |
467 | * reset or otherwise an error code. | |
468 | * | |
469 | * Procedure is fairly simple: | |
470 | * - reset the chip using the reset reg | |
471 | * - re-init context state | |
472 | * - re-init hardware status page | |
473 | * - re-init ring buffer | |
474 | * - re-init interrupt state | |
475 | * - re-init display | |
476 | */ | |
f803aa55 | 477 | int i915_reset(struct drm_device *dev, u8 flags) |
11ed50ec BG |
478 | { |
479 | drm_i915_private_t *dev_priv = dev->dev_private; | |
11ed50ec BG |
480 | /* |
481 | * We really should only reset the display subsystem if we actually | |
482 | * need to | |
483 | */ | |
484 | bool need_display = true; | |
0573ed4a | 485 | int ret; |
11ed50ec | 486 | |
d78cb50b CW |
487 | if (!i915_try_reset) |
488 | return 0; | |
489 | ||
340479aa CW |
490 | if (!mutex_trylock(&dev->struct_mutex)) |
491 | return -EBUSY; | |
11ed50ec | 492 | |
069efc1d | 493 | i915_gem_reset(dev); |
77f01230 | 494 | |
f803aa55 | 495 | ret = -ENODEV; |
ae681d96 CW |
496 | if (get_seconds() - dev_priv->last_gpu_reset < 5) { |
497 | DRM_ERROR("GPU hanging too fast, declaring wedged!\n"); | |
498 | } else switch (INTEL_INFO(dev)->gen) { | |
cff458c2 EA |
499 | case 6: |
500 | ret = gen6_do_reset(dev, flags); | |
501 | break; | |
f803aa55 | 502 | case 5: |
0573ed4a | 503 | ret = ironlake_do_reset(dev, flags); |
f803aa55 CW |
504 | break; |
505 | case 4: | |
0573ed4a | 506 | ret = i965_do_reset(dev, flags); |
f803aa55 | 507 | break; |
dc96e9b8 CW |
508 | case 2: |
509 | ret = i8xx_do_reset(dev, flags); | |
510 | break; | |
f803aa55 | 511 | } |
ae681d96 | 512 | dev_priv->last_gpu_reset = get_seconds(); |
0573ed4a | 513 | if (ret) { |
f803aa55 | 514 | DRM_ERROR("Failed to reset chip.\n"); |
f953c935 | 515 | mutex_unlock(&dev->struct_mutex); |
f803aa55 | 516 | return ret; |
11ed50ec BG |
517 | } |
518 | ||
519 | /* Ok, now get things going again... */ | |
520 | ||
521 | /* | |
522 | * Everything depends on having the GTT running, so we need to start | |
523 | * there. Fortunately we don't need to do this unless we reset the | |
524 | * chip at a PCI level. | |
525 | * | |
526 | * Next we need to restore the context, but we don't use those | |
527 | * yet either... | |
528 | * | |
529 | * Ring buffer needs to be re-initialized in the KMS case, or if X | |
530 | * was running at the time of the reset (i.e. we weren't VT | |
531 | * switched away). | |
532 | */ | |
533 | if (drm_core_check_feature(dev, DRIVER_MODESET) || | |
8187a2b7 | 534 | !dev_priv->mm.suspended) { |
11ed50ec | 535 | dev_priv->mm.suspended = 0; |
75a6898f | 536 | |
1ec14ad3 | 537 | dev_priv->ring[RCS].init(&dev_priv->ring[RCS]); |
75a6898f | 538 | if (HAS_BSD(dev)) |
1ec14ad3 | 539 | dev_priv->ring[VCS].init(&dev_priv->ring[VCS]); |
75a6898f | 540 | if (HAS_BLT(dev)) |
1ec14ad3 | 541 | dev_priv->ring[BCS].init(&dev_priv->ring[BCS]); |
75a6898f | 542 | |
11ed50ec BG |
543 | mutex_unlock(&dev->struct_mutex); |
544 | drm_irq_uninstall(dev); | |
545 | drm_irq_install(dev); | |
546 | mutex_lock(&dev->struct_mutex); | |
547 | } | |
548 | ||
9fd98141 CW |
549 | mutex_unlock(&dev->struct_mutex); |
550 | ||
11ed50ec | 551 | /* |
9fd98141 CW |
552 | * Perform a full modeset as on later generations, e.g. Ironlake, we may |
553 | * need to retrain the display link and cannot just restore the register | |
554 | * values. | |
11ed50ec | 555 | */ |
9fd98141 CW |
556 | if (need_display) { |
557 | mutex_lock(&dev->mode_config.mutex); | |
558 | drm_helper_resume_force_mode(dev); | |
559 | mutex_unlock(&dev->mode_config.mutex); | |
560 | } | |
11ed50ec | 561 | |
11ed50ec BG |
562 | return 0; |
563 | } | |
564 | ||
565 | ||
112b715e KH |
566 | static int __devinit |
567 | i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent) | |
568 | { | |
dcdb1674 | 569 | return drm_get_pci_dev(pdev, ent, &driver); |
112b715e KH |
570 | } |
571 | ||
572 | static void | |
573 | i915_pci_remove(struct pci_dev *pdev) | |
574 | { | |
575 | struct drm_device *dev = pci_get_drvdata(pdev); | |
576 | ||
577 | drm_put_dev(dev); | |
578 | } | |
579 | ||
84b79f8d | 580 | static int i915_pm_suspend(struct device *dev) |
112b715e | 581 | { |
84b79f8d RW |
582 | struct pci_dev *pdev = to_pci_dev(dev); |
583 | struct drm_device *drm_dev = pci_get_drvdata(pdev); | |
584 | int error; | |
112b715e | 585 | |
84b79f8d RW |
586 | if (!drm_dev || !drm_dev->dev_private) { |
587 | dev_err(dev, "DRM not initialized, aborting suspend.\n"); | |
588 | return -ENODEV; | |
589 | } | |
112b715e | 590 | |
5bcf719b DA |
591 | if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF) |
592 | return 0; | |
593 | ||
84b79f8d RW |
594 | error = i915_drm_freeze(drm_dev); |
595 | if (error) | |
596 | return error; | |
112b715e | 597 | |
84b79f8d RW |
598 | pci_disable_device(pdev); |
599 | pci_set_power_state(pdev, PCI_D3hot); | |
cbda12d7 | 600 | |
84b79f8d | 601 | return 0; |
cbda12d7 ZW |
602 | } |
603 | ||
84b79f8d | 604 | static int i915_pm_resume(struct device *dev) |
cbda12d7 | 605 | { |
84b79f8d RW |
606 | struct pci_dev *pdev = to_pci_dev(dev); |
607 | struct drm_device *drm_dev = pci_get_drvdata(pdev); | |
608 | ||
609 | return i915_resume(drm_dev); | |
cbda12d7 ZW |
610 | } |
611 | ||
84b79f8d | 612 | static int i915_pm_freeze(struct device *dev) |
cbda12d7 | 613 | { |
84b79f8d RW |
614 | struct pci_dev *pdev = to_pci_dev(dev); |
615 | struct drm_device *drm_dev = pci_get_drvdata(pdev); | |
616 | ||
617 | if (!drm_dev || !drm_dev->dev_private) { | |
618 | dev_err(dev, "DRM not initialized, aborting suspend.\n"); | |
619 | return -ENODEV; | |
620 | } | |
621 | ||
622 | return i915_drm_freeze(drm_dev); | |
cbda12d7 ZW |
623 | } |
624 | ||
84b79f8d | 625 | static int i915_pm_thaw(struct device *dev) |
cbda12d7 | 626 | { |
84b79f8d RW |
627 | struct pci_dev *pdev = to_pci_dev(dev); |
628 | struct drm_device *drm_dev = pci_get_drvdata(pdev); | |
629 | ||
630 | return i915_drm_thaw(drm_dev); | |
cbda12d7 ZW |
631 | } |
632 | ||
84b79f8d | 633 | static int i915_pm_poweroff(struct device *dev) |
cbda12d7 | 634 | { |
84b79f8d RW |
635 | struct pci_dev *pdev = to_pci_dev(dev); |
636 | struct drm_device *drm_dev = pci_get_drvdata(pdev); | |
84b79f8d | 637 | |
61caf87c | 638 | return i915_drm_freeze(drm_dev); |
cbda12d7 ZW |
639 | } |
640 | ||
b4b78d12 | 641 | static const struct dev_pm_ops i915_pm_ops = { |
cbda12d7 ZW |
642 | .suspend = i915_pm_suspend, |
643 | .resume = i915_pm_resume, | |
644 | .freeze = i915_pm_freeze, | |
645 | .thaw = i915_pm_thaw, | |
646 | .poweroff = i915_pm_poweroff, | |
84b79f8d | 647 | .restore = i915_pm_resume, |
cbda12d7 ZW |
648 | }; |
649 | ||
de151cf6 JB |
650 | static struct vm_operations_struct i915_gem_vm_ops = { |
651 | .fault = i915_gem_fault, | |
ab00b3e5 JB |
652 | .open = drm_gem_vm_open, |
653 | .close = drm_gem_vm_close, | |
de151cf6 JB |
654 | }; |
655 | ||
1da177e4 | 656 | static struct drm_driver driver = { |
792d2b9a DA |
657 | /* don't use mtrr's here, the Xserver or user space app should |
658 | * deal with them for intel hardware. | |
659 | */ | |
673a394b EA |
660 | .driver_features = |
661 | DRIVER_USE_AGP | DRIVER_REQUIRE_AGP | /* DRIVER_USE_MTRR |*/ | |
662 | DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM, | |
22eae947 | 663 | .load = i915_driver_load, |
ba8bbcf6 | 664 | .unload = i915_driver_unload, |
673a394b | 665 | .open = i915_driver_open, |
22eae947 DA |
666 | .lastclose = i915_driver_lastclose, |
667 | .preclose = i915_driver_preclose, | |
673a394b | 668 | .postclose = i915_driver_postclose, |
d8e29209 RW |
669 | |
670 | /* Used in place of i915_pm_ops for non-DRIVER_MODESET */ | |
671 | .suspend = i915_suspend, | |
672 | .resume = i915_resume, | |
673 | ||
cda17380 | 674 | .device_is_agp = i915_driver_device_is_agp, |
0a3e67a4 JB |
675 | .enable_vblank = i915_enable_vblank, |
676 | .disable_vblank = i915_disable_vblank, | |
0af7e4df MK |
677 | .get_vblank_timestamp = i915_get_vblank_timestamp, |
678 | .get_scanout_position = i915_get_crtc_scanoutpos, | |
1da177e4 LT |
679 | .irq_preinstall = i915_driver_irq_preinstall, |
680 | .irq_postinstall = i915_driver_irq_postinstall, | |
681 | .irq_uninstall = i915_driver_irq_uninstall, | |
682 | .irq_handler = i915_driver_irq_handler, | |
683 | .reclaim_buffers = drm_core_reclaim_buffers, | |
7c1c2871 DA |
684 | .master_create = i915_master_create, |
685 | .master_destroy = i915_master_destroy, | |
955b12de | 686 | #if defined(CONFIG_DEBUG_FS) |
27c202ad BG |
687 | .debugfs_init = i915_debugfs_init, |
688 | .debugfs_cleanup = i915_debugfs_cleanup, | |
955b12de | 689 | #endif |
673a394b EA |
690 | .gem_init_object = i915_gem_init_object, |
691 | .gem_free_object = i915_gem_free_object, | |
de151cf6 | 692 | .gem_vm_ops = &i915_gem_vm_ops, |
1da177e4 LT |
693 | .ioctls = i915_ioctls, |
694 | .fops = { | |
b5e89ed5 DA |
695 | .owner = THIS_MODULE, |
696 | .open = drm_open, | |
697 | .release = drm_release, | |
ed8b6704 | 698 | .unlocked_ioctl = drm_ioctl, |
de151cf6 | 699 | .mmap = drm_gem_mmap, |
b5e89ed5 DA |
700 | .poll = drm_poll, |
701 | .fasync = drm_fasync, | |
c9a9c5e0 | 702 | .read = drm_read, |
8ca7c1df | 703 | #ifdef CONFIG_COMPAT |
b5e89ed5 | 704 | .compat_ioctl = i915_compat_ioctl, |
8ca7c1df | 705 | #endif |
dc880abe | 706 | .llseek = noop_llseek, |
22eae947 DA |
707 | }, |
708 | ||
1da177e4 | 709 | .pci_driver = { |
22eae947 DA |
710 | .name = DRIVER_NAME, |
711 | .id_table = pciidlist, | |
112b715e KH |
712 | .probe = i915_pci_probe, |
713 | .remove = i915_pci_remove, | |
cbda12d7 | 714 | .driver.pm = &i915_pm_ops, |
22eae947 | 715 | }, |
bc5f4523 | 716 | |
22eae947 DA |
717 | .name = DRIVER_NAME, |
718 | .desc = DRIVER_DESC, | |
719 | .date = DRIVER_DATE, | |
720 | .major = DRIVER_MAJOR, | |
721 | .minor = DRIVER_MINOR, | |
722 | .patchlevel = DRIVER_PATCHLEVEL, | |
1da177e4 LT |
723 | }; |
724 | ||
725 | static int __init i915_init(void) | |
726 | { | |
1f7a6e37 ZW |
727 | if (!intel_agp_enabled) { |
728 | DRM_ERROR("drm/i915 can't work without intel_agp module!\n"); | |
729 | return -ENODEV; | |
730 | } | |
731 | ||
1da177e4 | 732 | driver.num_ioctls = i915_max_ioctl; |
79e53945 JB |
733 | |
734 | /* | |
735 | * If CONFIG_DRM_I915_KMS is set, default to KMS unless | |
736 | * explicitly disabled with the module pararmeter. | |
737 | * | |
738 | * Otherwise, just follow the parameter (defaulting to off). | |
739 | * | |
740 | * Allow optional vga_text_mode_force boot option to override | |
741 | * the default behavior. | |
742 | */ | |
743 | #if defined(CONFIG_DRM_I915_KMS) | |
744 | if (i915_modeset != 0) | |
745 | driver.driver_features |= DRIVER_MODESET; | |
746 | #endif | |
747 | if (i915_modeset == 1) | |
748 | driver.driver_features |= DRIVER_MODESET; | |
749 | ||
750 | #ifdef CONFIG_VGA_CONSOLE | |
751 | if (vgacon_text_force() && i915_modeset == -1) | |
752 | driver.driver_features &= ~DRIVER_MODESET; | |
753 | #endif | |
754 | ||
1da177e4 LT |
755 | return drm_init(&driver); |
756 | } | |
757 | ||
758 | static void __exit i915_exit(void) | |
759 | { | |
760 | drm_exit(&driver); | |
761 | } | |
762 | ||
763 | module_init(i915_init); | |
764 | module_exit(i915_exit); | |
765 | ||
b5e89ed5 DA |
766 | MODULE_AUTHOR(DRIVER_AUTHOR); |
767 | MODULE_DESCRIPTION(DRIVER_DESC); | |
1da177e4 | 768 | MODULE_LICENSE("GPL and additional rights"); |