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drm/i915: Acquire the backing storage outside of struct_mutex in set-domain
[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / i915 / i915_drv.c
CommitLineData
1da177e4
LT		 1/* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
2 */
0d6aa60b 3/*
bc54fd1a 4 *
1da177e4
LT		 5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
6 * All Rights Reserved.
bc54fd1a
DA		 7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
15 *
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
18 * of the Software.
19 *
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27 *
0d6aa60b 28 */
1da177e4 29
e5747e3a 30#include <linux/acpi.h>
0673ad47
CW		 31#include <linux/device.h>
32#include <linux/oom.h>
e0cd3608 33#include <linux/module.h>
0673ad47
CW		 34#include <linux/pci.h>
35#include <linux/pm.h>
d6102977 36#include <linux/pm_runtime.h>
0673ad47
CW		 37#include <linux/pnp.h>
38#include <linux/slab.h>
39#include <linux/vgaarb.h>
704ab614 40#include <linux/vga_switcheroo.h>
0673ad47
CW		 41#include <linux/vt.h>
42#include <acpi/video.h>
43
44#include <drm/drmP.h>
760285e7 45#include <drm/drm_crtc_helper.h>
0673ad47
CW		 46#include <drm/i915_drm.h>
47
48#include "i915_drv.h"
49#include "i915_trace.h"
50#include "i915_vgpu.h"
51#include "intel_drv.h"
79e53945 52
112b715e
KH		 53static struct drm_driver driver;
54
0673ad47
CW		 55static unsigned int i915_load_fail_count;
56
57bool __i915_inject_load_failure(const char *func, int line)
58{
59 if (i915_load_fail_count >= i915.inject_load_failure)
60 return false;
61
62 if (++i915_load_fail_count == i915.inject_load_failure) {
63 DRM_INFO("Injecting failure at checkpoint %u [%s:%d]\n",
64 i915.inject_load_failure, func, line);
65 return true;
66 }
67
68 return false;
69}
70
71#define FDO_BUG_URL "https://bugs.freedesktop.org/enter_bug.cgi?product=DRI"
72#define FDO_BUG_MSG "Please file a bug at " FDO_BUG_URL " against DRM/Intel " \
73 "providing the dmesg log by booting with drm.debug=0xf"
74
75void
76__i915_printk(struct drm_i915_private *dev_priv, const char *level,
77 const char *fmt, ...)
78{
79 static bool shown_bug_once;
c49d13ee 80 struct device *kdev = dev_priv->drm.dev;
0673ad47
CW		 81 bool is_error = level[1] <= KERN_ERR[1];
82 bool is_debug = level[1] == KERN_DEBUG[1];
83 struct va_format vaf;
84 va_list args;
85
86 if (is_debug && !(drm_debug & DRM_UT_DRIVER))
87 return;
88
89 va_start(args, fmt);
90
91 vaf.fmt = fmt;
92 vaf.va = &args;
93
c49d13ee 94 dev_printk(level, kdev, "[" DRM_NAME ":%ps] %pV",
0673ad47
CW		 95 __builtin_return_address(0), &vaf);
96
97 if (is_error && !shown_bug_once) {
c49d13ee 98 dev_notice(kdev, "%s", FDO_BUG_MSG);
0673ad47
CW		 99 shown_bug_once = true;
100 }
101
102 va_end(args);
103}
104
105static bool i915_error_injected(struct drm_i915_private *dev_priv)
106{
107 return i915.inject_load_failure &&
108 i915_load_fail_count == i915.inject_load_failure;
109}
110
111#define i915_load_error(dev_priv, fmt, ...) \
112 __i915_printk(dev_priv, \
113 i915_error_injected(dev_priv) ? KERN_DEBUG : KERN_ERR, \
114 fmt, ##__VA_ARGS__)
115
116
fd6b8f43 117static enum intel_pch intel_virt_detect_pch(struct drm_i915_private *dev_priv)
0673ad47
CW		 118{
119 enum intel_pch ret = PCH_NOP;
120
121 /*
122 * In a virtualized passthrough environment we can be in a
123 * setup where the ISA bridge is not able to be passed through.
124 * In this case, a south bridge can be emulated and we have to
125 * make an educated guess as to which PCH is really there.
126 */
127
fd6b8f43 128 if (IS_GEN5(dev_priv)) {
0673ad47
CW		 129 ret = PCH_IBX;
130 DRM_DEBUG_KMS("Assuming Ibex Peak PCH\n");
fd6b8f43 131 } else if (IS_GEN6(dev_priv) || IS_IVYBRIDGE(dev_priv)) {
0673ad47
CW		 132 ret = PCH_CPT;
133 DRM_DEBUG_KMS("Assuming CouarPoint PCH\n");
fd6b8f43 134 } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
0673ad47
CW		 135 ret = PCH_LPT;
136 DRM_DEBUG_KMS("Assuming LynxPoint PCH\n");
fd6b8f43 137 } else if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
0673ad47
CW		 138 ret = PCH_SPT;
139 DRM_DEBUG_KMS("Assuming SunrisePoint PCH\n");
140 }
141
142 return ret;
143}
144
145static void intel_detect_pch(struct drm_device *dev)
146{
fac5e23e 147 struct drm_i915_private *dev_priv = to_i915(dev);
0673ad47
CW		 148 struct pci_dev *pch = NULL;
149
150 /* In all current cases, num_pipes is equivalent to the PCH_NOP setting
151 * (which really amounts to a PCH but no South Display).
152 */
153 if (INTEL_INFO(dev)->num_pipes == 0) {
154 dev_priv->pch_type = PCH_NOP;
155 return;
156 }
157
158 /*
159 * The reason to probe ISA bridge instead of Dev31:Fun0 is to
160 * make graphics device passthrough work easy for VMM, that only
161 * need to expose ISA bridge to let driver know the real hardware
162 * underneath. This is a requirement from virtualization team.
163 *
164 * In some virtualized environments (e.g. XEN), there is irrelevant
165 * ISA bridge in the system. To work reliably, we should scan trhough
166 * all the ISA bridge devices and check for the first match, instead
167 * of only checking the first one.
168 */
169 while ((pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, pch))) {
170 if (pch->vendor == PCI_VENDOR_ID_INTEL) {
171 unsigned short id = pch->device & INTEL_PCH_DEVICE_ID_MASK;
172 dev_priv->pch_id = id;
173
174 if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) {
175 dev_priv->pch_type = PCH_IBX;
176 DRM_DEBUG_KMS("Found Ibex Peak PCH\n");
5db94019 177 WARN_ON(!IS_GEN5(dev_priv));
0673ad47
CW		 178 } else if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) {
179 dev_priv->pch_type = PCH_CPT;
180 DRM_DEBUG_KMS("Found CougarPoint PCH\n");
fd6b8f43
TU		 181 WARN_ON(!(IS_GEN6(dev_priv) ||
182 IS_IVYBRIDGE(dev_priv)));
0673ad47
CW		 183 } else if (id == INTEL_PCH_PPT_DEVICE_ID_TYPE) {
184 /* PantherPoint is CPT compatible */
185 dev_priv->pch_type = PCH_CPT;
186 DRM_DEBUG_KMS("Found PantherPoint PCH\n");
fd6b8f43
TU		 187 WARN_ON(!(IS_GEN6(dev_priv) ||
188 IS_IVYBRIDGE(dev_priv)));
0673ad47
CW		 189 } else if (id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
190 dev_priv->pch_type = PCH_LPT;
191 DRM_DEBUG_KMS("Found LynxPoint PCH\n");
8652744b
TU		 192 WARN_ON(!IS_HASWELL(dev_priv) &&
193 !IS_BROADWELL(dev_priv));
50a0bc90
TU		 194 WARN_ON(IS_HSW_ULT(dev_priv) ||
195 IS_BDW_ULT(dev_priv));
0673ad47
CW		 196 } else if (id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
197 dev_priv->pch_type = PCH_LPT;
198 DRM_DEBUG_KMS("Found LynxPoint LP PCH\n");
8652744b
TU		 199 WARN_ON(!IS_HASWELL(dev_priv) &&
200 !IS_BROADWELL(dev_priv));
50a0bc90
TU		 201 WARN_ON(!IS_HSW_ULT(dev_priv) &&
202 !IS_BDW_ULT(dev_priv));
0673ad47
CW		 203 } else if (id == INTEL_PCH_SPT_DEVICE_ID_TYPE) {
204 dev_priv->pch_type = PCH_SPT;
205 DRM_DEBUG_KMS("Found SunrisePoint PCH\n");
0853723b
TU		 206 WARN_ON(!IS_SKYLAKE(dev_priv) &&
207 !IS_KABYLAKE(dev_priv));
0673ad47
CW		 208 } else if (id == INTEL_PCH_SPT_LP_DEVICE_ID_TYPE) {
209 dev_priv->pch_type = PCH_SPT;
210 DRM_DEBUG_KMS("Found SunrisePoint LP PCH\n");
0853723b
TU		 211 WARN_ON(!IS_SKYLAKE(dev_priv) &&
212 !IS_KABYLAKE(dev_priv));
22dea0be
RV		 213 } else if (id == INTEL_PCH_KBP_DEVICE_ID_TYPE) {
214 dev_priv->pch_type = PCH_KBP;
215 DRM_DEBUG_KMS("Found KabyPoint PCH\n");
0853723b 216 WARN_ON(!IS_KABYLAKE(dev_priv));
0673ad47
CW		 217 } else if ((id == INTEL_PCH_P2X_DEVICE_ID_TYPE) ||
218 (id == INTEL_PCH_P3X_DEVICE_ID_TYPE) ||
219 ((id == INTEL_PCH_QEMU_DEVICE_ID_TYPE) &&
220 pch->subsystem_vendor ==
221 PCI_SUBVENDOR_ID_REDHAT_QUMRANET &&
222 pch->subsystem_device ==
223 PCI_SUBDEVICE_ID_QEMU)) {
fd6b8f43
TU		 224 dev_priv->pch_type =
225 intel_virt_detect_pch(dev_priv);
0673ad47
CW		 226 } else
227 continue;
228
229 break;
230 }
231 }
232 if (!pch)
233 DRM_DEBUG_KMS("No PCH found.\n");
234
235 pci_dev_put(pch);
236}
237
0673ad47
CW		 238static int i915_getparam(struct drm_device *dev, void *data,
239 struct drm_file *file_priv)
240{
fac5e23e 241 struct drm_i915_private *dev_priv = to_i915(dev);
52a05c30 242 struct pci_dev *pdev = dev_priv->drm.pdev;
0673ad47
CW		 243 drm_i915_getparam_t *param = data;
244 int value;
245
246 switch (param->param) {
247 case I915_PARAM_IRQ_ACTIVE:
248 case I915_PARAM_ALLOW_BATCHBUFFER:
249 case I915_PARAM_LAST_DISPATCH:
250 /* Reject all old ums/dri params. */
251 return -ENODEV;
252 case I915_PARAM_CHIPSET_ID:
52a05c30 253 value = pdev->device;
0673ad47
CW		 254 break;
255 case I915_PARAM_REVISION:
52a05c30 256 value = pdev->revision;
0673ad47 257 break;
0673ad47
CW		 258 case I915_PARAM_NUM_FENCES_AVAIL:
259 value = dev_priv->num_fence_regs;
260 break;
261 case I915_PARAM_HAS_OVERLAY:
262 value = dev_priv->overlay ? 1 : 0;
263 break;
0673ad47 264 case I915_PARAM_HAS_BSD:
3b3f1650 265 value = !!dev_priv->engine[VCS];
0673ad47
CW		 266 break;
267 case I915_PARAM_HAS_BLT:
3b3f1650 268 value = !!dev_priv->engine[BCS];
0673ad47
CW		 269 break;
270 case I915_PARAM_HAS_VEBOX:
3b3f1650 271 value = !!dev_priv->engine[VECS];
0673ad47
CW		 272 break;
273 case I915_PARAM_HAS_BSD2:
3b3f1650 274 value = !!dev_priv->engine[VCS2];
0673ad47 275 break;
0673ad47 276 case I915_PARAM_HAS_EXEC_CONSTANTS:
16162470 277 value = INTEL_GEN(dev_priv) >= 4;
0673ad47
CW		 278 break;
279 case I915_PARAM_HAS_LLC:
16162470 280 value = HAS_LLC(dev_priv);
0673ad47
CW		 281 break;
282 case I915_PARAM_HAS_WT:
16162470 283 value = HAS_WT(dev_priv);
0673ad47
CW		 284 break;
285 case I915_PARAM_HAS_ALIASING_PPGTT:
16162470 286 value = USES_PPGTT(dev_priv);
0673ad47
CW		 287 break;
288 case I915_PARAM_HAS_SEMAPHORES:
39df9190 289 value = i915.semaphores;
0673ad47 290 break;
0673ad47
CW		 291 case I915_PARAM_HAS_SECURE_BATCHES:
292 value = capable(CAP_SYS_ADMIN);
293 break;
0673ad47
CW		 294 case I915_PARAM_CMD_PARSER_VERSION:
295 value = i915_cmd_parser_get_version(dev_priv);
296 break;
0673ad47 297 case I915_PARAM_SUBSLICE_TOTAL:
57ec171e 298 value = sseu_subslice_total(&INTEL_INFO(dev_priv)->sseu);
0673ad47
CW		 299 if (!value)
300 return -ENODEV;
301 break;
302 case I915_PARAM_EU_TOTAL:
43b67998 303 value = INTEL_INFO(dev_priv)->sseu.eu_total;
0673ad47
CW		 304 if (!value)
305 return -ENODEV;
306 break;
307 case I915_PARAM_HAS_GPU_RESET:
308 value = i915.enable_hangcheck && intel_has_gpu_reset(dev_priv);
309 break;
310 case I915_PARAM_HAS_RESOURCE_STREAMER:
16162470 311 value = HAS_RESOURCE_STREAMER(dev_priv);
0673ad47 312 break;
37f501af 313 case I915_PARAM_HAS_POOLED_EU:
16162470 314 value = HAS_POOLED_EU(dev_priv);
37f501af 315 break;
316 case I915_PARAM_MIN_EU_IN_POOL:
43b67998 317 value = INTEL_INFO(dev_priv)->sseu.min_eu_in_pool;
37f501af 318 break;
4cc69075
CW		 319 case I915_PARAM_MMAP_GTT_VERSION:
320 /* Though we've started our numbering from 1, and so class all
321 * earlier versions as 0, in effect their value is undefined as
322 * the ioctl will report EINVAL for the unknown param!
323 */
324 value = i915_gem_mmap_gtt_version();
325 break;
16162470
DW		 326 case I915_PARAM_MMAP_VERSION:
327 /* Remember to bump this if the version changes! */
328 case I915_PARAM_HAS_GEM:
329 case I915_PARAM_HAS_PAGEFLIPPING:
330 case I915_PARAM_HAS_EXECBUF2: /* depends on GEM */
331 case I915_PARAM_HAS_RELAXED_FENCING:
332 case I915_PARAM_HAS_COHERENT_RINGS:
333 case I915_PARAM_HAS_RELAXED_DELTA:
334 case I915_PARAM_HAS_GEN7_SOL_RESET:
335 case I915_PARAM_HAS_WAIT_TIMEOUT:
336 case I915_PARAM_HAS_PRIME_VMAP_FLUSH:
337 case I915_PARAM_HAS_PINNED_BATCHES:
338 case I915_PARAM_HAS_EXEC_NO_RELOC:
339 case I915_PARAM_HAS_EXEC_HANDLE_LUT:
340 case I915_PARAM_HAS_COHERENT_PHYS_GTT:
341 case I915_PARAM_HAS_EXEC_SOFTPIN:
342 /* For the time being all of these are always true;
343 * if some supported hardware does not have one of these
344 * features this value needs to be provided from
345 * INTEL_INFO(), a feature macro, or similar.
346 */
347 value = 1;
348 break;
0673ad47
CW		 349 default:
350 DRM_DEBUG("Unknown parameter %d\n", param->param);
351 return -EINVAL;
352 }
353
dda33009 354 if (put_user(value, param->value))
0673ad47 355 return -EFAULT;
0673ad47
CW		 356
357 return 0;
358}
359
360static int i915_get_bridge_dev(struct drm_device *dev)
361{
fac5e23e 362 struct drm_i915_private *dev_priv = to_i915(dev);
0673ad47
CW		 363
364 dev_priv->bridge_dev = pci_get_bus_and_slot(0, PCI_DEVFN(0, 0));
365 if (!dev_priv->bridge_dev) {
366 DRM_ERROR("bridge device not found\n");
367 return -1;
368 }
369 return 0;
370}
371
372/* Allocate space for the MCH regs if needed, return nonzero on error */
373static int
374intel_alloc_mchbar_resource(struct drm_device *dev)
375{
fac5e23e 376 struct drm_i915_private *dev_priv = to_i915(dev);
0673ad47
CW		 377 int reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
378 u32 temp_lo, temp_hi = 0;
379 u64 mchbar_addr;
380 int ret;
381
382 if (INTEL_INFO(dev)->gen >= 4)
383 pci_read_config_dword(dev_priv->bridge_dev, reg + 4, &temp_hi);
384 pci_read_config_dword(dev_priv->bridge_dev, reg, &temp_lo);
385 mchbar_addr = ((u64)temp_hi << 32) | temp_lo;
386
387 /* If ACPI doesn't have it, assume we need to allocate it ourselves */
388#ifdef CONFIG_PNP
389 if (mchbar_addr &&
390 pnp_range_reserved(mchbar_addr, mchbar_addr + MCHBAR_SIZE))
391 return 0;
392#endif
393
394 /* Get some space for it */
395 dev_priv->mch_res.name = "i915 MCHBAR";
396 dev_priv->mch_res.flags = IORESOURCE_MEM;
397 ret = pci_bus_alloc_resource(dev_priv->bridge_dev->bus,
398 &dev_priv->mch_res,
399 MCHBAR_SIZE, MCHBAR_SIZE,
400 PCIBIOS_MIN_MEM,
401 0, pcibios_align_resource,
402 dev_priv->bridge_dev);
403 if (ret) {
404 DRM_DEBUG_DRIVER("failed bus alloc: %d\n", ret);
405 dev_priv->mch_res.start = 0;
406 return ret;
407 }
408
409 if (INTEL_INFO(dev)->gen >= 4)
410 pci_write_config_dword(dev_priv->bridge_dev, reg + 4,
411 upper_32_bits(dev_priv->mch_res.start));
412
413 pci_write_config_dword(dev_priv->bridge_dev, reg,
414 lower_32_bits(dev_priv->mch_res.start));
415 return 0;
416}
417
418/* Setup MCHBAR if possible, return true if we should disable it again */
419static void
420intel_setup_mchbar(struct drm_device *dev)
421{
fac5e23e 422 struct drm_i915_private *dev_priv = to_i915(dev);
0673ad47
CW		 423 int mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
424 u32 temp;
425 bool enabled;
426
920a14b2 427 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
0673ad47
CW		 428 return;
429
430 dev_priv->mchbar_need_disable = false;
431
50a0bc90 432 if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
0673ad47
CW		 433 pci_read_config_dword(dev_priv->bridge_dev, DEVEN, &temp);
434 enabled = !!(temp & DEVEN_MCHBAR_EN);
435 } else {
436 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
437 enabled = temp & 1;
438 }
439
440 /* If it's already enabled, don't have to do anything */
441 if (enabled)
442 return;
443
444 if (intel_alloc_mchbar_resource(dev))
445 return;
446
447 dev_priv->mchbar_need_disable = true;
448
449 /* Space is allocated or reserved, so enable it. */
50a0bc90 450 if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
0673ad47
CW		 451 pci_write_config_dword(dev_priv->bridge_dev, DEVEN,
452 temp | DEVEN_MCHBAR_EN);
453 } else {
454 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
455 pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp | 1);
456 }
457}
458
459static void
460intel_teardown_mchbar(struct drm_device *dev)
461{
fac5e23e 462 struct drm_i915_private *dev_priv = to_i915(dev);
0673ad47
CW		 463 int mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
464
465 if (dev_priv->mchbar_need_disable) {
50a0bc90 466 if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
0673ad47
CW		 467 u32 deven_val;
468
469 pci_read_config_dword(dev_priv->bridge_dev, DEVEN,
470 &deven_val);
471 deven_val &= ~DEVEN_MCHBAR_EN;
472 pci_write_config_dword(dev_priv->bridge_dev, DEVEN,
473 deven_val);
474 } else {
475 u32 mchbar_val;
476
477 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg,
478 &mchbar_val);
479 mchbar_val &= ~1;
480 pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg,
481 mchbar_val);
482 }
483 }
484
485 if (dev_priv->mch_res.start)
486 release_resource(&dev_priv->mch_res);
487}
488
489/* true = enable decode, false = disable decoder */
490static unsigned int i915_vga_set_decode(void *cookie, bool state)
491{
492 struct drm_device *dev = cookie;
493
494 intel_modeset_vga_set_state(dev, state);
495 if (state)
496 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
497 VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
498 else
499 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
500}
501
502static void i915_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state)
503{
504 struct drm_device *dev = pci_get_drvdata(pdev);
505 pm_message_t pmm = { .event = PM_EVENT_SUSPEND };
506
507 if (state == VGA_SWITCHEROO_ON) {
508 pr_info("switched on\n");
509 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
510 /* i915 resume handler doesn't set to D0 */
52a05c30 511 pci_set_power_state(pdev, PCI_D0);
0673ad47
CW		 512 i915_resume_switcheroo(dev);
513 dev->switch_power_state = DRM_SWITCH_POWER_ON;
514 } else {
515 pr_info("switched off\n");
516 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
517 i915_suspend_switcheroo(dev, pmm);
518 dev->switch_power_state = DRM_SWITCH_POWER_OFF;
519 }
520}
521
522static bool i915_switcheroo_can_switch(struct pci_dev *pdev)
523{
524 struct drm_device *dev = pci_get_drvdata(pdev);
525
526 /*
527 * FIXME: open_count is protected by drm_global_mutex but that would lead to
528 * locking inversion with the driver load path. And the access here is
529 * completely racy anyway. So don't bother with locking for now.
530 */
531 return dev->open_count == 0;
532}
533
534static const struct vga_switcheroo_client_ops i915_switcheroo_ops = {
535 .set_gpu_state = i915_switcheroo_set_state,
536 .reprobe = NULL,
537 .can_switch = i915_switcheroo_can_switch,
538};
539
540static void i915_gem_fini(struct drm_device *dev)
541{
0673ad47 542 mutex_lock(&dev->struct_mutex);
0673ad47
CW		 543 i915_gem_cleanup_engines(dev);
544 i915_gem_context_fini(dev);
545 mutex_unlock(&dev->struct_mutex);
546
547 WARN_ON(!list_empty(&to_i915(dev)->context_list));
548}
549
550static int i915_load_modeset_init(struct drm_device *dev)
551{
fac5e23e 552 struct drm_i915_private *dev_priv = to_i915(dev);
52a05c30 553 struct pci_dev *pdev = dev_priv->drm.pdev;
0673ad47
CW		 554 int ret;
555
556 if (i915_inject_load_failure())
557 return -ENODEV;
558
559 ret = intel_bios_init(dev_priv);
560 if (ret)
561 DRM_INFO("failed to find VBIOS tables\n");
562
563 /* If we have > 1 VGA cards, then we need to arbitrate access
564 * to the common VGA resources.
565 *
566 * If we are a secondary display controller (!PCI_DISPLAY_CLASS_VGA),
567 * then we do not take part in VGA arbitration and the
568 * vga_client_register() fails with -ENODEV.
569 */
52a05c30 570 ret = vga_client_register(pdev, dev, NULL, i915_vga_set_decode);
0673ad47
CW		 571 if (ret && ret != -ENODEV)
572 goto out;
573
574 intel_register_dsm_handler();
575
52a05c30 576 ret = vga_switcheroo_register_client(pdev, &i915_switcheroo_ops, false);
0673ad47
CW		 577 if (ret)
578 goto cleanup_vga_client;
579
580 /* must happen before intel_power_domains_init_hw() on VLV/CHV */
581 intel_update_rawclk(dev_priv);
582
583 intel_power_domains_init_hw(dev_priv, false);
584
585 intel_csr_ucode_init(dev_priv);
586
587 ret = intel_irq_install(dev_priv);
588 if (ret)
589 goto cleanup_csr;
590
591 intel_setup_gmbus(dev);
592
593 /* Important: The output setup functions called by modeset_init need
594 * working irqs for e.g. gmbus and dp aux transfers. */
595 intel_modeset_init(dev);
596
597 intel_guc_init(dev);
598
599 ret = i915_gem_init(dev);
600 if (ret)
601 goto cleanup_irq;
602
603 intel_modeset_gem_init(dev);
604
605 if (INTEL_INFO(dev)->num_pipes == 0)
606 return 0;
607
608 ret = intel_fbdev_init(dev);
609 if (ret)
610 goto cleanup_gem;
611
612 /* Only enable hotplug handling once the fbdev is fully set up. */
613 intel_hpd_init(dev_priv);
614
615 drm_kms_helper_poll_init(dev);
616
617 return 0;
618
619cleanup_gem:
1c777c5d
ID		 620 if (i915_gem_suspend(dev))
621 DRM_ERROR("failed to idle hardware; continuing to unload!\n");
0673ad47
CW		 622 i915_gem_fini(dev);
623cleanup_irq:
624 intel_guc_fini(dev);
625 drm_irq_uninstall(dev);
626 intel_teardown_gmbus(dev);
627cleanup_csr:
628 intel_csr_ucode_fini(dev_priv);
629 intel_power_domains_fini(dev_priv);
52a05c30 630 vga_switcheroo_unregister_client(pdev);
0673ad47 631cleanup_vga_client:
52a05c30 632 vga_client_register(pdev, NULL, NULL, NULL);
0673ad47
CW		 633out:
634 return ret;
635}
636
637#if IS_ENABLED(CONFIG_FB)
638static int i915_kick_out_firmware_fb(struct drm_i915_private *dev_priv)
639{
640 struct apertures_struct *ap;
91c8a326 641 struct pci_dev *pdev = dev_priv->drm.pdev;
0673ad47
CW		 642 struct i915_ggtt *ggtt = &dev_priv->ggtt;
643 bool primary;
644 int ret;
645
646 ap = alloc_apertures(1);
647 if (!ap)
648 return -ENOMEM;
649
650 ap->ranges[0].base = ggtt->mappable_base;
651 ap->ranges[0].size = ggtt->mappable_end;
652
653 primary =
654 pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW;
655
44adece5 656 ret = drm_fb_helper_remove_conflicting_framebuffers(ap, "inteldrmfb", primary);
0673ad47
CW		 657
658 kfree(ap);
659
660 return ret;
661}
662#else
663static int i915_kick_out_firmware_fb(struct drm_i915_private *dev_priv)
664{
665 return 0;
666}
667#endif
668
669#if !defined(CONFIG_VGA_CONSOLE)
670static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv)
671{
672 return 0;
673}
674#elif !defined(CONFIG_DUMMY_CONSOLE)
675static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv)
676{
677 return -ENODEV;
678}
679#else
680static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv)
681{
682 int ret = 0;
683
684 DRM_INFO("Replacing VGA console driver\n");
685
686 console_lock();
687 if (con_is_bound(&vga_con))
688 ret = do_take_over_console(&dummy_con, 0, MAX_NR_CONSOLES - 1, 1);
689 if (ret == 0) {
690 ret = do_unregister_con_driver(&vga_con);
691
692 /* Ignore "already unregistered". */
693 if (ret == -ENODEV)
694 ret = 0;
695 }
696 console_unlock();
697
698 return ret;
699}
700#endif
701
0673ad47
CW		 702static void intel_init_dpio(struct drm_i915_private *dev_priv)
703{
704 /*
705 * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
706 * CHV x1 PHY (DP/HDMI D)
707 * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
708 */
709 if (IS_CHERRYVIEW(dev_priv)) {
710 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
711 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
712 } else if (IS_VALLEYVIEW(dev_priv)) {
713 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
714 }
715}
716
717static int i915_workqueues_init(struct drm_i915_private *dev_priv)
718{
719 /*
720 * The i915 workqueue is primarily used for batched retirement of
721 * requests (and thus managing bo) once the task has been completed
722 * by the GPU. i915_gem_retire_requests() is called directly when we
723 * need high-priority retirement, such as waiting for an explicit
724 * bo.
725 *
726 * It is also used for periodic low-priority events, such as
727 * idle-timers and recording error state.
728 *
729 * All tasks on the workqueue are expected to acquire the dev mutex
730 * so there is no point in running more than one instance of the
731 * workqueue at any time. Use an ordered one.
732 */
733 dev_priv->wq = alloc_ordered_workqueue("i915", 0);
734 if (dev_priv->wq == NULL)
735 goto out_err;
736
737 dev_priv->hotplug.dp_wq = alloc_ordered_workqueue("i915-dp", 0);
738 if (dev_priv->hotplug.dp_wq == NULL)
739 goto out_free_wq;
740
0673ad47
CW		 741 return 0;
742
0673ad47
CW		 743out_free_wq:
744 destroy_workqueue(dev_priv->wq);
745out_err:
746 DRM_ERROR("Failed to allocate workqueues.\n");
747
748 return -ENOMEM;
749}
750
751static void i915_workqueues_cleanup(struct drm_i915_private *dev_priv)
752{
0673ad47
CW		 753 destroy_workqueue(dev_priv->hotplug.dp_wq);
754 destroy_workqueue(dev_priv->wq);
755}
756
4fc7e845
PZ		 757/*
758 * We don't keep the workarounds for pre-production hardware, so we expect our
759 * driver to fail on these machines in one way or another. A little warning on
760 * dmesg may help both the user and the bug triagers.
761 */
762static void intel_detect_preproduction_hw(struct drm_i915_private *dev_priv)
763{
764 if (IS_HSW_EARLY_SDV(dev_priv) ||
765 IS_SKL_REVID(dev_priv, 0, SKL_REVID_F0))
766 DRM_ERROR("This is a pre-production stepping. "
767 "It may not be fully functional.\n");
768}
769
0673ad47
CW		 770/**
771 * i915_driver_init_early - setup state not requiring device access
772 * @dev_priv: device private
773 *
774 * Initialize everything that is a "SW-only" state, that is state not
775 * requiring accessing the device or exposing the driver via kernel internal
776 * or userspace interfaces. Example steps belonging here: lock initialization,
777 * system memory allocation, setting up device specific attributes and
778 * function hooks not requiring accessing the device.
779 */
780static int i915_driver_init_early(struct drm_i915_private *dev_priv,
781 const struct pci_device_id *ent)
782{
783 const struct intel_device_info *match_info =
784 (struct intel_device_info *)ent->driver_data;
785 struct intel_device_info *device_info;
786 int ret = 0;
787
788 if (i915_inject_load_failure())
789 return -ENODEV;
790
791 /* Setup the write-once "constant" device info */
94b4f3ba 792 device_info = mkwrite_device_info(dev_priv);
0673ad47
CW		 793 memcpy(device_info, match_info, sizeof(*device_info));
794 device_info->device_id = dev_priv->drm.pdev->device;
795
796 BUG_ON(device_info->gen > sizeof(device_info->gen_mask) * BITS_PER_BYTE);
797 device_info->gen_mask = BIT(device_info->gen - 1);
798
799 spin_lock_init(&dev_priv->irq_lock);
800 spin_lock_init(&dev_priv->gpu_error.lock);
801 mutex_init(&dev_priv->backlight_lock);
802 spin_lock_init(&dev_priv->uncore.lock);
803 spin_lock_init(&dev_priv->mm.object_stat_lock);
804 spin_lock_init(&dev_priv->mmio_flip_lock);
805 mutex_init(&dev_priv->sb_lock);
806 mutex_init(&dev_priv->modeset_restore_lock);
807 mutex_init(&dev_priv->av_mutex);
808 mutex_init(&dev_priv->wm.wm_mutex);
809 mutex_init(&dev_priv->pps_mutex);
810
0b1de5d5
CW		 811 i915_memcpy_init_early(dev_priv);
812
0673ad47
CW		 813 ret = i915_workqueues_init(dev_priv);
814 if (ret < 0)
815 return ret;
816
817 ret = intel_gvt_init(dev_priv);
818 if (ret < 0)
819 goto err_workqueues;
820
821 /* This must be called before any calls to HAS_PCH_* */
822 intel_detect_pch(&dev_priv->drm);
823
824 intel_pm_setup(&dev_priv->drm);
825 intel_init_dpio(dev_priv);
826 intel_power_domains_init(dev_priv);
827 intel_irq_init(dev_priv);
828 intel_init_display_hooks(dev_priv);
829 intel_init_clock_gating_hooks(dev_priv);
830 intel_init_audio_hooks(dev_priv);
831 i915_gem_load_init(&dev_priv->drm);
832
36cdd013 833 intel_display_crc_init(dev_priv);
0673ad47 834
94b4f3ba 835 intel_device_info_dump(dev_priv);
0673ad47 836
4fc7e845 837 intel_detect_preproduction_hw(dev_priv);
0673ad47
CW		 838
839 return 0;
840
841err_workqueues:
842 i915_workqueues_cleanup(dev_priv);
843 return ret;
844}
845
846/**
847 * i915_driver_cleanup_early - cleanup the setup done in i915_driver_init_early()
848 * @dev_priv: device private
849 */
850static void i915_driver_cleanup_early(struct drm_i915_private *dev_priv)
851{
91c8a326 852 i915_gem_load_cleanup(&dev_priv->drm);
0673ad47
CW		 853 i915_workqueues_cleanup(dev_priv);
854}
855
856static int i915_mmio_setup(struct drm_device *dev)
857{
858 struct drm_i915_private *dev_priv = to_i915(dev);
52a05c30 859 struct pci_dev *pdev = dev_priv->drm.pdev;
0673ad47
CW		 860 int mmio_bar;
861 int mmio_size;
862
5db94019 863 mmio_bar = IS_GEN2(dev_priv) ? 1 : 0;
0673ad47
CW		 864 /*
865 * Before gen4, the registers and the GTT are behind different BARs.
866 * However, from gen4 onwards, the registers and the GTT are shared
867 * in the same BAR, so we want to restrict this ioremap from
868 * clobbering the GTT which we want ioremap_wc instead. Fortunately,
869 * the register BAR remains the same size for all the earlier
870 * generations up to Ironlake.
871 */
872 if (INTEL_INFO(dev)->gen < 5)
873 mmio_size = 512 * 1024;
874 else
875 mmio_size = 2 * 1024 * 1024;
52a05c30 876 dev_priv->regs = pci_iomap(pdev, mmio_bar, mmio_size);
0673ad47
CW		 877 if (dev_priv->regs == NULL) {
878 DRM_ERROR("failed to map registers\n");
879
880 return -EIO;
881 }
882
883 /* Try to make sure MCHBAR is enabled before poking at it */
884 intel_setup_mchbar(dev);
885
886 return 0;
887}
888
889static void i915_mmio_cleanup(struct drm_device *dev)
890{
891 struct drm_i915_private *dev_priv = to_i915(dev);
52a05c30 892 struct pci_dev *pdev = dev_priv->drm.pdev;
0673ad47
CW		 893
894 intel_teardown_mchbar(dev);
52a05c30 895 pci_iounmap(pdev, dev_priv->regs);
0673ad47
CW		 896}
897
898/**
899 * i915_driver_init_mmio - setup device MMIO
900 * @dev_priv: device private
901 *
902 * Setup minimal device state necessary for MMIO accesses later in the
903 * initialization sequence. The setup here should avoid any other device-wide
904 * side effects or exposing the driver via kernel internal or user space
905 * interfaces.
906 */
907static int i915_driver_init_mmio(struct drm_i915_private *dev_priv)
908{
91c8a326 909 struct drm_device *dev = &dev_priv->drm;
0673ad47
CW		 910 int ret;
911
912 if (i915_inject_load_failure())
913 return -ENODEV;
914
915 if (i915_get_bridge_dev(dev))
916 return -EIO;
917
918 ret = i915_mmio_setup(dev);
919 if (ret < 0)
920 goto put_bridge;
921
922 intel_uncore_init(dev_priv);
923
924 return 0;
925
926put_bridge:
927 pci_dev_put(dev_priv->bridge_dev);
928
929 return ret;
930}
931
932/**
933 * i915_driver_cleanup_mmio - cleanup the setup done in i915_driver_init_mmio()
934 * @dev_priv: device private
935 */
936static void i915_driver_cleanup_mmio(struct drm_i915_private *dev_priv)
937{
91c8a326 938 struct drm_device *dev = &dev_priv->drm;
0673ad47
CW		 939
940 intel_uncore_fini(dev_priv);
941 i915_mmio_cleanup(dev);
942 pci_dev_put(dev_priv->bridge_dev);
943}
944
94b4f3ba
CW		 945static void intel_sanitize_options(struct drm_i915_private *dev_priv)
946{
947 i915.enable_execlists =
948 intel_sanitize_enable_execlists(dev_priv,
949 i915.enable_execlists);
950
951 /*
952 * i915.enable_ppgtt is read-only, so do an early pass to validate the
953 * user's requested state against the hardware/driver capabilities. We
954 * do this now so that we can print out any log messages once rather
955 * than every time we check intel_enable_ppgtt().
956 */
957 i915.enable_ppgtt =
958 intel_sanitize_enable_ppgtt(dev_priv, i915.enable_ppgtt);
959 DRM_DEBUG_DRIVER("ppgtt mode: %i\n", i915.enable_ppgtt);
39df9190
CW		 960
961 i915.semaphores = intel_sanitize_semaphores(dev_priv, i915.semaphores);
962 DRM_DEBUG_DRIVER("use GPU sempahores? %s\n", yesno(i915.semaphores));
94b4f3ba
CW		 963}
964
0673ad47
CW		 965/**
966 * i915_driver_init_hw - setup state requiring device access
967 * @dev_priv: device private
968 *
969 * Setup state that requires accessing the device, but doesn't require
970 * exposing the driver via kernel internal or userspace interfaces.
971 */
972static int i915_driver_init_hw(struct drm_i915_private *dev_priv)
973{
52a05c30 974 struct pci_dev *pdev = dev_priv->drm.pdev;
91c8a326 975 struct drm_device *dev = &dev_priv->drm;
0673ad47
CW		 976 int ret;
977
978 if (i915_inject_load_failure())
979 return -ENODEV;
980
94b4f3ba
CW		 981 intel_device_info_runtime_init(dev_priv);
982
983 intel_sanitize_options(dev_priv);
0673ad47 984
97d6d7ab 985 ret = i915_ggtt_probe_hw(dev_priv);
0673ad47
CW		 986 if (ret)
987 return ret;
988
0673ad47
CW		 989 /* WARNING: Apparently we must kick fbdev drivers before vgacon,
990 * otherwise the vga fbdev driver falls over. */
991 ret = i915_kick_out_firmware_fb(dev_priv);
992 if (ret) {
993 DRM_ERROR("failed to remove conflicting framebuffer drivers\n");
994 goto out_ggtt;
995 }
996
997 ret = i915_kick_out_vgacon(dev_priv);
998 if (ret) {
999 DRM_ERROR("failed to remove conflicting VGA console\n");
1000 goto out_ggtt;
1001 }
1002
97d6d7ab 1003 ret = i915_ggtt_init_hw(dev_priv);
0088e522
CW		 1004 if (ret)
1005 return ret;
1006
97d6d7ab 1007 ret = i915_ggtt_enable_hw(dev_priv);
0088e522
CW		 1008 if (ret) {
1009 DRM_ERROR("failed to enable GGTT\n");
1010 goto out_ggtt;
1011 }
1012
52a05c30 1013 pci_set_master(pdev);
0673ad47
CW		 1014
1015 /* overlay on gen2 is broken and can't address above 1G */
5db94019 1016 if (IS_GEN2(dev_priv)) {
52a05c30 1017 ret = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(30));
0673ad47
CW		 1018 if (ret) {
1019 DRM_ERROR("failed to set DMA mask\n");
1020
1021 goto out_ggtt;
1022 }
1023 }
1024
0673ad47
CW		 1025 /* 965GM sometimes incorrectly writes to hardware status page (HWS)
1026 * using 32bit addressing, overwriting memory if HWS is located
1027 * above 4GB.
1028 *
1029 * The documentation also mentions an issue with undefined
1030 * behaviour if any general state is accessed within a page above 4GB,
1031 * which also needs to be handled carefully.
1032 */
1033 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev)) {
52a05c30 1034 ret = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
0673ad47
CW		 1035
1036 if (ret) {
1037 DRM_ERROR("failed to set DMA mask\n");
1038
1039 goto out_ggtt;
1040 }
1041 }
1042
0673ad47
CW		 1043 pm_qos_add_request(&dev_priv->pm_qos, PM_QOS_CPU_DMA_LATENCY,
1044 PM_QOS_DEFAULT_VALUE);
1045
1046 intel_uncore_sanitize(dev_priv);
1047
1048 intel_opregion_setup(dev_priv);
1049
1050 i915_gem_load_init_fences(dev_priv);
1051
1052 /* On the 945G/GM, the chipset reports the MSI capability on the
1053 * integrated graphics even though the support isn't actually there
1054 * according to the published specs. It doesn't appear to function
1055 * correctly in testing on 945G.
1056 * This may be a side effect of MSI having been made available for PEG
1057 * and the registers being closely associated.
1058 *
1059 * According to chipset errata, on the 965GM, MSI interrupts may
1060 * be lost or delayed, but we use them anyways to avoid
1061 * stuck interrupts on some machines.
1062 */
50a0bc90 1063 if (!IS_I945G(dev_priv) && !IS_I945GM(dev_priv)) {
52a05c30 1064 if (pci_enable_msi(pdev) < 0)
0673ad47
CW		 1065 DRM_DEBUG_DRIVER("can't enable MSI");
1066 }
1067
1068 return 0;
1069
1070out_ggtt:
97d6d7ab 1071 i915_ggtt_cleanup_hw(dev_priv);
0673ad47
CW		 1072
1073 return ret;
1074}
1075
1076/**
1077 * i915_driver_cleanup_hw - cleanup the setup done in i915_driver_init_hw()
1078 * @dev_priv: device private
1079 */
1080static void i915_driver_cleanup_hw(struct drm_i915_private *dev_priv)
1081{
52a05c30 1082 struct pci_dev *pdev = dev_priv->drm.pdev;
0673ad47 1083
52a05c30
DW		 1084 if (pdev->msi_enabled)
1085 pci_disable_msi(pdev);
0673ad47
CW		 1086
1087 pm_qos_remove_request(&dev_priv->pm_qos);
97d6d7ab 1088 i915_ggtt_cleanup_hw(dev_priv);
0673ad47
CW		 1089}
1090
1091/**
1092 * i915_driver_register - register the driver with the rest of the system
1093 * @dev_priv: device private
1094 *
1095 * Perform any steps necessary to make the driver available via kernel
1096 * internal or userspace interfaces.
1097 */
1098static void i915_driver_register(struct drm_i915_private *dev_priv)
1099{
91c8a326 1100 struct drm_device *dev = &dev_priv->drm;
0673ad47
CW		 1101
1102 i915_gem_shrinker_init(dev_priv);
1103
1104 /*
1105 * Notify a valid surface after modesetting,
1106 * when running inside a VM.
1107 */
1108 if (intel_vgpu_active(dev_priv))
1109 I915_WRITE(vgtif_reg(display_ready), VGT_DRV_DISPLAY_READY);
1110
1111 /* Reveal our presence to userspace */
1112 if (drm_dev_register(dev, 0) == 0) {
1113 i915_debugfs_register(dev_priv);
f8240835 1114 i915_guc_register(dev_priv);
694c2828 1115 i915_setup_sysfs(dev_priv);
0673ad47
CW		 1116 } else
1117 DRM_ERROR("Failed to register driver for userspace access!\n");
1118
1119 if (INTEL_INFO(dev_priv)->num_pipes) {
1120 /* Must be done after probing outputs */
1121 intel_opregion_register(dev_priv);
1122 acpi_video_register();
1123 }
1124
1125 if (IS_GEN5(dev_priv))
1126 intel_gpu_ips_init(dev_priv);
1127
1128 i915_audio_component_init(dev_priv);
1129
1130 /*
1131 * Some ports require correctly set-up hpd registers for detection to
1132 * work properly (leading to ghost connected connector status), e.g. VGA
1133 * on gm45. Hence we can only set up the initial fbdev config after hpd
1134 * irqs are fully enabled. We do it last so that the async config
1135 * cannot run before the connectors are registered.
1136 */
1137 intel_fbdev_initial_config_async(dev);
1138}
1139
1140/**
1141 * i915_driver_unregister - cleanup the registration done in i915_driver_regiser()
1142 * @dev_priv: device private
1143 */
1144static void i915_driver_unregister(struct drm_i915_private *dev_priv)
1145{
1146 i915_audio_component_cleanup(dev_priv);
1147
1148 intel_gpu_ips_teardown();
1149 acpi_video_unregister();
1150 intel_opregion_unregister(dev_priv);
1151
694c2828 1152 i915_teardown_sysfs(dev_priv);
f8240835 1153 i915_guc_unregister(dev_priv);
0673ad47 1154 i915_debugfs_unregister(dev_priv);
91c8a326 1155 drm_dev_unregister(&dev_priv->drm);
0673ad47
CW		 1156
1157 i915_gem_shrinker_cleanup(dev_priv);
1158}
1159
1160/**
1161 * i915_driver_load - setup chip and create an initial config
1162 * @dev: DRM device
1163 * @flags: startup flags
1164 *
1165 * The driver load routine has to do several things:
1166 * - drive output discovery via intel_modeset_init()
1167 * - initialize the memory manager
1168 * - allocate initial config memory
1169 * - setup the DRM framebuffer with the allocated memory
1170 */
42f5551d 1171int i915_driver_load(struct pci_dev *pdev, const struct pci_device_id *ent)
0673ad47
CW		 1172{
1173 struct drm_i915_private *dev_priv;
1174 int ret;
7d87a7f7 1175
a09d0ba1
CW		 1176 if (i915.nuclear_pageflip)
1177 driver.driver_features |= DRIVER_ATOMIC;
1178
0673ad47
CW		 1179 ret = -ENOMEM;
1180 dev_priv = kzalloc(sizeof(*dev_priv), GFP_KERNEL);
1181 if (dev_priv)
1182 ret = drm_dev_init(&dev_priv->drm, &driver, &pdev->dev);
1183 if (ret) {
1184 dev_printk(KERN_ERR, &pdev->dev,
1185 "[" DRM_NAME ":%s] allocation failed\n", __func__);
1186 kfree(dev_priv);
1187 return ret;
1188 }
72bbf0af 1189
0673ad47
CW		 1190 dev_priv->drm.pdev = pdev;
1191 dev_priv->drm.dev_private = dev_priv;
719388e1 1192
0673ad47
CW		 1193 ret = pci_enable_device(pdev);
1194 if (ret)
1195 goto out_free_priv;
1347f5b4 1196
0673ad47 1197 pci_set_drvdata(pdev, &dev_priv->drm);
ef11bdb3 1198
0673ad47
CW		 1199 ret = i915_driver_init_early(dev_priv, ent);
1200 if (ret < 0)
1201 goto out_pci_disable;
ef11bdb3 1202
0673ad47 1203 intel_runtime_pm_get(dev_priv);
1da177e4 1204
0673ad47
CW		 1205 ret = i915_driver_init_mmio(dev_priv);
1206 if (ret < 0)
1207 goto out_runtime_pm_put;
79e53945 1208
0673ad47
CW		 1209 ret = i915_driver_init_hw(dev_priv);
1210 if (ret < 0)
1211 goto out_cleanup_mmio;
30c964a6
RB		 1212
1213 /*
0673ad47
CW		 1214 * TODO: move the vblank init and parts of modeset init steps into one
1215 * of the i915_driver_init_/i915_driver_register functions according
1216 * to the role/effect of the given init step.
30c964a6 1217 */
0673ad47 1218 if (INTEL_INFO(dev_priv)->num_pipes) {
91c8a326 1219 ret = drm_vblank_init(&dev_priv->drm,
0673ad47
CW		 1220 INTEL_INFO(dev_priv)->num_pipes);
1221 if (ret)
1222 goto out_cleanup_hw;
30c964a6
RB		 1223 }
1224
91c8a326 1225 ret = i915_load_modeset_init(&dev_priv->drm);
0673ad47
CW		 1226 if (ret < 0)
1227 goto out_cleanup_vblank;
1228
1229 i915_driver_register(dev_priv);
1230
1231 intel_runtime_pm_enable(dev_priv);
1232
bc5ca47c
CW		 1233 /* Everything is in place, we can now relax! */
1234 DRM_INFO("Initialized %s %d.%d.%d %s for %s on minor %d\n",
1235 driver.name, driver.major, driver.minor, driver.patchlevel,
1236 driver.date, pci_name(pdev), dev_priv->drm.primary->index);
0525a062
CW		 1237 if (IS_ENABLED(CONFIG_DRM_I915_DEBUG))
1238 DRM_INFO("DRM_I915_DEBUG enabled\n");
1239 if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM))
1240 DRM_INFO("DRM_I915_DEBUG_GEM enabled\n");
bc5ca47c 1241
0673ad47
CW		 1242 intel_runtime_pm_put(dev_priv);
1243
1244 return 0;
1245
1246out_cleanup_vblank:
91c8a326 1247 drm_vblank_cleanup(&dev_priv->drm);
0673ad47
CW		 1248out_cleanup_hw:
1249 i915_driver_cleanup_hw(dev_priv);
1250out_cleanup_mmio:
1251 i915_driver_cleanup_mmio(dev_priv);
1252out_runtime_pm_put:
1253 intel_runtime_pm_put(dev_priv);
1254 i915_driver_cleanup_early(dev_priv);
1255out_pci_disable:
1256 pci_disable_device(pdev);
1257out_free_priv:
1258 i915_load_error(dev_priv, "Device initialization failed (%d)\n", ret);
1259 drm_dev_unref(&dev_priv->drm);
30c964a6
RB		 1260 return ret;
1261}
1262
42f5551d 1263void i915_driver_unload(struct drm_device *dev)
3bad0781 1264{
fac5e23e 1265 struct drm_i915_private *dev_priv = to_i915(dev);
52a05c30 1266 struct pci_dev *pdev = dev_priv->drm.pdev;
3bad0781 1267
0673ad47
CW		 1268 intel_fbdev_fini(dev);
1269
42f5551d
CW		 1270 if (i915_gem_suspend(dev))
1271 DRM_ERROR("failed to idle hardware; continuing to unload!\n");
ce1bb329 1272
0673ad47
CW		 1273 intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
1274
1275 i915_driver_unregister(dev_priv);
1276
1277 drm_vblank_cleanup(dev);
1278
1279 intel_modeset_cleanup(dev);
1280
3bad0781 1281 /*
0673ad47
CW		 1282 * free the memory space allocated for the child device
1283 * config parsed from VBT
3bad0781 1284 */
0673ad47
CW		 1285 if (dev_priv->vbt.child_dev && dev_priv->vbt.child_dev_num) {
1286 kfree(dev_priv->vbt.child_dev);
1287 dev_priv->vbt.child_dev = NULL;
1288 dev_priv->vbt.child_dev_num = 0;
1289 }
1290 kfree(dev_priv->vbt.sdvo_lvds_vbt_mode);
1291 dev_priv->vbt.sdvo_lvds_vbt_mode = NULL;
1292 kfree(dev_priv->vbt.lfp_lvds_vbt_mode);
1293 dev_priv->vbt.lfp_lvds_vbt_mode = NULL;
3bad0781 1294
52a05c30
DW		 1295 vga_switcheroo_unregister_client(pdev);
1296 vga_client_register(pdev, NULL, NULL, NULL);
bcdb72ac 1297
0673ad47 1298 intel_csr_ucode_fini(dev_priv);
bcdb72ac 1299
0673ad47
CW		 1300 /* Free error state after interrupts are fully disabled. */
1301 cancel_delayed_work_sync(&dev_priv->gpu_error.hangcheck_work);
1302 i915_destroy_error_state(dev);
1303
1304 /* Flush any outstanding unpin_work. */
b7137e0c 1305 drain_workqueue(dev_priv->wq);
0673ad47
CW		 1306
1307 intel_guc_fini(dev);
1308 i915_gem_fini(dev);
1309 intel_fbc_cleanup_cfb(dev_priv);
1310
1311 intel_power_domains_fini(dev_priv);
1312
1313 i915_driver_cleanup_hw(dev_priv);
1314 i915_driver_cleanup_mmio(dev_priv);
1315
1316 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
1317
1318 i915_driver_cleanup_early(dev_priv);
3bad0781
ZW		 1319}
1320
0673ad47 1321static int i915_driver_open(struct drm_device *dev, struct drm_file *file)
2911a35b 1322{
0673ad47 1323 int ret;
2911a35b 1324
0673ad47
CW		 1325 ret = i915_gem_open(dev, file);
1326 if (ret)
1327 return ret;
2911a35b 1328
0673ad47
CW		 1329 return 0;
1330}
71386ef9 1331
0673ad47
CW		 1332/**
1333 * i915_driver_lastclose - clean up after all DRM clients have exited
1334 * @dev: DRM device
1335 *
1336 * Take care of cleaning up after all DRM clients have exited. In the
1337 * mode setting case, we want to restore the kernel's initial mode (just
1338 * in case the last client left us in a bad state).
1339 *
1340 * Additionally, in the non-mode setting case, we'll tear down the GTT
1341 * and DMA structures, since the kernel won't be using them, and clea
1342 * up any GEM state.
1343 */
1344static void i915_driver_lastclose(struct drm_device *dev)
1345{
1346 intel_fbdev_restore_mode(dev);
1347 vga_switcheroo_process_delayed_switch();
1348}
2911a35b 1349
0673ad47
CW		 1350static void i915_driver_preclose(struct drm_device *dev, struct drm_file *file)
1351{
1352 mutex_lock(&dev->struct_mutex);
1353 i915_gem_context_close(dev, file);
1354 i915_gem_release(dev, file);
1355 mutex_unlock(&dev->struct_mutex);
1356}
1357
1358static void i915_driver_postclose(struct drm_device *dev, struct drm_file *file)
1359{
1360 struct drm_i915_file_private *file_priv = file->driver_priv;
1361
1362 kfree(file_priv);
2911a35b
BW		 1363}
1364
07f9cd0b
ID		 1365static void intel_suspend_encoders(struct drm_i915_private *dev_priv)
1366{
91c8a326 1367 struct drm_device *dev = &dev_priv->drm;
19c8054c 1368 struct intel_encoder *encoder;
07f9cd0b
ID		 1369
1370 drm_modeset_lock_all(dev);
19c8054c
JN		 1371 for_each_intel_encoder(dev, encoder)
1372 if (encoder->suspend)
1373 encoder->suspend(encoder);
07f9cd0b
ID		 1374 drm_modeset_unlock_all(dev);
1375}
1376
1a5df187
PZ		 1377static int vlv_resume_prepare(struct drm_i915_private *dev_priv,
1378 bool rpm_resume);
507e126e 1379static int vlv_suspend_complete(struct drm_i915_private *dev_priv);
f75a1985 1380
bc87229f
ID		 1381static bool suspend_to_idle(struct drm_i915_private *dev_priv)
1382{
1383#if IS_ENABLED(CONFIG_ACPI_SLEEP)
1384 if (acpi_target_system_state() < ACPI_STATE_S3)
1385 return true;
1386#endif
1387 return false;
1388}
ebc32824 1389
5e365c39 1390static int i915_drm_suspend(struct drm_device *dev)
ba8bbcf6 1391{
fac5e23e 1392 struct drm_i915_private *dev_priv = to_i915(dev);
52a05c30 1393 struct pci_dev *pdev = dev_priv->drm.pdev;
e5747e3a 1394 pci_power_t opregion_target_state;
d5818938 1395 int error;
61caf87c 1396
b8efb17b
ZR		 1397 /* ignore lid events during suspend */
1398 mutex_lock(&dev_priv->modeset_restore_lock);
1399 dev_priv->modeset_restore = MODESET_SUSPENDED;
1400 mutex_unlock(&dev_priv->modeset_restore_lock);
1401
1f814dac
ID		 1402 disable_rpm_wakeref_asserts(dev_priv);
1403
c67a470b
PZ		 1404 /* We do a lot of poking in a lot of registers, make sure they work
1405 * properly. */
da7e29bd 1406 intel_display_set_init_power(dev_priv, true);
cb10799c 1407
5bcf719b
DA		 1408 drm_kms_helper_poll_disable(dev);
1409
52a05c30 1410 pci_save_state(pdev);
ba8bbcf6 1411
d5818938
DV		 1412 error = i915_gem_suspend(dev);
1413 if (error) {
52a05c30 1414 dev_err(&pdev->dev,
d5818938 1415 "GEM idle failed, resume might fail\n");
1f814dac 1416 goto out;
d5818938 1417 }
db1b76ca 1418
a1c41994
AD		 1419 intel_guc_suspend(dev);
1420
6b72d486 1421 intel_display_suspend(dev);
2eb5252e 1422
d5818938 1423 intel_dp_mst_suspend(dev);
7d708ee4 1424
d5818938
DV		 1425 intel_runtime_pm_disable_interrupts(dev_priv);
1426 intel_hpd_cancel_work(dev_priv);
09b64267 1427
d5818938 1428 intel_suspend_encoders(dev_priv);
0e32b39c 1429
d5818938 1430 intel_suspend_hw(dev);
5669fcac 1431
828c7908
BW		 1432 i915_gem_suspend_gtt_mappings(dev);
1433
9e06dd39
JB		 1434 i915_save_state(dev);
1435
bc87229f 1436 opregion_target_state = suspend_to_idle(dev_priv) ? PCI_D1 : PCI_D3cold;
6f9f4b7a 1437 intel_opregion_notify_adapter(dev_priv, opregion_target_state);
e5747e3a 1438
dc97997a 1439 intel_uncore_forcewake_reset(dev_priv, false);
03d92e47 1440 intel_opregion_unregister(dev_priv);
8ee1c3db 1441
82e3b8c1 1442 intel_fbdev_set_suspend(dev, FBINFO_STATE_SUSPENDED, true);
3fa016a0 1443
62d5d69b
MK		 1444 dev_priv->suspend_count++;
1445
f74ed08d 1446 intel_csr_ucode_suspend(dev_priv);
f514c2d8 1447
1f814dac
ID		 1448out:
1449 enable_rpm_wakeref_asserts(dev_priv);
1450
1451 return error;
84b79f8d
RW		 1452}
1453
c49d13ee 1454static int i915_drm_suspend_late(struct drm_device *dev, bool hibernation)
c3c09c95 1455{
c49d13ee 1456 struct drm_i915_private *dev_priv = to_i915(dev);
52a05c30 1457 struct pci_dev *pdev = dev_priv->drm.pdev;
bc87229f 1458 bool fw_csr;
c3c09c95
ID		 1459 int ret;
1460
1f814dac
ID		 1461 disable_rpm_wakeref_asserts(dev_priv);
1462
4c494a57
ID		 1463 intel_display_set_init_power(dev_priv, false);
1464
a7c8125f
ID		 1465 fw_csr = !IS_BROXTON(dev_priv) &&
1466 suspend_to_idle(dev_priv) && dev_priv->csr.dmc_payload;
bc87229f
ID		 1467 /*
1468 * In case of firmware assisted context save/restore don't manually
1469 * deinit the power domains. This also means the CSR/DMC firmware will
1470 * stay active, it will power down any HW resources as required and
1471 * also enable deeper system power states that would be blocked if the
1472 * firmware was inactive.
1473 */
1474 if (!fw_csr)
1475 intel_power_domains_suspend(dev_priv);
73dfc227 1476
507e126e 1477 ret = 0;
b8aea3d1 1478 if (IS_BROXTON(dev_priv))
507e126e 1479 bxt_enable_dc9(dev_priv);
b8aea3d1 1480 else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
507e126e
ID		 1481 hsw_enable_pc8(dev_priv);
1482 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1483 ret = vlv_suspend_complete(dev_priv);
c3c09c95
ID		 1484
1485 if (ret) {
1486 DRM_ERROR("Suspend complete failed: %d\n", ret);
bc87229f
ID		 1487 if (!fw_csr)
1488 intel_power_domains_init_hw(dev_priv, true);
c3c09c95 1489
1f814dac 1490 goto out;
c3c09c95
ID		 1491 }
1492
52a05c30 1493 pci_disable_device(pdev);
ab3be73f 1494 /*
54875571 1495 * During hibernation on some platforms the BIOS may try to access
ab3be73f
ID		 1496 * the device even though it's already in D3 and hang the machine. So
1497 * leave the device in D0 on those platforms and hope the BIOS will
54875571
ID		 1498 * power down the device properly. The issue was seen on multiple old
1499 * GENs with different BIOS vendors, so having an explicit blacklist
1500 * is inpractical; apply the workaround on everything pre GEN6. The
1501 * platforms where the issue was seen:
1502 * Lenovo Thinkpad X301, X61s, X60, T60, X41
1503 * Fujitsu FSC S7110
1504 * Acer Aspire 1830T
ab3be73f 1505 */
54875571 1506 if (!(hibernation && INTEL_INFO(dev_priv)->gen < 6))
52a05c30 1507 pci_set_power_state(pdev, PCI_D3hot);
c3c09c95 1508
bc87229f
ID		 1509 dev_priv->suspended_to_idle = suspend_to_idle(dev_priv);
1510
1f814dac
ID		 1511out:
1512 enable_rpm_wakeref_asserts(dev_priv);
1513
1514 return ret;
c3c09c95
ID		 1515}
1516
1751fcf9 1517int i915_suspend_switcheroo(struct drm_device *dev, pm_message_t state)
84b79f8d
RW		 1518{
1519 int error;
1520
ded8b07d 1521 if (!dev) {
84b79f8d
RW		 1522 DRM_ERROR("dev: %p\n", dev);
1523 DRM_ERROR("DRM not initialized, aborting suspend.\n");
1524 return -ENODEV;
1525 }
1526
0b14cbd2
ID		 1527 if (WARN_ON_ONCE(state.event != PM_EVENT_SUSPEND &&
1528 state.event != PM_EVENT_FREEZE))
1529 return -EINVAL;
5bcf719b
DA		 1530
1531 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1532 return 0;
6eecba33 1533
5e365c39 1534 error = i915_drm_suspend(dev);
84b79f8d
RW		 1535 if (error)
1536 return error;
1537
ab3be73f 1538 return i915_drm_suspend_late(dev, false);
ba8bbcf6
JB		 1539}
1540
5e365c39 1541static int i915_drm_resume(struct drm_device *dev)
76c4b250 1542{
fac5e23e 1543 struct drm_i915_private *dev_priv = to_i915(dev);
ac840ae5 1544 int ret;
9d49c0ef 1545
1f814dac 1546 disable_rpm_wakeref_asserts(dev_priv);
abc80abd 1547 intel_sanitize_gt_powersave(dev_priv);
1f814dac 1548
97d6d7ab 1549 ret = i915_ggtt_enable_hw(dev_priv);
ac840ae5
VS		 1550 if (ret)
1551 DRM_ERROR("failed to re-enable GGTT\n");
1552
f74ed08d
ID		 1553 intel_csr_ucode_resume(dev_priv);
1554
5ab57c70 1555 i915_gem_resume(dev);
9d49c0ef 1556
61caf87c 1557 i915_restore_state(dev);
8090ba8c 1558 intel_pps_unlock_regs_wa(dev_priv);
6f9f4b7a 1559 intel_opregion_setup(dev_priv);
61caf87c 1560
d5818938
DV		 1561 intel_init_pch_refclk(dev);
1562 drm_mode_config_reset(dev);
1833b134 1563
364aece0
PA		 1564 /*
1565 * Interrupts have to be enabled before any batches are run. If not the
1566 * GPU will hang. i915_gem_init_hw() will initiate batches to
1567 * update/restore the context.
1568 *
1569 * Modeset enabling in intel_modeset_init_hw() also needs working
1570 * interrupts.
1571 */
1572 intel_runtime_pm_enable_interrupts(dev_priv);
1573
d5818938
DV		 1574 mutex_lock(&dev->struct_mutex);
1575 if (i915_gem_init_hw(dev)) {
1576 DRM_ERROR("failed to re-initialize GPU, declaring wedged!\n");
821ed7df 1577 i915_gem_set_wedged(dev_priv);
d5818938
DV		 1578 }
1579 mutex_unlock(&dev->struct_mutex);
226485e9 1580
a1c41994
AD		 1581 intel_guc_resume(dev);
1582
d5818938 1583 intel_modeset_init_hw(dev);
24576d23 1584
d5818938
DV		 1585 spin_lock_irq(&dev_priv->irq_lock);
1586 if (dev_priv->display.hpd_irq_setup)
91d14251 1587 dev_priv->display.hpd_irq_setup(dev_priv);
d5818938 1588 spin_unlock_irq(&dev_priv->irq_lock);
0e32b39c 1589
d5818938 1590 intel_dp_mst_resume(dev);
e7d6f7d7 1591
a16b7658
L		 1592 intel_display_resume(dev);
1593
d5818938
DV		 1594 /*
1595 * ... but also need to make sure that hotplug processing
1596 * doesn't cause havoc. Like in the driver load code we don't
1597 * bother with the tiny race here where we might loose hotplug
1598 * notifications.
1599 * */
1600 intel_hpd_init(dev_priv);
1601 /* Config may have changed between suspend and resume */
1602 drm_helper_hpd_irq_event(dev);
1daed3fb 1603
03d92e47 1604 intel_opregion_register(dev_priv);
44834a67 1605
82e3b8c1 1606 intel_fbdev_set_suspend(dev, FBINFO_STATE_RUNNING, false);
073f34d9 1607
b8efb17b
ZR		 1608 mutex_lock(&dev_priv->modeset_restore_lock);
1609 dev_priv->modeset_restore = MODESET_DONE;
1610 mutex_unlock(&dev_priv->modeset_restore_lock);
8a187455 1611
6f9f4b7a 1612 intel_opregion_notify_adapter(dev_priv, PCI_D0);
e5747e3a 1613
54b4f68f 1614 intel_autoenable_gt_powersave(dev_priv);
ee6f280e
ID		 1615 drm_kms_helper_poll_enable(dev);
1616
1f814dac
ID		 1617 enable_rpm_wakeref_asserts(dev_priv);
1618
074c6ada 1619 return 0;
84b79f8d
RW		 1620}
1621
5e365c39 1622static int i915_drm_resume_early(struct drm_device *dev)
84b79f8d 1623{
fac5e23e 1624 struct drm_i915_private *dev_priv = to_i915(dev);
52a05c30 1625 struct pci_dev *pdev = dev_priv->drm.pdev;
44410cd0 1626 int ret;
36d61e67 1627
76c4b250
ID		 1628 /*
1629 * We have a resume ordering issue with the snd-hda driver also
1630 * requiring our device to be power up. Due to the lack of a
1631 * parent/child relationship we currently solve this with an early
1632 * resume hook.
1633 *
1634 * FIXME: This should be solved with a special hdmi sink device or
1635 * similar so that power domains can be employed.
1636 */
44410cd0
ID		 1637
1638 /*
1639 * Note that we need to set the power state explicitly, since we
1640 * powered off the device during freeze and the PCI core won't power
1641 * it back up for us during thaw. Powering off the device during
1642 * freeze is not a hard requirement though, and during the
1643 * suspend/resume phases the PCI core makes sure we get here with the
1644 * device powered on. So in case we change our freeze logic and keep
1645 * the device powered we can also remove the following set power state
1646 * call.
1647 */
52a05c30 1648 ret = pci_set_power_state(pdev, PCI_D0);
44410cd0
ID		 1649 if (ret) {
1650 DRM_ERROR("failed to set PCI D0 power state (%d)\n", ret);
1651 goto out;
1652 }
1653
1654 /*
1655 * Note that pci_enable_device() first enables any parent bridge
1656 * device and only then sets the power state for this device. The
1657 * bridge enabling is a nop though, since bridge devices are resumed
1658 * first. The order of enabling power and enabling the device is
1659 * imposed by the PCI core as described above, so here we preserve the
1660 * same order for the freeze/thaw phases.
1661 *
1662 * TODO: eventually we should remove pci_disable_device() /
1663 * pci_enable_enable_device() from suspend/resume. Due to how they
1664 * depend on the device enable refcount we can't anyway depend on them
1665 * disabling/enabling the device.
1666 */
52a05c30 1667 if (pci_enable_device(pdev)) {
bc87229f
ID		 1668 ret = -EIO;
1669 goto out;
1670 }
84b79f8d 1671
52a05c30 1672 pci_set_master(pdev);
84b79f8d 1673
1f814dac
ID		 1674 disable_rpm_wakeref_asserts(dev_priv);
1675
666a4537 1676 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1a5df187 1677 ret = vlv_resume_prepare(dev_priv, false);
36d61e67 1678 if (ret)
ff0b187f
DL		 1679 DRM_ERROR("Resume prepare failed: %d, continuing anyway\n",
1680 ret);
36d61e67 1681
dc97997a 1682 intel_uncore_early_sanitize(dev_priv, true);
efee833a 1683
dc97997a 1684 if (IS_BROXTON(dev_priv)) {
da2f41d1
ID		 1685 if (!dev_priv->suspended_to_idle)
1686 gen9_sanitize_dc_state(dev_priv);
507e126e 1687 bxt_disable_dc9(dev_priv);
da2f41d1 1688 } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
a9a6b73a 1689 hsw_disable_pc8(dev_priv);
da2f41d1 1690 }
efee833a 1691
dc97997a 1692 intel_uncore_sanitize(dev_priv);
bc87229f 1693
a7c8125f
ID		 1694 if (IS_BROXTON(dev_priv) ||
1695 !(dev_priv->suspended_to_idle && dev_priv->csr.dmc_payload))
bc87229f
ID		 1696 intel_power_domains_init_hw(dev_priv, true);
1697
6e35e8ab
ID		 1698 enable_rpm_wakeref_asserts(dev_priv);
1699
bc87229f
ID		 1700out:
1701 dev_priv->suspended_to_idle = false;
36d61e67
ID		 1702
1703 return ret;
76c4b250
ID		 1704}
1705
1751fcf9 1706int i915_resume_switcheroo(struct drm_device *dev)
76c4b250 1707{
50a0072f 1708 int ret;
76c4b250 1709
097dd837
ID		 1710 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1711 return 0;
1712
5e365c39 1713 ret = i915_drm_resume_early(dev);
50a0072f
ID		 1714 if (ret)
1715 return ret;
1716
5a17514e
ID		 1717 return i915_drm_resume(dev);
1718}
1719
9e60ab03
CW		 1720static void disable_engines_irq(struct drm_i915_private *dev_priv)
1721{
1722 struct intel_engine_cs *engine;
3b3f1650 1723 enum intel_engine_id id;
9e60ab03
CW		 1724
1725 /* Ensure irq handler finishes, and not run again. */
1726 disable_irq(dev_priv->drm.irq);
3b3f1650 1727 for_each_engine(engine, dev_priv, id)
9e60ab03
CW		 1728 tasklet_kill(&engine->irq_tasklet);
1729}
1730
1731static void enable_engines_irq(struct drm_i915_private *dev_priv)
1732{
1733 enable_irq(dev_priv->drm.irq);
1734}
1735
11ed50ec 1736/**
f3953dcb 1737 * i915_reset - reset chip after a hang
11ed50ec 1738 * @dev: drm device to reset
11ed50ec 1739 *
780f262a
CW		 1740 * Reset the chip. Useful if a hang is detected. Marks the device as wedged
1741 * on failure.
11ed50ec 1742 *
221fe799
CW		 1743 * Caller must hold the struct_mutex.
1744 *
11ed50ec
BG		 1745 * Procedure is fairly simple:
1746 * - reset the chip using the reset reg
1747 * - re-init context state
1748 * - re-init hardware status page
1749 * - re-init ring buffer
1750 * - re-init interrupt state
1751 * - re-init display
1752 */
780f262a 1753void i915_reset(struct drm_i915_private *dev_priv)
11ed50ec 1754{
91c8a326 1755 struct drm_device *dev = &dev_priv->drm;
d98c52cf 1756 struct i915_gpu_error *error = &dev_priv->gpu_error;
0573ed4a 1757 int ret;
11ed50ec 1758
221fe799
CW		 1759 lockdep_assert_held(&dev->struct_mutex);
1760
1761 if (!test_and_clear_bit(I915_RESET_IN_PROGRESS, &error->flags))
780f262a 1762 return;
11ed50ec 1763
d98c52cf 1764 /* Clear any previous failed attempts at recovery. Time to try again. */
8af29b0c
CW		 1765 __clear_bit(I915_WEDGED, &error->flags);
1766 error->reset_count++;
d98c52cf 1767
7b4d3a16 1768 pr_notice("drm/i915: Resetting chip after gpu hang\n");
9e60ab03
CW		 1769
1770 disable_engines_irq(dev_priv);
dc97997a 1771 ret = intel_gpu_reset(dev_priv, ALL_ENGINES);
9e60ab03
CW		 1772 enable_engines_irq(dev_priv);
1773
0573ed4a 1774 if (ret) {
804e59a8
CW		 1775 if (ret != -ENODEV)
1776 DRM_ERROR("Failed to reset chip: %i\n", ret);
1777 else
1778 DRM_DEBUG_DRIVER("GPU reset disabled\n");
d98c52cf 1779 goto error;
11ed50ec
BG		 1780 }
1781
821ed7df 1782 i915_gem_reset(dev_priv);
1362b776
VS		 1783 intel_overlay_reset(dev_priv);
1784
11ed50ec
BG		 1785 /* Ok, now get things going again... */
1786
1787 /*
1788 * Everything depends on having the GTT running, so we need to start
1789 * there. Fortunately we don't need to do this unless we reset the
1790 * chip at a PCI level.
1791 *
1792 * Next we need to restore the context, but we don't use those
1793 * yet either...
1794 *
1795 * Ring buffer needs to be re-initialized in the KMS case, or if X
1796 * was running at the time of the reset (i.e. we weren't VT
1797 * switched away).
1798 */
33d30a9c 1799 ret = i915_gem_init_hw(dev);
33d30a9c
DV		 1800 if (ret) {
1801 DRM_ERROR("Failed hw init on reset %d\n", ret);
d98c52cf 1802 goto error;
11ed50ec
BG		 1803 }
1804
780f262a
CW		 1805wakeup:
1806 wake_up_bit(&error->flags, I915_RESET_IN_PROGRESS);
1807 return;
d98c52cf
CW		 1808
1809error:
821ed7df 1810 i915_gem_set_wedged(dev_priv);
780f262a 1811 goto wakeup;
11ed50ec
BG		 1812}
1813
c49d13ee 1814static int i915_pm_suspend(struct device *kdev)
112b715e 1815{
c49d13ee
DW		 1816 struct pci_dev *pdev = to_pci_dev(kdev);
1817 struct drm_device *dev = pci_get_drvdata(pdev);
112b715e 1818
c49d13ee
DW		 1819 if (!dev) {
1820 dev_err(kdev, "DRM not initialized, aborting suspend.\n");
84b79f8d
RW		 1821 return -ENODEV;
1822 }
112b715e 1823
c49d13ee 1824 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
5bcf719b
DA		 1825 return 0;
1826
c49d13ee 1827 return i915_drm_suspend(dev);
76c4b250
ID		 1828}
1829
c49d13ee 1830static int i915_pm_suspend_late(struct device *kdev)
76c4b250 1831{
c49d13ee 1832 struct drm_device *dev = &kdev_to_i915(kdev)->drm;
76c4b250
ID		 1833
1834 /*
c965d995 1835 * We have a suspend ordering issue with the snd-hda driver also
76c4b250
ID		 1836 * requiring our device to be power up. Due to the lack of a
1837 * parent/child relationship we currently solve this with an late
1838 * suspend hook.
1839 *
1840 * FIXME: This should be solved with a special hdmi sink device or
1841 * similar so that power domains can be employed.
1842 */
c49d13ee 1843 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
76c4b250 1844 return 0;
112b715e 1845
c49d13ee 1846 return i915_drm_suspend_late(dev, false);
ab3be73f
ID		 1847}
1848
c49d13ee 1849static int i915_pm_poweroff_late(struct device *kdev)
ab3be73f 1850{
c49d13ee 1851 struct drm_device *dev = &kdev_to_i915(kdev)->drm;
ab3be73f 1852
c49d13ee 1853 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
ab3be73f
ID		 1854 return 0;
1855
c49d13ee 1856 return i915_drm_suspend_late(dev, true);
cbda12d7
ZW		 1857}
1858
c49d13ee 1859static int i915_pm_resume_early(struct device *kdev)
76c4b250 1860{
c49d13ee 1861 struct drm_device *dev = &kdev_to_i915(kdev)->drm;
76c4b250 1862
c49d13ee 1863 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
097dd837
ID		 1864 return 0;
1865
c49d13ee 1866 return i915_drm_resume_early(dev);
76c4b250
ID		 1867}
1868
c49d13ee 1869static int i915_pm_resume(struct device *kdev)
cbda12d7 1870{
c49d13ee 1871 struct drm_device *dev = &kdev_to_i915(kdev)->drm;
84b79f8d 1872
c49d13ee 1873 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
097dd837
ID		 1874 return 0;
1875
c49d13ee 1876 return i915_drm_resume(dev);
cbda12d7
ZW		 1877}
1878
1f19ac2a 1879/* freeze: before creating the hibernation_image */
c49d13ee 1880static int i915_pm_freeze(struct device *kdev)
1f19ac2a 1881{
6a800eab
CW		 1882 int ret;
1883
1884 ret = i915_pm_suspend(kdev);
1885 if (ret)
1886 return ret;
1887
1888 ret = i915_gem_freeze(kdev_to_i915(kdev));
1889 if (ret)
1890 return ret;
1891
1892 return 0;
1f19ac2a
CW		 1893}
1894
c49d13ee 1895static int i915_pm_freeze_late(struct device *kdev)
1f19ac2a 1896{
461fb99c
CW		 1897 int ret;
1898
c49d13ee 1899 ret = i915_pm_suspend_late(kdev);
461fb99c
CW		 1900 if (ret)
1901 return ret;
1902
c49d13ee 1903 ret = i915_gem_freeze_late(kdev_to_i915(kdev));
461fb99c
CW		 1904 if (ret)
1905 return ret;
1906
1907 return 0;
1f19ac2a
CW		 1908}
1909
1910/* thaw: called after creating the hibernation image, but before turning off. */
c49d13ee 1911static int i915_pm_thaw_early(struct device *kdev)
1f19ac2a 1912{
c49d13ee 1913 return i915_pm_resume_early(kdev);
1f19ac2a
CW		 1914}
1915
c49d13ee 1916static int i915_pm_thaw(struct device *kdev)
1f19ac2a 1917{
c49d13ee 1918 return i915_pm_resume(kdev);
1f19ac2a
CW		 1919}
1920
1921/* restore: called after loading the hibernation image. */
c49d13ee 1922static int i915_pm_restore_early(struct device *kdev)
1f19ac2a 1923{
c49d13ee 1924 return i915_pm_resume_early(kdev);
1f19ac2a
CW		 1925}
1926
c49d13ee 1927static int i915_pm_restore(struct device *kdev)
1f19ac2a 1928{
c49d13ee 1929 return i915_pm_resume(kdev);
1f19ac2a
CW		 1930}
1931
ddeea5b0
ID		 1932/*
1933 * Save all Gunit registers that may be lost after a D3 and a subsequent
1934 * S0i[R123] transition. The list of registers needing a save/restore is
1935 * defined in the VLV2_S0IXRegs document. This documents marks all Gunit
1936 * registers in the following way:
1937 * - Driver: saved/restored by the driver
1938 * - Punit : saved/restored by the Punit firmware
1939 * - No, w/o marking: no need to save/restore, since the register is R/O or
1940 * used internally by the HW in a way that doesn't depend
1941 * keeping the content across a suspend/resume.
1942 * - Debug : used for debugging
1943 *
1944 * We save/restore all registers marked with 'Driver', with the following
1945 * exceptions:
1946 * - Registers out of use, including also registers marked with 'Debug'.
1947 * These have no effect on the driver's operation, so we don't save/restore
1948 * them to reduce the overhead.
1949 * - Registers that are fully setup by an initialization function called from
1950 * the resume path. For example many clock gating and RPS/RC6 registers.
1951 * - Registers that provide the right functionality with their reset defaults.
1952 *
1953 * TODO: Except for registers that based on the above 3 criteria can be safely
1954 * ignored, we save/restore all others, practically treating the HW context as
1955 * a black-box for the driver. Further investigation is needed to reduce the
1956 * saved/restored registers even further, by following the same 3 criteria.
1957 */
1958static void vlv_save_gunit_s0ix_state(struct drm_i915_private *dev_priv)
1959{
1960 struct vlv_s0ix_state *s = &dev_priv->vlv_s0ix_state;
1961 int i;
1962
1963 /* GAM 0x4000-0x4770 */
1964 s->wr_watermark = I915_READ(GEN7_WR_WATERMARK);
1965 s->gfx_prio_ctrl = I915_READ(GEN7_GFX_PRIO_CTRL);
1966 s->arb_mode = I915_READ(ARB_MODE);
1967 s->gfx_pend_tlb0 = I915_READ(GEN7_GFX_PEND_TLB0);
1968 s->gfx_pend_tlb1 = I915_READ(GEN7_GFX_PEND_TLB1);
1969
1970 for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++)
22dfe79f 1971 s->lra_limits[i] = I915_READ(GEN7_LRA_LIMITS(i));
ddeea5b0
ID		 1972
1973 s->media_max_req_count = I915_READ(GEN7_MEDIA_MAX_REQ_COUNT);
b5f1c97f 1974 s->gfx_max_req_count = I915_READ(GEN7_GFX_MAX_REQ_COUNT);
ddeea5b0
ID		 1975
1976 s->render_hwsp = I915_READ(RENDER_HWS_PGA_GEN7);
1977 s->ecochk = I915_READ(GAM_ECOCHK);
1978 s->bsd_hwsp = I915_READ(BSD_HWS_PGA_GEN7);
1979 s->blt_hwsp = I915_READ(BLT_HWS_PGA_GEN7);
1980
1981 s->tlb_rd_addr = I915_READ(GEN7_TLB_RD_ADDR);
1982
1983 /* MBC 0x9024-0x91D0, 0x8500 */
1984 s->g3dctl = I915_READ(VLV_G3DCTL);
1985 s->gsckgctl = I915_READ(VLV_GSCKGCTL);
1986 s->mbctl = I915_READ(GEN6_MBCTL);
1987
1988 /* GCP 0x9400-0x9424, 0x8100-0x810C */
1989 s->ucgctl1 = I915_READ(GEN6_UCGCTL1);
1990 s->ucgctl3 = I915_READ(GEN6_UCGCTL3);
1991 s->rcgctl1 = I915_READ(GEN6_RCGCTL1);
1992 s->rcgctl2 = I915_READ(GEN6_RCGCTL2);
1993 s->rstctl = I915_READ(GEN6_RSTCTL);
1994 s->misccpctl = I915_READ(GEN7_MISCCPCTL);
1995
1996 /* GPM 0xA000-0xAA84, 0x8000-0x80FC */
1997 s->gfxpause = I915_READ(GEN6_GFXPAUSE);
1998 s->rpdeuhwtc = I915_READ(GEN6_RPDEUHWTC);
1999 s->rpdeuc = I915_READ(GEN6_RPDEUC);
2000 s->ecobus = I915_READ(ECOBUS);
2001 s->pwrdwnupctl = I915_READ(VLV_PWRDWNUPCTL);
2002 s->rp_down_timeout = I915_READ(GEN6_RP_DOWN_TIMEOUT);
2003 s->rp_deucsw = I915_READ(GEN6_RPDEUCSW);
2004 s->rcubmabdtmr = I915_READ(GEN6_RCUBMABDTMR);
2005 s->rcedata = I915_READ(VLV_RCEDATA);
2006 s->spare2gh = I915_READ(VLV_SPAREG2H);
2007
2008 /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */
2009 s->gt_imr = I915_READ(GTIMR);
2010 s->gt_ier = I915_READ(GTIER);
2011 s->pm_imr = I915_READ(GEN6_PMIMR);
2012 s->pm_ier = I915_READ(GEN6_PMIER);
2013
2014 for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++)
22dfe79f 2015 s->gt_scratch[i] = I915_READ(GEN7_GT_SCRATCH(i));
ddeea5b0
ID		 2016
2017 /* GT SA CZ domain, 0x100000-0x138124 */
2018 s->tilectl = I915_READ(TILECTL);
2019 s->gt_fifoctl = I915_READ(GTFIFOCTL);
2020 s->gtlc_wake_ctrl = I915_READ(VLV_GTLC_WAKE_CTRL);
2021 s->gtlc_survive = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
2022 s->pmwgicz = I915_READ(VLV_PMWGICZ);
2023
2024 /* Gunit-Display CZ domain, 0x182028-0x1821CF */
2025 s->gu_ctl0 = I915_READ(VLV_GU_CTL0);
2026 s->gu_ctl1 = I915_READ(VLV_GU_CTL1);
9c25210f 2027 s->pcbr = I915_READ(VLV_PCBR);
ddeea5b0
ID		 2028 s->clock_gate_dis2 = I915_READ(VLV_GUNIT_CLOCK_GATE2);
2029
2030 /*
2031 * Not saving any of:
2032 * DFT, 0x9800-0x9EC0
2033 * SARB, 0xB000-0xB1FC
2034 * GAC, 0x5208-0x524C, 0x14000-0x14C000
2035 * PCI CFG
2036 */
2037}
2038
2039static void vlv_restore_gunit_s0ix_state(struct drm_i915_private *dev_priv)
2040{
2041 struct vlv_s0ix_state *s = &dev_priv->vlv_s0ix_state;
2042 u32 val;
2043 int i;
2044
2045 /* GAM 0x4000-0x4770 */
2046 I915_WRITE(GEN7_WR_WATERMARK, s->wr_watermark);
2047 I915_WRITE(GEN7_GFX_PRIO_CTRL, s->gfx_prio_ctrl);
2048 I915_WRITE(ARB_MODE, s->arb_mode | (0xffff << 16));
2049 I915_WRITE(GEN7_GFX_PEND_TLB0, s->gfx_pend_tlb0);
2050 I915_WRITE(GEN7_GFX_PEND_TLB1, s->gfx_pend_tlb1);
2051
2052 for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++)
22dfe79f 2053 I915_WRITE(GEN7_LRA_LIMITS(i), s->lra_limits[i]);
ddeea5b0
ID		 2054
2055 I915_WRITE(GEN7_MEDIA_MAX_REQ_COUNT, s->media_max_req_count);
b5f1c97f 2056 I915_WRITE(GEN7_GFX_MAX_REQ_COUNT, s->gfx_max_req_count);
ddeea5b0
ID		 2057
2058 I915_WRITE(RENDER_HWS_PGA_GEN7, s->render_hwsp);
2059 I915_WRITE(GAM_ECOCHK, s->ecochk);
2060 I915_WRITE(BSD_HWS_PGA_GEN7, s->bsd_hwsp);
2061 I915_WRITE(BLT_HWS_PGA_GEN7, s->blt_hwsp);
2062
2063 I915_WRITE(GEN7_TLB_RD_ADDR, s->tlb_rd_addr);
2064
2065 /* MBC 0x9024-0x91D0, 0x8500 */
2066 I915_WRITE(VLV_G3DCTL, s->g3dctl);
2067 I915_WRITE(VLV_GSCKGCTL, s->gsckgctl);
2068 I915_WRITE(GEN6_MBCTL, s->mbctl);
2069
2070 /* GCP 0x9400-0x9424, 0x8100-0x810C */
2071 I915_WRITE(GEN6_UCGCTL1, s->ucgctl1);
2072 I915_WRITE(GEN6_UCGCTL3, s->ucgctl3);
2073 I915_WRITE(GEN6_RCGCTL1, s->rcgctl1);
2074 I915_WRITE(GEN6_RCGCTL2, s->rcgctl2);
2075 I915_WRITE(GEN6_RSTCTL, s->rstctl);
2076 I915_WRITE(GEN7_MISCCPCTL, s->misccpctl);
2077
2078 /* GPM 0xA000-0xAA84, 0x8000-0x80FC */
2079 I915_WRITE(GEN6_GFXPAUSE, s->gfxpause);
2080 I915_WRITE(GEN6_RPDEUHWTC, s->rpdeuhwtc);
2081 I915_WRITE(GEN6_RPDEUC, s->rpdeuc);
2082 I915_WRITE(ECOBUS, s->ecobus);
2083 I915_WRITE(VLV_PWRDWNUPCTL, s->pwrdwnupctl);
2084 I915_WRITE(GEN6_RP_DOWN_TIMEOUT,s->rp_down_timeout);
2085 I915_WRITE(GEN6_RPDEUCSW, s->rp_deucsw);
2086 I915_WRITE(GEN6_RCUBMABDTMR, s->rcubmabdtmr);
2087 I915_WRITE(VLV_RCEDATA, s->rcedata);
2088 I915_WRITE(VLV_SPAREG2H, s->spare2gh);
2089
2090 /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */
2091 I915_WRITE(GTIMR, s->gt_imr);
2092 I915_WRITE(GTIER, s->gt_ier);
2093 I915_WRITE(GEN6_PMIMR, s->pm_imr);
2094 I915_WRITE(GEN6_PMIER, s->pm_ier);
2095
2096 for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++)
22dfe79f 2097 I915_WRITE(GEN7_GT_SCRATCH(i), s->gt_scratch[i]);
ddeea5b0
ID		 2098
2099 /* GT SA CZ domain, 0x100000-0x138124 */
2100 I915_WRITE(TILECTL, s->tilectl);
2101 I915_WRITE(GTFIFOCTL, s->gt_fifoctl);
2102 /*
2103 * Preserve the GT allow wake and GFX force clock bit, they are not
2104 * be restored, as they are used to control the s0ix suspend/resume
2105 * sequence by the caller.
2106 */
2107 val = I915_READ(VLV_GTLC_WAKE_CTRL);
2108 val &= VLV_GTLC_ALLOWWAKEREQ;
2109 val |= s->gtlc_wake_ctrl & ~VLV_GTLC_ALLOWWAKEREQ;
2110 I915_WRITE(VLV_GTLC_WAKE_CTRL, val);
2111
2112 val = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
2113 val &= VLV_GFX_CLK_FORCE_ON_BIT;
2114 val |= s->gtlc_survive & ~VLV_GFX_CLK_FORCE_ON_BIT;
2115 I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, val);
2116
2117 I915_WRITE(VLV_PMWGICZ, s->pmwgicz);
2118
2119 /* Gunit-Display CZ domain, 0x182028-0x1821CF */
2120 I915_WRITE(VLV_GU_CTL0, s->gu_ctl0);
2121 I915_WRITE(VLV_GU_CTL1, s->gu_ctl1);
9c25210f 2122 I915_WRITE(VLV_PCBR, s->pcbr);
ddeea5b0
ID		 2123 I915_WRITE(VLV_GUNIT_CLOCK_GATE2, s->clock_gate_dis2);
2124}
2125
650ad970
ID		 2126int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool force_on)
2127{
2128 u32 val;
2129 int err;
2130
650ad970
ID		 2131 val = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
2132 val &= ~VLV_GFX_CLK_FORCE_ON_BIT;
2133 if (force_on)
2134 val |= VLV_GFX_CLK_FORCE_ON_BIT;
2135 I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, val);
2136
2137 if (!force_on)
2138 return 0;
2139
c6ddc5f3
CW		 2140 err = intel_wait_for_register(dev_priv,
2141 VLV_GTLC_SURVIVABILITY_REG,
2142 VLV_GFX_CLK_STATUS_BIT,
2143 VLV_GFX_CLK_STATUS_BIT,
2144 20);
650ad970
ID		 2145 if (err)
2146 DRM_ERROR("timeout waiting for GFX clock force-on (%08x)\n",
2147 I915_READ(VLV_GTLC_SURVIVABILITY_REG));
2148
2149 return err;
650ad970
ID		 2150}
2151
ddeea5b0
ID		 2152static int vlv_allow_gt_wake(struct drm_i915_private *dev_priv, bool allow)
2153{
2154 u32 val;
2155 int err = 0;
2156
2157 val = I915_READ(VLV_GTLC_WAKE_CTRL);
2158 val &= ~VLV_GTLC_ALLOWWAKEREQ;
2159 if (allow)
2160 val |= VLV_GTLC_ALLOWWAKEREQ;
2161 I915_WRITE(VLV_GTLC_WAKE_CTRL, val);
2162 POSTING_READ(VLV_GTLC_WAKE_CTRL);
2163
b2736695
CW		 2164 err = intel_wait_for_register(dev_priv,
2165 VLV_GTLC_PW_STATUS,
2166 VLV_GTLC_ALLOWWAKEACK,
2167 allow,
2168 1);
ddeea5b0
ID		 2169 if (err)
2170 DRM_ERROR("timeout disabling GT waking\n");
b2736695 2171
ddeea5b0 2172 return err;
ddeea5b0
ID		 2173}
2174
2175static int vlv_wait_for_gt_wells(struct drm_i915_private *dev_priv,
2176 bool wait_for_on)
2177{
2178 u32 mask;
2179 u32 val;
2180 int err;
2181
2182 mask = VLV_GTLC_PW_MEDIA_STATUS_MASK | VLV_GTLC_PW_RENDER_STATUS_MASK;
2183 val = wait_for_on ? mask : 0;
41ce405e 2184 if ((I915_READ(VLV_GTLC_PW_STATUS) & mask) == val)
ddeea5b0
ID		 2185 return 0;
2186
2187 DRM_DEBUG_KMS("waiting for GT wells to go %s (%08x)\n",
87ad3212
JN		 2188 onoff(wait_for_on),
2189 I915_READ(VLV_GTLC_PW_STATUS));
ddeea5b0
ID		 2190
2191 /*
2192 * RC6 transitioning can be delayed up to 2 msec (see
2193 * valleyview_enable_rps), use 3 msec for safety.
2194 */
41ce405e
CW		 2195 err = intel_wait_for_register(dev_priv,
2196 VLV_GTLC_PW_STATUS, mask, val,
2197 3);
ddeea5b0
ID		 2198 if (err)
2199 DRM_ERROR("timeout waiting for GT wells to go %s\n",
87ad3212 2200 onoff(wait_for_on));
ddeea5b0
ID		 2201
2202 return err;
ddeea5b0
ID		 2203}
2204
2205static void vlv_check_no_gt_access(struct drm_i915_private *dev_priv)
2206{
2207 if (!(I915_READ(VLV_GTLC_PW_STATUS) & VLV_GTLC_ALLOWWAKEERR))
2208 return;
2209
6fa283b0 2210 DRM_DEBUG_DRIVER("GT register access while GT waking disabled\n");
ddeea5b0
ID		 2211 I915_WRITE(VLV_GTLC_PW_STATUS, VLV_GTLC_ALLOWWAKEERR);
2212}
2213
ebc32824 2214static int vlv_suspend_complete(struct drm_i915_private *dev_priv)
ddeea5b0
ID		 2215{
2216 u32 mask;
2217 int err;
2218
2219 /*
2220 * Bspec defines the following GT well on flags as debug only, so
2221 * don't treat them as hard failures.
2222 */
2223 (void)vlv_wait_for_gt_wells(dev_priv, false);
2224
2225 mask = VLV_GTLC_RENDER_CTX_EXISTS | VLV_GTLC_MEDIA_CTX_EXISTS;
2226 WARN_ON((I915_READ(VLV_GTLC_WAKE_CTRL) & mask) != mask);
2227
2228 vlv_check_no_gt_access(dev_priv);
2229
2230 err = vlv_force_gfx_clock(dev_priv, true);
2231 if (err)
2232 goto err1;
2233
2234 err = vlv_allow_gt_wake(dev_priv, false);
2235 if (err)
2236 goto err2;
98711167 2237
2d1fe073 2238 if (!IS_CHERRYVIEW(dev_priv))
98711167 2239 vlv_save_gunit_s0ix_state(dev_priv);
ddeea5b0
ID		 2240
2241 err = vlv_force_gfx_clock(dev_priv, false);
2242 if (err)
2243 goto err2;
2244
2245 return 0;
2246
2247err2:
2248 /* For safety always re-enable waking and disable gfx clock forcing */
2249 vlv_allow_gt_wake(dev_priv, true);
2250err1:
2251 vlv_force_gfx_clock(dev_priv, false);
2252
2253 return err;
2254}
2255
016970be
SK		 2256static int vlv_resume_prepare(struct drm_i915_private *dev_priv,
2257 bool rpm_resume)
ddeea5b0 2258{
91c8a326 2259 struct drm_device *dev = &dev_priv->drm;
ddeea5b0
ID		 2260 int err;
2261 int ret;
2262
2263 /*
2264 * If any of the steps fail just try to continue, that's the best we
2265 * can do at this point. Return the first error code (which will also
2266 * leave RPM permanently disabled).
2267 */
2268 ret = vlv_force_gfx_clock(dev_priv, true);
2269
2d1fe073 2270 if (!IS_CHERRYVIEW(dev_priv))
98711167 2271 vlv_restore_gunit_s0ix_state(dev_priv);
ddeea5b0
ID		 2272
2273 err = vlv_allow_gt_wake(dev_priv, true);
2274 if (!ret)
2275 ret = err;
2276
2277 err = vlv_force_gfx_clock(dev_priv, false);
2278 if (!ret)
2279 ret = err;
2280
2281 vlv_check_no_gt_access(dev_priv);
2282
7c108fd8 2283 if (rpm_resume)
016970be 2284 intel_init_clock_gating(dev);
ddeea5b0
ID		 2285
2286 return ret;
2287}
2288
c49d13ee 2289static int intel_runtime_suspend(struct device *kdev)
8a187455 2290{
c49d13ee 2291 struct pci_dev *pdev = to_pci_dev(kdev);
8a187455 2292 struct drm_device *dev = pci_get_drvdata(pdev);
fac5e23e 2293 struct drm_i915_private *dev_priv = to_i915(dev);
0ab9cfeb 2294 int ret;
8a187455 2295
dc97997a 2296 if (WARN_ON_ONCE(!(dev_priv->rps.enabled && intel_enable_rc6())))
c6df39b5
ID		 2297 return -ENODEV;
2298
6772ffe0 2299 if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev_priv)))
604effb7
ID		 2300 return -ENODEV;
2301
8a187455
PZ		 2302 DRM_DEBUG_KMS("Suspending device\n");
2303
1f814dac
ID		 2304 disable_rpm_wakeref_asserts(dev_priv);
2305
d6102977
ID		 2306 /*
2307 * We are safe here against re-faults, since the fault handler takes
2308 * an RPM reference.
2309 */
7c108fd8 2310 i915_gem_runtime_suspend(dev_priv);
d6102977 2311
a1c41994
AD		 2312 intel_guc_suspend(dev);
2313
2eb5252e 2314 intel_runtime_pm_disable_interrupts(dev_priv);
b5478bcd 2315
507e126e
ID		 2316 ret = 0;
2317 if (IS_BROXTON(dev_priv)) {
2318 bxt_display_core_uninit(dev_priv);
2319 bxt_enable_dc9(dev_priv);
2320 } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
2321 hsw_enable_pc8(dev_priv);
2322 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
2323 ret = vlv_suspend_complete(dev_priv);
2324 }
2325
0ab9cfeb
ID		 2326 if (ret) {
2327 DRM_ERROR("Runtime suspend failed, disabling it (%d)\n", ret);
b963291c 2328 intel_runtime_pm_enable_interrupts(dev_priv);
0ab9cfeb 2329
1f814dac
ID		 2330 enable_rpm_wakeref_asserts(dev_priv);
2331
0ab9cfeb
ID		 2332 return ret;
2333 }
a8a8bd54 2334
dc97997a 2335 intel_uncore_forcewake_reset(dev_priv, false);
1f814dac
ID		 2336
2337 enable_rpm_wakeref_asserts(dev_priv);
2338 WARN_ON_ONCE(atomic_read(&dev_priv->pm.wakeref_count));
55ec45c2 2339
bc3b9346 2340 if (intel_uncore_arm_unclaimed_mmio_detection(dev_priv))
55ec45c2
MK		 2341 DRM_ERROR("Unclaimed access detected prior to suspending\n");
2342
8a187455 2343 dev_priv->pm.suspended = true;
1fb2362b
KCA		 2344
2345 /*
c8a0bd42
PZ		 2346 * FIXME: We really should find a document that references the arguments
2347 * used below!
1fb2362b 2348 */
6f9f4b7a 2349 if (IS_BROADWELL(dev_priv)) {
d37ae19a
PZ		 2350 /*
2351 * On Broadwell, if we use PCI_D1 the PCH DDI ports will stop
2352 * being detected, and the call we do at intel_runtime_resume()
2353 * won't be able to restore them. Since PCI_D3hot matches the
2354 * actual specification and appears to be working, use it.
2355 */
6f9f4b7a 2356 intel_opregion_notify_adapter(dev_priv, PCI_D3hot);
d37ae19a 2357 } else {
c8a0bd42
PZ		 2358 /*
2359 * current versions of firmware which depend on this opregion
2360 * notification have repurposed the D1 definition to mean
2361 * "runtime suspended" vs. what you would normally expect (D3)
2362 * to distinguish it from notifications that might be sent via
2363 * the suspend path.
2364 */
6f9f4b7a 2365 intel_opregion_notify_adapter(dev_priv, PCI_D1);
c8a0bd42 2366 }
8a187455 2367
59bad947 2368 assert_forcewakes_inactive(dev_priv);
dc9fb09c 2369
19625e85
L		 2370 if (!IS_VALLEYVIEW(dev_priv) || !IS_CHERRYVIEW(dev_priv))
2371 intel_hpd_poll_init(dev_priv);
2372
a8a8bd54 2373 DRM_DEBUG_KMS("Device suspended\n");
8a187455
PZ		 2374 return 0;
2375}
2376
c49d13ee 2377static int intel_runtime_resume(struct device *kdev)
8a187455 2378{
c49d13ee 2379 struct pci_dev *pdev = to_pci_dev(kdev);
8a187455 2380 struct drm_device *dev = pci_get_drvdata(pdev);
fac5e23e 2381 struct drm_i915_private *dev_priv = to_i915(dev);
1a5df187 2382 int ret = 0;
8a187455 2383
6772ffe0 2384 if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev_priv)))
604effb7 2385 return -ENODEV;
8a187455
PZ		 2386
2387 DRM_DEBUG_KMS("Resuming device\n");
2388
1f814dac
ID		 2389 WARN_ON_ONCE(atomic_read(&dev_priv->pm.wakeref_count));
2390 disable_rpm_wakeref_asserts(dev_priv);
2391
6f9f4b7a 2392 intel_opregion_notify_adapter(dev_priv, PCI_D0);
8a187455 2393 dev_priv->pm.suspended = false;
55ec45c2
MK		 2394 if (intel_uncore_unclaimed_mmio(dev_priv))
2395 DRM_DEBUG_DRIVER("Unclaimed access during suspend, bios?\n");
8a187455 2396
a1c41994
AD		 2397 intel_guc_resume(dev);
2398
1a5df187
PZ		 2399 if (IS_GEN6(dev_priv))
2400 intel_init_pch_refclk(dev);
31335cec 2401
e2d214ae 2402 if (IS_BROXTON(dev_priv)) {
507e126e
ID		 2403 bxt_disable_dc9(dev_priv);
2404 bxt_display_core_init(dev_priv, true);
f62c79b3
ID		 2405 if (dev_priv->csr.dmc_payload &&
2406 (dev_priv->csr.allowed_dc_mask & DC_STATE_EN_UPTO_DC5))
2407 gen9_enable_dc5(dev_priv);
507e126e 2408 } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
1a5df187 2409 hsw_disable_pc8(dev_priv);
507e126e 2410 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1a5df187 2411 ret = vlv_resume_prepare(dev_priv, true);
507e126e 2412 }
1a5df187 2413
0ab9cfeb
ID		 2414 /*
2415 * No point of rolling back things in case of an error, as the best
2416 * we can do is to hope that things will still work (and disable RPM).
2417 */
92b806d3 2418 i915_gem_init_swizzling(dev);
92b806d3 2419
b963291c 2420 intel_runtime_pm_enable_interrupts(dev_priv);
08d8a232
VS		 2421
2422 /*
2423 * On VLV/CHV display interrupts are part of the display
2424 * power well, so hpd is reinitialized from there. For
2425 * everyone else do it here.
2426 */
666a4537 2427 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv))
08d8a232
VS		 2428 intel_hpd_init(dev_priv);
2429
1f814dac
ID		 2430 enable_rpm_wakeref_asserts(dev_priv);
2431
0ab9cfeb
ID		 2432 if (ret)
2433 DRM_ERROR("Runtime resume failed, disabling it (%d)\n", ret);
2434 else
2435 DRM_DEBUG_KMS("Device resumed\n");
2436
2437 return ret;
8a187455
PZ		 2438}
2439
42f5551d 2440const struct dev_pm_ops i915_pm_ops = {
5545dbbf
ID		 2441 /*
2442 * S0ix (via system suspend) and S3 event handlers [PMSG_SUSPEND,
2443 * PMSG_RESUME]
2444 */
0206e353 2445 .suspend = i915_pm_suspend,
76c4b250
ID		 2446 .suspend_late = i915_pm_suspend_late,
2447 .resume_early = i915_pm_resume_early,
0206e353 2448 .resume = i915_pm_resume,
5545dbbf
ID		 2449
2450 /*
2451 * S4 event handlers
2452 * @freeze, @freeze_late : called (1) before creating the
2453 * hibernation image [PMSG_FREEZE] and
2454 * (2) after rebooting, before restoring
2455 * the image [PMSG_QUIESCE]
2456 * @thaw, @thaw_early : called (1) after creating the hibernation
2457 * image, before writing it [PMSG_THAW]
2458 * and (2) after failing to create or
2459 * restore the image [PMSG_RECOVER]
2460 * @poweroff, @poweroff_late: called after writing the hibernation
2461 * image, before rebooting [PMSG_HIBERNATE]
2462 * @restore, @restore_early : called after rebooting and restoring the
2463 * hibernation image [PMSG_RESTORE]
2464 */
1f19ac2a
CW		 2465 .freeze = i915_pm_freeze,
2466 .freeze_late = i915_pm_freeze_late,
2467 .thaw_early = i915_pm_thaw_early,
2468 .thaw = i915_pm_thaw,
36d61e67 2469 .poweroff = i915_pm_suspend,
ab3be73f 2470 .poweroff_late = i915_pm_poweroff_late,
1f19ac2a
CW		 2471 .restore_early = i915_pm_restore_early,
2472 .restore = i915_pm_restore,
5545dbbf
ID		 2473
2474 /* S0ix (via runtime suspend) event handlers */
97bea207
PZ		 2475 .runtime_suspend = intel_runtime_suspend,
2476 .runtime_resume = intel_runtime_resume,
cbda12d7
ZW		 2477};
2478
78b68556 2479static const struct vm_operations_struct i915_gem_vm_ops = {
de151cf6 2480 .fault = i915_gem_fault,
ab00b3e5
JB		 2481 .open = drm_gem_vm_open,
2482 .close = drm_gem_vm_close,
de151cf6
JB		 2483};
2484
e08e96de
AV		 2485static const struct file_operations i915_driver_fops = {
2486 .owner = THIS_MODULE,
2487 .open = drm_open,
2488 .release = drm_release,
2489 .unlocked_ioctl = drm_ioctl,
2490 .mmap = drm_gem_mmap,
2491 .poll = drm_poll,
e08e96de
AV		 2492 .read = drm_read,
2493#ifdef CONFIG_COMPAT
2494 .compat_ioctl = i915_compat_ioctl,
2495#endif
2496 .llseek = noop_llseek,
2497};
2498
0673ad47
CW		 2499static int
2500i915_gem_reject_pin_ioctl(struct drm_device *dev, void *data,
2501 struct drm_file *file)
2502{
2503 return -ENODEV;
2504}
2505
2506static const struct drm_ioctl_desc i915_ioctls[] = {
2507 DRM_IOCTL_DEF_DRV(I915_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2508 DRM_IOCTL_DEF_DRV(I915_FLUSH, drm_noop, DRM_AUTH),
2509 DRM_IOCTL_DEF_DRV(I915_FLIP, drm_noop, DRM_AUTH),
2510 DRM_IOCTL_DEF_DRV(I915_BATCHBUFFER, drm_noop, DRM_AUTH),
2511 DRM_IOCTL_DEF_DRV(I915_IRQ_EMIT, drm_noop, DRM_AUTH),
2512 DRM_IOCTL_DEF_DRV(I915_IRQ_WAIT, drm_noop, DRM_AUTH),
2513 DRM_IOCTL_DEF_DRV(I915_GETPARAM, i915_getparam, DRM_AUTH|DRM_RENDER_ALLOW),
2514 DRM_IOCTL_DEF_DRV(I915_SETPARAM, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2515 DRM_IOCTL_DEF_DRV(I915_ALLOC, drm_noop, DRM_AUTH),
2516 DRM_IOCTL_DEF_DRV(I915_FREE, drm_noop, DRM_AUTH),
2517 DRM_IOCTL_DEF_DRV(I915_INIT_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2518 DRM_IOCTL_DEF_DRV(I915_CMDBUFFER, drm_noop, DRM_AUTH),
2519 DRM_IOCTL_DEF_DRV(I915_DESTROY_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2520 DRM_IOCTL_DEF_DRV(I915_SET_VBLANK_PIPE, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2521 DRM_IOCTL_DEF_DRV(I915_GET_VBLANK_PIPE, drm_noop, DRM_AUTH),
2522 DRM_IOCTL_DEF_DRV(I915_VBLANK_SWAP, drm_noop, DRM_AUTH),
2523 DRM_IOCTL_DEF_DRV(I915_HWS_ADDR, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2524 DRM_IOCTL_DEF_DRV(I915_GEM_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2525 DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER, i915_gem_execbuffer, DRM_AUTH),
2526 DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER2, i915_gem_execbuffer2, DRM_AUTH|DRM_RENDER_ALLOW),
2527 DRM_IOCTL_DEF_DRV(I915_GEM_PIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY),
2528 DRM_IOCTL_DEF_DRV(I915_GEM_UNPIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY),
2529 DRM_IOCTL_DEF_DRV(I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2530 DRM_IOCTL_DEF_DRV(I915_GEM_SET_CACHING, i915_gem_set_caching_ioctl, DRM_RENDER_ALLOW),
2531 DRM_IOCTL_DEF_DRV(I915_GEM_GET_CACHING, i915_gem_get_caching_ioctl, DRM_RENDER_ALLOW),
2532 DRM_IOCTL_DEF_DRV(I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2533 DRM_IOCTL_DEF_DRV(I915_GEM_ENTERVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2534 DRM_IOCTL_DEF_DRV(I915_GEM_LEAVEVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2535 DRM_IOCTL_DEF_DRV(I915_GEM_CREATE, i915_gem_create_ioctl, DRM_RENDER_ALLOW),
2536 DRM_IOCTL_DEF_DRV(I915_GEM_PREAD, i915_gem_pread_ioctl, DRM_RENDER_ALLOW),
2537 DRM_IOCTL_DEF_DRV(I915_GEM_PWRITE, i915_gem_pwrite_ioctl, DRM_RENDER_ALLOW),
2538 DRM_IOCTL_DEF_DRV(I915_GEM_MMAP, i915_gem_mmap_ioctl, DRM_RENDER_ALLOW),
2539 DRM_IOCTL_DEF_DRV(I915_GEM_MMAP_GTT, i915_gem_mmap_gtt_ioctl, DRM_RENDER_ALLOW),
2540 DRM_IOCTL_DEF_DRV(I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, DRM_RENDER_ALLOW),
2541 DRM_IOCTL_DEF_DRV(I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, DRM_RENDER_ALLOW),
2542 DRM_IOCTL_DEF_DRV(I915_GEM_SET_TILING, i915_gem_set_tiling, DRM_RENDER_ALLOW),
2543 DRM_IOCTL_DEF_DRV(I915_GEM_GET_TILING, i915_gem_get_tiling, DRM_RENDER_ALLOW),
2544 DRM_IOCTL_DEF_DRV(I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, DRM_RENDER_ALLOW),
2545 DRM_IOCTL_DEF_DRV(I915_GET_PIPE_FROM_CRTC_ID, intel_get_pipe_from_crtc_id, 0),
2546 DRM_IOCTL_DEF_DRV(I915_GEM_MADVISE, i915_gem_madvise_ioctl, DRM_RENDER_ALLOW),
2547 DRM_IOCTL_DEF_DRV(I915_OVERLAY_PUT_IMAGE, intel_overlay_put_image_ioctl, DRM_MASTER|DRM_CONTROL_ALLOW),
2548 DRM_IOCTL_DEF_DRV(I915_OVERLAY_ATTRS, intel_overlay_attrs_ioctl, DRM_MASTER|DRM_CONTROL_ALLOW),
2549 DRM_IOCTL_DEF_DRV(I915_SET_SPRITE_COLORKEY, intel_sprite_set_colorkey, DRM_MASTER|DRM_CONTROL_ALLOW),
2550 DRM_IOCTL_DEF_DRV(I915_GET_SPRITE_COLORKEY, drm_noop, DRM_MASTER|DRM_CONTROL_ALLOW),
2551 DRM_IOCTL_DEF_DRV(I915_GEM_WAIT, i915_gem_wait_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2552 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_CREATE, i915_gem_context_create_ioctl, DRM_RENDER_ALLOW),
2553 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_DESTROY, i915_gem_context_destroy_ioctl, DRM_RENDER_ALLOW),
2554 DRM_IOCTL_DEF_DRV(I915_REG_READ, i915_reg_read_ioctl, DRM_RENDER_ALLOW),
2555 DRM_IOCTL_DEF_DRV(I915_GET_RESET_STATS, i915_gem_context_reset_stats_ioctl, DRM_RENDER_ALLOW),
2556 DRM_IOCTL_DEF_DRV(I915_GEM_USERPTR, i915_gem_userptr_ioctl, DRM_RENDER_ALLOW),
2557 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_GETPARAM, i915_gem_context_getparam_ioctl, DRM_RENDER_ALLOW),
2558 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_SETPARAM, i915_gem_context_setparam_ioctl, DRM_RENDER_ALLOW),
2559};
2560
1da177e4 2561static struct drm_driver driver = {
0c54781b
MW		 2562 /* Don't use MTRRs here; the Xserver or userspace app should
2563 * deal with them for Intel hardware.
792d2b9a 2564 */
673a394b 2565 .driver_features =
10ba5012 2566 DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM | DRIVER_PRIME |
1751fcf9 2567 DRIVER_RENDER | DRIVER_MODESET,
673a394b 2568 .open = i915_driver_open,
22eae947
DA		 2569 .lastclose = i915_driver_lastclose,
2570 .preclose = i915_driver_preclose,
673a394b 2571 .postclose = i915_driver_postclose,
915b4d11 2572 .set_busid = drm_pci_set_busid,
d8e29209 2573
b1f788c6 2574 .gem_close_object = i915_gem_close_object,
673a394b 2575 .gem_free_object = i915_gem_free_object,
de151cf6 2576 .gem_vm_ops = &i915_gem_vm_ops,
1286ff73
DV		 2577
2578 .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
2579 .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
2580 .gem_prime_export = i915_gem_prime_export,
2581 .gem_prime_import = i915_gem_prime_import,
2582
ff72145b 2583 .dumb_create = i915_gem_dumb_create,
da6b51d0 2584 .dumb_map_offset = i915_gem_mmap_gtt,
43387b37 2585 .dumb_destroy = drm_gem_dumb_destroy,
1da177e4 2586 .ioctls = i915_ioctls,
0673ad47 2587 .num_ioctls = ARRAY_SIZE(i915_ioctls),
e08e96de 2588 .fops = &i915_driver_fops,
22eae947
DA		 2589 .name = DRIVER_NAME,
2590 .desc = DRIVER_DESC,
2591 .date = DRIVER_DATE,
2592 .major = DRIVER_MAJOR,
2593 .minor = DRIVER_MINOR,
2594 .patchlevel = DRIVER_PATCHLEVEL,
1da177e4 2595};
ubuntu-bionic-kernel mirror