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1da177e4 LT |
1 | /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*- |
2 | */ | |
0d6aa60b | 3 | /* |
bc54fd1a | 4 | * |
1da177e4 LT |
5 | * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. |
6 | * All Rights Reserved. | |
bc54fd1a DA |
7 | * |
8 | * Permission is hereby granted, free of charge, to any person obtaining a | |
9 | * copy of this software and associated documentation files (the | |
10 | * "Software"), to deal in the Software without restriction, including | |
11 | * without limitation the rights to use, copy, modify, merge, publish, | |
12 | * distribute, sub license, and/or sell copies of the Software, and to | |
13 | * permit persons to whom the Software is furnished to do so, subject to | |
14 | * the following conditions: | |
15 | * | |
16 | * The above copyright notice and this permission notice (including the | |
17 | * next paragraph) shall be included in all copies or substantial portions | |
18 | * of the Software. | |
19 | * | |
20 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS | |
21 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
22 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. | |
23 | * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR | |
24 | * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, | |
25 | * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE | |
26 | * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. | |
27 | * | |
0d6aa60b | 28 | */ |
1da177e4 | 29 | |
e5747e3a | 30 | #include <linux/acpi.h> |
0673ad47 CW |
31 | #include <linux/device.h> |
32 | #include <linux/oom.h> | |
e0cd3608 | 33 | #include <linux/module.h> |
0673ad47 CW |
34 | #include <linux/pci.h> |
35 | #include <linux/pm.h> | |
d6102977 | 36 | #include <linux/pm_runtime.h> |
0673ad47 CW |
37 | #include <linux/pnp.h> |
38 | #include <linux/slab.h> | |
39 | #include <linux/vgaarb.h> | |
704ab614 | 40 | #include <linux/vga_switcheroo.h> |
0673ad47 CW |
41 | #include <linux/vt.h> |
42 | #include <acpi/video.h> | |
43 | ||
44 | #include <drm/drmP.h> | |
760285e7 | 45 | #include <drm/drm_crtc_helper.h> |
0673ad47 CW |
46 | #include <drm/i915_drm.h> |
47 | ||
48 | #include "i915_drv.h" | |
49 | #include "i915_trace.h" | |
50 | #include "i915_vgpu.h" | |
51 | #include "intel_drv.h" | |
79e53945 | 52 | |
112b715e KH |
53 | static struct drm_driver driver; |
54 | ||
0673ad47 CW |
55 | static unsigned int i915_load_fail_count; |
56 | ||
57 | bool __i915_inject_load_failure(const char *func, int line) | |
58 | { | |
59 | if (i915_load_fail_count >= i915.inject_load_failure) | |
60 | return false; | |
61 | ||
62 | if (++i915_load_fail_count == i915.inject_load_failure) { | |
63 | DRM_INFO("Injecting failure at checkpoint %u [%s:%d]\n", | |
64 | i915.inject_load_failure, func, line); | |
65 | return true; | |
66 | } | |
67 | ||
68 | return false; | |
69 | } | |
70 | ||
71 | #define FDO_BUG_URL "https://bugs.freedesktop.org/enter_bug.cgi?product=DRI" | |
72 | #define FDO_BUG_MSG "Please file a bug at " FDO_BUG_URL " against DRM/Intel " \ | |
73 | "providing the dmesg log by booting with drm.debug=0xf" | |
74 | ||
75 | void | |
76 | __i915_printk(struct drm_i915_private *dev_priv, const char *level, | |
77 | const char *fmt, ...) | |
78 | { | |
79 | static bool shown_bug_once; | |
c49d13ee | 80 | struct device *kdev = dev_priv->drm.dev; |
0673ad47 CW |
81 | bool is_error = level[1] <= KERN_ERR[1]; |
82 | bool is_debug = level[1] == KERN_DEBUG[1]; | |
83 | struct va_format vaf; | |
84 | va_list args; | |
85 | ||
86 | if (is_debug && !(drm_debug & DRM_UT_DRIVER)) | |
87 | return; | |
88 | ||
89 | va_start(args, fmt); | |
90 | ||
91 | vaf.fmt = fmt; | |
92 | vaf.va = &args; | |
93 | ||
c49d13ee | 94 | dev_printk(level, kdev, "[" DRM_NAME ":%ps] %pV", |
0673ad47 CW |
95 | __builtin_return_address(0), &vaf); |
96 | ||
97 | if (is_error && !shown_bug_once) { | |
c49d13ee | 98 | dev_notice(kdev, "%s", FDO_BUG_MSG); |
0673ad47 CW |
99 | shown_bug_once = true; |
100 | } | |
101 | ||
102 | va_end(args); | |
103 | } | |
104 | ||
105 | static bool i915_error_injected(struct drm_i915_private *dev_priv) | |
106 | { | |
107 | return i915.inject_load_failure && | |
108 | i915_load_fail_count == i915.inject_load_failure; | |
109 | } | |
110 | ||
111 | #define i915_load_error(dev_priv, fmt, ...) \ | |
112 | __i915_printk(dev_priv, \ | |
113 | i915_error_injected(dev_priv) ? KERN_DEBUG : KERN_ERR, \ | |
114 | fmt, ##__VA_ARGS__) | |
115 | ||
116 | ||
fd6b8f43 | 117 | static enum intel_pch intel_virt_detect_pch(struct drm_i915_private *dev_priv) |
0673ad47 CW |
118 | { |
119 | enum intel_pch ret = PCH_NOP; | |
120 | ||
121 | /* | |
122 | * In a virtualized passthrough environment we can be in a | |
123 | * setup where the ISA bridge is not able to be passed through. | |
124 | * In this case, a south bridge can be emulated and we have to | |
125 | * make an educated guess as to which PCH is really there. | |
126 | */ | |
127 | ||
fd6b8f43 | 128 | if (IS_GEN5(dev_priv)) { |
0673ad47 CW |
129 | ret = PCH_IBX; |
130 | DRM_DEBUG_KMS("Assuming Ibex Peak PCH\n"); | |
fd6b8f43 | 131 | } else if (IS_GEN6(dev_priv) || IS_IVYBRIDGE(dev_priv)) { |
0673ad47 CW |
132 | ret = PCH_CPT; |
133 | DRM_DEBUG_KMS("Assuming CouarPoint PCH\n"); | |
fd6b8f43 | 134 | } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) { |
0673ad47 CW |
135 | ret = PCH_LPT; |
136 | DRM_DEBUG_KMS("Assuming LynxPoint PCH\n"); | |
fd6b8f43 | 137 | } else if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) { |
0673ad47 CW |
138 | ret = PCH_SPT; |
139 | DRM_DEBUG_KMS("Assuming SunrisePoint PCH\n"); | |
140 | } | |
141 | ||
142 | return ret; | |
143 | } | |
144 | ||
145 | static void intel_detect_pch(struct drm_device *dev) | |
146 | { | |
fac5e23e | 147 | struct drm_i915_private *dev_priv = to_i915(dev); |
0673ad47 CW |
148 | struct pci_dev *pch = NULL; |
149 | ||
150 | /* In all current cases, num_pipes is equivalent to the PCH_NOP setting | |
151 | * (which really amounts to a PCH but no South Display). | |
152 | */ | |
b7f05d4a | 153 | if (INTEL_INFO(dev_priv)->num_pipes == 0) { |
0673ad47 CW |
154 | dev_priv->pch_type = PCH_NOP; |
155 | return; | |
156 | } | |
157 | ||
158 | /* | |
159 | * The reason to probe ISA bridge instead of Dev31:Fun0 is to | |
160 | * make graphics device passthrough work easy for VMM, that only | |
161 | * need to expose ISA bridge to let driver know the real hardware | |
162 | * underneath. This is a requirement from virtualization team. | |
163 | * | |
164 | * In some virtualized environments (e.g. XEN), there is irrelevant | |
165 | * ISA bridge in the system. To work reliably, we should scan trhough | |
166 | * all the ISA bridge devices and check for the first match, instead | |
167 | * of only checking the first one. | |
168 | */ | |
169 | while ((pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, pch))) { | |
170 | if (pch->vendor == PCI_VENDOR_ID_INTEL) { | |
171 | unsigned short id = pch->device & INTEL_PCH_DEVICE_ID_MASK; | |
172 | dev_priv->pch_id = id; | |
173 | ||
174 | if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) { | |
175 | dev_priv->pch_type = PCH_IBX; | |
176 | DRM_DEBUG_KMS("Found Ibex Peak PCH\n"); | |
5db94019 | 177 | WARN_ON(!IS_GEN5(dev_priv)); |
0673ad47 CW |
178 | } else if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) { |
179 | dev_priv->pch_type = PCH_CPT; | |
180 | DRM_DEBUG_KMS("Found CougarPoint PCH\n"); | |
fd6b8f43 TU |
181 | WARN_ON(!(IS_GEN6(dev_priv) || |
182 | IS_IVYBRIDGE(dev_priv))); | |
0673ad47 CW |
183 | } else if (id == INTEL_PCH_PPT_DEVICE_ID_TYPE) { |
184 | /* PantherPoint is CPT compatible */ | |
185 | dev_priv->pch_type = PCH_CPT; | |
186 | DRM_DEBUG_KMS("Found PantherPoint PCH\n"); | |
fd6b8f43 TU |
187 | WARN_ON(!(IS_GEN6(dev_priv) || |
188 | IS_IVYBRIDGE(dev_priv))); | |
0673ad47 CW |
189 | } else if (id == INTEL_PCH_LPT_DEVICE_ID_TYPE) { |
190 | dev_priv->pch_type = PCH_LPT; | |
191 | DRM_DEBUG_KMS("Found LynxPoint PCH\n"); | |
8652744b TU |
192 | WARN_ON(!IS_HASWELL(dev_priv) && |
193 | !IS_BROADWELL(dev_priv)); | |
50a0bc90 TU |
194 | WARN_ON(IS_HSW_ULT(dev_priv) || |
195 | IS_BDW_ULT(dev_priv)); | |
0673ad47 CW |
196 | } else if (id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) { |
197 | dev_priv->pch_type = PCH_LPT; | |
198 | DRM_DEBUG_KMS("Found LynxPoint LP PCH\n"); | |
8652744b TU |
199 | WARN_ON(!IS_HASWELL(dev_priv) && |
200 | !IS_BROADWELL(dev_priv)); | |
50a0bc90 TU |
201 | WARN_ON(!IS_HSW_ULT(dev_priv) && |
202 | !IS_BDW_ULT(dev_priv)); | |
0673ad47 CW |
203 | } else if (id == INTEL_PCH_SPT_DEVICE_ID_TYPE) { |
204 | dev_priv->pch_type = PCH_SPT; | |
205 | DRM_DEBUG_KMS("Found SunrisePoint PCH\n"); | |
0853723b TU |
206 | WARN_ON(!IS_SKYLAKE(dev_priv) && |
207 | !IS_KABYLAKE(dev_priv)); | |
0673ad47 CW |
208 | } else if (id == INTEL_PCH_SPT_LP_DEVICE_ID_TYPE) { |
209 | dev_priv->pch_type = PCH_SPT; | |
210 | DRM_DEBUG_KMS("Found SunrisePoint LP PCH\n"); | |
0853723b TU |
211 | WARN_ON(!IS_SKYLAKE(dev_priv) && |
212 | !IS_KABYLAKE(dev_priv)); | |
22dea0be RV |
213 | } else if (id == INTEL_PCH_KBP_DEVICE_ID_TYPE) { |
214 | dev_priv->pch_type = PCH_KBP; | |
215 | DRM_DEBUG_KMS("Found KabyPoint PCH\n"); | |
0853723b | 216 | WARN_ON(!IS_KABYLAKE(dev_priv)); |
0673ad47 CW |
217 | } else if ((id == INTEL_PCH_P2X_DEVICE_ID_TYPE) || |
218 | (id == INTEL_PCH_P3X_DEVICE_ID_TYPE) || | |
219 | ((id == INTEL_PCH_QEMU_DEVICE_ID_TYPE) && | |
220 | pch->subsystem_vendor == | |
221 | PCI_SUBVENDOR_ID_REDHAT_QUMRANET && | |
222 | pch->subsystem_device == | |
223 | PCI_SUBDEVICE_ID_QEMU)) { | |
fd6b8f43 TU |
224 | dev_priv->pch_type = |
225 | intel_virt_detect_pch(dev_priv); | |
0673ad47 CW |
226 | } else |
227 | continue; | |
228 | ||
229 | break; | |
230 | } | |
231 | } | |
232 | if (!pch) | |
233 | DRM_DEBUG_KMS("No PCH found.\n"); | |
234 | ||
235 | pci_dev_put(pch); | |
236 | } | |
237 | ||
0673ad47 CW |
238 | static int i915_getparam(struct drm_device *dev, void *data, |
239 | struct drm_file *file_priv) | |
240 | { | |
fac5e23e | 241 | struct drm_i915_private *dev_priv = to_i915(dev); |
52a05c30 | 242 | struct pci_dev *pdev = dev_priv->drm.pdev; |
0673ad47 CW |
243 | drm_i915_getparam_t *param = data; |
244 | int value; | |
245 | ||
246 | switch (param->param) { | |
247 | case I915_PARAM_IRQ_ACTIVE: | |
248 | case I915_PARAM_ALLOW_BATCHBUFFER: | |
249 | case I915_PARAM_LAST_DISPATCH: | |
250 | /* Reject all old ums/dri params. */ | |
251 | return -ENODEV; | |
252 | case I915_PARAM_CHIPSET_ID: | |
52a05c30 | 253 | value = pdev->device; |
0673ad47 CW |
254 | break; |
255 | case I915_PARAM_REVISION: | |
52a05c30 | 256 | value = pdev->revision; |
0673ad47 | 257 | break; |
0673ad47 CW |
258 | case I915_PARAM_NUM_FENCES_AVAIL: |
259 | value = dev_priv->num_fence_regs; | |
260 | break; | |
261 | case I915_PARAM_HAS_OVERLAY: | |
262 | value = dev_priv->overlay ? 1 : 0; | |
263 | break; | |
0673ad47 | 264 | case I915_PARAM_HAS_BSD: |
3b3f1650 | 265 | value = !!dev_priv->engine[VCS]; |
0673ad47 CW |
266 | break; |
267 | case I915_PARAM_HAS_BLT: | |
3b3f1650 | 268 | value = !!dev_priv->engine[BCS]; |
0673ad47 CW |
269 | break; |
270 | case I915_PARAM_HAS_VEBOX: | |
3b3f1650 | 271 | value = !!dev_priv->engine[VECS]; |
0673ad47 CW |
272 | break; |
273 | case I915_PARAM_HAS_BSD2: | |
3b3f1650 | 274 | value = !!dev_priv->engine[VCS2]; |
0673ad47 | 275 | break; |
0673ad47 | 276 | case I915_PARAM_HAS_EXEC_CONSTANTS: |
16162470 | 277 | value = INTEL_GEN(dev_priv) >= 4; |
0673ad47 CW |
278 | break; |
279 | case I915_PARAM_HAS_LLC: | |
16162470 | 280 | value = HAS_LLC(dev_priv); |
0673ad47 CW |
281 | break; |
282 | case I915_PARAM_HAS_WT: | |
16162470 | 283 | value = HAS_WT(dev_priv); |
0673ad47 CW |
284 | break; |
285 | case I915_PARAM_HAS_ALIASING_PPGTT: | |
16162470 | 286 | value = USES_PPGTT(dev_priv); |
0673ad47 CW |
287 | break; |
288 | case I915_PARAM_HAS_SEMAPHORES: | |
39df9190 | 289 | value = i915.semaphores; |
0673ad47 | 290 | break; |
0673ad47 CW |
291 | case I915_PARAM_HAS_SECURE_BATCHES: |
292 | value = capable(CAP_SYS_ADMIN); | |
293 | break; | |
0673ad47 CW |
294 | case I915_PARAM_CMD_PARSER_VERSION: |
295 | value = i915_cmd_parser_get_version(dev_priv); | |
296 | break; | |
0673ad47 | 297 | case I915_PARAM_SUBSLICE_TOTAL: |
57ec171e | 298 | value = sseu_subslice_total(&INTEL_INFO(dev_priv)->sseu); |
0673ad47 CW |
299 | if (!value) |
300 | return -ENODEV; | |
301 | break; | |
302 | case I915_PARAM_EU_TOTAL: | |
43b67998 | 303 | value = INTEL_INFO(dev_priv)->sseu.eu_total; |
0673ad47 CW |
304 | if (!value) |
305 | return -ENODEV; | |
306 | break; | |
307 | case I915_PARAM_HAS_GPU_RESET: | |
308 | value = i915.enable_hangcheck && intel_has_gpu_reset(dev_priv); | |
309 | break; | |
310 | case I915_PARAM_HAS_RESOURCE_STREAMER: | |
16162470 | 311 | value = HAS_RESOURCE_STREAMER(dev_priv); |
0673ad47 | 312 | break; |
37f501af | 313 | case I915_PARAM_HAS_POOLED_EU: |
16162470 | 314 | value = HAS_POOLED_EU(dev_priv); |
37f501af | 315 | break; |
316 | case I915_PARAM_MIN_EU_IN_POOL: | |
43b67998 | 317 | value = INTEL_INFO(dev_priv)->sseu.min_eu_in_pool; |
37f501af | 318 | break; |
4cc69075 CW |
319 | case I915_PARAM_MMAP_GTT_VERSION: |
320 | /* Though we've started our numbering from 1, and so class all | |
321 | * earlier versions as 0, in effect their value is undefined as | |
322 | * the ioctl will report EINVAL for the unknown param! | |
323 | */ | |
324 | value = i915_gem_mmap_gtt_version(); | |
325 | break; | |
0de9136d CW |
326 | case I915_PARAM_HAS_SCHEDULER: |
327 | value = dev_priv->engine[RCS] && | |
328 | dev_priv->engine[RCS]->schedule; | |
329 | break; | |
16162470 DW |
330 | case I915_PARAM_MMAP_VERSION: |
331 | /* Remember to bump this if the version changes! */ | |
332 | case I915_PARAM_HAS_GEM: | |
333 | case I915_PARAM_HAS_PAGEFLIPPING: | |
334 | case I915_PARAM_HAS_EXECBUF2: /* depends on GEM */ | |
335 | case I915_PARAM_HAS_RELAXED_FENCING: | |
336 | case I915_PARAM_HAS_COHERENT_RINGS: | |
337 | case I915_PARAM_HAS_RELAXED_DELTA: | |
338 | case I915_PARAM_HAS_GEN7_SOL_RESET: | |
339 | case I915_PARAM_HAS_WAIT_TIMEOUT: | |
340 | case I915_PARAM_HAS_PRIME_VMAP_FLUSH: | |
341 | case I915_PARAM_HAS_PINNED_BATCHES: | |
342 | case I915_PARAM_HAS_EXEC_NO_RELOC: | |
343 | case I915_PARAM_HAS_EXEC_HANDLE_LUT: | |
344 | case I915_PARAM_HAS_COHERENT_PHYS_GTT: | |
345 | case I915_PARAM_HAS_EXEC_SOFTPIN: | |
346 | /* For the time being all of these are always true; | |
347 | * if some supported hardware does not have one of these | |
348 | * features this value needs to be provided from | |
349 | * INTEL_INFO(), a feature macro, or similar. | |
350 | */ | |
351 | value = 1; | |
352 | break; | |
0673ad47 CW |
353 | default: |
354 | DRM_DEBUG("Unknown parameter %d\n", param->param); | |
355 | return -EINVAL; | |
356 | } | |
357 | ||
dda33009 | 358 | if (put_user(value, param->value)) |
0673ad47 | 359 | return -EFAULT; |
0673ad47 CW |
360 | |
361 | return 0; | |
362 | } | |
363 | ||
364 | static int i915_get_bridge_dev(struct drm_device *dev) | |
365 | { | |
fac5e23e | 366 | struct drm_i915_private *dev_priv = to_i915(dev); |
0673ad47 CW |
367 | |
368 | dev_priv->bridge_dev = pci_get_bus_and_slot(0, PCI_DEVFN(0, 0)); | |
369 | if (!dev_priv->bridge_dev) { | |
370 | DRM_ERROR("bridge device not found\n"); | |
371 | return -1; | |
372 | } | |
373 | return 0; | |
374 | } | |
375 | ||
376 | /* Allocate space for the MCH regs if needed, return nonzero on error */ | |
377 | static int | |
378 | intel_alloc_mchbar_resource(struct drm_device *dev) | |
379 | { | |
fac5e23e | 380 | struct drm_i915_private *dev_priv = to_i915(dev); |
514e1d64 | 381 | int reg = INTEL_GEN(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915; |
0673ad47 CW |
382 | u32 temp_lo, temp_hi = 0; |
383 | u64 mchbar_addr; | |
384 | int ret; | |
385 | ||
514e1d64 | 386 | if (INTEL_GEN(dev_priv) >= 4) |
0673ad47 CW |
387 | pci_read_config_dword(dev_priv->bridge_dev, reg + 4, &temp_hi); |
388 | pci_read_config_dword(dev_priv->bridge_dev, reg, &temp_lo); | |
389 | mchbar_addr = ((u64)temp_hi << 32) | temp_lo; | |
390 | ||
391 | /* If ACPI doesn't have it, assume we need to allocate it ourselves */ | |
392 | #ifdef CONFIG_PNP | |
393 | if (mchbar_addr && | |
394 | pnp_range_reserved(mchbar_addr, mchbar_addr + MCHBAR_SIZE)) | |
395 | return 0; | |
396 | #endif | |
397 | ||
398 | /* Get some space for it */ | |
399 | dev_priv->mch_res.name = "i915 MCHBAR"; | |
400 | dev_priv->mch_res.flags = IORESOURCE_MEM; | |
401 | ret = pci_bus_alloc_resource(dev_priv->bridge_dev->bus, | |
402 | &dev_priv->mch_res, | |
403 | MCHBAR_SIZE, MCHBAR_SIZE, | |
404 | PCIBIOS_MIN_MEM, | |
405 | 0, pcibios_align_resource, | |
406 | dev_priv->bridge_dev); | |
407 | if (ret) { | |
408 | DRM_DEBUG_DRIVER("failed bus alloc: %d\n", ret); | |
409 | dev_priv->mch_res.start = 0; | |
410 | return ret; | |
411 | } | |
412 | ||
514e1d64 | 413 | if (INTEL_GEN(dev_priv) >= 4) |
0673ad47 CW |
414 | pci_write_config_dword(dev_priv->bridge_dev, reg + 4, |
415 | upper_32_bits(dev_priv->mch_res.start)); | |
416 | ||
417 | pci_write_config_dword(dev_priv->bridge_dev, reg, | |
418 | lower_32_bits(dev_priv->mch_res.start)); | |
419 | return 0; | |
420 | } | |
421 | ||
422 | /* Setup MCHBAR if possible, return true if we should disable it again */ | |
423 | static void | |
424 | intel_setup_mchbar(struct drm_device *dev) | |
425 | { | |
fac5e23e | 426 | struct drm_i915_private *dev_priv = to_i915(dev); |
514e1d64 | 427 | int mchbar_reg = INTEL_GEN(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915; |
0673ad47 CW |
428 | u32 temp; |
429 | bool enabled; | |
430 | ||
920a14b2 | 431 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) |
0673ad47 CW |
432 | return; |
433 | ||
434 | dev_priv->mchbar_need_disable = false; | |
435 | ||
50a0bc90 | 436 | if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) { |
0673ad47 CW |
437 | pci_read_config_dword(dev_priv->bridge_dev, DEVEN, &temp); |
438 | enabled = !!(temp & DEVEN_MCHBAR_EN); | |
439 | } else { | |
440 | pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp); | |
441 | enabled = temp & 1; | |
442 | } | |
443 | ||
444 | /* If it's already enabled, don't have to do anything */ | |
445 | if (enabled) | |
446 | return; | |
447 | ||
448 | if (intel_alloc_mchbar_resource(dev)) | |
449 | return; | |
450 | ||
451 | dev_priv->mchbar_need_disable = true; | |
452 | ||
453 | /* Space is allocated or reserved, so enable it. */ | |
50a0bc90 | 454 | if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) { |
0673ad47 CW |
455 | pci_write_config_dword(dev_priv->bridge_dev, DEVEN, |
456 | temp | DEVEN_MCHBAR_EN); | |
457 | } else { | |
458 | pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp); | |
459 | pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp | 1); | |
460 | } | |
461 | } | |
462 | ||
463 | static void | |
464 | intel_teardown_mchbar(struct drm_device *dev) | |
465 | { | |
fac5e23e | 466 | struct drm_i915_private *dev_priv = to_i915(dev); |
514e1d64 | 467 | int mchbar_reg = INTEL_GEN(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915; |
0673ad47 CW |
468 | |
469 | if (dev_priv->mchbar_need_disable) { | |
50a0bc90 | 470 | if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) { |
0673ad47 CW |
471 | u32 deven_val; |
472 | ||
473 | pci_read_config_dword(dev_priv->bridge_dev, DEVEN, | |
474 | &deven_val); | |
475 | deven_val &= ~DEVEN_MCHBAR_EN; | |
476 | pci_write_config_dword(dev_priv->bridge_dev, DEVEN, | |
477 | deven_val); | |
478 | } else { | |
479 | u32 mchbar_val; | |
480 | ||
481 | pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, | |
482 | &mchbar_val); | |
483 | mchbar_val &= ~1; | |
484 | pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, | |
485 | mchbar_val); | |
486 | } | |
487 | } | |
488 | ||
489 | if (dev_priv->mch_res.start) | |
490 | release_resource(&dev_priv->mch_res); | |
491 | } | |
492 | ||
493 | /* true = enable decode, false = disable decoder */ | |
494 | static unsigned int i915_vga_set_decode(void *cookie, bool state) | |
495 | { | |
496 | struct drm_device *dev = cookie; | |
497 | ||
498 | intel_modeset_vga_set_state(dev, state); | |
499 | if (state) | |
500 | return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM | | |
501 | VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM; | |
502 | else | |
503 | return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM; | |
504 | } | |
505 | ||
506 | static void i915_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state) | |
507 | { | |
508 | struct drm_device *dev = pci_get_drvdata(pdev); | |
509 | pm_message_t pmm = { .event = PM_EVENT_SUSPEND }; | |
510 | ||
511 | if (state == VGA_SWITCHEROO_ON) { | |
512 | pr_info("switched on\n"); | |
513 | dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; | |
514 | /* i915 resume handler doesn't set to D0 */ | |
52a05c30 | 515 | pci_set_power_state(pdev, PCI_D0); |
0673ad47 CW |
516 | i915_resume_switcheroo(dev); |
517 | dev->switch_power_state = DRM_SWITCH_POWER_ON; | |
518 | } else { | |
519 | pr_info("switched off\n"); | |
520 | dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; | |
521 | i915_suspend_switcheroo(dev, pmm); | |
522 | dev->switch_power_state = DRM_SWITCH_POWER_OFF; | |
523 | } | |
524 | } | |
525 | ||
526 | static bool i915_switcheroo_can_switch(struct pci_dev *pdev) | |
527 | { | |
528 | struct drm_device *dev = pci_get_drvdata(pdev); | |
529 | ||
530 | /* | |
531 | * FIXME: open_count is protected by drm_global_mutex but that would lead to | |
532 | * locking inversion with the driver load path. And the access here is | |
533 | * completely racy anyway. So don't bother with locking for now. | |
534 | */ | |
535 | return dev->open_count == 0; | |
536 | } | |
537 | ||
538 | static const struct vga_switcheroo_client_ops i915_switcheroo_ops = { | |
539 | .set_gpu_state = i915_switcheroo_set_state, | |
540 | .reprobe = NULL, | |
541 | .can_switch = i915_switcheroo_can_switch, | |
542 | }; | |
543 | ||
fbbd37b3 | 544 | static void i915_gem_fini(struct drm_i915_private *dev_priv) |
0673ad47 | 545 | { |
fbbd37b3 CW |
546 | mutex_lock(&dev_priv->drm.struct_mutex); |
547 | i915_gem_cleanup_engines(&dev_priv->drm); | |
548 | i915_gem_context_fini(&dev_priv->drm); | |
549 | mutex_unlock(&dev_priv->drm.struct_mutex); | |
0673ad47 | 550 | |
7d5d59e5 | 551 | rcu_barrier(); |
fbbd37b3 CW |
552 | flush_work(&dev_priv->mm.free_work); |
553 | ||
554 | WARN_ON(!list_empty(&dev_priv->context_list)); | |
0673ad47 CW |
555 | } |
556 | ||
557 | static int i915_load_modeset_init(struct drm_device *dev) | |
558 | { | |
fac5e23e | 559 | struct drm_i915_private *dev_priv = to_i915(dev); |
52a05c30 | 560 | struct pci_dev *pdev = dev_priv->drm.pdev; |
0673ad47 CW |
561 | int ret; |
562 | ||
563 | if (i915_inject_load_failure()) | |
564 | return -ENODEV; | |
565 | ||
566 | ret = intel_bios_init(dev_priv); | |
567 | if (ret) | |
568 | DRM_INFO("failed to find VBIOS tables\n"); | |
569 | ||
570 | /* If we have > 1 VGA cards, then we need to arbitrate access | |
571 | * to the common VGA resources. | |
572 | * | |
573 | * If we are a secondary display controller (!PCI_DISPLAY_CLASS_VGA), | |
574 | * then we do not take part in VGA arbitration and the | |
575 | * vga_client_register() fails with -ENODEV. | |
576 | */ | |
52a05c30 | 577 | ret = vga_client_register(pdev, dev, NULL, i915_vga_set_decode); |
0673ad47 CW |
578 | if (ret && ret != -ENODEV) |
579 | goto out; | |
580 | ||
581 | intel_register_dsm_handler(); | |
582 | ||
52a05c30 | 583 | ret = vga_switcheroo_register_client(pdev, &i915_switcheroo_ops, false); |
0673ad47 CW |
584 | if (ret) |
585 | goto cleanup_vga_client; | |
586 | ||
587 | /* must happen before intel_power_domains_init_hw() on VLV/CHV */ | |
588 | intel_update_rawclk(dev_priv); | |
589 | ||
590 | intel_power_domains_init_hw(dev_priv, false); | |
591 | ||
592 | intel_csr_ucode_init(dev_priv); | |
593 | ||
594 | ret = intel_irq_install(dev_priv); | |
595 | if (ret) | |
596 | goto cleanup_csr; | |
597 | ||
598 | intel_setup_gmbus(dev); | |
599 | ||
600 | /* Important: The output setup functions called by modeset_init need | |
601 | * working irqs for e.g. gmbus and dp aux transfers. */ | |
b079bd17 VS |
602 | ret = intel_modeset_init(dev); |
603 | if (ret) | |
604 | goto cleanup_irq; | |
0673ad47 CW |
605 | |
606 | intel_guc_init(dev); | |
607 | ||
608 | ret = i915_gem_init(dev); | |
609 | if (ret) | |
610 | goto cleanup_irq; | |
611 | ||
612 | intel_modeset_gem_init(dev); | |
613 | ||
b7f05d4a | 614 | if (INTEL_INFO(dev_priv)->num_pipes == 0) |
0673ad47 CW |
615 | return 0; |
616 | ||
617 | ret = intel_fbdev_init(dev); | |
618 | if (ret) | |
619 | goto cleanup_gem; | |
620 | ||
621 | /* Only enable hotplug handling once the fbdev is fully set up. */ | |
622 | intel_hpd_init(dev_priv); | |
623 | ||
624 | drm_kms_helper_poll_init(dev); | |
625 | ||
626 | return 0; | |
627 | ||
628 | cleanup_gem: | |
1c777c5d ID |
629 | if (i915_gem_suspend(dev)) |
630 | DRM_ERROR("failed to idle hardware; continuing to unload!\n"); | |
fbbd37b3 | 631 | i915_gem_fini(dev_priv); |
0673ad47 CW |
632 | cleanup_irq: |
633 | intel_guc_fini(dev); | |
634 | drm_irq_uninstall(dev); | |
635 | intel_teardown_gmbus(dev); | |
636 | cleanup_csr: | |
637 | intel_csr_ucode_fini(dev_priv); | |
638 | intel_power_domains_fini(dev_priv); | |
52a05c30 | 639 | vga_switcheroo_unregister_client(pdev); |
0673ad47 | 640 | cleanup_vga_client: |
52a05c30 | 641 | vga_client_register(pdev, NULL, NULL, NULL); |
0673ad47 CW |
642 | out: |
643 | return ret; | |
644 | } | |
645 | ||
646 | #if IS_ENABLED(CONFIG_FB) | |
647 | static int i915_kick_out_firmware_fb(struct drm_i915_private *dev_priv) | |
648 | { | |
649 | struct apertures_struct *ap; | |
91c8a326 | 650 | struct pci_dev *pdev = dev_priv->drm.pdev; |
0673ad47 CW |
651 | struct i915_ggtt *ggtt = &dev_priv->ggtt; |
652 | bool primary; | |
653 | int ret; | |
654 | ||
655 | ap = alloc_apertures(1); | |
656 | if (!ap) | |
657 | return -ENOMEM; | |
658 | ||
659 | ap->ranges[0].base = ggtt->mappable_base; | |
660 | ap->ranges[0].size = ggtt->mappable_end; | |
661 | ||
662 | primary = | |
663 | pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW; | |
664 | ||
44adece5 | 665 | ret = drm_fb_helper_remove_conflicting_framebuffers(ap, "inteldrmfb", primary); |
0673ad47 CW |
666 | |
667 | kfree(ap); | |
668 | ||
669 | return ret; | |
670 | } | |
671 | #else | |
672 | static int i915_kick_out_firmware_fb(struct drm_i915_private *dev_priv) | |
673 | { | |
674 | return 0; | |
675 | } | |
676 | #endif | |
677 | ||
678 | #if !defined(CONFIG_VGA_CONSOLE) | |
679 | static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv) | |
680 | { | |
681 | return 0; | |
682 | } | |
683 | #elif !defined(CONFIG_DUMMY_CONSOLE) | |
684 | static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv) | |
685 | { | |
686 | return -ENODEV; | |
687 | } | |
688 | #else | |
689 | static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv) | |
690 | { | |
691 | int ret = 0; | |
692 | ||
693 | DRM_INFO("Replacing VGA console driver\n"); | |
694 | ||
695 | console_lock(); | |
696 | if (con_is_bound(&vga_con)) | |
697 | ret = do_take_over_console(&dummy_con, 0, MAX_NR_CONSOLES - 1, 1); | |
698 | if (ret == 0) { | |
699 | ret = do_unregister_con_driver(&vga_con); | |
700 | ||
701 | /* Ignore "already unregistered". */ | |
702 | if (ret == -ENODEV) | |
703 | ret = 0; | |
704 | } | |
705 | console_unlock(); | |
706 | ||
707 | return ret; | |
708 | } | |
709 | #endif | |
710 | ||
0673ad47 CW |
711 | static void intel_init_dpio(struct drm_i915_private *dev_priv) |
712 | { | |
713 | /* | |
714 | * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C), | |
715 | * CHV x1 PHY (DP/HDMI D) | |
716 | * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C) | |
717 | */ | |
718 | if (IS_CHERRYVIEW(dev_priv)) { | |
719 | DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2; | |
720 | DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO; | |
721 | } else if (IS_VALLEYVIEW(dev_priv)) { | |
722 | DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO; | |
723 | } | |
724 | } | |
725 | ||
726 | static int i915_workqueues_init(struct drm_i915_private *dev_priv) | |
727 | { | |
728 | /* | |
729 | * The i915 workqueue is primarily used for batched retirement of | |
730 | * requests (and thus managing bo) once the task has been completed | |
731 | * by the GPU. i915_gem_retire_requests() is called directly when we | |
732 | * need high-priority retirement, such as waiting for an explicit | |
733 | * bo. | |
734 | * | |
735 | * It is also used for periodic low-priority events, such as | |
736 | * idle-timers and recording error state. | |
737 | * | |
738 | * All tasks on the workqueue are expected to acquire the dev mutex | |
739 | * so there is no point in running more than one instance of the | |
740 | * workqueue at any time. Use an ordered one. | |
741 | */ | |
742 | dev_priv->wq = alloc_ordered_workqueue("i915", 0); | |
743 | if (dev_priv->wq == NULL) | |
744 | goto out_err; | |
745 | ||
746 | dev_priv->hotplug.dp_wq = alloc_ordered_workqueue("i915-dp", 0); | |
747 | if (dev_priv->hotplug.dp_wq == NULL) | |
748 | goto out_free_wq; | |
749 | ||
0673ad47 CW |
750 | return 0; |
751 | ||
0673ad47 CW |
752 | out_free_wq: |
753 | destroy_workqueue(dev_priv->wq); | |
754 | out_err: | |
755 | DRM_ERROR("Failed to allocate workqueues.\n"); | |
756 | ||
757 | return -ENOMEM; | |
758 | } | |
759 | ||
760 | static void i915_workqueues_cleanup(struct drm_i915_private *dev_priv) | |
761 | { | |
0673ad47 CW |
762 | destroy_workqueue(dev_priv->hotplug.dp_wq); |
763 | destroy_workqueue(dev_priv->wq); | |
764 | } | |
765 | ||
4fc7e845 PZ |
766 | /* |
767 | * We don't keep the workarounds for pre-production hardware, so we expect our | |
768 | * driver to fail on these machines in one way or another. A little warning on | |
769 | * dmesg may help both the user and the bug triagers. | |
770 | */ | |
771 | static void intel_detect_preproduction_hw(struct drm_i915_private *dev_priv) | |
772 | { | |
773 | if (IS_HSW_EARLY_SDV(dev_priv) || | |
774 | IS_SKL_REVID(dev_priv, 0, SKL_REVID_F0)) | |
775 | DRM_ERROR("This is a pre-production stepping. " | |
776 | "It may not be fully functional.\n"); | |
777 | } | |
778 | ||
0673ad47 CW |
779 | /** |
780 | * i915_driver_init_early - setup state not requiring device access | |
781 | * @dev_priv: device private | |
782 | * | |
783 | * Initialize everything that is a "SW-only" state, that is state not | |
784 | * requiring accessing the device or exposing the driver via kernel internal | |
785 | * or userspace interfaces. Example steps belonging here: lock initialization, | |
786 | * system memory allocation, setting up device specific attributes and | |
787 | * function hooks not requiring accessing the device. | |
788 | */ | |
789 | static int i915_driver_init_early(struct drm_i915_private *dev_priv, | |
790 | const struct pci_device_id *ent) | |
791 | { | |
792 | const struct intel_device_info *match_info = | |
793 | (struct intel_device_info *)ent->driver_data; | |
794 | struct intel_device_info *device_info; | |
795 | int ret = 0; | |
796 | ||
797 | if (i915_inject_load_failure()) | |
798 | return -ENODEV; | |
799 | ||
800 | /* Setup the write-once "constant" device info */ | |
94b4f3ba | 801 | device_info = mkwrite_device_info(dev_priv); |
0673ad47 CW |
802 | memcpy(device_info, match_info, sizeof(*device_info)); |
803 | device_info->device_id = dev_priv->drm.pdev->device; | |
804 | ||
805 | BUG_ON(device_info->gen > sizeof(device_info->gen_mask) * BITS_PER_BYTE); | |
806 | device_info->gen_mask = BIT(device_info->gen - 1); | |
807 | ||
808 | spin_lock_init(&dev_priv->irq_lock); | |
809 | spin_lock_init(&dev_priv->gpu_error.lock); | |
810 | mutex_init(&dev_priv->backlight_lock); | |
811 | spin_lock_init(&dev_priv->uncore.lock); | |
812 | spin_lock_init(&dev_priv->mm.object_stat_lock); | |
813 | spin_lock_init(&dev_priv->mmio_flip_lock); | |
814 | mutex_init(&dev_priv->sb_lock); | |
815 | mutex_init(&dev_priv->modeset_restore_lock); | |
816 | mutex_init(&dev_priv->av_mutex); | |
817 | mutex_init(&dev_priv->wm.wm_mutex); | |
818 | mutex_init(&dev_priv->pps_mutex); | |
819 | ||
0b1de5d5 CW |
820 | i915_memcpy_init_early(dev_priv); |
821 | ||
0673ad47 CW |
822 | ret = i915_workqueues_init(dev_priv); |
823 | if (ret < 0) | |
824 | return ret; | |
825 | ||
826 | ret = intel_gvt_init(dev_priv); | |
827 | if (ret < 0) | |
828 | goto err_workqueues; | |
829 | ||
830 | /* This must be called before any calls to HAS_PCH_* */ | |
831 | intel_detect_pch(&dev_priv->drm); | |
832 | ||
833 | intel_pm_setup(&dev_priv->drm); | |
834 | intel_init_dpio(dev_priv); | |
835 | intel_power_domains_init(dev_priv); | |
836 | intel_irq_init(dev_priv); | |
3ac168a7 | 837 | intel_hangcheck_init(dev_priv); |
0673ad47 CW |
838 | intel_init_display_hooks(dev_priv); |
839 | intel_init_clock_gating_hooks(dev_priv); | |
840 | intel_init_audio_hooks(dev_priv); | |
73cb9701 CW |
841 | ret = i915_gem_load_init(&dev_priv->drm); |
842 | if (ret < 0) | |
843 | goto err_gvt; | |
0673ad47 | 844 | |
36cdd013 | 845 | intel_display_crc_init(dev_priv); |
0673ad47 | 846 | |
94b4f3ba | 847 | intel_device_info_dump(dev_priv); |
0673ad47 | 848 | |
4fc7e845 | 849 | intel_detect_preproduction_hw(dev_priv); |
0673ad47 CW |
850 | |
851 | return 0; | |
852 | ||
73cb9701 CW |
853 | err_gvt: |
854 | intel_gvt_cleanup(dev_priv); | |
0673ad47 CW |
855 | err_workqueues: |
856 | i915_workqueues_cleanup(dev_priv); | |
857 | return ret; | |
858 | } | |
859 | ||
860 | /** | |
861 | * i915_driver_cleanup_early - cleanup the setup done in i915_driver_init_early() | |
862 | * @dev_priv: device private | |
863 | */ | |
864 | static void i915_driver_cleanup_early(struct drm_i915_private *dev_priv) | |
865 | { | |
91c8a326 | 866 | i915_gem_load_cleanup(&dev_priv->drm); |
0673ad47 CW |
867 | i915_workqueues_cleanup(dev_priv); |
868 | } | |
869 | ||
870 | static int i915_mmio_setup(struct drm_device *dev) | |
871 | { | |
872 | struct drm_i915_private *dev_priv = to_i915(dev); | |
52a05c30 | 873 | struct pci_dev *pdev = dev_priv->drm.pdev; |
0673ad47 CW |
874 | int mmio_bar; |
875 | int mmio_size; | |
876 | ||
5db94019 | 877 | mmio_bar = IS_GEN2(dev_priv) ? 1 : 0; |
0673ad47 CW |
878 | /* |
879 | * Before gen4, the registers and the GTT are behind different BARs. | |
880 | * However, from gen4 onwards, the registers and the GTT are shared | |
881 | * in the same BAR, so we want to restrict this ioremap from | |
882 | * clobbering the GTT which we want ioremap_wc instead. Fortunately, | |
883 | * the register BAR remains the same size for all the earlier | |
884 | * generations up to Ironlake. | |
885 | */ | |
514e1d64 | 886 | if (INTEL_GEN(dev_priv) < 5) |
0673ad47 CW |
887 | mmio_size = 512 * 1024; |
888 | else | |
889 | mmio_size = 2 * 1024 * 1024; | |
52a05c30 | 890 | dev_priv->regs = pci_iomap(pdev, mmio_bar, mmio_size); |
0673ad47 CW |
891 | if (dev_priv->regs == NULL) { |
892 | DRM_ERROR("failed to map registers\n"); | |
893 | ||
894 | return -EIO; | |
895 | } | |
896 | ||
897 | /* Try to make sure MCHBAR is enabled before poking at it */ | |
898 | intel_setup_mchbar(dev); | |
899 | ||
900 | return 0; | |
901 | } | |
902 | ||
903 | static void i915_mmio_cleanup(struct drm_device *dev) | |
904 | { | |
905 | struct drm_i915_private *dev_priv = to_i915(dev); | |
52a05c30 | 906 | struct pci_dev *pdev = dev_priv->drm.pdev; |
0673ad47 CW |
907 | |
908 | intel_teardown_mchbar(dev); | |
52a05c30 | 909 | pci_iounmap(pdev, dev_priv->regs); |
0673ad47 CW |
910 | } |
911 | ||
912 | /** | |
913 | * i915_driver_init_mmio - setup device MMIO | |
914 | * @dev_priv: device private | |
915 | * | |
916 | * Setup minimal device state necessary for MMIO accesses later in the | |
917 | * initialization sequence. The setup here should avoid any other device-wide | |
918 | * side effects or exposing the driver via kernel internal or user space | |
919 | * interfaces. | |
920 | */ | |
921 | static int i915_driver_init_mmio(struct drm_i915_private *dev_priv) | |
922 | { | |
91c8a326 | 923 | struct drm_device *dev = &dev_priv->drm; |
0673ad47 CW |
924 | int ret; |
925 | ||
926 | if (i915_inject_load_failure()) | |
927 | return -ENODEV; | |
928 | ||
929 | if (i915_get_bridge_dev(dev)) | |
930 | return -EIO; | |
931 | ||
932 | ret = i915_mmio_setup(dev); | |
933 | if (ret < 0) | |
934 | goto put_bridge; | |
935 | ||
936 | intel_uncore_init(dev_priv); | |
937 | ||
938 | return 0; | |
939 | ||
940 | put_bridge: | |
941 | pci_dev_put(dev_priv->bridge_dev); | |
942 | ||
943 | return ret; | |
944 | } | |
945 | ||
946 | /** | |
947 | * i915_driver_cleanup_mmio - cleanup the setup done in i915_driver_init_mmio() | |
948 | * @dev_priv: device private | |
949 | */ | |
950 | static void i915_driver_cleanup_mmio(struct drm_i915_private *dev_priv) | |
951 | { | |
91c8a326 | 952 | struct drm_device *dev = &dev_priv->drm; |
0673ad47 CW |
953 | |
954 | intel_uncore_fini(dev_priv); | |
955 | i915_mmio_cleanup(dev); | |
956 | pci_dev_put(dev_priv->bridge_dev); | |
957 | } | |
958 | ||
94b4f3ba CW |
959 | static void intel_sanitize_options(struct drm_i915_private *dev_priv) |
960 | { | |
961 | i915.enable_execlists = | |
962 | intel_sanitize_enable_execlists(dev_priv, | |
963 | i915.enable_execlists); | |
964 | ||
965 | /* | |
966 | * i915.enable_ppgtt is read-only, so do an early pass to validate the | |
967 | * user's requested state against the hardware/driver capabilities. We | |
968 | * do this now so that we can print out any log messages once rather | |
969 | * than every time we check intel_enable_ppgtt(). | |
970 | */ | |
971 | i915.enable_ppgtt = | |
972 | intel_sanitize_enable_ppgtt(dev_priv, i915.enable_ppgtt); | |
973 | DRM_DEBUG_DRIVER("ppgtt mode: %i\n", i915.enable_ppgtt); | |
39df9190 CW |
974 | |
975 | i915.semaphores = intel_sanitize_semaphores(dev_priv, i915.semaphores); | |
976 | DRM_DEBUG_DRIVER("use GPU sempahores? %s\n", yesno(i915.semaphores)); | |
94b4f3ba CW |
977 | } |
978 | ||
0673ad47 CW |
979 | /** |
980 | * i915_driver_init_hw - setup state requiring device access | |
981 | * @dev_priv: device private | |
982 | * | |
983 | * Setup state that requires accessing the device, but doesn't require | |
984 | * exposing the driver via kernel internal or userspace interfaces. | |
985 | */ | |
986 | static int i915_driver_init_hw(struct drm_i915_private *dev_priv) | |
987 | { | |
52a05c30 | 988 | struct pci_dev *pdev = dev_priv->drm.pdev; |
0673ad47 CW |
989 | int ret; |
990 | ||
991 | if (i915_inject_load_failure()) | |
992 | return -ENODEV; | |
993 | ||
94b4f3ba CW |
994 | intel_device_info_runtime_init(dev_priv); |
995 | ||
996 | intel_sanitize_options(dev_priv); | |
0673ad47 | 997 | |
97d6d7ab | 998 | ret = i915_ggtt_probe_hw(dev_priv); |
0673ad47 CW |
999 | if (ret) |
1000 | return ret; | |
1001 | ||
0673ad47 CW |
1002 | /* WARNING: Apparently we must kick fbdev drivers before vgacon, |
1003 | * otherwise the vga fbdev driver falls over. */ | |
1004 | ret = i915_kick_out_firmware_fb(dev_priv); | |
1005 | if (ret) { | |
1006 | DRM_ERROR("failed to remove conflicting framebuffer drivers\n"); | |
1007 | goto out_ggtt; | |
1008 | } | |
1009 | ||
1010 | ret = i915_kick_out_vgacon(dev_priv); | |
1011 | if (ret) { | |
1012 | DRM_ERROR("failed to remove conflicting VGA console\n"); | |
1013 | goto out_ggtt; | |
1014 | } | |
1015 | ||
97d6d7ab | 1016 | ret = i915_ggtt_init_hw(dev_priv); |
0088e522 CW |
1017 | if (ret) |
1018 | return ret; | |
1019 | ||
97d6d7ab | 1020 | ret = i915_ggtt_enable_hw(dev_priv); |
0088e522 CW |
1021 | if (ret) { |
1022 | DRM_ERROR("failed to enable GGTT\n"); | |
1023 | goto out_ggtt; | |
1024 | } | |
1025 | ||
52a05c30 | 1026 | pci_set_master(pdev); |
0673ad47 CW |
1027 | |
1028 | /* overlay on gen2 is broken and can't address above 1G */ | |
5db94019 | 1029 | if (IS_GEN2(dev_priv)) { |
52a05c30 | 1030 | ret = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(30)); |
0673ad47 CW |
1031 | if (ret) { |
1032 | DRM_ERROR("failed to set DMA mask\n"); | |
1033 | ||
1034 | goto out_ggtt; | |
1035 | } | |
1036 | } | |
1037 | ||
0673ad47 CW |
1038 | /* 965GM sometimes incorrectly writes to hardware status page (HWS) |
1039 | * using 32bit addressing, overwriting memory if HWS is located | |
1040 | * above 4GB. | |
1041 | * | |
1042 | * The documentation also mentions an issue with undefined | |
1043 | * behaviour if any general state is accessed within a page above 4GB, | |
1044 | * which also needs to be handled carefully. | |
1045 | */ | |
a26e5239 | 1046 | if (IS_BROADWATER(dev_priv) || IS_CRESTLINE(dev_priv)) { |
52a05c30 | 1047 | ret = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32)); |
0673ad47 CW |
1048 | |
1049 | if (ret) { | |
1050 | DRM_ERROR("failed to set DMA mask\n"); | |
1051 | ||
1052 | goto out_ggtt; | |
1053 | } | |
1054 | } | |
1055 | ||
0673ad47 CW |
1056 | pm_qos_add_request(&dev_priv->pm_qos, PM_QOS_CPU_DMA_LATENCY, |
1057 | PM_QOS_DEFAULT_VALUE); | |
1058 | ||
1059 | intel_uncore_sanitize(dev_priv); | |
1060 | ||
1061 | intel_opregion_setup(dev_priv); | |
1062 | ||
1063 | i915_gem_load_init_fences(dev_priv); | |
1064 | ||
1065 | /* On the 945G/GM, the chipset reports the MSI capability on the | |
1066 | * integrated graphics even though the support isn't actually there | |
1067 | * according to the published specs. It doesn't appear to function | |
1068 | * correctly in testing on 945G. | |
1069 | * This may be a side effect of MSI having been made available for PEG | |
1070 | * and the registers being closely associated. | |
1071 | * | |
1072 | * According to chipset errata, on the 965GM, MSI interrupts may | |
1073 | * be lost or delayed, but we use them anyways to avoid | |
1074 | * stuck interrupts on some machines. | |
1075 | */ | |
50a0bc90 | 1076 | if (!IS_I945G(dev_priv) && !IS_I945GM(dev_priv)) { |
52a05c30 | 1077 | if (pci_enable_msi(pdev) < 0) |
0673ad47 CW |
1078 | DRM_DEBUG_DRIVER("can't enable MSI"); |
1079 | } | |
1080 | ||
1081 | return 0; | |
1082 | ||
1083 | out_ggtt: | |
97d6d7ab | 1084 | i915_ggtt_cleanup_hw(dev_priv); |
0673ad47 CW |
1085 | |
1086 | return ret; | |
1087 | } | |
1088 | ||
1089 | /** | |
1090 | * i915_driver_cleanup_hw - cleanup the setup done in i915_driver_init_hw() | |
1091 | * @dev_priv: device private | |
1092 | */ | |
1093 | static void i915_driver_cleanup_hw(struct drm_i915_private *dev_priv) | |
1094 | { | |
52a05c30 | 1095 | struct pci_dev *pdev = dev_priv->drm.pdev; |
0673ad47 | 1096 | |
52a05c30 DW |
1097 | if (pdev->msi_enabled) |
1098 | pci_disable_msi(pdev); | |
0673ad47 CW |
1099 | |
1100 | pm_qos_remove_request(&dev_priv->pm_qos); | |
97d6d7ab | 1101 | i915_ggtt_cleanup_hw(dev_priv); |
0673ad47 CW |
1102 | } |
1103 | ||
1104 | /** | |
1105 | * i915_driver_register - register the driver with the rest of the system | |
1106 | * @dev_priv: device private | |
1107 | * | |
1108 | * Perform any steps necessary to make the driver available via kernel | |
1109 | * internal or userspace interfaces. | |
1110 | */ | |
1111 | static void i915_driver_register(struct drm_i915_private *dev_priv) | |
1112 | { | |
91c8a326 | 1113 | struct drm_device *dev = &dev_priv->drm; |
0673ad47 CW |
1114 | |
1115 | i915_gem_shrinker_init(dev_priv); | |
1116 | ||
1117 | /* | |
1118 | * Notify a valid surface after modesetting, | |
1119 | * when running inside a VM. | |
1120 | */ | |
1121 | if (intel_vgpu_active(dev_priv)) | |
1122 | I915_WRITE(vgtif_reg(display_ready), VGT_DRV_DISPLAY_READY); | |
1123 | ||
1124 | /* Reveal our presence to userspace */ | |
1125 | if (drm_dev_register(dev, 0) == 0) { | |
1126 | i915_debugfs_register(dev_priv); | |
f8240835 | 1127 | i915_guc_register(dev_priv); |
694c2828 | 1128 | i915_setup_sysfs(dev_priv); |
0673ad47 CW |
1129 | } else |
1130 | DRM_ERROR("Failed to register driver for userspace access!\n"); | |
1131 | ||
1132 | if (INTEL_INFO(dev_priv)->num_pipes) { | |
1133 | /* Must be done after probing outputs */ | |
1134 | intel_opregion_register(dev_priv); | |
1135 | acpi_video_register(); | |
1136 | } | |
1137 | ||
1138 | if (IS_GEN5(dev_priv)) | |
1139 | intel_gpu_ips_init(dev_priv); | |
1140 | ||
1141 | i915_audio_component_init(dev_priv); | |
1142 | ||
1143 | /* | |
1144 | * Some ports require correctly set-up hpd registers for detection to | |
1145 | * work properly (leading to ghost connected connector status), e.g. VGA | |
1146 | * on gm45. Hence we can only set up the initial fbdev config after hpd | |
1147 | * irqs are fully enabled. We do it last so that the async config | |
1148 | * cannot run before the connectors are registered. | |
1149 | */ | |
1150 | intel_fbdev_initial_config_async(dev); | |
1151 | } | |
1152 | ||
1153 | /** | |
1154 | * i915_driver_unregister - cleanup the registration done in i915_driver_regiser() | |
1155 | * @dev_priv: device private | |
1156 | */ | |
1157 | static void i915_driver_unregister(struct drm_i915_private *dev_priv) | |
1158 | { | |
1159 | i915_audio_component_cleanup(dev_priv); | |
1160 | ||
1161 | intel_gpu_ips_teardown(); | |
1162 | acpi_video_unregister(); | |
1163 | intel_opregion_unregister(dev_priv); | |
1164 | ||
694c2828 | 1165 | i915_teardown_sysfs(dev_priv); |
f8240835 | 1166 | i915_guc_unregister(dev_priv); |
0673ad47 | 1167 | i915_debugfs_unregister(dev_priv); |
91c8a326 | 1168 | drm_dev_unregister(&dev_priv->drm); |
0673ad47 CW |
1169 | |
1170 | i915_gem_shrinker_cleanup(dev_priv); | |
1171 | } | |
1172 | ||
1173 | /** | |
1174 | * i915_driver_load - setup chip and create an initial config | |
d2ad3ae4 JL |
1175 | * @pdev: PCI device |
1176 | * @ent: matching PCI ID entry | |
0673ad47 CW |
1177 | * |
1178 | * The driver load routine has to do several things: | |
1179 | * - drive output discovery via intel_modeset_init() | |
1180 | * - initialize the memory manager | |
1181 | * - allocate initial config memory | |
1182 | * - setup the DRM framebuffer with the allocated memory | |
1183 | */ | |
42f5551d | 1184 | int i915_driver_load(struct pci_dev *pdev, const struct pci_device_id *ent) |
0673ad47 CW |
1185 | { |
1186 | struct drm_i915_private *dev_priv; | |
1187 | int ret; | |
7d87a7f7 | 1188 | |
a09d0ba1 CW |
1189 | if (i915.nuclear_pageflip) |
1190 | driver.driver_features |= DRIVER_ATOMIC; | |
1191 | ||
0673ad47 CW |
1192 | ret = -ENOMEM; |
1193 | dev_priv = kzalloc(sizeof(*dev_priv), GFP_KERNEL); | |
1194 | if (dev_priv) | |
1195 | ret = drm_dev_init(&dev_priv->drm, &driver, &pdev->dev); | |
1196 | if (ret) { | |
1197 | dev_printk(KERN_ERR, &pdev->dev, | |
1198 | "[" DRM_NAME ":%s] allocation failed\n", __func__); | |
1199 | kfree(dev_priv); | |
1200 | return ret; | |
1201 | } | |
72bbf0af | 1202 | |
0673ad47 CW |
1203 | dev_priv->drm.pdev = pdev; |
1204 | dev_priv->drm.dev_private = dev_priv; | |
719388e1 | 1205 | |
0673ad47 CW |
1206 | ret = pci_enable_device(pdev); |
1207 | if (ret) | |
1208 | goto out_free_priv; | |
1347f5b4 | 1209 | |
0673ad47 | 1210 | pci_set_drvdata(pdev, &dev_priv->drm); |
ef11bdb3 | 1211 | |
0673ad47 CW |
1212 | ret = i915_driver_init_early(dev_priv, ent); |
1213 | if (ret < 0) | |
1214 | goto out_pci_disable; | |
ef11bdb3 | 1215 | |
0673ad47 | 1216 | intel_runtime_pm_get(dev_priv); |
1da177e4 | 1217 | |
0673ad47 CW |
1218 | ret = i915_driver_init_mmio(dev_priv); |
1219 | if (ret < 0) | |
1220 | goto out_runtime_pm_put; | |
79e53945 | 1221 | |
0673ad47 CW |
1222 | ret = i915_driver_init_hw(dev_priv); |
1223 | if (ret < 0) | |
1224 | goto out_cleanup_mmio; | |
30c964a6 RB |
1225 | |
1226 | /* | |
0673ad47 CW |
1227 | * TODO: move the vblank init and parts of modeset init steps into one |
1228 | * of the i915_driver_init_/i915_driver_register functions according | |
1229 | * to the role/effect of the given init step. | |
30c964a6 | 1230 | */ |
0673ad47 | 1231 | if (INTEL_INFO(dev_priv)->num_pipes) { |
91c8a326 | 1232 | ret = drm_vblank_init(&dev_priv->drm, |
0673ad47 CW |
1233 | INTEL_INFO(dev_priv)->num_pipes); |
1234 | if (ret) | |
1235 | goto out_cleanup_hw; | |
30c964a6 RB |
1236 | } |
1237 | ||
91c8a326 | 1238 | ret = i915_load_modeset_init(&dev_priv->drm); |
0673ad47 CW |
1239 | if (ret < 0) |
1240 | goto out_cleanup_vblank; | |
1241 | ||
1242 | i915_driver_register(dev_priv); | |
1243 | ||
1244 | intel_runtime_pm_enable(dev_priv); | |
1245 | ||
bc5ca47c CW |
1246 | /* Everything is in place, we can now relax! */ |
1247 | DRM_INFO("Initialized %s %d.%d.%d %s for %s on minor %d\n", | |
1248 | driver.name, driver.major, driver.minor, driver.patchlevel, | |
1249 | driver.date, pci_name(pdev), dev_priv->drm.primary->index); | |
0525a062 CW |
1250 | if (IS_ENABLED(CONFIG_DRM_I915_DEBUG)) |
1251 | DRM_INFO("DRM_I915_DEBUG enabled\n"); | |
1252 | if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM)) | |
1253 | DRM_INFO("DRM_I915_DEBUG_GEM enabled\n"); | |
bc5ca47c | 1254 | |
0673ad47 CW |
1255 | intel_runtime_pm_put(dev_priv); |
1256 | ||
1257 | return 0; | |
1258 | ||
1259 | out_cleanup_vblank: | |
91c8a326 | 1260 | drm_vblank_cleanup(&dev_priv->drm); |
0673ad47 CW |
1261 | out_cleanup_hw: |
1262 | i915_driver_cleanup_hw(dev_priv); | |
1263 | out_cleanup_mmio: | |
1264 | i915_driver_cleanup_mmio(dev_priv); | |
1265 | out_runtime_pm_put: | |
1266 | intel_runtime_pm_put(dev_priv); | |
1267 | i915_driver_cleanup_early(dev_priv); | |
1268 | out_pci_disable: | |
1269 | pci_disable_device(pdev); | |
1270 | out_free_priv: | |
1271 | i915_load_error(dev_priv, "Device initialization failed (%d)\n", ret); | |
1272 | drm_dev_unref(&dev_priv->drm); | |
30c964a6 RB |
1273 | return ret; |
1274 | } | |
1275 | ||
42f5551d | 1276 | void i915_driver_unload(struct drm_device *dev) |
3bad0781 | 1277 | { |
fac5e23e | 1278 | struct drm_i915_private *dev_priv = to_i915(dev); |
52a05c30 | 1279 | struct pci_dev *pdev = dev_priv->drm.pdev; |
3bad0781 | 1280 | |
0673ad47 CW |
1281 | intel_fbdev_fini(dev); |
1282 | ||
42f5551d CW |
1283 | if (i915_gem_suspend(dev)) |
1284 | DRM_ERROR("failed to idle hardware; continuing to unload!\n"); | |
ce1bb329 | 1285 | |
0673ad47 CW |
1286 | intel_display_power_get(dev_priv, POWER_DOMAIN_INIT); |
1287 | ||
1288 | i915_driver_unregister(dev_priv); | |
1289 | ||
1290 | drm_vblank_cleanup(dev); | |
1291 | ||
1292 | intel_modeset_cleanup(dev); | |
1293 | ||
3bad0781 | 1294 | /* |
0673ad47 CW |
1295 | * free the memory space allocated for the child device |
1296 | * config parsed from VBT | |
3bad0781 | 1297 | */ |
0673ad47 CW |
1298 | if (dev_priv->vbt.child_dev && dev_priv->vbt.child_dev_num) { |
1299 | kfree(dev_priv->vbt.child_dev); | |
1300 | dev_priv->vbt.child_dev = NULL; | |
1301 | dev_priv->vbt.child_dev_num = 0; | |
1302 | } | |
1303 | kfree(dev_priv->vbt.sdvo_lvds_vbt_mode); | |
1304 | dev_priv->vbt.sdvo_lvds_vbt_mode = NULL; | |
1305 | kfree(dev_priv->vbt.lfp_lvds_vbt_mode); | |
1306 | dev_priv->vbt.lfp_lvds_vbt_mode = NULL; | |
3bad0781 | 1307 | |
52a05c30 DW |
1308 | vga_switcheroo_unregister_client(pdev); |
1309 | vga_client_register(pdev, NULL, NULL, NULL); | |
bcdb72ac | 1310 | |
0673ad47 | 1311 | intel_csr_ucode_fini(dev_priv); |
bcdb72ac | 1312 | |
0673ad47 CW |
1313 | /* Free error state after interrupts are fully disabled. */ |
1314 | cancel_delayed_work_sync(&dev_priv->gpu_error.hangcheck_work); | |
1315 | i915_destroy_error_state(dev); | |
1316 | ||
1317 | /* Flush any outstanding unpin_work. */ | |
b7137e0c | 1318 | drain_workqueue(dev_priv->wq); |
0673ad47 CW |
1319 | |
1320 | intel_guc_fini(dev); | |
fbbd37b3 | 1321 | i915_gem_fini(dev_priv); |
0673ad47 CW |
1322 | intel_fbc_cleanup_cfb(dev_priv); |
1323 | ||
1324 | intel_power_domains_fini(dev_priv); | |
1325 | ||
1326 | i915_driver_cleanup_hw(dev_priv); | |
1327 | i915_driver_cleanup_mmio(dev_priv); | |
1328 | ||
1329 | intel_display_power_put(dev_priv, POWER_DOMAIN_INIT); | |
1330 | ||
1331 | i915_driver_cleanup_early(dev_priv); | |
3bad0781 ZW |
1332 | } |
1333 | ||
0673ad47 | 1334 | static int i915_driver_open(struct drm_device *dev, struct drm_file *file) |
2911a35b | 1335 | { |
0673ad47 | 1336 | int ret; |
2911a35b | 1337 | |
0673ad47 CW |
1338 | ret = i915_gem_open(dev, file); |
1339 | if (ret) | |
1340 | return ret; | |
2911a35b | 1341 | |
0673ad47 CW |
1342 | return 0; |
1343 | } | |
71386ef9 | 1344 | |
0673ad47 CW |
1345 | /** |
1346 | * i915_driver_lastclose - clean up after all DRM clients have exited | |
1347 | * @dev: DRM device | |
1348 | * | |
1349 | * Take care of cleaning up after all DRM clients have exited. In the | |
1350 | * mode setting case, we want to restore the kernel's initial mode (just | |
1351 | * in case the last client left us in a bad state). | |
1352 | * | |
1353 | * Additionally, in the non-mode setting case, we'll tear down the GTT | |
1354 | * and DMA structures, since the kernel won't be using them, and clea | |
1355 | * up any GEM state. | |
1356 | */ | |
1357 | static void i915_driver_lastclose(struct drm_device *dev) | |
1358 | { | |
1359 | intel_fbdev_restore_mode(dev); | |
1360 | vga_switcheroo_process_delayed_switch(); | |
1361 | } | |
2911a35b | 1362 | |
0673ad47 CW |
1363 | static void i915_driver_preclose(struct drm_device *dev, struct drm_file *file) |
1364 | { | |
1365 | mutex_lock(&dev->struct_mutex); | |
1366 | i915_gem_context_close(dev, file); | |
1367 | i915_gem_release(dev, file); | |
1368 | mutex_unlock(&dev->struct_mutex); | |
1369 | } | |
1370 | ||
1371 | static void i915_driver_postclose(struct drm_device *dev, struct drm_file *file) | |
1372 | { | |
1373 | struct drm_i915_file_private *file_priv = file->driver_priv; | |
1374 | ||
1375 | kfree(file_priv); | |
2911a35b BW |
1376 | } |
1377 | ||
07f9cd0b ID |
1378 | static void intel_suspend_encoders(struct drm_i915_private *dev_priv) |
1379 | { | |
91c8a326 | 1380 | struct drm_device *dev = &dev_priv->drm; |
19c8054c | 1381 | struct intel_encoder *encoder; |
07f9cd0b ID |
1382 | |
1383 | drm_modeset_lock_all(dev); | |
19c8054c JN |
1384 | for_each_intel_encoder(dev, encoder) |
1385 | if (encoder->suspend) | |
1386 | encoder->suspend(encoder); | |
07f9cd0b ID |
1387 | drm_modeset_unlock_all(dev); |
1388 | } | |
1389 | ||
1a5df187 PZ |
1390 | static int vlv_resume_prepare(struct drm_i915_private *dev_priv, |
1391 | bool rpm_resume); | |
507e126e | 1392 | static int vlv_suspend_complete(struct drm_i915_private *dev_priv); |
f75a1985 | 1393 | |
bc87229f ID |
1394 | static bool suspend_to_idle(struct drm_i915_private *dev_priv) |
1395 | { | |
1396 | #if IS_ENABLED(CONFIG_ACPI_SLEEP) | |
1397 | if (acpi_target_system_state() < ACPI_STATE_S3) | |
1398 | return true; | |
1399 | #endif | |
1400 | return false; | |
1401 | } | |
ebc32824 | 1402 | |
5e365c39 | 1403 | static int i915_drm_suspend(struct drm_device *dev) |
ba8bbcf6 | 1404 | { |
fac5e23e | 1405 | struct drm_i915_private *dev_priv = to_i915(dev); |
52a05c30 | 1406 | struct pci_dev *pdev = dev_priv->drm.pdev; |
e5747e3a | 1407 | pci_power_t opregion_target_state; |
d5818938 | 1408 | int error; |
61caf87c | 1409 | |
b8efb17b ZR |
1410 | /* ignore lid events during suspend */ |
1411 | mutex_lock(&dev_priv->modeset_restore_lock); | |
1412 | dev_priv->modeset_restore = MODESET_SUSPENDED; | |
1413 | mutex_unlock(&dev_priv->modeset_restore_lock); | |
1414 | ||
1f814dac ID |
1415 | disable_rpm_wakeref_asserts(dev_priv); |
1416 | ||
c67a470b PZ |
1417 | /* We do a lot of poking in a lot of registers, make sure they work |
1418 | * properly. */ | |
da7e29bd | 1419 | intel_display_set_init_power(dev_priv, true); |
cb10799c | 1420 | |
5bcf719b DA |
1421 | drm_kms_helper_poll_disable(dev); |
1422 | ||
52a05c30 | 1423 | pci_save_state(pdev); |
ba8bbcf6 | 1424 | |
d5818938 DV |
1425 | error = i915_gem_suspend(dev); |
1426 | if (error) { | |
52a05c30 | 1427 | dev_err(&pdev->dev, |
d5818938 | 1428 | "GEM idle failed, resume might fail\n"); |
1f814dac | 1429 | goto out; |
d5818938 | 1430 | } |
db1b76ca | 1431 | |
a1c41994 AD |
1432 | intel_guc_suspend(dev); |
1433 | ||
6b72d486 | 1434 | intel_display_suspend(dev); |
2eb5252e | 1435 | |
d5818938 | 1436 | intel_dp_mst_suspend(dev); |
7d708ee4 | 1437 | |
d5818938 DV |
1438 | intel_runtime_pm_disable_interrupts(dev_priv); |
1439 | intel_hpd_cancel_work(dev_priv); | |
09b64267 | 1440 | |
d5818938 | 1441 | intel_suspend_encoders(dev_priv); |
0e32b39c | 1442 | |
712bf364 | 1443 | intel_suspend_hw(dev_priv); |
5669fcac | 1444 | |
828c7908 BW |
1445 | i915_gem_suspend_gtt_mappings(dev); |
1446 | ||
9e06dd39 JB |
1447 | i915_save_state(dev); |
1448 | ||
bc87229f | 1449 | opregion_target_state = suspend_to_idle(dev_priv) ? PCI_D1 : PCI_D3cold; |
6f9f4b7a | 1450 | intel_opregion_notify_adapter(dev_priv, opregion_target_state); |
e5747e3a | 1451 | |
dc97997a | 1452 | intel_uncore_forcewake_reset(dev_priv, false); |
03d92e47 | 1453 | intel_opregion_unregister(dev_priv); |
8ee1c3db | 1454 | |
82e3b8c1 | 1455 | intel_fbdev_set_suspend(dev, FBINFO_STATE_SUSPENDED, true); |
3fa016a0 | 1456 | |
62d5d69b MK |
1457 | dev_priv->suspend_count++; |
1458 | ||
f74ed08d | 1459 | intel_csr_ucode_suspend(dev_priv); |
f514c2d8 | 1460 | |
1f814dac ID |
1461 | out: |
1462 | enable_rpm_wakeref_asserts(dev_priv); | |
1463 | ||
1464 | return error; | |
84b79f8d RW |
1465 | } |
1466 | ||
c49d13ee | 1467 | static int i915_drm_suspend_late(struct drm_device *dev, bool hibernation) |
c3c09c95 | 1468 | { |
c49d13ee | 1469 | struct drm_i915_private *dev_priv = to_i915(dev); |
52a05c30 | 1470 | struct pci_dev *pdev = dev_priv->drm.pdev; |
bc87229f | 1471 | bool fw_csr; |
c3c09c95 ID |
1472 | int ret; |
1473 | ||
1f814dac ID |
1474 | disable_rpm_wakeref_asserts(dev_priv); |
1475 | ||
4c494a57 ID |
1476 | intel_display_set_init_power(dev_priv, false); |
1477 | ||
a7c8125f ID |
1478 | fw_csr = !IS_BROXTON(dev_priv) && |
1479 | suspend_to_idle(dev_priv) && dev_priv->csr.dmc_payload; | |
bc87229f ID |
1480 | /* |
1481 | * In case of firmware assisted context save/restore don't manually | |
1482 | * deinit the power domains. This also means the CSR/DMC firmware will | |
1483 | * stay active, it will power down any HW resources as required and | |
1484 | * also enable deeper system power states that would be blocked if the | |
1485 | * firmware was inactive. | |
1486 | */ | |
1487 | if (!fw_csr) | |
1488 | intel_power_domains_suspend(dev_priv); | |
73dfc227 | 1489 | |
507e126e | 1490 | ret = 0; |
b8aea3d1 | 1491 | if (IS_BROXTON(dev_priv)) |
507e126e | 1492 | bxt_enable_dc9(dev_priv); |
b8aea3d1 | 1493 | else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) |
507e126e ID |
1494 | hsw_enable_pc8(dev_priv); |
1495 | else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) | |
1496 | ret = vlv_suspend_complete(dev_priv); | |
c3c09c95 ID |
1497 | |
1498 | if (ret) { | |
1499 | DRM_ERROR("Suspend complete failed: %d\n", ret); | |
bc87229f ID |
1500 | if (!fw_csr) |
1501 | intel_power_domains_init_hw(dev_priv, true); | |
c3c09c95 | 1502 | |
1f814dac | 1503 | goto out; |
c3c09c95 ID |
1504 | } |
1505 | ||
52a05c30 | 1506 | pci_disable_device(pdev); |
ab3be73f | 1507 | /* |
54875571 | 1508 | * During hibernation on some platforms the BIOS may try to access |
ab3be73f ID |
1509 | * the device even though it's already in D3 and hang the machine. So |
1510 | * leave the device in D0 on those platforms and hope the BIOS will | |
54875571 ID |
1511 | * power down the device properly. The issue was seen on multiple old |
1512 | * GENs with different BIOS vendors, so having an explicit blacklist | |
1513 | * is inpractical; apply the workaround on everything pre GEN6. The | |
1514 | * platforms where the issue was seen: | |
1515 | * Lenovo Thinkpad X301, X61s, X60, T60, X41 | |
1516 | * Fujitsu FSC S7110 | |
1517 | * Acer Aspire 1830T | |
ab3be73f | 1518 | */ |
514e1d64 | 1519 | if (!(hibernation && INTEL_GEN(dev_priv) < 6)) |
52a05c30 | 1520 | pci_set_power_state(pdev, PCI_D3hot); |
c3c09c95 | 1521 | |
bc87229f ID |
1522 | dev_priv->suspended_to_idle = suspend_to_idle(dev_priv); |
1523 | ||
1f814dac ID |
1524 | out: |
1525 | enable_rpm_wakeref_asserts(dev_priv); | |
1526 | ||
1527 | return ret; | |
c3c09c95 ID |
1528 | } |
1529 | ||
1751fcf9 | 1530 | int i915_suspend_switcheroo(struct drm_device *dev, pm_message_t state) |
84b79f8d RW |
1531 | { |
1532 | int error; | |
1533 | ||
ded8b07d | 1534 | if (!dev) { |
84b79f8d RW |
1535 | DRM_ERROR("dev: %p\n", dev); |
1536 | DRM_ERROR("DRM not initialized, aborting suspend.\n"); | |
1537 | return -ENODEV; | |
1538 | } | |
1539 | ||
0b14cbd2 ID |
1540 | if (WARN_ON_ONCE(state.event != PM_EVENT_SUSPEND && |
1541 | state.event != PM_EVENT_FREEZE)) | |
1542 | return -EINVAL; | |
5bcf719b DA |
1543 | |
1544 | if (dev->switch_power_state == DRM_SWITCH_POWER_OFF) | |
1545 | return 0; | |
6eecba33 | 1546 | |
5e365c39 | 1547 | error = i915_drm_suspend(dev); |
84b79f8d RW |
1548 | if (error) |
1549 | return error; | |
1550 | ||
ab3be73f | 1551 | return i915_drm_suspend_late(dev, false); |
ba8bbcf6 JB |
1552 | } |
1553 | ||
5e365c39 | 1554 | static int i915_drm_resume(struct drm_device *dev) |
76c4b250 | 1555 | { |
fac5e23e | 1556 | struct drm_i915_private *dev_priv = to_i915(dev); |
ac840ae5 | 1557 | int ret; |
9d49c0ef | 1558 | |
1f814dac | 1559 | disable_rpm_wakeref_asserts(dev_priv); |
abc80abd | 1560 | intel_sanitize_gt_powersave(dev_priv); |
1f814dac | 1561 | |
97d6d7ab | 1562 | ret = i915_ggtt_enable_hw(dev_priv); |
ac840ae5 VS |
1563 | if (ret) |
1564 | DRM_ERROR("failed to re-enable GGTT\n"); | |
1565 | ||
f74ed08d ID |
1566 | intel_csr_ucode_resume(dev_priv); |
1567 | ||
5ab57c70 | 1568 | i915_gem_resume(dev); |
9d49c0ef | 1569 | |
61caf87c | 1570 | i915_restore_state(dev); |
8090ba8c | 1571 | intel_pps_unlock_regs_wa(dev_priv); |
6f9f4b7a | 1572 | intel_opregion_setup(dev_priv); |
61caf87c | 1573 | |
d5818938 DV |
1574 | intel_init_pch_refclk(dev); |
1575 | drm_mode_config_reset(dev); | |
1833b134 | 1576 | |
364aece0 PA |
1577 | /* |
1578 | * Interrupts have to be enabled before any batches are run. If not the | |
1579 | * GPU will hang. i915_gem_init_hw() will initiate batches to | |
1580 | * update/restore the context. | |
1581 | * | |
1582 | * Modeset enabling in intel_modeset_init_hw() also needs working | |
1583 | * interrupts. | |
1584 | */ | |
1585 | intel_runtime_pm_enable_interrupts(dev_priv); | |
1586 | ||
d5818938 DV |
1587 | mutex_lock(&dev->struct_mutex); |
1588 | if (i915_gem_init_hw(dev)) { | |
1589 | DRM_ERROR("failed to re-initialize GPU, declaring wedged!\n"); | |
821ed7df | 1590 | i915_gem_set_wedged(dev_priv); |
d5818938 DV |
1591 | } |
1592 | mutex_unlock(&dev->struct_mutex); | |
226485e9 | 1593 | |
a1c41994 AD |
1594 | intel_guc_resume(dev); |
1595 | ||
d5818938 | 1596 | intel_modeset_init_hw(dev); |
24576d23 | 1597 | |
d5818938 DV |
1598 | spin_lock_irq(&dev_priv->irq_lock); |
1599 | if (dev_priv->display.hpd_irq_setup) | |
91d14251 | 1600 | dev_priv->display.hpd_irq_setup(dev_priv); |
d5818938 | 1601 | spin_unlock_irq(&dev_priv->irq_lock); |
0e32b39c | 1602 | |
d5818938 | 1603 | intel_dp_mst_resume(dev); |
e7d6f7d7 | 1604 | |
a16b7658 L |
1605 | intel_display_resume(dev); |
1606 | ||
e0b70061 L |
1607 | drm_kms_helper_poll_enable(dev); |
1608 | ||
d5818938 DV |
1609 | /* |
1610 | * ... but also need to make sure that hotplug processing | |
1611 | * doesn't cause havoc. Like in the driver load code we don't | |
1612 | * bother with the tiny race here where we might loose hotplug | |
1613 | * notifications. | |
1614 | * */ | |
1615 | intel_hpd_init(dev_priv); | |
1daed3fb | 1616 | |
03d92e47 | 1617 | intel_opregion_register(dev_priv); |
44834a67 | 1618 | |
82e3b8c1 | 1619 | intel_fbdev_set_suspend(dev, FBINFO_STATE_RUNNING, false); |
073f34d9 | 1620 | |
b8efb17b ZR |
1621 | mutex_lock(&dev_priv->modeset_restore_lock); |
1622 | dev_priv->modeset_restore = MODESET_DONE; | |
1623 | mutex_unlock(&dev_priv->modeset_restore_lock); | |
8a187455 | 1624 | |
6f9f4b7a | 1625 | intel_opregion_notify_adapter(dev_priv, PCI_D0); |
e5747e3a | 1626 | |
54b4f68f | 1627 | intel_autoenable_gt_powersave(dev_priv); |
ee6f280e | 1628 | |
1f814dac ID |
1629 | enable_rpm_wakeref_asserts(dev_priv); |
1630 | ||
074c6ada | 1631 | return 0; |
84b79f8d RW |
1632 | } |
1633 | ||
5e365c39 | 1634 | static int i915_drm_resume_early(struct drm_device *dev) |
84b79f8d | 1635 | { |
fac5e23e | 1636 | struct drm_i915_private *dev_priv = to_i915(dev); |
52a05c30 | 1637 | struct pci_dev *pdev = dev_priv->drm.pdev; |
44410cd0 | 1638 | int ret; |
36d61e67 | 1639 | |
76c4b250 ID |
1640 | /* |
1641 | * We have a resume ordering issue with the snd-hda driver also | |
1642 | * requiring our device to be power up. Due to the lack of a | |
1643 | * parent/child relationship we currently solve this with an early | |
1644 | * resume hook. | |
1645 | * | |
1646 | * FIXME: This should be solved with a special hdmi sink device or | |
1647 | * similar so that power domains can be employed. | |
1648 | */ | |
44410cd0 ID |
1649 | |
1650 | /* | |
1651 | * Note that we need to set the power state explicitly, since we | |
1652 | * powered off the device during freeze and the PCI core won't power | |
1653 | * it back up for us during thaw. Powering off the device during | |
1654 | * freeze is not a hard requirement though, and during the | |
1655 | * suspend/resume phases the PCI core makes sure we get here with the | |
1656 | * device powered on. So in case we change our freeze logic and keep | |
1657 | * the device powered we can also remove the following set power state | |
1658 | * call. | |
1659 | */ | |
52a05c30 | 1660 | ret = pci_set_power_state(pdev, PCI_D0); |
44410cd0 ID |
1661 | if (ret) { |
1662 | DRM_ERROR("failed to set PCI D0 power state (%d)\n", ret); | |
1663 | goto out; | |
1664 | } | |
1665 | ||
1666 | /* | |
1667 | * Note that pci_enable_device() first enables any parent bridge | |
1668 | * device and only then sets the power state for this device. The | |
1669 | * bridge enabling is a nop though, since bridge devices are resumed | |
1670 | * first. The order of enabling power and enabling the device is | |
1671 | * imposed by the PCI core as described above, so here we preserve the | |
1672 | * same order for the freeze/thaw phases. | |
1673 | * | |
1674 | * TODO: eventually we should remove pci_disable_device() / | |
1675 | * pci_enable_enable_device() from suspend/resume. Due to how they | |
1676 | * depend on the device enable refcount we can't anyway depend on them | |
1677 | * disabling/enabling the device. | |
1678 | */ | |
52a05c30 | 1679 | if (pci_enable_device(pdev)) { |
bc87229f ID |
1680 | ret = -EIO; |
1681 | goto out; | |
1682 | } | |
84b79f8d | 1683 | |
52a05c30 | 1684 | pci_set_master(pdev); |
84b79f8d | 1685 | |
1f814dac ID |
1686 | disable_rpm_wakeref_asserts(dev_priv); |
1687 | ||
666a4537 | 1688 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) |
1a5df187 | 1689 | ret = vlv_resume_prepare(dev_priv, false); |
36d61e67 | 1690 | if (ret) |
ff0b187f DL |
1691 | DRM_ERROR("Resume prepare failed: %d, continuing anyway\n", |
1692 | ret); | |
36d61e67 | 1693 | |
dc97997a | 1694 | intel_uncore_early_sanitize(dev_priv, true); |
efee833a | 1695 | |
dc97997a | 1696 | if (IS_BROXTON(dev_priv)) { |
da2f41d1 ID |
1697 | if (!dev_priv->suspended_to_idle) |
1698 | gen9_sanitize_dc_state(dev_priv); | |
507e126e | 1699 | bxt_disable_dc9(dev_priv); |
da2f41d1 | 1700 | } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) { |
a9a6b73a | 1701 | hsw_disable_pc8(dev_priv); |
da2f41d1 | 1702 | } |
efee833a | 1703 | |
dc97997a | 1704 | intel_uncore_sanitize(dev_priv); |
bc87229f | 1705 | |
a7c8125f ID |
1706 | if (IS_BROXTON(dev_priv) || |
1707 | !(dev_priv->suspended_to_idle && dev_priv->csr.dmc_payload)) | |
bc87229f ID |
1708 | intel_power_domains_init_hw(dev_priv, true); |
1709 | ||
6e35e8ab ID |
1710 | enable_rpm_wakeref_asserts(dev_priv); |
1711 | ||
bc87229f ID |
1712 | out: |
1713 | dev_priv->suspended_to_idle = false; | |
36d61e67 ID |
1714 | |
1715 | return ret; | |
76c4b250 ID |
1716 | } |
1717 | ||
1751fcf9 | 1718 | int i915_resume_switcheroo(struct drm_device *dev) |
76c4b250 | 1719 | { |
50a0072f | 1720 | int ret; |
76c4b250 | 1721 | |
097dd837 ID |
1722 | if (dev->switch_power_state == DRM_SWITCH_POWER_OFF) |
1723 | return 0; | |
1724 | ||
5e365c39 | 1725 | ret = i915_drm_resume_early(dev); |
50a0072f ID |
1726 | if (ret) |
1727 | return ret; | |
1728 | ||
5a17514e ID |
1729 | return i915_drm_resume(dev); |
1730 | } | |
1731 | ||
9e60ab03 CW |
1732 | static void disable_engines_irq(struct drm_i915_private *dev_priv) |
1733 | { | |
1734 | struct intel_engine_cs *engine; | |
3b3f1650 | 1735 | enum intel_engine_id id; |
9e60ab03 CW |
1736 | |
1737 | /* Ensure irq handler finishes, and not run again. */ | |
1738 | disable_irq(dev_priv->drm.irq); | |
3b3f1650 | 1739 | for_each_engine(engine, dev_priv, id) |
9e60ab03 CW |
1740 | tasklet_kill(&engine->irq_tasklet); |
1741 | } | |
1742 | ||
1743 | static void enable_engines_irq(struct drm_i915_private *dev_priv) | |
1744 | { | |
1745 | enable_irq(dev_priv->drm.irq); | |
1746 | } | |
1747 | ||
11ed50ec | 1748 | /** |
f3953dcb | 1749 | * i915_reset - reset chip after a hang |
11ed50ec | 1750 | * @dev: drm device to reset |
11ed50ec | 1751 | * |
780f262a CW |
1752 | * Reset the chip. Useful if a hang is detected. Marks the device as wedged |
1753 | * on failure. | |
11ed50ec | 1754 | * |
221fe799 CW |
1755 | * Caller must hold the struct_mutex. |
1756 | * | |
11ed50ec BG |
1757 | * Procedure is fairly simple: |
1758 | * - reset the chip using the reset reg | |
1759 | * - re-init context state | |
1760 | * - re-init hardware status page | |
1761 | * - re-init ring buffer | |
1762 | * - re-init interrupt state | |
1763 | * - re-init display | |
1764 | */ | |
780f262a | 1765 | void i915_reset(struct drm_i915_private *dev_priv) |
11ed50ec | 1766 | { |
91c8a326 | 1767 | struct drm_device *dev = &dev_priv->drm; |
d98c52cf | 1768 | struct i915_gpu_error *error = &dev_priv->gpu_error; |
0573ed4a | 1769 | int ret; |
11ed50ec | 1770 | |
221fe799 CW |
1771 | lockdep_assert_held(&dev->struct_mutex); |
1772 | ||
1773 | if (!test_and_clear_bit(I915_RESET_IN_PROGRESS, &error->flags)) | |
780f262a | 1774 | return; |
11ed50ec | 1775 | |
d98c52cf | 1776 | /* Clear any previous failed attempts at recovery. Time to try again. */ |
8af29b0c CW |
1777 | __clear_bit(I915_WEDGED, &error->flags); |
1778 | error->reset_count++; | |
d98c52cf | 1779 | |
7b4d3a16 | 1780 | pr_notice("drm/i915: Resetting chip after gpu hang\n"); |
9e60ab03 CW |
1781 | |
1782 | disable_engines_irq(dev_priv); | |
dc97997a | 1783 | ret = intel_gpu_reset(dev_priv, ALL_ENGINES); |
9e60ab03 CW |
1784 | enable_engines_irq(dev_priv); |
1785 | ||
0573ed4a | 1786 | if (ret) { |
804e59a8 CW |
1787 | if (ret != -ENODEV) |
1788 | DRM_ERROR("Failed to reset chip: %i\n", ret); | |
1789 | else | |
1790 | DRM_DEBUG_DRIVER("GPU reset disabled\n"); | |
d98c52cf | 1791 | goto error; |
11ed50ec BG |
1792 | } |
1793 | ||
821ed7df | 1794 | i915_gem_reset(dev_priv); |
1362b776 VS |
1795 | intel_overlay_reset(dev_priv); |
1796 | ||
11ed50ec BG |
1797 | /* Ok, now get things going again... */ |
1798 | ||
1799 | /* | |
1800 | * Everything depends on having the GTT running, so we need to start | |
1801 | * there. Fortunately we don't need to do this unless we reset the | |
1802 | * chip at a PCI level. | |
1803 | * | |
1804 | * Next we need to restore the context, but we don't use those | |
1805 | * yet either... | |
1806 | * | |
1807 | * Ring buffer needs to be re-initialized in the KMS case, or if X | |
1808 | * was running at the time of the reset (i.e. we weren't VT | |
1809 | * switched away). | |
1810 | */ | |
33d30a9c | 1811 | ret = i915_gem_init_hw(dev); |
33d30a9c DV |
1812 | if (ret) { |
1813 | DRM_ERROR("Failed hw init on reset %d\n", ret); | |
d98c52cf | 1814 | goto error; |
11ed50ec BG |
1815 | } |
1816 | ||
780f262a CW |
1817 | wakeup: |
1818 | wake_up_bit(&error->flags, I915_RESET_IN_PROGRESS); | |
1819 | return; | |
d98c52cf CW |
1820 | |
1821 | error: | |
821ed7df | 1822 | i915_gem_set_wedged(dev_priv); |
780f262a | 1823 | goto wakeup; |
11ed50ec BG |
1824 | } |
1825 | ||
c49d13ee | 1826 | static int i915_pm_suspend(struct device *kdev) |
112b715e | 1827 | { |
c49d13ee DW |
1828 | struct pci_dev *pdev = to_pci_dev(kdev); |
1829 | struct drm_device *dev = pci_get_drvdata(pdev); | |
112b715e | 1830 | |
c49d13ee DW |
1831 | if (!dev) { |
1832 | dev_err(kdev, "DRM not initialized, aborting suspend.\n"); | |
84b79f8d RW |
1833 | return -ENODEV; |
1834 | } | |
112b715e | 1835 | |
c49d13ee | 1836 | if (dev->switch_power_state == DRM_SWITCH_POWER_OFF) |
5bcf719b DA |
1837 | return 0; |
1838 | ||
c49d13ee | 1839 | return i915_drm_suspend(dev); |
76c4b250 ID |
1840 | } |
1841 | ||
c49d13ee | 1842 | static int i915_pm_suspend_late(struct device *kdev) |
76c4b250 | 1843 | { |
c49d13ee | 1844 | struct drm_device *dev = &kdev_to_i915(kdev)->drm; |
76c4b250 ID |
1845 | |
1846 | /* | |
c965d995 | 1847 | * We have a suspend ordering issue with the snd-hda driver also |
76c4b250 ID |
1848 | * requiring our device to be power up. Due to the lack of a |
1849 | * parent/child relationship we currently solve this with an late | |
1850 | * suspend hook. | |
1851 | * | |
1852 | * FIXME: This should be solved with a special hdmi sink device or | |
1853 | * similar so that power domains can be employed. | |
1854 | */ | |
c49d13ee | 1855 | if (dev->switch_power_state == DRM_SWITCH_POWER_OFF) |
76c4b250 | 1856 | return 0; |
112b715e | 1857 | |
c49d13ee | 1858 | return i915_drm_suspend_late(dev, false); |
ab3be73f ID |
1859 | } |
1860 | ||
c49d13ee | 1861 | static int i915_pm_poweroff_late(struct device *kdev) |
ab3be73f | 1862 | { |
c49d13ee | 1863 | struct drm_device *dev = &kdev_to_i915(kdev)->drm; |
ab3be73f | 1864 | |
c49d13ee | 1865 | if (dev->switch_power_state == DRM_SWITCH_POWER_OFF) |
ab3be73f ID |
1866 | return 0; |
1867 | ||
c49d13ee | 1868 | return i915_drm_suspend_late(dev, true); |
cbda12d7 ZW |
1869 | } |
1870 | ||
c49d13ee | 1871 | static int i915_pm_resume_early(struct device *kdev) |
76c4b250 | 1872 | { |
c49d13ee | 1873 | struct drm_device *dev = &kdev_to_i915(kdev)->drm; |
76c4b250 | 1874 | |
c49d13ee | 1875 | if (dev->switch_power_state == DRM_SWITCH_POWER_OFF) |
097dd837 ID |
1876 | return 0; |
1877 | ||
c49d13ee | 1878 | return i915_drm_resume_early(dev); |
76c4b250 ID |
1879 | } |
1880 | ||
c49d13ee | 1881 | static int i915_pm_resume(struct device *kdev) |
cbda12d7 | 1882 | { |
c49d13ee | 1883 | struct drm_device *dev = &kdev_to_i915(kdev)->drm; |
84b79f8d | 1884 | |
c49d13ee | 1885 | if (dev->switch_power_state == DRM_SWITCH_POWER_OFF) |
097dd837 ID |
1886 | return 0; |
1887 | ||
c49d13ee | 1888 | return i915_drm_resume(dev); |
cbda12d7 ZW |
1889 | } |
1890 | ||
1f19ac2a | 1891 | /* freeze: before creating the hibernation_image */ |
c49d13ee | 1892 | static int i915_pm_freeze(struct device *kdev) |
1f19ac2a | 1893 | { |
6a800eab CW |
1894 | int ret; |
1895 | ||
1896 | ret = i915_pm_suspend(kdev); | |
1897 | if (ret) | |
1898 | return ret; | |
1899 | ||
1900 | ret = i915_gem_freeze(kdev_to_i915(kdev)); | |
1901 | if (ret) | |
1902 | return ret; | |
1903 | ||
1904 | return 0; | |
1f19ac2a CW |
1905 | } |
1906 | ||
c49d13ee | 1907 | static int i915_pm_freeze_late(struct device *kdev) |
1f19ac2a | 1908 | { |
461fb99c CW |
1909 | int ret; |
1910 | ||
c49d13ee | 1911 | ret = i915_pm_suspend_late(kdev); |
461fb99c CW |
1912 | if (ret) |
1913 | return ret; | |
1914 | ||
c49d13ee | 1915 | ret = i915_gem_freeze_late(kdev_to_i915(kdev)); |
461fb99c CW |
1916 | if (ret) |
1917 | return ret; | |
1918 | ||
1919 | return 0; | |
1f19ac2a CW |
1920 | } |
1921 | ||
1922 | /* thaw: called after creating the hibernation image, but before turning off. */ | |
c49d13ee | 1923 | static int i915_pm_thaw_early(struct device *kdev) |
1f19ac2a | 1924 | { |
c49d13ee | 1925 | return i915_pm_resume_early(kdev); |
1f19ac2a CW |
1926 | } |
1927 | ||
c49d13ee | 1928 | static int i915_pm_thaw(struct device *kdev) |
1f19ac2a | 1929 | { |
c49d13ee | 1930 | return i915_pm_resume(kdev); |
1f19ac2a CW |
1931 | } |
1932 | ||
1933 | /* restore: called after loading the hibernation image. */ | |
c49d13ee | 1934 | static int i915_pm_restore_early(struct device *kdev) |
1f19ac2a | 1935 | { |
c49d13ee | 1936 | return i915_pm_resume_early(kdev); |
1f19ac2a CW |
1937 | } |
1938 | ||
c49d13ee | 1939 | static int i915_pm_restore(struct device *kdev) |
1f19ac2a | 1940 | { |
c49d13ee | 1941 | return i915_pm_resume(kdev); |
1f19ac2a CW |
1942 | } |
1943 | ||
ddeea5b0 ID |
1944 | /* |
1945 | * Save all Gunit registers that may be lost after a D3 and a subsequent | |
1946 | * S0i[R123] transition. The list of registers needing a save/restore is | |
1947 | * defined in the VLV2_S0IXRegs document. This documents marks all Gunit | |
1948 | * registers in the following way: | |
1949 | * - Driver: saved/restored by the driver | |
1950 | * - Punit : saved/restored by the Punit firmware | |
1951 | * - No, w/o marking: no need to save/restore, since the register is R/O or | |
1952 | * used internally by the HW in a way that doesn't depend | |
1953 | * keeping the content across a suspend/resume. | |
1954 | * - Debug : used for debugging | |
1955 | * | |
1956 | * We save/restore all registers marked with 'Driver', with the following | |
1957 | * exceptions: | |
1958 | * - Registers out of use, including also registers marked with 'Debug'. | |
1959 | * These have no effect on the driver's operation, so we don't save/restore | |
1960 | * them to reduce the overhead. | |
1961 | * - Registers that are fully setup by an initialization function called from | |
1962 | * the resume path. For example many clock gating and RPS/RC6 registers. | |
1963 | * - Registers that provide the right functionality with their reset defaults. | |
1964 | * | |
1965 | * TODO: Except for registers that based on the above 3 criteria can be safely | |
1966 | * ignored, we save/restore all others, practically treating the HW context as | |
1967 | * a black-box for the driver. Further investigation is needed to reduce the | |
1968 | * saved/restored registers even further, by following the same 3 criteria. | |
1969 | */ | |
1970 | static void vlv_save_gunit_s0ix_state(struct drm_i915_private *dev_priv) | |
1971 | { | |
1972 | struct vlv_s0ix_state *s = &dev_priv->vlv_s0ix_state; | |
1973 | int i; | |
1974 | ||
1975 | /* GAM 0x4000-0x4770 */ | |
1976 | s->wr_watermark = I915_READ(GEN7_WR_WATERMARK); | |
1977 | s->gfx_prio_ctrl = I915_READ(GEN7_GFX_PRIO_CTRL); | |
1978 | s->arb_mode = I915_READ(ARB_MODE); | |
1979 | s->gfx_pend_tlb0 = I915_READ(GEN7_GFX_PEND_TLB0); | |
1980 | s->gfx_pend_tlb1 = I915_READ(GEN7_GFX_PEND_TLB1); | |
1981 | ||
1982 | for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++) | |
22dfe79f | 1983 | s->lra_limits[i] = I915_READ(GEN7_LRA_LIMITS(i)); |
ddeea5b0 ID |
1984 | |
1985 | s->media_max_req_count = I915_READ(GEN7_MEDIA_MAX_REQ_COUNT); | |
b5f1c97f | 1986 | s->gfx_max_req_count = I915_READ(GEN7_GFX_MAX_REQ_COUNT); |
ddeea5b0 ID |
1987 | |
1988 | s->render_hwsp = I915_READ(RENDER_HWS_PGA_GEN7); | |
1989 | s->ecochk = I915_READ(GAM_ECOCHK); | |
1990 | s->bsd_hwsp = I915_READ(BSD_HWS_PGA_GEN7); | |
1991 | s->blt_hwsp = I915_READ(BLT_HWS_PGA_GEN7); | |
1992 | ||
1993 | s->tlb_rd_addr = I915_READ(GEN7_TLB_RD_ADDR); | |
1994 | ||
1995 | /* MBC 0x9024-0x91D0, 0x8500 */ | |
1996 | s->g3dctl = I915_READ(VLV_G3DCTL); | |
1997 | s->gsckgctl = I915_READ(VLV_GSCKGCTL); | |
1998 | s->mbctl = I915_READ(GEN6_MBCTL); | |
1999 | ||
2000 | /* GCP 0x9400-0x9424, 0x8100-0x810C */ | |
2001 | s->ucgctl1 = I915_READ(GEN6_UCGCTL1); | |
2002 | s->ucgctl3 = I915_READ(GEN6_UCGCTL3); | |
2003 | s->rcgctl1 = I915_READ(GEN6_RCGCTL1); | |
2004 | s->rcgctl2 = I915_READ(GEN6_RCGCTL2); | |
2005 | s->rstctl = I915_READ(GEN6_RSTCTL); | |
2006 | s->misccpctl = I915_READ(GEN7_MISCCPCTL); | |
2007 | ||
2008 | /* GPM 0xA000-0xAA84, 0x8000-0x80FC */ | |
2009 | s->gfxpause = I915_READ(GEN6_GFXPAUSE); | |
2010 | s->rpdeuhwtc = I915_READ(GEN6_RPDEUHWTC); | |
2011 | s->rpdeuc = I915_READ(GEN6_RPDEUC); | |
2012 | s->ecobus = I915_READ(ECOBUS); | |
2013 | s->pwrdwnupctl = I915_READ(VLV_PWRDWNUPCTL); | |
2014 | s->rp_down_timeout = I915_READ(GEN6_RP_DOWN_TIMEOUT); | |
2015 | s->rp_deucsw = I915_READ(GEN6_RPDEUCSW); | |
2016 | s->rcubmabdtmr = I915_READ(GEN6_RCUBMABDTMR); | |
2017 | s->rcedata = I915_READ(VLV_RCEDATA); | |
2018 | s->spare2gh = I915_READ(VLV_SPAREG2H); | |
2019 | ||
2020 | /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */ | |
2021 | s->gt_imr = I915_READ(GTIMR); | |
2022 | s->gt_ier = I915_READ(GTIER); | |
2023 | s->pm_imr = I915_READ(GEN6_PMIMR); | |
2024 | s->pm_ier = I915_READ(GEN6_PMIER); | |
2025 | ||
2026 | for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++) | |
22dfe79f | 2027 | s->gt_scratch[i] = I915_READ(GEN7_GT_SCRATCH(i)); |
ddeea5b0 ID |
2028 | |
2029 | /* GT SA CZ domain, 0x100000-0x138124 */ | |
2030 | s->tilectl = I915_READ(TILECTL); | |
2031 | s->gt_fifoctl = I915_READ(GTFIFOCTL); | |
2032 | s->gtlc_wake_ctrl = I915_READ(VLV_GTLC_WAKE_CTRL); | |
2033 | s->gtlc_survive = I915_READ(VLV_GTLC_SURVIVABILITY_REG); | |
2034 | s->pmwgicz = I915_READ(VLV_PMWGICZ); | |
2035 | ||
2036 | /* Gunit-Display CZ domain, 0x182028-0x1821CF */ | |
2037 | s->gu_ctl0 = I915_READ(VLV_GU_CTL0); | |
2038 | s->gu_ctl1 = I915_READ(VLV_GU_CTL1); | |
9c25210f | 2039 | s->pcbr = I915_READ(VLV_PCBR); |
ddeea5b0 ID |
2040 | s->clock_gate_dis2 = I915_READ(VLV_GUNIT_CLOCK_GATE2); |
2041 | ||
2042 | /* | |
2043 | * Not saving any of: | |
2044 | * DFT, 0x9800-0x9EC0 | |
2045 | * SARB, 0xB000-0xB1FC | |
2046 | * GAC, 0x5208-0x524C, 0x14000-0x14C000 | |
2047 | * PCI CFG | |
2048 | */ | |
2049 | } | |
2050 | ||
2051 | static void vlv_restore_gunit_s0ix_state(struct drm_i915_private *dev_priv) | |
2052 | { | |
2053 | struct vlv_s0ix_state *s = &dev_priv->vlv_s0ix_state; | |
2054 | u32 val; | |
2055 | int i; | |
2056 | ||
2057 | /* GAM 0x4000-0x4770 */ | |
2058 | I915_WRITE(GEN7_WR_WATERMARK, s->wr_watermark); | |
2059 | I915_WRITE(GEN7_GFX_PRIO_CTRL, s->gfx_prio_ctrl); | |
2060 | I915_WRITE(ARB_MODE, s->arb_mode | (0xffff << 16)); | |
2061 | I915_WRITE(GEN7_GFX_PEND_TLB0, s->gfx_pend_tlb0); | |
2062 | I915_WRITE(GEN7_GFX_PEND_TLB1, s->gfx_pend_tlb1); | |
2063 | ||
2064 | for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++) | |
22dfe79f | 2065 | I915_WRITE(GEN7_LRA_LIMITS(i), s->lra_limits[i]); |
ddeea5b0 ID |
2066 | |
2067 | I915_WRITE(GEN7_MEDIA_MAX_REQ_COUNT, s->media_max_req_count); | |
b5f1c97f | 2068 | I915_WRITE(GEN7_GFX_MAX_REQ_COUNT, s->gfx_max_req_count); |
ddeea5b0 ID |
2069 | |
2070 | I915_WRITE(RENDER_HWS_PGA_GEN7, s->render_hwsp); | |
2071 | I915_WRITE(GAM_ECOCHK, s->ecochk); | |
2072 | I915_WRITE(BSD_HWS_PGA_GEN7, s->bsd_hwsp); | |
2073 | I915_WRITE(BLT_HWS_PGA_GEN7, s->blt_hwsp); | |
2074 | ||
2075 | I915_WRITE(GEN7_TLB_RD_ADDR, s->tlb_rd_addr); | |
2076 | ||
2077 | /* MBC 0x9024-0x91D0, 0x8500 */ | |
2078 | I915_WRITE(VLV_G3DCTL, s->g3dctl); | |
2079 | I915_WRITE(VLV_GSCKGCTL, s->gsckgctl); | |
2080 | I915_WRITE(GEN6_MBCTL, s->mbctl); | |
2081 | ||
2082 | /* GCP 0x9400-0x9424, 0x8100-0x810C */ | |
2083 | I915_WRITE(GEN6_UCGCTL1, s->ucgctl1); | |
2084 | I915_WRITE(GEN6_UCGCTL3, s->ucgctl3); | |
2085 | I915_WRITE(GEN6_RCGCTL1, s->rcgctl1); | |
2086 | I915_WRITE(GEN6_RCGCTL2, s->rcgctl2); | |
2087 | I915_WRITE(GEN6_RSTCTL, s->rstctl); | |
2088 | I915_WRITE(GEN7_MISCCPCTL, s->misccpctl); | |
2089 | ||
2090 | /* GPM 0xA000-0xAA84, 0x8000-0x80FC */ | |
2091 | I915_WRITE(GEN6_GFXPAUSE, s->gfxpause); | |
2092 | I915_WRITE(GEN6_RPDEUHWTC, s->rpdeuhwtc); | |
2093 | I915_WRITE(GEN6_RPDEUC, s->rpdeuc); | |
2094 | I915_WRITE(ECOBUS, s->ecobus); | |
2095 | I915_WRITE(VLV_PWRDWNUPCTL, s->pwrdwnupctl); | |
2096 | I915_WRITE(GEN6_RP_DOWN_TIMEOUT,s->rp_down_timeout); | |
2097 | I915_WRITE(GEN6_RPDEUCSW, s->rp_deucsw); | |
2098 | I915_WRITE(GEN6_RCUBMABDTMR, s->rcubmabdtmr); | |
2099 | I915_WRITE(VLV_RCEDATA, s->rcedata); | |
2100 | I915_WRITE(VLV_SPAREG2H, s->spare2gh); | |
2101 | ||
2102 | /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */ | |
2103 | I915_WRITE(GTIMR, s->gt_imr); | |
2104 | I915_WRITE(GTIER, s->gt_ier); | |
2105 | I915_WRITE(GEN6_PMIMR, s->pm_imr); | |
2106 | I915_WRITE(GEN6_PMIER, s->pm_ier); | |
2107 | ||
2108 | for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++) | |
22dfe79f | 2109 | I915_WRITE(GEN7_GT_SCRATCH(i), s->gt_scratch[i]); |
ddeea5b0 ID |
2110 | |
2111 | /* GT SA CZ domain, 0x100000-0x138124 */ | |
2112 | I915_WRITE(TILECTL, s->tilectl); | |
2113 | I915_WRITE(GTFIFOCTL, s->gt_fifoctl); | |
2114 | /* | |
2115 | * Preserve the GT allow wake and GFX force clock bit, they are not | |
2116 | * be restored, as they are used to control the s0ix suspend/resume | |
2117 | * sequence by the caller. | |
2118 | */ | |
2119 | val = I915_READ(VLV_GTLC_WAKE_CTRL); | |
2120 | val &= VLV_GTLC_ALLOWWAKEREQ; | |
2121 | val |= s->gtlc_wake_ctrl & ~VLV_GTLC_ALLOWWAKEREQ; | |
2122 | I915_WRITE(VLV_GTLC_WAKE_CTRL, val); | |
2123 | ||
2124 | val = I915_READ(VLV_GTLC_SURVIVABILITY_REG); | |
2125 | val &= VLV_GFX_CLK_FORCE_ON_BIT; | |
2126 | val |= s->gtlc_survive & ~VLV_GFX_CLK_FORCE_ON_BIT; | |
2127 | I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, val); | |
2128 | ||
2129 | I915_WRITE(VLV_PMWGICZ, s->pmwgicz); | |
2130 | ||
2131 | /* Gunit-Display CZ domain, 0x182028-0x1821CF */ | |
2132 | I915_WRITE(VLV_GU_CTL0, s->gu_ctl0); | |
2133 | I915_WRITE(VLV_GU_CTL1, s->gu_ctl1); | |
9c25210f | 2134 | I915_WRITE(VLV_PCBR, s->pcbr); |
ddeea5b0 ID |
2135 | I915_WRITE(VLV_GUNIT_CLOCK_GATE2, s->clock_gate_dis2); |
2136 | } | |
2137 | ||
650ad970 ID |
2138 | int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool force_on) |
2139 | { | |
2140 | u32 val; | |
2141 | int err; | |
2142 | ||
650ad970 ID |
2143 | val = I915_READ(VLV_GTLC_SURVIVABILITY_REG); |
2144 | val &= ~VLV_GFX_CLK_FORCE_ON_BIT; | |
2145 | if (force_on) | |
2146 | val |= VLV_GFX_CLK_FORCE_ON_BIT; | |
2147 | I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, val); | |
2148 | ||
2149 | if (!force_on) | |
2150 | return 0; | |
2151 | ||
c6ddc5f3 CW |
2152 | err = intel_wait_for_register(dev_priv, |
2153 | VLV_GTLC_SURVIVABILITY_REG, | |
2154 | VLV_GFX_CLK_STATUS_BIT, | |
2155 | VLV_GFX_CLK_STATUS_BIT, | |
2156 | 20); | |
650ad970 ID |
2157 | if (err) |
2158 | DRM_ERROR("timeout waiting for GFX clock force-on (%08x)\n", | |
2159 | I915_READ(VLV_GTLC_SURVIVABILITY_REG)); | |
2160 | ||
2161 | return err; | |
650ad970 ID |
2162 | } |
2163 | ||
ddeea5b0 ID |
2164 | static int vlv_allow_gt_wake(struct drm_i915_private *dev_priv, bool allow) |
2165 | { | |
2166 | u32 val; | |
2167 | int err = 0; | |
2168 | ||
2169 | val = I915_READ(VLV_GTLC_WAKE_CTRL); | |
2170 | val &= ~VLV_GTLC_ALLOWWAKEREQ; | |
2171 | if (allow) | |
2172 | val |= VLV_GTLC_ALLOWWAKEREQ; | |
2173 | I915_WRITE(VLV_GTLC_WAKE_CTRL, val); | |
2174 | POSTING_READ(VLV_GTLC_WAKE_CTRL); | |
2175 | ||
b2736695 CW |
2176 | err = intel_wait_for_register(dev_priv, |
2177 | VLV_GTLC_PW_STATUS, | |
2178 | VLV_GTLC_ALLOWWAKEACK, | |
2179 | allow, | |
2180 | 1); | |
ddeea5b0 ID |
2181 | if (err) |
2182 | DRM_ERROR("timeout disabling GT waking\n"); | |
b2736695 | 2183 | |
ddeea5b0 | 2184 | return err; |
ddeea5b0 ID |
2185 | } |
2186 | ||
2187 | static int vlv_wait_for_gt_wells(struct drm_i915_private *dev_priv, | |
2188 | bool wait_for_on) | |
2189 | { | |
2190 | u32 mask; | |
2191 | u32 val; | |
2192 | int err; | |
2193 | ||
2194 | mask = VLV_GTLC_PW_MEDIA_STATUS_MASK | VLV_GTLC_PW_RENDER_STATUS_MASK; | |
2195 | val = wait_for_on ? mask : 0; | |
41ce405e | 2196 | if ((I915_READ(VLV_GTLC_PW_STATUS) & mask) == val) |
ddeea5b0 ID |
2197 | return 0; |
2198 | ||
2199 | DRM_DEBUG_KMS("waiting for GT wells to go %s (%08x)\n", | |
87ad3212 JN |
2200 | onoff(wait_for_on), |
2201 | I915_READ(VLV_GTLC_PW_STATUS)); | |
ddeea5b0 ID |
2202 | |
2203 | /* | |
2204 | * RC6 transitioning can be delayed up to 2 msec (see | |
2205 | * valleyview_enable_rps), use 3 msec for safety. | |
2206 | */ | |
41ce405e CW |
2207 | err = intel_wait_for_register(dev_priv, |
2208 | VLV_GTLC_PW_STATUS, mask, val, | |
2209 | 3); | |
ddeea5b0 ID |
2210 | if (err) |
2211 | DRM_ERROR("timeout waiting for GT wells to go %s\n", | |
87ad3212 | 2212 | onoff(wait_for_on)); |
ddeea5b0 ID |
2213 | |
2214 | return err; | |
ddeea5b0 ID |
2215 | } |
2216 | ||
2217 | static void vlv_check_no_gt_access(struct drm_i915_private *dev_priv) | |
2218 | { | |
2219 | if (!(I915_READ(VLV_GTLC_PW_STATUS) & VLV_GTLC_ALLOWWAKEERR)) | |
2220 | return; | |
2221 | ||
6fa283b0 | 2222 | DRM_DEBUG_DRIVER("GT register access while GT waking disabled\n"); |
ddeea5b0 ID |
2223 | I915_WRITE(VLV_GTLC_PW_STATUS, VLV_GTLC_ALLOWWAKEERR); |
2224 | } | |
2225 | ||
ebc32824 | 2226 | static int vlv_suspend_complete(struct drm_i915_private *dev_priv) |
ddeea5b0 ID |
2227 | { |
2228 | u32 mask; | |
2229 | int err; | |
2230 | ||
2231 | /* | |
2232 | * Bspec defines the following GT well on flags as debug only, so | |
2233 | * don't treat them as hard failures. | |
2234 | */ | |
2235 | (void)vlv_wait_for_gt_wells(dev_priv, false); | |
2236 | ||
2237 | mask = VLV_GTLC_RENDER_CTX_EXISTS | VLV_GTLC_MEDIA_CTX_EXISTS; | |
2238 | WARN_ON((I915_READ(VLV_GTLC_WAKE_CTRL) & mask) != mask); | |
2239 | ||
2240 | vlv_check_no_gt_access(dev_priv); | |
2241 | ||
2242 | err = vlv_force_gfx_clock(dev_priv, true); | |
2243 | if (err) | |
2244 | goto err1; | |
2245 | ||
2246 | err = vlv_allow_gt_wake(dev_priv, false); | |
2247 | if (err) | |
2248 | goto err2; | |
98711167 | 2249 | |
2d1fe073 | 2250 | if (!IS_CHERRYVIEW(dev_priv)) |
98711167 | 2251 | vlv_save_gunit_s0ix_state(dev_priv); |
ddeea5b0 ID |
2252 | |
2253 | err = vlv_force_gfx_clock(dev_priv, false); | |
2254 | if (err) | |
2255 | goto err2; | |
2256 | ||
2257 | return 0; | |
2258 | ||
2259 | err2: | |
2260 | /* For safety always re-enable waking and disable gfx clock forcing */ | |
2261 | vlv_allow_gt_wake(dev_priv, true); | |
2262 | err1: | |
2263 | vlv_force_gfx_clock(dev_priv, false); | |
2264 | ||
2265 | return err; | |
2266 | } | |
2267 | ||
016970be SK |
2268 | static int vlv_resume_prepare(struct drm_i915_private *dev_priv, |
2269 | bool rpm_resume) | |
ddeea5b0 | 2270 | { |
ddeea5b0 ID |
2271 | int err; |
2272 | int ret; | |
2273 | ||
2274 | /* | |
2275 | * If any of the steps fail just try to continue, that's the best we | |
2276 | * can do at this point. Return the first error code (which will also | |
2277 | * leave RPM permanently disabled). | |
2278 | */ | |
2279 | ret = vlv_force_gfx_clock(dev_priv, true); | |
2280 | ||
2d1fe073 | 2281 | if (!IS_CHERRYVIEW(dev_priv)) |
98711167 | 2282 | vlv_restore_gunit_s0ix_state(dev_priv); |
ddeea5b0 ID |
2283 | |
2284 | err = vlv_allow_gt_wake(dev_priv, true); | |
2285 | if (!ret) | |
2286 | ret = err; | |
2287 | ||
2288 | err = vlv_force_gfx_clock(dev_priv, false); | |
2289 | if (!ret) | |
2290 | ret = err; | |
2291 | ||
2292 | vlv_check_no_gt_access(dev_priv); | |
2293 | ||
7c108fd8 | 2294 | if (rpm_resume) |
46f16e63 | 2295 | intel_init_clock_gating(dev_priv); |
ddeea5b0 ID |
2296 | |
2297 | return ret; | |
2298 | } | |
2299 | ||
c49d13ee | 2300 | static int intel_runtime_suspend(struct device *kdev) |
8a187455 | 2301 | { |
c49d13ee | 2302 | struct pci_dev *pdev = to_pci_dev(kdev); |
8a187455 | 2303 | struct drm_device *dev = pci_get_drvdata(pdev); |
fac5e23e | 2304 | struct drm_i915_private *dev_priv = to_i915(dev); |
0ab9cfeb | 2305 | int ret; |
8a187455 | 2306 | |
dc97997a | 2307 | if (WARN_ON_ONCE(!(dev_priv->rps.enabled && intel_enable_rc6()))) |
c6df39b5 ID |
2308 | return -ENODEV; |
2309 | ||
6772ffe0 | 2310 | if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev_priv))) |
604effb7 ID |
2311 | return -ENODEV; |
2312 | ||
8a187455 PZ |
2313 | DRM_DEBUG_KMS("Suspending device\n"); |
2314 | ||
1f814dac ID |
2315 | disable_rpm_wakeref_asserts(dev_priv); |
2316 | ||
d6102977 ID |
2317 | /* |
2318 | * We are safe here against re-faults, since the fault handler takes | |
2319 | * an RPM reference. | |
2320 | */ | |
7c108fd8 | 2321 | i915_gem_runtime_suspend(dev_priv); |
d6102977 | 2322 | |
a1c41994 AD |
2323 | intel_guc_suspend(dev); |
2324 | ||
2eb5252e | 2325 | intel_runtime_pm_disable_interrupts(dev_priv); |
b5478bcd | 2326 | |
507e126e ID |
2327 | ret = 0; |
2328 | if (IS_BROXTON(dev_priv)) { | |
2329 | bxt_display_core_uninit(dev_priv); | |
2330 | bxt_enable_dc9(dev_priv); | |
2331 | } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) { | |
2332 | hsw_enable_pc8(dev_priv); | |
2333 | } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { | |
2334 | ret = vlv_suspend_complete(dev_priv); | |
2335 | } | |
2336 | ||
0ab9cfeb ID |
2337 | if (ret) { |
2338 | DRM_ERROR("Runtime suspend failed, disabling it (%d)\n", ret); | |
b963291c | 2339 | intel_runtime_pm_enable_interrupts(dev_priv); |
0ab9cfeb | 2340 | |
1f814dac ID |
2341 | enable_rpm_wakeref_asserts(dev_priv); |
2342 | ||
0ab9cfeb ID |
2343 | return ret; |
2344 | } | |
a8a8bd54 | 2345 | |
dc97997a | 2346 | intel_uncore_forcewake_reset(dev_priv, false); |
1f814dac ID |
2347 | |
2348 | enable_rpm_wakeref_asserts(dev_priv); | |
2349 | WARN_ON_ONCE(atomic_read(&dev_priv->pm.wakeref_count)); | |
55ec45c2 | 2350 | |
bc3b9346 | 2351 | if (intel_uncore_arm_unclaimed_mmio_detection(dev_priv)) |
55ec45c2 MK |
2352 | DRM_ERROR("Unclaimed access detected prior to suspending\n"); |
2353 | ||
8a187455 | 2354 | dev_priv->pm.suspended = true; |
1fb2362b KCA |
2355 | |
2356 | /* | |
c8a0bd42 PZ |
2357 | * FIXME: We really should find a document that references the arguments |
2358 | * used below! | |
1fb2362b | 2359 | */ |
6f9f4b7a | 2360 | if (IS_BROADWELL(dev_priv)) { |
d37ae19a PZ |
2361 | /* |
2362 | * On Broadwell, if we use PCI_D1 the PCH DDI ports will stop | |
2363 | * being detected, and the call we do at intel_runtime_resume() | |
2364 | * won't be able to restore them. Since PCI_D3hot matches the | |
2365 | * actual specification and appears to be working, use it. | |
2366 | */ | |
6f9f4b7a | 2367 | intel_opregion_notify_adapter(dev_priv, PCI_D3hot); |
d37ae19a | 2368 | } else { |
c8a0bd42 PZ |
2369 | /* |
2370 | * current versions of firmware which depend on this opregion | |
2371 | * notification have repurposed the D1 definition to mean | |
2372 | * "runtime suspended" vs. what you would normally expect (D3) | |
2373 | * to distinguish it from notifications that might be sent via | |
2374 | * the suspend path. | |
2375 | */ | |
6f9f4b7a | 2376 | intel_opregion_notify_adapter(dev_priv, PCI_D1); |
c8a0bd42 | 2377 | } |
8a187455 | 2378 | |
59bad947 | 2379 | assert_forcewakes_inactive(dev_priv); |
dc9fb09c | 2380 | |
19625e85 L |
2381 | if (!IS_VALLEYVIEW(dev_priv) || !IS_CHERRYVIEW(dev_priv)) |
2382 | intel_hpd_poll_init(dev_priv); | |
2383 | ||
a8a8bd54 | 2384 | DRM_DEBUG_KMS("Device suspended\n"); |
8a187455 PZ |
2385 | return 0; |
2386 | } | |
2387 | ||
c49d13ee | 2388 | static int intel_runtime_resume(struct device *kdev) |
8a187455 | 2389 | { |
c49d13ee | 2390 | struct pci_dev *pdev = to_pci_dev(kdev); |
8a187455 | 2391 | struct drm_device *dev = pci_get_drvdata(pdev); |
fac5e23e | 2392 | struct drm_i915_private *dev_priv = to_i915(dev); |
1a5df187 | 2393 | int ret = 0; |
8a187455 | 2394 | |
6772ffe0 | 2395 | if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev_priv))) |
604effb7 | 2396 | return -ENODEV; |
8a187455 PZ |
2397 | |
2398 | DRM_DEBUG_KMS("Resuming device\n"); | |
2399 | ||
1f814dac ID |
2400 | WARN_ON_ONCE(atomic_read(&dev_priv->pm.wakeref_count)); |
2401 | disable_rpm_wakeref_asserts(dev_priv); | |
2402 | ||
6f9f4b7a | 2403 | intel_opregion_notify_adapter(dev_priv, PCI_D0); |
8a187455 | 2404 | dev_priv->pm.suspended = false; |
55ec45c2 MK |
2405 | if (intel_uncore_unclaimed_mmio(dev_priv)) |
2406 | DRM_DEBUG_DRIVER("Unclaimed access during suspend, bios?\n"); | |
8a187455 | 2407 | |
a1c41994 AD |
2408 | intel_guc_resume(dev); |
2409 | ||
1a5df187 PZ |
2410 | if (IS_GEN6(dev_priv)) |
2411 | intel_init_pch_refclk(dev); | |
31335cec | 2412 | |
e2d214ae | 2413 | if (IS_BROXTON(dev_priv)) { |
507e126e ID |
2414 | bxt_disable_dc9(dev_priv); |
2415 | bxt_display_core_init(dev_priv, true); | |
f62c79b3 ID |
2416 | if (dev_priv->csr.dmc_payload && |
2417 | (dev_priv->csr.allowed_dc_mask & DC_STATE_EN_UPTO_DC5)) | |
2418 | gen9_enable_dc5(dev_priv); | |
507e126e | 2419 | } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) { |
1a5df187 | 2420 | hsw_disable_pc8(dev_priv); |
507e126e | 2421 | } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { |
1a5df187 | 2422 | ret = vlv_resume_prepare(dev_priv, true); |
507e126e | 2423 | } |
1a5df187 | 2424 | |
0ab9cfeb ID |
2425 | /* |
2426 | * No point of rolling back things in case of an error, as the best | |
2427 | * we can do is to hope that things will still work (and disable RPM). | |
2428 | */ | |
92b806d3 | 2429 | i915_gem_init_swizzling(dev); |
92b806d3 | 2430 | |
b963291c | 2431 | intel_runtime_pm_enable_interrupts(dev_priv); |
08d8a232 VS |
2432 | |
2433 | /* | |
2434 | * On VLV/CHV display interrupts are part of the display | |
2435 | * power well, so hpd is reinitialized from there. For | |
2436 | * everyone else do it here. | |
2437 | */ | |
666a4537 | 2438 | if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) |
08d8a232 VS |
2439 | intel_hpd_init(dev_priv); |
2440 | ||
1f814dac ID |
2441 | enable_rpm_wakeref_asserts(dev_priv); |
2442 | ||
0ab9cfeb ID |
2443 | if (ret) |
2444 | DRM_ERROR("Runtime resume failed, disabling it (%d)\n", ret); | |
2445 | else | |
2446 | DRM_DEBUG_KMS("Device resumed\n"); | |
2447 | ||
2448 | return ret; | |
8a187455 PZ |
2449 | } |
2450 | ||
42f5551d | 2451 | const struct dev_pm_ops i915_pm_ops = { |
5545dbbf ID |
2452 | /* |
2453 | * S0ix (via system suspend) and S3 event handlers [PMSG_SUSPEND, | |
2454 | * PMSG_RESUME] | |
2455 | */ | |
0206e353 | 2456 | .suspend = i915_pm_suspend, |
76c4b250 ID |
2457 | .suspend_late = i915_pm_suspend_late, |
2458 | .resume_early = i915_pm_resume_early, | |
0206e353 | 2459 | .resume = i915_pm_resume, |
5545dbbf ID |
2460 | |
2461 | /* | |
2462 | * S4 event handlers | |
2463 | * @freeze, @freeze_late : called (1) before creating the | |
2464 | * hibernation image [PMSG_FREEZE] and | |
2465 | * (2) after rebooting, before restoring | |
2466 | * the image [PMSG_QUIESCE] | |
2467 | * @thaw, @thaw_early : called (1) after creating the hibernation | |
2468 | * image, before writing it [PMSG_THAW] | |
2469 | * and (2) after failing to create or | |
2470 | * restore the image [PMSG_RECOVER] | |
2471 | * @poweroff, @poweroff_late: called after writing the hibernation | |
2472 | * image, before rebooting [PMSG_HIBERNATE] | |
2473 | * @restore, @restore_early : called after rebooting and restoring the | |
2474 | * hibernation image [PMSG_RESTORE] | |
2475 | */ | |
1f19ac2a CW |
2476 | .freeze = i915_pm_freeze, |
2477 | .freeze_late = i915_pm_freeze_late, | |
2478 | .thaw_early = i915_pm_thaw_early, | |
2479 | .thaw = i915_pm_thaw, | |
36d61e67 | 2480 | .poweroff = i915_pm_suspend, |
ab3be73f | 2481 | .poweroff_late = i915_pm_poweroff_late, |
1f19ac2a CW |
2482 | .restore_early = i915_pm_restore_early, |
2483 | .restore = i915_pm_restore, | |
5545dbbf ID |
2484 | |
2485 | /* S0ix (via runtime suspend) event handlers */ | |
97bea207 PZ |
2486 | .runtime_suspend = intel_runtime_suspend, |
2487 | .runtime_resume = intel_runtime_resume, | |
cbda12d7 ZW |
2488 | }; |
2489 | ||
78b68556 | 2490 | static const struct vm_operations_struct i915_gem_vm_ops = { |
de151cf6 | 2491 | .fault = i915_gem_fault, |
ab00b3e5 JB |
2492 | .open = drm_gem_vm_open, |
2493 | .close = drm_gem_vm_close, | |
de151cf6 JB |
2494 | }; |
2495 | ||
e08e96de AV |
2496 | static const struct file_operations i915_driver_fops = { |
2497 | .owner = THIS_MODULE, | |
2498 | .open = drm_open, | |
2499 | .release = drm_release, | |
2500 | .unlocked_ioctl = drm_ioctl, | |
2501 | .mmap = drm_gem_mmap, | |
2502 | .poll = drm_poll, | |
e08e96de | 2503 | .read = drm_read, |
e08e96de | 2504 | .compat_ioctl = i915_compat_ioctl, |
e08e96de AV |
2505 | .llseek = noop_llseek, |
2506 | }; | |
2507 | ||
0673ad47 CW |
2508 | static int |
2509 | i915_gem_reject_pin_ioctl(struct drm_device *dev, void *data, | |
2510 | struct drm_file *file) | |
2511 | { | |
2512 | return -ENODEV; | |
2513 | } | |
2514 | ||
2515 | static const struct drm_ioctl_desc i915_ioctls[] = { | |
2516 | DRM_IOCTL_DEF_DRV(I915_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), | |
2517 | DRM_IOCTL_DEF_DRV(I915_FLUSH, drm_noop, DRM_AUTH), | |
2518 | DRM_IOCTL_DEF_DRV(I915_FLIP, drm_noop, DRM_AUTH), | |
2519 | DRM_IOCTL_DEF_DRV(I915_BATCHBUFFER, drm_noop, DRM_AUTH), | |
2520 | DRM_IOCTL_DEF_DRV(I915_IRQ_EMIT, drm_noop, DRM_AUTH), | |
2521 | DRM_IOCTL_DEF_DRV(I915_IRQ_WAIT, drm_noop, DRM_AUTH), | |
2522 | DRM_IOCTL_DEF_DRV(I915_GETPARAM, i915_getparam, DRM_AUTH|DRM_RENDER_ALLOW), | |
2523 | DRM_IOCTL_DEF_DRV(I915_SETPARAM, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), | |
2524 | DRM_IOCTL_DEF_DRV(I915_ALLOC, drm_noop, DRM_AUTH), | |
2525 | DRM_IOCTL_DEF_DRV(I915_FREE, drm_noop, DRM_AUTH), | |
2526 | DRM_IOCTL_DEF_DRV(I915_INIT_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), | |
2527 | DRM_IOCTL_DEF_DRV(I915_CMDBUFFER, drm_noop, DRM_AUTH), | |
2528 | DRM_IOCTL_DEF_DRV(I915_DESTROY_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), | |
2529 | DRM_IOCTL_DEF_DRV(I915_SET_VBLANK_PIPE, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), | |
2530 | DRM_IOCTL_DEF_DRV(I915_GET_VBLANK_PIPE, drm_noop, DRM_AUTH), | |
2531 | DRM_IOCTL_DEF_DRV(I915_VBLANK_SWAP, drm_noop, DRM_AUTH), | |
2532 | DRM_IOCTL_DEF_DRV(I915_HWS_ADDR, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), | |
2533 | DRM_IOCTL_DEF_DRV(I915_GEM_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), | |
2534 | DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER, i915_gem_execbuffer, DRM_AUTH), | |
2535 | DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER2, i915_gem_execbuffer2, DRM_AUTH|DRM_RENDER_ALLOW), | |
2536 | DRM_IOCTL_DEF_DRV(I915_GEM_PIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY), | |
2537 | DRM_IOCTL_DEF_DRV(I915_GEM_UNPIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY), | |
2538 | DRM_IOCTL_DEF_DRV(I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), | |
2539 | DRM_IOCTL_DEF_DRV(I915_GEM_SET_CACHING, i915_gem_set_caching_ioctl, DRM_RENDER_ALLOW), | |
2540 | DRM_IOCTL_DEF_DRV(I915_GEM_GET_CACHING, i915_gem_get_caching_ioctl, DRM_RENDER_ALLOW), | |
2541 | DRM_IOCTL_DEF_DRV(I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), | |
2542 | DRM_IOCTL_DEF_DRV(I915_GEM_ENTERVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), | |
2543 | DRM_IOCTL_DEF_DRV(I915_GEM_LEAVEVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), | |
2544 | DRM_IOCTL_DEF_DRV(I915_GEM_CREATE, i915_gem_create_ioctl, DRM_RENDER_ALLOW), | |
2545 | DRM_IOCTL_DEF_DRV(I915_GEM_PREAD, i915_gem_pread_ioctl, DRM_RENDER_ALLOW), | |
2546 | DRM_IOCTL_DEF_DRV(I915_GEM_PWRITE, i915_gem_pwrite_ioctl, DRM_RENDER_ALLOW), | |
2547 | DRM_IOCTL_DEF_DRV(I915_GEM_MMAP, i915_gem_mmap_ioctl, DRM_RENDER_ALLOW), | |
2548 | DRM_IOCTL_DEF_DRV(I915_GEM_MMAP_GTT, i915_gem_mmap_gtt_ioctl, DRM_RENDER_ALLOW), | |
2549 | DRM_IOCTL_DEF_DRV(I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, DRM_RENDER_ALLOW), | |
2550 | DRM_IOCTL_DEF_DRV(I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, DRM_RENDER_ALLOW), | |
2551 | DRM_IOCTL_DEF_DRV(I915_GEM_SET_TILING, i915_gem_set_tiling, DRM_RENDER_ALLOW), | |
2552 | DRM_IOCTL_DEF_DRV(I915_GEM_GET_TILING, i915_gem_get_tiling, DRM_RENDER_ALLOW), | |
2553 | DRM_IOCTL_DEF_DRV(I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, DRM_RENDER_ALLOW), | |
2554 | DRM_IOCTL_DEF_DRV(I915_GET_PIPE_FROM_CRTC_ID, intel_get_pipe_from_crtc_id, 0), | |
2555 | DRM_IOCTL_DEF_DRV(I915_GEM_MADVISE, i915_gem_madvise_ioctl, DRM_RENDER_ALLOW), | |
2556 | DRM_IOCTL_DEF_DRV(I915_OVERLAY_PUT_IMAGE, intel_overlay_put_image_ioctl, DRM_MASTER|DRM_CONTROL_ALLOW), | |
2557 | DRM_IOCTL_DEF_DRV(I915_OVERLAY_ATTRS, intel_overlay_attrs_ioctl, DRM_MASTER|DRM_CONTROL_ALLOW), | |
2558 | DRM_IOCTL_DEF_DRV(I915_SET_SPRITE_COLORKEY, intel_sprite_set_colorkey, DRM_MASTER|DRM_CONTROL_ALLOW), | |
2559 | DRM_IOCTL_DEF_DRV(I915_GET_SPRITE_COLORKEY, drm_noop, DRM_MASTER|DRM_CONTROL_ALLOW), | |
2560 | DRM_IOCTL_DEF_DRV(I915_GEM_WAIT, i915_gem_wait_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), | |
2561 | DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_CREATE, i915_gem_context_create_ioctl, DRM_RENDER_ALLOW), | |
2562 | DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_DESTROY, i915_gem_context_destroy_ioctl, DRM_RENDER_ALLOW), | |
2563 | DRM_IOCTL_DEF_DRV(I915_REG_READ, i915_reg_read_ioctl, DRM_RENDER_ALLOW), | |
2564 | DRM_IOCTL_DEF_DRV(I915_GET_RESET_STATS, i915_gem_context_reset_stats_ioctl, DRM_RENDER_ALLOW), | |
2565 | DRM_IOCTL_DEF_DRV(I915_GEM_USERPTR, i915_gem_userptr_ioctl, DRM_RENDER_ALLOW), | |
2566 | DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_GETPARAM, i915_gem_context_getparam_ioctl, DRM_RENDER_ALLOW), | |
2567 | DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_SETPARAM, i915_gem_context_setparam_ioctl, DRM_RENDER_ALLOW), | |
2568 | }; | |
2569 | ||
1da177e4 | 2570 | static struct drm_driver driver = { |
0c54781b MW |
2571 | /* Don't use MTRRs here; the Xserver or userspace app should |
2572 | * deal with them for Intel hardware. | |
792d2b9a | 2573 | */ |
673a394b | 2574 | .driver_features = |
10ba5012 | 2575 | DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM | DRIVER_PRIME | |
1751fcf9 | 2576 | DRIVER_RENDER | DRIVER_MODESET, |
673a394b | 2577 | .open = i915_driver_open, |
22eae947 DA |
2578 | .lastclose = i915_driver_lastclose, |
2579 | .preclose = i915_driver_preclose, | |
673a394b | 2580 | .postclose = i915_driver_postclose, |
915b4d11 | 2581 | .set_busid = drm_pci_set_busid, |
d8e29209 | 2582 | |
b1f788c6 | 2583 | .gem_close_object = i915_gem_close_object, |
f0cd5182 | 2584 | .gem_free_object_unlocked = i915_gem_free_object, |
de151cf6 | 2585 | .gem_vm_ops = &i915_gem_vm_ops, |
1286ff73 DV |
2586 | |
2587 | .prime_handle_to_fd = drm_gem_prime_handle_to_fd, | |
2588 | .prime_fd_to_handle = drm_gem_prime_fd_to_handle, | |
2589 | .gem_prime_export = i915_gem_prime_export, | |
2590 | .gem_prime_import = i915_gem_prime_import, | |
2591 | ||
ff72145b | 2592 | .dumb_create = i915_gem_dumb_create, |
da6b51d0 | 2593 | .dumb_map_offset = i915_gem_mmap_gtt, |
43387b37 | 2594 | .dumb_destroy = drm_gem_dumb_destroy, |
1da177e4 | 2595 | .ioctls = i915_ioctls, |
0673ad47 | 2596 | .num_ioctls = ARRAY_SIZE(i915_ioctls), |
e08e96de | 2597 | .fops = &i915_driver_fops, |
22eae947 DA |
2598 | .name = DRIVER_NAME, |
2599 | .desc = DRIVER_DESC, | |
2600 | .date = DRIVER_DATE, | |
2601 | .major = DRIVER_MAJOR, | |
2602 | .minor = DRIVER_MINOR, | |
2603 | .patchlevel = DRIVER_PATCHLEVEL, | |
1da177e4 | 2604 | }; |