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1da177e4 LT |
1 | /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*- |
2 | */ | |
0d6aa60b | 3 | /* |
bc54fd1a | 4 | * |
1da177e4 LT |
5 | * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. |
6 | * All Rights Reserved. | |
bc54fd1a DA |
7 | * |
8 | * Permission is hereby granted, free of charge, to any person obtaining a | |
9 | * copy of this software and associated documentation files (the | |
10 | * "Software"), to deal in the Software without restriction, including | |
11 | * without limitation the rights to use, copy, modify, merge, publish, | |
12 | * distribute, sub license, and/or sell copies of the Software, and to | |
13 | * permit persons to whom the Software is furnished to do so, subject to | |
14 | * the following conditions: | |
15 | * | |
16 | * The above copyright notice and this permission notice (including the | |
17 | * next paragraph) shall be included in all copies or substantial portions | |
18 | * of the Software. | |
19 | * | |
20 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS | |
21 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
22 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. | |
23 | * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR | |
24 | * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, | |
25 | * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE | |
26 | * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. | |
27 | * | |
0d6aa60b | 28 | */ |
1da177e4 LT |
29 | |
30 | #ifndef _I915_DRV_H_ | |
31 | #define _I915_DRV_H_ | |
32 | ||
e9b73c67 CW |
33 | #include <uapi/drm/i915_drm.h> |
34 | ||
585fb111 | 35 | #include "i915_reg.h" |
79e53945 | 36 | #include "intel_bios.h" |
8187a2b7 | 37 | #include "intel_ringbuffer.h" |
0839ccb8 | 38 | #include <linux/io-mapping.h> |
f899fc64 | 39 | #include <linux/i2c.h> |
c167a6fc | 40 | #include <linux/i2c-algo-bit.h> |
0ade6386 | 41 | #include <drm/intel-gtt.h> |
aaa6fd2a | 42 | #include <linux/backlight.h> |
2911a35b | 43 | #include <linux/intel-iommu.h> |
742cbee8 | 44 | #include <linux/kref.h> |
9ee32fea | 45 | #include <linux/pm_qos.h> |
585fb111 | 46 | |
1da177e4 LT |
47 | /* General customization: |
48 | */ | |
49 | ||
50 | #define DRIVER_AUTHOR "Tungsten Graphics, Inc." | |
51 | ||
52 | #define DRIVER_NAME "i915" | |
53 | #define DRIVER_DESC "Intel Graphics" | |
673a394b | 54 | #define DRIVER_DATE "20080730" |
1da177e4 | 55 | |
317c35d1 JB |
56 | enum pipe { |
57 | PIPE_A = 0, | |
58 | PIPE_B, | |
9db4a9c7 JB |
59 | PIPE_C, |
60 | I915_MAX_PIPES | |
317c35d1 | 61 | }; |
9db4a9c7 | 62 | #define pipe_name(p) ((p) + 'A') |
317c35d1 | 63 | |
a5c961d1 PZ |
64 | enum transcoder { |
65 | TRANSCODER_A = 0, | |
66 | TRANSCODER_B, | |
67 | TRANSCODER_C, | |
68 | TRANSCODER_EDP = 0xF, | |
69 | }; | |
70 | #define transcoder_name(t) ((t) + 'A') | |
71 | ||
80824003 JB |
72 | enum plane { |
73 | PLANE_A = 0, | |
74 | PLANE_B, | |
9db4a9c7 | 75 | PLANE_C, |
80824003 | 76 | }; |
9db4a9c7 | 77 | #define plane_name(p) ((p) + 'A') |
52440211 | 78 | |
06da8da2 VS |
79 | #define sprite_name(p, s) ((p) * dev_priv->num_plane + (s) + 'A') |
80 | ||
2b139522 ED |
81 | enum port { |
82 | PORT_A = 0, | |
83 | PORT_B, | |
84 | PORT_C, | |
85 | PORT_D, | |
86 | PORT_E, | |
87 | I915_MAX_PORTS | |
88 | }; | |
89 | #define port_name(p) ((p) + 'A') | |
90 | ||
1d843f9d EE |
91 | enum hpd_pin { |
92 | HPD_NONE = 0, | |
93 | HPD_PORT_A = HPD_NONE, /* PORT_A is internal */ | |
94 | HPD_TV = HPD_NONE, /* TV is known to be unreliable */ | |
95 | HPD_CRT, | |
96 | HPD_SDVO_B, | |
97 | HPD_SDVO_C, | |
98 | HPD_PORT_B, | |
99 | HPD_PORT_C, | |
100 | HPD_PORT_D, | |
101 | HPD_NUM_PINS | |
102 | }; | |
103 | ||
2a2d5482 CW |
104 | #define I915_GEM_GPU_DOMAINS \ |
105 | (I915_GEM_DOMAIN_RENDER | \ | |
106 | I915_GEM_DOMAIN_SAMPLER | \ | |
107 | I915_GEM_DOMAIN_COMMAND | \ | |
108 | I915_GEM_DOMAIN_INSTRUCTION | \ | |
109 | I915_GEM_DOMAIN_VERTEX) | |
62fdfeaf | 110 | |
7eb552ae | 111 | #define for_each_pipe(p) for ((p) = 0; (p) < INTEL_INFO(dev)->num_pipes; (p)++) |
9db4a9c7 | 112 | |
6c2b7c12 DV |
113 | #define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \ |
114 | list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \ | |
115 | if ((intel_encoder)->base.crtc == (__crtc)) | |
116 | ||
ee7b9f93 JB |
117 | struct intel_pch_pll { |
118 | int refcount; /* count of number of CRTCs sharing this PLL */ | |
119 | int active; /* count of number of active CRTCs (i.e. DPMS on) */ | |
120 | bool on; /* is the PLL actually active? Disabled during modeset */ | |
121 | int pll_reg; | |
122 | int fp0_reg; | |
123 | int fp1_reg; | |
124 | }; | |
125 | #define I915_NUM_PLLS 2 | |
126 | ||
e69d0bc1 DV |
127 | /* Used by dp and fdi links */ |
128 | struct intel_link_m_n { | |
129 | uint32_t tu; | |
130 | uint32_t gmch_m; | |
131 | uint32_t gmch_n; | |
132 | uint32_t link_m; | |
133 | uint32_t link_n; | |
134 | }; | |
135 | ||
136 | void intel_link_compute_m_n(int bpp, int nlanes, | |
137 | int pixel_clock, int link_clock, | |
138 | struct intel_link_m_n *m_n); | |
139 | ||
6441ab5f PZ |
140 | struct intel_ddi_plls { |
141 | int spll_refcount; | |
142 | int wrpll1_refcount; | |
143 | int wrpll2_refcount; | |
144 | }; | |
145 | ||
1da177e4 LT |
146 | /* Interface history: |
147 | * | |
148 | * 1.1: Original. | |
0d6aa60b DA |
149 | * 1.2: Add Power Management |
150 | * 1.3: Add vblank support | |
de227f5f | 151 | * 1.4: Fix cmdbuffer path, add heap destroy |
702880f2 | 152 | * 1.5: Add vblank pipe configuration |
2228ed67 MD |
153 | * 1.6: - New ioctl for scheduling buffer swaps on vertical blank |
154 | * - Support vertical blank on secondary display pipe | |
1da177e4 LT |
155 | */ |
156 | #define DRIVER_MAJOR 1 | |
2228ed67 | 157 | #define DRIVER_MINOR 6 |
1da177e4 LT |
158 | #define DRIVER_PATCHLEVEL 0 |
159 | ||
673a394b | 160 | #define WATCH_COHERENCY 0 |
23bc5982 | 161 | #define WATCH_LISTS 0 |
42d6ab48 | 162 | #define WATCH_GTT 0 |
673a394b | 163 | |
71acb5eb DA |
164 | #define I915_GEM_PHYS_CURSOR_0 1 |
165 | #define I915_GEM_PHYS_CURSOR_1 2 | |
166 | #define I915_GEM_PHYS_OVERLAY_REGS 3 | |
167 | #define I915_MAX_PHYS_OBJECT (I915_GEM_PHYS_OVERLAY_REGS) | |
168 | ||
169 | struct drm_i915_gem_phys_object { | |
170 | int id; | |
171 | struct page **page_list; | |
172 | drm_dma_handle_t *handle; | |
05394f39 | 173 | struct drm_i915_gem_object *cur_obj; |
71acb5eb DA |
174 | }; |
175 | ||
0a3e67a4 JB |
176 | struct opregion_header; |
177 | struct opregion_acpi; | |
178 | struct opregion_swsci; | |
179 | struct opregion_asle; | |
8d715f00 | 180 | struct drm_i915_private; |
0a3e67a4 | 181 | |
8ee1c3db | 182 | struct intel_opregion { |
5bc4418b BW |
183 | struct opregion_header __iomem *header; |
184 | struct opregion_acpi __iomem *acpi; | |
185 | struct opregion_swsci __iomem *swsci; | |
186 | struct opregion_asle __iomem *asle; | |
187 | void __iomem *vbt; | |
01fe9dbd | 188 | u32 __iomem *lid_state; |
8ee1c3db | 189 | }; |
44834a67 | 190 | #define OPREGION_SIZE (8*1024) |
8ee1c3db | 191 | |
6ef3d427 CW |
192 | struct intel_overlay; |
193 | struct intel_overlay_error_state; | |
194 | ||
7c1c2871 DA |
195 | struct drm_i915_master_private { |
196 | drm_local_map_t *sarea; | |
197 | struct _drm_i915_sarea *sarea_priv; | |
198 | }; | |
de151cf6 | 199 | #define I915_FENCE_REG_NONE -1 |
42b5aeab VS |
200 | #define I915_MAX_NUM_FENCES 32 |
201 | /* 32 fences + sign bit for FENCE_REG_NONE */ | |
202 | #define I915_MAX_NUM_FENCE_BITS 6 | |
de151cf6 JB |
203 | |
204 | struct drm_i915_fence_reg { | |
007cc8ac | 205 | struct list_head lru_list; |
caea7476 | 206 | struct drm_i915_gem_object *obj; |
1690e1eb | 207 | int pin_count; |
de151cf6 | 208 | }; |
7c1c2871 | 209 | |
9b9d172d | 210 | struct sdvo_device_mapping { |
e957d772 | 211 | u8 initialized; |
9b9d172d | 212 | u8 dvo_port; |
213 | u8 slave_addr; | |
214 | u8 dvo_wiring; | |
e957d772 | 215 | u8 i2c_pin; |
b1083333 | 216 | u8 ddc_pin; |
9b9d172d | 217 | }; |
218 | ||
c4a1d9e4 CW |
219 | struct intel_display_error_state; |
220 | ||
63eeaf38 | 221 | struct drm_i915_error_state { |
742cbee8 | 222 | struct kref ref; |
63eeaf38 JB |
223 | u32 eir; |
224 | u32 pgtbl_er; | |
be998e2e | 225 | u32 ier; |
b9a3906b | 226 | u32 ccid; |
0f3b6849 CW |
227 | u32 derrmr; |
228 | u32 forcewake; | |
9574b3fe | 229 | bool waiting[I915_NUM_RINGS]; |
9db4a9c7 | 230 | u32 pipestat[I915_MAX_PIPES]; |
c1cd90ed DV |
231 | u32 tail[I915_NUM_RINGS]; |
232 | u32 head[I915_NUM_RINGS]; | |
0f3b6849 | 233 | u32 ctl[I915_NUM_RINGS]; |
d27b1e0e DV |
234 | u32 ipeir[I915_NUM_RINGS]; |
235 | u32 ipehr[I915_NUM_RINGS]; | |
236 | u32 instdone[I915_NUM_RINGS]; | |
237 | u32 acthd[I915_NUM_RINGS]; | |
7e3b8737 | 238 | u32 semaphore_mboxes[I915_NUM_RINGS][I915_NUM_RINGS - 1]; |
df2b23d9 | 239 | u32 semaphore_seqno[I915_NUM_RINGS][I915_NUM_RINGS - 1]; |
12f55818 | 240 | u32 rc_psmi[I915_NUM_RINGS]; /* sleep state */ |
7e3b8737 DV |
241 | /* our own tracking of ring head and tail */ |
242 | u32 cpu_ring_head[I915_NUM_RINGS]; | |
243 | u32 cpu_ring_tail[I915_NUM_RINGS]; | |
1d8f38f4 | 244 | u32 error; /* gen6+ */ |
71e172e8 | 245 | u32 err_int; /* gen7 */ |
c1cd90ed DV |
246 | u32 instpm[I915_NUM_RINGS]; |
247 | u32 instps[I915_NUM_RINGS]; | |
050ee91f | 248 | u32 extra_instdone[I915_NUM_INSTDONE_REG]; |
d27b1e0e | 249 | u32 seqno[I915_NUM_RINGS]; |
9df30794 | 250 | u64 bbaddr; |
33f3f518 DV |
251 | u32 fault_reg[I915_NUM_RINGS]; |
252 | u32 done_reg; | |
c1cd90ed | 253 | u32 faddr[I915_NUM_RINGS]; |
4b9de737 | 254 | u64 fence[I915_MAX_NUM_FENCES]; |
63eeaf38 | 255 | struct timeval time; |
52d39a21 CW |
256 | struct drm_i915_error_ring { |
257 | struct drm_i915_error_object { | |
258 | int page_count; | |
259 | u32 gtt_offset; | |
260 | u32 *pages[0]; | |
8c123e54 | 261 | } *ringbuffer, *batchbuffer, *ctx; |
52d39a21 CW |
262 | struct drm_i915_error_request { |
263 | long jiffies; | |
264 | u32 seqno; | |
ee4f42b1 | 265 | u32 tail; |
52d39a21 CW |
266 | } *requests; |
267 | int num_requests; | |
268 | } ring[I915_NUM_RINGS]; | |
9df30794 | 269 | struct drm_i915_error_buffer { |
a779e5ab | 270 | u32 size; |
9df30794 | 271 | u32 name; |
0201f1ec | 272 | u32 rseqno, wseqno; |
9df30794 CW |
273 | u32 gtt_offset; |
274 | u32 read_domains; | |
275 | u32 write_domain; | |
4b9de737 | 276 | s32 fence_reg:I915_MAX_NUM_FENCE_BITS; |
9df30794 CW |
277 | s32 pinned:2; |
278 | u32 tiling:2; | |
279 | u32 dirty:1; | |
280 | u32 purgeable:1; | |
5d1333fc | 281 | s32 ring:4; |
93dfb40c | 282 | u32 cache_level:2; |
c724e8a9 CW |
283 | } *active_bo, *pinned_bo; |
284 | u32 active_bo_count, pinned_bo_count; | |
6ef3d427 | 285 | struct intel_overlay_error_state *overlay; |
c4a1d9e4 | 286 | struct intel_display_error_state *display; |
63eeaf38 JB |
287 | }; |
288 | ||
b8cecdf5 | 289 | struct intel_crtc_config; |
0e8ffe1b | 290 | struct intel_crtc; |
b8cecdf5 | 291 | |
e70236a8 | 292 | struct drm_i915_display_funcs { |
ee5382ae | 293 | bool (*fbc_enabled)(struct drm_device *dev); |
e70236a8 JB |
294 | void (*enable_fbc)(struct drm_crtc *crtc, unsigned long interval); |
295 | void (*disable_fbc)(struct drm_device *dev); | |
296 | int (*get_display_clock_speed)(struct drm_device *dev); | |
297 | int (*get_fifo_size)(struct drm_device *dev, int plane); | |
d210246a | 298 | void (*update_wm)(struct drm_device *dev); |
b840d907 JB |
299 | void (*update_sprite_wm)(struct drm_device *dev, int pipe, |
300 | uint32_t sprite_width, int pixel_size); | |
1f8eeabf ED |
301 | void (*update_linetime_wm)(struct drm_device *dev, int pipe, |
302 | struct drm_display_mode *mode); | |
47fab737 | 303 | void (*modeset_global_resources)(struct drm_device *dev); |
0e8ffe1b DV |
304 | /* Returns the active state of the crtc, and if the crtc is active, |
305 | * fills out the pipe-config with the hw state. */ | |
306 | bool (*get_pipe_config)(struct intel_crtc *, | |
307 | struct intel_crtc_config *); | |
f564048e | 308 | int (*crtc_mode_set)(struct drm_crtc *crtc, |
f564048e EA |
309 | int x, int y, |
310 | struct drm_framebuffer *old_fb); | |
76e5a89c DV |
311 | void (*crtc_enable)(struct drm_crtc *crtc); |
312 | void (*crtc_disable)(struct drm_crtc *crtc); | |
ee7b9f93 | 313 | void (*off)(struct drm_crtc *crtc); |
e0dac65e WF |
314 | void (*write_eld)(struct drm_connector *connector, |
315 | struct drm_crtc *crtc); | |
674cf967 | 316 | void (*fdi_link_train)(struct drm_crtc *crtc); |
6067aaea | 317 | void (*init_clock_gating)(struct drm_device *dev); |
8c9f3aaf JB |
318 | int (*queue_flip)(struct drm_device *dev, struct drm_crtc *crtc, |
319 | struct drm_framebuffer *fb, | |
320 | struct drm_i915_gem_object *obj); | |
17638cd6 JB |
321 | int (*update_plane)(struct drm_crtc *crtc, struct drm_framebuffer *fb, |
322 | int x, int y); | |
20afbda2 | 323 | void (*hpd_irq_setup)(struct drm_device *dev); |
e70236a8 JB |
324 | /* clock updates for mode set */ |
325 | /* cursor updates */ | |
326 | /* render clock increase/decrease */ | |
327 | /* display clock increase/decrease */ | |
328 | /* pll clock increase/decrease */ | |
e70236a8 JB |
329 | }; |
330 | ||
990bbdad CW |
331 | struct drm_i915_gt_funcs { |
332 | void (*force_wake_get)(struct drm_i915_private *dev_priv); | |
333 | void (*force_wake_put)(struct drm_i915_private *dev_priv); | |
334 | }; | |
335 | ||
79fc46df DL |
336 | #define DEV_INFO_FOR_EACH_FLAG(func, sep) \ |
337 | func(is_mobile) sep \ | |
338 | func(is_i85x) sep \ | |
339 | func(is_i915g) sep \ | |
340 | func(is_i945gm) sep \ | |
341 | func(is_g33) sep \ | |
342 | func(need_gfx_hws) sep \ | |
343 | func(is_g4x) sep \ | |
344 | func(is_pineview) sep \ | |
345 | func(is_broadwater) sep \ | |
346 | func(is_crestline) sep \ | |
347 | func(is_ivybridge) sep \ | |
348 | func(is_valleyview) sep \ | |
349 | func(is_haswell) sep \ | |
350 | func(has_force_wake) sep \ | |
351 | func(has_fbc) sep \ | |
352 | func(has_pipe_cxsr) sep \ | |
353 | func(has_hotplug) sep \ | |
354 | func(cursor_needs_physical) sep \ | |
355 | func(has_overlay) sep \ | |
356 | func(overlay_needs_physical) sep \ | |
357 | func(supports_tv) sep \ | |
358 | func(has_bsd_ring) sep \ | |
359 | func(has_blt_ring) sep \ | |
dd93be58 | 360 | func(has_llc) sep \ |
30568c45 DL |
361 | func(has_ddi) sep \ |
362 | func(has_fpga_dbg) | |
c96ea64e | 363 | |
a587f779 DL |
364 | #define DEFINE_FLAG(name) u8 name:1 |
365 | #define SEP_SEMICOLON ; | |
366 | ||
cfdf1fa2 | 367 | struct intel_device_info { |
10fce67a | 368 | u32 display_mmio_offset; |
7eb552ae | 369 | u8 num_pipes:3; |
c96c3a8c | 370 | u8 gen; |
a587f779 | 371 | DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG, SEP_SEMICOLON); |
cfdf1fa2 KH |
372 | }; |
373 | ||
a587f779 DL |
374 | #undef DEFINE_FLAG |
375 | #undef SEP_SEMICOLON | |
376 | ||
7faf1ab2 DV |
377 | enum i915_cache_level { |
378 | I915_CACHE_NONE = 0, | |
379 | I915_CACHE_LLC, | |
380 | I915_CACHE_LLC_MLC, /* gen6+, in docs at least! */ | |
381 | }; | |
382 | ||
2d04befb KG |
383 | typedef uint32_t gen6_gtt_pte_t; |
384 | ||
5d4545ae BW |
385 | /* The Graphics Translation Table is the way in which GEN hardware translates a |
386 | * Graphics Virtual Address into a Physical Address. In addition to the normal | |
387 | * collateral associated with any va->pa translations GEN hardware also has a | |
388 | * portion of the GTT which can be mapped by the CPU and remain both coherent | |
389 | * and correct (in cases like swizzling). That region is referred to as GMADR in | |
390 | * the spec. | |
391 | */ | |
392 | struct i915_gtt { | |
393 | unsigned long start; /* Start offset of used GTT */ | |
394 | size_t total; /* Total size GTT can map */ | |
baa09f5f | 395 | size_t stolen_size; /* Total size of stolen memory */ |
5d4545ae BW |
396 | |
397 | unsigned long mappable_end; /* End offset that we can CPU map */ | |
398 | struct io_mapping *mappable; /* Mapping to our CPU mappable region */ | |
399 | phys_addr_t mappable_base; /* PA of our GMADR */ | |
400 | ||
401 | /** "Graphics Stolen Memory" holds the global PTEs */ | |
402 | void __iomem *gsm; | |
a81cc00c BW |
403 | |
404 | bool do_idle_maps; | |
9c61a32d BW |
405 | dma_addr_t scratch_page_dma; |
406 | struct page *scratch_page; | |
7faf1ab2 DV |
407 | |
408 | /* global gtt ops */ | |
baa09f5f | 409 | int (*gtt_probe)(struct drm_device *dev, size_t *gtt_total, |
41907ddc BW |
410 | size_t *stolen, phys_addr_t *mappable_base, |
411 | unsigned long *mappable_end); | |
baa09f5f | 412 | void (*gtt_remove)(struct drm_device *dev); |
7faf1ab2 DV |
413 | void (*gtt_clear_range)(struct drm_device *dev, |
414 | unsigned int first_entry, | |
415 | unsigned int num_entries); | |
416 | void (*gtt_insert_entries)(struct drm_device *dev, | |
417 | struct sg_table *st, | |
418 | unsigned int pg_start, | |
419 | enum i915_cache_level cache_level); | |
2d04befb KG |
420 | gen6_gtt_pte_t (*pte_encode)(struct drm_device *dev, |
421 | dma_addr_t addr, | |
422 | enum i915_cache_level level); | |
5d4545ae | 423 | }; |
a54c0c27 | 424 | #define gtt_total_entries(gtt) ((gtt).total >> PAGE_SHIFT) |
5d4545ae | 425 | |
1d2a314c DV |
426 | #define I915_PPGTT_PD_ENTRIES 512 |
427 | #define I915_PPGTT_PT_ENTRIES 1024 | |
428 | struct i915_hw_ppgtt { | |
8f2c59f0 | 429 | struct drm_device *dev; |
1d2a314c DV |
430 | unsigned num_pd_entries; |
431 | struct page **pt_pages; | |
432 | uint32_t pd_offset; | |
433 | dma_addr_t *pt_dma_addr; | |
434 | dma_addr_t scratch_page_dma_addr; | |
def886c3 DV |
435 | |
436 | /* pte functions, mirroring the interface of the global gtt. */ | |
437 | void (*clear_range)(struct i915_hw_ppgtt *ppgtt, | |
438 | unsigned int first_entry, | |
439 | unsigned int num_entries); | |
440 | void (*insert_entries)(struct i915_hw_ppgtt *ppgtt, | |
441 | struct sg_table *st, | |
442 | unsigned int pg_start, | |
443 | enum i915_cache_level cache_level); | |
2d04befb KG |
444 | gen6_gtt_pte_t (*pte_encode)(struct drm_device *dev, |
445 | dma_addr_t addr, | |
446 | enum i915_cache_level level); | |
b7c36d25 | 447 | int (*enable)(struct drm_device *dev); |
3440d265 | 448 | void (*cleanup)(struct i915_hw_ppgtt *ppgtt); |
1d2a314c DV |
449 | }; |
450 | ||
40521054 BW |
451 | |
452 | /* This must match up with the value previously used for execbuf2.rsvd1. */ | |
453 | #define DEFAULT_CONTEXT_ID 0 | |
454 | struct i915_hw_context { | |
455 | int id; | |
e0556841 | 456 | bool is_initialized; |
40521054 BW |
457 | struct drm_i915_file_private *file_priv; |
458 | struct intel_ring_buffer *ring; | |
459 | struct drm_i915_gem_object *obj; | |
460 | }; | |
461 | ||
b5e50c3f | 462 | enum no_fbc_reason { |
bed4a673 | 463 | FBC_NO_OUTPUT, /* no outputs enabled to compress */ |
b5e50c3f JB |
464 | FBC_STOLEN_TOO_SMALL, /* not enough space to hold compressed buffers */ |
465 | FBC_UNSUPPORTED_MODE, /* interlace or doublescanned mode */ | |
466 | FBC_MODE_TOO_LARGE, /* mode too large for compression */ | |
467 | FBC_BAD_PLANE, /* fbc not supported on plane */ | |
468 | FBC_NOT_TILED, /* buffer not tiled */ | |
9c928d16 | 469 | FBC_MULTIPLE_PIPES, /* more than one pipe active */ |
c1a9f047 | 470 | FBC_MODULE_PARAM, |
b5e50c3f JB |
471 | }; |
472 | ||
3bad0781 | 473 | enum intel_pch { |
f0350830 | 474 | PCH_NONE = 0, /* No PCH present */ |
3bad0781 ZW |
475 | PCH_IBX, /* Ibexpeak PCH */ |
476 | PCH_CPT, /* Cougarpoint PCH */ | |
eb877ebf | 477 | PCH_LPT, /* Lynxpoint PCH */ |
40c7ead9 | 478 | PCH_NOP, |
3bad0781 ZW |
479 | }; |
480 | ||
988d6ee8 PZ |
481 | enum intel_sbi_destination { |
482 | SBI_ICLK, | |
483 | SBI_MPHY, | |
484 | }; | |
485 | ||
b690e96c | 486 | #define QUIRK_PIPEA_FORCE (1<<0) |
435793df | 487 | #define QUIRK_LVDS_SSC_DISABLE (1<<1) |
4dca20ef | 488 | #define QUIRK_INVERT_BRIGHTNESS (1<<2) |
b690e96c | 489 | |
8be48d92 | 490 | struct intel_fbdev; |
1630fe75 | 491 | struct intel_fbc_work; |
38651674 | 492 | |
c2b9152f DV |
493 | struct intel_gmbus { |
494 | struct i2c_adapter adapter; | |
f2ce9faf | 495 | u32 force_bit; |
c2b9152f | 496 | u32 reg0; |
36c785f0 | 497 | u32 gpio_reg; |
c167a6fc | 498 | struct i2c_algo_bit_data bit_algo; |
c2b9152f DV |
499 | struct drm_i915_private *dev_priv; |
500 | }; | |
501 | ||
f4c956ad | 502 | struct i915_suspend_saved_registers { |
ba8bbcf6 JB |
503 | u8 saveLBB; |
504 | u32 saveDSPACNTR; | |
505 | u32 saveDSPBCNTR; | |
e948e994 | 506 | u32 saveDSPARB; |
ba8bbcf6 JB |
507 | u32 savePIPEACONF; |
508 | u32 savePIPEBCONF; | |
509 | u32 savePIPEASRC; | |
510 | u32 savePIPEBSRC; | |
511 | u32 saveFPA0; | |
512 | u32 saveFPA1; | |
513 | u32 saveDPLL_A; | |
514 | u32 saveDPLL_A_MD; | |
515 | u32 saveHTOTAL_A; | |
516 | u32 saveHBLANK_A; | |
517 | u32 saveHSYNC_A; | |
518 | u32 saveVTOTAL_A; | |
519 | u32 saveVBLANK_A; | |
520 | u32 saveVSYNC_A; | |
521 | u32 saveBCLRPAT_A; | |
5586c8bc | 522 | u32 saveTRANSACONF; |
42048781 ZW |
523 | u32 saveTRANS_HTOTAL_A; |
524 | u32 saveTRANS_HBLANK_A; | |
525 | u32 saveTRANS_HSYNC_A; | |
526 | u32 saveTRANS_VTOTAL_A; | |
527 | u32 saveTRANS_VBLANK_A; | |
528 | u32 saveTRANS_VSYNC_A; | |
0da3ea12 | 529 | u32 savePIPEASTAT; |
ba8bbcf6 JB |
530 | u32 saveDSPASTRIDE; |
531 | u32 saveDSPASIZE; | |
532 | u32 saveDSPAPOS; | |
585fb111 | 533 | u32 saveDSPAADDR; |
ba8bbcf6 JB |
534 | u32 saveDSPASURF; |
535 | u32 saveDSPATILEOFF; | |
536 | u32 savePFIT_PGM_RATIOS; | |
0eb96d6e | 537 | u32 saveBLC_HIST_CTL; |
ba8bbcf6 JB |
538 | u32 saveBLC_PWM_CTL; |
539 | u32 saveBLC_PWM_CTL2; | |
42048781 ZW |
540 | u32 saveBLC_CPU_PWM_CTL; |
541 | u32 saveBLC_CPU_PWM_CTL2; | |
ba8bbcf6 JB |
542 | u32 saveFPB0; |
543 | u32 saveFPB1; | |
544 | u32 saveDPLL_B; | |
545 | u32 saveDPLL_B_MD; | |
546 | u32 saveHTOTAL_B; | |
547 | u32 saveHBLANK_B; | |
548 | u32 saveHSYNC_B; | |
549 | u32 saveVTOTAL_B; | |
550 | u32 saveVBLANK_B; | |
551 | u32 saveVSYNC_B; | |
552 | u32 saveBCLRPAT_B; | |
5586c8bc | 553 | u32 saveTRANSBCONF; |
42048781 ZW |
554 | u32 saveTRANS_HTOTAL_B; |
555 | u32 saveTRANS_HBLANK_B; | |
556 | u32 saveTRANS_HSYNC_B; | |
557 | u32 saveTRANS_VTOTAL_B; | |
558 | u32 saveTRANS_VBLANK_B; | |
559 | u32 saveTRANS_VSYNC_B; | |
0da3ea12 | 560 | u32 savePIPEBSTAT; |
ba8bbcf6 JB |
561 | u32 saveDSPBSTRIDE; |
562 | u32 saveDSPBSIZE; | |
563 | u32 saveDSPBPOS; | |
585fb111 | 564 | u32 saveDSPBADDR; |
ba8bbcf6 JB |
565 | u32 saveDSPBSURF; |
566 | u32 saveDSPBTILEOFF; | |
585fb111 JB |
567 | u32 saveVGA0; |
568 | u32 saveVGA1; | |
569 | u32 saveVGA_PD; | |
ba8bbcf6 JB |
570 | u32 saveVGACNTRL; |
571 | u32 saveADPA; | |
572 | u32 saveLVDS; | |
585fb111 JB |
573 | u32 savePP_ON_DELAYS; |
574 | u32 savePP_OFF_DELAYS; | |
ba8bbcf6 JB |
575 | u32 saveDVOA; |
576 | u32 saveDVOB; | |
577 | u32 saveDVOC; | |
578 | u32 savePP_ON; | |
579 | u32 savePP_OFF; | |
580 | u32 savePP_CONTROL; | |
585fb111 | 581 | u32 savePP_DIVISOR; |
ba8bbcf6 JB |
582 | u32 savePFIT_CONTROL; |
583 | u32 save_palette_a[256]; | |
584 | u32 save_palette_b[256]; | |
06027f91 | 585 | u32 saveDPFC_CB_BASE; |
ba8bbcf6 JB |
586 | u32 saveFBC_CFB_BASE; |
587 | u32 saveFBC_LL_BASE; | |
588 | u32 saveFBC_CONTROL; | |
589 | u32 saveFBC_CONTROL2; | |
0da3ea12 JB |
590 | u32 saveIER; |
591 | u32 saveIIR; | |
592 | u32 saveIMR; | |
42048781 ZW |
593 | u32 saveDEIER; |
594 | u32 saveDEIMR; | |
595 | u32 saveGTIER; | |
596 | u32 saveGTIMR; | |
597 | u32 saveFDI_RXA_IMR; | |
598 | u32 saveFDI_RXB_IMR; | |
1f84e550 | 599 | u32 saveCACHE_MODE_0; |
1f84e550 | 600 | u32 saveMI_ARB_STATE; |
ba8bbcf6 JB |
601 | u32 saveSWF0[16]; |
602 | u32 saveSWF1[16]; | |
603 | u32 saveSWF2[3]; | |
604 | u8 saveMSR; | |
605 | u8 saveSR[8]; | |
123f794f | 606 | u8 saveGR[25]; |
ba8bbcf6 | 607 | u8 saveAR_INDEX; |
a59e122a | 608 | u8 saveAR[21]; |
ba8bbcf6 | 609 | u8 saveDACMASK; |
a59e122a | 610 | u8 saveCR[37]; |
4b9de737 | 611 | uint64_t saveFENCE[I915_MAX_NUM_FENCES]; |
1fd1c624 EA |
612 | u32 saveCURACNTR; |
613 | u32 saveCURAPOS; | |
614 | u32 saveCURABASE; | |
615 | u32 saveCURBCNTR; | |
616 | u32 saveCURBPOS; | |
617 | u32 saveCURBBASE; | |
618 | u32 saveCURSIZE; | |
a4fc5ed6 KP |
619 | u32 saveDP_B; |
620 | u32 saveDP_C; | |
621 | u32 saveDP_D; | |
622 | u32 savePIPEA_GMCH_DATA_M; | |
623 | u32 savePIPEB_GMCH_DATA_M; | |
624 | u32 savePIPEA_GMCH_DATA_N; | |
625 | u32 savePIPEB_GMCH_DATA_N; | |
626 | u32 savePIPEA_DP_LINK_M; | |
627 | u32 savePIPEB_DP_LINK_M; | |
628 | u32 savePIPEA_DP_LINK_N; | |
629 | u32 savePIPEB_DP_LINK_N; | |
42048781 ZW |
630 | u32 saveFDI_RXA_CTL; |
631 | u32 saveFDI_TXA_CTL; | |
632 | u32 saveFDI_RXB_CTL; | |
633 | u32 saveFDI_TXB_CTL; | |
634 | u32 savePFA_CTL_1; | |
635 | u32 savePFB_CTL_1; | |
636 | u32 savePFA_WIN_SZ; | |
637 | u32 savePFB_WIN_SZ; | |
638 | u32 savePFA_WIN_POS; | |
639 | u32 savePFB_WIN_POS; | |
5586c8bc ZW |
640 | u32 savePCH_DREF_CONTROL; |
641 | u32 saveDISP_ARB_CTL; | |
642 | u32 savePIPEA_DATA_M1; | |
643 | u32 savePIPEA_DATA_N1; | |
644 | u32 savePIPEA_LINK_M1; | |
645 | u32 savePIPEA_LINK_N1; | |
646 | u32 savePIPEB_DATA_M1; | |
647 | u32 savePIPEB_DATA_N1; | |
648 | u32 savePIPEB_LINK_M1; | |
649 | u32 savePIPEB_LINK_N1; | |
b5b72e89 | 650 | u32 saveMCHBAR_RENDER_STANDBY; |
cda2bb78 | 651 | u32 savePCH_PORT_HOTPLUG; |
f4c956ad | 652 | }; |
c85aa885 DV |
653 | |
654 | struct intel_gen6_power_mgmt { | |
655 | struct work_struct work; | |
656 | u32 pm_iir; | |
657 | /* lock - irqsave spinlock that protectects the work_struct and | |
658 | * pm_iir. */ | |
659 | spinlock_t lock; | |
660 | ||
661 | /* The below variables an all the rps hw state are protected by | |
662 | * dev->struct mutext. */ | |
663 | u8 cur_delay; | |
664 | u8 min_delay; | |
665 | u8 max_delay; | |
31c77388 | 666 | u8 hw_max; |
1a01ab3b JB |
667 | |
668 | struct delayed_work delayed_resume_work; | |
4fc688ce JB |
669 | |
670 | /* | |
671 | * Protects RPS/RC6 register access and PCU communication. | |
672 | * Must be taken after struct_mutex if nested. | |
673 | */ | |
674 | struct mutex hw_lock; | |
c85aa885 DV |
675 | }; |
676 | ||
1a240d4d DV |
677 | /* defined intel_pm.c */ |
678 | extern spinlock_t mchdev_lock; | |
679 | ||
c85aa885 DV |
680 | struct intel_ilk_power_mgmt { |
681 | u8 cur_delay; | |
682 | u8 min_delay; | |
683 | u8 max_delay; | |
684 | u8 fmax; | |
685 | u8 fstart; | |
686 | ||
687 | u64 last_count1; | |
688 | unsigned long last_time1; | |
689 | unsigned long chipset_power; | |
690 | u64 last_count2; | |
691 | struct timespec last_time2; | |
692 | unsigned long gfx_power; | |
693 | u8 corr; | |
694 | ||
695 | int c_m; | |
696 | int r_t; | |
3e373948 DV |
697 | |
698 | struct drm_i915_gem_object *pwrctx; | |
699 | struct drm_i915_gem_object *renderctx; | |
c85aa885 DV |
700 | }; |
701 | ||
231f42a4 DV |
702 | struct i915_dri1_state { |
703 | unsigned allow_batchbuffer : 1; | |
704 | u32 __iomem *gfx_hws_cpu_addr; | |
705 | ||
706 | unsigned int cpp; | |
707 | int back_offset; | |
708 | int front_offset; | |
709 | int current_page; | |
710 | int page_flipping; | |
711 | ||
712 | uint32_t counter; | |
713 | }; | |
714 | ||
a4da4fa4 DV |
715 | struct intel_l3_parity { |
716 | u32 *remap_info; | |
717 | struct work_struct error_work; | |
718 | }; | |
719 | ||
4b5aed62 | 720 | struct i915_gem_mm { |
4b5aed62 DV |
721 | /** Memory allocator for GTT stolen memory */ |
722 | struct drm_mm stolen; | |
723 | /** Memory allocator for GTT */ | |
724 | struct drm_mm gtt_space; | |
725 | /** List of all objects in gtt_space. Used to restore gtt | |
726 | * mappings on resume */ | |
727 | struct list_head bound_list; | |
728 | /** | |
729 | * List of objects which are not bound to the GTT (thus | |
730 | * are idle and not used by the GPU) but still have | |
731 | * (presumably uncached) pages still attached. | |
732 | */ | |
733 | struct list_head unbound_list; | |
734 | ||
735 | /** Usable portion of the GTT for GEM */ | |
736 | unsigned long stolen_base; /* limited to low memory (32-bit) */ | |
737 | ||
738 | int gtt_mtrr; | |
739 | ||
740 | /** PPGTT used for aliasing the PPGTT with the GTT */ | |
741 | struct i915_hw_ppgtt *aliasing_ppgtt; | |
742 | ||
743 | struct shrinker inactive_shrinker; | |
744 | bool shrinker_no_lock_stealing; | |
745 | ||
746 | /** | |
747 | * List of objects currently involved in rendering. | |
748 | * | |
749 | * Includes buffers having the contents of their GPU caches | |
750 | * flushed, not necessarily primitives. last_rendering_seqno | |
751 | * represents when the rendering involved will be completed. | |
752 | * | |
753 | * A reference is held on the buffer while on this list. | |
754 | */ | |
755 | struct list_head active_list; | |
756 | ||
757 | /** | |
758 | * LRU list of objects which are not in the ringbuffer and | |
759 | * are ready to unbind, but are still in the GTT. | |
760 | * | |
761 | * last_rendering_seqno is 0 while an object is in this list. | |
762 | * | |
763 | * A reference is not held on the buffer while on this list, | |
764 | * as merely being GTT-bound shouldn't prevent its being | |
765 | * freed, and we'll pull it off the list in the free path. | |
766 | */ | |
767 | struct list_head inactive_list; | |
768 | ||
769 | /** LRU list of objects with fence regs on them. */ | |
770 | struct list_head fence_list; | |
771 | ||
772 | /** | |
773 | * We leave the user IRQ off as much as possible, | |
774 | * but this means that requests will finish and never | |
775 | * be retired once the system goes idle. Set a timer to | |
776 | * fire periodically while the ring is running. When it | |
777 | * fires, go retire requests. | |
778 | */ | |
779 | struct delayed_work retire_work; | |
780 | ||
781 | /** | |
782 | * Are we in a non-interruptible section of code like | |
783 | * modesetting? | |
784 | */ | |
785 | bool interruptible; | |
786 | ||
787 | /** | |
788 | * Flag if the X Server, and thus DRM, is not currently in | |
789 | * control of the device. | |
790 | * | |
791 | * This is set between LeaveVT and EnterVT. It needs to be | |
792 | * replaced with a semaphore. It also needs to be | |
793 | * transitioned away from for kernel modesetting. | |
794 | */ | |
795 | int suspended; | |
796 | ||
4b5aed62 DV |
797 | /** Bit 6 swizzling required for X tiling */ |
798 | uint32_t bit_6_swizzle_x; | |
799 | /** Bit 6 swizzling required for Y tiling */ | |
800 | uint32_t bit_6_swizzle_y; | |
801 | ||
802 | /* storage for physical objects */ | |
803 | struct drm_i915_gem_phys_object *phys_objs[I915_MAX_PHYS_OBJECT]; | |
804 | ||
805 | /* accounting, useful for userland debugging */ | |
806 | size_t object_memory; | |
807 | u32 object_count; | |
808 | }; | |
809 | ||
99584db3 DV |
810 | struct i915_gpu_error { |
811 | /* For hangcheck timer */ | |
812 | #define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */ | |
813 | #define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD) | |
814 | struct timer_list hangcheck_timer; | |
815 | int hangcheck_count; | |
816 | uint32_t last_acthd[I915_NUM_RINGS]; | |
817 | uint32_t prev_instdone[I915_NUM_INSTDONE_REG]; | |
818 | ||
819 | /* For reset and error_state handling. */ | |
820 | spinlock_t lock; | |
821 | /* Protected by the above dev->gpu_error.lock. */ | |
822 | struct drm_i915_error_state *first_error; | |
823 | struct work_struct work; | |
99584db3 DV |
824 | |
825 | unsigned long last_reset; | |
826 | ||
1f83fee0 | 827 | /** |
f69061be | 828 | * State variable and reset counter controlling the reset flow |
1f83fee0 | 829 | * |
f69061be DV |
830 | * Upper bits are for the reset counter. This counter is used by the |
831 | * wait_seqno code to race-free noticed that a reset event happened and | |
832 | * that it needs to restart the entire ioctl (since most likely the | |
833 | * seqno it waited for won't ever signal anytime soon). | |
834 | * | |
835 | * This is important for lock-free wait paths, where no contended lock | |
836 | * naturally enforces the correct ordering between the bail-out of the | |
837 | * waiter and the gpu reset work code. | |
1f83fee0 DV |
838 | * |
839 | * Lowest bit controls the reset state machine: Set means a reset is in | |
840 | * progress. This state will (presuming we don't have any bugs) decay | |
841 | * into either unset (successful reset) or the special WEDGED value (hw | |
842 | * terminally sour). All waiters on the reset_queue will be woken when | |
843 | * that happens. | |
844 | */ | |
845 | atomic_t reset_counter; | |
846 | ||
847 | /** | |
848 | * Special values/flags for reset_counter | |
849 | * | |
850 | * Note that the code relies on | |
851 | * I915_WEDGED & I915_RESET_IN_PROGRESS_FLAG | |
852 | * being true. | |
853 | */ | |
854 | #define I915_RESET_IN_PROGRESS_FLAG 1 | |
855 | #define I915_WEDGED 0xffffffff | |
856 | ||
857 | /** | |
858 | * Waitqueue to signal when the reset has completed. Used by clients | |
859 | * that wait for dev_priv->mm.wedged to settle. | |
860 | */ | |
861 | wait_queue_head_t reset_queue; | |
33196ded | 862 | |
99584db3 DV |
863 | /* For gpu hang simulation. */ |
864 | unsigned int stop_rings; | |
865 | }; | |
866 | ||
b8efb17b ZR |
867 | enum modeset_restore { |
868 | MODESET_ON_LID_OPEN, | |
869 | MODESET_DONE, | |
870 | MODESET_SUSPENDED, | |
871 | }; | |
872 | ||
f4c956ad DV |
873 | typedef struct drm_i915_private { |
874 | struct drm_device *dev; | |
42dcedd4 | 875 | struct kmem_cache *slab; |
f4c956ad DV |
876 | |
877 | const struct intel_device_info *info; | |
878 | ||
879 | int relative_constants_mode; | |
880 | ||
881 | void __iomem *regs; | |
882 | ||
883 | struct drm_i915_gt_funcs gt; | |
884 | /** gt_fifo_count and the subsequent register write are synchronized | |
885 | * with dev->struct_mutex. */ | |
886 | unsigned gt_fifo_count; | |
887 | /** forcewake_count is protected by gt_lock */ | |
888 | unsigned forcewake_count; | |
889 | /** gt_lock is also taken in irq contexts. */ | |
99057c81 | 890 | spinlock_t gt_lock; |
f4c956ad DV |
891 | |
892 | struct intel_gmbus gmbus[GMBUS_NUM_PORTS]; | |
893 | ||
28c70f16 | 894 | |
f4c956ad DV |
895 | /** gmbus_mutex protects against concurrent usage of the single hw gmbus |
896 | * controller on different i2c buses. */ | |
897 | struct mutex gmbus_mutex; | |
898 | ||
899 | /** | |
900 | * Base address of the gmbus and gpio block. | |
901 | */ | |
902 | uint32_t gpio_mmio_base; | |
903 | ||
28c70f16 DV |
904 | wait_queue_head_t gmbus_wait_queue; |
905 | ||
f4c956ad DV |
906 | struct pci_dev *bridge_dev; |
907 | struct intel_ring_buffer ring[I915_NUM_RINGS]; | |
f72b3435 | 908 | uint32_t last_seqno, next_seqno; |
f4c956ad DV |
909 | |
910 | drm_dma_handle_t *status_page_dmah; | |
f4c956ad DV |
911 | struct resource mch_res; |
912 | ||
913 | atomic_t irq_received; | |
914 | ||
915 | /* protects the irq masks */ | |
916 | spinlock_t irq_lock; | |
917 | ||
9ee32fea DV |
918 | /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */ |
919 | struct pm_qos_request pm_qos; | |
920 | ||
f4c956ad | 921 | /* DPIO indirect register protection */ |
09153000 | 922 | struct mutex dpio_lock; |
f4c956ad DV |
923 | |
924 | /** Cached value of IMR to avoid reads in updating the bitfield */ | |
f4c956ad DV |
925 | u32 irq_mask; |
926 | u32 gt_irq_mask; | |
f4c956ad | 927 | |
f4c956ad | 928 | struct work_struct hotplug_work; |
52d7eced | 929 | bool enable_hotplug_processing; |
b543fb04 EE |
930 | struct { |
931 | unsigned long hpd_last_jiffies; | |
932 | int hpd_cnt; | |
933 | enum { | |
934 | HPD_ENABLED = 0, | |
935 | HPD_DISABLED = 1, | |
936 | HPD_MARK_DISABLED = 2 | |
937 | } hpd_mark; | |
938 | } hpd_stats[HPD_NUM_PINS]; | |
142e2398 | 939 | u32 hpd_event_bits; |
ac4c16c5 | 940 | struct timer_list hotplug_reenable_timer; |
f4c956ad | 941 | |
f4c956ad | 942 | int num_pch_pll; |
7f1f3851 | 943 | int num_plane; |
f4c956ad | 944 | |
f4c956ad DV |
945 | unsigned long cfb_size; |
946 | unsigned int cfb_fb; | |
947 | enum plane cfb_plane; | |
948 | int cfb_y; | |
949 | struct intel_fbc_work *fbc_work; | |
950 | ||
951 | struct intel_opregion opregion; | |
952 | ||
953 | /* overlay */ | |
954 | struct intel_overlay *overlay; | |
2c6602df | 955 | unsigned int sprite_scaling_enabled; |
f4c956ad | 956 | |
31ad8ec6 JN |
957 | /* backlight */ |
958 | struct { | |
959 | int level; | |
960 | bool enabled; | |
961 | struct backlight_device *device; | |
962 | } backlight; | |
963 | ||
f4c956ad | 964 | /* LVDS info */ |
f4c956ad DV |
965 | struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */ |
966 | struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */ | |
967 | ||
968 | /* Feature bits from the VBIOS */ | |
969 | unsigned int int_tv_support:1; | |
970 | unsigned int lvds_dither:1; | |
971 | unsigned int lvds_vbt:1; | |
972 | unsigned int int_crt_support:1; | |
973 | unsigned int lvds_use_ssc:1; | |
974 | unsigned int display_clock_mode:1; | |
3f704fa2 | 975 | unsigned int fdi_rx_polarity_inverted:1; |
f4c956ad DV |
976 | int lvds_ssc_freq; |
977 | unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */ | |
f4c956ad DV |
978 | struct { |
979 | int rate; | |
980 | int lanes; | |
981 | int preemphasis; | |
982 | int vswing; | |
983 | ||
984 | bool initialized; | |
985 | bool support; | |
986 | int bpp; | |
987 | struct edp_power_seq pps; | |
988 | } edp; | |
989 | bool no_aux_handshake; | |
990 | ||
991 | int crt_ddc_pin; | |
992 | struct drm_i915_fence_reg fence_regs[I915_MAX_NUM_FENCES]; /* assume 965 */ | |
993 | int fence_reg_start; /* 4 if userland hasn't ioctl'd us yet */ | |
994 | int num_fence_regs; /* 8 on pre-965, 16 otherwise */ | |
995 | ||
996 | unsigned int fsb_freq, mem_freq, is_ddr3; | |
997 | ||
f4c956ad DV |
998 | struct workqueue_struct *wq; |
999 | ||
1000 | /* Display functions */ | |
1001 | struct drm_i915_display_funcs display; | |
1002 | ||
1003 | /* PCH chipset type */ | |
1004 | enum intel_pch pch_type; | |
17a303ec | 1005 | unsigned short pch_id; |
f4c956ad DV |
1006 | |
1007 | unsigned long quirks; | |
1008 | ||
b8efb17b ZR |
1009 | enum modeset_restore modeset_restore; |
1010 | struct mutex modeset_restore_lock; | |
673a394b | 1011 | |
5d4545ae BW |
1012 | struct i915_gtt gtt; |
1013 | ||
4b5aed62 | 1014 | struct i915_gem_mm mm; |
8781342d | 1015 | |
8781342d DV |
1016 | /* Kernel Modesetting */ |
1017 | ||
9b9d172d | 1018 | struct sdvo_device_mapping sdvo_mappings[2]; |
a3e17eb8 ZY |
1019 | /* indicate whether the LVDS_BORDER should be enabled or not */ |
1020 | unsigned int lvds_border_bits; | |
1d8e1c75 CW |
1021 | /* Panel fitter placement and size for Ironlake+ */ |
1022 | u32 pch_pf_pos, pch_pf_size; | |
652c393a | 1023 | |
27f8227b JB |
1024 | struct drm_crtc *plane_to_crtc_mapping[3]; |
1025 | struct drm_crtc *pipe_to_crtc_mapping[3]; | |
6b95a207 KH |
1026 | wait_queue_head_t pending_flip_queue; |
1027 | ||
ee7b9f93 | 1028 | struct intel_pch_pll pch_plls[I915_NUM_PLLS]; |
6441ab5f | 1029 | struct intel_ddi_plls ddi_plls; |
ee7b9f93 | 1030 | |
652c393a JB |
1031 | /* Reclocking support */ |
1032 | bool render_reclock_avail; | |
1033 | bool lvds_downclock_avail; | |
18f9ed12 ZY |
1034 | /* indicates the reduced downclock for LVDS*/ |
1035 | int lvds_downclock; | |
652c393a | 1036 | u16 orig_clock; |
6363ee6f ZY |
1037 | int child_dev_num; |
1038 | struct child_device_config *child_dev; | |
f97108d1 | 1039 | |
c4804411 | 1040 | bool mchbar_need_disable; |
f97108d1 | 1041 | |
a4da4fa4 DV |
1042 | struct intel_l3_parity l3_parity; |
1043 | ||
c6a828d3 | 1044 | /* gen6+ rps state */ |
c85aa885 | 1045 | struct intel_gen6_power_mgmt rps; |
c6a828d3 | 1046 | |
20e4d407 DV |
1047 | /* ilk-only ips/rps state. Everything in here is protected by the global |
1048 | * mchdev_lock in intel_pm.c */ | |
c85aa885 | 1049 | struct intel_ilk_power_mgmt ips; |
b5e50c3f JB |
1050 | |
1051 | enum no_fbc_reason no_fbc_reason; | |
38651674 | 1052 | |
20bf377e JB |
1053 | struct drm_mm_node *compressed_fb; |
1054 | struct drm_mm_node *compressed_llb; | |
34dc4d44 | 1055 | |
99584db3 | 1056 | struct i915_gpu_error gpu_error; |
ae681d96 | 1057 | |
8be48d92 DA |
1058 | /* list of fbdev register on this device */ |
1059 | struct intel_fbdev *fbdev; | |
e953fd7b | 1060 | |
073f34d9 JB |
1061 | /* |
1062 | * The console may be contended at resume, but we don't | |
1063 | * want it to block on it. | |
1064 | */ | |
1065 | struct work_struct console_resume_work; | |
1066 | ||
e953fd7b | 1067 | struct drm_property *broadcast_rgb_property; |
3f43c48d | 1068 | struct drm_property *force_audio_property; |
e3689190 | 1069 | |
254f965c BW |
1070 | bool hw_contexts_disabled; |
1071 | uint32_t hw_context_size; | |
f4c956ad | 1072 | |
3e68320e | 1073 | u32 fdi_rx_config; |
68d18ad7 | 1074 | |
f4c956ad | 1075 | struct i915_suspend_saved_registers regfile; |
231f42a4 DV |
1076 | |
1077 | /* Old dri1 support infrastructure, beware the dragons ya fools entering | |
1078 | * here! */ | |
1079 | struct i915_dri1_state dri1; | |
1da177e4 LT |
1080 | } drm_i915_private_t; |
1081 | ||
b4519513 CW |
1082 | /* Iterate over initialised rings */ |
1083 | #define for_each_ring(ring__, dev_priv__, i__) \ | |
1084 | for ((i__) = 0; (i__) < I915_NUM_RINGS; (i__)++) \ | |
1085 | if (((ring__) = &(dev_priv__)->ring[(i__)]), intel_ring_initialized((ring__))) | |
1086 | ||
b1d7e4b4 WF |
1087 | enum hdmi_force_audio { |
1088 | HDMI_AUDIO_OFF_DVI = -2, /* no aux data for HDMI-DVI converter */ | |
1089 | HDMI_AUDIO_OFF, /* force turn off HDMI audio */ | |
1090 | HDMI_AUDIO_AUTO, /* trust EDID */ | |
1091 | HDMI_AUDIO_ON, /* force turn on HDMI audio */ | |
1092 | }; | |
1093 | ||
ed2f3452 CW |
1094 | #define I915_GTT_RESERVED ((struct drm_mm_node *)0x1) |
1095 | ||
37e680a1 CW |
1096 | struct drm_i915_gem_object_ops { |
1097 | /* Interface between the GEM object and its backing storage. | |
1098 | * get_pages() is called once prior to the use of the associated set | |
1099 | * of pages before to binding them into the GTT, and put_pages() is | |
1100 | * called after we no longer need them. As we expect there to be | |
1101 | * associated cost with migrating pages between the backing storage | |
1102 | * and making them available for the GPU (e.g. clflush), we may hold | |
1103 | * onto the pages after they are no longer referenced by the GPU | |
1104 | * in case they may be used again shortly (for example migrating the | |
1105 | * pages to a different memory domain within the GTT). put_pages() | |
1106 | * will therefore most likely be called when the object itself is | |
1107 | * being released or under memory pressure (where we attempt to | |
1108 | * reap pages for the shrinker). | |
1109 | */ | |
1110 | int (*get_pages)(struct drm_i915_gem_object *); | |
1111 | void (*put_pages)(struct drm_i915_gem_object *); | |
1112 | }; | |
1113 | ||
673a394b | 1114 | struct drm_i915_gem_object { |
c397b908 | 1115 | struct drm_gem_object base; |
673a394b | 1116 | |
37e680a1 CW |
1117 | const struct drm_i915_gem_object_ops *ops; |
1118 | ||
673a394b EA |
1119 | /** Current space allocated to this object in the GTT, if any. */ |
1120 | struct drm_mm_node *gtt_space; | |
c1ad11fc CW |
1121 | /** Stolen memory for this object, instead of being backed by shmem. */ |
1122 | struct drm_mm_node *stolen; | |
93a37f20 | 1123 | struct list_head gtt_list; |
673a394b | 1124 | |
65ce3027 | 1125 | /** This object's place on the active/inactive lists */ |
69dc4987 CW |
1126 | struct list_head ring_list; |
1127 | struct list_head mm_list; | |
432e58ed CW |
1128 | /** This object's place in the batchbuffer or on the eviction list */ |
1129 | struct list_head exec_list; | |
673a394b EA |
1130 | |
1131 | /** | |
65ce3027 CW |
1132 | * This is set if the object is on the active lists (has pending |
1133 | * rendering and so a non-zero seqno), and is not set if it i s on | |
1134 | * inactive (ready to be unbound) list. | |
673a394b | 1135 | */ |
0206e353 | 1136 | unsigned int active:1; |
673a394b EA |
1137 | |
1138 | /** | |
1139 | * This is set if the object has been written to since last bound | |
1140 | * to the GTT | |
1141 | */ | |
0206e353 | 1142 | unsigned int dirty:1; |
778c3544 DV |
1143 | |
1144 | /** | |
1145 | * Fence register bits (if any) for this object. Will be set | |
1146 | * as needed when mapped into the GTT. | |
1147 | * Protected by dev->struct_mutex. | |
778c3544 | 1148 | */ |
4b9de737 | 1149 | signed int fence_reg:I915_MAX_NUM_FENCE_BITS; |
778c3544 | 1150 | |
778c3544 DV |
1151 | /** |
1152 | * Advice: are the backing pages purgeable? | |
1153 | */ | |
0206e353 | 1154 | unsigned int madv:2; |
778c3544 | 1155 | |
778c3544 DV |
1156 | /** |
1157 | * Current tiling mode for the object. | |
1158 | */ | |
0206e353 | 1159 | unsigned int tiling_mode:2; |
5d82e3e6 CW |
1160 | /** |
1161 | * Whether the tiling parameters for the currently associated fence | |
1162 | * register have changed. Note that for the purposes of tracking | |
1163 | * tiling changes we also treat the unfenced register, the register | |
1164 | * slot that the object occupies whilst it executes a fenced | |
1165 | * command (such as BLT on gen2/3), as a "fence". | |
1166 | */ | |
1167 | unsigned int fence_dirty:1; | |
778c3544 DV |
1168 | |
1169 | /** How many users have pinned this object in GTT space. The following | |
1170 | * users can each hold at most one reference: pwrite/pread, pin_ioctl | |
1171 | * (via user_pin_count), execbuffer (objects are not allowed multiple | |
1172 | * times for the same batchbuffer), and the framebuffer code. When | |
1173 | * switching/pageflipping, the framebuffer code has at most two buffers | |
1174 | * pinned per crtc. | |
1175 | * | |
1176 | * In the worst case this is 1 + 1 + 1 + 2*2 = 7. That would fit into 3 | |
1177 | * bits with absolutely no headroom. So use 4 bits. */ | |
0206e353 | 1178 | unsigned int pin_count:4; |
778c3544 | 1179 | #define DRM_I915_GEM_OBJECT_MAX_PIN_COUNT 0xf |
673a394b | 1180 | |
75e9e915 DV |
1181 | /** |
1182 | * Is the object at the current location in the gtt mappable and | |
1183 | * fenceable? Used to avoid costly recalculations. | |
1184 | */ | |
0206e353 | 1185 | unsigned int map_and_fenceable:1; |
75e9e915 | 1186 | |
fb7d516a DV |
1187 | /** |
1188 | * Whether the current gtt mapping needs to be mappable (and isn't just | |
1189 | * mappable by accident). Track pin and fault separate for a more | |
1190 | * accurate mappable working set. | |
1191 | */ | |
0206e353 AJ |
1192 | unsigned int fault_mappable:1; |
1193 | unsigned int pin_mappable:1; | |
fb7d516a | 1194 | |
caea7476 CW |
1195 | /* |
1196 | * Is the GPU currently using a fence to access this buffer, | |
1197 | */ | |
1198 | unsigned int pending_fenced_gpu_access:1; | |
1199 | unsigned int fenced_gpu_access:1; | |
1200 | ||
93dfb40c CW |
1201 | unsigned int cache_level:2; |
1202 | ||
7bddb01f | 1203 | unsigned int has_aliasing_ppgtt_mapping:1; |
74898d7e | 1204 | unsigned int has_global_gtt_mapping:1; |
9da3da66 | 1205 | unsigned int has_dma_mapping:1; |
7bddb01f | 1206 | |
9da3da66 | 1207 | struct sg_table *pages; |
a5570178 | 1208 | int pages_pin_count; |
673a394b | 1209 | |
1286ff73 | 1210 | /* prime dma-buf support */ |
9a70cc2a DA |
1211 | void *dma_buf_vmapping; |
1212 | int vmapping_count; | |
1213 | ||
67731b87 CW |
1214 | /** |
1215 | * Used for performing relocations during execbuffer insertion. | |
1216 | */ | |
1217 | struct hlist_node exec_node; | |
1218 | unsigned long exec_handle; | |
6fe4f140 | 1219 | struct drm_i915_gem_exec_object2 *exec_entry; |
67731b87 | 1220 | |
673a394b EA |
1221 | /** |
1222 | * Current offset of the object in GTT space. | |
1223 | * | |
1224 | * This is the same as gtt_space->start | |
1225 | */ | |
1226 | uint32_t gtt_offset; | |
e67b8ce1 | 1227 | |
caea7476 CW |
1228 | struct intel_ring_buffer *ring; |
1229 | ||
1c293ea3 | 1230 | /** Breadcrumb of last rendering to the buffer. */ |
0201f1ec CW |
1231 | uint32_t last_read_seqno; |
1232 | uint32_t last_write_seqno; | |
caea7476 CW |
1233 | /** Breadcrumb of last fenced GPU access to the buffer. */ |
1234 | uint32_t last_fenced_seqno; | |
673a394b | 1235 | |
778c3544 | 1236 | /** Current tiling stride for the object, if it's tiled. */ |
de151cf6 | 1237 | uint32_t stride; |
673a394b | 1238 | |
280b713b | 1239 | /** Record of address bit 17 of each page at last unbind. */ |
d312ec25 | 1240 | unsigned long *bit_17; |
280b713b | 1241 | |
79e53945 JB |
1242 | /** User space pin count and filp owning the pin */ |
1243 | uint32_t user_pin_count; | |
1244 | struct drm_file *pin_filp; | |
71acb5eb DA |
1245 | |
1246 | /** for phy allocated objects */ | |
1247 | struct drm_i915_gem_phys_object *phys_obj; | |
673a394b | 1248 | }; |
b45305fc | 1249 | #define to_gem_object(obj) (&((struct drm_i915_gem_object *)(obj))->base) |
673a394b | 1250 | |
62b8b215 | 1251 | #define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base) |
23010e43 | 1252 | |
673a394b EA |
1253 | /** |
1254 | * Request queue structure. | |
1255 | * | |
1256 | * The request queue allows us to note sequence numbers that have been emitted | |
1257 | * and may be associated with active buffers to be retired. | |
1258 | * | |
1259 | * By keeping this list, we can avoid having to do questionable | |
1260 | * sequence-number comparisons on buffer last_rendering_seqnos, and associate | |
1261 | * an emission time with seqnos for tracking how far ahead of the GPU we are. | |
1262 | */ | |
1263 | struct drm_i915_gem_request { | |
852835f3 ZN |
1264 | /** On Which ring this request was generated */ |
1265 | struct intel_ring_buffer *ring; | |
1266 | ||
673a394b EA |
1267 | /** GEM sequence number associated with this request. */ |
1268 | uint32_t seqno; | |
1269 | ||
a71d8d94 CW |
1270 | /** Postion in the ringbuffer of the end of the request */ |
1271 | u32 tail; | |
1272 | ||
673a394b EA |
1273 | /** Time at which this request was emitted, in jiffies. */ |
1274 | unsigned long emitted_jiffies; | |
1275 | ||
b962442e | 1276 | /** global list entry for this request */ |
673a394b | 1277 | struct list_head list; |
b962442e | 1278 | |
f787a5f5 | 1279 | struct drm_i915_file_private *file_priv; |
b962442e EA |
1280 | /** file_priv list entry for this request */ |
1281 | struct list_head client_list; | |
673a394b EA |
1282 | }; |
1283 | ||
1284 | struct drm_i915_file_private { | |
1285 | struct { | |
99057c81 | 1286 | spinlock_t lock; |
b962442e | 1287 | struct list_head request_list; |
673a394b | 1288 | } mm; |
40521054 | 1289 | struct idr context_idr; |
673a394b EA |
1290 | }; |
1291 | ||
cae5852d ZN |
1292 | #define INTEL_INFO(dev) (((struct drm_i915_private *) (dev)->dev_private)->info) |
1293 | ||
1294 | #define IS_I830(dev) ((dev)->pci_device == 0x3577) | |
1295 | #define IS_845G(dev) ((dev)->pci_device == 0x2562) | |
1296 | #define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x) | |
1297 | #define IS_I865G(dev) ((dev)->pci_device == 0x2572) | |
1298 | #define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g) | |
1299 | #define IS_I915GM(dev) ((dev)->pci_device == 0x2592) | |
1300 | #define IS_I945G(dev) ((dev)->pci_device == 0x2772) | |
1301 | #define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm) | |
1302 | #define IS_BROADWATER(dev) (INTEL_INFO(dev)->is_broadwater) | |
1303 | #define IS_CRESTLINE(dev) (INTEL_INFO(dev)->is_crestline) | |
1304 | #define IS_GM45(dev) ((dev)->pci_device == 0x2A42) | |
1305 | #define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x) | |
1306 | #define IS_PINEVIEW_G(dev) ((dev)->pci_device == 0xa001) | |
1307 | #define IS_PINEVIEW_M(dev) ((dev)->pci_device == 0xa011) | |
1308 | #define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview) | |
1309 | #define IS_G33(dev) (INTEL_INFO(dev)->is_g33) | |
1310 | #define IS_IRONLAKE_D(dev) ((dev)->pci_device == 0x0042) | |
1311 | #define IS_IRONLAKE_M(dev) ((dev)->pci_device == 0x0046) | |
4b65177b | 1312 | #define IS_IVYBRIDGE(dev) (INTEL_INFO(dev)->is_ivybridge) |
8ab43976 JB |
1313 | #define IS_IVB_GT1(dev) ((dev)->pci_device == 0x0156 || \ |
1314 | (dev)->pci_device == 0x0152 || \ | |
1315 | (dev)->pci_device == 0x015a) | |
6547fbdb DV |
1316 | #define IS_SNB_GT1(dev) ((dev)->pci_device == 0x0102 || \ |
1317 | (dev)->pci_device == 0x0106 || \ | |
1318 | (dev)->pci_device == 0x010A) | |
70a3eb7a | 1319 | #define IS_VALLEYVIEW(dev) (INTEL_INFO(dev)->is_valleyview) |
4cae9ae0 | 1320 | #define IS_HASWELL(dev) (INTEL_INFO(dev)->is_haswell) |
cae5852d | 1321 | #define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile) |
d567b07f PZ |
1322 | #define IS_ULT(dev) (IS_HASWELL(dev) && \ |
1323 | ((dev)->pci_device & 0xFF00) == 0x0A00) | |
cae5852d | 1324 | |
85436696 JB |
1325 | /* |
1326 | * The genX designation typically refers to the render engine, so render | |
1327 | * capability related checks should use IS_GEN, while display and other checks | |
1328 | * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular | |
1329 | * chips, etc.). | |
1330 | */ | |
cae5852d ZN |
1331 | #define IS_GEN2(dev) (INTEL_INFO(dev)->gen == 2) |
1332 | #define IS_GEN3(dev) (INTEL_INFO(dev)->gen == 3) | |
1333 | #define IS_GEN4(dev) (INTEL_INFO(dev)->gen == 4) | |
1334 | #define IS_GEN5(dev) (INTEL_INFO(dev)->gen == 5) | |
1335 | #define IS_GEN6(dev) (INTEL_INFO(dev)->gen == 6) | |
85436696 | 1336 | #define IS_GEN7(dev) (INTEL_INFO(dev)->gen == 7) |
cae5852d ZN |
1337 | |
1338 | #define HAS_BSD(dev) (INTEL_INFO(dev)->has_bsd_ring) | |
1339 | #define HAS_BLT(dev) (INTEL_INFO(dev)->has_blt_ring) | |
3d29b842 | 1340 | #define HAS_LLC(dev) (INTEL_INFO(dev)->has_llc) |
cae5852d ZN |
1341 | #define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws) |
1342 | ||
254f965c | 1343 | #define HAS_HW_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 6) |
93553609 | 1344 | #define HAS_ALIASING_PPGTT(dev) (INTEL_INFO(dev)->gen >=6 && !IS_VALLEYVIEW(dev)) |
1d2a314c | 1345 | |
05394f39 | 1346 | #define HAS_OVERLAY(dev) (INTEL_INFO(dev)->has_overlay) |
cae5852d ZN |
1347 | #define OVERLAY_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->overlay_needs_physical) |
1348 | ||
b45305fc DV |
1349 | /* Early gen2 have a totally busted CS tlb and require pinned batches. */ |
1350 | #define HAS_BROKEN_CS_TLB(dev) (IS_I830(dev) || IS_845G(dev)) | |
1351 | ||
cae5852d ZN |
1352 | /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte |
1353 | * rows, which changed the alignment requirements and fence programming. | |
1354 | */ | |
1355 | #define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \ | |
1356 | IS_I915GM(dev))) | |
1357 | #define SUPPORTS_DIGITAL_OUTPUTS(dev) (!IS_GEN2(dev) && !IS_PINEVIEW(dev)) | |
1358 | #define SUPPORTS_INTEGRATED_HDMI(dev) (IS_G4X(dev) || IS_GEN5(dev)) | |
1359 | #define SUPPORTS_INTEGRATED_DP(dev) (IS_G4X(dev) || IS_GEN5(dev)) | |
1360 | #define SUPPORTS_EDP(dev) (IS_IRONLAKE_M(dev)) | |
1361 | #define SUPPORTS_TV(dev) (INTEL_INFO(dev)->supports_tv) | |
1362 | #define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug) | |
1363 | /* dsparb controlled by hw only */ | |
1364 | #define DSPARB_HWCONTROL(dev) (IS_G4X(dev) || IS_IRONLAKE(dev)) | |
1365 | ||
1366 | #define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2) | |
1367 | #define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr) | |
1368 | #define I915_HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc) | |
cae5852d | 1369 | |
eceae481 | 1370 | #define HAS_PIPE_CONTROL(dev) (INTEL_INFO(dev)->gen >= 5) |
cae5852d | 1371 | |
dd93be58 | 1372 | #define HAS_DDI(dev) (INTEL_INFO(dev)->has_ddi) |
86d52df6 | 1373 | #define HAS_POWER_WELL(dev) (IS_HASWELL(dev)) |
30568c45 | 1374 | #define HAS_FPGA_DBG_UNCLAIMED(dev) (INTEL_INFO(dev)->has_fpga_dbg) |
affa9354 | 1375 | |
17a303ec PZ |
1376 | #define INTEL_PCH_DEVICE_ID_MASK 0xff00 |
1377 | #define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00 | |
1378 | #define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00 | |
1379 | #define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00 | |
1380 | #define INTEL_PCH_LPT_DEVICE_ID_TYPE 0x8c00 | |
1381 | #define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE 0x9c00 | |
1382 | ||
cae5852d | 1383 | #define INTEL_PCH_TYPE(dev) (((struct drm_i915_private *)(dev)->dev_private)->pch_type) |
eb877ebf | 1384 | #define HAS_PCH_LPT(dev) (INTEL_PCH_TYPE(dev) == PCH_LPT) |
cae5852d ZN |
1385 | #define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT) |
1386 | #define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX) | |
40c7ead9 | 1387 | #define HAS_PCH_NOP(dev) (INTEL_PCH_TYPE(dev) == PCH_NOP) |
45e6e3a1 | 1388 | #define HAS_PCH_SPLIT(dev) (INTEL_PCH_TYPE(dev) != PCH_NONE) |
cae5852d | 1389 | |
b7884eb4 DV |
1390 | #define HAS_FORCE_WAKE(dev) (INTEL_INFO(dev)->has_force_wake) |
1391 | ||
f27b9265 | 1392 | #define HAS_L3_GPU_CACHE(dev) (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) |
e1ef7cc2 | 1393 | |
c8735b0c BW |
1394 | #define GT_FREQUENCY_MULTIPLIER 50 |
1395 | ||
05394f39 CW |
1396 | #include "i915_trace.h" |
1397 | ||
83b7f9ac ED |
1398 | /** |
1399 | * RC6 is a special power stage which allows the GPU to enter an very | |
1400 | * low-voltage mode when idle, using down to 0V while at this stage. This | |
1401 | * stage is entered automatically when the GPU is idle when RC6 support is | |
1402 | * enabled, and as soon as new workload arises GPU wakes up automatically as well. | |
1403 | * | |
1404 | * There are different RC6 modes available in Intel GPU, which differentiate | |
1405 | * among each other with the latency required to enter and leave RC6 and | |
1406 | * voltage consumed by the GPU in different states. | |
1407 | * | |
1408 | * The combination of the following flags define which states GPU is allowed | |
1409 | * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and | |
1410 | * RC6pp is deepest RC6. Their support by hardware varies according to the | |
1411 | * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one | |
1412 | * which brings the most power savings; deeper states save more power, but | |
1413 | * require higher latency to switch to and wake up. | |
1414 | */ | |
1415 | #define INTEL_RC6_ENABLE (1<<0) | |
1416 | #define INTEL_RC6p_ENABLE (1<<1) | |
1417 | #define INTEL_RC6pp_ENABLE (1<<2) | |
1418 | ||
c153f45f | 1419 | extern struct drm_ioctl_desc i915_ioctls[]; |
b3a83639 | 1420 | extern int i915_max_ioctl; |
a35d9d3c BW |
1421 | extern unsigned int i915_fbpercrtc __always_unused; |
1422 | extern int i915_panel_ignore_lid __read_mostly; | |
1423 | extern unsigned int i915_powersave __read_mostly; | |
f45b5557 | 1424 | extern int i915_semaphores __read_mostly; |
a35d9d3c | 1425 | extern unsigned int i915_lvds_downclock __read_mostly; |
121d527a | 1426 | extern int i915_lvds_channel_mode __read_mostly; |
4415e63b | 1427 | extern int i915_panel_use_ssc __read_mostly; |
a35d9d3c | 1428 | extern int i915_vbt_sdvo_panel_type __read_mostly; |
c0f372b3 | 1429 | extern int i915_enable_rc6 __read_mostly; |
4415e63b | 1430 | extern int i915_enable_fbc __read_mostly; |
a35d9d3c | 1431 | extern bool i915_enable_hangcheck __read_mostly; |
650dc07e | 1432 | extern int i915_enable_ppgtt __read_mostly; |
0a3af268 | 1433 | extern unsigned int i915_preliminary_hw_support __read_mostly; |
2124b72e | 1434 | extern int i915_disable_power_well __read_mostly; |
b3a83639 | 1435 | |
6a9ee8af DA |
1436 | extern int i915_suspend(struct drm_device *dev, pm_message_t state); |
1437 | extern int i915_resume(struct drm_device *dev); | |
7c1c2871 DA |
1438 | extern int i915_master_create(struct drm_device *dev, struct drm_master *master); |
1439 | extern void i915_master_destroy(struct drm_device *dev, struct drm_master *master); | |
1440 | ||
1da177e4 | 1441 | /* i915_dma.c */ |
d05c617e | 1442 | void i915_update_dri1_breadcrumb(struct drm_device *dev); |
84b1fd10 | 1443 | extern void i915_kernel_lost_context(struct drm_device * dev); |
22eae947 | 1444 | extern int i915_driver_load(struct drm_device *, unsigned long flags); |
ba8bbcf6 | 1445 | extern int i915_driver_unload(struct drm_device *); |
673a394b | 1446 | extern int i915_driver_open(struct drm_device *dev, struct drm_file *file_priv); |
84b1fd10 | 1447 | extern void i915_driver_lastclose(struct drm_device * dev); |
6c340eac EA |
1448 | extern void i915_driver_preclose(struct drm_device *dev, |
1449 | struct drm_file *file_priv); | |
673a394b EA |
1450 | extern void i915_driver_postclose(struct drm_device *dev, |
1451 | struct drm_file *file_priv); | |
84b1fd10 | 1452 | extern int i915_driver_device_is_agp(struct drm_device * dev); |
c43b5634 | 1453 | #ifdef CONFIG_COMPAT |
0d6aa60b DA |
1454 | extern long i915_compat_ioctl(struct file *filp, unsigned int cmd, |
1455 | unsigned long arg); | |
c43b5634 | 1456 | #endif |
673a394b | 1457 | extern int i915_emit_box(struct drm_device *dev, |
c4e7a414 CW |
1458 | struct drm_clip_rect *box, |
1459 | int DR1, int DR4); | |
8e96d9c4 | 1460 | extern int intel_gpu_reset(struct drm_device *dev); |
d4b8bb2a | 1461 | extern int i915_reset(struct drm_device *dev); |
7648fa99 JB |
1462 | extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv); |
1463 | extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv); | |
1464 | extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv); | |
1465 | extern void i915_update_gfx_val(struct drm_i915_private *dev_priv); | |
1466 | ||
073f34d9 | 1467 | extern void intel_console_resume(struct work_struct *work); |
af6061af | 1468 | |
1da177e4 | 1469 | /* i915_irq.c */ |
f65d9421 | 1470 | void i915_hangcheck_elapsed(unsigned long data); |
527f9e90 | 1471 | void i915_handle_error(struct drm_device *dev, bool wedged); |
1da177e4 | 1472 | |
f71d4af4 | 1473 | extern void intel_irq_init(struct drm_device *dev); |
20afbda2 | 1474 | extern void intel_hpd_init(struct drm_device *dev); |
990bbdad | 1475 | extern void intel_gt_init(struct drm_device *dev); |
16995a9f | 1476 | extern void intel_gt_reset(struct drm_device *dev); |
b1f14ad0 | 1477 | |
742cbee8 DV |
1478 | void i915_error_state_free(struct kref *error_ref); |
1479 | ||
7c463586 KP |
1480 | void |
1481 | i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask); | |
1482 | ||
1483 | void | |
1484 | i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask); | |
1485 | ||
0206e353 | 1486 | void intel_enable_asle(struct drm_device *dev); |
01c66889 | 1487 | |
3bd3c932 CW |
1488 | #ifdef CONFIG_DEBUG_FS |
1489 | extern void i915_destroy_error_state(struct drm_device *dev); | |
1490 | #else | |
1491 | #define i915_destroy_error_state(x) | |
1492 | #endif | |
1493 | ||
7c463586 | 1494 | |
673a394b EA |
1495 | /* i915_gem.c */ |
1496 | int i915_gem_init_ioctl(struct drm_device *dev, void *data, | |
1497 | struct drm_file *file_priv); | |
1498 | int i915_gem_create_ioctl(struct drm_device *dev, void *data, | |
1499 | struct drm_file *file_priv); | |
1500 | int i915_gem_pread_ioctl(struct drm_device *dev, void *data, | |
1501 | struct drm_file *file_priv); | |
1502 | int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data, | |
1503 | struct drm_file *file_priv); | |
1504 | int i915_gem_mmap_ioctl(struct drm_device *dev, void *data, | |
1505 | struct drm_file *file_priv); | |
de151cf6 JB |
1506 | int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data, |
1507 | struct drm_file *file_priv); | |
673a394b EA |
1508 | int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data, |
1509 | struct drm_file *file_priv); | |
1510 | int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data, | |
1511 | struct drm_file *file_priv); | |
1512 | int i915_gem_execbuffer(struct drm_device *dev, void *data, | |
1513 | struct drm_file *file_priv); | |
76446cac JB |
1514 | int i915_gem_execbuffer2(struct drm_device *dev, void *data, |
1515 | struct drm_file *file_priv); | |
673a394b EA |
1516 | int i915_gem_pin_ioctl(struct drm_device *dev, void *data, |
1517 | struct drm_file *file_priv); | |
1518 | int i915_gem_unpin_ioctl(struct drm_device *dev, void *data, | |
1519 | struct drm_file *file_priv); | |
1520 | int i915_gem_busy_ioctl(struct drm_device *dev, void *data, | |
1521 | struct drm_file *file_priv); | |
199adf40 BW |
1522 | int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data, |
1523 | struct drm_file *file); | |
1524 | int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data, | |
1525 | struct drm_file *file); | |
673a394b EA |
1526 | int i915_gem_throttle_ioctl(struct drm_device *dev, void *data, |
1527 | struct drm_file *file_priv); | |
3ef94daa CW |
1528 | int i915_gem_madvise_ioctl(struct drm_device *dev, void *data, |
1529 | struct drm_file *file_priv); | |
673a394b EA |
1530 | int i915_gem_entervt_ioctl(struct drm_device *dev, void *data, |
1531 | struct drm_file *file_priv); | |
1532 | int i915_gem_leavevt_ioctl(struct drm_device *dev, void *data, | |
1533 | struct drm_file *file_priv); | |
1534 | int i915_gem_set_tiling(struct drm_device *dev, void *data, | |
1535 | struct drm_file *file_priv); | |
1536 | int i915_gem_get_tiling(struct drm_device *dev, void *data, | |
1537 | struct drm_file *file_priv); | |
5a125c3c EA |
1538 | int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data, |
1539 | struct drm_file *file_priv); | |
23ba4fd0 BW |
1540 | int i915_gem_wait_ioctl(struct drm_device *dev, void *data, |
1541 | struct drm_file *file_priv); | |
673a394b | 1542 | void i915_gem_load(struct drm_device *dev); |
42dcedd4 CW |
1543 | void *i915_gem_object_alloc(struct drm_device *dev); |
1544 | void i915_gem_object_free(struct drm_i915_gem_object *obj); | |
673a394b | 1545 | int i915_gem_init_object(struct drm_gem_object *obj); |
37e680a1 CW |
1546 | void i915_gem_object_init(struct drm_i915_gem_object *obj, |
1547 | const struct drm_i915_gem_object_ops *ops); | |
05394f39 CW |
1548 | struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev, |
1549 | size_t size); | |
673a394b | 1550 | void i915_gem_free_object(struct drm_gem_object *obj); |
42dcedd4 | 1551 | |
2021746e CW |
1552 | int __must_check i915_gem_object_pin(struct drm_i915_gem_object *obj, |
1553 | uint32_t alignment, | |
86a1ee26 CW |
1554 | bool map_and_fenceable, |
1555 | bool nonblocking); | |
05394f39 | 1556 | void i915_gem_object_unpin(struct drm_i915_gem_object *obj); |
2021746e | 1557 | int __must_check i915_gem_object_unbind(struct drm_i915_gem_object *obj); |
dd624afd | 1558 | int i915_gem_object_put_pages(struct drm_i915_gem_object *obj); |
05394f39 | 1559 | void i915_gem_release_mmap(struct drm_i915_gem_object *obj); |
673a394b | 1560 | void i915_gem_lastclose(struct drm_device *dev); |
f787a5f5 | 1561 | |
37e680a1 | 1562 | int __must_check i915_gem_object_get_pages(struct drm_i915_gem_object *obj); |
9da3da66 CW |
1563 | static inline struct page *i915_gem_object_get_page(struct drm_i915_gem_object *obj, int n) |
1564 | { | |
67d5a50c ID |
1565 | struct sg_page_iter sg_iter; |
1566 | ||
1567 | for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, n) | |
2db76d7c | 1568 | return sg_page_iter_page(&sg_iter); |
67d5a50c ID |
1569 | |
1570 | return NULL; | |
9da3da66 | 1571 | } |
a5570178 CW |
1572 | static inline void i915_gem_object_pin_pages(struct drm_i915_gem_object *obj) |
1573 | { | |
1574 | BUG_ON(obj->pages == NULL); | |
1575 | obj->pages_pin_count++; | |
1576 | } | |
1577 | static inline void i915_gem_object_unpin_pages(struct drm_i915_gem_object *obj) | |
1578 | { | |
1579 | BUG_ON(obj->pages_pin_count == 0); | |
1580 | obj->pages_pin_count--; | |
1581 | } | |
1582 | ||
54cf91dc | 1583 | int __must_check i915_mutex_lock_interruptible(struct drm_device *dev); |
2911a35b BW |
1584 | int i915_gem_object_sync(struct drm_i915_gem_object *obj, |
1585 | struct intel_ring_buffer *to); | |
54cf91dc | 1586 | void i915_gem_object_move_to_active(struct drm_i915_gem_object *obj, |
9d773091 | 1587 | struct intel_ring_buffer *ring); |
54cf91dc | 1588 | |
ff72145b DA |
1589 | int i915_gem_dumb_create(struct drm_file *file_priv, |
1590 | struct drm_device *dev, | |
1591 | struct drm_mode_create_dumb *args); | |
1592 | int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev, | |
1593 | uint32_t handle, uint64_t *offset); | |
1594 | int i915_gem_dumb_destroy(struct drm_file *file_priv, struct drm_device *dev, | |
0206e353 | 1595 | uint32_t handle); |
f787a5f5 CW |
1596 | /** |
1597 | * Returns true if seq1 is later than seq2. | |
1598 | */ | |
1599 | static inline bool | |
1600 | i915_seqno_passed(uint32_t seq1, uint32_t seq2) | |
1601 | { | |
1602 | return (int32_t)(seq1 - seq2) >= 0; | |
1603 | } | |
1604 | ||
fca26bb4 MK |
1605 | int __must_check i915_gem_get_seqno(struct drm_device *dev, u32 *seqno); |
1606 | int __must_check i915_gem_set_seqno(struct drm_device *dev, u32 seqno); | |
06d98131 | 1607 | int __must_check i915_gem_object_get_fence(struct drm_i915_gem_object *obj); |
d9e86c0e | 1608 | int __must_check i915_gem_object_put_fence(struct drm_i915_gem_object *obj); |
2021746e | 1609 | |
9a5a53b3 | 1610 | static inline bool |
1690e1eb CW |
1611 | i915_gem_object_pin_fence(struct drm_i915_gem_object *obj) |
1612 | { | |
1613 | if (obj->fence_reg != I915_FENCE_REG_NONE) { | |
1614 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; | |
1615 | dev_priv->fence_regs[obj->fence_reg].pin_count++; | |
9a5a53b3 CW |
1616 | return true; |
1617 | } else | |
1618 | return false; | |
1690e1eb CW |
1619 | } |
1620 | ||
1621 | static inline void | |
1622 | i915_gem_object_unpin_fence(struct drm_i915_gem_object *obj) | |
1623 | { | |
1624 | if (obj->fence_reg != I915_FENCE_REG_NONE) { | |
1625 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; | |
1626 | dev_priv->fence_regs[obj->fence_reg].pin_count--; | |
1627 | } | |
1628 | } | |
1629 | ||
b09a1fec | 1630 | void i915_gem_retire_requests(struct drm_device *dev); |
a71d8d94 | 1631 | void i915_gem_retire_requests_ring(struct intel_ring_buffer *ring); |
33196ded | 1632 | int __must_check i915_gem_check_wedge(struct i915_gpu_error *error, |
d6b2c790 | 1633 | bool interruptible); |
1f83fee0 DV |
1634 | static inline bool i915_reset_in_progress(struct i915_gpu_error *error) |
1635 | { | |
1636 | return unlikely(atomic_read(&error->reset_counter) | |
1637 | & I915_RESET_IN_PROGRESS_FLAG); | |
1638 | } | |
1639 | ||
1640 | static inline bool i915_terminally_wedged(struct i915_gpu_error *error) | |
1641 | { | |
1642 | return atomic_read(&error->reset_counter) == I915_WEDGED; | |
1643 | } | |
a71d8d94 | 1644 | |
069efc1d | 1645 | void i915_gem_reset(struct drm_device *dev); |
05394f39 | 1646 | void i915_gem_clflush_object(struct drm_i915_gem_object *obj); |
2021746e CW |
1647 | int __must_check i915_gem_object_set_domain(struct drm_i915_gem_object *obj, |
1648 | uint32_t read_domains, | |
1649 | uint32_t write_domain); | |
a8198eea | 1650 | int __must_check i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj); |
1070a42b | 1651 | int __must_check i915_gem_init(struct drm_device *dev); |
f691e2f4 | 1652 | int __must_check i915_gem_init_hw(struct drm_device *dev); |
b9524a1e | 1653 | void i915_gem_l3_remap(struct drm_device *dev); |
f691e2f4 | 1654 | void i915_gem_init_swizzling(struct drm_device *dev); |
79e53945 | 1655 | void i915_gem_cleanup_ringbuffer(struct drm_device *dev); |
b2da9fe5 | 1656 | int __must_check i915_gpu_idle(struct drm_device *dev); |
2021746e | 1657 | int __must_check i915_gem_idle(struct drm_device *dev); |
3bb73aba CW |
1658 | int i915_add_request(struct intel_ring_buffer *ring, |
1659 | struct drm_file *file, | |
acb868d3 | 1660 | u32 *seqno); |
199b2bc2 BW |
1661 | int __must_check i915_wait_seqno(struct intel_ring_buffer *ring, |
1662 | uint32_t seqno); | |
de151cf6 | 1663 | int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf); |
2021746e CW |
1664 | int __must_check |
1665 | i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, | |
1666 | bool write); | |
1667 | int __must_check | |
dabdfe02 CW |
1668 | i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write); |
1669 | int __must_check | |
2da3b9b9 CW |
1670 | i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj, |
1671 | u32 alignment, | |
2021746e | 1672 | struct intel_ring_buffer *pipelined); |
71acb5eb | 1673 | int i915_gem_attach_phys_object(struct drm_device *dev, |
05394f39 | 1674 | struct drm_i915_gem_object *obj, |
6eeefaf3 CW |
1675 | int id, |
1676 | int align); | |
71acb5eb | 1677 | void i915_gem_detach_phys_object(struct drm_device *dev, |
05394f39 | 1678 | struct drm_i915_gem_object *obj); |
71acb5eb | 1679 | void i915_gem_free_all_phys_object(struct drm_device *dev); |
05394f39 | 1680 | void i915_gem_release(struct drm_device *dev, struct drm_file *file); |
673a394b | 1681 | |
0fa87796 ID |
1682 | uint32_t |
1683 | i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode); | |
467cffba | 1684 | uint32_t |
d865110c ID |
1685 | i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size, |
1686 | int tiling_mode, bool fenced); | |
467cffba | 1687 | |
e4ffd173 CW |
1688 | int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj, |
1689 | enum i915_cache_level cache_level); | |
1690 | ||
1286ff73 DV |
1691 | struct drm_gem_object *i915_gem_prime_import(struct drm_device *dev, |
1692 | struct dma_buf *dma_buf); | |
1693 | ||
1694 | struct dma_buf *i915_gem_prime_export(struct drm_device *dev, | |
1695 | struct drm_gem_object *gem_obj, int flags); | |
1696 | ||
254f965c BW |
1697 | /* i915_gem_context.c */ |
1698 | void i915_gem_context_init(struct drm_device *dev); | |
1699 | void i915_gem_context_fini(struct drm_device *dev); | |
254f965c | 1700 | void i915_gem_context_close(struct drm_device *dev, struct drm_file *file); |
e0556841 BW |
1701 | int i915_switch_context(struct intel_ring_buffer *ring, |
1702 | struct drm_file *file, int to_id); | |
84624813 BW |
1703 | int i915_gem_context_create_ioctl(struct drm_device *dev, void *data, |
1704 | struct drm_file *file); | |
1705 | int i915_gem_context_destroy_ioctl(struct drm_device *dev, void *data, | |
1706 | struct drm_file *file); | |
1286ff73 | 1707 | |
76aaf220 | 1708 | /* i915_gem_gtt.c */ |
1d2a314c | 1709 | void i915_gem_cleanup_aliasing_ppgtt(struct drm_device *dev); |
7bddb01f DV |
1710 | void i915_ppgtt_bind_object(struct i915_hw_ppgtt *ppgtt, |
1711 | struct drm_i915_gem_object *obj, | |
1712 | enum i915_cache_level cache_level); | |
1713 | void i915_ppgtt_unbind_object(struct i915_hw_ppgtt *ppgtt, | |
1714 | struct drm_i915_gem_object *obj); | |
1d2a314c | 1715 | |
76aaf220 | 1716 | void i915_gem_restore_gtt_mappings(struct drm_device *dev); |
74163907 DV |
1717 | int __must_check i915_gem_gtt_prepare_object(struct drm_i915_gem_object *obj); |
1718 | void i915_gem_gtt_bind_object(struct drm_i915_gem_object *obj, | |
e4ffd173 | 1719 | enum i915_cache_level cache_level); |
05394f39 | 1720 | void i915_gem_gtt_unbind_object(struct drm_i915_gem_object *obj); |
74163907 | 1721 | void i915_gem_gtt_finish_object(struct drm_i915_gem_object *obj); |
d7e5008f BW |
1722 | void i915_gem_init_global_gtt(struct drm_device *dev); |
1723 | void i915_gem_setup_global_gtt(struct drm_device *dev, unsigned long start, | |
1724 | unsigned long mappable_end, unsigned long end); | |
e76e9aeb | 1725 | int i915_gem_gtt_init(struct drm_device *dev); |
d09105c6 | 1726 | static inline void i915_gem_chipset_flush(struct drm_device *dev) |
e76e9aeb BW |
1727 | { |
1728 | if (INTEL_INFO(dev)->gen < 6) | |
1729 | intel_gtt_chipset_flush(); | |
1730 | } | |
1731 | ||
76aaf220 | 1732 | |
b47eb4a2 | 1733 | /* i915_gem_evict.c */ |
2021746e | 1734 | int __must_check i915_gem_evict_something(struct drm_device *dev, int min_size, |
42d6ab48 CW |
1735 | unsigned alignment, |
1736 | unsigned cache_level, | |
86a1ee26 CW |
1737 | bool mappable, |
1738 | bool nonblock); | |
6c085a72 | 1739 | int i915_gem_evict_everything(struct drm_device *dev); |
b47eb4a2 | 1740 | |
9797fbfb CW |
1741 | /* i915_gem_stolen.c */ |
1742 | int i915_gem_init_stolen(struct drm_device *dev); | |
11be49eb CW |
1743 | int i915_gem_stolen_setup_compression(struct drm_device *dev, int size); |
1744 | void i915_gem_stolen_cleanup_compression(struct drm_device *dev); | |
9797fbfb | 1745 | void i915_gem_cleanup_stolen(struct drm_device *dev); |
0104fdbb CW |
1746 | struct drm_i915_gem_object * |
1747 | i915_gem_object_create_stolen(struct drm_device *dev, u32 size); | |
866d12b4 CW |
1748 | struct drm_i915_gem_object * |
1749 | i915_gem_object_create_stolen_for_preallocated(struct drm_device *dev, | |
1750 | u32 stolen_offset, | |
1751 | u32 gtt_offset, | |
1752 | u32 size); | |
0104fdbb | 1753 | void i915_gem_object_release_stolen(struct drm_i915_gem_object *obj); |
9797fbfb | 1754 | |
673a394b | 1755 | /* i915_gem_tiling.c */ |
e9b73c67 CW |
1756 | inline static bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj) |
1757 | { | |
1758 | drm_i915_private_t *dev_priv = obj->base.dev->dev_private; | |
1759 | ||
1760 | return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 && | |
1761 | obj->tiling_mode != I915_TILING_NONE; | |
1762 | } | |
1763 | ||
673a394b | 1764 | void i915_gem_detect_bit_6_swizzle(struct drm_device *dev); |
05394f39 CW |
1765 | void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj); |
1766 | void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj); | |
673a394b EA |
1767 | |
1768 | /* i915_gem_debug.c */ | |
05394f39 | 1769 | void i915_gem_dump_object(struct drm_i915_gem_object *obj, int len, |
673a394b | 1770 | const char *where, uint32_t mark); |
23bc5982 CW |
1771 | #if WATCH_LISTS |
1772 | int i915_verify_lists(struct drm_device *dev); | |
673a394b | 1773 | #else |
23bc5982 | 1774 | #define i915_verify_lists(dev) 0 |
673a394b | 1775 | #endif |
05394f39 CW |
1776 | void i915_gem_object_check_coherency(struct drm_i915_gem_object *obj, |
1777 | int handle); | |
1778 | void i915_gem_dump_object(struct drm_i915_gem_object *obj, int len, | |
673a394b | 1779 | const char *where, uint32_t mark); |
1da177e4 | 1780 | |
2017263e | 1781 | /* i915_debugfs.c */ |
27c202ad BG |
1782 | int i915_debugfs_init(struct drm_minor *minor); |
1783 | void i915_debugfs_cleanup(struct drm_minor *minor); | |
2017263e | 1784 | |
317c35d1 JB |
1785 | /* i915_suspend.c */ |
1786 | extern int i915_save_state(struct drm_device *dev); | |
1787 | extern int i915_restore_state(struct drm_device *dev); | |
0a3e67a4 | 1788 | |
d8157a36 DV |
1789 | /* i915_ums.c */ |
1790 | void i915_save_display_reg(struct drm_device *dev); | |
1791 | void i915_restore_display_reg(struct drm_device *dev); | |
317c35d1 | 1792 | |
0136db58 BW |
1793 | /* i915_sysfs.c */ |
1794 | void i915_setup_sysfs(struct drm_device *dev_priv); | |
1795 | void i915_teardown_sysfs(struct drm_device *dev_priv); | |
1796 | ||
f899fc64 CW |
1797 | /* intel_i2c.c */ |
1798 | extern int intel_setup_gmbus(struct drm_device *dev); | |
1799 | extern void intel_teardown_gmbus(struct drm_device *dev); | |
3bd7d909 DK |
1800 | extern inline bool intel_gmbus_is_port_valid(unsigned port) |
1801 | { | |
2ed06c93 | 1802 | return (port >= GMBUS_PORT_SSC && port <= GMBUS_PORT_DPD); |
3bd7d909 DK |
1803 | } |
1804 | ||
1805 | extern struct i2c_adapter *intel_gmbus_get_adapter( | |
1806 | struct drm_i915_private *dev_priv, unsigned port); | |
e957d772 CW |
1807 | extern void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed); |
1808 | extern void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit); | |
b8232e90 CW |
1809 | extern inline bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter) |
1810 | { | |
1811 | return container_of(adapter, struct intel_gmbus, adapter)->force_bit; | |
1812 | } | |
f899fc64 CW |
1813 | extern void intel_i2c_reset(struct drm_device *dev); |
1814 | ||
3b617967 | 1815 | /* intel_opregion.c */ |
44834a67 CW |
1816 | extern int intel_opregion_setup(struct drm_device *dev); |
1817 | #ifdef CONFIG_ACPI | |
1818 | extern void intel_opregion_init(struct drm_device *dev); | |
1819 | extern void intel_opregion_fini(struct drm_device *dev); | |
3b617967 CW |
1820 | extern void intel_opregion_asle_intr(struct drm_device *dev); |
1821 | extern void intel_opregion_gse_intr(struct drm_device *dev); | |
1822 | extern void intel_opregion_enable_asle(struct drm_device *dev); | |
65e082c9 | 1823 | #else |
44834a67 CW |
1824 | static inline void intel_opregion_init(struct drm_device *dev) { return; } |
1825 | static inline void intel_opregion_fini(struct drm_device *dev) { return; } | |
3b617967 CW |
1826 | static inline void intel_opregion_asle_intr(struct drm_device *dev) { return; } |
1827 | static inline void intel_opregion_gse_intr(struct drm_device *dev) { return; } | |
1828 | static inline void intel_opregion_enable_asle(struct drm_device *dev) { return; } | |
65e082c9 | 1829 | #endif |
8ee1c3db | 1830 | |
723bfd70 JB |
1831 | /* intel_acpi.c */ |
1832 | #ifdef CONFIG_ACPI | |
1833 | extern void intel_register_dsm_handler(void); | |
1834 | extern void intel_unregister_dsm_handler(void); | |
1835 | #else | |
1836 | static inline void intel_register_dsm_handler(void) { return; } | |
1837 | static inline void intel_unregister_dsm_handler(void) { return; } | |
1838 | #endif /* CONFIG_ACPI */ | |
1839 | ||
79e53945 | 1840 | /* modesetting */ |
f817586c | 1841 | extern void intel_modeset_init_hw(struct drm_device *dev); |
79e53945 | 1842 | extern void intel_modeset_init(struct drm_device *dev); |
2c7111db | 1843 | extern void intel_modeset_gem_init(struct drm_device *dev); |
79e53945 | 1844 | extern void intel_modeset_cleanup(struct drm_device *dev); |
28d52043 | 1845 | extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state); |
45e2b5f6 DV |
1846 | extern void intel_modeset_setup_hw_state(struct drm_device *dev, |
1847 | bool force_restore); | |
44cec740 | 1848 | extern void i915_redisable_vga(struct drm_device *dev); |
ee5382ae | 1849 | extern bool intel_fbc_enabled(struct drm_device *dev); |
43a9539f | 1850 | extern void intel_disable_fbc(struct drm_device *dev); |
7648fa99 | 1851 | extern bool ironlake_set_drps(struct drm_device *dev, u8 val); |
dde86e2d | 1852 | extern void intel_init_pch_refclk(struct drm_device *dev); |
3b8d8d91 | 1853 | extern void gen6_set_rps(struct drm_device *dev, u8 val); |
0a073b84 JB |
1854 | extern void valleyview_set_rps(struct drm_device *dev, u8 val); |
1855 | extern int valleyview_rps_max_freq(struct drm_i915_private *dev_priv); | |
1856 | extern int valleyview_rps_min_freq(struct drm_i915_private *dev_priv); | |
0206e353 AJ |
1857 | extern void intel_detect_pch(struct drm_device *dev); |
1858 | extern int intel_trans_dp_port_sel(struct drm_crtc *crtc); | |
0136db58 | 1859 | extern int intel_enable_rc6(const struct drm_device *dev); |
3bad0781 | 1860 | |
2911a35b | 1861 | extern bool i915_semaphore_is_enabled(struct drm_device *dev); |
c0c7babc BW |
1862 | int i915_reg_read_ioctl(struct drm_device *dev, void *data, |
1863 | struct drm_file *file); | |
575155a9 | 1864 | |
6ef3d427 | 1865 | /* overlay */ |
3bd3c932 | 1866 | #ifdef CONFIG_DEBUG_FS |
6ef3d427 CW |
1867 | extern struct intel_overlay_error_state *intel_overlay_capture_error_state(struct drm_device *dev); |
1868 | extern void intel_overlay_print_error_state(struct seq_file *m, struct intel_overlay_error_state *error); | |
c4a1d9e4 CW |
1869 | |
1870 | extern struct intel_display_error_state *intel_display_capture_error_state(struct drm_device *dev); | |
1871 | extern void intel_display_print_error_state(struct seq_file *m, | |
1872 | struct drm_device *dev, | |
1873 | struct intel_display_error_state *error); | |
3bd3c932 | 1874 | #endif |
6ef3d427 | 1875 | |
b7287d80 BW |
1876 | /* On SNB platform, before reading ring registers forcewake bit |
1877 | * must be set to prevent GT core from power down and stale values being | |
1878 | * returned. | |
1879 | */ | |
fcca7926 BW |
1880 | void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv); |
1881 | void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv); | |
67a3744f | 1882 | int __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv); |
b7287d80 | 1883 | |
42c0526c BW |
1884 | int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u8 mbox, u32 *val); |
1885 | int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32 val); | |
a0e4e199 JB |
1886 | int valleyview_punit_read(struct drm_i915_private *dev_priv, u8 addr, u32 *val); |
1887 | int valleyview_punit_write(struct drm_i915_private *dev_priv, u8 addr, u32 val); | |
0a073b84 JB |
1888 | int valleyview_nc_read(struct drm_i915_private *dev_priv, u8 addr, u32 *val); |
1889 | ||
855ba3be JB |
1890 | int vlv_gpu_freq(int ddr_freq, int val); |
1891 | int vlv_freq_opcode(int ddr_freq, int val); | |
42c0526c | 1892 | |
5f75377d | 1893 | #define __i915_read(x, y) \ |
f7000883 | 1894 | u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg); |
fcca7926 | 1895 | |
5f75377d KP |
1896 | __i915_read(8, b) |
1897 | __i915_read(16, w) | |
1898 | __i915_read(32, l) | |
1899 | __i915_read(64, q) | |
1900 | #undef __i915_read | |
1901 | ||
1902 | #define __i915_write(x, y) \ | |
f7000883 AK |
1903 | void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x val); |
1904 | ||
5f75377d KP |
1905 | __i915_write(8, b) |
1906 | __i915_write(16, w) | |
1907 | __i915_write(32, l) | |
1908 | __i915_write(64, q) | |
1909 | #undef __i915_write | |
1910 | ||
1911 | #define I915_READ8(reg) i915_read8(dev_priv, (reg)) | |
1912 | #define I915_WRITE8(reg, val) i915_write8(dev_priv, (reg), (val)) | |
1913 | ||
1914 | #define I915_READ16(reg) i915_read16(dev_priv, (reg)) | |
1915 | #define I915_WRITE16(reg, val) i915_write16(dev_priv, (reg), (val)) | |
1916 | #define I915_READ16_NOTRACE(reg) readw(dev_priv->regs + (reg)) | |
1917 | #define I915_WRITE16_NOTRACE(reg, val) writew(val, dev_priv->regs + (reg)) | |
1918 | ||
1919 | #define I915_READ(reg) i915_read32(dev_priv, (reg)) | |
1920 | #define I915_WRITE(reg, val) i915_write32(dev_priv, (reg), (val)) | |
cae5852d ZN |
1921 | #define I915_READ_NOTRACE(reg) readl(dev_priv->regs + (reg)) |
1922 | #define I915_WRITE_NOTRACE(reg, val) writel(val, dev_priv->regs + (reg)) | |
5f75377d KP |
1923 | |
1924 | #define I915_WRITE64(reg, val) i915_write64(dev_priv, (reg), (val)) | |
1925 | #define I915_READ64(reg) i915_read64(dev_priv, (reg)) | |
cae5852d ZN |
1926 | |
1927 | #define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg) | |
1928 | #define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg) | |
1929 | ||
55bc60db VS |
1930 | /* "Broadcast RGB" property */ |
1931 | #define INTEL_BROADCAST_RGB_AUTO 0 | |
1932 | #define INTEL_BROADCAST_RGB_FULL 1 | |
1933 | #define INTEL_BROADCAST_RGB_LIMITED 2 | |
ba4f01a3 | 1934 | |
766aa1c4 VS |
1935 | static inline uint32_t i915_vgacntrl_reg(struct drm_device *dev) |
1936 | { | |
1937 | if (HAS_PCH_SPLIT(dev)) | |
1938 | return CPU_VGACNTRL; | |
1939 | else if (IS_VALLEYVIEW(dev)) | |
1940 | return VLV_VGACNTRL; | |
1941 | else | |
1942 | return VGACNTRL; | |
1943 | } | |
1944 | ||
2bb4629a VS |
1945 | static inline void __user *to_user_ptr(u64 address) |
1946 | { | |
1947 | return (void __user *)(uintptr_t)address; | |
1948 | } | |
1949 | ||
1da177e4 | 1950 | #endif |