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1da177e4 LT |
1 | /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*- |
2 | */ | |
0d6aa60b | 3 | /* |
bc54fd1a | 4 | * |
1da177e4 LT |
5 | * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. |
6 | * All Rights Reserved. | |
bc54fd1a DA |
7 | * |
8 | * Permission is hereby granted, free of charge, to any person obtaining a | |
9 | * copy of this software and associated documentation files (the | |
10 | * "Software"), to deal in the Software without restriction, including | |
11 | * without limitation the rights to use, copy, modify, merge, publish, | |
12 | * distribute, sub license, and/or sell copies of the Software, and to | |
13 | * permit persons to whom the Software is furnished to do so, subject to | |
14 | * the following conditions: | |
15 | * | |
16 | * The above copyright notice and this permission notice (including the | |
17 | * next paragraph) shall be included in all copies or substantial portions | |
18 | * of the Software. | |
19 | * | |
20 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS | |
21 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
22 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. | |
23 | * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR | |
24 | * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, | |
25 | * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE | |
26 | * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. | |
27 | * | |
0d6aa60b | 28 | */ |
1da177e4 LT |
29 | |
30 | #ifndef _I915_DRV_H_ | |
31 | #define _I915_DRV_H_ | |
32 | ||
585fb111 | 33 | #include "i915_reg.h" |
79e53945 | 34 | #include "intel_bios.h" |
8187a2b7 | 35 | #include "intel_ringbuffer.h" |
0839ccb8 | 36 | #include <linux/io-mapping.h> |
f899fc64 | 37 | #include <linux/i2c.h> |
c167a6fc | 38 | #include <linux/i2c-algo-bit.h> |
0ade6386 | 39 | #include <drm/intel-gtt.h> |
aaa6fd2a | 40 | #include <linux/backlight.h> |
2911a35b | 41 | #include <linux/intel-iommu.h> |
742cbee8 | 42 | #include <linux/kref.h> |
585fb111 | 43 | |
1da177e4 LT |
44 | /* General customization: |
45 | */ | |
46 | ||
47 | #define DRIVER_AUTHOR "Tungsten Graphics, Inc." | |
48 | ||
49 | #define DRIVER_NAME "i915" | |
50 | #define DRIVER_DESC "Intel Graphics" | |
673a394b | 51 | #define DRIVER_DATE "20080730" |
1da177e4 | 52 | |
317c35d1 JB |
53 | enum pipe { |
54 | PIPE_A = 0, | |
55 | PIPE_B, | |
9db4a9c7 JB |
56 | PIPE_C, |
57 | I915_MAX_PIPES | |
317c35d1 | 58 | }; |
9db4a9c7 | 59 | #define pipe_name(p) ((p) + 'A') |
317c35d1 | 60 | |
80824003 JB |
61 | enum plane { |
62 | PLANE_A = 0, | |
63 | PLANE_B, | |
9db4a9c7 | 64 | PLANE_C, |
80824003 | 65 | }; |
9db4a9c7 | 66 | #define plane_name(p) ((p) + 'A') |
52440211 | 67 | |
2b139522 ED |
68 | enum port { |
69 | PORT_A = 0, | |
70 | PORT_B, | |
71 | PORT_C, | |
72 | PORT_D, | |
73 | PORT_E, | |
74 | I915_MAX_PORTS | |
75 | }; | |
76 | #define port_name(p) ((p) + 'A') | |
77 | ||
62fdfeaf EA |
78 | #define I915_GEM_GPU_DOMAINS (~(I915_GEM_DOMAIN_CPU | I915_GEM_DOMAIN_GTT)) |
79 | ||
9db4a9c7 JB |
80 | #define for_each_pipe(p) for ((p) = 0; (p) < dev_priv->num_pipe; (p)++) |
81 | ||
6c2b7c12 DV |
82 | #define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \ |
83 | list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \ | |
84 | if ((intel_encoder)->base.crtc == (__crtc)) | |
85 | ||
ee7b9f93 JB |
86 | struct intel_pch_pll { |
87 | int refcount; /* count of number of CRTCs sharing this PLL */ | |
88 | int active; /* count of number of active CRTCs (i.e. DPMS on) */ | |
89 | bool on; /* is the PLL actually active? Disabled during modeset */ | |
90 | int pll_reg; | |
91 | int fp0_reg; | |
92 | int fp1_reg; | |
93 | }; | |
94 | #define I915_NUM_PLLS 2 | |
95 | ||
1da177e4 LT |
96 | /* Interface history: |
97 | * | |
98 | * 1.1: Original. | |
0d6aa60b DA |
99 | * 1.2: Add Power Management |
100 | * 1.3: Add vblank support | |
de227f5f | 101 | * 1.4: Fix cmdbuffer path, add heap destroy |
702880f2 | 102 | * 1.5: Add vblank pipe configuration |
2228ed67 MD |
103 | * 1.6: - New ioctl for scheduling buffer swaps on vertical blank |
104 | * - Support vertical blank on secondary display pipe | |
1da177e4 LT |
105 | */ |
106 | #define DRIVER_MAJOR 1 | |
2228ed67 | 107 | #define DRIVER_MINOR 6 |
1da177e4 LT |
108 | #define DRIVER_PATCHLEVEL 0 |
109 | ||
673a394b | 110 | #define WATCH_COHERENCY 0 |
23bc5982 | 111 | #define WATCH_LISTS 0 |
42d6ab48 | 112 | #define WATCH_GTT 0 |
673a394b | 113 | |
71acb5eb DA |
114 | #define I915_GEM_PHYS_CURSOR_0 1 |
115 | #define I915_GEM_PHYS_CURSOR_1 2 | |
116 | #define I915_GEM_PHYS_OVERLAY_REGS 3 | |
117 | #define I915_MAX_PHYS_OBJECT (I915_GEM_PHYS_OVERLAY_REGS) | |
118 | ||
119 | struct drm_i915_gem_phys_object { | |
120 | int id; | |
121 | struct page **page_list; | |
122 | drm_dma_handle_t *handle; | |
05394f39 | 123 | struct drm_i915_gem_object *cur_obj; |
71acb5eb DA |
124 | }; |
125 | ||
1da177e4 LT |
126 | struct mem_block { |
127 | struct mem_block *next; | |
128 | struct mem_block *prev; | |
129 | int start; | |
130 | int size; | |
6c340eac | 131 | struct drm_file *file_priv; /* NULL: free, -1: heap, other: real files */ |
1da177e4 LT |
132 | }; |
133 | ||
0a3e67a4 JB |
134 | struct opregion_header; |
135 | struct opregion_acpi; | |
136 | struct opregion_swsci; | |
137 | struct opregion_asle; | |
8d715f00 | 138 | struct drm_i915_private; |
0a3e67a4 | 139 | |
8ee1c3db | 140 | struct intel_opregion { |
5bc4418b BW |
141 | struct opregion_header __iomem *header; |
142 | struct opregion_acpi __iomem *acpi; | |
143 | struct opregion_swsci __iomem *swsci; | |
144 | struct opregion_asle __iomem *asle; | |
145 | void __iomem *vbt; | |
01fe9dbd | 146 | u32 __iomem *lid_state; |
8ee1c3db | 147 | }; |
44834a67 | 148 | #define OPREGION_SIZE (8*1024) |
8ee1c3db | 149 | |
6ef3d427 CW |
150 | struct intel_overlay; |
151 | struct intel_overlay_error_state; | |
152 | ||
7c1c2871 DA |
153 | struct drm_i915_master_private { |
154 | drm_local_map_t *sarea; | |
155 | struct _drm_i915_sarea *sarea_priv; | |
156 | }; | |
de151cf6 | 157 | #define I915_FENCE_REG_NONE -1 |
4b9de737 DV |
158 | #define I915_MAX_NUM_FENCES 16 |
159 | /* 16 fences + sign bit for FENCE_REG_NONE */ | |
160 | #define I915_MAX_NUM_FENCE_BITS 5 | |
de151cf6 JB |
161 | |
162 | struct drm_i915_fence_reg { | |
007cc8ac | 163 | struct list_head lru_list; |
caea7476 | 164 | struct drm_i915_gem_object *obj; |
1690e1eb | 165 | int pin_count; |
de151cf6 | 166 | }; |
7c1c2871 | 167 | |
9b9d172d | 168 | struct sdvo_device_mapping { |
e957d772 | 169 | u8 initialized; |
9b9d172d | 170 | u8 dvo_port; |
171 | u8 slave_addr; | |
172 | u8 dvo_wiring; | |
e957d772 | 173 | u8 i2c_pin; |
b1083333 | 174 | u8 ddc_pin; |
9b9d172d | 175 | }; |
176 | ||
c4a1d9e4 CW |
177 | struct intel_display_error_state; |
178 | ||
63eeaf38 | 179 | struct drm_i915_error_state { |
742cbee8 | 180 | struct kref ref; |
63eeaf38 JB |
181 | u32 eir; |
182 | u32 pgtbl_er; | |
be998e2e | 183 | u32 ier; |
b9a3906b | 184 | u32 ccid; |
9574b3fe | 185 | bool waiting[I915_NUM_RINGS]; |
9db4a9c7 | 186 | u32 pipestat[I915_MAX_PIPES]; |
c1cd90ed DV |
187 | u32 tail[I915_NUM_RINGS]; |
188 | u32 head[I915_NUM_RINGS]; | |
d27b1e0e DV |
189 | u32 ipeir[I915_NUM_RINGS]; |
190 | u32 ipehr[I915_NUM_RINGS]; | |
191 | u32 instdone[I915_NUM_RINGS]; | |
192 | u32 acthd[I915_NUM_RINGS]; | |
7e3b8737 | 193 | u32 semaphore_mboxes[I915_NUM_RINGS][I915_NUM_RINGS - 1]; |
12f55818 | 194 | u32 rc_psmi[I915_NUM_RINGS]; /* sleep state */ |
7e3b8737 DV |
195 | /* our own tracking of ring head and tail */ |
196 | u32 cpu_ring_head[I915_NUM_RINGS]; | |
197 | u32 cpu_ring_tail[I915_NUM_RINGS]; | |
1d8f38f4 | 198 | u32 error; /* gen6+ */ |
71e172e8 | 199 | u32 err_int; /* gen7 */ |
c1cd90ed DV |
200 | u32 instpm[I915_NUM_RINGS]; |
201 | u32 instps[I915_NUM_RINGS]; | |
050ee91f | 202 | u32 extra_instdone[I915_NUM_INSTDONE_REG]; |
d27b1e0e | 203 | u32 seqno[I915_NUM_RINGS]; |
9df30794 | 204 | u64 bbaddr; |
33f3f518 DV |
205 | u32 fault_reg[I915_NUM_RINGS]; |
206 | u32 done_reg; | |
c1cd90ed | 207 | u32 faddr[I915_NUM_RINGS]; |
4b9de737 | 208 | u64 fence[I915_MAX_NUM_FENCES]; |
63eeaf38 | 209 | struct timeval time; |
52d39a21 CW |
210 | struct drm_i915_error_ring { |
211 | struct drm_i915_error_object { | |
212 | int page_count; | |
213 | u32 gtt_offset; | |
214 | u32 *pages[0]; | |
215 | } *ringbuffer, *batchbuffer; | |
216 | struct drm_i915_error_request { | |
217 | long jiffies; | |
218 | u32 seqno; | |
ee4f42b1 | 219 | u32 tail; |
52d39a21 CW |
220 | } *requests; |
221 | int num_requests; | |
222 | } ring[I915_NUM_RINGS]; | |
9df30794 | 223 | struct drm_i915_error_buffer { |
a779e5ab | 224 | u32 size; |
9df30794 | 225 | u32 name; |
0201f1ec | 226 | u32 rseqno, wseqno; |
9df30794 CW |
227 | u32 gtt_offset; |
228 | u32 read_domains; | |
229 | u32 write_domain; | |
4b9de737 | 230 | s32 fence_reg:I915_MAX_NUM_FENCE_BITS; |
9df30794 CW |
231 | s32 pinned:2; |
232 | u32 tiling:2; | |
233 | u32 dirty:1; | |
234 | u32 purgeable:1; | |
5d1333fc | 235 | s32 ring:4; |
93dfb40c | 236 | u32 cache_level:2; |
c724e8a9 CW |
237 | } *active_bo, *pinned_bo; |
238 | u32 active_bo_count, pinned_bo_count; | |
6ef3d427 | 239 | struct intel_overlay_error_state *overlay; |
c4a1d9e4 | 240 | struct intel_display_error_state *display; |
63eeaf38 JB |
241 | }; |
242 | ||
e70236a8 | 243 | struct drm_i915_display_funcs { |
ee5382ae | 244 | bool (*fbc_enabled)(struct drm_device *dev); |
e70236a8 JB |
245 | void (*enable_fbc)(struct drm_crtc *crtc, unsigned long interval); |
246 | void (*disable_fbc)(struct drm_device *dev); | |
247 | int (*get_display_clock_speed)(struct drm_device *dev); | |
248 | int (*get_fifo_size)(struct drm_device *dev, int plane); | |
d210246a | 249 | void (*update_wm)(struct drm_device *dev); |
b840d907 JB |
250 | void (*update_sprite_wm)(struct drm_device *dev, int pipe, |
251 | uint32_t sprite_width, int pixel_size); | |
1f8eeabf ED |
252 | void (*update_linetime_wm)(struct drm_device *dev, int pipe, |
253 | struct drm_display_mode *mode); | |
f564048e EA |
254 | int (*crtc_mode_set)(struct drm_crtc *crtc, |
255 | struct drm_display_mode *mode, | |
256 | struct drm_display_mode *adjusted_mode, | |
257 | int x, int y, | |
258 | struct drm_framebuffer *old_fb); | |
76e5a89c DV |
259 | void (*crtc_enable)(struct drm_crtc *crtc); |
260 | void (*crtc_disable)(struct drm_crtc *crtc); | |
ee7b9f93 | 261 | void (*off)(struct drm_crtc *crtc); |
e0dac65e WF |
262 | void (*write_eld)(struct drm_connector *connector, |
263 | struct drm_crtc *crtc); | |
674cf967 | 264 | void (*fdi_link_train)(struct drm_crtc *crtc); |
6067aaea | 265 | void (*init_clock_gating)(struct drm_device *dev); |
645c62a5 | 266 | void (*init_pch_clock_gating)(struct drm_device *dev); |
8c9f3aaf JB |
267 | int (*queue_flip)(struct drm_device *dev, struct drm_crtc *crtc, |
268 | struct drm_framebuffer *fb, | |
269 | struct drm_i915_gem_object *obj); | |
17638cd6 JB |
270 | int (*update_plane)(struct drm_crtc *crtc, struct drm_framebuffer *fb, |
271 | int x, int y); | |
e70236a8 JB |
272 | /* clock updates for mode set */ |
273 | /* cursor updates */ | |
274 | /* render clock increase/decrease */ | |
275 | /* display clock increase/decrease */ | |
276 | /* pll clock increase/decrease */ | |
e70236a8 JB |
277 | }; |
278 | ||
990bbdad CW |
279 | struct drm_i915_gt_funcs { |
280 | void (*force_wake_get)(struct drm_i915_private *dev_priv); | |
281 | void (*force_wake_put)(struct drm_i915_private *dev_priv); | |
282 | }; | |
283 | ||
c96ea64e DV |
284 | #define DEV_INFO_FLAGS \ |
285 | DEV_INFO_FLAG(is_mobile) DEV_INFO_SEP \ | |
286 | DEV_INFO_FLAG(is_i85x) DEV_INFO_SEP \ | |
287 | DEV_INFO_FLAG(is_i915g) DEV_INFO_SEP \ | |
288 | DEV_INFO_FLAG(is_i945gm) DEV_INFO_SEP \ | |
289 | DEV_INFO_FLAG(is_g33) DEV_INFO_SEP \ | |
290 | DEV_INFO_FLAG(need_gfx_hws) DEV_INFO_SEP \ | |
291 | DEV_INFO_FLAG(is_g4x) DEV_INFO_SEP \ | |
292 | DEV_INFO_FLAG(is_pineview) DEV_INFO_SEP \ | |
293 | DEV_INFO_FLAG(is_broadwater) DEV_INFO_SEP \ | |
294 | DEV_INFO_FLAG(is_crestline) DEV_INFO_SEP \ | |
295 | DEV_INFO_FLAG(is_ivybridge) DEV_INFO_SEP \ | |
296 | DEV_INFO_FLAG(is_valleyview) DEV_INFO_SEP \ | |
297 | DEV_INFO_FLAG(is_haswell) DEV_INFO_SEP \ | |
298 | DEV_INFO_FLAG(has_force_wake) DEV_INFO_SEP \ | |
299 | DEV_INFO_FLAG(has_fbc) DEV_INFO_SEP \ | |
300 | DEV_INFO_FLAG(has_pipe_cxsr) DEV_INFO_SEP \ | |
301 | DEV_INFO_FLAG(has_hotplug) DEV_INFO_SEP \ | |
302 | DEV_INFO_FLAG(cursor_needs_physical) DEV_INFO_SEP \ | |
303 | DEV_INFO_FLAG(has_overlay) DEV_INFO_SEP \ | |
304 | DEV_INFO_FLAG(overlay_needs_physical) DEV_INFO_SEP \ | |
305 | DEV_INFO_FLAG(supports_tv) DEV_INFO_SEP \ | |
306 | DEV_INFO_FLAG(has_bsd_ring) DEV_INFO_SEP \ | |
307 | DEV_INFO_FLAG(has_blt_ring) DEV_INFO_SEP \ | |
308 | DEV_INFO_FLAG(has_llc) | |
309 | ||
cfdf1fa2 | 310 | struct intel_device_info { |
c96c3a8c | 311 | u8 gen; |
0206e353 AJ |
312 | u8 is_mobile:1; |
313 | u8 is_i85x:1; | |
314 | u8 is_i915g:1; | |
315 | u8 is_i945gm:1; | |
316 | u8 is_g33:1; | |
317 | u8 need_gfx_hws:1; | |
318 | u8 is_g4x:1; | |
319 | u8 is_pineview:1; | |
320 | u8 is_broadwater:1; | |
321 | u8 is_crestline:1; | |
322 | u8 is_ivybridge:1; | |
70a3eb7a | 323 | u8 is_valleyview:1; |
b7884eb4 | 324 | u8 has_force_wake:1; |
4cae9ae0 | 325 | u8 is_haswell:1; |
0206e353 AJ |
326 | u8 has_fbc:1; |
327 | u8 has_pipe_cxsr:1; | |
328 | u8 has_hotplug:1; | |
329 | u8 cursor_needs_physical:1; | |
330 | u8 has_overlay:1; | |
331 | u8 overlay_needs_physical:1; | |
332 | u8 supports_tv:1; | |
333 | u8 has_bsd_ring:1; | |
334 | u8 has_blt_ring:1; | |
3d29b842 | 335 | u8 has_llc:1; |
cfdf1fa2 KH |
336 | }; |
337 | ||
1d2a314c DV |
338 | #define I915_PPGTT_PD_ENTRIES 512 |
339 | #define I915_PPGTT_PT_ENTRIES 1024 | |
340 | struct i915_hw_ppgtt { | |
341 | unsigned num_pd_entries; | |
342 | struct page **pt_pages; | |
343 | uint32_t pd_offset; | |
344 | dma_addr_t *pt_dma_addr; | |
345 | dma_addr_t scratch_page_dma_addr; | |
346 | }; | |
347 | ||
40521054 BW |
348 | |
349 | /* This must match up with the value previously used for execbuf2.rsvd1. */ | |
350 | #define DEFAULT_CONTEXT_ID 0 | |
351 | struct i915_hw_context { | |
352 | int id; | |
e0556841 | 353 | bool is_initialized; |
40521054 BW |
354 | struct drm_i915_file_private *file_priv; |
355 | struct intel_ring_buffer *ring; | |
356 | struct drm_i915_gem_object *obj; | |
357 | }; | |
358 | ||
b5e50c3f | 359 | enum no_fbc_reason { |
bed4a673 | 360 | FBC_NO_OUTPUT, /* no outputs enabled to compress */ |
b5e50c3f JB |
361 | FBC_STOLEN_TOO_SMALL, /* not enough space to hold compressed buffers */ |
362 | FBC_UNSUPPORTED_MODE, /* interlace or doublescanned mode */ | |
363 | FBC_MODE_TOO_LARGE, /* mode too large for compression */ | |
364 | FBC_BAD_PLANE, /* fbc not supported on plane */ | |
365 | FBC_NOT_TILED, /* buffer not tiled */ | |
9c928d16 | 366 | FBC_MULTIPLE_PIPES, /* more than one pipe active */ |
c1a9f047 | 367 | FBC_MODULE_PARAM, |
b5e50c3f JB |
368 | }; |
369 | ||
3bad0781 | 370 | enum intel_pch { |
f0350830 | 371 | PCH_NONE = 0, /* No PCH present */ |
3bad0781 ZW |
372 | PCH_IBX, /* Ibexpeak PCH */ |
373 | PCH_CPT, /* Cougarpoint PCH */ | |
eb877ebf | 374 | PCH_LPT, /* Lynxpoint PCH */ |
3bad0781 ZW |
375 | }; |
376 | ||
b690e96c | 377 | #define QUIRK_PIPEA_FORCE (1<<0) |
435793df | 378 | #define QUIRK_LVDS_SSC_DISABLE (1<<1) |
4dca20ef | 379 | #define QUIRK_INVERT_BRIGHTNESS (1<<2) |
b690e96c | 380 | |
8be48d92 | 381 | struct intel_fbdev; |
1630fe75 | 382 | struct intel_fbc_work; |
38651674 | 383 | |
c2b9152f DV |
384 | struct intel_gmbus { |
385 | struct i2c_adapter adapter; | |
f6f808c8 | 386 | bool force_bit; |
c2b9152f | 387 | u32 reg0; |
36c785f0 | 388 | u32 gpio_reg; |
c167a6fc | 389 | struct i2c_algo_bit_data bit_algo; |
c2b9152f DV |
390 | struct drm_i915_private *dev_priv; |
391 | }; | |
392 | ||
1da177e4 | 393 | typedef struct drm_i915_private { |
673a394b EA |
394 | struct drm_device *dev; |
395 | ||
cfdf1fa2 KH |
396 | const struct intel_device_info *info; |
397 | ||
72bfa19c | 398 | int relative_constants_mode; |
ac5c4e76 | 399 | |
3043c60c | 400 | void __iomem *regs; |
990bbdad CW |
401 | |
402 | struct drm_i915_gt_funcs gt; | |
9f1f46a4 DV |
403 | /** gt_fifo_count and the subsequent register write are synchronized |
404 | * with dev->struct_mutex. */ | |
405 | unsigned gt_fifo_count; | |
406 | /** forcewake_count is protected by gt_lock */ | |
407 | unsigned forcewake_count; | |
408 | /** gt_lock is also taken in irq contexts. */ | |
409 | struct spinlock gt_lock; | |
1da177e4 | 410 | |
f2c9677b | 411 | struct intel_gmbus gmbus[GMBUS_NUM_PORTS]; |
f899fc64 | 412 | |
8a8ed1f5 YS |
413 | /** gmbus_mutex protects against concurrent usage of the single hw gmbus |
414 | * controller on different i2c buses. */ | |
415 | struct mutex gmbus_mutex; | |
416 | ||
110447fc DV |
417 | /** |
418 | * Base address of the gmbus and gpio block. | |
419 | */ | |
420 | uint32_t gpio_mmio_base; | |
421 | ||
ec2a4c3f | 422 | struct pci_dev *bridge_dev; |
1ec14ad3 | 423 | struct intel_ring_buffer ring[I915_NUM_RINGS]; |
6f392d54 | 424 | uint32_t next_seqno; |
1da177e4 | 425 | |
9c8da5eb | 426 | drm_dma_handle_t *status_page_dmah; |
0a3e67a4 | 427 | uint32_t counter; |
05394f39 CW |
428 | struct drm_i915_gem_object *pwrctx; |
429 | struct drm_i915_gem_object *renderctx; | |
1da177e4 | 430 | |
d7658989 JB |
431 | struct resource mch_res; |
432 | ||
1da177e4 | 433 | atomic_t irq_received; |
1ec14ad3 CW |
434 | |
435 | /* protects the irq masks */ | |
436 | spinlock_t irq_lock; | |
57f350b6 JB |
437 | |
438 | /* DPIO indirect register protection */ | |
439 | spinlock_t dpio_lock; | |
440 | ||
ed4cb414 | 441 | /** Cached value of IMR to avoid reads in updating the bitfield */ |
7c463586 | 442 | u32 pipestat[2]; |
1ec14ad3 CW |
443 | u32 irq_mask; |
444 | u32 gt_irq_mask; | |
445 | u32 pch_irq_mask; | |
1da177e4 | 446 | |
5ca58282 JB |
447 | u32 hotplug_supported_mask; |
448 | struct work_struct hotplug_work; | |
449 | ||
a3524f1b | 450 | int num_pipe; |
ee7b9f93 | 451 | int num_pch_pll; |
a6b54f3f | 452 | |
f65d9421 | 453 | /* For hangcheck timer */ |
576ae4b8 | 454 | #define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */ |
f65d9421 BG |
455 | struct timer_list hangcheck_timer; |
456 | int hangcheck_count; | |
b4519513 | 457 | uint32_t last_acthd[I915_NUM_RINGS]; |
050ee91f | 458 | uint32_t prev_instdone[I915_NUM_INSTDONE_REG]; |
f65d9421 | 459 | |
e5eb3d63 DV |
460 | unsigned int stop_rings; |
461 | ||
80824003 | 462 | unsigned long cfb_size; |
016b9b61 CW |
463 | unsigned int cfb_fb; |
464 | enum plane cfb_plane; | |
bed4a673 | 465 | int cfb_y; |
1630fe75 | 466 | struct intel_fbc_work *fbc_work; |
80824003 | 467 | |
8ee1c3db MG |
468 | struct intel_opregion opregion; |
469 | ||
02e792fb DV |
470 | /* overlay */ |
471 | struct intel_overlay *overlay; | |
b840d907 | 472 | bool sprite_scaling_enabled; |
02e792fb | 473 | |
79e53945 | 474 | /* LVDS info */ |
a9573556 | 475 | int backlight_level; /* restore backlight to this value */ |
47356eb6 | 476 | bool backlight_enabled; |
88631706 ML |
477 | struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */ |
478 | struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */ | |
79e53945 JB |
479 | |
480 | /* Feature bits from the VBIOS */ | |
95281e35 HE |
481 | unsigned int int_tv_support:1; |
482 | unsigned int lvds_dither:1; | |
483 | unsigned int lvds_vbt:1; | |
484 | unsigned int int_crt_support:1; | |
43565a06 | 485 | unsigned int lvds_use_ssc:1; |
abd06860 | 486 | unsigned int display_clock_mode:1; |
43565a06 | 487 | int lvds_ssc_freq; |
b0354385 TI |
488 | unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */ |
489 | unsigned int lvds_val; /* used for checking LVDS channel mode */ | |
5ceb0f9b | 490 | struct { |
9f0e7ff4 JB |
491 | int rate; |
492 | int lanes; | |
493 | int preemphasis; | |
494 | int vswing; | |
495 | ||
496 | bool initialized; | |
497 | bool support; | |
498 | int bpp; | |
499 | struct edp_power_seq pps; | |
5ceb0f9b | 500 | } edp; |
89667383 | 501 | bool no_aux_handshake; |
79e53945 | 502 | |
c1c7af60 JB |
503 | struct notifier_block lid_notifier; |
504 | ||
f899fc64 | 505 | int crt_ddc_pin; |
4b9de737 | 506 | struct drm_i915_fence_reg fence_regs[I915_MAX_NUM_FENCES]; /* assume 965 */ |
de151cf6 JB |
507 | int fence_reg_start; /* 4 if userland hasn't ioctl'd us yet */ |
508 | int num_fence_regs; /* 8 on pre-965, 16 otherwise */ | |
509 | ||
95534263 | 510 | unsigned int fsb_freq, mem_freq, is_ddr3; |
7662c8bd | 511 | |
63eeaf38 | 512 | spinlock_t error_lock; |
742cbee8 | 513 | /* Protected by dev->error_lock. */ |
63eeaf38 | 514 | struct drm_i915_error_state *first_error; |
8a905236 | 515 | struct work_struct error_work; |
30dbf0c0 | 516 | struct completion error_completion; |
9c9fe1f8 | 517 | struct workqueue_struct *wq; |
63eeaf38 | 518 | |
e70236a8 JB |
519 | /* Display functions */ |
520 | struct drm_i915_display_funcs display; | |
521 | ||
3bad0781 ZW |
522 | /* PCH chipset type */ |
523 | enum intel_pch pch_type; | |
524 | ||
b690e96c JB |
525 | unsigned long quirks; |
526 | ||
ba8bbcf6 | 527 | /* Register state */ |
c9354c85 | 528 | bool modeset_on_lid; |
ba8bbcf6 JB |
529 | u8 saveLBB; |
530 | u32 saveDSPACNTR; | |
531 | u32 saveDSPBCNTR; | |
e948e994 | 532 | u32 saveDSPARB; |
968b503e | 533 | u32 saveHWS; |
ba8bbcf6 JB |
534 | u32 savePIPEACONF; |
535 | u32 savePIPEBCONF; | |
536 | u32 savePIPEASRC; | |
537 | u32 savePIPEBSRC; | |
538 | u32 saveFPA0; | |
539 | u32 saveFPA1; | |
540 | u32 saveDPLL_A; | |
541 | u32 saveDPLL_A_MD; | |
542 | u32 saveHTOTAL_A; | |
543 | u32 saveHBLANK_A; | |
544 | u32 saveHSYNC_A; | |
545 | u32 saveVTOTAL_A; | |
546 | u32 saveVBLANK_A; | |
547 | u32 saveVSYNC_A; | |
548 | u32 saveBCLRPAT_A; | |
5586c8bc | 549 | u32 saveTRANSACONF; |
42048781 ZW |
550 | u32 saveTRANS_HTOTAL_A; |
551 | u32 saveTRANS_HBLANK_A; | |
552 | u32 saveTRANS_HSYNC_A; | |
553 | u32 saveTRANS_VTOTAL_A; | |
554 | u32 saveTRANS_VBLANK_A; | |
555 | u32 saveTRANS_VSYNC_A; | |
0da3ea12 | 556 | u32 savePIPEASTAT; |
ba8bbcf6 JB |
557 | u32 saveDSPASTRIDE; |
558 | u32 saveDSPASIZE; | |
559 | u32 saveDSPAPOS; | |
585fb111 | 560 | u32 saveDSPAADDR; |
ba8bbcf6 JB |
561 | u32 saveDSPASURF; |
562 | u32 saveDSPATILEOFF; | |
563 | u32 savePFIT_PGM_RATIOS; | |
0eb96d6e | 564 | u32 saveBLC_HIST_CTL; |
ba8bbcf6 JB |
565 | u32 saveBLC_PWM_CTL; |
566 | u32 saveBLC_PWM_CTL2; | |
42048781 ZW |
567 | u32 saveBLC_CPU_PWM_CTL; |
568 | u32 saveBLC_CPU_PWM_CTL2; | |
ba8bbcf6 JB |
569 | u32 saveFPB0; |
570 | u32 saveFPB1; | |
571 | u32 saveDPLL_B; | |
572 | u32 saveDPLL_B_MD; | |
573 | u32 saveHTOTAL_B; | |
574 | u32 saveHBLANK_B; | |
575 | u32 saveHSYNC_B; | |
576 | u32 saveVTOTAL_B; | |
577 | u32 saveVBLANK_B; | |
578 | u32 saveVSYNC_B; | |
579 | u32 saveBCLRPAT_B; | |
5586c8bc | 580 | u32 saveTRANSBCONF; |
42048781 ZW |
581 | u32 saveTRANS_HTOTAL_B; |
582 | u32 saveTRANS_HBLANK_B; | |
583 | u32 saveTRANS_HSYNC_B; | |
584 | u32 saveTRANS_VTOTAL_B; | |
585 | u32 saveTRANS_VBLANK_B; | |
586 | u32 saveTRANS_VSYNC_B; | |
0da3ea12 | 587 | u32 savePIPEBSTAT; |
ba8bbcf6 JB |
588 | u32 saveDSPBSTRIDE; |
589 | u32 saveDSPBSIZE; | |
590 | u32 saveDSPBPOS; | |
585fb111 | 591 | u32 saveDSPBADDR; |
ba8bbcf6 JB |
592 | u32 saveDSPBSURF; |
593 | u32 saveDSPBTILEOFF; | |
585fb111 JB |
594 | u32 saveVGA0; |
595 | u32 saveVGA1; | |
596 | u32 saveVGA_PD; | |
ba8bbcf6 JB |
597 | u32 saveVGACNTRL; |
598 | u32 saveADPA; | |
599 | u32 saveLVDS; | |
585fb111 JB |
600 | u32 savePP_ON_DELAYS; |
601 | u32 savePP_OFF_DELAYS; | |
ba8bbcf6 JB |
602 | u32 saveDVOA; |
603 | u32 saveDVOB; | |
604 | u32 saveDVOC; | |
605 | u32 savePP_ON; | |
606 | u32 savePP_OFF; | |
607 | u32 savePP_CONTROL; | |
585fb111 | 608 | u32 savePP_DIVISOR; |
ba8bbcf6 JB |
609 | u32 savePFIT_CONTROL; |
610 | u32 save_palette_a[256]; | |
611 | u32 save_palette_b[256]; | |
06027f91 | 612 | u32 saveDPFC_CB_BASE; |
ba8bbcf6 JB |
613 | u32 saveFBC_CFB_BASE; |
614 | u32 saveFBC_LL_BASE; | |
615 | u32 saveFBC_CONTROL; | |
616 | u32 saveFBC_CONTROL2; | |
0da3ea12 JB |
617 | u32 saveIER; |
618 | u32 saveIIR; | |
619 | u32 saveIMR; | |
42048781 ZW |
620 | u32 saveDEIER; |
621 | u32 saveDEIMR; | |
622 | u32 saveGTIER; | |
623 | u32 saveGTIMR; | |
624 | u32 saveFDI_RXA_IMR; | |
625 | u32 saveFDI_RXB_IMR; | |
1f84e550 | 626 | u32 saveCACHE_MODE_0; |
1f84e550 | 627 | u32 saveMI_ARB_STATE; |
ba8bbcf6 JB |
628 | u32 saveSWF0[16]; |
629 | u32 saveSWF1[16]; | |
630 | u32 saveSWF2[3]; | |
631 | u8 saveMSR; | |
632 | u8 saveSR[8]; | |
123f794f | 633 | u8 saveGR[25]; |
ba8bbcf6 | 634 | u8 saveAR_INDEX; |
a59e122a | 635 | u8 saveAR[21]; |
ba8bbcf6 | 636 | u8 saveDACMASK; |
a59e122a | 637 | u8 saveCR[37]; |
4b9de737 | 638 | uint64_t saveFENCE[I915_MAX_NUM_FENCES]; |
1fd1c624 EA |
639 | u32 saveCURACNTR; |
640 | u32 saveCURAPOS; | |
641 | u32 saveCURABASE; | |
642 | u32 saveCURBCNTR; | |
643 | u32 saveCURBPOS; | |
644 | u32 saveCURBBASE; | |
645 | u32 saveCURSIZE; | |
a4fc5ed6 KP |
646 | u32 saveDP_B; |
647 | u32 saveDP_C; | |
648 | u32 saveDP_D; | |
649 | u32 savePIPEA_GMCH_DATA_M; | |
650 | u32 savePIPEB_GMCH_DATA_M; | |
651 | u32 savePIPEA_GMCH_DATA_N; | |
652 | u32 savePIPEB_GMCH_DATA_N; | |
653 | u32 savePIPEA_DP_LINK_M; | |
654 | u32 savePIPEB_DP_LINK_M; | |
655 | u32 savePIPEA_DP_LINK_N; | |
656 | u32 savePIPEB_DP_LINK_N; | |
42048781 ZW |
657 | u32 saveFDI_RXA_CTL; |
658 | u32 saveFDI_TXA_CTL; | |
659 | u32 saveFDI_RXB_CTL; | |
660 | u32 saveFDI_TXB_CTL; | |
661 | u32 savePFA_CTL_1; | |
662 | u32 savePFB_CTL_1; | |
663 | u32 savePFA_WIN_SZ; | |
664 | u32 savePFB_WIN_SZ; | |
665 | u32 savePFA_WIN_POS; | |
666 | u32 savePFB_WIN_POS; | |
5586c8bc ZW |
667 | u32 savePCH_DREF_CONTROL; |
668 | u32 saveDISP_ARB_CTL; | |
669 | u32 savePIPEA_DATA_M1; | |
670 | u32 savePIPEA_DATA_N1; | |
671 | u32 savePIPEA_LINK_M1; | |
672 | u32 savePIPEA_LINK_N1; | |
673 | u32 savePIPEB_DATA_M1; | |
674 | u32 savePIPEB_DATA_N1; | |
675 | u32 savePIPEB_LINK_M1; | |
676 | u32 savePIPEB_LINK_N1; | |
b5b72e89 | 677 | u32 saveMCHBAR_RENDER_STANDBY; |
cda2bb78 | 678 | u32 savePCH_PORT_HOTPLUG; |
673a394b EA |
679 | |
680 | struct { | |
19966754 | 681 | /** Bridge to intel-gtt-ko */ |
c64f7ba5 | 682 | const struct intel_gtt *gtt; |
19966754 | 683 | /** Memory allocator for GTT stolen memory */ |
fe669bf8 | 684 | struct drm_mm stolen; |
19966754 | 685 | /** Memory allocator for GTT */ |
673a394b | 686 | struct drm_mm gtt_space; |
93a37f20 DV |
687 | /** List of all objects in gtt_space. Used to restore gtt |
688 | * mappings on resume */ | |
6c085a72 CW |
689 | struct list_head bound_list; |
690 | /** | |
691 | * List of objects which are not bound to the GTT (thus | |
692 | * are idle and not used by the GPU) but still have | |
693 | * (presumably uncached) pages still attached. | |
694 | */ | |
695 | struct list_head unbound_list; | |
bee4a186 CW |
696 | |
697 | /** Usable portion of the GTT for GEM */ | |
698 | unsigned long gtt_start; | |
a6e0aa42 | 699 | unsigned long gtt_mappable_end; |
bee4a186 | 700 | unsigned long gtt_end; |
673a394b | 701 | |
0839ccb8 | 702 | struct io_mapping *gtt_mapping; |
dd2757f8 | 703 | phys_addr_t gtt_base_addr; |
ab657db1 | 704 | int gtt_mtrr; |
0839ccb8 | 705 | |
1d2a314c DV |
706 | /** PPGTT used for aliasing the PPGTT with the GTT */ |
707 | struct i915_hw_ppgtt *aliasing_ppgtt; | |
708 | ||
b9524a1e BW |
709 | u32 *l3_remap_info; |
710 | ||
17250b71 | 711 | struct shrinker inactive_shrinker; |
31169714 | 712 | |
69dc4987 CW |
713 | /** |
714 | * List of objects currently involved in rendering. | |
715 | * | |
716 | * Includes buffers having the contents of their GPU caches | |
717 | * flushed, not necessarily primitives. last_rendering_seqno | |
718 | * represents when the rendering involved will be completed. | |
719 | * | |
720 | * A reference is held on the buffer while on this list. | |
721 | */ | |
722 | struct list_head active_list; | |
723 | ||
673a394b EA |
724 | /** |
725 | * LRU list of objects which are not in the ringbuffer and | |
726 | * are ready to unbind, but are still in the GTT. | |
727 | * | |
ce44b0ea EA |
728 | * last_rendering_seqno is 0 while an object is in this list. |
729 | * | |
673a394b EA |
730 | * A reference is not held on the buffer while on this list, |
731 | * as merely being GTT-bound shouldn't prevent its being | |
732 | * freed, and we'll pull it off the list in the free path. | |
733 | */ | |
734 | struct list_head inactive_list; | |
735 | ||
a09ba7fa EA |
736 | /** LRU list of objects with fence regs on them. */ |
737 | struct list_head fence_list; | |
738 | ||
673a394b EA |
739 | /** |
740 | * We leave the user IRQ off as much as possible, | |
741 | * but this means that requests will finish and never | |
742 | * be retired once the system goes idle. Set a timer to | |
743 | * fire periodically while the ring is running. When it | |
744 | * fires, go retire requests. | |
745 | */ | |
746 | struct delayed_work retire_work; | |
747 | ||
ce453d81 CW |
748 | /** |
749 | * Are we in a non-interruptible section of code like | |
750 | * modesetting? | |
751 | */ | |
752 | bool interruptible; | |
753 | ||
673a394b EA |
754 | /** |
755 | * Flag if the X Server, and thus DRM, is not currently in | |
756 | * control of the device. | |
757 | * | |
758 | * This is set between LeaveVT and EnterVT. It needs to be | |
759 | * replaced with a semaphore. It also needs to be | |
760 | * transitioned away from for kernel modesetting. | |
761 | */ | |
762 | int suspended; | |
763 | ||
764 | /** | |
765 | * Flag if the hardware appears to be wedged. | |
766 | * | |
767 | * This is set when attempts to idle the device timeout. | |
25985edc | 768 | * It prevents command submission from occurring and makes |
673a394b EA |
769 | * every pending request fail |
770 | */ | |
ba1234d1 | 771 | atomic_t wedged; |
673a394b EA |
772 | |
773 | /** Bit 6 swizzling required for X tiling */ | |
774 | uint32_t bit_6_swizzle_x; | |
775 | /** Bit 6 swizzling required for Y tiling */ | |
776 | uint32_t bit_6_swizzle_y; | |
71acb5eb DA |
777 | |
778 | /* storage for physical objects */ | |
779 | struct drm_i915_gem_phys_object *phys_objs[I915_MAX_PHYS_OBJECT]; | |
9220434a | 780 | |
73aa808f | 781 | /* accounting, useful for userland debugging */ |
73aa808f | 782 | size_t gtt_total; |
6299f992 CW |
783 | size_t mappable_gtt_total; |
784 | size_t object_memory; | |
73aa808f | 785 | u32 object_count; |
673a394b | 786 | } mm; |
8781342d DV |
787 | |
788 | /* Old dri1 support infrastructure, beware the dragons ya fools entering | |
789 | * here! */ | |
790 | struct { | |
791 | unsigned allow_batchbuffer : 1; | |
316d3884 | 792 | u32 __iomem *gfx_hws_cpu_addr; |
5d985ac8 DV |
793 | |
794 | unsigned int cpp; | |
795 | int back_offset; | |
796 | int front_offset; | |
797 | int current_page; | |
798 | int page_flipping; | |
8781342d DV |
799 | } dri1; |
800 | ||
801 | /* Kernel Modesetting */ | |
802 | ||
9b9d172d | 803 | struct sdvo_device_mapping sdvo_mappings[2]; |
a3e17eb8 ZY |
804 | /* indicate whether the LVDS_BORDER should be enabled or not */ |
805 | unsigned int lvds_border_bits; | |
1d8e1c75 CW |
806 | /* Panel fitter placement and size for Ironlake+ */ |
807 | u32 pch_pf_pos, pch_pf_size; | |
652c393a | 808 | |
27f8227b JB |
809 | struct drm_crtc *plane_to_crtc_mapping[3]; |
810 | struct drm_crtc *pipe_to_crtc_mapping[3]; | |
6b95a207 KH |
811 | wait_queue_head_t pending_flip_queue; |
812 | ||
ee7b9f93 JB |
813 | struct intel_pch_pll pch_plls[I915_NUM_PLLS]; |
814 | ||
652c393a JB |
815 | /* Reclocking support */ |
816 | bool render_reclock_avail; | |
817 | bool lvds_downclock_avail; | |
18f9ed12 ZY |
818 | /* indicates the reduced downclock for LVDS*/ |
819 | int lvds_downclock; | |
652c393a | 820 | u16 orig_clock; |
6363ee6f ZY |
821 | int child_dev_num; |
822 | struct child_device_config *child_dev; | |
a2565377 | 823 | struct drm_connector *int_lvds_connector; |
aaa6fd2a | 824 | struct drm_connector *int_edp_connector; |
f97108d1 | 825 | |
c4804411 | 826 | bool mchbar_need_disable; |
f97108d1 | 827 | |
c6a828d3 DV |
828 | /* gen6+ rps state */ |
829 | struct { | |
830 | struct work_struct work; | |
831 | u32 pm_iir; | |
832 | /* lock - irqsave spinlock that protectects the work_struct and | |
833 | * pm_iir. */ | |
834 | spinlock_t lock; | |
835 | ||
836 | /* The below variables an all the rps hw state are protected by | |
837 | * dev->struct mutext. */ | |
838 | u8 cur_delay; | |
839 | u8 min_delay; | |
840 | u8 max_delay; | |
841 | } rps; | |
842 | ||
20e4d407 DV |
843 | /* ilk-only ips/rps state. Everything in here is protected by the global |
844 | * mchdev_lock in intel_pm.c */ | |
845 | struct { | |
846 | u8 cur_delay; | |
847 | u8 min_delay; | |
848 | u8 max_delay; | |
849 | u8 fmax; | |
850 | u8 fstart; | |
851 | ||
852 | u64 last_count1; | |
853 | unsigned long last_time1; | |
854 | unsigned long chipset_power; | |
855 | u64 last_count2; | |
856 | struct timespec last_time2; | |
857 | unsigned long gfx_power; | |
858 | u8 corr; | |
859 | ||
860 | int c_m; | |
861 | int r_t; | |
862 | } ips; | |
b5e50c3f JB |
863 | |
864 | enum no_fbc_reason no_fbc_reason; | |
38651674 | 865 | |
20bf377e JB |
866 | struct drm_mm_node *compressed_fb; |
867 | struct drm_mm_node *compressed_llb; | |
34dc4d44 | 868 | |
ae681d96 CW |
869 | unsigned long last_gpu_reset; |
870 | ||
8be48d92 DA |
871 | /* list of fbdev register on this device */ |
872 | struct intel_fbdev *fbdev; | |
e953fd7b | 873 | |
aaa6fd2a MG |
874 | struct backlight_device *backlight; |
875 | ||
e953fd7b | 876 | struct drm_property *broadcast_rgb_property; |
3f43c48d | 877 | struct drm_property *force_audio_property; |
e3689190 BW |
878 | |
879 | struct work_struct parity_error_work; | |
254f965c BW |
880 | bool hw_contexts_disabled; |
881 | uint32_t hw_context_size; | |
1da177e4 LT |
882 | } drm_i915_private_t; |
883 | ||
b4519513 CW |
884 | /* Iterate over initialised rings */ |
885 | #define for_each_ring(ring__, dev_priv__, i__) \ | |
886 | for ((i__) = 0; (i__) < I915_NUM_RINGS; (i__)++) \ | |
887 | if (((ring__) = &(dev_priv__)->ring[(i__)]), intel_ring_initialized((ring__))) | |
888 | ||
b1d7e4b4 WF |
889 | enum hdmi_force_audio { |
890 | HDMI_AUDIO_OFF_DVI = -2, /* no aux data for HDMI-DVI converter */ | |
891 | HDMI_AUDIO_OFF, /* force turn off HDMI audio */ | |
892 | HDMI_AUDIO_AUTO, /* trust EDID */ | |
893 | HDMI_AUDIO_ON, /* force turn on HDMI audio */ | |
894 | }; | |
895 | ||
93dfb40c | 896 | enum i915_cache_level { |
e6994aee | 897 | I915_CACHE_NONE = 0, |
93dfb40c | 898 | I915_CACHE_LLC, |
e6994aee | 899 | I915_CACHE_LLC_MLC, /* gen6+, in docs at least! */ |
93dfb40c CW |
900 | }; |
901 | ||
37e680a1 CW |
902 | struct drm_i915_gem_object_ops { |
903 | /* Interface between the GEM object and its backing storage. | |
904 | * get_pages() is called once prior to the use of the associated set | |
905 | * of pages before to binding them into the GTT, and put_pages() is | |
906 | * called after we no longer need them. As we expect there to be | |
907 | * associated cost with migrating pages between the backing storage | |
908 | * and making them available for the GPU (e.g. clflush), we may hold | |
909 | * onto the pages after they are no longer referenced by the GPU | |
910 | * in case they may be used again shortly (for example migrating the | |
911 | * pages to a different memory domain within the GTT). put_pages() | |
912 | * will therefore most likely be called when the object itself is | |
913 | * being released or under memory pressure (where we attempt to | |
914 | * reap pages for the shrinker). | |
915 | */ | |
916 | int (*get_pages)(struct drm_i915_gem_object *); | |
917 | void (*put_pages)(struct drm_i915_gem_object *); | |
918 | }; | |
919 | ||
673a394b | 920 | struct drm_i915_gem_object { |
c397b908 | 921 | struct drm_gem_object base; |
673a394b | 922 | |
37e680a1 CW |
923 | const struct drm_i915_gem_object_ops *ops; |
924 | ||
673a394b EA |
925 | /** Current space allocated to this object in the GTT, if any. */ |
926 | struct drm_mm_node *gtt_space; | |
93a37f20 | 927 | struct list_head gtt_list; |
673a394b | 928 | |
65ce3027 | 929 | /** This object's place on the active/inactive lists */ |
69dc4987 CW |
930 | struct list_head ring_list; |
931 | struct list_head mm_list; | |
432e58ed CW |
932 | /** This object's place in the batchbuffer or on the eviction list */ |
933 | struct list_head exec_list; | |
673a394b EA |
934 | |
935 | /** | |
65ce3027 CW |
936 | * This is set if the object is on the active lists (has pending |
937 | * rendering and so a non-zero seqno), and is not set if it i s on | |
938 | * inactive (ready to be unbound) list. | |
673a394b | 939 | */ |
0206e353 | 940 | unsigned int active:1; |
673a394b EA |
941 | |
942 | /** | |
943 | * This is set if the object has been written to since last bound | |
944 | * to the GTT | |
945 | */ | |
0206e353 | 946 | unsigned int dirty:1; |
778c3544 DV |
947 | |
948 | /** | |
949 | * Fence register bits (if any) for this object. Will be set | |
950 | * as needed when mapped into the GTT. | |
951 | * Protected by dev->struct_mutex. | |
778c3544 | 952 | */ |
4b9de737 | 953 | signed int fence_reg:I915_MAX_NUM_FENCE_BITS; |
778c3544 | 954 | |
778c3544 DV |
955 | /** |
956 | * Advice: are the backing pages purgeable? | |
957 | */ | |
0206e353 | 958 | unsigned int madv:2; |
778c3544 | 959 | |
778c3544 DV |
960 | /** |
961 | * Current tiling mode for the object. | |
962 | */ | |
0206e353 | 963 | unsigned int tiling_mode:2; |
5d82e3e6 CW |
964 | /** |
965 | * Whether the tiling parameters for the currently associated fence | |
966 | * register have changed. Note that for the purposes of tracking | |
967 | * tiling changes we also treat the unfenced register, the register | |
968 | * slot that the object occupies whilst it executes a fenced | |
969 | * command (such as BLT on gen2/3), as a "fence". | |
970 | */ | |
971 | unsigned int fence_dirty:1; | |
778c3544 DV |
972 | |
973 | /** How many users have pinned this object in GTT space. The following | |
974 | * users can each hold at most one reference: pwrite/pread, pin_ioctl | |
975 | * (via user_pin_count), execbuffer (objects are not allowed multiple | |
976 | * times for the same batchbuffer), and the framebuffer code. When | |
977 | * switching/pageflipping, the framebuffer code has at most two buffers | |
978 | * pinned per crtc. | |
979 | * | |
980 | * In the worst case this is 1 + 1 + 1 + 2*2 = 7. That would fit into 3 | |
981 | * bits with absolutely no headroom. So use 4 bits. */ | |
0206e353 | 982 | unsigned int pin_count:4; |
778c3544 | 983 | #define DRM_I915_GEM_OBJECT_MAX_PIN_COUNT 0xf |
673a394b | 984 | |
75e9e915 DV |
985 | /** |
986 | * Is the object at the current location in the gtt mappable and | |
987 | * fenceable? Used to avoid costly recalculations. | |
988 | */ | |
0206e353 | 989 | unsigned int map_and_fenceable:1; |
75e9e915 | 990 | |
fb7d516a DV |
991 | /** |
992 | * Whether the current gtt mapping needs to be mappable (and isn't just | |
993 | * mappable by accident). Track pin and fault separate for a more | |
994 | * accurate mappable working set. | |
995 | */ | |
0206e353 AJ |
996 | unsigned int fault_mappable:1; |
997 | unsigned int pin_mappable:1; | |
fb7d516a | 998 | |
caea7476 CW |
999 | /* |
1000 | * Is the GPU currently using a fence to access this buffer, | |
1001 | */ | |
1002 | unsigned int pending_fenced_gpu_access:1; | |
1003 | unsigned int fenced_gpu_access:1; | |
1004 | ||
93dfb40c CW |
1005 | unsigned int cache_level:2; |
1006 | ||
7bddb01f | 1007 | unsigned int has_aliasing_ppgtt_mapping:1; |
74898d7e | 1008 | unsigned int has_global_gtt_mapping:1; |
7bddb01f | 1009 | |
856fa198 | 1010 | struct page **pages; |
673a394b | 1011 | |
185cbcb3 DV |
1012 | /** |
1013 | * DMAR support | |
1014 | */ | |
1015 | struct scatterlist *sg_list; | |
1016 | int num_sg; | |
1017 | ||
1286ff73 DV |
1018 | /* prime dma-buf support */ |
1019 | struct sg_table *sg_table; | |
9a70cc2a DA |
1020 | void *dma_buf_vmapping; |
1021 | int vmapping_count; | |
1022 | ||
67731b87 CW |
1023 | /** |
1024 | * Used for performing relocations during execbuffer insertion. | |
1025 | */ | |
1026 | struct hlist_node exec_node; | |
1027 | unsigned long exec_handle; | |
6fe4f140 | 1028 | struct drm_i915_gem_exec_object2 *exec_entry; |
67731b87 | 1029 | |
673a394b EA |
1030 | /** |
1031 | * Current offset of the object in GTT space. | |
1032 | * | |
1033 | * This is the same as gtt_space->start | |
1034 | */ | |
1035 | uint32_t gtt_offset; | |
e67b8ce1 | 1036 | |
caea7476 CW |
1037 | struct intel_ring_buffer *ring; |
1038 | ||
1c293ea3 | 1039 | /** Breadcrumb of last rendering to the buffer. */ |
0201f1ec CW |
1040 | uint32_t last_read_seqno; |
1041 | uint32_t last_write_seqno; | |
caea7476 CW |
1042 | /** Breadcrumb of last fenced GPU access to the buffer. */ |
1043 | uint32_t last_fenced_seqno; | |
673a394b | 1044 | |
778c3544 | 1045 | /** Current tiling stride for the object, if it's tiled. */ |
de151cf6 | 1046 | uint32_t stride; |
673a394b | 1047 | |
280b713b | 1048 | /** Record of address bit 17 of each page at last unbind. */ |
d312ec25 | 1049 | unsigned long *bit_17; |
280b713b | 1050 | |
79e53945 JB |
1051 | /** User space pin count and filp owning the pin */ |
1052 | uint32_t user_pin_count; | |
1053 | struct drm_file *pin_filp; | |
71acb5eb DA |
1054 | |
1055 | /** for phy allocated objects */ | |
1056 | struct drm_i915_gem_phys_object *phys_obj; | |
b70d11da | 1057 | |
6b95a207 KH |
1058 | /** |
1059 | * Number of crtcs where this object is currently the fb, but | |
1060 | * will be page flipped away on the next vblank. When it | |
1061 | * reaches 0, dev_priv->pending_flip_queue will be woken up. | |
1062 | */ | |
1063 | atomic_t pending_flip; | |
673a394b EA |
1064 | }; |
1065 | ||
62b8b215 | 1066 | #define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base) |
23010e43 | 1067 | |
673a394b EA |
1068 | /** |
1069 | * Request queue structure. | |
1070 | * | |
1071 | * The request queue allows us to note sequence numbers that have been emitted | |
1072 | * and may be associated with active buffers to be retired. | |
1073 | * | |
1074 | * By keeping this list, we can avoid having to do questionable | |
1075 | * sequence-number comparisons on buffer last_rendering_seqnos, and associate | |
1076 | * an emission time with seqnos for tracking how far ahead of the GPU we are. | |
1077 | */ | |
1078 | struct drm_i915_gem_request { | |
852835f3 ZN |
1079 | /** On Which ring this request was generated */ |
1080 | struct intel_ring_buffer *ring; | |
1081 | ||
673a394b EA |
1082 | /** GEM sequence number associated with this request. */ |
1083 | uint32_t seqno; | |
1084 | ||
a71d8d94 CW |
1085 | /** Postion in the ringbuffer of the end of the request */ |
1086 | u32 tail; | |
1087 | ||
673a394b EA |
1088 | /** Time at which this request was emitted, in jiffies. */ |
1089 | unsigned long emitted_jiffies; | |
1090 | ||
b962442e | 1091 | /** global list entry for this request */ |
673a394b | 1092 | struct list_head list; |
b962442e | 1093 | |
f787a5f5 | 1094 | struct drm_i915_file_private *file_priv; |
b962442e EA |
1095 | /** file_priv list entry for this request */ |
1096 | struct list_head client_list; | |
673a394b EA |
1097 | }; |
1098 | ||
1099 | struct drm_i915_file_private { | |
1100 | struct { | |
1c25595f | 1101 | struct spinlock lock; |
b962442e | 1102 | struct list_head request_list; |
673a394b | 1103 | } mm; |
40521054 | 1104 | struct idr context_idr; |
673a394b EA |
1105 | }; |
1106 | ||
cae5852d ZN |
1107 | #define INTEL_INFO(dev) (((struct drm_i915_private *) (dev)->dev_private)->info) |
1108 | ||
1109 | #define IS_I830(dev) ((dev)->pci_device == 0x3577) | |
1110 | #define IS_845G(dev) ((dev)->pci_device == 0x2562) | |
1111 | #define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x) | |
1112 | #define IS_I865G(dev) ((dev)->pci_device == 0x2572) | |
1113 | #define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g) | |
1114 | #define IS_I915GM(dev) ((dev)->pci_device == 0x2592) | |
1115 | #define IS_I945G(dev) ((dev)->pci_device == 0x2772) | |
1116 | #define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm) | |
1117 | #define IS_BROADWATER(dev) (INTEL_INFO(dev)->is_broadwater) | |
1118 | #define IS_CRESTLINE(dev) (INTEL_INFO(dev)->is_crestline) | |
1119 | #define IS_GM45(dev) ((dev)->pci_device == 0x2A42) | |
1120 | #define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x) | |
1121 | #define IS_PINEVIEW_G(dev) ((dev)->pci_device == 0xa001) | |
1122 | #define IS_PINEVIEW_M(dev) ((dev)->pci_device == 0xa011) | |
1123 | #define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview) | |
1124 | #define IS_G33(dev) (INTEL_INFO(dev)->is_g33) | |
1125 | #define IS_IRONLAKE_D(dev) ((dev)->pci_device == 0x0042) | |
1126 | #define IS_IRONLAKE_M(dev) ((dev)->pci_device == 0x0046) | |
4b65177b | 1127 | #define IS_IVYBRIDGE(dev) (INTEL_INFO(dev)->is_ivybridge) |
70a3eb7a | 1128 | #define IS_VALLEYVIEW(dev) (INTEL_INFO(dev)->is_valleyview) |
4cae9ae0 | 1129 | #define IS_HASWELL(dev) (INTEL_INFO(dev)->is_haswell) |
cae5852d ZN |
1130 | #define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile) |
1131 | ||
85436696 JB |
1132 | /* |
1133 | * The genX designation typically refers to the render engine, so render | |
1134 | * capability related checks should use IS_GEN, while display and other checks | |
1135 | * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular | |
1136 | * chips, etc.). | |
1137 | */ | |
cae5852d ZN |
1138 | #define IS_GEN2(dev) (INTEL_INFO(dev)->gen == 2) |
1139 | #define IS_GEN3(dev) (INTEL_INFO(dev)->gen == 3) | |
1140 | #define IS_GEN4(dev) (INTEL_INFO(dev)->gen == 4) | |
1141 | #define IS_GEN5(dev) (INTEL_INFO(dev)->gen == 5) | |
1142 | #define IS_GEN6(dev) (INTEL_INFO(dev)->gen == 6) | |
85436696 | 1143 | #define IS_GEN7(dev) (INTEL_INFO(dev)->gen == 7) |
cae5852d ZN |
1144 | |
1145 | #define HAS_BSD(dev) (INTEL_INFO(dev)->has_bsd_ring) | |
1146 | #define HAS_BLT(dev) (INTEL_INFO(dev)->has_blt_ring) | |
3d29b842 | 1147 | #define HAS_LLC(dev) (INTEL_INFO(dev)->has_llc) |
cae5852d ZN |
1148 | #define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws) |
1149 | ||
254f965c | 1150 | #define HAS_HW_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 6) |
93553609 | 1151 | #define HAS_ALIASING_PPGTT(dev) (INTEL_INFO(dev)->gen >=6 && !IS_VALLEYVIEW(dev)) |
1d2a314c | 1152 | |
05394f39 | 1153 | #define HAS_OVERLAY(dev) (INTEL_INFO(dev)->has_overlay) |
cae5852d ZN |
1154 | #define OVERLAY_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->overlay_needs_physical) |
1155 | ||
1156 | /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte | |
1157 | * rows, which changed the alignment requirements and fence programming. | |
1158 | */ | |
1159 | #define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \ | |
1160 | IS_I915GM(dev))) | |
1161 | #define SUPPORTS_DIGITAL_OUTPUTS(dev) (!IS_GEN2(dev) && !IS_PINEVIEW(dev)) | |
1162 | #define SUPPORTS_INTEGRATED_HDMI(dev) (IS_G4X(dev) || IS_GEN5(dev)) | |
1163 | #define SUPPORTS_INTEGRATED_DP(dev) (IS_G4X(dev) || IS_GEN5(dev)) | |
1164 | #define SUPPORTS_EDP(dev) (IS_IRONLAKE_M(dev)) | |
1165 | #define SUPPORTS_TV(dev) (INTEL_INFO(dev)->supports_tv) | |
1166 | #define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug) | |
1167 | /* dsparb controlled by hw only */ | |
1168 | #define DSPARB_HWCONTROL(dev) (IS_G4X(dev) || IS_IRONLAKE(dev)) | |
1169 | ||
1170 | #define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2) | |
1171 | #define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr) | |
1172 | #define I915_HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc) | |
cae5852d | 1173 | |
eceae481 | 1174 | #define HAS_PIPE_CONTROL(dev) (INTEL_INFO(dev)->gen >= 5) |
cae5852d ZN |
1175 | |
1176 | #define INTEL_PCH_TYPE(dev) (((struct drm_i915_private *)(dev)->dev_private)->pch_type) | |
eb877ebf | 1177 | #define HAS_PCH_LPT(dev) (INTEL_PCH_TYPE(dev) == PCH_LPT) |
cae5852d ZN |
1178 | #define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT) |
1179 | #define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX) | |
45e6e3a1 | 1180 | #define HAS_PCH_SPLIT(dev) (INTEL_PCH_TYPE(dev) != PCH_NONE) |
cae5852d | 1181 | |
b7884eb4 DV |
1182 | #define HAS_FORCE_WAKE(dev) (INTEL_INFO(dev)->has_force_wake) |
1183 | ||
f27b9265 | 1184 | #define HAS_L3_GPU_CACHE(dev) (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) |
e1ef7cc2 | 1185 | |
05394f39 CW |
1186 | #include "i915_trace.h" |
1187 | ||
83b7f9ac ED |
1188 | /** |
1189 | * RC6 is a special power stage which allows the GPU to enter an very | |
1190 | * low-voltage mode when idle, using down to 0V while at this stage. This | |
1191 | * stage is entered automatically when the GPU is idle when RC6 support is | |
1192 | * enabled, and as soon as new workload arises GPU wakes up automatically as well. | |
1193 | * | |
1194 | * There are different RC6 modes available in Intel GPU, which differentiate | |
1195 | * among each other with the latency required to enter and leave RC6 and | |
1196 | * voltage consumed by the GPU in different states. | |
1197 | * | |
1198 | * The combination of the following flags define which states GPU is allowed | |
1199 | * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and | |
1200 | * RC6pp is deepest RC6. Their support by hardware varies according to the | |
1201 | * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one | |
1202 | * which brings the most power savings; deeper states save more power, but | |
1203 | * require higher latency to switch to and wake up. | |
1204 | */ | |
1205 | #define INTEL_RC6_ENABLE (1<<0) | |
1206 | #define INTEL_RC6p_ENABLE (1<<1) | |
1207 | #define INTEL_RC6pp_ENABLE (1<<2) | |
1208 | ||
c153f45f | 1209 | extern struct drm_ioctl_desc i915_ioctls[]; |
b3a83639 | 1210 | extern int i915_max_ioctl; |
a35d9d3c BW |
1211 | extern unsigned int i915_fbpercrtc __always_unused; |
1212 | extern int i915_panel_ignore_lid __read_mostly; | |
1213 | extern unsigned int i915_powersave __read_mostly; | |
f45b5557 | 1214 | extern int i915_semaphores __read_mostly; |
a35d9d3c | 1215 | extern unsigned int i915_lvds_downclock __read_mostly; |
121d527a | 1216 | extern int i915_lvds_channel_mode __read_mostly; |
4415e63b | 1217 | extern int i915_panel_use_ssc __read_mostly; |
a35d9d3c | 1218 | extern int i915_vbt_sdvo_panel_type __read_mostly; |
c0f372b3 | 1219 | extern int i915_enable_rc6 __read_mostly; |
4415e63b | 1220 | extern int i915_enable_fbc __read_mostly; |
a35d9d3c | 1221 | extern bool i915_enable_hangcheck __read_mostly; |
650dc07e | 1222 | extern int i915_enable_ppgtt __read_mostly; |
b3a83639 | 1223 | |
6a9ee8af DA |
1224 | extern int i915_suspend(struct drm_device *dev, pm_message_t state); |
1225 | extern int i915_resume(struct drm_device *dev); | |
7c1c2871 DA |
1226 | extern int i915_master_create(struct drm_device *dev, struct drm_master *master); |
1227 | extern void i915_master_destroy(struct drm_device *dev, struct drm_master *master); | |
1228 | ||
1da177e4 | 1229 | /* i915_dma.c */ |
d05c617e | 1230 | void i915_update_dri1_breadcrumb(struct drm_device *dev); |
84b1fd10 | 1231 | extern void i915_kernel_lost_context(struct drm_device * dev); |
22eae947 | 1232 | extern int i915_driver_load(struct drm_device *, unsigned long flags); |
ba8bbcf6 | 1233 | extern int i915_driver_unload(struct drm_device *); |
673a394b | 1234 | extern int i915_driver_open(struct drm_device *dev, struct drm_file *file_priv); |
84b1fd10 | 1235 | extern void i915_driver_lastclose(struct drm_device * dev); |
6c340eac EA |
1236 | extern void i915_driver_preclose(struct drm_device *dev, |
1237 | struct drm_file *file_priv); | |
673a394b EA |
1238 | extern void i915_driver_postclose(struct drm_device *dev, |
1239 | struct drm_file *file_priv); | |
84b1fd10 | 1240 | extern int i915_driver_device_is_agp(struct drm_device * dev); |
c43b5634 | 1241 | #ifdef CONFIG_COMPAT |
0d6aa60b DA |
1242 | extern long i915_compat_ioctl(struct file *filp, unsigned int cmd, |
1243 | unsigned long arg); | |
c43b5634 | 1244 | #endif |
673a394b | 1245 | extern int i915_emit_box(struct drm_device *dev, |
c4e7a414 CW |
1246 | struct drm_clip_rect *box, |
1247 | int DR1, int DR4); | |
8e96d9c4 | 1248 | extern int intel_gpu_reset(struct drm_device *dev); |
d4b8bb2a | 1249 | extern int i915_reset(struct drm_device *dev); |
7648fa99 JB |
1250 | extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv); |
1251 | extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv); | |
1252 | extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv); | |
1253 | extern void i915_update_gfx_val(struct drm_i915_private *dev_priv); | |
1254 | ||
af6061af | 1255 | |
1da177e4 | 1256 | /* i915_irq.c */ |
f65d9421 | 1257 | void i915_hangcheck_elapsed(unsigned long data); |
527f9e90 | 1258 | void i915_handle_error(struct drm_device *dev, bool wedged); |
1da177e4 | 1259 | |
f71d4af4 | 1260 | extern void intel_irq_init(struct drm_device *dev); |
990bbdad | 1261 | extern void intel_gt_init(struct drm_device *dev); |
b1f14ad0 | 1262 | |
742cbee8 DV |
1263 | void i915_error_state_free(struct kref *error_ref); |
1264 | ||
7c463586 KP |
1265 | void |
1266 | i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask); | |
1267 | ||
1268 | void | |
1269 | i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask); | |
1270 | ||
0206e353 | 1271 | void intel_enable_asle(struct drm_device *dev); |
01c66889 | 1272 | |
3bd3c932 CW |
1273 | #ifdef CONFIG_DEBUG_FS |
1274 | extern void i915_destroy_error_state(struct drm_device *dev); | |
1275 | #else | |
1276 | #define i915_destroy_error_state(x) | |
1277 | #endif | |
1278 | ||
7c463586 | 1279 | |
673a394b EA |
1280 | /* i915_gem.c */ |
1281 | int i915_gem_init_ioctl(struct drm_device *dev, void *data, | |
1282 | struct drm_file *file_priv); | |
1283 | int i915_gem_create_ioctl(struct drm_device *dev, void *data, | |
1284 | struct drm_file *file_priv); | |
1285 | int i915_gem_pread_ioctl(struct drm_device *dev, void *data, | |
1286 | struct drm_file *file_priv); | |
1287 | int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data, | |
1288 | struct drm_file *file_priv); | |
1289 | int i915_gem_mmap_ioctl(struct drm_device *dev, void *data, | |
1290 | struct drm_file *file_priv); | |
de151cf6 JB |
1291 | int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data, |
1292 | struct drm_file *file_priv); | |
673a394b EA |
1293 | int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data, |
1294 | struct drm_file *file_priv); | |
1295 | int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data, | |
1296 | struct drm_file *file_priv); | |
1297 | int i915_gem_execbuffer(struct drm_device *dev, void *data, | |
1298 | struct drm_file *file_priv); | |
76446cac JB |
1299 | int i915_gem_execbuffer2(struct drm_device *dev, void *data, |
1300 | struct drm_file *file_priv); | |
673a394b EA |
1301 | int i915_gem_pin_ioctl(struct drm_device *dev, void *data, |
1302 | struct drm_file *file_priv); | |
1303 | int i915_gem_unpin_ioctl(struct drm_device *dev, void *data, | |
1304 | struct drm_file *file_priv); | |
1305 | int i915_gem_busy_ioctl(struct drm_device *dev, void *data, | |
1306 | struct drm_file *file_priv); | |
e6994aee CW |
1307 | int i915_gem_get_cacheing_ioctl(struct drm_device *dev, void *data, |
1308 | struct drm_file *file); | |
1309 | int i915_gem_set_cacheing_ioctl(struct drm_device *dev, void *data, | |
1310 | struct drm_file *file); | |
673a394b EA |
1311 | int i915_gem_throttle_ioctl(struct drm_device *dev, void *data, |
1312 | struct drm_file *file_priv); | |
3ef94daa CW |
1313 | int i915_gem_madvise_ioctl(struct drm_device *dev, void *data, |
1314 | struct drm_file *file_priv); | |
673a394b EA |
1315 | int i915_gem_entervt_ioctl(struct drm_device *dev, void *data, |
1316 | struct drm_file *file_priv); | |
1317 | int i915_gem_leavevt_ioctl(struct drm_device *dev, void *data, | |
1318 | struct drm_file *file_priv); | |
1319 | int i915_gem_set_tiling(struct drm_device *dev, void *data, | |
1320 | struct drm_file *file_priv); | |
1321 | int i915_gem_get_tiling(struct drm_device *dev, void *data, | |
1322 | struct drm_file *file_priv); | |
5a125c3c EA |
1323 | int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data, |
1324 | struct drm_file *file_priv); | |
23ba4fd0 BW |
1325 | int i915_gem_wait_ioctl(struct drm_device *dev, void *data, |
1326 | struct drm_file *file_priv); | |
673a394b | 1327 | void i915_gem_load(struct drm_device *dev); |
673a394b | 1328 | int i915_gem_init_object(struct drm_gem_object *obj); |
37e680a1 CW |
1329 | void i915_gem_object_init(struct drm_i915_gem_object *obj, |
1330 | const struct drm_i915_gem_object_ops *ops); | |
05394f39 CW |
1331 | struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev, |
1332 | size_t size); | |
673a394b | 1333 | void i915_gem_free_object(struct drm_gem_object *obj); |
2021746e CW |
1334 | int __must_check i915_gem_object_pin(struct drm_i915_gem_object *obj, |
1335 | uint32_t alignment, | |
86a1ee26 CW |
1336 | bool map_and_fenceable, |
1337 | bool nonblocking); | |
05394f39 | 1338 | void i915_gem_object_unpin(struct drm_i915_gem_object *obj); |
2021746e | 1339 | int __must_check i915_gem_object_unbind(struct drm_i915_gem_object *obj); |
05394f39 | 1340 | void i915_gem_release_mmap(struct drm_i915_gem_object *obj); |
673a394b | 1341 | void i915_gem_lastclose(struct drm_device *dev); |
f787a5f5 | 1342 | |
37e680a1 | 1343 | int __must_check i915_gem_object_get_pages(struct drm_i915_gem_object *obj); |
54cf91dc | 1344 | int __must_check i915_mutex_lock_interruptible(struct drm_device *dev); |
2911a35b BW |
1345 | int i915_gem_object_sync(struct drm_i915_gem_object *obj, |
1346 | struct intel_ring_buffer *to); | |
54cf91dc | 1347 | void i915_gem_object_move_to_active(struct drm_i915_gem_object *obj, |
1ec14ad3 CW |
1348 | struct intel_ring_buffer *ring, |
1349 | u32 seqno); | |
54cf91dc | 1350 | |
ff72145b DA |
1351 | int i915_gem_dumb_create(struct drm_file *file_priv, |
1352 | struct drm_device *dev, | |
1353 | struct drm_mode_create_dumb *args); | |
1354 | int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev, | |
1355 | uint32_t handle, uint64_t *offset); | |
1356 | int i915_gem_dumb_destroy(struct drm_file *file_priv, struct drm_device *dev, | |
0206e353 | 1357 | uint32_t handle); |
f787a5f5 CW |
1358 | /** |
1359 | * Returns true if seq1 is later than seq2. | |
1360 | */ | |
1361 | static inline bool | |
1362 | i915_seqno_passed(uint32_t seq1, uint32_t seq2) | |
1363 | { | |
1364 | return (int32_t)(seq1 - seq2) >= 0; | |
1365 | } | |
1366 | ||
53d227f2 | 1367 | u32 i915_gem_next_request_seqno(struct intel_ring_buffer *ring); |
54cf91dc | 1368 | |
06d98131 | 1369 | int __must_check i915_gem_object_get_fence(struct drm_i915_gem_object *obj); |
d9e86c0e | 1370 | int __must_check i915_gem_object_put_fence(struct drm_i915_gem_object *obj); |
2021746e | 1371 | |
9a5a53b3 | 1372 | static inline bool |
1690e1eb CW |
1373 | i915_gem_object_pin_fence(struct drm_i915_gem_object *obj) |
1374 | { | |
1375 | if (obj->fence_reg != I915_FENCE_REG_NONE) { | |
1376 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; | |
1377 | dev_priv->fence_regs[obj->fence_reg].pin_count++; | |
9a5a53b3 CW |
1378 | return true; |
1379 | } else | |
1380 | return false; | |
1690e1eb CW |
1381 | } |
1382 | ||
1383 | static inline void | |
1384 | i915_gem_object_unpin_fence(struct drm_i915_gem_object *obj) | |
1385 | { | |
1386 | if (obj->fence_reg != I915_FENCE_REG_NONE) { | |
1387 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; | |
1388 | dev_priv->fence_regs[obj->fence_reg].pin_count--; | |
1389 | } | |
1390 | } | |
1391 | ||
b09a1fec | 1392 | void i915_gem_retire_requests(struct drm_device *dev); |
a71d8d94 | 1393 | void i915_gem_retire_requests_ring(struct intel_ring_buffer *ring); |
d6b2c790 DV |
1394 | int __must_check i915_gem_check_wedge(struct drm_i915_private *dev_priv, |
1395 | bool interruptible); | |
a71d8d94 | 1396 | |
069efc1d | 1397 | void i915_gem_reset(struct drm_device *dev); |
05394f39 | 1398 | void i915_gem_clflush_object(struct drm_i915_gem_object *obj); |
2021746e CW |
1399 | int __must_check i915_gem_object_set_domain(struct drm_i915_gem_object *obj, |
1400 | uint32_t read_domains, | |
1401 | uint32_t write_domain); | |
a8198eea | 1402 | int __must_check i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj); |
1070a42b | 1403 | int __must_check i915_gem_init(struct drm_device *dev); |
f691e2f4 | 1404 | int __must_check i915_gem_init_hw(struct drm_device *dev); |
b9524a1e | 1405 | void i915_gem_l3_remap(struct drm_device *dev); |
f691e2f4 | 1406 | void i915_gem_init_swizzling(struct drm_device *dev); |
e21af88d | 1407 | void i915_gem_init_ppgtt(struct drm_device *dev); |
79e53945 | 1408 | void i915_gem_cleanup_ringbuffer(struct drm_device *dev); |
b2da9fe5 | 1409 | int __must_check i915_gpu_idle(struct drm_device *dev); |
2021746e | 1410 | int __must_check i915_gem_idle(struct drm_device *dev); |
3bb73aba CW |
1411 | int i915_add_request(struct intel_ring_buffer *ring, |
1412 | struct drm_file *file, | |
1413 | struct drm_i915_gem_request *request); | |
199b2bc2 BW |
1414 | int __must_check i915_wait_seqno(struct intel_ring_buffer *ring, |
1415 | uint32_t seqno); | |
de151cf6 | 1416 | int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf); |
2021746e CW |
1417 | int __must_check |
1418 | i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, | |
1419 | bool write); | |
1420 | int __must_check | |
dabdfe02 CW |
1421 | i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write); |
1422 | int __must_check | |
2da3b9b9 CW |
1423 | i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj, |
1424 | u32 alignment, | |
2021746e | 1425 | struct intel_ring_buffer *pipelined); |
71acb5eb | 1426 | int i915_gem_attach_phys_object(struct drm_device *dev, |
05394f39 | 1427 | struct drm_i915_gem_object *obj, |
6eeefaf3 CW |
1428 | int id, |
1429 | int align); | |
71acb5eb | 1430 | void i915_gem_detach_phys_object(struct drm_device *dev, |
05394f39 | 1431 | struct drm_i915_gem_object *obj); |
71acb5eb | 1432 | void i915_gem_free_all_phys_object(struct drm_device *dev); |
05394f39 | 1433 | void i915_gem_release(struct drm_device *dev, struct drm_file *file); |
673a394b | 1434 | |
467cffba | 1435 | uint32_t |
e28f8711 CW |
1436 | i915_gem_get_unfenced_gtt_alignment(struct drm_device *dev, |
1437 | uint32_t size, | |
1438 | int tiling_mode); | |
467cffba | 1439 | |
e4ffd173 CW |
1440 | int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj, |
1441 | enum i915_cache_level cache_level); | |
1442 | ||
1286ff73 DV |
1443 | struct drm_gem_object *i915_gem_prime_import(struct drm_device *dev, |
1444 | struct dma_buf *dma_buf); | |
1445 | ||
1446 | struct dma_buf *i915_gem_prime_export(struct drm_device *dev, | |
1447 | struct drm_gem_object *gem_obj, int flags); | |
1448 | ||
254f965c BW |
1449 | /* i915_gem_context.c */ |
1450 | void i915_gem_context_init(struct drm_device *dev); | |
1451 | void i915_gem_context_fini(struct drm_device *dev); | |
254f965c | 1452 | void i915_gem_context_close(struct drm_device *dev, struct drm_file *file); |
e0556841 BW |
1453 | int i915_switch_context(struct intel_ring_buffer *ring, |
1454 | struct drm_file *file, int to_id); | |
84624813 BW |
1455 | int i915_gem_context_create_ioctl(struct drm_device *dev, void *data, |
1456 | struct drm_file *file); | |
1457 | int i915_gem_context_destroy_ioctl(struct drm_device *dev, void *data, | |
1458 | struct drm_file *file); | |
1286ff73 | 1459 | |
76aaf220 | 1460 | /* i915_gem_gtt.c */ |
1d2a314c DV |
1461 | int __must_check i915_gem_init_aliasing_ppgtt(struct drm_device *dev); |
1462 | void i915_gem_cleanup_aliasing_ppgtt(struct drm_device *dev); | |
7bddb01f DV |
1463 | void i915_ppgtt_bind_object(struct i915_hw_ppgtt *ppgtt, |
1464 | struct drm_i915_gem_object *obj, | |
1465 | enum i915_cache_level cache_level); | |
1466 | void i915_ppgtt_unbind_object(struct i915_hw_ppgtt *ppgtt, | |
1467 | struct drm_i915_gem_object *obj); | |
1d2a314c | 1468 | |
76aaf220 | 1469 | void i915_gem_restore_gtt_mappings(struct drm_device *dev); |
74163907 DV |
1470 | int __must_check i915_gem_gtt_prepare_object(struct drm_i915_gem_object *obj); |
1471 | void i915_gem_gtt_bind_object(struct drm_i915_gem_object *obj, | |
e4ffd173 | 1472 | enum i915_cache_level cache_level); |
05394f39 | 1473 | void i915_gem_gtt_unbind_object(struct drm_i915_gem_object *obj); |
74163907 | 1474 | void i915_gem_gtt_finish_object(struct drm_i915_gem_object *obj); |
644ec02b DV |
1475 | void i915_gem_init_global_gtt(struct drm_device *dev, |
1476 | unsigned long start, | |
1477 | unsigned long mappable_end, | |
1478 | unsigned long end); | |
76aaf220 | 1479 | |
b47eb4a2 | 1480 | /* i915_gem_evict.c */ |
2021746e | 1481 | int __must_check i915_gem_evict_something(struct drm_device *dev, int min_size, |
42d6ab48 CW |
1482 | unsigned alignment, |
1483 | unsigned cache_level, | |
86a1ee26 CW |
1484 | bool mappable, |
1485 | bool nonblock); | |
6c085a72 | 1486 | int i915_gem_evict_everything(struct drm_device *dev); |
b47eb4a2 | 1487 | |
9797fbfb CW |
1488 | /* i915_gem_stolen.c */ |
1489 | int i915_gem_init_stolen(struct drm_device *dev); | |
1490 | void i915_gem_cleanup_stolen(struct drm_device *dev); | |
1491 | ||
673a394b EA |
1492 | /* i915_gem_tiling.c */ |
1493 | void i915_gem_detect_bit_6_swizzle(struct drm_device *dev); | |
05394f39 CW |
1494 | void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj); |
1495 | void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj); | |
673a394b EA |
1496 | |
1497 | /* i915_gem_debug.c */ | |
05394f39 | 1498 | void i915_gem_dump_object(struct drm_i915_gem_object *obj, int len, |
673a394b | 1499 | const char *where, uint32_t mark); |
23bc5982 CW |
1500 | #if WATCH_LISTS |
1501 | int i915_verify_lists(struct drm_device *dev); | |
673a394b | 1502 | #else |
23bc5982 | 1503 | #define i915_verify_lists(dev) 0 |
673a394b | 1504 | #endif |
05394f39 CW |
1505 | void i915_gem_object_check_coherency(struct drm_i915_gem_object *obj, |
1506 | int handle); | |
1507 | void i915_gem_dump_object(struct drm_i915_gem_object *obj, int len, | |
673a394b | 1508 | const char *where, uint32_t mark); |
1da177e4 | 1509 | |
2017263e | 1510 | /* i915_debugfs.c */ |
27c202ad BG |
1511 | int i915_debugfs_init(struct drm_minor *minor); |
1512 | void i915_debugfs_cleanup(struct drm_minor *minor); | |
2017263e | 1513 | |
317c35d1 JB |
1514 | /* i915_suspend.c */ |
1515 | extern int i915_save_state(struct drm_device *dev); | |
1516 | extern int i915_restore_state(struct drm_device *dev); | |
0a3e67a4 JB |
1517 | |
1518 | /* i915_suspend.c */ | |
1519 | extern int i915_save_state(struct drm_device *dev); | |
1520 | extern int i915_restore_state(struct drm_device *dev); | |
317c35d1 | 1521 | |
0136db58 BW |
1522 | /* i915_sysfs.c */ |
1523 | void i915_setup_sysfs(struct drm_device *dev_priv); | |
1524 | void i915_teardown_sysfs(struct drm_device *dev_priv); | |
1525 | ||
f899fc64 CW |
1526 | /* intel_i2c.c */ |
1527 | extern int intel_setup_gmbus(struct drm_device *dev); | |
1528 | extern void intel_teardown_gmbus(struct drm_device *dev); | |
3bd7d909 DK |
1529 | extern inline bool intel_gmbus_is_port_valid(unsigned port) |
1530 | { | |
2ed06c93 | 1531 | return (port >= GMBUS_PORT_SSC && port <= GMBUS_PORT_DPD); |
3bd7d909 DK |
1532 | } |
1533 | ||
1534 | extern struct i2c_adapter *intel_gmbus_get_adapter( | |
1535 | struct drm_i915_private *dev_priv, unsigned port); | |
e957d772 CW |
1536 | extern void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed); |
1537 | extern void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit); | |
b8232e90 CW |
1538 | extern inline bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter) |
1539 | { | |
1540 | return container_of(adapter, struct intel_gmbus, adapter)->force_bit; | |
1541 | } | |
f899fc64 CW |
1542 | extern void intel_i2c_reset(struct drm_device *dev); |
1543 | ||
3b617967 | 1544 | /* intel_opregion.c */ |
44834a67 CW |
1545 | extern int intel_opregion_setup(struct drm_device *dev); |
1546 | #ifdef CONFIG_ACPI | |
1547 | extern void intel_opregion_init(struct drm_device *dev); | |
1548 | extern void intel_opregion_fini(struct drm_device *dev); | |
3b617967 CW |
1549 | extern void intel_opregion_asle_intr(struct drm_device *dev); |
1550 | extern void intel_opregion_gse_intr(struct drm_device *dev); | |
1551 | extern void intel_opregion_enable_asle(struct drm_device *dev); | |
65e082c9 | 1552 | #else |
44834a67 CW |
1553 | static inline void intel_opregion_init(struct drm_device *dev) { return; } |
1554 | static inline void intel_opregion_fini(struct drm_device *dev) { return; } | |
3b617967 CW |
1555 | static inline void intel_opregion_asle_intr(struct drm_device *dev) { return; } |
1556 | static inline void intel_opregion_gse_intr(struct drm_device *dev) { return; } | |
1557 | static inline void intel_opregion_enable_asle(struct drm_device *dev) { return; } | |
65e082c9 | 1558 | #endif |
8ee1c3db | 1559 | |
723bfd70 JB |
1560 | /* intel_acpi.c */ |
1561 | #ifdef CONFIG_ACPI | |
1562 | extern void intel_register_dsm_handler(void); | |
1563 | extern void intel_unregister_dsm_handler(void); | |
1564 | #else | |
1565 | static inline void intel_register_dsm_handler(void) { return; } | |
1566 | static inline void intel_unregister_dsm_handler(void) { return; } | |
1567 | #endif /* CONFIG_ACPI */ | |
1568 | ||
79e53945 | 1569 | /* modesetting */ |
f817586c | 1570 | extern void intel_modeset_init_hw(struct drm_device *dev); |
79e53945 | 1571 | extern void intel_modeset_init(struct drm_device *dev); |
2c7111db | 1572 | extern void intel_modeset_gem_init(struct drm_device *dev); |
79e53945 | 1573 | extern void intel_modeset_cleanup(struct drm_device *dev); |
28d52043 | 1574 | extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state); |
24929352 | 1575 | extern void intel_modeset_setup_hw_state(struct drm_device *dev); |
ee5382ae | 1576 | extern bool intel_fbc_enabled(struct drm_device *dev); |
43a9539f | 1577 | extern void intel_disable_fbc(struct drm_device *dev); |
7648fa99 | 1578 | extern bool ironlake_set_drps(struct drm_device *dev, u8 val); |
9fb526db | 1579 | extern void ironlake_init_pch_refclk(struct drm_device *dev); |
3b8d8d91 | 1580 | extern void gen6_set_rps(struct drm_device *dev, u8 val); |
0206e353 AJ |
1581 | extern void intel_detect_pch(struct drm_device *dev); |
1582 | extern int intel_trans_dp_port_sel(struct drm_crtc *crtc); | |
0136db58 | 1583 | extern int intel_enable_rc6(const struct drm_device *dev); |
3bad0781 | 1584 | |
2911a35b | 1585 | extern bool i915_semaphore_is_enabled(struct drm_device *dev); |
c0c7babc BW |
1586 | int i915_reg_read_ioctl(struct drm_device *dev, void *data, |
1587 | struct drm_file *file); | |
575155a9 | 1588 | |
6ef3d427 | 1589 | /* overlay */ |
3bd3c932 | 1590 | #ifdef CONFIG_DEBUG_FS |
6ef3d427 CW |
1591 | extern struct intel_overlay_error_state *intel_overlay_capture_error_state(struct drm_device *dev); |
1592 | extern void intel_overlay_print_error_state(struct seq_file *m, struct intel_overlay_error_state *error); | |
c4a1d9e4 CW |
1593 | |
1594 | extern struct intel_display_error_state *intel_display_capture_error_state(struct drm_device *dev); | |
1595 | extern void intel_display_print_error_state(struct seq_file *m, | |
1596 | struct drm_device *dev, | |
1597 | struct intel_display_error_state *error); | |
3bd3c932 | 1598 | #endif |
6ef3d427 | 1599 | |
b7287d80 BW |
1600 | /* On SNB platform, before reading ring registers forcewake bit |
1601 | * must be set to prevent GT core from power down and stale values being | |
1602 | * returned. | |
1603 | */ | |
fcca7926 BW |
1604 | void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv); |
1605 | void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv); | |
67a3744f | 1606 | int __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv); |
b7287d80 | 1607 | |
5f75377d | 1608 | #define __i915_read(x, y) \ |
f7000883 | 1609 | u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg); |
fcca7926 | 1610 | |
5f75377d KP |
1611 | __i915_read(8, b) |
1612 | __i915_read(16, w) | |
1613 | __i915_read(32, l) | |
1614 | __i915_read(64, q) | |
1615 | #undef __i915_read | |
1616 | ||
1617 | #define __i915_write(x, y) \ | |
f7000883 AK |
1618 | void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x val); |
1619 | ||
5f75377d KP |
1620 | __i915_write(8, b) |
1621 | __i915_write(16, w) | |
1622 | __i915_write(32, l) | |
1623 | __i915_write(64, q) | |
1624 | #undef __i915_write | |
1625 | ||
1626 | #define I915_READ8(reg) i915_read8(dev_priv, (reg)) | |
1627 | #define I915_WRITE8(reg, val) i915_write8(dev_priv, (reg), (val)) | |
1628 | ||
1629 | #define I915_READ16(reg) i915_read16(dev_priv, (reg)) | |
1630 | #define I915_WRITE16(reg, val) i915_write16(dev_priv, (reg), (val)) | |
1631 | #define I915_READ16_NOTRACE(reg) readw(dev_priv->regs + (reg)) | |
1632 | #define I915_WRITE16_NOTRACE(reg, val) writew(val, dev_priv->regs + (reg)) | |
1633 | ||
1634 | #define I915_READ(reg) i915_read32(dev_priv, (reg)) | |
1635 | #define I915_WRITE(reg, val) i915_write32(dev_priv, (reg), (val)) | |
cae5852d ZN |
1636 | #define I915_READ_NOTRACE(reg) readl(dev_priv->regs + (reg)) |
1637 | #define I915_WRITE_NOTRACE(reg, val) writel(val, dev_priv->regs + (reg)) | |
5f75377d KP |
1638 | |
1639 | #define I915_WRITE64(reg, val) i915_write64(dev_priv, (reg), (val)) | |
1640 | #define I915_READ64(reg) i915_read64(dev_priv, (reg)) | |
cae5852d ZN |
1641 | |
1642 | #define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg) | |
1643 | #define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg) | |
1644 | ||
ba4f01a3 | 1645 | |
1da177e4 | 1646 | #endif |