]>
Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*- |
2 | */ | |
0d6aa60b | 3 | /* |
bc54fd1a | 4 | * |
1da177e4 LT |
5 | * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. |
6 | * All Rights Reserved. | |
bc54fd1a DA |
7 | * |
8 | * Permission is hereby granted, free of charge, to any person obtaining a | |
9 | * copy of this software and associated documentation files (the | |
10 | * "Software"), to deal in the Software without restriction, including | |
11 | * without limitation the rights to use, copy, modify, merge, publish, | |
12 | * distribute, sub license, and/or sell copies of the Software, and to | |
13 | * permit persons to whom the Software is furnished to do so, subject to | |
14 | * the following conditions: | |
15 | * | |
16 | * The above copyright notice and this permission notice (including the | |
17 | * next paragraph) shall be included in all copies or substantial portions | |
18 | * of the Software. | |
19 | * | |
20 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS | |
21 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
22 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. | |
23 | * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR | |
24 | * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, | |
25 | * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE | |
26 | * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. | |
27 | * | |
0d6aa60b | 28 | */ |
1da177e4 LT |
29 | |
30 | #ifndef _I915_DRV_H_ | |
31 | #define _I915_DRV_H_ | |
32 | ||
e9b73c67 CW |
33 | #include <uapi/drm/i915_drm.h> |
34 | ||
585fb111 | 35 | #include "i915_reg.h" |
79e53945 | 36 | #include "intel_bios.h" |
8187a2b7 | 37 | #include "intel_ringbuffer.h" |
b20385f1 | 38 | #include "intel_lrc.h" |
0260c420 | 39 | #include "i915_gem_gtt.h" |
0839ccb8 | 40 | #include <linux/io-mapping.h> |
f899fc64 | 41 | #include <linux/i2c.h> |
c167a6fc | 42 | #include <linux/i2c-algo-bit.h> |
0ade6386 | 43 | #include <drm/intel-gtt.h> |
aaa6fd2a | 44 | #include <linux/backlight.h> |
5cc9ed4b | 45 | #include <linux/hashtable.h> |
2911a35b | 46 | #include <linux/intel-iommu.h> |
742cbee8 | 47 | #include <linux/kref.h> |
9ee32fea | 48 | #include <linux/pm_qos.h> |
585fb111 | 49 | |
1da177e4 LT |
50 | /* General customization: |
51 | */ | |
52 | ||
53 | #define DRIVER_AUTHOR "Tungsten Graphics, Inc." | |
54 | ||
55 | #define DRIVER_NAME "i915" | |
56 | #define DRIVER_DESC "Intel Graphics" | |
2c0827cf | 57 | #define DRIVER_DATE "20140808" |
1da177e4 | 58 | |
317c35d1 | 59 | enum pipe { |
752aa88a | 60 | INVALID_PIPE = -1, |
317c35d1 JB |
61 | PIPE_A = 0, |
62 | PIPE_B, | |
9db4a9c7 | 63 | PIPE_C, |
a57c774a AK |
64 | _PIPE_EDP, |
65 | I915_MAX_PIPES = _PIPE_EDP | |
317c35d1 | 66 | }; |
9db4a9c7 | 67 | #define pipe_name(p) ((p) + 'A') |
317c35d1 | 68 | |
a5c961d1 PZ |
69 | enum transcoder { |
70 | TRANSCODER_A = 0, | |
71 | TRANSCODER_B, | |
72 | TRANSCODER_C, | |
a57c774a AK |
73 | TRANSCODER_EDP, |
74 | I915_MAX_TRANSCODERS | |
a5c961d1 PZ |
75 | }; |
76 | #define transcoder_name(t) ((t) + 'A') | |
77 | ||
80824003 JB |
78 | enum plane { |
79 | PLANE_A = 0, | |
80 | PLANE_B, | |
9db4a9c7 | 81 | PLANE_C, |
80824003 | 82 | }; |
9db4a9c7 | 83 | #define plane_name(p) ((p) + 'A') |
52440211 | 84 | |
d615a166 | 85 | #define sprite_name(p, s) ((p) * INTEL_INFO(dev)->num_sprites[(p)] + (s) + 'A') |
06da8da2 | 86 | |
2b139522 ED |
87 | enum port { |
88 | PORT_A = 0, | |
89 | PORT_B, | |
90 | PORT_C, | |
91 | PORT_D, | |
92 | PORT_E, | |
93 | I915_MAX_PORTS | |
94 | }; | |
95 | #define port_name(p) ((p) + 'A') | |
96 | ||
a09caddd | 97 | #define I915_NUM_PHYS_VLV 2 |
e4607fcf CML |
98 | |
99 | enum dpio_channel { | |
100 | DPIO_CH0, | |
101 | DPIO_CH1 | |
102 | }; | |
103 | ||
104 | enum dpio_phy { | |
105 | DPIO_PHY0, | |
106 | DPIO_PHY1 | |
107 | }; | |
108 | ||
b97186f0 PZ |
109 | enum intel_display_power_domain { |
110 | POWER_DOMAIN_PIPE_A, | |
111 | POWER_DOMAIN_PIPE_B, | |
112 | POWER_DOMAIN_PIPE_C, | |
113 | POWER_DOMAIN_PIPE_A_PANEL_FITTER, | |
114 | POWER_DOMAIN_PIPE_B_PANEL_FITTER, | |
115 | POWER_DOMAIN_PIPE_C_PANEL_FITTER, | |
116 | POWER_DOMAIN_TRANSCODER_A, | |
117 | POWER_DOMAIN_TRANSCODER_B, | |
118 | POWER_DOMAIN_TRANSCODER_C, | |
f52e353e | 119 | POWER_DOMAIN_TRANSCODER_EDP, |
319be8ae ID |
120 | POWER_DOMAIN_PORT_DDI_A_2_LANES, |
121 | POWER_DOMAIN_PORT_DDI_A_4_LANES, | |
122 | POWER_DOMAIN_PORT_DDI_B_2_LANES, | |
123 | POWER_DOMAIN_PORT_DDI_B_4_LANES, | |
124 | POWER_DOMAIN_PORT_DDI_C_2_LANES, | |
125 | POWER_DOMAIN_PORT_DDI_C_4_LANES, | |
126 | POWER_DOMAIN_PORT_DDI_D_2_LANES, | |
127 | POWER_DOMAIN_PORT_DDI_D_4_LANES, | |
128 | POWER_DOMAIN_PORT_DSI, | |
129 | POWER_DOMAIN_PORT_CRT, | |
130 | POWER_DOMAIN_PORT_OTHER, | |
cdf8dd7f | 131 | POWER_DOMAIN_VGA, |
fbeeaa23 | 132 | POWER_DOMAIN_AUDIO, |
bd2bb1b9 | 133 | POWER_DOMAIN_PLLS, |
baa70707 | 134 | POWER_DOMAIN_INIT, |
bddc7645 ID |
135 | |
136 | POWER_DOMAIN_NUM, | |
b97186f0 PZ |
137 | }; |
138 | ||
139 | #define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A) | |
140 | #define POWER_DOMAIN_PIPE_PANEL_FITTER(pipe) \ | |
141 | ((pipe) + POWER_DOMAIN_PIPE_A_PANEL_FITTER) | |
f52e353e ID |
142 | #define POWER_DOMAIN_TRANSCODER(tran) \ |
143 | ((tran) == TRANSCODER_EDP ? POWER_DOMAIN_TRANSCODER_EDP : \ | |
144 | (tran) + POWER_DOMAIN_TRANSCODER_A) | |
b97186f0 | 145 | |
1d843f9d EE |
146 | enum hpd_pin { |
147 | HPD_NONE = 0, | |
148 | HPD_PORT_A = HPD_NONE, /* PORT_A is internal */ | |
149 | HPD_TV = HPD_NONE, /* TV is known to be unreliable */ | |
150 | HPD_CRT, | |
151 | HPD_SDVO_B, | |
152 | HPD_SDVO_C, | |
153 | HPD_PORT_B, | |
154 | HPD_PORT_C, | |
155 | HPD_PORT_D, | |
156 | HPD_NUM_PINS | |
157 | }; | |
158 | ||
2a2d5482 CW |
159 | #define I915_GEM_GPU_DOMAINS \ |
160 | (I915_GEM_DOMAIN_RENDER | \ | |
161 | I915_GEM_DOMAIN_SAMPLER | \ | |
162 | I915_GEM_DOMAIN_COMMAND | \ | |
163 | I915_GEM_DOMAIN_INSTRUCTION | \ | |
164 | I915_GEM_DOMAIN_VERTEX) | |
62fdfeaf | 165 | |
7eb552ae | 166 | #define for_each_pipe(p) for ((p) = 0; (p) < INTEL_INFO(dev)->num_pipes; (p)++) |
d615a166 | 167 | #define for_each_sprite(p, s) for ((s) = 0; (s) < INTEL_INFO(dev)->num_sprites[(p)]; (s)++) |
9db4a9c7 | 168 | |
d79b814d DL |
169 | #define for_each_crtc(dev, crtc) \ |
170 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) | |
171 | ||
d063ae48 DL |
172 | #define for_each_intel_crtc(dev, intel_crtc) \ |
173 | list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, base.head) | |
174 | ||
b2784e15 DL |
175 | #define for_each_intel_encoder(dev, intel_encoder) \ |
176 | list_for_each_entry(intel_encoder, \ | |
177 | &(dev)->mode_config.encoder_list, \ | |
178 | base.head) | |
179 | ||
6c2b7c12 DV |
180 | #define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \ |
181 | list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \ | |
182 | if ((intel_encoder)->base.crtc == (__crtc)) | |
183 | ||
53f5e3ca JB |
184 | #define for_each_connector_on_encoder(dev, __encoder, intel_connector) \ |
185 | list_for_each_entry((intel_connector), &(dev)->mode_config.connector_list, base.head) \ | |
186 | if ((intel_connector)->base.encoder == (__encoder)) | |
187 | ||
b04c5bd6 BF |
188 | #define for_each_power_domain(domain, mask) \ |
189 | for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \ | |
190 | if ((1 << (domain)) & (mask)) | |
191 | ||
e7b903d2 | 192 | struct drm_i915_private; |
5cc9ed4b | 193 | struct i915_mmu_object; |
e7b903d2 | 194 | |
46edb027 DV |
195 | enum intel_dpll_id { |
196 | DPLL_ID_PRIVATE = -1, /* non-shared dpll in use */ | |
197 | /* real shared dpll ids must be >= 0 */ | |
9cd86933 DV |
198 | DPLL_ID_PCH_PLL_A = 0, |
199 | DPLL_ID_PCH_PLL_B = 1, | |
200 | DPLL_ID_WRPLL1 = 0, | |
201 | DPLL_ID_WRPLL2 = 1, | |
46edb027 DV |
202 | }; |
203 | #define I915_NUM_PLLS 2 | |
204 | ||
5358901f | 205 | struct intel_dpll_hw_state { |
dcfc3552 | 206 | /* i9xx, pch plls */ |
66e985c0 | 207 | uint32_t dpll; |
8bcc2795 | 208 | uint32_t dpll_md; |
66e985c0 DV |
209 | uint32_t fp0; |
210 | uint32_t fp1; | |
dcfc3552 DL |
211 | |
212 | /* hsw, bdw */ | |
d452c5b6 | 213 | uint32_t wrpll; |
5358901f DV |
214 | }; |
215 | ||
e72f9fbf | 216 | struct intel_shared_dpll { |
ee7b9f93 JB |
217 | int refcount; /* count of number of CRTCs sharing this PLL */ |
218 | int active; /* count of number of active CRTCs (i.e. DPMS on) */ | |
219 | bool on; /* is the PLL actually active? Disabled during modeset */ | |
46edb027 DV |
220 | const char *name; |
221 | /* should match the index in the dev_priv->shared_dplls array */ | |
222 | enum intel_dpll_id id; | |
5358901f | 223 | struct intel_dpll_hw_state hw_state; |
96f6128c DV |
224 | /* The mode_set hook is optional and should be used together with the |
225 | * intel_prepare_shared_dpll function. */ | |
15bdd4cf DV |
226 | void (*mode_set)(struct drm_i915_private *dev_priv, |
227 | struct intel_shared_dpll *pll); | |
e7b903d2 DV |
228 | void (*enable)(struct drm_i915_private *dev_priv, |
229 | struct intel_shared_dpll *pll); | |
230 | void (*disable)(struct drm_i915_private *dev_priv, | |
231 | struct intel_shared_dpll *pll); | |
5358901f DV |
232 | bool (*get_hw_state)(struct drm_i915_private *dev_priv, |
233 | struct intel_shared_dpll *pll, | |
234 | struct intel_dpll_hw_state *hw_state); | |
ee7b9f93 | 235 | }; |
ee7b9f93 | 236 | |
e69d0bc1 DV |
237 | /* Used by dp and fdi links */ |
238 | struct intel_link_m_n { | |
239 | uint32_t tu; | |
240 | uint32_t gmch_m; | |
241 | uint32_t gmch_n; | |
242 | uint32_t link_m; | |
243 | uint32_t link_n; | |
244 | }; | |
245 | ||
246 | void intel_link_compute_m_n(int bpp, int nlanes, | |
247 | int pixel_clock, int link_clock, | |
248 | struct intel_link_m_n *m_n); | |
249 | ||
1da177e4 LT |
250 | /* Interface history: |
251 | * | |
252 | * 1.1: Original. | |
0d6aa60b DA |
253 | * 1.2: Add Power Management |
254 | * 1.3: Add vblank support | |
de227f5f | 255 | * 1.4: Fix cmdbuffer path, add heap destroy |
702880f2 | 256 | * 1.5: Add vblank pipe configuration |
2228ed67 MD |
257 | * 1.6: - New ioctl for scheduling buffer swaps on vertical blank |
258 | * - Support vertical blank on secondary display pipe | |
1da177e4 LT |
259 | */ |
260 | #define DRIVER_MAJOR 1 | |
2228ed67 | 261 | #define DRIVER_MINOR 6 |
1da177e4 LT |
262 | #define DRIVER_PATCHLEVEL 0 |
263 | ||
23bc5982 | 264 | #define WATCH_LISTS 0 |
42d6ab48 | 265 | #define WATCH_GTT 0 |
673a394b | 266 | |
0a3e67a4 JB |
267 | struct opregion_header; |
268 | struct opregion_acpi; | |
269 | struct opregion_swsci; | |
270 | struct opregion_asle; | |
271 | ||
8ee1c3db | 272 | struct intel_opregion { |
5bc4418b BW |
273 | struct opregion_header __iomem *header; |
274 | struct opregion_acpi __iomem *acpi; | |
275 | struct opregion_swsci __iomem *swsci; | |
ebde53c7 JN |
276 | u32 swsci_gbda_sub_functions; |
277 | u32 swsci_sbcb_sub_functions; | |
5bc4418b BW |
278 | struct opregion_asle __iomem *asle; |
279 | void __iomem *vbt; | |
01fe9dbd | 280 | u32 __iomem *lid_state; |
91a60f20 | 281 | struct work_struct asle_work; |
8ee1c3db | 282 | }; |
44834a67 | 283 | #define OPREGION_SIZE (8*1024) |
8ee1c3db | 284 | |
6ef3d427 CW |
285 | struct intel_overlay; |
286 | struct intel_overlay_error_state; | |
287 | ||
7c1c2871 DA |
288 | struct drm_i915_master_private { |
289 | drm_local_map_t *sarea; | |
290 | struct _drm_i915_sarea *sarea_priv; | |
291 | }; | |
de151cf6 | 292 | #define I915_FENCE_REG_NONE -1 |
42b5aeab VS |
293 | #define I915_MAX_NUM_FENCES 32 |
294 | /* 32 fences + sign bit for FENCE_REG_NONE */ | |
295 | #define I915_MAX_NUM_FENCE_BITS 6 | |
de151cf6 JB |
296 | |
297 | struct drm_i915_fence_reg { | |
007cc8ac | 298 | struct list_head lru_list; |
caea7476 | 299 | struct drm_i915_gem_object *obj; |
1690e1eb | 300 | int pin_count; |
de151cf6 | 301 | }; |
7c1c2871 | 302 | |
9b9d172d | 303 | struct sdvo_device_mapping { |
e957d772 | 304 | u8 initialized; |
9b9d172d | 305 | u8 dvo_port; |
306 | u8 slave_addr; | |
307 | u8 dvo_wiring; | |
e957d772 | 308 | u8 i2c_pin; |
b1083333 | 309 | u8 ddc_pin; |
9b9d172d | 310 | }; |
311 | ||
c4a1d9e4 CW |
312 | struct intel_display_error_state; |
313 | ||
63eeaf38 | 314 | struct drm_i915_error_state { |
742cbee8 | 315 | struct kref ref; |
585b0288 BW |
316 | struct timeval time; |
317 | ||
cb383002 | 318 | char error_msg[128]; |
48b031e3 | 319 | u32 reset_count; |
62d5d69b | 320 | u32 suspend_count; |
cb383002 | 321 | |
585b0288 | 322 | /* Generic register state */ |
63eeaf38 JB |
323 | u32 eir; |
324 | u32 pgtbl_er; | |
be998e2e | 325 | u32 ier; |
885ea5a8 | 326 | u32 gtier[4]; |
b9a3906b | 327 | u32 ccid; |
0f3b6849 CW |
328 | u32 derrmr; |
329 | u32 forcewake; | |
585b0288 BW |
330 | u32 error; /* gen6+ */ |
331 | u32 err_int; /* gen7 */ | |
332 | u32 done_reg; | |
91ec5d11 BW |
333 | u32 gac_eco; |
334 | u32 gam_ecochk; | |
335 | u32 gab_ctl; | |
336 | u32 gfx_mode; | |
585b0288 | 337 | u32 extra_instdone[I915_NUM_INSTDONE_REG]; |
585b0288 BW |
338 | u64 fence[I915_MAX_NUM_FENCES]; |
339 | struct intel_overlay_error_state *overlay; | |
340 | struct intel_display_error_state *display; | |
0ca36d78 | 341 | struct drm_i915_error_object *semaphore_obj; |
585b0288 | 342 | |
52d39a21 | 343 | struct drm_i915_error_ring { |
372fbb8e | 344 | bool valid; |
362b8af7 BW |
345 | /* Software tracked state */ |
346 | bool waiting; | |
347 | int hangcheck_score; | |
348 | enum intel_ring_hangcheck_action hangcheck_action; | |
349 | int num_requests; | |
350 | ||
351 | /* our own tracking of ring head and tail */ | |
352 | u32 cpu_ring_head; | |
353 | u32 cpu_ring_tail; | |
354 | ||
355 | u32 semaphore_seqno[I915_NUM_RINGS - 1]; | |
356 | ||
357 | /* Register state */ | |
358 | u32 tail; | |
359 | u32 head; | |
360 | u32 ctl; | |
361 | u32 hws; | |
362 | u32 ipeir; | |
363 | u32 ipehr; | |
364 | u32 instdone; | |
362b8af7 BW |
365 | u32 bbstate; |
366 | u32 instpm; | |
367 | u32 instps; | |
368 | u32 seqno; | |
369 | u64 bbaddr; | |
50877445 | 370 | u64 acthd; |
362b8af7 | 371 | u32 fault_reg; |
13ffadd1 | 372 | u64 faddr; |
362b8af7 BW |
373 | u32 rc_psmi; /* sleep state */ |
374 | u32 semaphore_mboxes[I915_NUM_RINGS - 1]; | |
375 | ||
52d39a21 CW |
376 | struct drm_i915_error_object { |
377 | int page_count; | |
378 | u32 gtt_offset; | |
379 | u32 *pages[0]; | |
ab0e7ff9 | 380 | } *ringbuffer, *batchbuffer, *wa_batchbuffer, *ctx, *hws_page; |
362b8af7 | 381 | |
52d39a21 CW |
382 | struct drm_i915_error_request { |
383 | long jiffies; | |
384 | u32 seqno; | |
ee4f42b1 | 385 | u32 tail; |
52d39a21 | 386 | } *requests; |
6c7a01ec BW |
387 | |
388 | struct { | |
389 | u32 gfx_mode; | |
390 | union { | |
391 | u64 pdp[4]; | |
392 | u32 pp_dir_base; | |
393 | }; | |
394 | } vm_info; | |
ab0e7ff9 CW |
395 | |
396 | pid_t pid; | |
397 | char comm[TASK_COMM_LEN]; | |
52d39a21 | 398 | } ring[I915_NUM_RINGS]; |
9df30794 | 399 | struct drm_i915_error_buffer { |
a779e5ab | 400 | u32 size; |
9df30794 | 401 | u32 name; |
0201f1ec | 402 | u32 rseqno, wseqno; |
9df30794 CW |
403 | u32 gtt_offset; |
404 | u32 read_domains; | |
405 | u32 write_domain; | |
4b9de737 | 406 | s32 fence_reg:I915_MAX_NUM_FENCE_BITS; |
9df30794 CW |
407 | s32 pinned:2; |
408 | u32 tiling:2; | |
409 | u32 dirty:1; | |
410 | u32 purgeable:1; | |
5cc9ed4b | 411 | u32 userptr:1; |
5d1333fc | 412 | s32 ring:4; |
f56383cb | 413 | u32 cache_level:3; |
95f5301d | 414 | } **active_bo, **pinned_bo; |
6c7a01ec | 415 | |
95f5301d | 416 | u32 *active_bo_count, *pinned_bo_count; |
63eeaf38 JB |
417 | }; |
418 | ||
7bd688cd | 419 | struct intel_connector; |
b8cecdf5 | 420 | struct intel_crtc_config; |
46f297fb | 421 | struct intel_plane_config; |
0e8ffe1b | 422 | struct intel_crtc; |
ee9300bb DV |
423 | struct intel_limit; |
424 | struct dpll; | |
b8cecdf5 | 425 | |
e70236a8 | 426 | struct drm_i915_display_funcs { |
ee5382ae | 427 | bool (*fbc_enabled)(struct drm_device *dev); |
993495ae | 428 | void (*enable_fbc)(struct drm_crtc *crtc); |
e70236a8 JB |
429 | void (*disable_fbc)(struct drm_device *dev); |
430 | int (*get_display_clock_speed)(struct drm_device *dev); | |
431 | int (*get_fifo_size)(struct drm_device *dev, int plane); | |
ee9300bb DV |
432 | /** |
433 | * find_dpll() - Find the best values for the PLL | |
434 | * @limit: limits for the PLL | |
435 | * @crtc: current CRTC | |
436 | * @target: target frequency in kHz | |
437 | * @refclk: reference clock frequency in kHz | |
438 | * @match_clock: if provided, @best_clock P divider must | |
439 | * match the P divider from @match_clock | |
440 | * used for LVDS downclocking | |
441 | * @best_clock: best PLL values found | |
442 | * | |
443 | * Returns true on success, false on failure. | |
444 | */ | |
445 | bool (*find_dpll)(const struct intel_limit *limit, | |
446 | struct drm_crtc *crtc, | |
447 | int target, int refclk, | |
448 | struct dpll *match_clock, | |
449 | struct dpll *best_clock); | |
46ba614c | 450 | void (*update_wm)(struct drm_crtc *crtc); |
adf3d35e VS |
451 | void (*update_sprite_wm)(struct drm_plane *plane, |
452 | struct drm_crtc *crtc, | |
ed57cb8a DL |
453 | uint32_t sprite_width, uint32_t sprite_height, |
454 | int pixel_size, bool enable, bool scaled); | |
47fab737 | 455 | void (*modeset_global_resources)(struct drm_device *dev); |
0e8ffe1b DV |
456 | /* Returns the active state of the crtc, and if the crtc is active, |
457 | * fills out the pipe-config with the hw state. */ | |
458 | bool (*get_pipe_config)(struct intel_crtc *, | |
459 | struct intel_crtc_config *); | |
46f297fb JB |
460 | void (*get_plane_config)(struct intel_crtc *, |
461 | struct intel_plane_config *); | |
f564048e | 462 | int (*crtc_mode_set)(struct drm_crtc *crtc, |
f564048e EA |
463 | int x, int y, |
464 | struct drm_framebuffer *old_fb); | |
76e5a89c DV |
465 | void (*crtc_enable)(struct drm_crtc *crtc); |
466 | void (*crtc_disable)(struct drm_crtc *crtc); | |
ee7b9f93 | 467 | void (*off)(struct drm_crtc *crtc); |
e0dac65e | 468 | void (*write_eld)(struct drm_connector *connector, |
34427052 JN |
469 | struct drm_crtc *crtc, |
470 | struct drm_display_mode *mode); | |
674cf967 | 471 | void (*fdi_link_train)(struct drm_crtc *crtc); |
6067aaea | 472 | void (*init_clock_gating)(struct drm_device *dev); |
8c9f3aaf JB |
473 | int (*queue_flip)(struct drm_device *dev, struct drm_crtc *crtc, |
474 | struct drm_framebuffer *fb, | |
ed8d1975 | 475 | struct drm_i915_gem_object *obj, |
a4872ba6 | 476 | struct intel_engine_cs *ring, |
ed8d1975 | 477 | uint32_t flags); |
29b9bde6 DV |
478 | void (*update_primary_plane)(struct drm_crtc *crtc, |
479 | struct drm_framebuffer *fb, | |
480 | int x, int y); | |
20afbda2 | 481 | void (*hpd_irq_setup)(struct drm_device *dev); |
e70236a8 JB |
482 | /* clock updates for mode set */ |
483 | /* cursor updates */ | |
484 | /* render clock increase/decrease */ | |
485 | /* display clock increase/decrease */ | |
486 | /* pll clock increase/decrease */ | |
7bd688cd JN |
487 | |
488 | int (*setup_backlight)(struct intel_connector *connector); | |
7bd688cd JN |
489 | uint32_t (*get_backlight)(struct intel_connector *connector); |
490 | void (*set_backlight)(struct intel_connector *connector, | |
491 | uint32_t level); | |
492 | void (*disable_backlight)(struct intel_connector *connector); | |
493 | void (*enable_backlight)(struct intel_connector *connector); | |
e70236a8 JB |
494 | }; |
495 | ||
907b28c5 | 496 | struct intel_uncore_funcs { |
c8d9a590 D |
497 | void (*force_wake_get)(struct drm_i915_private *dev_priv, |
498 | int fw_engine); | |
499 | void (*force_wake_put)(struct drm_i915_private *dev_priv, | |
500 | int fw_engine); | |
0b274481 BW |
501 | |
502 | uint8_t (*mmio_readb)(struct drm_i915_private *dev_priv, off_t offset, bool trace); | |
503 | uint16_t (*mmio_readw)(struct drm_i915_private *dev_priv, off_t offset, bool trace); | |
504 | uint32_t (*mmio_readl)(struct drm_i915_private *dev_priv, off_t offset, bool trace); | |
505 | uint64_t (*mmio_readq)(struct drm_i915_private *dev_priv, off_t offset, bool trace); | |
506 | ||
507 | void (*mmio_writeb)(struct drm_i915_private *dev_priv, off_t offset, | |
508 | uint8_t val, bool trace); | |
509 | void (*mmio_writew)(struct drm_i915_private *dev_priv, off_t offset, | |
510 | uint16_t val, bool trace); | |
511 | void (*mmio_writel)(struct drm_i915_private *dev_priv, off_t offset, | |
512 | uint32_t val, bool trace); | |
513 | void (*mmio_writeq)(struct drm_i915_private *dev_priv, off_t offset, | |
514 | uint64_t val, bool trace); | |
990bbdad CW |
515 | }; |
516 | ||
907b28c5 CW |
517 | struct intel_uncore { |
518 | spinlock_t lock; /** lock is also taken in irq contexts. */ | |
519 | ||
520 | struct intel_uncore_funcs funcs; | |
521 | ||
522 | unsigned fifo_count; | |
523 | unsigned forcewake_count; | |
aec347ab | 524 | |
940aece4 D |
525 | unsigned fw_rendercount; |
526 | unsigned fw_mediacount; | |
527 | ||
8232644c | 528 | struct timer_list force_wake_timer; |
907b28c5 CW |
529 | }; |
530 | ||
79fc46df DL |
531 | #define DEV_INFO_FOR_EACH_FLAG(func, sep) \ |
532 | func(is_mobile) sep \ | |
533 | func(is_i85x) sep \ | |
534 | func(is_i915g) sep \ | |
535 | func(is_i945gm) sep \ | |
536 | func(is_g33) sep \ | |
537 | func(need_gfx_hws) sep \ | |
538 | func(is_g4x) sep \ | |
539 | func(is_pineview) sep \ | |
540 | func(is_broadwater) sep \ | |
541 | func(is_crestline) sep \ | |
542 | func(is_ivybridge) sep \ | |
543 | func(is_valleyview) sep \ | |
544 | func(is_haswell) sep \ | |
b833d685 | 545 | func(is_preliminary) sep \ |
79fc46df DL |
546 | func(has_fbc) sep \ |
547 | func(has_pipe_cxsr) sep \ | |
548 | func(has_hotplug) sep \ | |
549 | func(cursor_needs_physical) sep \ | |
550 | func(has_overlay) sep \ | |
551 | func(overlay_needs_physical) sep \ | |
552 | func(supports_tv) sep \ | |
dd93be58 | 553 | func(has_llc) sep \ |
30568c45 DL |
554 | func(has_ddi) sep \ |
555 | func(has_fpga_dbg) | |
c96ea64e | 556 | |
a587f779 DL |
557 | #define DEFINE_FLAG(name) u8 name:1 |
558 | #define SEP_SEMICOLON ; | |
c96ea64e | 559 | |
cfdf1fa2 | 560 | struct intel_device_info { |
10fce67a | 561 | u32 display_mmio_offset; |
87f1f465 | 562 | u16 device_id; |
7eb552ae | 563 | u8 num_pipes:3; |
d615a166 | 564 | u8 num_sprites[I915_MAX_PIPES]; |
c96c3a8c | 565 | u8 gen; |
73ae478c | 566 | u8 ring_mask; /* Rings supported by the HW */ |
a587f779 | 567 | DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG, SEP_SEMICOLON); |
a57c774a AK |
568 | /* Register offsets for the various display pipes and transcoders */ |
569 | int pipe_offsets[I915_MAX_TRANSCODERS]; | |
570 | int trans_offsets[I915_MAX_TRANSCODERS]; | |
a57c774a | 571 | int palette_offsets[I915_MAX_PIPES]; |
5efb3e28 | 572 | int cursor_offsets[I915_MAX_PIPES]; |
cfdf1fa2 KH |
573 | }; |
574 | ||
a587f779 DL |
575 | #undef DEFINE_FLAG |
576 | #undef SEP_SEMICOLON | |
577 | ||
7faf1ab2 DV |
578 | enum i915_cache_level { |
579 | I915_CACHE_NONE = 0, | |
350ec881 CW |
580 | I915_CACHE_LLC, /* also used for snoopable memory on non-LLC */ |
581 | I915_CACHE_L3_LLC, /* gen7+, L3 sits between the domain specifc | |
582 | caches, eg sampler/render caches, and the | |
583 | large Last-Level-Cache. LLC is coherent with | |
584 | the CPU, but L3 is only visible to the GPU. */ | |
651d794f | 585 | I915_CACHE_WT, /* hsw:gt3e WriteThrough for scanouts */ |
7faf1ab2 DV |
586 | }; |
587 | ||
e59ec13d MK |
588 | struct i915_ctx_hang_stats { |
589 | /* This context had batch pending when hang was declared */ | |
590 | unsigned batch_pending; | |
591 | ||
592 | /* This context had batch active when hang was declared */ | |
593 | unsigned batch_active; | |
be62acb4 MK |
594 | |
595 | /* Time when this context was last blamed for a GPU reset */ | |
596 | unsigned long guilty_ts; | |
597 | ||
598 | /* This context is banned to submit more work */ | |
599 | bool banned; | |
e59ec13d | 600 | }; |
40521054 BW |
601 | |
602 | /* This must match up with the value previously used for execbuf2.rsvd1. */ | |
821d66dd | 603 | #define DEFAULT_CONTEXT_HANDLE 0 |
31b7a88d OM |
604 | /** |
605 | * struct intel_context - as the name implies, represents a context. | |
606 | * @ref: reference count. | |
607 | * @user_handle: userspace tracking identity for this context. | |
608 | * @remap_slice: l3 row remapping information. | |
609 | * @file_priv: filp associated with this context (NULL for global default | |
610 | * context). | |
611 | * @hang_stats: information about the role of this context in possible GPU | |
612 | * hangs. | |
613 | * @vm: virtual memory space used by this context. | |
614 | * @legacy_hw_ctx: render context backing object and whether it is correctly | |
615 | * initialized (legacy ring submission mechanism only). | |
616 | * @link: link in the global list of contexts. | |
617 | * | |
618 | * Contexts are memory images used by the hardware to store copies of their | |
619 | * internal state. | |
620 | */ | |
273497e5 | 621 | struct intel_context { |
dce3271b | 622 | struct kref ref; |
821d66dd | 623 | int user_handle; |
3ccfd19d | 624 | uint8_t remap_slice; |
40521054 | 625 | struct drm_i915_file_private *file_priv; |
e59ec13d | 626 | struct i915_ctx_hang_stats hang_stats; |
ae6c4806 | 627 | struct i915_hw_ppgtt *ppgtt; |
a33afea5 | 628 | |
c9e003af | 629 | /* Legacy ring buffer submission */ |
ea0c76f8 OM |
630 | struct { |
631 | struct drm_i915_gem_object *rcs_state; | |
632 | bool initialized; | |
633 | } legacy_hw_ctx; | |
634 | ||
c9e003af OM |
635 | /* Execlists */ |
636 | struct { | |
637 | struct drm_i915_gem_object *state; | |
84c2377f | 638 | struct intel_ringbuffer *ringbuf; |
c9e003af OM |
639 | } engine[I915_NUM_RINGS]; |
640 | ||
a33afea5 | 641 | struct list_head link; |
40521054 BW |
642 | }; |
643 | ||
5c3fe8b0 BW |
644 | struct i915_fbc { |
645 | unsigned long size; | |
5e59f717 | 646 | unsigned threshold; |
5c3fe8b0 BW |
647 | unsigned int fb_id; |
648 | enum plane plane; | |
649 | int y; | |
650 | ||
c4213885 | 651 | struct drm_mm_node compressed_fb; |
5c3fe8b0 BW |
652 | struct drm_mm_node *compressed_llb; |
653 | ||
da46f936 RV |
654 | bool false_color; |
655 | ||
5c3fe8b0 BW |
656 | struct intel_fbc_work { |
657 | struct delayed_work work; | |
658 | struct drm_crtc *crtc; | |
659 | struct drm_framebuffer *fb; | |
5c3fe8b0 BW |
660 | } *fbc_work; |
661 | ||
29ebf90f CW |
662 | enum no_fbc_reason { |
663 | FBC_OK, /* FBC is enabled */ | |
664 | FBC_UNSUPPORTED, /* FBC is not supported by this chipset */ | |
5c3fe8b0 BW |
665 | FBC_NO_OUTPUT, /* no outputs enabled to compress */ |
666 | FBC_STOLEN_TOO_SMALL, /* not enough space for buffers */ | |
667 | FBC_UNSUPPORTED_MODE, /* interlace or doublescanned mode */ | |
668 | FBC_MODE_TOO_LARGE, /* mode too large for compression */ | |
669 | FBC_BAD_PLANE, /* fbc not supported on plane */ | |
670 | FBC_NOT_TILED, /* buffer not tiled */ | |
671 | FBC_MULTIPLE_PIPES, /* more than one pipe active */ | |
672 | FBC_MODULE_PARAM, | |
673 | FBC_CHIP_DEFAULT, /* disabled by default on this chip */ | |
674 | } no_fbc_reason; | |
b5e50c3f JB |
675 | }; |
676 | ||
439d7ac0 PB |
677 | struct i915_drrs { |
678 | struct intel_connector *connector; | |
679 | }; | |
680 | ||
2807cf69 | 681 | struct intel_dp; |
a031d709 | 682 | struct i915_psr { |
f0355c4a | 683 | struct mutex lock; |
a031d709 RV |
684 | bool sink_support; |
685 | bool source_ok; | |
2807cf69 | 686 | struct intel_dp *enabled; |
7c8f8a70 RV |
687 | bool active; |
688 | struct delayed_work work; | |
9ca15301 | 689 | unsigned busy_frontbuffer_bits; |
3f51e471 | 690 | }; |
5c3fe8b0 | 691 | |
3bad0781 | 692 | enum intel_pch { |
f0350830 | 693 | PCH_NONE = 0, /* No PCH present */ |
3bad0781 ZW |
694 | PCH_IBX, /* Ibexpeak PCH */ |
695 | PCH_CPT, /* Cougarpoint PCH */ | |
eb877ebf | 696 | PCH_LPT, /* Lynxpoint PCH */ |
40c7ead9 | 697 | PCH_NOP, |
3bad0781 ZW |
698 | }; |
699 | ||
988d6ee8 PZ |
700 | enum intel_sbi_destination { |
701 | SBI_ICLK, | |
702 | SBI_MPHY, | |
703 | }; | |
704 | ||
b690e96c | 705 | #define QUIRK_PIPEA_FORCE (1<<0) |
435793df | 706 | #define QUIRK_LVDS_SSC_DISABLE (1<<1) |
4dca20ef | 707 | #define QUIRK_INVERT_BRIGHTNESS (1<<2) |
9c72cc6f | 708 | #define QUIRK_BACKLIGHT_PRESENT (1<<3) |
b690e96c | 709 | |
8be48d92 | 710 | struct intel_fbdev; |
1630fe75 | 711 | struct intel_fbc_work; |
38651674 | 712 | |
c2b9152f DV |
713 | struct intel_gmbus { |
714 | struct i2c_adapter adapter; | |
f2ce9faf | 715 | u32 force_bit; |
c2b9152f | 716 | u32 reg0; |
36c785f0 | 717 | u32 gpio_reg; |
c167a6fc | 718 | struct i2c_algo_bit_data bit_algo; |
c2b9152f DV |
719 | struct drm_i915_private *dev_priv; |
720 | }; | |
721 | ||
f4c956ad | 722 | struct i915_suspend_saved_registers { |
ba8bbcf6 JB |
723 | u8 saveLBB; |
724 | u32 saveDSPACNTR; | |
725 | u32 saveDSPBCNTR; | |
e948e994 | 726 | u32 saveDSPARB; |
ba8bbcf6 JB |
727 | u32 savePIPEACONF; |
728 | u32 savePIPEBCONF; | |
729 | u32 savePIPEASRC; | |
730 | u32 savePIPEBSRC; | |
731 | u32 saveFPA0; | |
732 | u32 saveFPA1; | |
733 | u32 saveDPLL_A; | |
734 | u32 saveDPLL_A_MD; | |
735 | u32 saveHTOTAL_A; | |
736 | u32 saveHBLANK_A; | |
737 | u32 saveHSYNC_A; | |
738 | u32 saveVTOTAL_A; | |
739 | u32 saveVBLANK_A; | |
740 | u32 saveVSYNC_A; | |
741 | u32 saveBCLRPAT_A; | |
5586c8bc | 742 | u32 saveTRANSACONF; |
42048781 ZW |
743 | u32 saveTRANS_HTOTAL_A; |
744 | u32 saveTRANS_HBLANK_A; | |
745 | u32 saveTRANS_HSYNC_A; | |
746 | u32 saveTRANS_VTOTAL_A; | |
747 | u32 saveTRANS_VBLANK_A; | |
748 | u32 saveTRANS_VSYNC_A; | |
0da3ea12 | 749 | u32 savePIPEASTAT; |
ba8bbcf6 JB |
750 | u32 saveDSPASTRIDE; |
751 | u32 saveDSPASIZE; | |
752 | u32 saveDSPAPOS; | |
585fb111 | 753 | u32 saveDSPAADDR; |
ba8bbcf6 JB |
754 | u32 saveDSPASURF; |
755 | u32 saveDSPATILEOFF; | |
756 | u32 savePFIT_PGM_RATIOS; | |
0eb96d6e | 757 | u32 saveBLC_HIST_CTL; |
ba8bbcf6 JB |
758 | u32 saveBLC_PWM_CTL; |
759 | u32 saveBLC_PWM_CTL2; | |
07bf139b | 760 | u32 saveBLC_HIST_CTL_B; |
42048781 ZW |
761 | u32 saveBLC_CPU_PWM_CTL; |
762 | u32 saveBLC_CPU_PWM_CTL2; | |
ba8bbcf6 JB |
763 | u32 saveFPB0; |
764 | u32 saveFPB1; | |
765 | u32 saveDPLL_B; | |
766 | u32 saveDPLL_B_MD; | |
767 | u32 saveHTOTAL_B; | |
768 | u32 saveHBLANK_B; | |
769 | u32 saveHSYNC_B; | |
770 | u32 saveVTOTAL_B; | |
771 | u32 saveVBLANK_B; | |
772 | u32 saveVSYNC_B; | |
773 | u32 saveBCLRPAT_B; | |
5586c8bc | 774 | u32 saveTRANSBCONF; |
42048781 ZW |
775 | u32 saveTRANS_HTOTAL_B; |
776 | u32 saveTRANS_HBLANK_B; | |
777 | u32 saveTRANS_HSYNC_B; | |
778 | u32 saveTRANS_VTOTAL_B; | |
779 | u32 saveTRANS_VBLANK_B; | |
780 | u32 saveTRANS_VSYNC_B; | |
0da3ea12 | 781 | u32 savePIPEBSTAT; |
ba8bbcf6 JB |
782 | u32 saveDSPBSTRIDE; |
783 | u32 saveDSPBSIZE; | |
784 | u32 saveDSPBPOS; | |
585fb111 | 785 | u32 saveDSPBADDR; |
ba8bbcf6 JB |
786 | u32 saveDSPBSURF; |
787 | u32 saveDSPBTILEOFF; | |
585fb111 JB |
788 | u32 saveVGA0; |
789 | u32 saveVGA1; | |
790 | u32 saveVGA_PD; | |
ba8bbcf6 JB |
791 | u32 saveVGACNTRL; |
792 | u32 saveADPA; | |
793 | u32 saveLVDS; | |
585fb111 JB |
794 | u32 savePP_ON_DELAYS; |
795 | u32 savePP_OFF_DELAYS; | |
ba8bbcf6 JB |
796 | u32 saveDVOA; |
797 | u32 saveDVOB; | |
798 | u32 saveDVOC; | |
799 | u32 savePP_ON; | |
800 | u32 savePP_OFF; | |
801 | u32 savePP_CONTROL; | |
585fb111 | 802 | u32 savePP_DIVISOR; |
ba8bbcf6 JB |
803 | u32 savePFIT_CONTROL; |
804 | u32 save_palette_a[256]; | |
805 | u32 save_palette_b[256]; | |
ba8bbcf6 | 806 | u32 saveFBC_CONTROL; |
0da3ea12 JB |
807 | u32 saveIER; |
808 | u32 saveIIR; | |
809 | u32 saveIMR; | |
42048781 ZW |
810 | u32 saveDEIER; |
811 | u32 saveDEIMR; | |
812 | u32 saveGTIER; | |
813 | u32 saveGTIMR; | |
814 | u32 saveFDI_RXA_IMR; | |
815 | u32 saveFDI_RXB_IMR; | |
1f84e550 | 816 | u32 saveCACHE_MODE_0; |
1f84e550 | 817 | u32 saveMI_ARB_STATE; |
ba8bbcf6 JB |
818 | u32 saveSWF0[16]; |
819 | u32 saveSWF1[16]; | |
820 | u32 saveSWF2[3]; | |
821 | u8 saveMSR; | |
822 | u8 saveSR[8]; | |
123f794f | 823 | u8 saveGR[25]; |
ba8bbcf6 | 824 | u8 saveAR_INDEX; |
a59e122a | 825 | u8 saveAR[21]; |
ba8bbcf6 | 826 | u8 saveDACMASK; |
a59e122a | 827 | u8 saveCR[37]; |
4b9de737 | 828 | uint64_t saveFENCE[I915_MAX_NUM_FENCES]; |
1fd1c624 EA |
829 | u32 saveCURACNTR; |
830 | u32 saveCURAPOS; | |
831 | u32 saveCURABASE; | |
832 | u32 saveCURBCNTR; | |
833 | u32 saveCURBPOS; | |
834 | u32 saveCURBBASE; | |
835 | u32 saveCURSIZE; | |
a4fc5ed6 KP |
836 | u32 saveDP_B; |
837 | u32 saveDP_C; | |
838 | u32 saveDP_D; | |
839 | u32 savePIPEA_GMCH_DATA_M; | |
840 | u32 savePIPEB_GMCH_DATA_M; | |
841 | u32 savePIPEA_GMCH_DATA_N; | |
842 | u32 savePIPEB_GMCH_DATA_N; | |
843 | u32 savePIPEA_DP_LINK_M; | |
844 | u32 savePIPEB_DP_LINK_M; | |
845 | u32 savePIPEA_DP_LINK_N; | |
846 | u32 savePIPEB_DP_LINK_N; | |
42048781 ZW |
847 | u32 saveFDI_RXA_CTL; |
848 | u32 saveFDI_TXA_CTL; | |
849 | u32 saveFDI_RXB_CTL; | |
850 | u32 saveFDI_TXB_CTL; | |
851 | u32 savePFA_CTL_1; | |
852 | u32 savePFB_CTL_1; | |
853 | u32 savePFA_WIN_SZ; | |
854 | u32 savePFB_WIN_SZ; | |
855 | u32 savePFA_WIN_POS; | |
856 | u32 savePFB_WIN_POS; | |
5586c8bc ZW |
857 | u32 savePCH_DREF_CONTROL; |
858 | u32 saveDISP_ARB_CTL; | |
859 | u32 savePIPEA_DATA_M1; | |
860 | u32 savePIPEA_DATA_N1; | |
861 | u32 savePIPEA_LINK_M1; | |
862 | u32 savePIPEA_LINK_N1; | |
863 | u32 savePIPEB_DATA_M1; | |
864 | u32 savePIPEB_DATA_N1; | |
865 | u32 savePIPEB_LINK_M1; | |
866 | u32 savePIPEB_LINK_N1; | |
b5b72e89 | 867 | u32 saveMCHBAR_RENDER_STANDBY; |
cda2bb78 | 868 | u32 savePCH_PORT_HOTPLUG; |
f4c956ad | 869 | }; |
c85aa885 | 870 | |
ddeea5b0 ID |
871 | struct vlv_s0ix_state { |
872 | /* GAM */ | |
873 | u32 wr_watermark; | |
874 | u32 gfx_prio_ctrl; | |
875 | u32 arb_mode; | |
876 | u32 gfx_pend_tlb0; | |
877 | u32 gfx_pend_tlb1; | |
878 | u32 lra_limits[GEN7_LRA_LIMITS_REG_NUM]; | |
879 | u32 media_max_req_count; | |
880 | u32 gfx_max_req_count; | |
881 | u32 render_hwsp; | |
882 | u32 ecochk; | |
883 | u32 bsd_hwsp; | |
884 | u32 blt_hwsp; | |
885 | u32 tlb_rd_addr; | |
886 | ||
887 | /* MBC */ | |
888 | u32 g3dctl; | |
889 | u32 gsckgctl; | |
890 | u32 mbctl; | |
891 | ||
892 | /* GCP */ | |
893 | u32 ucgctl1; | |
894 | u32 ucgctl3; | |
895 | u32 rcgctl1; | |
896 | u32 rcgctl2; | |
897 | u32 rstctl; | |
898 | u32 misccpctl; | |
899 | ||
900 | /* GPM */ | |
901 | u32 gfxpause; | |
902 | u32 rpdeuhwtc; | |
903 | u32 rpdeuc; | |
904 | u32 ecobus; | |
905 | u32 pwrdwnupctl; | |
906 | u32 rp_down_timeout; | |
907 | u32 rp_deucsw; | |
908 | u32 rcubmabdtmr; | |
909 | u32 rcedata; | |
910 | u32 spare2gh; | |
911 | ||
912 | /* Display 1 CZ domain */ | |
913 | u32 gt_imr; | |
914 | u32 gt_ier; | |
915 | u32 pm_imr; | |
916 | u32 pm_ier; | |
917 | u32 gt_scratch[GEN7_GT_SCRATCH_REG_NUM]; | |
918 | ||
919 | /* GT SA CZ domain */ | |
920 | u32 tilectl; | |
921 | u32 gt_fifoctl; | |
922 | u32 gtlc_wake_ctrl; | |
923 | u32 gtlc_survive; | |
924 | u32 pmwgicz; | |
925 | ||
926 | /* Display 2 CZ domain */ | |
927 | u32 gu_ctl0; | |
928 | u32 gu_ctl1; | |
929 | u32 clock_gate_dis2; | |
930 | }; | |
931 | ||
bf225f20 CW |
932 | struct intel_rps_ei { |
933 | u32 cz_clock; | |
934 | u32 render_c0; | |
935 | u32 media_c0; | |
31685c25 D |
936 | }; |
937 | ||
c85aa885 | 938 | struct intel_gen6_power_mgmt { |
59cdb63d | 939 | /* work and pm_iir are protected by dev_priv->irq_lock */ |
c85aa885 DV |
940 | struct work_struct work; |
941 | u32 pm_iir; | |
59cdb63d | 942 | |
b39fb297 BW |
943 | /* Frequencies are stored in potentially platform dependent multiples. |
944 | * In other words, *_freq needs to be multiplied by X to be interesting. | |
945 | * Soft limits are those which are used for the dynamic reclocking done | |
946 | * by the driver (raise frequencies under heavy loads, and lower for | |
947 | * lighter loads). Hard limits are those imposed by the hardware. | |
948 | * | |
949 | * A distinction is made for overclocking, which is never enabled by | |
950 | * default, and is considered to be above the hard limit if it's | |
951 | * possible at all. | |
952 | */ | |
953 | u8 cur_freq; /* Current frequency (cached, may not == HW) */ | |
954 | u8 min_freq_softlimit; /* Minimum frequency permitted by the driver */ | |
955 | u8 max_freq_softlimit; /* Max frequency permitted by the driver */ | |
956 | u8 max_freq; /* Maximum frequency, RP0 if not overclocking */ | |
957 | u8 min_freq; /* AKA RPn. Minimum frequency */ | |
958 | u8 efficient_freq; /* AKA RPe. Pre-determined balanced frequency */ | |
959 | u8 rp1_freq; /* "less than" RP0 power/freqency */ | |
960 | u8 rp0_freq; /* Non-overclocked max frequency. */ | |
67c3bf6f | 961 | u32 cz_freq; |
1a01ab3b | 962 | |
31685c25 D |
963 | u32 ei_interrupt_count; |
964 | ||
dd75fdc8 CW |
965 | int last_adj; |
966 | enum { LOW_POWER, BETWEEN, HIGH_POWER } power; | |
967 | ||
c0951f0c | 968 | bool enabled; |
1a01ab3b | 969 | struct delayed_work delayed_resume_work; |
4fc688ce | 970 | |
bf225f20 CW |
971 | /* manual wa residency calculations */ |
972 | struct intel_rps_ei up_ei, down_ei; | |
973 | ||
4fc688ce JB |
974 | /* |
975 | * Protects RPS/RC6 register access and PCU communication. | |
976 | * Must be taken after struct_mutex if nested. | |
977 | */ | |
978 | struct mutex hw_lock; | |
c85aa885 DV |
979 | }; |
980 | ||
1a240d4d DV |
981 | /* defined intel_pm.c */ |
982 | extern spinlock_t mchdev_lock; | |
983 | ||
c85aa885 DV |
984 | struct intel_ilk_power_mgmt { |
985 | u8 cur_delay; | |
986 | u8 min_delay; | |
987 | u8 max_delay; | |
988 | u8 fmax; | |
989 | u8 fstart; | |
990 | ||
991 | u64 last_count1; | |
992 | unsigned long last_time1; | |
993 | unsigned long chipset_power; | |
994 | u64 last_count2; | |
995 | struct timespec last_time2; | |
996 | unsigned long gfx_power; | |
997 | u8 corr; | |
998 | ||
999 | int c_m; | |
1000 | int r_t; | |
3e373948 DV |
1001 | |
1002 | struct drm_i915_gem_object *pwrctx; | |
1003 | struct drm_i915_gem_object *renderctx; | |
c85aa885 DV |
1004 | }; |
1005 | ||
c6cb582e ID |
1006 | struct drm_i915_private; |
1007 | struct i915_power_well; | |
1008 | ||
1009 | struct i915_power_well_ops { | |
1010 | /* | |
1011 | * Synchronize the well's hw state to match the current sw state, for | |
1012 | * example enable/disable it based on the current refcount. Called | |
1013 | * during driver init and resume time, possibly after first calling | |
1014 | * the enable/disable handlers. | |
1015 | */ | |
1016 | void (*sync_hw)(struct drm_i915_private *dev_priv, | |
1017 | struct i915_power_well *power_well); | |
1018 | /* | |
1019 | * Enable the well and resources that depend on it (for example | |
1020 | * interrupts located on the well). Called after the 0->1 refcount | |
1021 | * transition. | |
1022 | */ | |
1023 | void (*enable)(struct drm_i915_private *dev_priv, | |
1024 | struct i915_power_well *power_well); | |
1025 | /* | |
1026 | * Disable the well and resources that depend on it. Called after | |
1027 | * the 1->0 refcount transition. | |
1028 | */ | |
1029 | void (*disable)(struct drm_i915_private *dev_priv, | |
1030 | struct i915_power_well *power_well); | |
1031 | /* Returns the hw enabled state. */ | |
1032 | bool (*is_enabled)(struct drm_i915_private *dev_priv, | |
1033 | struct i915_power_well *power_well); | |
1034 | }; | |
1035 | ||
a38911a3 WX |
1036 | /* Power well structure for haswell */ |
1037 | struct i915_power_well { | |
c1ca727f | 1038 | const char *name; |
6f3ef5dd | 1039 | bool always_on; |
a38911a3 WX |
1040 | /* power well enable/disable usage count */ |
1041 | int count; | |
bfafe93a ID |
1042 | /* cached hw enabled state */ |
1043 | bool hw_enabled; | |
c1ca727f | 1044 | unsigned long domains; |
77961eb9 | 1045 | unsigned long data; |
c6cb582e | 1046 | const struct i915_power_well_ops *ops; |
a38911a3 WX |
1047 | }; |
1048 | ||
83c00f55 | 1049 | struct i915_power_domains { |
baa70707 ID |
1050 | /* |
1051 | * Power wells needed for initialization at driver init and suspend | |
1052 | * time are on. They are kept on until after the first modeset. | |
1053 | */ | |
1054 | bool init_power_on; | |
0d116a29 | 1055 | bool initializing; |
c1ca727f | 1056 | int power_well_count; |
baa70707 | 1057 | |
83c00f55 | 1058 | struct mutex lock; |
1da51581 | 1059 | int domain_use_count[POWER_DOMAIN_NUM]; |
c1ca727f | 1060 | struct i915_power_well *power_wells; |
83c00f55 ID |
1061 | }; |
1062 | ||
231f42a4 DV |
1063 | struct i915_dri1_state { |
1064 | unsigned allow_batchbuffer : 1; | |
1065 | u32 __iomem *gfx_hws_cpu_addr; | |
1066 | ||
1067 | unsigned int cpp; | |
1068 | int back_offset; | |
1069 | int front_offset; | |
1070 | int current_page; | |
1071 | int page_flipping; | |
1072 | ||
1073 | uint32_t counter; | |
1074 | }; | |
1075 | ||
db1b76ca DV |
1076 | struct i915_ums_state { |
1077 | /** | |
1078 | * Flag if the X Server, and thus DRM, is not currently in | |
1079 | * control of the device. | |
1080 | * | |
1081 | * This is set between LeaveVT and EnterVT. It needs to be | |
1082 | * replaced with a semaphore. It also needs to be | |
1083 | * transitioned away from for kernel modesetting. | |
1084 | */ | |
1085 | int mm_suspended; | |
1086 | }; | |
1087 | ||
35a85ac6 | 1088 | #define MAX_L3_SLICES 2 |
a4da4fa4 | 1089 | struct intel_l3_parity { |
35a85ac6 | 1090 | u32 *remap_info[MAX_L3_SLICES]; |
a4da4fa4 | 1091 | struct work_struct error_work; |
35a85ac6 | 1092 | int which_slice; |
a4da4fa4 DV |
1093 | }; |
1094 | ||
4b5aed62 | 1095 | struct i915_gem_mm { |
4b5aed62 DV |
1096 | /** Memory allocator for GTT stolen memory */ |
1097 | struct drm_mm stolen; | |
4b5aed62 DV |
1098 | /** List of all objects in gtt_space. Used to restore gtt |
1099 | * mappings on resume */ | |
1100 | struct list_head bound_list; | |
1101 | /** | |
1102 | * List of objects which are not bound to the GTT (thus | |
1103 | * are idle and not used by the GPU) but still have | |
1104 | * (presumably uncached) pages still attached. | |
1105 | */ | |
1106 | struct list_head unbound_list; | |
1107 | ||
1108 | /** Usable portion of the GTT for GEM */ | |
1109 | unsigned long stolen_base; /* limited to low memory (32-bit) */ | |
1110 | ||
4b5aed62 DV |
1111 | /** PPGTT used for aliasing the PPGTT with the GTT */ |
1112 | struct i915_hw_ppgtt *aliasing_ppgtt; | |
1113 | ||
2cfcd32a | 1114 | struct notifier_block oom_notifier; |
ceabbba5 | 1115 | struct shrinker shrinker; |
4b5aed62 DV |
1116 | bool shrinker_no_lock_stealing; |
1117 | ||
4b5aed62 DV |
1118 | /** LRU list of objects with fence regs on them. */ |
1119 | struct list_head fence_list; | |
1120 | ||
1121 | /** | |
1122 | * We leave the user IRQ off as much as possible, | |
1123 | * but this means that requests will finish and never | |
1124 | * be retired once the system goes idle. Set a timer to | |
1125 | * fire periodically while the ring is running. When it | |
1126 | * fires, go retire requests. | |
1127 | */ | |
1128 | struct delayed_work retire_work; | |
1129 | ||
b29c19b6 CW |
1130 | /** |
1131 | * When we detect an idle GPU, we want to turn on | |
1132 | * powersaving features. So once we see that there | |
1133 | * are no more requests outstanding and no more | |
1134 | * arrive within a small period of time, we fire | |
1135 | * off the idle_work. | |
1136 | */ | |
1137 | struct delayed_work idle_work; | |
1138 | ||
4b5aed62 DV |
1139 | /** |
1140 | * Are we in a non-interruptible section of code like | |
1141 | * modesetting? | |
1142 | */ | |
1143 | bool interruptible; | |
1144 | ||
f62a0076 CW |
1145 | /** |
1146 | * Is the GPU currently considered idle, or busy executing userspace | |
1147 | * requests? Whilst idle, we attempt to power down the hardware and | |
1148 | * display clocks. In order to reduce the effect on performance, there | |
1149 | * is a slight delay before we do so. | |
1150 | */ | |
1151 | bool busy; | |
1152 | ||
bdf1e7e3 DV |
1153 | /* the indicator for dispatch video commands on two BSD rings */ |
1154 | int bsd_ring_dispatch_index; | |
1155 | ||
4b5aed62 DV |
1156 | /** Bit 6 swizzling required for X tiling */ |
1157 | uint32_t bit_6_swizzle_x; | |
1158 | /** Bit 6 swizzling required for Y tiling */ | |
1159 | uint32_t bit_6_swizzle_y; | |
1160 | ||
4b5aed62 | 1161 | /* accounting, useful for userland debugging */ |
c20e8355 | 1162 | spinlock_t object_stat_lock; |
4b5aed62 DV |
1163 | size_t object_memory; |
1164 | u32 object_count; | |
1165 | }; | |
1166 | ||
edc3d884 MK |
1167 | struct drm_i915_error_state_buf { |
1168 | unsigned bytes; | |
1169 | unsigned size; | |
1170 | int err; | |
1171 | u8 *buf; | |
1172 | loff_t start; | |
1173 | loff_t pos; | |
1174 | }; | |
1175 | ||
fc16b48b MK |
1176 | struct i915_error_state_file_priv { |
1177 | struct drm_device *dev; | |
1178 | struct drm_i915_error_state *error; | |
1179 | }; | |
1180 | ||
99584db3 DV |
1181 | struct i915_gpu_error { |
1182 | /* For hangcheck timer */ | |
1183 | #define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */ | |
1184 | #define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD) | |
be62acb4 MK |
1185 | /* Hang gpu twice in this window and your context gets banned */ |
1186 | #define DRM_I915_CTX_BAN_PERIOD DIV_ROUND_UP(8*DRM_I915_HANGCHECK_PERIOD, 1000) | |
1187 | ||
99584db3 | 1188 | struct timer_list hangcheck_timer; |
99584db3 DV |
1189 | |
1190 | /* For reset and error_state handling. */ | |
1191 | spinlock_t lock; | |
1192 | /* Protected by the above dev->gpu_error.lock. */ | |
1193 | struct drm_i915_error_state *first_error; | |
1194 | struct work_struct work; | |
99584db3 | 1195 | |
094f9a54 CW |
1196 | |
1197 | unsigned long missed_irq_rings; | |
1198 | ||
1f83fee0 | 1199 | /** |
2ac0f450 | 1200 | * State variable controlling the reset flow and count |
1f83fee0 | 1201 | * |
2ac0f450 MK |
1202 | * This is a counter which gets incremented when reset is triggered, |
1203 | * and again when reset has been handled. So odd values (lowest bit set) | |
1204 | * means that reset is in progress and even values that | |
1205 | * (reset_counter >> 1):th reset was successfully completed. | |
1206 | * | |
1207 | * If reset is not completed succesfully, the I915_WEDGE bit is | |
1208 | * set meaning that hardware is terminally sour and there is no | |
1209 | * recovery. All waiters on the reset_queue will be woken when | |
1210 | * that happens. | |
1211 | * | |
1212 | * This counter is used by the wait_seqno code to notice that reset | |
1213 | * event happened and it needs to restart the entire ioctl (since most | |
1214 | * likely the seqno it waited for won't ever signal anytime soon). | |
f69061be DV |
1215 | * |
1216 | * This is important for lock-free wait paths, where no contended lock | |
1217 | * naturally enforces the correct ordering between the bail-out of the | |
1218 | * waiter and the gpu reset work code. | |
1f83fee0 DV |
1219 | */ |
1220 | atomic_t reset_counter; | |
1221 | ||
1f83fee0 | 1222 | #define I915_RESET_IN_PROGRESS_FLAG 1 |
2ac0f450 | 1223 | #define I915_WEDGED (1 << 31) |
1f83fee0 DV |
1224 | |
1225 | /** | |
1226 | * Waitqueue to signal when the reset has completed. Used by clients | |
1227 | * that wait for dev_priv->mm.wedged to settle. | |
1228 | */ | |
1229 | wait_queue_head_t reset_queue; | |
33196ded | 1230 | |
88b4aa87 MK |
1231 | /* Userspace knobs for gpu hang simulation; |
1232 | * combines both a ring mask, and extra flags | |
1233 | */ | |
1234 | u32 stop_rings; | |
1235 | #define I915_STOP_RING_ALLOW_BAN (1 << 31) | |
1236 | #define I915_STOP_RING_ALLOW_WARN (1 << 30) | |
094f9a54 CW |
1237 | |
1238 | /* For missed irq/seqno simulation. */ | |
1239 | unsigned int test_irq_rings; | |
99584db3 DV |
1240 | }; |
1241 | ||
b8efb17b ZR |
1242 | enum modeset_restore { |
1243 | MODESET_ON_LID_OPEN, | |
1244 | MODESET_DONE, | |
1245 | MODESET_SUSPENDED, | |
1246 | }; | |
1247 | ||
6acab15a | 1248 | struct ddi_vbt_port_info { |
ce4dd49e DL |
1249 | /* |
1250 | * This is an index in the HDMI/DVI DDI buffer translation table. | |
1251 | * The special value HDMI_LEVEL_SHIFT_UNKNOWN means the VBT didn't | |
1252 | * populate this field. | |
1253 | */ | |
1254 | #define HDMI_LEVEL_SHIFT_UNKNOWN 0xff | |
6acab15a | 1255 | uint8_t hdmi_level_shift; |
311a2094 PZ |
1256 | |
1257 | uint8_t supports_dvi:1; | |
1258 | uint8_t supports_hdmi:1; | |
1259 | uint8_t supports_dp:1; | |
6acab15a PZ |
1260 | }; |
1261 | ||
83a7280e PB |
1262 | enum drrs_support_type { |
1263 | DRRS_NOT_SUPPORTED = 0, | |
1264 | STATIC_DRRS_SUPPORT = 1, | |
1265 | SEAMLESS_DRRS_SUPPORT = 2 | |
1266 | }; | |
1267 | ||
41aa3448 RV |
1268 | struct intel_vbt_data { |
1269 | struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */ | |
1270 | struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */ | |
1271 | ||
1272 | /* Feature bits */ | |
1273 | unsigned int int_tv_support:1; | |
1274 | unsigned int lvds_dither:1; | |
1275 | unsigned int lvds_vbt:1; | |
1276 | unsigned int int_crt_support:1; | |
1277 | unsigned int lvds_use_ssc:1; | |
1278 | unsigned int display_clock_mode:1; | |
1279 | unsigned int fdi_rx_polarity_inverted:1; | |
3e6bd011 | 1280 | unsigned int has_mipi:1; |
41aa3448 RV |
1281 | int lvds_ssc_freq; |
1282 | unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */ | |
1283 | ||
83a7280e PB |
1284 | enum drrs_support_type drrs_type; |
1285 | ||
41aa3448 RV |
1286 | /* eDP */ |
1287 | int edp_rate; | |
1288 | int edp_lanes; | |
1289 | int edp_preemphasis; | |
1290 | int edp_vswing; | |
1291 | bool edp_initialized; | |
1292 | bool edp_support; | |
1293 | int edp_bpp; | |
1294 | struct edp_power_seq edp_pps; | |
1295 | ||
f00076d2 JN |
1296 | struct { |
1297 | u16 pwm_freq_hz; | |
39fbc9c8 | 1298 | bool present; |
f00076d2 | 1299 | bool active_low_pwm; |
1de6068e | 1300 | u8 min_brightness; /* min_brightness/255 of max */ |
f00076d2 JN |
1301 | } backlight; |
1302 | ||
d17c5443 SK |
1303 | /* MIPI DSI */ |
1304 | struct { | |
3e6bd011 | 1305 | u16 port; |
d17c5443 | 1306 | u16 panel_id; |
d3b542fc SK |
1307 | struct mipi_config *config; |
1308 | struct mipi_pps_data *pps; | |
1309 | u8 seq_version; | |
1310 | u32 size; | |
1311 | u8 *data; | |
1312 | u8 *sequence[MIPI_SEQ_MAX]; | |
d17c5443 SK |
1313 | } dsi; |
1314 | ||
41aa3448 RV |
1315 | int crt_ddc_pin; |
1316 | ||
1317 | int child_dev_num; | |
768f69c9 | 1318 | union child_device_config *child_dev; |
6acab15a PZ |
1319 | |
1320 | struct ddi_vbt_port_info ddi_port_info[I915_MAX_PORTS]; | |
41aa3448 RV |
1321 | }; |
1322 | ||
77c122bc VS |
1323 | enum intel_ddb_partitioning { |
1324 | INTEL_DDB_PART_1_2, | |
1325 | INTEL_DDB_PART_5_6, /* IVB+ */ | |
1326 | }; | |
1327 | ||
1fd527cc VS |
1328 | struct intel_wm_level { |
1329 | bool enable; | |
1330 | uint32_t pri_val; | |
1331 | uint32_t spr_val; | |
1332 | uint32_t cur_val; | |
1333 | uint32_t fbc_val; | |
1334 | }; | |
1335 | ||
820c1980 | 1336 | struct ilk_wm_values { |
609cedef VS |
1337 | uint32_t wm_pipe[3]; |
1338 | uint32_t wm_lp[3]; | |
1339 | uint32_t wm_lp_spr[3]; | |
1340 | uint32_t wm_linetime[3]; | |
1341 | bool enable_fbc_wm; | |
1342 | enum intel_ddb_partitioning partitioning; | |
1343 | }; | |
1344 | ||
c67a470b | 1345 | /* |
765dab67 PZ |
1346 | * This struct helps tracking the state needed for runtime PM, which puts the |
1347 | * device in PCI D3 state. Notice that when this happens, nothing on the | |
1348 | * graphics device works, even register access, so we don't get interrupts nor | |
1349 | * anything else. | |
c67a470b | 1350 | * |
765dab67 PZ |
1351 | * Every piece of our code that needs to actually touch the hardware needs to |
1352 | * either call intel_runtime_pm_get or call intel_display_power_get with the | |
1353 | * appropriate power domain. | |
a8a8bd54 | 1354 | * |
765dab67 PZ |
1355 | * Our driver uses the autosuspend delay feature, which means we'll only really |
1356 | * suspend if we stay with zero refcount for a certain amount of time. The | |
1357 | * default value is currently very conservative (see intel_init_runtime_pm), but | |
1358 | * it can be changed with the standard runtime PM files from sysfs. | |
c67a470b PZ |
1359 | * |
1360 | * The irqs_disabled variable becomes true exactly after we disable the IRQs and | |
1361 | * goes back to false exactly before we reenable the IRQs. We use this variable | |
1362 | * to check if someone is trying to enable/disable IRQs while they're supposed | |
1363 | * to be disabled. This shouldn't happen and we'll print some error messages in | |
730488b2 | 1364 | * case it happens. |
c67a470b | 1365 | * |
765dab67 | 1366 | * For more, read the Documentation/power/runtime_pm.txt. |
c67a470b | 1367 | */ |
5d584b2e PZ |
1368 | struct i915_runtime_pm { |
1369 | bool suspended; | |
9df7575f | 1370 | bool _irqs_disabled; |
c67a470b PZ |
1371 | }; |
1372 | ||
926321d5 DV |
1373 | enum intel_pipe_crc_source { |
1374 | INTEL_PIPE_CRC_SOURCE_NONE, | |
1375 | INTEL_PIPE_CRC_SOURCE_PLANE1, | |
1376 | INTEL_PIPE_CRC_SOURCE_PLANE2, | |
1377 | INTEL_PIPE_CRC_SOURCE_PF, | |
5b3a856b | 1378 | INTEL_PIPE_CRC_SOURCE_PIPE, |
3d099a05 DV |
1379 | /* TV/DP on pre-gen5/vlv can't use the pipe source. */ |
1380 | INTEL_PIPE_CRC_SOURCE_TV, | |
1381 | INTEL_PIPE_CRC_SOURCE_DP_B, | |
1382 | INTEL_PIPE_CRC_SOURCE_DP_C, | |
1383 | INTEL_PIPE_CRC_SOURCE_DP_D, | |
46a19188 | 1384 | INTEL_PIPE_CRC_SOURCE_AUTO, |
926321d5 DV |
1385 | INTEL_PIPE_CRC_SOURCE_MAX, |
1386 | }; | |
1387 | ||
8bf1e9f1 | 1388 | struct intel_pipe_crc_entry { |
ac2300d4 | 1389 | uint32_t frame; |
8bf1e9f1 SH |
1390 | uint32_t crc[5]; |
1391 | }; | |
1392 | ||
b2c88f5b | 1393 | #define INTEL_PIPE_CRC_ENTRIES_NR 128 |
8bf1e9f1 | 1394 | struct intel_pipe_crc { |
d538bbdf DL |
1395 | spinlock_t lock; |
1396 | bool opened; /* exclusive access to the result file */ | |
e5f75aca | 1397 | struct intel_pipe_crc_entry *entries; |
926321d5 | 1398 | enum intel_pipe_crc_source source; |
d538bbdf | 1399 | int head, tail; |
07144428 | 1400 | wait_queue_head_t wq; |
8bf1e9f1 SH |
1401 | }; |
1402 | ||
f99d7069 DV |
1403 | struct i915_frontbuffer_tracking { |
1404 | struct mutex lock; | |
1405 | ||
1406 | /* | |
1407 | * Tracking bits for delayed frontbuffer flushing du to gpu activity or | |
1408 | * scheduled flips. | |
1409 | */ | |
1410 | unsigned busy_bits; | |
1411 | unsigned flip_bits; | |
1412 | }; | |
1413 | ||
77fec556 | 1414 | struct drm_i915_private { |
f4c956ad | 1415 | struct drm_device *dev; |
42dcedd4 | 1416 | struct kmem_cache *slab; |
f4c956ad | 1417 | |
5c969aa7 | 1418 | const struct intel_device_info info; |
f4c956ad DV |
1419 | |
1420 | int relative_constants_mode; | |
1421 | ||
1422 | void __iomem *regs; | |
1423 | ||
907b28c5 | 1424 | struct intel_uncore uncore; |
f4c956ad DV |
1425 | |
1426 | struct intel_gmbus gmbus[GMBUS_NUM_PORTS]; | |
1427 | ||
28c70f16 | 1428 | |
f4c956ad DV |
1429 | /** gmbus_mutex protects against concurrent usage of the single hw gmbus |
1430 | * controller on different i2c buses. */ | |
1431 | struct mutex gmbus_mutex; | |
1432 | ||
1433 | /** | |
1434 | * Base address of the gmbus and gpio block. | |
1435 | */ | |
1436 | uint32_t gpio_mmio_base; | |
1437 | ||
b6fdd0f2 SS |
1438 | /* MMIO base address for MIPI regs */ |
1439 | uint32_t mipi_mmio_base; | |
1440 | ||
28c70f16 DV |
1441 | wait_queue_head_t gmbus_wait_queue; |
1442 | ||
f4c956ad | 1443 | struct pci_dev *bridge_dev; |
a4872ba6 | 1444 | struct intel_engine_cs ring[I915_NUM_RINGS]; |
3e78998a | 1445 | struct drm_i915_gem_object *semaphore_obj; |
f72b3435 | 1446 | uint32_t last_seqno, next_seqno; |
f4c956ad DV |
1447 | |
1448 | drm_dma_handle_t *status_page_dmah; | |
f4c956ad DV |
1449 | struct resource mch_res; |
1450 | ||
f4c956ad DV |
1451 | /* protects the irq masks */ |
1452 | spinlock_t irq_lock; | |
1453 | ||
84c33a64 SG |
1454 | /* protects the mmio flip data */ |
1455 | spinlock_t mmio_flip_lock; | |
1456 | ||
f8b79e58 ID |
1457 | bool display_irqs_enabled; |
1458 | ||
9ee32fea DV |
1459 | /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */ |
1460 | struct pm_qos_request pm_qos; | |
1461 | ||
f4c956ad | 1462 | /* DPIO indirect register protection */ |
09153000 | 1463 | struct mutex dpio_lock; |
f4c956ad DV |
1464 | |
1465 | /** Cached value of IMR to avoid reads in updating the bitfield */ | |
abd58f01 BW |
1466 | union { |
1467 | u32 irq_mask; | |
1468 | u32 de_irq_mask[I915_MAX_PIPES]; | |
1469 | }; | |
f4c956ad | 1470 | u32 gt_irq_mask; |
605cd25b | 1471 | u32 pm_irq_mask; |
a6706b45 | 1472 | u32 pm_rps_events; |
91d181dd | 1473 | u32 pipestat_irq_mask[I915_MAX_PIPES]; |
f4c956ad | 1474 | |
f4c956ad | 1475 | struct work_struct hotplug_work; |
b543fb04 EE |
1476 | struct { |
1477 | unsigned long hpd_last_jiffies; | |
1478 | int hpd_cnt; | |
1479 | enum { | |
1480 | HPD_ENABLED = 0, | |
1481 | HPD_DISABLED = 1, | |
1482 | HPD_MARK_DISABLED = 2 | |
1483 | } hpd_mark; | |
1484 | } hpd_stats[HPD_NUM_PINS]; | |
142e2398 | 1485 | u32 hpd_event_bits; |
ac4c16c5 | 1486 | struct timer_list hotplug_reenable_timer; |
f4c956ad | 1487 | |
5c3fe8b0 | 1488 | struct i915_fbc fbc; |
439d7ac0 | 1489 | struct i915_drrs drrs; |
f4c956ad | 1490 | struct intel_opregion opregion; |
41aa3448 | 1491 | struct intel_vbt_data vbt; |
f4c956ad DV |
1492 | |
1493 | /* overlay */ | |
1494 | struct intel_overlay *overlay; | |
f4c956ad | 1495 | |
58c68779 JN |
1496 | /* backlight registers and fields in struct intel_panel */ |
1497 | spinlock_t backlight_lock; | |
31ad8ec6 | 1498 | |
f4c956ad | 1499 | /* LVDS info */ |
f4c956ad DV |
1500 | bool no_aux_handshake; |
1501 | ||
f4c956ad DV |
1502 | struct drm_i915_fence_reg fence_regs[I915_MAX_NUM_FENCES]; /* assume 965 */ |
1503 | int fence_reg_start; /* 4 if userland hasn't ioctl'd us yet */ | |
1504 | int num_fence_regs; /* 8 on pre-965, 16 otherwise */ | |
1505 | ||
1506 | unsigned int fsb_freq, mem_freq, is_ddr3; | |
d60c4473 | 1507 | unsigned int vlv_cdclk_freq; |
f4c956ad | 1508 | |
645416f5 DV |
1509 | /** |
1510 | * wq - Driver workqueue for GEM. | |
1511 | * | |
1512 | * NOTE: Work items scheduled here are not allowed to grab any modeset | |
1513 | * locks, for otherwise the flushing done in the pageflip code will | |
1514 | * result in deadlocks. | |
1515 | */ | |
f4c956ad DV |
1516 | struct workqueue_struct *wq; |
1517 | ||
1518 | /* Display functions */ | |
1519 | struct drm_i915_display_funcs display; | |
1520 | ||
1521 | /* PCH chipset type */ | |
1522 | enum intel_pch pch_type; | |
17a303ec | 1523 | unsigned short pch_id; |
f4c956ad DV |
1524 | |
1525 | unsigned long quirks; | |
1526 | ||
b8efb17b ZR |
1527 | enum modeset_restore modeset_restore; |
1528 | struct mutex modeset_restore_lock; | |
673a394b | 1529 | |
a7bbbd63 | 1530 | struct list_head vm_list; /* Global list of all address spaces */ |
0260c420 | 1531 | struct i915_gtt gtt; /* VM representing the global address space */ |
5d4545ae | 1532 | |
4b5aed62 | 1533 | struct i915_gem_mm mm; |
5cc9ed4b CW |
1534 | #if defined(CONFIG_MMU_NOTIFIER) |
1535 | DECLARE_HASHTABLE(mmu_notifiers, 7); | |
1536 | #endif | |
8781342d | 1537 | |
8781342d DV |
1538 | /* Kernel Modesetting */ |
1539 | ||
9b9d172d | 1540 | struct sdvo_device_mapping sdvo_mappings[2]; |
652c393a | 1541 | |
76c4ac04 DL |
1542 | struct drm_crtc *plane_to_crtc_mapping[I915_MAX_PIPES]; |
1543 | struct drm_crtc *pipe_to_crtc_mapping[I915_MAX_PIPES]; | |
6b95a207 KH |
1544 | wait_queue_head_t pending_flip_queue; |
1545 | ||
c4597872 DV |
1546 | #ifdef CONFIG_DEBUG_FS |
1547 | struct intel_pipe_crc pipe_crc[I915_MAX_PIPES]; | |
1548 | #endif | |
1549 | ||
e72f9fbf DV |
1550 | int num_shared_dpll; |
1551 | struct intel_shared_dpll shared_dplls[I915_NUM_PLLS]; | |
e4607fcf | 1552 | int dpio_phy_iosf_port[I915_NUM_PHYS_VLV]; |
ee7b9f93 | 1553 | |
652c393a JB |
1554 | /* Reclocking support */ |
1555 | bool render_reclock_avail; | |
1556 | bool lvds_downclock_avail; | |
18f9ed12 ZY |
1557 | /* indicates the reduced downclock for LVDS*/ |
1558 | int lvds_downclock; | |
f99d7069 DV |
1559 | |
1560 | struct i915_frontbuffer_tracking fb_tracking; | |
1561 | ||
652c393a | 1562 | u16 orig_clock; |
f97108d1 | 1563 | |
c4804411 | 1564 | bool mchbar_need_disable; |
f97108d1 | 1565 | |
a4da4fa4 DV |
1566 | struct intel_l3_parity l3_parity; |
1567 | ||
59124506 BW |
1568 | /* Cannot be determined by PCIID. You must always read a register. */ |
1569 | size_t ellc_size; | |
1570 | ||
c6a828d3 | 1571 | /* gen6+ rps state */ |
c85aa885 | 1572 | struct intel_gen6_power_mgmt rps; |
c6a828d3 | 1573 | |
20e4d407 DV |
1574 | /* ilk-only ips/rps state. Everything in here is protected by the global |
1575 | * mchdev_lock in intel_pm.c */ | |
c85aa885 | 1576 | struct intel_ilk_power_mgmt ips; |
b5e50c3f | 1577 | |
83c00f55 | 1578 | struct i915_power_domains power_domains; |
a38911a3 | 1579 | |
a031d709 | 1580 | struct i915_psr psr; |
3f51e471 | 1581 | |
99584db3 | 1582 | struct i915_gpu_error gpu_error; |
ae681d96 | 1583 | |
c9cddffc JB |
1584 | struct drm_i915_gem_object *vlv_pctx; |
1585 | ||
4520f53a | 1586 | #ifdef CONFIG_DRM_I915_FBDEV |
8be48d92 DA |
1587 | /* list of fbdev register on this device */ |
1588 | struct intel_fbdev *fbdev; | |
4520f53a | 1589 | #endif |
e953fd7b | 1590 | |
073f34d9 JB |
1591 | /* |
1592 | * The console may be contended at resume, but we don't | |
1593 | * want it to block on it. | |
1594 | */ | |
1595 | struct work_struct console_resume_work; | |
1596 | ||
e953fd7b | 1597 | struct drm_property *broadcast_rgb_property; |
3f43c48d | 1598 | struct drm_property *force_audio_property; |
e3689190 | 1599 | |
254f965c | 1600 | uint32_t hw_context_size; |
a33afea5 | 1601 | struct list_head context_list; |
f4c956ad | 1602 | |
3e68320e | 1603 | u32 fdi_rx_config; |
68d18ad7 | 1604 | |
842f1c8b | 1605 | u32 suspend_count; |
f4c956ad | 1606 | struct i915_suspend_saved_registers regfile; |
ddeea5b0 | 1607 | struct vlv_s0ix_state vlv_s0ix_state; |
231f42a4 | 1608 | |
53615a5e VS |
1609 | struct { |
1610 | /* | |
1611 | * Raw watermark latency values: | |
1612 | * in 0.1us units for WM0, | |
1613 | * in 0.5us units for WM1+. | |
1614 | */ | |
1615 | /* primary */ | |
1616 | uint16_t pri_latency[5]; | |
1617 | /* sprite */ | |
1618 | uint16_t spr_latency[5]; | |
1619 | /* cursor */ | |
1620 | uint16_t cur_latency[5]; | |
609cedef VS |
1621 | |
1622 | /* current hardware state */ | |
820c1980 | 1623 | struct ilk_wm_values hw; |
53615a5e VS |
1624 | } wm; |
1625 | ||
8a187455 PZ |
1626 | struct i915_runtime_pm pm; |
1627 | ||
13cf5504 DA |
1628 | struct intel_digital_port *hpd_irq_port[I915_MAX_PORTS]; |
1629 | u32 long_hpd_port_mask; | |
1630 | u32 short_hpd_port_mask; | |
1631 | struct work_struct dig_port_work; | |
1632 | ||
0e32b39c DA |
1633 | /* |
1634 | * if we get a HPD irq from DP and a HPD irq from non-DP | |
1635 | * the non-DP HPD could block the workqueue on a mode config | |
1636 | * mutex getting, that userspace may have taken. However | |
1637 | * userspace is waiting on the DP workqueue to run which is | |
1638 | * blocked behind the non-DP one. | |
1639 | */ | |
1640 | struct workqueue_struct *dp_wq; | |
1641 | ||
231f42a4 DV |
1642 | /* Old dri1 support infrastructure, beware the dragons ya fools entering |
1643 | * here! */ | |
1644 | struct i915_dri1_state dri1; | |
db1b76ca DV |
1645 | /* Old ums support infrastructure, same warning applies. */ |
1646 | struct i915_ums_state ums; | |
bdf1e7e3 | 1647 | |
a83014d3 OM |
1648 | /* Abstract the submission mechanism (legacy ringbuffer or execlists) away */ |
1649 | struct { | |
1650 | int (*do_execbuf)(struct drm_device *dev, struct drm_file *file, | |
1651 | struct intel_engine_cs *ring, | |
1652 | struct intel_context *ctx, | |
1653 | struct drm_i915_gem_execbuffer2 *args, | |
1654 | struct list_head *vmas, | |
1655 | struct drm_i915_gem_object *batch_obj, | |
1656 | u64 exec_start, u32 flags); | |
1657 | int (*init_rings)(struct drm_device *dev); | |
1658 | void (*cleanup_ring)(struct intel_engine_cs *ring); | |
1659 | void (*stop_ring)(struct intel_engine_cs *ring); | |
1660 | } gt; | |
1661 | ||
bdf1e7e3 DV |
1662 | /* |
1663 | * NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch | |
1664 | * will be rejected. Instead look for a better place. | |
1665 | */ | |
77fec556 | 1666 | }; |
1da177e4 | 1667 | |
2c1792a1 CW |
1668 | static inline struct drm_i915_private *to_i915(const struct drm_device *dev) |
1669 | { | |
1670 | return dev->dev_private; | |
1671 | } | |
1672 | ||
b4519513 CW |
1673 | /* Iterate over initialised rings */ |
1674 | #define for_each_ring(ring__, dev_priv__, i__) \ | |
1675 | for ((i__) = 0; (i__) < I915_NUM_RINGS; (i__)++) \ | |
1676 | if (((ring__) = &(dev_priv__)->ring[(i__)]), intel_ring_initialized((ring__))) | |
1677 | ||
b1d7e4b4 WF |
1678 | enum hdmi_force_audio { |
1679 | HDMI_AUDIO_OFF_DVI = -2, /* no aux data for HDMI-DVI converter */ | |
1680 | HDMI_AUDIO_OFF, /* force turn off HDMI audio */ | |
1681 | HDMI_AUDIO_AUTO, /* trust EDID */ | |
1682 | HDMI_AUDIO_ON, /* force turn on HDMI audio */ | |
1683 | }; | |
1684 | ||
190d6cd5 | 1685 | #define I915_GTT_OFFSET_NONE ((u32)-1) |
ed2f3452 | 1686 | |
37e680a1 CW |
1687 | struct drm_i915_gem_object_ops { |
1688 | /* Interface between the GEM object and its backing storage. | |
1689 | * get_pages() is called once prior to the use of the associated set | |
1690 | * of pages before to binding them into the GTT, and put_pages() is | |
1691 | * called after we no longer need them. As we expect there to be | |
1692 | * associated cost with migrating pages between the backing storage | |
1693 | * and making them available for the GPU (e.g. clflush), we may hold | |
1694 | * onto the pages after they are no longer referenced by the GPU | |
1695 | * in case they may be used again shortly (for example migrating the | |
1696 | * pages to a different memory domain within the GTT). put_pages() | |
1697 | * will therefore most likely be called when the object itself is | |
1698 | * being released or under memory pressure (where we attempt to | |
1699 | * reap pages for the shrinker). | |
1700 | */ | |
1701 | int (*get_pages)(struct drm_i915_gem_object *); | |
1702 | void (*put_pages)(struct drm_i915_gem_object *); | |
5cc9ed4b CW |
1703 | int (*dmabuf_export)(struct drm_i915_gem_object *); |
1704 | void (*release)(struct drm_i915_gem_object *); | |
37e680a1 CW |
1705 | }; |
1706 | ||
a071fa00 DV |
1707 | /* |
1708 | * Frontbuffer tracking bits. Set in obj->frontbuffer_bits while a gem bo is | |
1709 | * considered to be the frontbuffer for the given plane interface-vise. This | |
1710 | * doesn't mean that the hw necessarily already scans it out, but that any | |
1711 | * rendering (by the cpu or gpu) will land in the frontbuffer eventually. | |
1712 | * | |
1713 | * We have one bit per pipe and per scanout plane type. | |
1714 | */ | |
1715 | #define INTEL_FRONTBUFFER_BITS_PER_PIPE 4 | |
1716 | #define INTEL_FRONTBUFFER_BITS \ | |
1717 | (INTEL_FRONTBUFFER_BITS_PER_PIPE * I915_MAX_PIPES) | |
1718 | #define INTEL_FRONTBUFFER_PRIMARY(pipe) \ | |
1719 | (1 << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))) | |
1720 | #define INTEL_FRONTBUFFER_CURSOR(pipe) \ | |
1721 | (1 << (1 +(INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))) | |
1722 | #define INTEL_FRONTBUFFER_SPRITE(pipe) \ | |
1723 | (1 << (2 +(INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))) | |
1724 | #define INTEL_FRONTBUFFER_OVERLAY(pipe) \ | |
1725 | (1 << (3 +(INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))) | |
cc36513c DV |
1726 | #define INTEL_FRONTBUFFER_ALL_MASK(pipe) \ |
1727 | (0xf << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))) | |
a071fa00 | 1728 | |
673a394b | 1729 | struct drm_i915_gem_object { |
c397b908 | 1730 | struct drm_gem_object base; |
673a394b | 1731 | |
37e680a1 CW |
1732 | const struct drm_i915_gem_object_ops *ops; |
1733 | ||
2f633156 BW |
1734 | /** List of VMAs backed by this object */ |
1735 | struct list_head vma_list; | |
1736 | ||
c1ad11fc CW |
1737 | /** Stolen memory for this object, instead of being backed by shmem. */ |
1738 | struct drm_mm_node *stolen; | |
35c20a60 | 1739 | struct list_head global_list; |
673a394b | 1740 | |
69dc4987 | 1741 | struct list_head ring_list; |
b25cb2f8 BW |
1742 | /** Used in execbuf to temporarily hold a ref */ |
1743 | struct list_head obj_exec_link; | |
673a394b EA |
1744 | |
1745 | /** | |
65ce3027 CW |
1746 | * This is set if the object is on the active lists (has pending |
1747 | * rendering and so a non-zero seqno), and is not set if it i s on | |
1748 | * inactive (ready to be unbound) list. | |
673a394b | 1749 | */ |
0206e353 | 1750 | unsigned int active:1; |
673a394b EA |
1751 | |
1752 | /** | |
1753 | * This is set if the object has been written to since last bound | |
1754 | * to the GTT | |
1755 | */ | |
0206e353 | 1756 | unsigned int dirty:1; |
778c3544 DV |
1757 | |
1758 | /** | |
1759 | * Fence register bits (if any) for this object. Will be set | |
1760 | * as needed when mapped into the GTT. | |
1761 | * Protected by dev->struct_mutex. | |
778c3544 | 1762 | */ |
4b9de737 | 1763 | signed int fence_reg:I915_MAX_NUM_FENCE_BITS; |
778c3544 | 1764 | |
778c3544 DV |
1765 | /** |
1766 | * Advice: are the backing pages purgeable? | |
1767 | */ | |
0206e353 | 1768 | unsigned int madv:2; |
778c3544 | 1769 | |
778c3544 DV |
1770 | /** |
1771 | * Current tiling mode for the object. | |
1772 | */ | |
0206e353 | 1773 | unsigned int tiling_mode:2; |
5d82e3e6 CW |
1774 | /** |
1775 | * Whether the tiling parameters for the currently associated fence | |
1776 | * register have changed. Note that for the purposes of tracking | |
1777 | * tiling changes we also treat the unfenced register, the register | |
1778 | * slot that the object occupies whilst it executes a fenced | |
1779 | * command (such as BLT on gen2/3), as a "fence". | |
1780 | */ | |
1781 | unsigned int fence_dirty:1; | |
778c3544 | 1782 | |
75e9e915 DV |
1783 | /** |
1784 | * Is the object at the current location in the gtt mappable and | |
1785 | * fenceable? Used to avoid costly recalculations. | |
1786 | */ | |
0206e353 | 1787 | unsigned int map_and_fenceable:1; |
75e9e915 | 1788 | |
fb7d516a DV |
1789 | /** |
1790 | * Whether the current gtt mapping needs to be mappable (and isn't just | |
1791 | * mappable by accident). Track pin and fault separate for a more | |
1792 | * accurate mappable working set. | |
1793 | */ | |
0206e353 AJ |
1794 | unsigned int fault_mappable:1; |
1795 | unsigned int pin_mappable:1; | |
cc98b413 | 1796 | unsigned int pin_display:1; |
fb7d516a | 1797 | |
24f3a8cf AG |
1798 | /* |
1799 | * Is the object to be mapped as read-only to the GPU | |
1800 | * Only honoured if hardware has relevant pte bit | |
1801 | */ | |
1802 | unsigned long gt_ro:1; | |
651d794f | 1803 | unsigned int cache_level:3; |
93dfb40c | 1804 | |
7bddb01f | 1805 | unsigned int has_aliasing_ppgtt_mapping:1; |
74898d7e | 1806 | unsigned int has_global_gtt_mapping:1; |
9da3da66 | 1807 | unsigned int has_dma_mapping:1; |
7bddb01f | 1808 | |
a071fa00 DV |
1809 | unsigned int frontbuffer_bits:INTEL_FRONTBUFFER_BITS; |
1810 | ||
9da3da66 | 1811 | struct sg_table *pages; |
a5570178 | 1812 | int pages_pin_count; |
673a394b | 1813 | |
1286ff73 | 1814 | /* prime dma-buf support */ |
9a70cc2a DA |
1815 | void *dma_buf_vmapping; |
1816 | int vmapping_count; | |
1817 | ||
a4872ba6 | 1818 | struct intel_engine_cs *ring; |
caea7476 | 1819 | |
1c293ea3 | 1820 | /** Breadcrumb of last rendering to the buffer. */ |
0201f1ec CW |
1821 | uint32_t last_read_seqno; |
1822 | uint32_t last_write_seqno; | |
caea7476 CW |
1823 | /** Breadcrumb of last fenced GPU access to the buffer. */ |
1824 | uint32_t last_fenced_seqno; | |
673a394b | 1825 | |
778c3544 | 1826 | /** Current tiling stride for the object, if it's tiled. */ |
de151cf6 | 1827 | uint32_t stride; |
673a394b | 1828 | |
80075d49 DV |
1829 | /** References from framebuffers, locks out tiling changes. */ |
1830 | unsigned long framebuffer_references; | |
1831 | ||
280b713b | 1832 | /** Record of address bit 17 of each page at last unbind. */ |
d312ec25 | 1833 | unsigned long *bit_17; |
280b713b | 1834 | |
79e53945 | 1835 | /** User space pin count and filp owning the pin */ |
aa5f8021 | 1836 | unsigned long user_pin_count; |
79e53945 | 1837 | struct drm_file *pin_filp; |
71acb5eb DA |
1838 | |
1839 | /** for phy allocated objects */ | |
00731155 | 1840 | drm_dma_handle_t *phys_handle; |
673a394b | 1841 | |
5cc9ed4b CW |
1842 | union { |
1843 | struct i915_gem_userptr { | |
1844 | uintptr_t ptr; | |
1845 | unsigned read_only :1; | |
1846 | unsigned workers :4; | |
1847 | #define I915_GEM_USERPTR_MAX_WORKERS 15 | |
1848 | ||
1849 | struct mm_struct *mm; | |
1850 | struct i915_mmu_object *mn; | |
1851 | struct work_struct *work; | |
1852 | } userptr; | |
1853 | }; | |
1854 | }; | |
62b8b215 | 1855 | #define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base) |
23010e43 | 1856 | |
a071fa00 DV |
1857 | void i915_gem_track_fb(struct drm_i915_gem_object *old, |
1858 | struct drm_i915_gem_object *new, | |
1859 | unsigned frontbuffer_bits); | |
1860 | ||
673a394b EA |
1861 | /** |
1862 | * Request queue structure. | |
1863 | * | |
1864 | * The request queue allows us to note sequence numbers that have been emitted | |
1865 | * and may be associated with active buffers to be retired. | |
1866 | * | |
1867 | * By keeping this list, we can avoid having to do questionable | |
1868 | * sequence-number comparisons on buffer last_rendering_seqnos, and associate | |
1869 | * an emission time with seqnos for tracking how far ahead of the GPU we are. | |
1870 | */ | |
1871 | struct drm_i915_gem_request { | |
852835f3 | 1872 | /** On Which ring this request was generated */ |
a4872ba6 | 1873 | struct intel_engine_cs *ring; |
852835f3 | 1874 | |
673a394b EA |
1875 | /** GEM sequence number associated with this request. */ |
1876 | uint32_t seqno; | |
1877 | ||
7d736f4f MK |
1878 | /** Position in the ringbuffer of the start of the request */ |
1879 | u32 head; | |
1880 | ||
1881 | /** Position in the ringbuffer of the end of the request */ | |
a71d8d94 CW |
1882 | u32 tail; |
1883 | ||
0e50e96b | 1884 | /** Context related to this request */ |
273497e5 | 1885 | struct intel_context *ctx; |
0e50e96b | 1886 | |
7d736f4f MK |
1887 | /** Batch buffer related to this request if any */ |
1888 | struct drm_i915_gem_object *batch_obj; | |
1889 | ||
673a394b EA |
1890 | /** Time at which this request was emitted, in jiffies. */ |
1891 | unsigned long emitted_jiffies; | |
1892 | ||
b962442e | 1893 | /** global list entry for this request */ |
673a394b | 1894 | struct list_head list; |
b962442e | 1895 | |
f787a5f5 | 1896 | struct drm_i915_file_private *file_priv; |
b962442e EA |
1897 | /** file_priv list entry for this request */ |
1898 | struct list_head client_list; | |
673a394b EA |
1899 | }; |
1900 | ||
1901 | struct drm_i915_file_private { | |
b29c19b6 | 1902 | struct drm_i915_private *dev_priv; |
ab0e7ff9 | 1903 | struct drm_file *file; |
b29c19b6 | 1904 | |
673a394b | 1905 | struct { |
99057c81 | 1906 | spinlock_t lock; |
b962442e | 1907 | struct list_head request_list; |
b29c19b6 | 1908 | struct delayed_work idle_work; |
673a394b | 1909 | } mm; |
40521054 | 1910 | struct idr context_idr; |
e59ec13d | 1911 | |
b29c19b6 | 1912 | atomic_t rps_wait_boost; |
a4872ba6 | 1913 | struct intel_engine_cs *bsd_ring; |
673a394b EA |
1914 | }; |
1915 | ||
351e3db2 BV |
1916 | /* |
1917 | * A command that requires special handling by the command parser. | |
1918 | */ | |
1919 | struct drm_i915_cmd_descriptor { | |
1920 | /* | |
1921 | * Flags describing how the command parser processes the command. | |
1922 | * | |
1923 | * CMD_DESC_FIXED: The command has a fixed length if this is set, | |
1924 | * a length mask if not set | |
1925 | * CMD_DESC_SKIP: The command is allowed but does not follow the | |
1926 | * standard length encoding for the opcode range in | |
1927 | * which it falls | |
1928 | * CMD_DESC_REJECT: The command is never allowed | |
1929 | * CMD_DESC_REGISTER: The command should be checked against the | |
1930 | * register whitelist for the appropriate ring | |
1931 | * CMD_DESC_MASTER: The command is allowed if the submitting process | |
1932 | * is the DRM master | |
1933 | */ | |
1934 | u32 flags; | |
1935 | #define CMD_DESC_FIXED (1<<0) | |
1936 | #define CMD_DESC_SKIP (1<<1) | |
1937 | #define CMD_DESC_REJECT (1<<2) | |
1938 | #define CMD_DESC_REGISTER (1<<3) | |
1939 | #define CMD_DESC_BITMASK (1<<4) | |
1940 | #define CMD_DESC_MASTER (1<<5) | |
1941 | ||
1942 | /* | |
1943 | * The command's unique identification bits and the bitmask to get them. | |
1944 | * This isn't strictly the opcode field as defined in the spec and may | |
1945 | * also include type, subtype, and/or subop fields. | |
1946 | */ | |
1947 | struct { | |
1948 | u32 value; | |
1949 | u32 mask; | |
1950 | } cmd; | |
1951 | ||
1952 | /* | |
1953 | * The command's length. The command is either fixed length (i.e. does | |
1954 | * not include a length field) or has a length field mask. The flag | |
1955 | * CMD_DESC_FIXED indicates a fixed length. Otherwise, the command has | |
1956 | * a length mask. All command entries in a command table must include | |
1957 | * length information. | |
1958 | */ | |
1959 | union { | |
1960 | u32 fixed; | |
1961 | u32 mask; | |
1962 | } length; | |
1963 | ||
1964 | /* | |
1965 | * Describes where to find a register address in the command to check | |
1966 | * against the ring's register whitelist. Only valid if flags has the | |
1967 | * CMD_DESC_REGISTER bit set. | |
1968 | */ | |
1969 | struct { | |
1970 | u32 offset; | |
1971 | u32 mask; | |
1972 | } reg; | |
1973 | ||
1974 | #define MAX_CMD_DESC_BITMASKS 3 | |
1975 | /* | |
1976 | * Describes command checks where a particular dword is masked and | |
1977 | * compared against an expected value. If the command does not match | |
1978 | * the expected value, the parser rejects it. Only valid if flags has | |
1979 | * the CMD_DESC_BITMASK bit set. Only entries where mask is non-zero | |
1980 | * are valid. | |
d4d48035 BV |
1981 | * |
1982 | * If the check specifies a non-zero condition_mask then the parser | |
1983 | * only performs the check when the bits specified by condition_mask | |
1984 | * are non-zero. | |
351e3db2 BV |
1985 | */ |
1986 | struct { | |
1987 | u32 offset; | |
1988 | u32 mask; | |
1989 | u32 expected; | |
d4d48035 BV |
1990 | u32 condition_offset; |
1991 | u32 condition_mask; | |
351e3db2 BV |
1992 | } bits[MAX_CMD_DESC_BITMASKS]; |
1993 | }; | |
1994 | ||
1995 | /* | |
1996 | * A table of commands requiring special handling by the command parser. | |
1997 | * | |
1998 | * Each ring has an array of tables. Each table consists of an array of command | |
1999 | * descriptors, which must be sorted with command opcodes in ascending order. | |
2000 | */ | |
2001 | struct drm_i915_cmd_table { | |
2002 | const struct drm_i915_cmd_descriptor *table; | |
2003 | int count; | |
2004 | }; | |
2005 | ||
dbbe9127 | 2006 | /* Note that the (struct drm_i915_private *) cast is just to shut up gcc. */ |
7312e2dd CW |
2007 | #define __I915__(p) ({ \ |
2008 | struct drm_i915_private *__p; \ | |
2009 | if (__builtin_types_compatible_p(typeof(*p), struct drm_i915_private)) \ | |
2010 | __p = (struct drm_i915_private *)p; \ | |
2011 | else if (__builtin_types_compatible_p(typeof(*p), struct drm_device)) \ | |
2012 | __p = to_i915((struct drm_device *)p); \ | |
2013 | else \ | |
2014 | BUILD_BUG(); \ | |
2015 | __p; \ | |
2016 | }) | |
dbbe9127 | 2017 | #define INTEL_INFO(p) (&__I915__(p)->info) |
87f1f465 | 2018 | #define INTEL_DEVID(p) (INTEL_INFO(p)->device_id) |
cae5852d | 2019 | |
87f1f465 CW |
2020 | #define IS_I830(dev) (INTEL_DEVID(dev) == 0x3577) |
2021 | #define IS_845G(dev) (INTEL_DEVID(dev) == 0x2562) | |
cae5852d | 2022 | #define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x) |
87f1f465 | 2023 | #define IS_I865G(dev) (INTEL_DEVID(dev) == 0x2572) |
cae5852d | 2024 | #define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g) |
87f1f465 CW |
2025 | #define IS_I915GM(dev) (INTEL_DEVID(dev) == 0x2592) |
2026 | #define IS_I945G(dev) (INTEL_DEVID(dev) == 0x2772) | |
cae5852d ZN |
2027 | #define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm) |
2028 | #define IS_BROADWATER(dev) (INTEL_INFO(dev)->is_broadwater) | |
2029 | #define IS_CRESTLINE(dev) (INTEL_INFO(dev)->is_crestline) | |
87f1f465 | 2030 | #define IS_GM45(dev) (INTEL_DEVID(dev) == 0x2A42) |
cae5852d | 2031 | #define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x) |
87f1f465 CW |
2032 | #define IS_PINEVIEW_G(dev) (INTEL_DEVID(dev) == 0xa001) |
2033 | #define IS_PINEVIEW_M(dev) (INTEL_DEVID(dev) == 0xa011) | |
cae5852d ZN |
2034 | #define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview) |
2035 | #define IS_G33(dev) (INTEL_INFO(dev)->is_g33) | |
87f1f465 | 2036 | #define IS_IRONLAKE_M(dev) (INTEL_DEVID(dev) == 0x0046) |
4b65177b | 2037 | #define IS_IVYBRIDGE(dev) (INTEL_INFO(dev)->is_ivybridge) |
87f1f465 CW |
2038 | #define IS_IVB_GT1(dev) (INTEL_DEVID(dev) == 0x0156 || \ |
2039 | INTEL_DEVID(dev) == 0x0152 || \ | |
2040 | INTEL_DEVID(dev) == 0x015a) | |
2041 | #define IS_SNB_GT1(dev) (INTEL_DEVID(dev) == 0x0102 || \ | |
2042 | INTEL_DEVID(dev) == 0x0106 || \ | |
2043 | INTEL_DEVID(dev) == 0x010A) | |
70a3eb7a | 2044 | #define IS_VALLEYVIEW(dev) (INTEL_INFO(dev)->is_valleyview) |
6df4027b | 2045 | #define IS_CHERRYVIEW(dev) (INTEL_INFO(dev)->is_valleyview && IS_GEN8(dev)) |
4cae9ae0 | 2046 | #define IS_HASWELL(dev) (INTEL_INFO(dev)->is_haswell) |
8179f1f0 | 2047 | #define IS_BROADWELL(dev) (!INTEL_INFO(dev)->is_valleyview && IS_GEN8(dev)) |
cae5852d | 2048 | #define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile) |
ed1c9e2c | 2049 | #define IS_HSW_EARLY_SDV(dev) (IS_HASWELL(dev) && \ |
87f1f465 | 2050 | (INTEL_DEVID(dev) & 0xFF00) == 0x0C00) |
5dd8c4c3 | 2051 | #define IS_BDW_ULT(dev) (IS_BROADWELL(dev) && \ |
87f1f465 CW |
2052 | ((INTEL_DEVID(dev) & 0xf) == 0x2 || \ |
2053 | (INTEL_DEVID(dev) & 0xf) == 0x6 || \ | |
2054 | (INTEL_DEVID(dev) & 0xf) == 0xe)) | |
5dd8c4c3 | 2055 | #define IS_HSW_ULT(dev) (IS_HASWELL(dev) && \ |
87f1f465 | 2056 | (INTEL_DEVID(dev) & 0xFF00) == 0x0A00) |
5dd8c4c3 | 2057 | #define IS_ULT(dev) (IS_HSW_ULT(dev) || IS_BDW_ULT(dev)) |
9435373e | 2058 | #define IS_HSW_GT3(dev) (IS_HASWELL(dev) && \ |
87f1f465 | 2059 | (INTEL_DEVID(dev) & 0x00F0) == 0x0020) |
9bbfd20a | 2060 | /* ULX machines are also considered ULT. */ |
87f1f465 CW |
2061 | #define IS_HSW_ULX(dev) (INTEL_DEVID(dev) == 0x0A0E || \ |
2062 | INTEL_DEVID(dev) == 0x0A1E) | |
b833d685 | 2063 | #define IS_PRELIMINARY_HW(intel_info) ((intel_info)->is_preliminary) |
cae5852d | 2064 | |
85436696 JB |
2065 | /* |
2066 | * The genX designation typically refers to the render engine, so render | |
2067 | * capability related checks should use IS_GEN, while display and other checks | |
2068 | * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular | |
2069 | * chips, etc.). | |
2070 | */ | |
cae5852d ZN |
2071 | #define IS_GEN2(dev) (INTEL_INFO(dev)->gen == 2) |
2072 | #define IS_GEN3(dev) (INTEL_INFO(dev)->gen == 3) | |
2073 | #define IS_GEN4(dev) (INTEL_INFO(dev)->gen == 4) | |
2074 | #define IS_GEN5(dev) (INTEL_INFO(dev)->gen == 5) | |
2075 | #define IS_GEN6(dev) (INTEL_INFO(dev)->gen == 6) | |
85436696 | 2076 | #define IS_GEN7(dev) (INTEL_INFO(dev)->gen == 7) |
d2980845 | 2077 | #define IS_GEN8(dev) (INTEL_INFO(dev)->gen == 8) |
cae5852d | 2078 | |
73ae478c BW |
2079 | #define RENDER_RING (1<<RCS) |
2080 | #define BSD_RING (1<<VCS) | |
2081 | #define BLT_RING (1<<BCS) | |
2082 | #define VEBOX_RING (1<<VECS) | |
845f74a7 | 2083 | #define BSD2_RING (1<<VCS2) |
63c42e56 | 2084 | #define HAS_BSD(dev) (INTEL_INFO(dev)->ring_mask & BSD_RING) |
845f74a7 | 2085 | #define HAS_BSD2(dev) (INTEL_INFO(dev)->ring_mask & BSD2_RING) |
63c42e56 BW |
2086 | #define HAS_BLT(dev) (INTEL_INFO(dev)->ring_mask & BLT_RING) |
2087 | #define HAS_VEBOX(dev) (INTEL_INFO(dev)->ring_mask & VEBOX_RING) | |
2088 | #define HAS_LLC(dev) (INTEL_INFO(dev)->has_llc) | |
2089 | #define HAS_WT(dev) ((IS_HASWELL(dev) || IS_BROADWELL(dev)) && \ | |
2090 | to_i915(dev)->ellc_size) | |
cae5852d ZN |
2091 | #define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws) |
2092 | ||
254f965c | 2093 | #define HAS_HW_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 6) |
127f1003 | 2094 | #define HAS_LOGICAL_RING_CONTEXTS(dev) 0 |
7365fb78 JB |
2095 | #define HAS_ALIASING_PPGTT(dev) (INTEL_INFO(dev)->gen >= 6) |
2096 | #define HAS_PPGTT(dev) (INTEL_INFO(dev)->gen >= 7 && !IS_GEN8(dev)) | |
692ef70c JB |
2097 | #define USES_PPGTT(dev) (i915.enable_ppgtt) |
2098 | #define USES_FULL_PPGTT(dev) (i915.enable_ppgtt == 2) | |
1d2a314c | 2099 | |
05394f39 | 2100 | #define HAS_OVERLAY(dev) (INTEL_INFO(dev)->has_overlay) |
cae5852d ZN |
2101 | #define OVERLAY_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->overlay_needs_physical) |
2102 | ||
b45305fc DV |
2103 | /* Early gen2 have a totally busted CS tlb and require pinned batches. */ |
2104 | #define HAS_BROKEN_CS_TLB(dev) (IS_I830(dev) || IS_845G(dev)) | |
4e6b788c DV |
2105 | /* |
2106 | * dp aux and gmbus irq on gen4 seems to be able to generate legacy interrupts | |
2107 | * even when in MSI mode. This results in spurious interrupt warnings if the | |
2108 | * legacy irq no. is shared with another device. The kernel then disables that | |
2109 | * interrupt source and so prevents the other device from working properly. | |
2110 | */ | |
2111 | #define HAS_AUX_IRQ(dev) (INTEL_INFO(dev)->gen >= 5) | |
2112 | #define HAS_GMBUS_IRQ(dev) (INTEL_INFO(dev)->gen >= 5) | |
b45305fc | 2113 | |
cae5852d ZN |
2114 | /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte |
2115 | * rows, which changed the alignment requirements and fence programming. | |
2116 | */ | |
2117 | #define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \ | |
2118 | IS_I915GM(dev))) | |
2119 | #define SUPPORTS_DIGITAL_OUTPUTS(dev) (!IS_GEN2(dev) && !IS_PINEVIEW(dev)) | |
2120 | #define SUPPORTS_INTEGRATED_HDMI(dev) (IS_G4X(dev) || IS_GEN5(dev)) | |
2121 | #define SUPPORTS_INTEGRATED_DP(dev) (IS_G4X(dev) || IS_GEN5(dev)) | |
cae5852d ZN |
2122 | #define SUPPORTS_TV(dev) (INTEL_INFO(dev)->supports_tv) |
2123 | #define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug) | |
cae5852d ZN |
2124 | |
2125 | #define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2) | |
2126 | #define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr) | |
3a77c4c4 | 2127 | #define HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc) |
cae5852d | 2128 | |
2a114cc1 | 2129 | #define HAS_IPS(dev) (IS_ULT(dev) || IS_BROADWELL(dev)) |
f5adf94e | 2130 | |
dd93be58 | 2131 | #define HAS_DDI(dev) (INTEL_INFO(dev)->has_ddi) |
30568c45 | 2132 | #define HAS_FPGA_DBG_UNCLAIMED(dev) (INTEL_INFO(dev)->has_fpga_dbg) |
ed8546ac | 2133 | #define HAS_PSR(dev) (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
6157d3c8 | 2134 | #define HAS_RUNTIME_PM(dev) (IS_GEN6(dev) || IS_HASWELL(dev) || \ |
fd7f8cce | 2135 | IS_BROADWELL(dev) || IS_VALLEYVIEW(dev)) |
affa9354 | 2136 | |
17a303ec PZ |
2137 | #define INTEL_PCH_DEVICE_ID_MASK 0xff00 |
2138 | #define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00 | |
2139 | #define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00 | |
2140 | #define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00 | |
2141 | #define INTEL_PCH_LPT_DEVICE_ID_TYPE 0x8c00 | |
2142 | #define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE 0x9c00 | |
2143 | ||
2c1792a1 | 2144 | #define INTEL_PCH_TYPE(dev) (to_i915(dev)->pch_type) |
eb877ebf | 2145 | #define HAS_PCH_LPT(dev) (INTEL_PCH_TYPE(dev) == PCH_LPT) |
cae5852d ZN |
2146 | #define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT) |
2147 | #define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX) | |
40c7ead9 | 2148 | #define HAS_PCH_NOP(dev) (INTEL_PCH_TYPE(dev) == PCH_NOP) |
45e6e3a1 | 2149 | #define HAS_PCH_SPLIT(dev) (INTEL_PCH_TYPE(dev) != PCH_NONE) |
cae5852d | 2150 | |
5fafe292 SJ |
2151 | #define HAS_GMCH_DISPLAY(dev) (INTEL_INFO(dev)->gen < 5 || IS_VALLEYVIEW(dev)) |
2152 | ||
040d2baa BW |
2153 | /* DPF == dynamic parity feature */ |
2154 | #define HAS_L3_DPF(dev) (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) | |
2155 | #define NUM_L3_SLICES(dev) (IS_HSW_GT3(dev) ? 2 : HAS_L3_DPF(dev)) | |
e1ef7cc2 | 2156 | |
c8735b0c BW |
2157 | #define GT_FREQUENCY_MULTIPLIER 50 |
2158 | ||
05394f39 CW |
2159 | #include "i915_trace.h" |
2160 | ||
baa70943 | 2161 | extern const struct drm_ioctl_desc i915_ioctls[]; |
b3a83639 DA |
2162 | extern int i915_max_ioctl; |
2163 | ||
6a9ee8af DA |
2164 | extern int i915_suspend(struct drm_device *dev, pm_message_t state); |
2165 | extern int i915_resume(struct drm_device *dev); | |
7c1c2871 DA |
2166 | extern int i915_master_create(struct drm_device *dev, struct drm_master *master); |
2167 | extern void i915_master_destroy(struct drm_device *dev, struct drm_master *master); | |
2168 | ||
d330a953 JN |
2169 | /* i915_params.c */ |
2170 | struct i915_params { | |
2171 | int modeset; | |
2172 | int panel_ignore_lid; | |
2173 | unsigned int powersave; | |
2174 | int semaphores; | |
2175 | unsigned int lvds_downclock; | |
2176 | int lvds_channel_mode; | |
2177 | int panel_use_ssc; | |
2178 | int vbt_sdvo_panel_type; | |
2179 | int enable_rc6; | |
2180 | int enable_fbc; | |
d330a953 | 2181 | int enable_ppgtt; |
127f1003 | 2182 | int enable_execlists; |
d330a953 JN |
2183 | int enable_psr; |
2184 | unsigned int preliminary_hw_support; | |
2185 | int disable_power_well; | |
2186 | int enable_ips; | |
e5aa6541 | 2187 | int invert_brightness; |
351e3db2 | 2188 | int enable_cmd_parser; |
e5aa6541 DL |
2189 | /* leave bools at the end to not create holes */ |
2190 | bool enable_hangcheck; | |
2191 | bool fastboot; | |
d330a953 JN |
2192 | bool prefault_disable; |
2193 | bool reset; | |
a0bae57f | 2194 | bool disable_display; |
7a10dfa6 | 2195 | bool disable_vtd_wa; |
84c33a64 | 2196 | int use_mmio_flip; |
5978118c | 2197 | bool mmio_debug; |
d330a953 JN |
2198 | }; |
2199 | extern struct i915_params i915 __read_mostly; | |
2200 | ||
1da177e4 | 2201 | /* i915_dma.c */ |
d05c617e | 2202 | void i915_update_dri1_breadcrumb(struct drm_device *dev); |
84b1fd10 | 2203 | extern void i915_kernel_lost_context(struct drm_device * dev); |
22eae947 | 2204 | extern int i915_driver_load(struct drm_device *, unsigned long flags); |
ba8bbcf6 | 2205 | extern int i915_driver_unload(struct drm_device *); |
2885f6ac | 2206 | extern int i915_driver_open(struct drm_device *dev, struct drm_file *file); |
84b1fd10 | 2207 | extern void i915_driver_lastclose(struct drm_device * dev); |
6c340eac | 2208 | extern void i915_driver_preclose(struct drm_device *dev, |
2885f6ac | 2209 | struct drm_file *file); |
673a394b | 2210 | extern void i915_driver_postclose(struct drm_device *dev, |
2885f6ac | 2211 | struct drm_file *file); |
84b1fd10 | 2212 | extern int i915_driver_device_is_agp(struct drm_device * dev); |
c43b5634 | 2213 | #ifdef CONFIG_COMPAT |
0d6aa60b DA |
2214 | extern long i915_compat_ioctl(struct file *filp, unsigned int cmd, |
2215 | unsigned long arg); | |
c43b5634 | 2216 | #endif |
673a394b | 2217 | extern int i915_emit_box(struct drm_device *dev, |
c4e7a414 CW |
2218 | struct drm_clip_rect *box, |
2219 | int DR1, int DR4); | |
8e96d9c4 | 2220 | extern int intel_gpu_reset(struct drm_device *dev); |
d4b8bb2a | 2221 | extern int i915_reset(struct drm_device *dev); |
7648fa99 JB |
2222 | extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv); |
2223 | extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv); | |
2224 | extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv); | |
2225 | extern void i915_update_gfx_val(struct drm_i915_private *dev_priv); | |
650ad970 | 2226 | int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool on); |
7648fa99 | 2227 | |
073f34d9 | 2228 | extern void intel_console_resume(struct work_struct *work); |
af6061af | 2229 | |
1da177e4 | 2230 | /* i915_irq.c */ |
10cd45b6 | 2231 | void i915_queue_hangcheck(struct drm_device *dev); |
58174462 MK |
2232 | __printf(3, 4) |
2233 | void i915_handle_error(struct drm_device *dev, bool wedged, | |
2234 | const char *fmt, ...); | |
1da177e4 | 2235 | |
76c3552f D |
2236 | void gen6_set_pm_mask(struct drm_i915_private *dev_priv, u32 pm_iir, |
2237 | int new_delay); | |
f71d4af4 | 2238 | extern void intel_irq_init(struct drm_device *dev); |
20afbda2 | 2239 | extern void intel_hpd_init(struct drm_device *dev); |
907b28c5 CW |
2240 | |
2241 | extern void intel_uncore_sanitize(struct drm_device *dev); | |
10018603 ID |
2242 | extern void intel_uncore_early_sanitize(struct drm_device *dev, |
2243 | bool restore_forcewake); | |
907b28c5 | 2244 | extern void intel_uncore_init(struct drm_device *dev); |
907b28c5 | 2245 | extern void intel_uncore_check_errors(struct drm_device *dev); |
aec347ab | 2246 | extern void intel_uncore_fini(struct drm_device *dev); |
156c7ca0 | 2247 | extern void intel_uncore_forcewake_reset(struct drm_device *dev, bool restore); |
b1f14ad0 | 2248 | |
7c463586 | 2249 | void |
50227e1c | 2250 | i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe, |
755e9019 | 2251 | u32 status_mask); |
7c463586 KP |
2252 | |
2253 | void | |
50227e1c | 2254 | i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe, |
755e9019 | 2255 | u32 status_mask); |
7c463586 | 2256 | |
f8b79e58 ID |
2257 | void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv); |
2258 | void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv); | |
2259 | ||
673a394b EA |
2260 | /* i915_gem.c */ |
2261 | int i915_gem_init_ioctl(struct drm_device *dev, void *data, | |
2262 | struct drm_file *file_priv); | |
2263 | int i915_gem_create_ioctl(struct drm_device *dev, void *data, | |
2264 | struct drm_file *file_priv); | |
2265 | int i915_gem_pread_ioctl(struct drm_device *dev, void *data, | |
2266 | struct drm_file *file_priv); | |
2267 | int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data, | |
2268 | struct drm_file *file_priv); | |
2269 | int i915_gem_mmap_ioctl(struct drm_device *dev, void *data, | |
2270 | struct drm_file *file_priv); | |
de151cf6 JB |
2271 | int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data, |
2272 | struct drm_file *file_priv); | |
673a394b EA |
2273 | int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data, |
2274 | struct drm_file *file_priv); | |
2275 | int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data, | |
2276 | struct drm_file *file_priv); | |
ba8b7ccb OM |
2277 | void i915_gem_execbuffer_move_to_active(struct list_head *vmas, |
2278 | struct intel_engine_cs *ring); | |
2279 | void i915_gem_execbuffer_retire_commands(struct drm_device *dev, | |
2280 | struct drm_file *file, | |
2281 | struct intel_engine_cs *ring, | |
2282 | struct drm_i915_gem_object *obj); | |
a83014d3 OM |
2283 | int i915_gem_ringbuffer_submission(struct drm_device *dev, |
2284 | struct drm_file *file, | |
2285 | struct intel_engine_cs *ring, | |
2286 | struct intel_context *ctx, | |
2287 | struct drm_i915_gem_execbuffer2 *args, | |
2288 | struct list_head *vmas, | |
2289 | struct drm_i915_gem_object *batch_obj, | |
2290 | u64 exec_start, u32 flags); | |
673a394b EA |
2291 | int i915_gem_execbuffer(struct drm_device *dev, void *data, |
2292 | struct drm_file *file_priv); | |
76446cac JB |
2293 | int i915_gem_execbuffer2(struct drm_device *dev, void *data, |
2294 | struct drm_file *file_priv); | |
673a394b EA |
2295 | int i915_gem_pin_ioctl(struct drm_device *dev, void *data, |
2296 | struct drm_file *file_priv); | |
2297 | int i915_gem_unpin_ioctl(struct drm_device *dev, void *data, | |
2298 | struct drm_file *file_priv); | |
2299 | int i915_gem_busy_ioctl(struct drm_device *dev, void *data, | |
2300 | struct drm_file *file_priv); | |
199adf40 BW |
2301 | int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data, |
2302 | struct drm_file *file); | |
2303 | int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data, | |
2304 | struct drm_file *file); | |
673a394b EA |
2305 | int i915_gem_throttle_ioctl(struct drm_device *dev, void *data, |
2306 | struct drm_file *file_priv); | |
3ef94daa CW |
2307 | int i915_gem_madvise_ioctl(struct drm_device *dev, void *data, |
2308 | struct drm_file *file_priv); | |
673a394b EA |
2309 | int i915_gem_entervt_ioctl(struct drm_device *dev, void *data, |
2310 | struct drm_file *file_priv); | |
2311 | int i915_gem_leavevt_ioctl(struct drm_device *dev, void *data, | |
2312 | struct drm_file *file_priv); | |
2313 | int i915_gem_set_tiling(struct drm_device *dev, void *data, | |
2314 | struct drm_file *file_priv); | |
2315 | int i915_gem_get_tiling(struct drm_device *dev, void *data, | |
2316 | struct drm_file *file_priv); | |
5cc9ed4b CW |
2317 | int i915_gem_init_userptr(struct drm_device *dev); |
2318 | int i915_gem_userptr_ioctl(struct drm_device *dev, void *data, | |
2319 | struct drm_file *file); | |
5a125c3c EA |
2320 | int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data, |
2321 | struct drm_file *file_priv); | |
23ba4fd0 BW |
2322 | int i915_gem_wait_ioctl(struct drm_device *dev, void *data, |
2323 | struct drm_file *file_priv); | |
673a394b | 2324 | void i915_gem_load(struct drm_device *dev); |
42dcedd4 CW |
2325 | void *i915_gem_object_alloc(struct drm_device *dev); |
2326 | void i915_gem_object_free(struct drm_i915_gem_object *obj); | |
37e680a1 CW |
2327 | void i915_gem_object_init(struct drm_i915_gem_object *obj, |
2328 | const struct drm_i915_gem_object_ops *ops); | |
05394f39 CW |
2329 | struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev, |
2330 | size_t size); | |
7e0d96bc BW |
2331 | void i915_init_vm(struct drm_i915_private *dev_priv, |
2332 | struct i915_address_space *vm); | |
673a394b | 2333 | void i915_gem_free_object(struct drm_gem_object *obj); |
2f633156 | 2334 | void i915_gem_vma_destroy(struct i915_vma *vma); |
42dcedd4 | 2335 | |
1ec9e26d DV |
2336 | #define PIN_MAPPABLE 0x1 |
2337 | #define PIN_NONBLOCK 0x2 | |
bf3d149b | 2338 | #define PIN_GLOBAL 0x4 |
d23db88c CW |
2339 | #define PIN_OFFSET_BIAS 0x8 |
2340 | #define PIN_OFFSET_MASK (~4095) | |
2021746e | 2341 | int __must_check i915_gem_object_pin(struct drm_i915_gem_object *obj, |
c37e2204 | 2342 | struct i915_address_space *vm, |
2021746e | 2343 | uint32_t alignment, |
d23db88c | 2344 | uint64_t flags); |
07fe0b12 | 2345 | int __must_check i915_vma_unbind(struct i915_vma *vma); |
dd624afd | 2346 | int i915_gem_object_put_pages(struct drm_i915_gem_object *obj); |
48018a57 | 2347 | void i915_gem_release_all_mmaps(struct drm_i915_private *dev_priv); |
05394f39 | 2348 | void i915_gem_release_mmap(struct drm_i915_gem_object *obj); |
673a394b | 2349 | void i915_gem_lastclose(struct drm_device *dev); |
f787a5f5 | 2350 | |
4c914c0c BV |
2351 | int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj, |
2352 | int *needs_clflush); | |
2353 | ||
37e680a1 | 2354 | int __must_check i915_gem_object_get_pages(struct drm_i915_gem_object *obj); |
9da3da66 CW |
2355 | static inline struct page *i915_gem_object_get_page(struct drm_i915_gem_object *obj, int n) |
2356 | { | |
67d5a50c ID |
2357 | struct sg_page_iter sg_iter; |
2358 | ||
2359 | for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, n) | |
2db76d7c | 2360 | return sg_page_iter_page(&sg_iter); |
67d5a50c ID |
2361 | |
2362 | return NULL; | |
9da3da66 | 2363 | } |
a5570178 CW |
2364 | static inline void i915_gem_object_pin_pages(struct drm_i915_gem_object *obj) |
2365 | { | |
2366 | BUG_ON(obj->pages == NULL); | |
2367 | obj->pages_pin_count++; | |
2368 | } | |
2369 | static inline void i915_gem_object_unpin_pages(struct drm_i915_gem_object *obj) | |
2370 | { | |
2371 | BUG_ON(obj->pages_pin_count == 0); | |
2372 | obj->pages_pin_count--; | |
2373 | } | |
2374 | ||
54cf91dc | 2375 | int __must_check i915_mutex_lock_interruptible(struct drm_device *dev); |
2911a35b | 2376 | int i915_gem_object_sync(struct drm_i915_gem_object *obj, |
a4872ba6 | 2377 | struct intel_engine_cs *to); |
e2d05a8b | 2378 | void i915_vma_move_to_active(struct i915_vma *vma, |
a4872ba6 | 2379 | struct intel_engine_cs *ring); |
ff72145b DA |
2380 | int i915_gem_dumb_create(struct drm_file *file_priv, |
2381 | struct drm_device *dev, | |
2382 | struct drm_mode_create_dumb *args); | |
2383 | int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev, | |
2384 | uint32_t handle, uint64_t *offset); | |
f787a5f5 CW |
2385 | /** |
2386 | * Returns true if seq1 is later than seq2. | |
2387 | */ | |
2388 | static inline bool | |
2389 | i915_seqno_passed(uint32_t seq1, uint32_t seq2) | |
2390 | { | |
2391 | return (int32_t)(seq1 - seq2) >= 0; | |
2392 | } | |
2393 | ||
fca26bb4 MK |
2394 | int __must_check i915_gem_get_seqno(struct drm_device *dev, u32 *seqno); |
2395 | int __must_check i915_gem_set_seqno(struct drm_device *dev, u32 seqno); | |
06d98131 | 2396 | int __must_check i915_gem_object_get_fence(struct drm_i915_gem_object *obj); |
d9e86c0e | 2397 | int __must_check i915_gem_object_put_fence(struct drm_i915_gem_object *obj); |
2021746e | 2398 | |
d8ffa60b DV |
2399 | bool i915_gem_object_pin_fence(struct drm_i915_gem_object *obj); |
2400 | void i915_gem_object_unpin_fence(struct drm_i915_gem_object *obj); | |
1690e1eb | 2401 | |
8d9fc7fd | 2402 | struct drm_i915_gem_request * |
a4872ba6 | 2403 | i915_gem_find_active_request(struct intel_engine_cs *ring); |
8d9fc7fd | 2404 | |
b29c19b6 | 2405 | bool i915_gem_retire_requests(struct drm_device *dev); |
a4872ba6 | 2406 | void i915_gem_retire_requests_ring(struct intel_engine_cs *ring); |
33196ded | 2407 | int __must_check i915_gem_check_wedge(struct i915_gpu_error *error, |
d6b2c790 | 2408 | bool interruptible); |
84c33a64 SG |
2409 | int __must_check i915_gem_check_olr(struct intel_engine_cs *ring, u32 seqno); |
2410 | ||
1f83fee0 DV |
2411 | static inline bool i915_reset_in_progress(struct i915_gpu_error *error) |
2412 | { | |
2413 | return unlikely(atomic_read(&error->reset_counter) | |
2ac0f450 | 2414 | & (I915_RESET_IN_PROGRESS_FLAG | I915_WEDGED)); |
1f83fee0 DV |
2415 | } |
2416 | ||
2417 | static inline bool i915_terminally_wedged(struct i915_gpu_error *error) | |
2418 | { | |
2ac0f450 MK |
2419 | return atomic_read(&error->reset_counter) & I915_WEDGED; |
2420 | } | |
2421 | ||
2422 | static inline u32 i915_reset_count(struct i915_gpu_error *error) | |
2423 | { | |
2424 | return ((atomic_read(&error->reset_counter) & ~I915_WEDGED) + 1) / 2; | |
1f83fee0 | 2425 | } |
a71d8d94 | 2426 | |
88b4aa87 MK |
2427 | static inline bool i915_stop_ring_allow_ban(struct drm_i915_private *dev_priv) |
2428 | { | |
2429 | return dev_priv->gpu_error.stop_rings == 0 || | |
2430 | dev_priv->gpu_error.stop_rings & I915_STOP_RING_ALLOW_BAN; | |
2431 | } | |
2432 | ||
2433 | static inline bool i915_stop_ring_allow_warn(struct drm_i915_private *dev_priv) | |
2434 | { | |
2435 | return dev_priv->gpu_error.stop_rings == 0 || | |
2436 | dev_priv->gpu_error.stop_rings & I915_STOP_RING_ALLOW_WARN; | |
2437 | } | |
2438 | ||
069efc1d | 2439 | void i915_gem_reset(struct drm_device *dev); |
000433b6 | 2440 | bool i915_gem_clflush_object(struct drm_i915_gem_object *obj, bool force); |
a8198eea | 2441 | int __must_check i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj); |
1070a42b | 2442 | int __must_check i915_gem_init(struct drm_device *dev); |
a83014d3 | 2443 | int i915_gem_init_rings(struct drm_device *dev); |
f691e2f4 | 2444 | int __must_check i915_gem_init_hw(struct drm_device *dev); |
a4872ba6 | 2445 | int i915_gem_l3_remap(struct intel_engine_cs *ring, int slice); |
f691e2f4 | 2446 | void i915_gem_init_swizzling(struct drm_device *dev); |
79e53945 | 2447 | void i915_gem_cleanup_ringbuffer(struct drm_device *dev); |
b2da9fe5 | 2448 | int __must_check i915_gpu_idle(struct drm_device *dev); |
45c5f202 | 2449 | int __must_check i915_gem_suspend(struct drm_device *dev); |
a4872ba6 | 2450 | int __i915_add_request(struct intel_engine_cs *ring, |
0025c077 | 2451 | struct drm_file *file, |
7d736f4f | 2452 | struct drm_i915_gem_object *batch_obj, |
0025c077 MK |
2453 | u32 *seqno); |
2454 | #define i915_add_request(ring, seqno) \ | |
854c94a7 | 2455 | __i915_add_request(ring, NULL, NULL, seqno) |
a4872ba6 | 2456 | int __must_check i915_wait_seqno(struct intel_engine_cs *ring, |
199b2bc2 | 2457 | uint32_t seqno); |
de151cf6 | 2458 | int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf); |
2021746e CW |
2459 | int __must_check |
2460 | i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, | |
2461 | bool write); | |
2462 | int __must_check | |
dabdfe02 CW |
2463 | i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write); |
2464 | int __must_check | |
2da3b9b9 CW |
2465 | i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj, |
2466 | u32 alignment, | |
a4872ba6 | 2467 | struct intel_engine_cs *pipelined); |
cc98b413 | 2468 | void i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object *obj); |
00731155 | 2469 | int i915_gem_object_attach_phys(struct drm_i915_gem_object *obj, |
6eeefaf3 | 2470 | int align); |
b29c19b6 | 2471 | int i915_gem_open(struct drm_device *dev, struct drm_file *file); |
05394f39 | 2472 | void i915_gem_release(struct drm_device *dev, struct drm_file *file); |
673a394b | 2473 | |
0fa87796 ID |
2474 | uint32_t |
2475 | i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode); | |
467cffba | 2476 | uint32_t |
d865110c ID |
2477 | i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size, |
2478 | int tiling_mode, bool fenced); | |
467cffba | 2479 | |
e4ffd173 CW |
2480 | int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj, |
2481 | enum i915_cache_level cache_level); | |
2482 | ||
1286ff73 DV |
2483 | struct drm_gem_object *i915_gem_prime_import(struct drm_device *dev, |
2484 | struct dma_buf *dma_buf); | |
2485 | ||
2486 | struct dma_buf *i915_gem_prime_export(struct drm_device *dev, | |
2487 | struct drm_gem_object *gem_obj, int flags); | |
2488 | ||
19b2dbde CW |
2489 | void i915_gem_restore_fences(struct drm_device *dev); |
2490 | ||
a70a3148 BW |
2491 | unsigned long i915_gem_obj_offset(struct drm_i915_gem_object *o, |
2492 | struct i915_address_space *vm); | |
2493 | bool i915_gem_obj_bound_any(struct drm_i915_gem_object *o); | |
2494 | bool i915_gem_obj_bound(struct drm_i915_gem_object *o, | |
2495 | struct i915_address_space *vm); | |
2496 | unsigned long i915_gem_obj_size(struct drm_i915_gem_object *o, | |
2497 | struct i915_address_space *vm); | |
2498 | struct i915_vma *i915_gem_obj_to_vma(struct drm_i915_gem_object *obj, | |
2499 | struct i915_address_space *vm); | |
accfef2e BW |
2500 | struct i915_vma * |
2501 | i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object *obj, | |
2502 | struct i915_address_space *vm); | |
5c2abbea BW |
2503 | |
2504 | struct i915_vma *i915_gem_obj_to_ggtt(struct drm_i915_gem_object *obj); | |
d7f46fc4 BW |
2505 | static inline bool i915_gem_obj_is_pinned(struct drm_i915_gem_object *obj) { |
2506 | struct i915_vma *vma; | |
2507 | list_for_each_entry(vma, &obj->vma_list, vma_link) | |
2508 | if (vma->pin_count > 0) | |
2509 | return true; | |
2510 | return false; | |
2511 | } | |
5c2abbea | 2512 | |
a70a3148 | 2513 | /* Some GGTT VM helpers */ |
5dc383b0 | 2514 | #define i915_obj_to_ggtt(obj) \ |
a70a3148 BW |
2515 | (&((struct drm_i915_private *)(obj)->base.dev->dev_private)->gtt.base) |
2516 | static inline bool i915_is_ggtt(struct i915_address_space *vm) | |
2517 | { | |
2518 | struct i915_address_space *ggtt = | |
2519 | &((struct drm_i915_private *)(vm)->dev->dev_private)->gtt.base; | |
2520 | return vm == ggtt; | |
2521 | } | |
2522 | ||
841cd773 DV |
2523 | static inline struct i915_hw_ppgtt * |
2524 | i915_vm_to_ppgtt(struct i915_address_space *vm) | |
2525 | { | |
2526 | WARN_ON(i915_is_ggtt(vm)); | |
2527 | ||
2528 | return container_of(vm, struct i915_hw_ppgtt, base); | |
2529 | } | |
2530 | ||
2531 | ||
a70a3148 BW |
2532 | static inline bool i915_gem_obj_ggtt_bound(struct drm_i915_gem_object *obj) |
2533 | { | |
5dc383b0 | 2534 | return i915_gem_obj_bound(obj, i915_obj_to_ggtt(obj)); |
a70a3148 BW |
2535 | } |
2536 | ||
2537 | static inline unsigned long | |
2538 | i915_gem_obj_ggtt_offset(struct drm_i915_gem_object *obj) | |
2539 | { | |
5dc383b0 | 2540 | return i915_gem_obj_offset(obj, i915_obj_to_ggtt(obj)); |
a70a3148 BW |
2541 | } |
2542 | ||
2543 | static inline unsigned long | |
2544 | i915_gem_obj_ggtt_size(struct drm_i915_gem_object *obj) | |
2545 | { | |
5dc383b0 | 2546 | return i915_gem_obj_size(obj, i915_obj_to_ggtt(obj)); |
a70a3148 | 2547 | } |
c37e2204 BW |
2548 | |
2549 | static inline int __must_check | |
2550 | i915_gem_obj_ggtt_pin(struct drm_i915_gem_object *obj, | |
2551 | uint32_t alignment, | |
1ec9e26d | 2552 | unsigned flags) |
c37e2204 | 2553 | { |
5dc383b0 DV |
2554 | return i915_gem_object_pin(obj, i915_obj_to_ggtt(obj), |
2555 | alignment, flags | PIN_GLOBAL); | |
c37e2204 | 2556 | } |
a70a3148 | 2557 | |
b287110e DV |
2558 | static inline int |
2559 | i915_gem_object_ggtt_unbind(struct drm_i915_gem_object *obj) | |
2560 | { | |
2561 | return i915_vma_unbind(i915_gem_obj_to_ggtt(obj)); | |
2562 | } | |
2563 | ||
2564 | void i915_gem_object_ggtt_unpin(struct drm_i915_gem_object *obj); | |
2565 | ||
254f965c | 2566 | /* i915_gem_context.c */ |
8245be31 | 2567 | int __must_check i915_gem_context_init(struct drm_device *dev); |
254f965c | 2568 | void i915_gem_context_fini(struct drm_device *dev); |
acce9ffa | 2569 | void i915_gem_context_reset(struct drm_device *dev); |
e422b888 | 2570 | int i915_gem_context_open(struct drm_device *dev, struct drm_file *file); |
2fa48d8d | 2571 | int i915_gem_context_enable(struct drm_i915_private *dev_priv); |
254f965c | 2572 | void i915_gem_context_close(struct drm_device *dev, struct drm_file *file); |
a4872ba6 | 2573 | int i915_switch_context(struct intel_engine_cs *ring, |
273497e5 OM |
2574 | struct intel_context *to); |
2575 | struct intel_context * | |
41bde553 | 2576 | i915_gem_context_get(struct drm_i915_file_private *file_priv, u32 id); |
dce3271b | 2577 | void i915_gem_context_free(struct kref *ctx_ref); |
8c857917 OM |
2578 | struct drm_i915_gem_object * |
2579 | i915_gem_alloc_context_obj(struct drm_device *dev, size_t size); | |
273497e5 | 2580 | static inline void i915_gem_context_reference(struct intel_context *ctx) |
dce3271b | 2581 | { |
691e6415 | 2582 | kref_get(&ctx->ref); |
dce3271b MK |
2583 | } |
2584 | ||
273497e5 | 2585 | static inline void i915_gem_context_unreference(struct intel_context *ctx) |
dce3271b | 2586 | { |
691e6415 | 2587 | kref_put(&ctx->ref, i915_gem_context_free); |
dce3271b MK |
2588 | } |
2589 | ||
273497e5 | 2590 | static inline bool i915_gem_context_is_default(const struct intel_context *c) |
3fac8978 | 2591 | { |
821d66dd | 2592 | return c->user_handle == DEFAULT_CONTEXT_HANDLE; |
3fac8978 MK |
2593 | } |
2594 | ||
84624813 BW |
2595 | int i915_gem_context_create_ioctl(struct drm_device *dev, void *data, |
2596 | struct drm_file *file); | |
2597 | int i915_gem_context_destroy_ioctl(struct drm_device *dev, void *data, | |
2598 | struct drm_file *file); | |
1286ff73 | 2599 | |
9d0a6fa6 | 2600 | /* i915_gem_render_state.c */ |
a4872ba6 | 2601 | int i915_gem_render_state_init(struct intel_engine_cs *ring); |
679845ed BW |
2602 | /* i915_gem_evict.c */ |
2603 | int __must_check i915_gem_evict_something(struct drm_device *dev, | |
2604 | struct i915_address_space *vm, | |
2605 | int min_size, | |
2606 | unsigned alignment, | |
2607 | unsigned cache_level, | |
d23db88c CW |
2608 | unsigned long start, |
2609 | unsigned long end, | |
1ec9e26d | 2610 | unsigned flags); |
679845ed BW |
2611 | int i915_gem_evict_vm(struct i915_address_space *vm, bool do_idle); |
2612 | int i915_gem_evict_everything(struct drm_device *dev); | |
1d2a314c | 2613 | |
0260c420 | 2614 | /* belongs in i915_gem_gtt.h */ |
d09105c6 | 2615 | static inline void i915_gem_chipset_flush(struct drm_device *dev) |
e76e9aeb BW |
2616 | { |
2617 | if (INTEL_INFO(dev)->gen < 6) | |
2618 | intel_gtt_chipset_flush(); | |
2619 | } | |
246cbfb5 | 2620 | |
9797fbfb CW |
2621 | /* i915_gem_stolen.c */ |
2622 | int i915_gem_init_stolen(struct drm_device *dev); | |
5e59f717 | 2623 | int i915_gem_stolen_setup_compression(struct drm_device *dev, int size, int fb_cpp); |
11be49eb | 2624 | void i915_gem_stolen_cleanup_compression(struct drm_device *dev); |
9797fbfb | 2625 | void i915_gem_cleanup_stolen(struct drm_device *dev); |
0104fdbb CW |
2626 | struct drm_i915_gem_object * |
2627 | i915_gem_object_create_stolen(struct drm_device *dev, u32 size); | |
866d12b4 CW |
2628 | struct drm_i915_gem_object * |
2629 | i915_gem_object_create_stolen_for_preallocated(struct drm_device *dev, | |
2630 | u32 stolen_offset, | |
2631 | u32 gtt_offset, | |
2632 | u32 size); | |
9797fbfb | 2633 | |
673a394b | 2634 | /* i915_gem_tiling.c */ |
2c1792a1 | 2635 | static inline bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj) |
e9b73c67 | 2636 | { |
50227e1c | 2637 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
e9b73c67 CW |
2638 | |
2639 | return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 && | |
2640 | obj->tiling_mode != I915_TILING_NONE; | |
2641 | } | |
2642 | ||
673a394b | 2643 | void i915_gem_detect_bit_6_swizzle(struct drm_device *dev); |
05394f39 CW |
2644 | void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj); |
2645 | void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj); | |
673a394b EA |
2646 | |
2647 | /* i915_gem_debug.c */ | |
23bc5982 CW |
2648 | #if WATCH_LISTS |
2649 | int i915_verify_lists(struct drm_device *dev); | |
673a394b | 2650 | #else |
23bc5982 | 2651 | #define i915_verify_lists(dev) 0 |
673a394b | 2652 | #endif |
1da177e4 | 2653 | |
2017263e | 2654 | /* i915_debugfs.c */ |
27c202ad BG |
2655 | int i915_debugfs_init(struct drm_minor *minor); |
2656 | void i915_debugfs_cleanup(struct drm_minor *minor); | |
f8c168fa | 2657 | #ifdef CONFIG_DEBUG_FS |
07144428 DL |
2658 | void intel_display_crc_init(struct drm_device *dev); |
2659 | #else | |
f8c168fa | 2660 | static inline void intel_display_crc_init(struct drm_device *dev) {} |
07144428 | 2661 | #endif |
84734a04 MK |
2662 | |
2663 | /* i915_gpu_error.c */ | |
edc3d884 MK |
2664 | __printf(2, 3) |
2665 | void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...); | |
fc16b48b MK |
2666 | int i915_error_state_to_str(struct drm_i915_error_state_buf *estr, |
2667 | const struct i915_error_state_file_priv *error); | |
4dc955f7 MK |
2668 | int i915_error_state_buf_init(struct drm_i915_error_state_buf *eb, |
2669 | size_t count, loff_t pos); | |
2670 | static inline void i915_error_state_buf_release( | |
2671 | struct drm_i915_error_state_buf *eb) | |
2672 | { | |
2673 | kfree(eb->buf); | |
2674 | } | |
58174462 MK |
2675 | void i915_capture_error_state(struct drm_device *dev, bool wedge, |
2676 | const char *error_msg); | |
84734a04 MK |
2677 | void i915_error_state_get(struct drm_device *dev, |
2678 | struct i915_error_state_file_priv *error_priv); | |
2679 | void i915_error_state_put(struct i915_error_state_file_priv *error_priv); | |
2680 | void i915_destroy_error_state(struct drm_device *dev); | |
2681 | ||
2682 | void i915_get_extra_instdone(struct drm_device *dev, uint32_t *instdone); | |
2683 | const char *i915_cache_level_str(int type); | |
2017263e | 2684 | |
351e3db2 | 2685 | /* i915_cmd_parser.c */ |
d728c8ef | 2686 | int i915_cmd_parser_get_version(void); |
a4872ba6 OM |
2687 | int i915_cmd_parser_init_ring(struct intel_engine_cs *ring); |
2688 | void i915_cmd_parser_fini_ring(struct intel_engine_cs *ring); | |
2689 | bool i915_needs_cmd_parser(struct intel_engine_cs *ring); | |
2690 | int i915_parse_cmds(struct intel_engine_cs *ring, | |
351e3db2 BV |
2691 | struct drm_i915_gem_object *batch_obj, |
2692 | u32 batch_start_offset, | |
2693 | bool is_master); | |
2694 | ||
317c35d1 JB |
2695 | /* i915_suspend.c */ |
2696 | extern int i915_save_state(struct drm_device *dev); | |
2697 | extern int i915_restore_state(struct drm_device *dev); | |
0a3e67a4 | 2698 | |
d8157a36 DV |
2699 | /* i915_ums.c */ |
2700 | void i915_save_display_reg(struct drm_device *dev); | |
2701 | void i915_restore_display_reg(struct drm_device *dev); | |
317c35d1 | 2702 | |
0136db58 BW |
2703 | /* i915_sysfs.c */ |
2704 | void i915_setup_sysfs(struct drm_device *dev_priv); | |
2705 | void i915_teardown_sysfs(struct drm_device *dev_priv); | |
2706 | ||
f899fc64 CW |
2707 | /* intel_i2c.c */ |
2708 | extern int intel_setup_gmbus(struct drm_device *dev); | |
2709 | extern void intel_teardown_gmbus(struct drm_device *dev); | |
8f375e10 | 2710 | static inline bool intel_gmbus_is_port_valid(unsigned port) |
3bd7d909 | 2711 | { |
2ed06c93 | 2712 | return (port >= GMBUS_PORT_SSC && port <= GMBUS_PORT_DPD); |
3bd7d909 DK |
2713 | } |
2714 | ||
2715 | extern struct i2c_adapter *intel_gmbus_get_adapter( | |
2716 | struct drm_i915_private *dev_priv, unsigned port); | |
e957d772 CW |
2717 | extern void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed); |
2718 | extern void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit); | |
8f375e10 | 2719 | static inline bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter) |
b8232e90 CW |
2720 | { |
2721 | return container_of(adapter, struct intel_gmbus, adapter)->force_bit; | |
2722 | } | |
f899fc64 CW |
2723 | extern void intel_i2c_reset(struct drm_device *dev); |
2724 | ||
3b617967 | 2725 | /* intel_opregion.c */ |
9c4b0a68 | 2726 | struct intel_encoder; |
44834a67 | 2727 | #ifdef CONFIG_ACPI |
27d50c82 | 2728 | extern int intel_opregion_setup(struct drm_device *dev); |
44834a67 CW |
2729 | extern void intel_opregion_init(struct drm_device *dev); |
2730 | extern void intel_opregion_fini(struct drm_device *dev); | |
3b617967 | 2731 | extern void intel_opregion_asle_intr(struct drm_device *dev); |
9c4b0a68 JN |
2732 | extern int intel_opregion_notify_encoder(struct intel_encoder *intel_encoder, |
2733 | bool enable); | |
ecbc5cf3 JN |
2734 | extern int intel_opregion_notify_adapter(struct drm_device *dev, |
2735 | pci_power_t state); | |
65e082c9 | 2736 | #else |
27d50c82 | 2737 | static inline int intel_opregion_setup(struct drm_device *dev) { return 0; } |
44834a67 CW |
2738 | static inline void intel_opregion_init(struct drm_device *dev) { return; } |
2739 | static inline void intel_opregion_fini(struct drm_device *dev) { return; } | |
3b617967 | 2740 | static inline void intel_opregion_asle_intr(struct drm_device *dev) { return; } |
9c4b0a68 JN |
2741 | static inline int |
2742 | intel_opregion_notify_encoder(struct intel_encoder *intel_encoder, bool enable) | |
2743 | { | |
2744 | return 0; | |
2745 | } | |
ecbc5cf3 JN |
2746 | static inline int |
2747 | intel_opregion_notify_adapter(struct drm_device *dev, pci_power_t state) | |
2748 | { | |
2749 | return 0; | |
2750 | } | |
65e082c9 | 2751 | #endif |
8ee1c3db | 2752 | |
723bfd70 JB |
2753 | /* intel_acpi.c */ |
2754 | #ifdef CONFIG_ACPI | |
2755 | extern void intel_register_dsm_handler(void); | |
2756 | extern void intel_unregister_dsm_handler(void); | |
2757 | #else | |
2758 | static inline void intel_register_dsm_handler(void) { return; } | |
2759 | static inline void intel_unregister_dsm_handler(void) { return; } | |
2760 | #endif /* CONFIG_ACPI */ | |
2761 | ||
79e53945 | 2762 | /* modesetting */ |
f817586c | 2763 | extern void intel_modeset_init_hw(struct drm_device *dev); |
7d708ee4 | 2764 | extern void intel_modeset_suspend_hw(struct drm_device *dev); |
79e53945 | 2765 | extern void intel_modeset_init(struct drm_device *dev); |
2c7111db | 2766 | extern void intel_modeset_gem_init(struct drm_device *dev); |
79e53945 | 2767 | extern void intel_modeset_cleanup(struct drm_device *dev); |
4932e2c3 | 2768 | extern void intel_connector_unregister(struct intel_connector *); |
28d52043 | 2769 | extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state); |
45e2b5f6 DV |
2770 | extern void intel_modeset_setup_hw_state(struct drm_device *dev, |
2771 | bool force_restore); | |
44cec740 | 2772 | extern void i915_redisable_vga(struct drm_device *dev); |
04098753 | 2773 | extern void i915_redisable_vga_power_on(struct drm_device *dev); |
ee5382ae | 2774 | extern bool intel_fbc_enabled(struct drm_device *dev); |
43a9539f | 2775 | extern void intel_disable_fbc(struct drm_device *dev); |
7648fa99 | 2776 | extern bool ironlake_set_drps(struct drm_device *dev, u8 val); |
dde86e2d | 2777 | extern void intel_init_pch_refclk(struct drm_device *dev); |
3b8d8d91 | 2778 | extern void gen6_set_rps(struct drm_device *dev, u8 val); |
0a073b84 | 2779 | extern void valleyview_set_rps(struct drm_device *dev, u8 val); |
5209b1f4 ID |
2780 | extern void intel_set_memory_cxsr(struct drm_i915_private *dev_priv, |
2781 | bool enable); | |
0206e353 AJ |
2782 | extern void intel_detect_pch(struct drm_device *dev); |
2783 | extern int intel_trans_dp_port_sel(struct drm_crtc *crtc); | |
0136db58 | 2784 | extern int intel_enable_rc6(const struct drm_device *dev); |
3bad0781 | 2785 | |
2911a35b | 2786 | extern bool i915_semaphore_is_enabled(struct drm_device *dev); |
c0c7babc BW |
2787 | int i915_reg_read_ioctl(struct drm_device *dev, void *data, |
2788 | struct drm_file *file); | |
b6359918 MK |
2789 | int i915_get_reset_stats_ioctl(struct drm_device *dev, void *data, |
2790 | struct drm_file *file); | |
575155a9 | 2791 | |
84c33a64 SG |
2792 | void intel_notify_mmio_flip(struct intel_engine_cs *ring); |
2793 | ||
6ef3d427 CW |
2794 | /* overlay */ |
2795 | extern struct intel_overlay_error_state *intel_overlay_capture_error_state(struct drm_device *dev); | |
edc3d884 MK |
2796 | extern void intel_overlay_print_error_state(struct drm_i915_error_state_buf *e, |
2797 | struct intel_overlay_error_state *error); | |
c4a1d9e4 CW |
2798 | |
2799 | extern struct intel_display_error_state *intel_display_capture_error_state(struct drm_device *dev); | |
edc3d884 | 2800 | extern void intel_display_print_error_state(struct drm_i915_error_state_buf *e, |
c4a1d9e4 CW |
2801 | struct drm_device *dev, |
2802 | struct intel_display_error_state *error); | |
6ef3d427 | 2803 | |
b7287d80 BW |
2804 | /* On SNB platform, before reading ring registers forcewake bit |
2805 | * must be set to prevent GT core from power down and stale values being | |
2806 | * returned. | |
2807 | */ | |
c8d9a590 D |
2808 | void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv, int fw_engine); |
2809 | void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv, int fw_engine); | |
e998c40f | 2810 | void assert_force_wake_inactive(struct drm_i915_private *dev_priv); |
b7287d80 | 2811 | |
42c0526c BW |
2812 | int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u8 mbox, u32 *val); |
2813 | int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32 val); | |
59de0813 JN |
2814 | |
2815 | /* intel_sideband.c */ | |
64936258 JN |
2816 | u32 vlv_punit_read(struct drm_i915_private *dev_priv, u8 addr); |
2817 | void vlv_punit_write(struct drm_i915_private *dev_priv, u8 addr, u32 val); | |
2818 | u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr); | |
e9f882a3 JN |
2819 | u32 vlv_gpio_nc_read(struct drm_i915_private *dev_priv, u32 reg); |
2820 | void vlv_gpio_nc_write(struct drm_i915_private *dev_priv, u32 reg, u32 val); | |
2821 | u32 vlv_cck_read(struct drm_i915_private *dev_priv, u32 reg); | |
2822 | void vlv_cck_write(struct drm_i915_private *dev_priv, u32 reg, u32 val); | |
2823 | u32 vlv_ccu_read(struct drm_i915_private *dev_priv, u32 reg); | |
2824 | void vlv_ccu_write(struct drm_i915_private *dev_priv, u32 reg, u32 val); | |
f3419158 JB |
2825 | u32 vlv_bunit_read(struct drm_i915_private *dev_priv, u32 reg); |
2826 | void vlv_bunit_write(struct drm_i915_private *dev_priv, u32 reg, u32 val); | |
e9f882a3 JN |
2827 | u32 vlv_gps_core_read(struct drm_i915_private *dev_priv, u32 reg); |
2828 | void vlv_gps_core_write(struct drm_i915_private *dev_priv, u32 reg, u32 val); | |
5e69f97f CML |
2829 | u32 vlv_dpio_read(struct drm_i915_private *dev_priv, enum pipe pipe, int reg); |
2830 | void vlv_dpio_write(struct drm_i915_private *dev_priv, enum pipe pipe, int reg, u32 val); | |
59de0813 JN |
2831 | u32 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg, |
2832 | enum intel_sbi_destination destination); | |
2833 | void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value, | |
2834 | enum intel_sbi_destination destination); | |
e9fe51c6 SK |
2835 | u32 vlv_flisdsi_read(struct drm_i915_private *dev_priv, u32 reg); |
2836 | void vlv_flisdsi_write(struct drm_i915_private *dev_priv, u32 reg, u32 val); | |
0a073b84 | 2837 | |
2ec3815f VS |
2838 | int vlv_gpu_freq(struct drm_i915_private *dev_priv, int val); |
2839 | int vlv_freq_opcode(struct drm_i915_private *dev_priv, int val); | |
42c0526c | 2840 | |
c8d9a590 D |
2841 | #define FORCEWAKE_RENDER (1 << 0) |
2842 | #define FORCEWAKE_MEDIA (1 << 1) | |
2843 | #define FORCEWAKE_ALL (FORCEWAKE_RENDER | FORCEWAKE_MEDIA) | |
2844 | ||
2845 | ||
0b274481 BW |
2846 | #define I915_READ8(reg) dev_priv->uncore.funcs.mmio_readb(dev_priv, (reg), true) |
2847 | #define I915_WRITE8(reg, val) dev_priv->uncore.funcs.mmio_writeb(dev_priv, (reg), (val), true) | |
2848 | ||
2849 | #define I915_READ16(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), true) | |
2850 | #define I915_WRITE16(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), true) | |
2851 | #define I915_READ16_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), false) | |
2852 | #define I915_WRITE16_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), false) | |
2853 | ||
2854 | #define I915_READ(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), true) | |
2855 | #define I915_WRITE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), true) | |
2856 | #define I915_READ_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), false) | |
2857 | #define I915_WRITE_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), false) | |
2858 | ||
698b3135 CW |
2859 | /* Be very careful with read/write 64-bit values. On 32-bit machines, they |
2860 | * will be implemented using 2 32-bit writes in an arbitrary order with | |
2861 | * an arbitrary delay between them. This can cause the hardware to | |
2862 | * act upon the intermediate value, possibly leading to corruption and | |
2863 | * machine death. You have been warned. | |
2864 | */ | |
0b274481 BW |
2865 | #define I915_WRITE64(reg, val) dev_priv->uncore.funcs.mmio_writeq(dev_priv, (reg), (val), true) |
2866 | #define I915_READ64(reg) dev_priv->uncore.funcs.mmio_readq(dev_priv, (reg), true) | |
cae5852d | 2867 | |
50877445 CW |
2868 | #define I915_READ64_2x32(lower_reg, upper_reg) ({ \ |
2869 | u32 upper = I915_READ(upper_reg); \ | |
2870 | u32 lower = I915_READ(lower_reg); \ | |
2871 | u32 tmp = I915_READ(upper_reg); \ | |
2872 | if (upper != tmp) { \ | |
2873 | upper = tmp; \ | |
2874 | lower = I915_READ(lower_reg); \ | |
2875 | WARN_ON(I915_READ(upper_reg) != upper); \ | |
2876 | } \ | |
2877 | (u64)upper << 32 | lower; }) | |
2878 | ||
cae5852d ZN |
2879 | #define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg) |
2880 | #define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg) | |
2881 | ||
55bc60db VS |
2882 | /* "Broadcast RGB" property */ |
2883 | #define INTEL_BROADCAST_RGB_AUTO 0 | |
2884 | #define INTEL_BROADCAST_RGB_FULL 1 | |
2885 | #define INTEL_BROADCAST_RGB_LIMITED 2 | |
ba4f01a3 | 2886 | |
766aa1c4 VS |
2887 | static inline uint32_t i915_vgacntrl_reg(struct drm_device *dev) |
2888 | { | |
92e23b99 | 2889 | if (IS_VALLEYVIEW(dev)) |
766aa1c4 | 2890 | return VLV_VGACNTRL; |
92e23b99 SJ |
2891 | else if (INTEL_INFO(dev)->gen >= 5) |
2892 | return CPU_VGACNTRL; | |
766aa1c4 VS |
2893 | else |
2894 | return VGACNTRL; | |
2895 | } | |
2896 | ||
2bb4629a VS |
2897 | static inline void __user *to_user_ptr(u64 address) |
2898 | { | |
2899 | return (void __user *)(uintptr_t)address; | |
2900 | } | |
2901 | ||
df97729f ID |
2902 | static inline unsigned long msecs_to_jiffies_timeout(const unsigned int m) |
2903 | { | |
2904 | unsigned long j = msecs_to_jiffies(m); | |
2905 | ||
2906 | return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1); | |
2907 | } | |
2908 | ||
2909 | static inline unsigned long | |
2910 | timespec_to_jiffies_timeout(const struct timespec *value) | |
2911 | { | |
2912 | unsigned long j = timespec_to_jiffies(value); | |
2913 | ||
2914 | return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1); | |
2915 | } | |
2916 | ||
dce56b3c PZ |
2917 | /* |
2918 | * If you need to wait X milliseconds between events A and B, but event B | |
2919 | * doesn't happen exactly after event A, you record the timestamp (jiffies) of | |
2920 | * when event A happened, then just before event B you call this function and | |
2921 | * pass the timestamp as the first argument, and X as the second argument. | |
2922 | */ | |
2923 | static inline void | |
2924 | wait_remaining_ms_from_jiffies(unsigned long timestamp_jiffies, int to_wait_ms) | |
2925 | { | |
ec5e0cfb | 2926 | unsigned long target_jiffies, tmp_jiffies, remaining_jiffies; |
dce56b3c PZ |
2927 | |
2928 | /* | |
2929 | * Don't re-read the value of "jiffies" every time since it may change | |
2930 | * behind our back and break the math. | |
2931 | */ | |
2932 | tmp_jiffies = jiffies; | |
2933 | target_jiffies = timestamp_jiffies + | |
2934 | msecs_to_jiffies_timeout(to_wait_ms); | |
2935 | ||
2936 | if (time_after(target_jiffies, tmp_jiffies)) { | |
ec5e0cfb ID |
2937 | remaining_jiffies = target_jiffies - tmp_jiffies; |
2938 | while (remaining_jiffies) | |
2939 | remaining_jiffies = | |
2940 | schedule_timeout_uninterruptible(remaining_jiffies); | |
dce56b3c PZ |
2941 | } |
2942 | } | |
2943 | ||
1da177e4 | 2944 | #endif |