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1da177e4 LT |
1 | /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*- |
2 | */ | |
0d6aa60b | 3 | /* |
bc54fd1a | 4 | * |
1da177e4 LT |
5 | * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. |
6 | * All Rights Reserved. | |
bc54fd1a DA |
7 | * |
8 | * Permission is hereby granted, free of charge, to any person obtaining a | |
9 | * copy of this software and associated documentation files (the | |
10 | * "Software"), to deal in the Software without restriction, including | |
11 | * without limitation the rights to use, copy, modify, merge, publish, | |
12 | * distribute, sub license, and/or sell copies of the Software, and to | |
13 | * permit persons to whom the Software is furnished to do so, subject to | |
14 | * the following conditions: | |
15 | * | |
16 | * The above copyright notice and this permission notice (including the | |
17 | * next paragraph) shall be included in all copies or substantial portions | |
18 | * of the Software. | |
19 | * | |
20 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS | |
21 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
22 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. | |
23 | * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR | |
24 | * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, | |
25 | * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE | |
26 | * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. | |
27 | * | |
0d6aa60b | 28 | */ |
1da177e4 LT |
29 | |
30 | #ifndef _I915_DRV_H_ | |
31 | #define _I915_DRV_H_ | |
32 | ||
585fb111 | 33 | #include "i915_reg.h" |
79e53945 | 34 | #include "intel_bios.h" |
0839ccb8 | 35 | #include <linux/io-mapping.h> |
585fb111 | 36 | |
1da177e4 LT |
37 | /* General customization: |
38 | */ | |
39 | ||
40 | #define DRIVER_AUTHOR "Tungsten Graphics, Inc." | |
41 | ||
42 | #define DRIVER_NAME "i915" | |
43 | #define DRIVER_DESC "Intel Graphics" | |
673a394b | 44 | #define DRIVER_DATE "20080730" |
1da177e4 | 45 | |
317c35d1 JB |
46 | enum pipe { |
47 | PIPE_A = 0, | |
48 | PIPE_B, | |
49 | }; | |
50 | ||
80824003 JB |
51 | enum plane { |
52 | PLANE_A = 0, | |
53 | PLANE_B, | |
54 | }; | |
55 | ||
52440211 KP |
56 | #define I915_NUM_PIPE 2 |
57 | ||
1da177e4 LT |
58 | /* Interface history: |
59 | * | |
60 | * 1.1: Original. | |
0d6aa60b DA |
61 | * 1.2: Add Power Management |
62 | * 1.3: Add vblank support | |
de227f5f | 63 | * 1.4: Fix cmdbuffer path, add heap destroy |
702880f2 | 64 | * 1.5: Add vblank pipe configuration |
2228ed67 MD |
65 | * 1.6: - New ioctl for scheduling buffer swaps on vertical blank |
66 | * - Support vertical blank on secondary display pipe | |
1da177e4 LT |
67 | */ |
68 | #define DRIVER_MAJOR 1 | |
2228ed67 | 69 | #define DRIVER_MINOR 6 |
1da177e4 LT |
70 | #define DRIVER_PATCHLEVEL 0 |
71 | ||
673a394b EA |
72 | #define WATCH_COHERENCY 0 |
73 | #define WATCH_BUF 0 | |
74 | #define WATCH_EXEC 0 | |
75 | #define WATCH_LRU 0 | |
76 | #define WATCH_RELOC 0 | |
77 | #define WATCH_INACTIVE 0 | |
78 | #define WATCH_PWRITE 0 | |
79 | ||
71acb5eb DA |
80 | #define I915_GEM_PHYS_CURSOR_0 1 |
81 | #define I915_GEM_PHYS_CURSOR_1 2 | |
82 | #define I915_GEM_PHYS_OVERLAY_REGS 3 | |
83 | #define I915_MAX_PHYS_OBJECT (I915_GEM_PHYS_OVERLAY_REGS) | |
84 | ||
85 | struct drm_i915_gem_phys_object { | |
86 | int id; | |
87 | struct page **page_list; | |
88 | drm_dma_handle_t *handle; | |
89 | struct drm_gem_object *cur_obj; | |
90 | }; | |
91 | ||
1da177e4 | 92 | typedef struct _drm_i915_ring_buffer { |
1da177e4 LT |
93 | unsigned long Size; |
94 | u8 *virtual_start; | |
95 | int head; | |
96 | int tail; | |
97 | int space; | |
98 | drm_local_map_t map; | |
673a394b | 99 | struct drm_gem_object *ring_obj; |
1da177e4 LT |
100 | } drm_i915_ring_buffer_t; |
101 | ||
102 | struct mem_block { | |
103 | struct mem_block *next; | |
104 | struct mem_block *prev; | |
105 | int start; | |
106 | int size; | |
6c340eac | 107 | struct drm_file *file_priv; /* NULL: free, -1: heap, other: real files */ |
1da177e4 LT |
108 | }; |
109 | ||
0a3e67a4 JB |
110 | struct opregion_header; |
111 | struct opregion_acpi; | |
112 | struct opregion_swsci; | |
113 | struct opregion_asle; | |
114 | ||
8ee1c3db MG |
115 | struct intel_opregion { |
116 | struct opregion_header *header; | |
117 | struct opregion_acpi *acpi; | |
118 | struct opregion_swsci *swsci; | |
119 | struct opregion_asle *asle; | |
120 | int enabled; | |
121 | }; | |
122 | ||
7c1c2871 DA |
123 | struct drm_i915_master_private { |
124 | drm_local_map_t *sarea; | |
125 | struct _drm_i915_sarea *sarea_priv; | |
126 | }; | |
de151cf6 JB |
127 | #define I915_FENCE_REG_NONE -1 |
128 | ||
129 | struct drm_i915_fence_reg { | |
130 | struct drm_gem_object *obj; | |
131 | }; | |
7c1c2871 | 132 | |
9b9d172d | 133 | struct sdvo_device_mapping { |
134 | u8 dvo_port; | |
135 | u8 slave_addr; | |
136 | u8 dvo_wiring; | |
137 | u8 initialized; | |
138 | }; | |
139 | ||
63eeaf38 JB |
140 | struct drm_i915_error_state { |
141 | u32 eir; | |
142 | u32 pgtbl_er; | |
143 | u32 pipeastat; | |
144 | u32 pipebstat; | |
145 | u32 ipeir; | |
146 | u32 ipehr; | |
147 | u32 instdone; | |
148 | u32 acthd; | |
149 | u32 instpm; | |
150 | u32 instps; | |
151 | u32 instdone1; | |
152 | u32 seqno; | |
153 | struct timeval time; | |
154 | }; | |
155 | ||
1da177e4 | 156 | typedef struct drm_i915_private { |
673a394b EA |
157 | struct drm_device *dev; |
158 | ||
ac5c4e76 DA |
159 | int has_gem; |
160 | ||
3043c60c | 161 | void __iomem *regs; |
1da177e4 | 162 | |
ec2a4c3f | 163 | struct pci_dev *bridge_dev; |
1da177e4 LT |
164 | drm_i915_ring_buffer_t ring; |
165 | ||
9c8da5eb | 166 | drm_dma_handle_t *status_page_dmah; |
1da177e4 | 167 | void *hw_status_page; |
1da177e4 | 168 | dma_addr_t dma_status_page; |
0a3e67a4 | 169 | uint32_t counter; |
dc7a9319 WZ |
170 | unsigned int status_gfx_addr; |
171 | drm_local_map_t hws_map; | |
673a394b | 172 | struct drm_gem_object *hws_obj; |
1da177e4 | 173 | |
d7658989 JB |
174 | struct resource mch_res; |
175 | ||
a6b54f3f | 176 | unsigned int cpp; |
1da177e4 LT |
177 | int back_offset; |
178 | int front_offset; | |
179 | int current_page; | |
180 | int page_flipping; | |
1da177e4 LT |
181 | |
182 | wait_queue_head_t irq_queue; | |
183 | atomic_t irq_received; | |
ed4cb414 EA |
184 | /** Protects user_irq_refcount and irq_mask_reg */ |
185 | spinlock_t user_irq_lock; | |
186 | /** Refcount for i915_user_irq_get() versus i915_user_irq_put(). */ | |
187 | int user_irq_refcount; | |
188 | /** Cached value of IMR to avoid reads in updating the bitfield */ | |
189 | u32 irq_mask_reg; | |
7c463586 | 190 | u32 pipestat[2]; |
036a4a7d ZW |
191 | /** splitted irq regs for graphics and display engine on IGDNG, |
192 | irq_mask_reg is still used for display irq. */ | |
193 | u32 gt_irq_mask_reg; | |
194 | u32 gt_irq_enable_reg; | |
195 | u32 de_irq_enable_reg; | |
1da177e4 | 196 | |
5ca58282 JB |
197 | u32 hotplug_supported_mask; |
198 | struct work_struct hotplug_work; | |
199 | ||
1da177e4 LT |
200 | int tex_lru_log_granularity; |
201 | int allow_batchbuffer; | |
202 | struct mem_block *agp_heap; | |
0d6aa60b | 203 | unsigned int sr01, adpa, ppcr, dvob, dvoc, lvds; |
702880f2 | 204 | int vblank_pipe; |
a6b54f3f | 205 | |
f65d9421 BG |
206 | /* For hangcheck timer */ |
207 | #define DRM_I915_HANGCHECK_PERIOD 75 /* in jiffies */ | |
208 | struct timer_list hangcheck_timer; | |
209 | int hangcheck_count; | |
210 | uint32_t last_acthd; | |
211 | ||
79e53945 JB |
212 | bool cursor_needs_physical; |
213 | ||
214 | struct drm_mm vram; | |
215 | ||
80824003 JB |
216 | unsigned long cfb_size; |
217 | unsigned long cfb_pitch; | |
218 | int cfb_fence; | |
219 | int cfb_plane; | |
220 | ||
79e53945 JB |
221 | int irq_enabled; |
222 | ||
8ee1c3db MG |
223 | struct intel_opregion opregion; |
224 | ||
79e53945 JB |
225 | /* LVDS info */ |
226 | int backlight_duty_cycle; /* restore backlight to this value */ | |
227 | bool panel_wants_dither; | |
228 | struct drm_display_mode *panel_fixed_mode; | |
88631706 ML |
229 | struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */ |
230 | struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */ | |
79e53945 JB |
231 | |
232 | /* Feature bits from the VBIOS */ | |
95281e35 HE |
233 | unsigned int int_tv_support:1; |
234 | unsigned int lvds_dither:1; | |
235 | unsigned int lvds_vbt:1; | |
236 | unsigned int int_crt_support:1; | |
43565a06 | 237 | unsigned int lvds_use_ssc:1; |
32f9d658 | 238 | unsigned int edp_support:1; |
43565a06 | 239 | int lvds_ssc_freq; |
79e53945 | 240 | |
c1c7af60 JB |
241 | struct notifier_block lid_notifier; |
242 | ||
db545019 | 243 | int crt_ddc_bus; /* -1 = unknown, else GPIO to use for CRT DDC */ |
de151cf6 JB |
244 | struct drm_i915_fence_reg fence_regs[16]; /* assume 965 */ |
245 | int fence_reg_start; /* 4 if userland hasn't ioctl'd us yet */ | |
246 | int num_fence_regs; /* 8 on pre-965, 16 otherwise */ | |
247 | ||
7662c8bd SL |
248 | unsigned int fsb_freq, mem_freq; |
249 | ||
63eeaf38 JB |
250 | spinlock_t error_lock; |
251 | struct drm_i915_error_state *first_error; | |
8a905236 | 252 | struct work_struct error_work; |
9c9fe1f8 | 253 | struct workqueue_struct *wq; |
63eeaf38 | 254 | |
ba8bbcf6 | 255 | /* Register state */ |
06891e27 | 256 | bool suspended; |
ba8bbcf6 JB |
257 | u8 saveLBB; |
258 | u32 saveDSPACNTR; | |
259 | u32 saveDSPBCNTR; | |
e948e994 | 260 | u32 saveDSPARB; |
881ee988 | 261 | u32 saveRENDERSTANDBY; |
461cba2d | 262 | u32 saveHWS; |
ba8bbcf6 JB |
263 | u32 savePIPEACONF; |
264 | u32 savePIPEBCONF; | |
265 | u32 savePIPEASRC; | |
266 | u32 savePIPEBSRC; | |
267 | u32 saveFPA0; | |
268 | u32 saveFPA1; | |
269 | u32 saveDPLL_A; | |
270 | u32 saveDPLL_A_MD; | |
271 | u32 saveHTOTAL_A; | |
272 | u32 saveHBLANK_A; | |
273 | u32 saveHSYNC_A; | |
274 | u32 saveVTOTAL_A; | |
275 | u32 saveVBLANK_A; | |
276 | u32 saveVSYNC_A; | |
277 | u32 saveBCLRPAT_A; | |
0da3ea12 | 278 | u32 savePIPEASTAT; |
ba8bbcf6 JB |
279 | u32 saveDSPASTRIDE; |
280 | u32 saveDSPASIZE; | |
281 | u32 saveDSPAPOS; | |
585fb111 | 282 | u32 saveDSPAADDR; |
ba8bbcf6 JB |
283 | u32 saveDSPASURF; |
284 | u32 saveDSPATILEOFF; | |
285 | u32 savePFIT_PGM_RATIOS; | |
286 | u32 saveBLC_PWM_CTL; | |
287 | u32 saveBLC_PWM_CTL2; | |
288 | u32 saveFPB0; | |
289 | u32 saveFPB1; | |
290 | u32 saveDPLL_B; | |
291 | u32 saveDPLL_B_MD; | |
292 | u32 saveHTOTAL_B; | |
293 | u32 saveHBLANK_B; | |
294 | u32 saveHSYNC_B; | |
295 | u32 saveVTOTAL_B; | |
296 | u32 saveVBLANK_B; | |
297 | u32 saveVSYNC_B; | |
298 | u32 saveBCLRPAT_B; | |
0da3ea12 | 299 | u32 savePIPEBSTAT; |
ba8bbcf6 JB |
300 | u32 saveDSPBSTRIDE; |
301 | u32 saveDSPBSIZE; | |
302 | u32 saveDSPBPOS; | |
585fb111 | 303 | u32 saveDSPBADDR; |
ba8bbcf6 JB |
304 | u32 saveDSPBSURF; |
305 | u32 saveDSPBTILEOFF; | |
585fb111 JB |
306 | u32 saveVGA0; |
307 | u32 saveVGA1; | |
308 | u32 saveVGA_PD; | |
ba8bbcf6 JB |
309 | u32 saveVGACNTRL; |
310 | u32 saveADPA; | |
311 | u32 saveLVDS; | |
585fb111 JB |
312 | u32 savePP_ON_DELAYS; |
313 | u32 savePP_OFF_DELAYS; | |
ba8bbcf6 JB |
314 | u32 saveDVOA; |
315 | u32 saveDVOB; | |
316 | u32 saveDVOC; | |
317 | u32 savePP_ON; | |
318 | u32 savePP_OFF; | |
319 | u32 savePP_CONTROL; | |
585fb111 | 320 | u32 savePP_DIVISOR; |
ba8bbcf6 JB |
321 | u32 savePFIT_CONTROL; |
322 | u32 save_palette_a[256]; | |
323 | u32 save_palette_b[256]; | |
324 | u32 saveFBC_CFB_BASE; | |
325 | u32 saveFBC_LL_BASE; | |
326 | u32 saveFBC_CONTROL; | |
327 | u32 saveFBC_CONTROL2; | |
0da3ea12 JB |
328 | u32 saveIER; |
329 | u32 saveIIR; | |
330 | u32 saveIMR; | |
1f84e550 | 331 | u32 saveCACHE_MODE_0; |
e948e994 | 332 | u32 saveD_STATE; |
652c393a | 333 | u32 saveDSPCLK_GATE_D; |
1f84e550 | 334 | u32 saveMI_ARB_STATE; |
ba8bbcf6 JB |
335 | u32 saveSWF0[16]; |
336 | u32 saveSWF1[16]; | |
337 | u32 saveSWF2[3]; | |
338 | u8 saveMSR; | |
339 | u8 saveSR[8]; | |
123f794f | 340 | u8 saveGR[25]; |
ba8bbcf6 | 341 | u8 saveAR_INDEX; |
a59e122a | 342 | u8 saveAR[21]; |
ba8bbcf6 | 343 | u8 saveDACMASK; |
a59e122a | 344 | u8 saveCR[37]; |
79f11c19 | 345 | uint64_t saveFENCE[16]; |
1fd1c624 EA |
346 | u32 saveCURACNTR; |
347 | u32 saveCURAPOS; | |
348 | u32 saveCURABASE; | |
349 | u32 saveCURBCNTR; | |
350 | u32 saveCURBPOS; | |
351 | u32 saveCURBBASE; | |
352 | u32 saveCURSIZE; | |
a4fc5ed6 KP |
353 | u32 saveDP_B; |
354 | u32 saveDP_C; | |
355 | u32 saveDP_D; | |
356 | u32 savePIPEA_GMCH_DATA_M; | |
357 | u32 savePIPEB_GMCH_DATA_M; | |
358 | u32 savePIPEA_GMCH_DATA_N; | |
359 | u32 savePIPEB_GMCH_DATA_N; | |
360 | u32 savePIPEA_DP_LINK_M; | |
361 | u32 savePIPEB_DP_LINK_M; | |
362 | u32 savePIPEA_DP_LINK_N; | |
363 | u32 savePIPEB_DP_LINK_N; | |
673a394b EA |
364 | |
365 | struct { | |
366 | struct drm_mm gtt_space; | |
367 | ||
0839ccb8 | 368 | struct io_mapping *gtt_mapping; |
ab657db1 | 369 | int gtt_mtrr; |
0839ccb8 | 370 | |
31169714 CW |
371 | /** |
372 | * Membership on list of all loaded devices, used to evict | |
373 | * inactive buffers under memory pressure. | |
374 | * | |
375 | * Modifications should only be done whilst holding the | |
376 | * shrink_list_lock spinlock. | |
377 | */ | |
378 | struct list_head shrink_list; | |
379 | ||
673a394b EA |
380 | /** |
381 | * List of objects currently involved in rendering from the | |
382 | * ringbuffer. | |
383 | * | |
ce44b0ea EA |
384 | * Includes buffers having the contents of their GPU caches |
385 | * flushed, not necessarily primitives. last_rendering_seqno | |
386 | * represents when the rendering involved will be completed. | |
387 | * | |
673a394b EA |
388 | * A reference is held on the buffer while on this list. |
389 | */ | |
5e118f41 | 390 | spinlock_t active_list_lock; |
673a394b EA |
391 | struct list_head active_list; |
392 | ||
393 | /** | |
394 | * List of objects which are not in the ringbuffer but which | |
395 | * still have a write_domain which needs to be flushed before | |
396 | * unbinding. | |
397 | * | |
ce44b0ea EA |
398 | * last_rendering_seqno is 0 while an object is in this list. |
399 | * | |
673a394b EA |
400 | * A reference is held on the buffer while on this list. |
401 | */ | |
402 | struct list_head flushing_list; | |
403 | ||
404 | /** | |
405 | * LRU list of objects which are not in the ringbuffer and | |
406 | * are ready to unbind, but are still in the GTT. | |
407 | * | |
ce44b0ea EA |
408 | * last_rendering_seqno is 0 while an object is in this list. |
409 | * | |
673a394b EA |
410 | * A reference is not held on the buffer while on this list, |
411 | * as merely being GTT-bound shouldn't prevent its being | |
412 | * freed, and we'll pull it off the list in the free path. | |
413 | */ | |
414 | struct list_head inactive_list; | |
415 | ||
a09ba7fa EA |
416 | /** LRU list of objects with fence regs on them. */ |
417 | struct list_head fence_list; | |
418 | ||
673a394b EA |
419 | /** |
420 | * List of breadcrumbs associated with GPU requests currently | |
421 | * outstanding. | |
422 | */ | |
423 | struct list_head request_list; | |
424 | ||
425 | /** | |
426 | * We leave the user IRQ off as much as possible, | |
427 | * but this means that requests will finish and never | |
428 | * be retired once the system goes idle. Set a timer to | |
429 | * fire periodically while the ring is running. When it | |
430 | * fires, go retire requests. | |
431 | */ | |
432 | struct delayed_work retire_work; | |
433 | ||
434 | uint32_t next_gem_seqno; | |
435 | ||
436 | /** | |
437 | * Waiting sequence number, if any | |
438 | */ | |
439 | uint32_t waiting_gem_seqno; | |
440 | ||
441 | /** | |
442 | * Last seq seen at irq time | |
443 | */ | |
444 | uint32_t irq_gem_seqno; | |
445 | ||
446 | /** | |
447 | * Flag if the X Server, and thus DRM, is not currently in | |
448 | * control of the device. | |
449 | * | |
450 | * This is set between LeaveVT and EnterVT. It needs to be | |
451 | * replaced with a semaphore. It also needs to be | |
452 | * transitioned away from for kernel modesetting. | |
453 | */ | |
454 | int suspended; | |
455 | ||
456 | /** | |
457 | * Flag if the hardware appears to be wedged. | |
458 | * | |
459 | * This is set when attempts to idle the device timeout. | |
460 | * It prevents command submission from occuring and makes | |
461 | * every pending request fail | |
462 | */ | |
ba1234d1 | 463 | atomic_t wedged; |
673a394b EA |
464 | |
465 | /** Bit 6 swizzling required for X tiling */ | |
466 | uint32_t bit_6_swizzle_x; | |
467 | /** Bit 6 swizzling required for Y tiling */ | |
468 | uint32_t bit_6_swizzle_y; | |
71acb5eb DA |
469 | |
470 | /* storage for physical objects */ | |
471 | struct drm_i915_gem_phys_object *phys_objs[I915_MAX_PHYS_OBJECT]; | |
673a394b | 472 | } mm; |
9b9d172d | 473 | struct sdvo_device_mapping sdvo_mappings[2]; |
652c393a JB |
474 | |
475 | /* Reclocking support */ | |
476 | bool render_reclock_avail; | |
477 | bool lvds_downclock_avail; | |
478 | struct work_struct idle_work; | |
479 | struct timer_list idle_timer; | |
480 | bool busy; | |
481 | u16 orig_clock; | |
1da177e4 LT |
482 | } drm_i915_private_t; |
483 | ||
673a394b EA |
484 | /** driver private structure attached to each drm_gem_object */ |
485 | struct drm_i915_gem_object { | |
486 | struct drm_gem_object *obj; | |
487 | ||
488 | /** Current space allocated to this object in the GTT, if any. */ | |
489 | struct drm_mm_node *gtt_space; | |
490 | ||
491 | /** This object's place on the active/flushing/inactive lists */ | |
492 | struct list_head list; | |
493 | ||
a09ba7fa EA |
494 | /** This object's place on the fenced object LRU */ |
495 | struct list_head fence_list; | |
496 | ||
673a394b EA |
497 | /** |
498 | * This is set if the object is on the active or flushing lists | |
499 | * (has pending rendering), and is not set if it's on inactive (ready | |
500 | * to be unbound). | |
501 | */ | |
502 | int active; | |
503 | ||
504 | /** | |
505 | * This is set if the object has been written to since last bound | |
506 | * to the GTT | |
507 | */ | |
508 | int dirty; | |
509 | ||
510 | /** AGP memory structure for our GTT binding. */ | |
511 | DRM_AGP_MEM *agp_mem; | |
512 | ||
856fa198 EA |
513 | struct page **pages; |
514 | int pages_refcount; | |
673a394b EA |
515 | |
516 | /** | |
517 | * Current offset of the object in GTT space. | |
518 | * | |
519 | * This is the same as gtt_space->start | |
520 | */ | |
521 | uint32_t gtt_offset; | |
e67b8ce1 | 522 | |
de151cf6 JB |
523 | /** |
524 | * Fake offset for use by mmap(2) | |
525 | */ | |
526 | uint64_t mmap_offset; | |
527 | ||
528 | /** | |
529 | * Fence register bits (if any) for this object. Will be set | |
530 | * as needed when mapped into the GTT. | |
531 | * Protected by dev->struct_mutex. | |
532 | */ | |
533 | int fence_reg; | |
673a394b | 534 | |
673a394b EA |
535 | /** How many users have pinned this object in GTT space */ |
536 | int pin_count; | |
537 | ||
538 | /** Breadcrumb of last rendering to the buffer. */ | |
539 | uint32_t last_rendering_seqno; | |
540 | ||
541 | /** Current tiling mode for the object. */ | |
542 | uint32_t tiling_mode; | |
de151cf6 | 543 | uint32_t stride; |
673a394b | 544 | |
280b713b EA |
545 | /** Record of address bit 17 of each page at last unbind. */ |
546 | long *bit_17; | |
547 | ||
ba1eb1d8 KP |
548 | /** AGP mapping type (AGP_USER_MEMORY or AGP_USER_CACHED_MEMORY */ |
549 | uint32_t agp_type; | |
550 | ||
673a394b | 551 | /** |
e47c68e9 EA |
552 | * If present, while GEM_DOMAIN_CPU is in the read domain this array |
553 | * flags which individual pages are valid. | |
673a394b EA |
554 | */ |
555 | uint8_t *page_cpu_valid; | |
79e53945 JB |
556 | |
557 | /** User space pin count and filp owning the pin */ | |
558 | uint32_t user_pin_count; | |
559 | struct drm_file *pin_filp; | |
71acb5eb DA |
560 | |
561 | /** for phy allocated objects */ | |
562 | struct drm_i915_gem_phys_object *phys_obj; | |
b70d11da KH |
563 | |
564 | /** | |
565 | * Used for checking the object doesn't appear more than once | |
566 | * in an execbuffer object list. | |
567 | */ | |
568 | int in_execbuffer; | |
3ef94daa CW |
569 | |
570 | /** | |
571 | * Advice: are the backing pages purgeable? | |
572 | */ | |
573 | int madv; | |
673a394b EA |
574 | }; |
575 | ||
576 | /** | |
577 | * Request queue structure. | |
578 | * | |
579 | * The request queue allows us to note sequence numbers that have been emitted | |
580 | * and may be associated with active buffers to be retired. | |
581 | * | |
582 | * By keeping this list, we can avoid having to do questionable | |
583 | * sequence-number comparisons on buffer last_rendering_seqnos, and associate | |
584 | * an emission time with seqnos for tracking how far ahead of the GPU we are. | |
585 | */ | |
586 | struct drm_i915_gem_request { | |
587 | /** GEM sequence number associated with this request. */ | |
588 | uint32_t seqno; | |
589 | ||
590 | /** Time at which this request was emitted, in jiffies. */ | |
591 | unsigned long emitted_jiffies; | |
592 | ||
b962442e | 593 | /** global list entry for this request */ |
673a394b | 594 | struct list_head list; |
b962442e EA |
595 | |
596 | /** file_priv list entry for this request */ | |
597 | struct list_head client_list; | |
673a394b EA |
598 | }; |
599 | ||
600 | struct drm_i915_file_private { | |
601 | struct { | |
b962442e | 602 | struct list_head request_list; |
673a394b EA |
603 | } mm; |
604 | }; | |
605 | ||
79e53945 JB |
606 | enum intel_chip_family { |
607 | CHIP_I8XX = 0x01, | |
608 | CHIP_I9XX = 0x02, | |
609 | CHIP_I915 = 0x04, | |
610 | CHIP_I965 = 0x08, | |
611 | }; | |
612 | ||
c153f45f | 613 | extern struct drm_ioctl_desc i915_ioctls[]; |
b3a83639 | 614 | extern int i915_max_ioctl; |
79e53945 | 615 | extern unsigned int i915_fbpercrtc; |
652c393a | 616 | extern unsigned int i915_powersave; |
b3a83639 | 617 | |
1341d655 BG |
618 | extern void i915_save_display(struct drm_device *dev); |
619 | extern void i915_restore_display(struct drm_device *dev); | |
7c1c2871 DA |
620 | extern int i915_master_create(struct drm_device *dev, struct drm_master *master); |
621 | extern void i915_master_destroy(struct drm_device *dev, struct drm_master *master); | |
622 | ||
1da177e4 | 623 | /* i915_dma.c */ |
84b1fd10 | 624 | extern void i915_kernel_lost_context(struct drm_device * dev); |
22eae947 | 625 | extern int i915_driver_load(struct drm_device *, unsigned long flags); |
ba8bbcf6 | 626 | extern int i915_driver_unload(struct drm_device *); |
673a394b | 627 | extern int i915_driver_open(struct drm_device *dev, struct drm_file *file_priv); |
84b1fd10 | 628 | extern void i915_driver_lastclose(struct drm_device * dev); |
6c340eac EA |
629 | extern void i915_driver_preclose(struct drm_device *dev, |
630 | struct drm_file *file_priv); | |
673a394b EA |
631 | extern void i915_driver_postclose(struct drm_device *dev, |
632 | struct drm_file *file_priv); | |
84b1fd10 | 633 | extern int i915_driver_device_is_agp(struct drm_device * dev); |
0d6aa60b DA |
634 | extern long i915_compat_ioctl(struct file *filp, unsigned int cmd, |
635 | unsigned long arg); | |
673a394b | 636 | extern int i915_emit_box(struct drm_device *dev, |
201361a5 | 637 | struct drm_clip_rect *boxes, |
673a394b | 638 | int i, int DR1, int DR4); |
11ed50ec | 639 | extern int i965_reset(struct drm_device *dev, u8 flags); |
af6061af | 640 | |
1da177e4 | 641 | /* i915_irq.c */ |
f65d9421 | 642 | void i915_hangcheck_elapsed(unsigned long data); |
c153f45f EA |
643 | extern int i915_irq_emit(struct drm_device *dev, void *data, |
644 | struct drm_file *file_priv); | |
645 | extern int i915_irq_wait(struct drm_device *dev, void *data, | |
646 | struct drm_file *file_priv); | |
673a394b EA |
647 | void i915_user_irq_get(struct drm_device *dev); |
648 | void i915_user_irq_put(struct drm_device *dev); | |
79e53945 | 649 | extern void i915_enable_interrupt (struct drm_device *dev); |
1da177e4 LT |
650 | |
651 | extern irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS); | |
84b1fd10 | 652 | extern void i915_driver_irq_preinstall(struct drm_device * dev); |
0a3e67a4 | 653 | extern int i915_driver_irq_postinstall(struct drm_device *dev); |
84b1fd10 | 654 | extern void i915_driver_irq_uninstall(struct drm_device * dev); |
c153f45f EA |
655 | extern int i915_vblank_pipe_set(struct drm_device *dev, void *data, |
656 | struct drm_file *file_priv); | |
657 | extern int i915_vblank_pipe_get(struct drm_device *dev, void *data, | |
658 | struct drm_file *file_priv); | |
0a3e67a4 JB |
659 | extern int i915_enable_vblank(struct drm_device *dev, int crtc); |
660 | extern void i915_disable_vblank(struct drm_device *dev, int crtc); | |
661 | extern u32 i915_get_vblank_counter(struct drm_device *dev, int crtc); | |
9880b7a5 | 662 | extern u32 gm45_get_vblank_counter(struct drm_device *dev, int crtc); |
c153f45f EA |
663 | extern int i915_vblank_swap(struct drm_device *dev, void *data, |
664 | struct drm_file *file_priv); | |
8ee1c3db | 665 | extern void i915_enable_irq(drm_i915_private_t *dev_priv, u32 mask); |
1da177e4 | 666 | |
7c463586 KP |
667 | void |
668 | i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask); | |
669 | ||
670 | void | |
671 | i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask); | |
672 | ||
673 | ||
1da177e4 | 674 | /* i915_mem.c */ |
c153f45f EA |
675 | extern int i915_mem_alloc(struct drm_device *dev, void *data, |
676 | struct drm_file *file_priv); | |
677 | extern int i915_mem_free(struct drm_device *dev, void *data, | |
678 | struct drm_file *file_priv); | |
679 | extern int i915_mem_init_heap(struct drm_device *dev, void *data, | |
680 | struct drm_file *file_priv); | |
681 | extern int i915_mem_destroy_heap(struct drm_device *dev, void *data, | |
682 | struct drm_file *file_priv); | |
1da177e4 | 683 | extern void i915_mem_takedown(struct mem_block **heap); |
84b1fd10 | 684 | extern void i915_mem_release(struct drm_device * dev, |
6c340eac | 685 | struct drm_file *file_priv, struct mem_block *heap); |
673a394b EA |
686 | /* i915_gem.c */ |
687 | int i915_gem_init_ioctl(struct drm_device *dev, void *data, | |
688 | struct drm_file *file_priv); | |
689 | int i915_gem_create_ioctl(struct drm_device *dev, void *data, | |
690 | struct drm_file *file_priv); | |
691 | int i915_gem_pread_ioctl(struct drm_device *dev, void *data, | |
692 | struct drm_file *file_priv); | |
693 | int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data, | |
694 | struct drm_file *file_priv); | |
695 | int i915_gem_mmap_ioctl(struct drm_device *dev, void *data, | |
696 | struct drm_file *file_priv); | |
de151cf6 JB |
697 | int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data, |
698 | struct drm_file *file_priv); | |
673a394b EA |
699 | int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data, |
700 | struct drm_file *file_priv); | |
701 | int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data, | |
702 | struct drm_file *file_priv); | |
703 | int i915_gem_execbuffer(struct drm_device *dev, void *data, | |
704 | struct drm_file *file_priv); | |
705 | int i915_gem_pin_ioctl(struct drm_device *dev, void *data, | |
706 | struct drm_file *file_priv); | |
707 | int i915_gem_unpin_ioctl(struct drm_device *dev, void *data, | |
708 | struct drm_file *file_priv); | |
709 | int i915_gem_busy_ioctl(struct drm_device *dev, void *data, | |
710 | struct drm_file *file_priv); | |
711 | int i915_gem_throttle_ioctl(struct drm_device *dev, void *data, | |
712 | struct drm_file *file_priv); | |
3ef94daa CW |
713 | int i915_gem_madvise_ioctl(struct drm_device *dev, void *data, |
714 | struct drm_file *file_priv); | |
673a394b EA |
715 | int i915_gem_entervt_ioctl(struct drm_device *dev, void *data, |
716 | struct drm_file *file_priv); | |
717 | int i915_gem_leavevt_ioctl(struct drm_device *dev, void *data, | |
718 | struct drm_file *file_priv); | |
719 | int i915_gem_set_tiling(struct drm_device *dev, void *data, | |
720 | struct drm_file *file_priv); | |
721 | int i915_gem_get_tiling(struct drm_device *dev, void *data, | |
722 | struct drm_file *file_priv); | |
5a125c3c EA |
723 | int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data, |
724 | struct drm_file *file_priv); | |
673a394b | 725 | void i915_gem_load(struct drm_device *dev); |
673a394b EA |
726 | int i915_gem_init_object(struct drm_gem_object *obj); |
727 | void i915_gem_free_object(struct drm_gem_object *obj); | |
728 | int i915_gem_object_pin(struct drm_gem_object *obj, uint32_t alignment); | |
729 | void i915_gem_object_unpin(struct drm_gem_object *obj); | |
0f973f27 | 730 | int i915_gem_object_unbind(struct drm_gem_object *obj); |
d05ca301 | 731 | void i915_gem_release_mmap(struct drm_gem_object *obj); |
673a394b EA |
732 | void i915_gem_lastclose(struct drm_device *dev); |
733 | uint32_t i915_get_gem_seqno(struct drm_device *dev); | |
22be1724 | 734 | bool i915_seqno_passed(uint32_t seq1, uint32_t seq2); |
8c4b8c3f | 735 | int i915_gem_object_get_fence_reg(struct drm_gem_object *obj); |
52dc7d32 | 736 | int i915_gem_object_put_fence_reg(struct drm_gem_object *obj); |
673a394b EA |
737 | void i915_gem_retire_requests(struct drm_device *dev); |
738 | void i915_gem_retire_work_handler(struct work_struct *work); | |
739 | void i915_gem_clflush_object(struct drm_gem_object *obj); | |
79e53945 JB |
740 | int i915_gem_object_set_domain(struct drm_gem_object *obj, |
741 | uint32_t read_domains, | |
742 | uint32_t write_domain); | |
743 | int i915_gem_init_ringbuffer(struct drm_device *dev); | |
744 | void i915_gem_cleanup_ringbuffer(struct drm_device *dev); | |
745 | int i915_gem_do_init(struct drm_device *dev, unsigned long start, | |
746 | unsigned long end); | |
5669fcac | 747 | int i915_gem_idle(struct drm_device *dev); |
de151cf6 | 748 | int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf); |
79e53945 JB |
749 | int i915_gem_object_set_to_gtt_domain(struct drm_gem_object *obj, |
750 | int write); | |
71acb5eb DA |
751 | int i915_gem_attach_phys_object(struct drm_device *dev, |
752 | struct drm_gem_object *obj, int id); | |
753 | void i915_gem_detach_phys_object(struct drm_device *dev, | |
754 | struct drm_gem_object *obj); | |
755 | void i915_gem_free_all_phys_object(struct drm_device *dev); | |
6911a9b8 BG |
756 | int i915_gem_object_get_pages(struct drm_gem_object *obj); |
757 | void i915_gem_object_put_pages(struct drm_gem_object *obj); | |
1fd1c624 | 758 | void i915_gem_release(struct drm_device * dev, struct drm_file *file_priv); |
673a394b | 759 | |
31169714 CW |
760 | void i915_gem_shrinker_init(void); |
761 | void i915_gem_shrinker_exit(void); | |
762 | ||
673a394b EA |
763 | /* i915_gem_tiling.c */ |
764 | void i915_gem_detect_bit_6_swizzle(struct drm_device *dev); | |
280b713b EA |
765 | void i915_gem_object_do_bit_17_swizzle(struct drm_gem_object *obj); |
766 | void i915_gem_object_save_bit_17_swizzle(struct drm_gem_object *obj); | |
673a394b EA |
767 | |
768 | /* i915_gem_debug.c */ | |
769 | void i915_gem_dump_object(struct drm_gem_object *obj, int len, | |
770 | const char *where, uint32_t mark); | |
771 | #if WATCH_INACTIVE | |
772 | void i915_verify_inactive(struct drm_device *dev, char *file, int line); | |
773 | #else | |
774 | #define i915_verify_inactive(dev, file, line) | |
775 | #endif | |
776 | void i915_gem_object_check_coherency(struct drm_gem_object *obj, int handle); | |
777 | void i915_gem_dump_object(struct drm_gem_object *obj, int len, | |
778 | const char *where, uint32_t mark); | |
779 | void i915_dump_lru(struct drm_device *dev, const char *where); | |
1da177e4 | 780 | |
2017263e | 781 | /* i915_debugfs.c */ |
27c202ad BG |
782 | int i915_debugfs_init(struct drm_minor *minor); |
783 | void i915_debugfs_cleanup(struct drm_minor *minor); | |
2017263e | 784 | |
317c35d1 JB |
785 | /* i915_suspend.c */ |
786 | extern int i915_save_state(struct drm_device *dev); | |
787 | extern int i915_restore_state(struct drm_device *dev); | |
0a3e67a4 JB |
788 | |
789 | /* i915_suspend.c */ | |
790 | extern int i915_save_state(struct drm_device *dev); | |
791 | extern int i915_restore_state(struct drm_device *dev); | |
317c35d1 | 792 | |
65e082c9 | 793 | #ifdef CONFIG_ACPI |
8ee1c3db | 794 | /* i915_opregion.c */ |
74a365b3 | 795 | extern int intel_opregion_init(struct drm_device *dev, int resume); |
3b1c1c11 | 796 | extern void intel_opregion_free(struct drm_device *dev, int suspend); |
8ee1c3db MG |
797 | extern void opregion_asle_intr(struct drm_device *dev); |
798 | extern void opregion_enable_asle(struct drm_device *dev); | |
65e082c9 | 799 | #else |
03ae61dd | 800 | static inline int intel_opregion_init(struct drm_device *dev, int resume) { return 0; } |
3b1c1c11 | 801 | static inline void intel_opregion_free(struct drm_device *dev, int suspend) { return; } |
65e082c9 LB |
802 | static inline void opregion_asle_intr(struct drm_device *dev) { return; } |
803 | static inline void opregion_enable_asle(struct drm_device *dev) { return; } | |
804 | #endif | |
8ee1c3db | 805 | |
79e53945 JB |
806 | /* modesetting */ |
807 | extern void intel_modeset_init(struct drm_device *dev); | |
808 | extern void intel_modeset_cleanup(struct drm_device *dev); | |
80824003 | 809 | extern void i8xx_disable_fbc(struct drm_device *dev); |
79e53945 | 810 | |
546b0974 EA |
811 | /** |
812 | * Lock test for when it's just for synchronization of ring access. | |
813 | * | |
814 | * In that case, we don't need to do it when GEM is initialized as nobody else | |
815 | * has access to the ring. | |
816 | */ | |
817 | #define RING_LOCK_TEST_WITH_RETURN(dev, file_priv) do { \ | |
818 | if (((drm_i915_private_t *)dev->dev_private)->ring.ring_obj == NULL) \ | |
819 | LOCK_TEST_WITH_RETURN(dev, file_priv); \ | |
820 | } while (0) | |
821 | ||
3043c60c EA |
822 | #define I915_READ(reg) readl(dev_priv->regs + (reg)) |
823 | #define I915_WRITE(reg, val) writel(val, dev_priv->regs + (reg)) | |
824 | #define I915_READ16(reg) readw(dev_priv->regs + (reg)) | |
825 | #define I915_WRITE16(reg, val) writel(val, dev_priv->regs + (reg)) | |
826 | #define I915_READ8(reg) readb(dev_priv->regs + (reg)) | |
827 | #define I915_WRITE8(reg, val) writeb(val, dev_priv->regs + (reg)) | |
de151cf6 | 828 | #define I915_WRITE64(reg, val) writeq(val, dev_priv->regs + (reg)) |
049ef7e4 | 829 | #define I915_READ64(reg) readq(dev_priv->regs + (reg)) |
7d57382e | 830 | #define POSTING_READ(reg) (void)I915_READ(reg) |
1da177e4 LT |
831 | |
832 | #define I915_VERBOSE 0 | |
833 | ||
0ef82af7 CW |
834 | #define RING_LOCALS volatile unsigned int *ring_virt__; |
835 | ||
836 | #define BEGIN_LP_RING(n) do { \ | |
837 | int bytes__ = 4*(n); \ | |
838 | if (I915_VERBOSE) DRM_DEBUG("BEGIN_LP_RING(%d)\n", (n)); \ | |
839 | /* a wrap must occur between instructions so pad beforehand */ \ | |
840 | if (unlikely (dev_priv->ring.tail + bytes__ > dev_priv->ring.Size)) \ | |
841 | i915_wrap_ring(dev); \ | |
842 | if (unlikely (dev_priv->ring.space < bytes__)) \ | |
843 | i915_wait_ring(dev, bytes__, __func__); \ | |
844 | ring_virt__ = (unsigned int *) \ | |
845 | (dev_priv->ring.virtual_start + dev_priv->ring.tail); \ | |
846 | dev_priv->ring.tail += bytes__; \ | |
847 | dev_priv->ring.tail &= dev_priv->ring.Size - 1; \ | |
848 | dev_priv->ring.space -= bytes__; \ | |
1da177e4 LT |
849 | } while (0) |
850 | ||
0ef82af7 | 851 | #define OUT_RING(n) do { \ |
1da177e4 | 852 | if (I915_VERBOSE) DRM_DEBUG(" OUT_RING %x\n", (int)(n)); \ |
0ef82af7 | 853 | *ring_virt__++ = (n); \ |
1da177e4 LT |
854 | } while (0) |
855 | ||
856 | #define ADVANCE_LP_RING() do { \ | |
0ef82af7 CW |
857 | if (I915_VERBOSE) \ |
858 | DRM_DEBUG("ADVANCE_LP_RING %x\n", dev_priv->ring.tail); \ | |
859 | I915_WRITE(PRB0_TAIL, dev_priv->ring.tail); \ | |
1da177e4 LT |
860 | } while(0) |
861 | ||
ba8bbcf6 | 862 | /** |
585fb111 JB |
863 | * Reads a dword out of the status page, which is written to from the command |
864 | * queue by automatic updates, MI_REPORT_HEAD, MI_STORE_DATA_INDEX, or | |
865 | * MI_STORE_DATA_IMM. | |
ba8bbcf6 | 866 | * |
585fb111 | 867 | * The following dwords have a reserved meaning: |
0cdad7e8 KP |
868 | * 0x00: ISR copy, updated when an ISR bit not set in the HWSTAM changes. |
869 | * 0x04: ring 0 head pointer | |
870 | * 0x05: ring 1 head pointer (915-class) | |
871 | * 0x06: ring 2 head pointer (915-class) | |
872 | * 0x10-0x1b: Context status DWords (GM45) | |
873 | * 0x1f: Last written status offset. (GM45) | |
ba8bbcf6 | 874 | * |
0cdad7e8 | 875 | * The area from dword 0x20 to 0x3ff is available for driver usage. |
ba8bbcf6 | 876 | */ |
585fb111 | 877 | #define READ_HWSP(dev_priv, reg) (((volatile u32*)(dev_priv->hw_status_page))[reg]) |
0baf823a | 878 | #define READ_BREADCRUMB(dev_priv) READ_HWSP(dev_priv, I915_BREADCRUMB_INDEX) |
0cdad7e8 | 879 | #define I915_GEM_HWS_INDEX 0x20 |
0baf823a | 880 | #define I915_BREADCRUMB_INDEX 0x21 |
ba8bbcf6 | 881 | |
0ef82af7 | 882 | extern int i915_wrap_ring(struct drm_device * dev); |
585fb111 | 883 | extern int i915_wait_ring(struct drm_device * dev, int n, const char *caller); |
ba8bbcf6 JB |
884 | |
885 | #define IS_I830(dev) ((dev)->pci_device == 0x3577) | |
886 | #define IS_845G(dev) ((dev)->pci_device == 0x2562) | |
887 | #define IS_I85X(dev) ((dev)->pci_device == 0x3582) | |
888 | #define IS_I855(dev) ((dev)->pci_device == 0x3582) | |
889 | #define IS_I865G(dev) ((dev)->pci_device == 0x2572) | |
890 | ||
4d1f7888 | 891 | #define IS_I915G(dev) ((dev)->pci_device == 0x2582 || (dev)->pci_device == 0x258a) |
ba8bbcf6 JB |
892 | #define IS_I915GM(dev) ((dev)->pci_device == 0x2592) |
893 | #define IS_I945G(dev) ((dev)->pci_device == 0x2772) | |
3bf48468 JB |
894 | #define IS_I945GM(dev) ((dev)->pci_device == 0x27A2 ||\ |
895 | (dev)->pci_device == 0x27AE) | |
ba8bbcf6 JB |
896 | #define IS_I965G(dev) ((dev)->pci_device == 0x2972 || \ |
897 | (dev)->pci_device == 0x2982 || \ | |
898 | (dev)->pci_device == 0x2992 || \ | |
899 | (dev)->pci_device == 0x29A2 || \ | |
900 | (dev)->pci_device == 0x2A02 || \ | |
5f5f9d4c | 901 | (dev)->pci_device == 0x2A12 || \ |
d3adbc0c ZW |
902 | (dev)->pci_device == 0x2A42 || \ |
903 | (dev)->pci_device == 0x2E02 || \ | |
904 | (dev)->pci_device == 0x2E12 || \ | |
72021788 | 905 | (dev)->pci_device == 0x2E22 || \ |
280da227 | 906 | (dev)->pci_device == 0x2E32 || \ |
7839c5d5 | 907 | (dev)->pci_device == 0x2E42 || \ |
280da227 ZW |
908 | (dev)->pci_device == 0x0042 || \ |
909 | (dev)->pci_device == 0x0046) | |
ba8bbcf6 | 910 | |
c9ed4486 ML |
911 | #define IS_I965GM(dev) ((dev)->pci_device == 0x2A02 || \ |
912 | (dev)->pci_device == 0x2A12) | |
ba8bbcf6 | 913 | |
b9bfdfe6 | 914 | #define IS_GM45(dev) ((dev)->pci_device == 0x2A42) |
5f5f9d4c | 915 | |
d3adbc0c ZW |
916 | #define IS_G4X(dev) ((dev)->pci_device == 0x2E02 || \ |
917 | (dev)->pci_device == 0x2E12 || \ | |
60fd99e3 | 918 | (dev)->pci_device == 0x2E22 || \ |
72021788 | 919 | (dev)->pci_device == 0x2E32 || \ |
7839c5d5 | 920 | (dev)->pci_device == 0x2E42 || \ |
60fd99e3 | 921 | IS_GM45(dev)) |
d3adbc0c | 922 | |
2177832f SL |
923 | #define IS_IGDG(dev) ((dev)->pci_device == 0xa001) |
924 | #define IS_IGDGM(dev) ((dev)->pci_device == 0xa011) | |
925 | #define IS_IGD(dev) (IS_IGDG(dev) || IS_IGDGM(dev)) | |
926 | ||
ba8bbcf6 JB |
927 | #define IS_G33(dev) ((dev)->pci_device == 0x29C2 || \ |
928 | (dev)->pci_device == 0x29B2 || \ | |
2177832f SL |
929 | (dev)->pci_device == 0x29D2 || \ |
930 | (IS_IGD(dev))) | |
ba8bbcf6 | 931 | |
280da227 ZW |
932 | #define IS_IGDNG_D(dev) ((dev)->pci_device == 0x0042) |
933 | #define IS_IGDNG_M(dev) ((dev)->pci_device == 0x0046) | |
934 | #define IS_IGDNG(dev) (IS_IGDNG_D(dev) || IS_IGDNG_M(dev)) | |
935 | ||
ba8bbcf6 | 936 | #define IS_I9XX(dev) (IS_I915G(dev) || IS_I915GM(dev) || IS_I945G(dev) || \ |
280da227 ZW |
937 | IS_I945GM(dev) || IS_I965G(dev) || IS_G33(dev) || \ |
938 | IS_IGDNG(dev)) | |
ba8bbcf6 JB |
939 | |
940 | #define IS_MOBILE(dev) (IS_I830(dev) || IS_I85X(dev) || IS_I915GM(dev) || \ | |
2177832f | 941 | IS_I945GM(dev) || IS_I965GM(dev) || IS_GM45(dev) || \ |
280da227 | 942 | IS_IGD(dev) || IS_IGDNG_M(dev)) |
ba8bbcf6 | 943 | |
280da227 ZW |
944 | #define I915_NEED_GFX_HWS(dev) (IS_G33(dev) || IS_GM45(dev) || IS_G4X(dev) || \ |
945 | IS_IGDNG(dev)) | |
0f973f27 JB |
946 | /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte |
947 | * rows, which changed the alignment requirements and fence programming. | |
948 | */ | |
949 | #define HAS_128_BYTE_Y_TILING(dev) (IS_I9XX(dev) && !(IS_I915G(dev) || \ | |
950 | IS_I915GM(dev))) | |
280da227 | 951 | #define SUPPORTS_INTEGRATED_HDMI(dev) (IS_G4X(dev) || IS_IGDNG(dev)) |
a4fc5ed6 | 952 | #define SUPPORTS_INTEGRATED_DP(dev) (IS_G4X(dev) || IS_IGDNG(dev)) |
32f9d658 | 953 | #define SUPPORTS_EDP(dev) (IS_IGDNG_M(dev)) |
af729a26 | 954 | #define I915_HAS_HOTPLUG(dev) (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev) || IS_I965G(dev)) |
7662c8bd | 955 | /* dsparb controlled by hw only */ |
22bd50c5 | 956 | #define DSPARB_HWCONTROL(dev) (IS_G4X(dev) || IS_IGDNG(dev)) |
b39d50e5 | 957 | |
652c393a JB |
958 | #define HAS_FW_BLC(dev) (IS_I9XX(dev) || IS_G4X(dev) || IS_IGDNG(dev)) |
959 | #define HAS_PIPE_CXSR(dev) (IS_G4X(dev) || IS_IGDNG(dev)) | |
c1a1cdc1 | 960 | #define I915_HAS_FBC(dev) (IS_MOBILE(dev) && (IS_I9XX(dev) || IS_I965G(dev))) |
652c393a | 961 | |
ba8bbcf6 | 962 | #define PRIMARY_RINGBUFFER_SIZE (128*1024) |
0d6aa60b | 963 | |
1da177e4 | 964 | #endif |