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1da177e4 LT |
1 | /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*- |
2 | */ | |
0d6aa60b | 3 | /* |
bc54fd1a | 4 | * |
1da177e4 LT |
5 | * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. |
6 | * All Rights Reserved. | |
bc54fd1a DA |
7 | * |
8 | * Permission is hereby granted, free of charge, to any person obtaining a | |
9 | * copy of this software and associated documentation files (the | |
10 | * "Software"), to deal in the Software without restriction, including | |
11 | * without limitation the rights to use, copy, modify, merge, publish, | |
12 | * distribute, sub license, and/or sell copies of the Software, and to | |
13 | * permit persons to whom the Software is furnished to do so, subject to | |
14 | * the following conditions: | |
15 | * | |
16 | * The above copyright notice and this permission notice (including the | |
17 | * next paragraph) shall be included in all copies or substantial portions | |
18 | * of the Software. | |
19 | * | |
20 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS | |
21 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
22 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. | |
23 | * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR | |
24 | * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, | |
25 | * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE | |
26 | * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. | |
27 | * | |
0d6aa60b | 28 | */ |
1da177e4 LT |
29 | |
30 | #ifndef _I915_DRV_H_ | |
31 | #define _I915_DRV_H_ | |
32 | ||
e9b73c67 CW |
33 | #include <uapi/drm/i915_drm.h> |
34 | ||
585fb111 | 35 | #include "i915_reg.h" |
79e53945 | 36 | #include "intel_bios.h" |
8187a2b7 | 37 | #include "intel_ringbuffer.h" |
0839ccb8 | 38 | #include <linux/io-mapping.h> |
f899fc64 | 39 | #include <linux/i2c.h> |
c167a6fc | 40 | #include <linux/i2c-algo-bit.h> |
0ade6386 | 41 | #include <drm/intel-gtt.h> |
aaa6fd2a | 42 | #include <linux/backlight.h> |
2911a35b | 43 | #include <linux/intel-iommu.h> |
742cbee8 | 44 | #include <linux/kref.h> |
9ee32fea | 45 | #include <linux/pm_qos.h> |
585fb111 | 46 | |
1da177e4 LT |
47 | /* General customization: |
48 | */ | |
49 | ||
50 | #define DRIVER_AUTHOR "Tungsten Graphics, Inc." | |
51 | ||
52 | #define DRIVER_NAME "i915" | |
53 | #define DRIVER_DESC "Intel Graphics" | |
673a394b | 54 | #define DRIVER_DATE "20080730" |
1da177e4 | 55 | |
317c35d1 JB |
56 | enum pipe { |
57 | PIPE_A = 0, | |
58 | PIPE_B, | |
9db4a9c7 JB |
59 | PIPE_C, |
60 | I915_MAX_PIPES | |
317c35d1 | 61 | }; |
9db4a9c7 | 62 | #define pipe_name(p) ((p) + 'A') |
317c35d1 | 63 | |
a5c961d1 PZ |
64 | enum transcoder { |
65 | TRANSCODER_A = 0, | |
66 | TRANSCODER_B, | |
67 | TRANSCODER_C, | |
68 | TRANSCODER_EDP = 0xF, | |
69 | }; | |
70 | #define transcoder_name(t) ((t) + 'A') | |
71 | ||
80824003 JB |
72 | enum plane { |
73 | PLANE_A = 0, | |
74 | PLANE_B, | |
9db4a9c7 | 75 | PLANE_C, |
80824003 | 76 | }; |
9db4a9c7 | 77 | #define plane_name(p) ((p) + 'A') |
52440211 | 78 | |
06da8da2 VS |
79 | #define sprite_name(p, s) ((p) * dev_priv->num_plane + (s) + 'A') |
80 | ||
2b139522 ED |
81 | enum port { |
82 | PORT_A = 0, | |
83 | PORT_B, | |
84 | PORT_C, | |
85 | PORT_D, | |
86 | PORT_E, | |
87 | I915_MAX_PORTS | |
88 | }; | |
89 | #define port_name(p) ((p) + 'A') | |
90 | ||
b97186f0 PZ |
91 | enum intel_display_power_domain { |
92 | POWER_DOMAIN_PIPE_A, | |
93 | POWER_DOMAIN_PIPE_B, | |
94 | POWER_DOMAIN_PIPE_C, | |
95 | POWER_DOMAIN_PIPE_A_PANEL_FITTER, | |
96 | POWER_DOMAIN_PIPE_B_PANEL_FITTER, | |
97 | POWER_DOMAIN_PIPE_C_PANEL_FITTER, | |
98 | POWER_DOMAIN_TRANSCODER_A, | |
99 | POWER_DOMAIN_TRANSCODER_B, | |
100 | POWER_DOMAIN_TRANSCODER_C, | |
101 | POWER_DOMAIN_TRANSCODER_EDP = POWER_DOMAIN_TRANSCODER_A + 0xF, | |
102 | }; | |
103 | ||
104 | #define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A) | |
105 | #define POWER_DOMAIN_PIPE_PANEL_FITTER(pipe) \ | |
106 | ((pipe) + POWER_DOMAIN_PIPE_A_PANEL_FITTER) | |
107 | #define POWER_DOMAIN_TRANSCODER(tran) ((tran) + POWER_DOMAIN_TRANSCODER_A) | |
108 | ||
1d843f9d EE |
109 | enum hpd_pin { |
110 | HPD_NONE = 0, | |
111 | HPD_PORT_A = HPD_NONE, /* PORT_A is internal */ | |
112 | HPD_TV = HPD_NONE, /* TV is known to be unreliable */ | |
113 | HPD_CRT, | |
114 | HPD_SDVO_B, | |
115 | HPD_SDVO_C, | |
116 | HPD_PORT_B, | |
117 | HPD_PORT_C, | |
118 | HPD_PORT_D, | |
119 | HPD_NUM_PINS | |
120 | }; | |
121 | ||
2a2d5482 CW |
122 | #define I915_GEM_GPU_DOMAINS \ |
123 | (I915_GEM_DOMAIN_RENDER | \ | |
124 | I915_GEM_DOMAIN_SAMPLER | \ | |
125 | I915_GEM_DOMAIN_COMMAND | \ | |
126 | I915_GEM_DOMAIN_INSTRUCTION | \ | |
127 | I915_GEM_DOMAIN_VERTEX) | |
62fdfeaf | 128 | |
7eb552ae | 129 | #define for_each_pipe(p) for ((p) = 0; (p) < INTEL_INFO(dev)->num_pipes; (p)++) |
9db4a9c7 | 130 | |
6c2b7c12 DV |
131 | #define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \ |
132 | list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \ | |
133 | if ((intel_encoder)->base.crtc == (__crtc)) | |
134 | ||
e7b903d2 DV |
135 | struct drm_i915_private; |
136 | ||
46edb027 DV |
137 | enum intel_dpll_id { |
138 | DPLL_ID_PRIVATE = -1, /* non-shared dpll in use */ | |
139 | /* real shared dpll ids must be >= 0 */ | |
140 | DPLL_ID_PCH_PLL_A, | |
141 | DPLL_ID_PCH_PLL_B, | |
142 | }; | |
143 | #define I915_NUM_PLLS 2 | |
144 | ||
5358901f | 145 | struct intel_dpll_hw_state { |
66e985c0 | 146 | uint32_t dpll; |
8bcc2795 | 147 | uint32_t dpll_md; |
66e985c0 DV |
148 | uint32_t fp0; |
149 | uint32_t fp1; | |
5358901f DV |
150 | }; |
151 | ||
e72f9fbf | 152 | struct intel_shared_dpll { |
ee7b9f93 JB |
153 | int refcount; /* count of number of CRTCs sharing this PLL */ |
154 | int active; /* count of number of active CRTCs (i.e. DPMS on) */ | |
155 | bool on; /* is the PLL actually active? Disabled during modeset */ | |
46edb027 DV |
156 | const char *name; |
157 | /* should match the index in the dev_priv->shared_dplls array */ | |
158 | enum intel_dpll_id id; | |
5358901f | 159 | struct intel_dpll_hw_state hw_state; |
15bdd4cf DV |
160 | void (*mode_set)(struct drm_i915_private *dev_priv, |
161 | struct intel_shared_dpll *pll); | |
e7b903d2 DV |
162 | void (*enable)(struct drm_i915_private *dev_priv, |
163 | struct intel_shared_dpll *pll); | |
164 | void (*disable)(struct drm_i915_private *dev_priv, | |
165 | struct intel_shared_dpll *pll); | |
5358901f DV |
166 | bool (*get_hw_state)(struct drm_i915_private *dev_priv, |
167 | struct intel_shared_dpll *pll, | |
168 | struct intel_dpll_hw_state *hw_state); | |
ee7b9f93 | 169 | }; |
ee7b9f93 | 170 | |
e69d0bc1 DV |
171 | /* Used by dp and fdi links */ |
172 | struct intel_link_m_n { | |
173 | uint32_t tu; | |
174 | uint32_t gmch_m; | |
175 | uint32_t gmch_n; | |
176 | uint32_t link_m; | |
177 | uint32_t link_n; | |
178 | }; | |
179 | ||
180 | void intel_link_compute_m_n(int bpp, int nlanes, | |
181 | int pixel_clock, int link_clock, | |
182 | struct intel_link_m_n *m_n); | |
183 | ||
6441ab5f PZ |
184 | struct intel_ddi_plls { |
185 | int spll_refcount; | |
186 | int wrpll1_refcount; | |
187 | int wrpll2_refcount; | |
188 | }; | |
189 | ||
1da177e4 LT |
190 | /* Interface history: |
191 | * | |
192 | * 1.1: Original. | |
0d6aa60b DA |
193 | * 1.2: Add Power Management |
194 | * 1.3: Add vblank support | |
de227f5f | 195 | * 1.4: Fix cmdbuffer path, add heap destroy |
702880f2 | 196 | * 1.5: Add vblank pipe configuration |
2228ed67 MD |
197 | * 1.6: - New ioctl for scheduling buffer swaps on vertical blank |
198 | * - Support vertical blank on secondary display pipe | |
1da177e4 LT |
199 | */ |
200 | #define DRIVER_MAJOR 1 | |
2228ed67 | 201 | #define DRIVER_MINOR 6 |
1da177e4 LT |
202 | #define DRIVER_PATCHLEVEL 0 |
203 | ||
23bc5982 | 204 | #define WATCH_LISTS 0 |
42d6ab48 | 205 | #define WATCH_GTT 0 |
673a394b | 206 | |
71acb5eb DA |
207 | #define I915_GEM_PHYS_CURSOR_0 1 |
208 | #define I915_GEM_PHYS_CURSOR_1 2 | |
209 | #define I915_GEM_PHYS_OVERLAY_REGS 3 | |
210 | #define I915_MAX_PHYS_OBJECT (I915_GEM_PHYS_OVERLAY_REGS) | |
211 | ||
212 | struct drm_i915_gem_phys_object { | |
213 | int id; | |
214 | struct page **page_list; | |
215 | drm_dma_handle_t *handle; | |
05394f39 | 216 | struct drm_i915_gem_object *cur_obj; |
71acb5eb DA |
217 | }; |
218 | ||
0a3e67a4 JB |
219 | struct opregion_header; |
220 | struct opregion_acpi; | |
221 | struct opregion_swsci; | |
222 | struct opregion_asle; | |
223 | ||
8ee1c3db | 224 | struct intel_opregion { |
5bc4418b BW |
225 | struct opregion_header __iomem *header; |
226 | struct opregion_acpi __iomem *acpi; | |
227 | struct opregion_swsci __iomem *swsci; | |
228 | struct opregion_asle __iomem *asle; | |
229 | void __iomem *vbt; | |
01fe9dbd | 230 | u32 __iomem *lid_state; |
8ee1c3db | 231 | }; |
44834a67 | 232 | #define OPREGION_SIZE (8*1024) |
8ee1c3db | 233 | |
6ef3d427 CW |
234 | struct intel_overlay; |
235 | struct intel_overlay_error_state; | |
236 | ||
7c1c2871 DA |
237 | struct drm_i915_master_private { |
238 | drm_local_map_t *sarea; | |
239 | struct _drm_i915_sarea *sarea_priv; | |
240 | }; | |
de151cf6 | 241 | #define I915_FENCE_REG_NONE -1 |
42b5aeab VS |
242 | #define I915_MAX_NUM_FENCES 32 |
243 | /* 32 fences + sign bit for FENCE_REG_NONE */ | |
244 | #define I915_MAX_NUM_FENCE_BITS 6 | |
de151cf6 JB |
245 | |
246 | struct drm_i915_fence_reg { | |
007cc8ac | 247 | struct list_head lru_list; |
caea7476 | 248 | struct drm_i915_gem_object *obj; |
1690e1eb | 249 | int pin_count; |
de151cf6 | 250 | }; |
7c1c2871 | 251 | |
9b9d172d | 252 | struct sdvo_device_mapping { |
e957d772 | 253 | u8 initialized; |
9b9d172d | 254 | u8 dvo_port; |
255 | u8 slave_addr; | |
256 | u8 dvo_wiring; | |
e957d772 | 257 | u8 i2c_pin; |
b1083333 | 258 | u8 ddc_pin; |
9b9d172d | 259 | }; |
260 | ||
c4a1d9e4 CW |
261 | struct intel_display_error_state; |
262 | ||
63eeaf38 | 263 | struct drm_i915_error_state { |
742cbee8 | 264 | struct kref ref; |
63eeaf38 JB |
265 | u32 eir; |
266 | u32 pgtbl_er; | |
be998e2e | 267 | u32 ier; |
b9a3906b | 268 | u32 ccid; |
0f3b6849 CW |
269 | u32 derrmr; |
270 | u32 forcewake; | |
9574b3fe | 271 | bool waiting[I915_NUM_RINGS]; |
9db4a9c7 | 272 | u32 pipestat[I915_MAX_PIPES]; |
c1cd90ed DV |
273 | u32 tail[I915_NUM_RINGS]; |
274 | u32 head[I915_NUM_RINGS]; | |
0f3b6849 | 275 | u32 ctl[I915_NUM_RINGS]; |
d27b1e0e DV |
276 | u32 ipeir[I915_NUM_RINGS]; |
277 | u32 ipehr[I915_NUM_RINGS]; | |
278 | u32 instdone[I915_NUM_RINGS]; | |
279 | u32 acthd[I915_NUM_RINGS]; | |
7e3b8737 | 280 | u32 semaphore_mboxes[I915_NUM_RINGS][I915_NUM_RINGS - 1]; |
df2b23d9 | 281 | u32 semaphore_seqno[I915_NUM_RINGS][I915_NUM_RINGS - 1]; |
12f55818 | 282 | u32 rc_psmi[I915_NUM_RINGS]; /* sleep state */ |
7e3b8737 DV |
283 | /* our own tracking of ring head and tail */ |
284 | u32 cpu_ring_head[I915_NUM_RINGS]; | |
285 | u32 cpu_ring_tail[I915_NUM_RINGS]; | |
1d8f38f4 | 286 | u32 error; /* gen6+ */ |
71e172e8 | 287 | u32 err_int; /* gen7 */ |
c1cd90ed DV |
288 | u32 instpm[I915_NUM_RINGS]; |
289 | u32 instps[I915_NUM_RINGS]; | |
050ee91f | 290 | u32 extra_instdone[I915_NUM_INSTDONE_REG]; |
d27b1e0e | 291 | u32 seqno[I915_NUM_RINGS]; |
9df30794 | 292 | u64 bbaddr; |
33f3f518 DV |
293 | u32 fault_reg[I915_NUM_RINGS]; |
294 | u32 done_reg; | |
c1cd90ed | 295 | u32 faddr[I915_NUM_RINGS]; |
4b9de737 | 296 | u64 fence[I915_MAX_NUM_FENCES]; |
63eeaf38 | 297 | struct timeval time; |
52d39a21 CW |
298 | struct drm_i915_error_ring { |
299 | struct drm_i915_error_object { | |
300 | int page_count; | |
301 | u32 gtt_offset; | |
302 | u32 *pages[0]; | |
8c123e54 | 303 | } *ringbuffer, *batchbuffer, *ctx; |
52d39a21 CW |
304 | struct drm_i915_error_request { |
305 | long jiffies; | |
306 | u32 seqno; | |
ee4f42b1 | 307 | u32 tail; |
52d39a21 CW |
308 | } *requests; |
309 | int num_requests; | |
310 | } ring[I915_NUM_RINGS]; | |
9df30794 | 311 | struct drm_i915_error_buffer { |
a779e5ab | 312 | u32 size; |
9df30794 | 313 | u32 name; |
0201f1ec | 314 | u32 rseqno, wseqno; |
9df30794 CW |
315 | u32 gtt_offset; |
316 | u32 read_domains; | |
317 | u32 write_domain; | |
4b9de737 | 318 | s32 fence_reg:I915_MAX_NUM_FENCE_BITS; |
9df30794 CW |
319 | s32 pinned:2; |
320 | u32 tiling:2; | |
321 | u32 dirty:1; | |
322 | u32 purgeable:1; | |
5d1333fc | 323 | s32 ring:4; |
93dfb40c | 324 | u32 cache_level:2; |
95f5301d BW |
325 | } **active_bo, **pinned_bo; |
326 | u32 *active_bo_count, *pinned_bo_count; | |
6ef3d427 | 327 | struct intel_overlay_error_state *overlay; |
c4a1d9e4 | 328 | struct intel_display_error_state *display; |
63eeaf38 JB |
329 | }; |
330 | ||
b8cecdf5 | 331 | struct intel_crtc_config; |
0e8ffe1b | 332 | struct intel_crtc; |
ee9300bb DV |
333 | struct intel_limit; |
334 | struct dpll; | |
b8cecdf5 | 335 | |
e70236a8 | 336 | struct drm_i915_display_funcs { |
ee5382ae | 337 | bool (*fbc_enabled)(struct drm_device *dev); |
e70236a8 JB |
338 | void (*enable_fbc)(struct drm_crtc *crtc, unsigned long interval); |
339 | void (*disable_fbc)(struct drm_device *dev); | |
340 | int (*get_display_clock_speed)(struct drm_device *dev); | |
341 | int (*get_fifo_size)(struct drm_device *dev, int plane); | |
ee9300bb DV |
342 | /** |
343 | * find_dpll() - Find the best values for the PLL | |
344 | * @limit: limits for the PLL | |
345 | * @crtc: current CRTC | |
346 | * @target: target frequency in kHz | |
347 | * @refclk: reference clock frequency in kHz | |
348 | * @match_clock: if provided, @best_clock P divider must | |
349 | * match the P divider from @match_clock | |
350 | * used for LVDS downclocking | |
351 | * @best_clock: best PLL values found | |
352 | * | |
353 | * Returns true on success, false on failure. | |
354 | */ | |
355 | bool (*find_dpll)(const struct intel_limit *limit, | |
356 | struct drm_crtc *crtc, | |
357 | int target, int refclk, | |
358 | struct dpll *match_clock, | |
359 | struct dpll *best_clock); | |
d210246a | 360 | void (*update_wm)(struct drm_device *dev); |
adf3d35e VS |
361 | void (*update_sprite_wm)(struct drm_plane *plane, |
362 | struct drm_crtc *crtc, | |
4c4ff43a | 363 | uint32_t sprite_width, int pixel_size, |
bdd57d03 | 364 | bool enable, bool scaled); |
47fab737 | 365 | void (*modeset_global_resources)(struct drm_device *dev); |
0e8ffe1b DV |
366 | /* Returns the active state of the crtc, and if the crtc is active, |
367 | * fills out the pipe-config with the hw state. */ | |
368 | bool (*get_pipe_config)(struct intel_crtc *, | |
369 | struct intel_crtc_config *); | |
f1f644dc | 370 | void (*get_clock)(struct intel_crtc *, struct intel_crtc_config *); |
f564048e | 371 | int (*crtc_mode_set)(struct drm_crtc *crtc, |
f564048e EA |
372 | int x, int y, |
373 | struct drm_framebuffer *old_fb); | |
76e5a89c DV |
374 | void (*crtc_enable)(struct drm_crtc *crtc); |
375 | void (*crtc_disable)(struct drm_crtc *crtc); | |
ee7b9f93 | 376 | void (*off)(struct drm_crtc *crtc); |
e0dac65e WF |
377 | void (*write_eld)(struct drm_connector *connector, |
378 | struct drm_crtc *crtc); | |
674cf967 | 379 | void (*fdi_link_train)(struct drm_crtc *crtc); |
6067aaea | 380 | void (*init_clock_gating)(struct drm_device *dev); |
8c9f3aaf JB |
381 | int (*queue_flip)(struct drm_device *dev, struct drm_crtc *crtc, |
382 | struct drm_framebuffer *fb, | |
ed8d1975 KP |
383 | struct drm_i915_gem_object *obj, |
384 | uint32_t flags); | |
17638cd6 JB |
385 | int (*update_plane)(struct drm_crtc *crtc, struct drm_framebuffer *fb, |
386 | int x, int y); | |
20afbda2 | 387 | void (*hpd_irq_setup)(struct drm_device *dev); |
e70236a8 JB |
388 | /* clock updates for mode set */ |
389 | /* cursor updates */ | |
390 | /* render clock increase/decrease */ | |
391 | /* display clock increase/decrease */ | |
392 | /* pll clock increase/decrease */ | |
e70236a8 JB |
393 | }; |
394 | ||
907b28c5 | 395 | struct intel_uncore_funcs { |
990bbdad CW |
396 | void (*force_wake_get)(struct drm_i915_private *dev_priv); |
397 | void (*force_wake_put)(struct drm_i915_private *dev_priv); | |
398 | }; | |
399 | ||
907b28c5 CW |
400 | struct intel_uncore { |
401 | spinlock_t lock; /** lock is also taken in irq contexts. */ | |
402 | ||
403 | struct intel_uncore_funcs funcs; | |
404 | ||
405 | unsigned fifo_count; | |
406 | unsigned forcewake_count; | |
407 | }; | |
408 | ||
79fc46df DL |
409 | #define DEV_INFO_FOR_EACH_FLAG(func, sep) \ |
410 | func(is_mobile) sep \ | |
411 | func(is_i85x) sep \ | |
412 | func(is_i915g) sep \ | |
413 | func(is_i945gm) sep \ | |
414 | func(is_g33) sep \ | |
415 | func(need_gfx_hws) sep \ | |
416 | func(is_g4x) sep \ | |
417 | func(is_pineview) sep \ | |
418 | func(is_broadwater) sep \ | |
419 | func(is_crestline) sep \ | |
420 | func(is_ivybridge) sep \ | |
421 | func(is_valleyview) sep \ | |
422 | func(is_haswell) sep \ | |
423 | func(has_force_wake) sep \ | |
424 | func(has_fbc) sep \ | |
425 | func(has_pipe_cxsr) sep \ | |
426 | func(has_hotplug) sep \ | |
427 | func(cursor_needs_physical) sep \ | |
428 | func(has_overlay) sep \ | |
429 | func(overlay_needs_physical) sep \ | |
430 | func(supports_tv) sep \ | |
431 | func(has_bsd_ring) sep \ | |
432 | func(has_blt_ring) sep \ | |
f72a1183 | 433 | func(has_vebox_ring) sep \ |
dd93be58 | 434 | func(has_llc) sep \ |
30568c45 DL |
435 | func(has_ddi) sep \ |
436 | func(has_fpga_dbg) | |
c96ea64e | 437 | |
a587f779 DL |
438 | #define DEFINE_FLAG(name) u8 name:1 |
439 | #define SEP_SEMICOLON ; | |
c96ea64e | 440 | |
cfdf1fa2 | 441 | struct intel_device_info { |
10fce67a | 442 | u32 display_mmio_offset; |
7eb552ae | 443 | u8 num_pipes:3; |
c96c3a8c | 444 | u8 gen; |
a587f779 | 445 | DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG, SEP_SEMICOLON); |
cfdf1fa2 KH |
446 | }; |
447 | ||
a587f779 DL |
448 | #undef DEFINE_FLAG |
449 | #undef SEP_SEMICOLON | |
450 | ||
7faf1ab2 DV |
451 | enum i915_cache_level { |
452 | I915_CACHE_NONE = 0, | |
350ec881 CW |
453 | I915_CACHE_LLC, /* also used for snoopable memory on non-LLC */ |
454 | I915_CACHE_L3_LLC, /* gen7+, L3 sits between the domain specifc | |
455 | caches, eg sampler/render caches, and the | |
456 | large Last-Level-Cache. LLC is coherent with | |
457 | the CPU, but L3 is only visible to the GPU. */ | |
651d794f | 458 | I915_CACHE_WT, /* hsw:gt3e WriteThrough for scanouts */ |
7faf1ab2 DV |
459 | }; |
460 | ||
2d04befb KG |
461 | typedef uint32_t gen6_gtt_pte_t; |
462 | ||
853ba5d2 | 463 | struct i915_address_space { |
93bd8649 | 464 | struct drm_mm mm; |
853ba5d2 | 465 | struct drm_device *dev; |
a7bbbd63 | 466 | struct list_head global_link; |
853ba5d2 BW |
467 | unsigned long start; /* Start offset always 0 for dri2 */ |
468 | size_t total; /* size addr space maps (ex. 2GB for ggtt) */ | |
469 | ||
470 | struct { | |
471 | dma_addr_t addr; | |
472 | struct page *page; | |
473 | } scratch; | |
474 | ||
5cef07e1 BW |
475 | /** |
476 | * List of objects currently involved in rendering. | |
477 | * | |
478 | * Includes buffers having the contents of their GPU caches | |
479 | * flushed, not necessarily primitives. last_rendering_seqno | |
480 | * represents when the rendering involved will be completed. | |
481 | * | |
482 | * A reference is held on the buffer while on this list. | |
483 | */ | |
484 | struct list_head active_list; | |
485 | ||
486 | /** | |
487 | * LRU list of objects which are not in the ringbuffer and | |
488 | * are ready to unbind, but are still in the GTT. | |
489 | * | |
490 | * last_rendering_seqno is 0 while an object is in this list. | |
491 | * | |
492 | * A reference is not held on the buffer while on this list, | |
493 | * as merely being GTT-bound shouldn't prevent its being | |
494 | * freed, and we'll pull it off the list in the free path. | |
495 | */ | |
496 | struct list_head inactive_list; | |
497 | ||
853ba5d2 BW |
498 | /* FIXME: Need a more generic return type */ |
499 | gen6_gtt_pte_t (*pte_encode)(dma_addr_t addr, | |
500 | enum i915_cache_level level); | |
501 | void (*clear_range)(struct i915_address_space *vm, | |
502 | unsigned int first_entry, | |
503 | unsigned int num_entries); | |
504 | void (*insert_entries)(struct i915_address_space *vm, | |
505 | struct sg_table *st, | |
506 | unsigned int first_entry, | |
507 | enum i915_cache_level cache_level); | |
508 | void (*cleanup)(struct i915_address_space *vm); | |
509 | }; | |
510 | ||
5d4545ae BW |
511 | /* The Graphics Translation Table is the way in which GEN hardware translates a |
512 | * Graphics Virtual Address into a Physical Address. In addition to the normal | |
513 | * collateral associated with any va->pa translations GEN hardware also has a | |
514 | * portion of the GTT which can be mapped by the CPU and remain both coherent | |
515 | * and correct (in cases like swizzling). That region is referred to as GMADR in | |
516 | * the spec. | |
517 | */ | |
518 | struct i915_gtt { | |
853ba5d2 | 519 | struct i915_address_space base; |
baa09f5f | 520 | size_t stolen_size; /* Total size of stolen memory */ |
5d4545ae BW |
521 | |
522 | unsigned long mappable_end; /* End offset that we can CPU map */ | |
523 | struct io_mapping *mappable; /* Mapping to our CPU mappable region */ | |
524 | phys_addr_t mappable_base; /* PA of our GMADR */ | |
525 | ||
526 | /** "Graphics Stolen Memory" holds the global PTEs */ | |
527 | void __iomem *gsm; | |
a81cc00c BW |
528 | |
529 | bool do_idle_maps; | |
7faf1ab2 | 530 | |
911bdf0a | 531 | int mtrr; |
7faf1ab2 DV |
532 | |
533 | /* global gtt ops */ | |
baa09f5f | 534 | int (*gtt_probe)(struct drm_device *dev, size_t *gtt_total, |
41907ddc BW |
535 | size_t *stolen, phys_addr_t *mappable_base, |
536 | unsigned long *mappable_end); | |
5d4545ae | 537 | }; |
853ba5d2 | 538 | #define gtt_total_entries(gtt) ((gtt).base.total >> PAGE_SHIFT) |
5d4545ae | 539 | |
1d2a314c | 540 | struct i915_hw_ppgtt { |
853ba5d2 | 541 | struct i915_address_space base; |
1d2a314c DV |
542 | unsigned num_pd_entries; |
543 | struct page **pt_pages; | |
544 | uint32_t pd_offset; | |
545 | dma_addr_t *pt_dma_addr; | |
def886c3 | 546 | |
b7c36d25 | 547 | int (*enable)(struct drm_device *dev); |
1d2a314c DV |
548 | }; |
549 | ||
0b02e798 BW |
550 | /** |
551 | * A VMA represents a GEM BO that is bound into an address space. Therefore, a | |
552 | * VMA's presence cannot be guaranteed before binding, or after unbinding the | |
553 | * object into/from the address space. | |
554 | * | |
555 | * To make things as simple as possible (ie. no refcounting), a VMA's lifetime | |
2f633156 BW |
556 | * will always be <= an objects lifetime. So object refcounting should cover us. |
557 | */ | |
558 | struct i915_vma { | |
559 | struct drm_mm_node node; | |
560 | struct drm_i915_gem_object *obj; | |
561 | struct i915_address_space *vm; | |
562 | ||
ca191b13 BW |
563 | /** This object's place on the active/inactive lists */ |
564 | struct list_head mm_list; | |
565 | ||
2f633156 | 566 | struct list_head vma_link; /* Link in the object's VMA list */ |
82a55ad1 BW |
567 | |
568 | /** This vma's place in the batchbuffer or on the eviction list */ | |
569 | struct list_head exec_list; | |
570 | ||
27173f1f BW |
571 | /** |
572 | * Used for performing relocations during execbuffer insertion. | |
573 | */ | |
574 | struct hlist_node exec_node; | |
575 | unsigned long exec_handle; | |
576 | struct drm_i915_gem_exec_object2 *exec_entry; | |
577 | ||
1d2a314c DV |
578 | }; |
579 | ||
e59ec13d MK |
580 | struct i915_ctx_hang_stats { |
581 | /* This context had batch pending when hang was declared */ | |
582 | unsigned batch_pending; | |
583 | ||
584 | /* This context had batch active when hang was declared */ | |
585 | unsigned batch_active; | |
586 | }; | |
40521054 BW |
587 | |
588 | /* This must match up with the value previously used for execbuf2.rsvd1. */ | |
589 | #define DEFAULT_CONTEXT_ID 0 | |
590 | struct i915_hw_context { | |
dce3271b | 591 | struct kref ref; |
40521054 | 592 | int id; |
e0556841 | 593 | bool is_initialized; |
40521054 BW |
594 | struct drm_i915_file_private *file_priv; |
595 | struct intel_ring_buffer *ring; | |
596 | struct drm_i915_gem_object *obj; | |
e59ec13d | 597 | struct i915_ctx_hang_stats hang_stats; |
40521054 BW |
598 | }; |
599 | ||
5c3fe8b0 BW |
600 | struct i915_fbc { |
601 | unsigned long size; | |
602 | unsigned int fb_id; | |
603 | enum plane plane; | |
604 | int y; | |
605 | ||
606 | struct drm_mm_node *compressed_fb; | |
607 | struct drm_mm_node *compressed_llb; | |
608 | ||
609 | struct intel_fbc_work { | |
610 | struct delayed_work work; | |
611 | struct drm_crtc *crtc; | |
612 | struct drm_framebuffer *fb; | |
613 | int interval; | |
614 | } *fbc_work; | |
615 | ||
29ebf90f CW |
616 | enum no_fbc_reason { |
617 | FBC_OK, /* FBC is enabled */ | |
618 | FBC_UNSUPPORTED, /* FBC is not supported by this chipset */ | |
5c3fe8b0 BW |
619 | FBC_NO_OUTPUT, /* no outputs enabled to compress */ |
620 | FBC_STOLEN_TOO_SMALL, /* not enough space for buffers */ | |
621 | FBC_UNSUPPORTED_MODE, /* interlace or doublescanned mode */ | |
622 | FBC_MODE_TOO_LARGE, /* mode too large for compression */ | |
623 | FBC_BAD_PLANE, /* fbc not supported on plane */ | |
624 | FBC_NOT_TILED, /* buffer not tiled */ | |
625 | FBC_MULTIPLE_PIPES, /* more than one pipe active */ | |
626 | FBC_MODULE_PARAM, | |
627 | FBC_CHIP_DEFAULT, /* disabled by default on this chip */ | |
628 | } no_fbc_reason; | |
b5e50c3f JB |
629 | }; |
630 | ||
3f51e471 RV |
631 | enum no_psr_reason { |
632 | PSR_NO_SOURCE, /* Not supported on platform */ | |
633 | PSR_NO_SINK, /* Not supported by panel */ | |
105b7c11 | 634 | PSR_MODULE_PARAM, |
3f51e471 RV |
635 | PSR_CRTC_NOT_ACTIVE, |
636 | PSR_PWR_WELL_ENABLED, | |
637 | PSR_NOT_TILED, | |
638 | PSR_SPRITE_ENABLED, | |
639 | PSR_S3D_ENABLED, | |
640 | PSR_INTERLACED_ENABLED, | |
641 | PSR_HSW_NOT_DDIA, | |
642 | }; | |
5c3fe8b0 | 643 | |
3bad0781 | 644 | enum intel_pch { |
f0350830 | 645 | PCH_NONE = 0, /* No PCH present */ |
3bad0781 ZW |
646 | PCH_IBX, /* Ibexpeak PCH */ |
647 | PCH_CPT, /* Cougarpoint PCH */ | |
eb877ebf | 648 | PCH_LPT, /* Lynxpoint PCH */ |
40c7ead9 | 649 | PCH_NOP, |
3bad0781 ZW |
650 | }; |
651 | ||
988d6ee8 PZ |
652 | enum intel_sbi_destination { |
653 | SBI_ICLK, | |
654 | SBI_MPHY, | |
655 | }; | |
656 | ||
b690e96c | 657 | #define QUIRK_PIPEA_FORCE (1<<0) |
435793df | 658 | #define QUIRK_LVDS_SSC_DISABLE (1<<1) |
4dca20ef | 659 | #define QUIRK_INVERT_BRIGHTNESS (1<<2) |
e85843be | 660 | #define QUIRK_NO_PCH_PWM_ENABLE (1<<3) |
b690e96c | 661 | |
8be48d92 | 662 | struct intel_fbdev; |
1630fe75 | 663 | struct intel_fbc_work; |
38651674 | 664 | |
c2b9152f DV |
665 | struct intel_gmbus { |
666 | struct i2c_adapter adapter; | |
f2ce9faf | 667 | u32 force_bit; |
c2b9152f | 668 | u32 reg0; |
36c785f0 | 669 | u32 gpio_reg; |
c167a6fc | 670 | struct i2c_algo_bit_data bit_algo; |
c2b9152f DV |
671 | struct drm_i915_private *dev_priv; |
672 | }; | |
673 | ||
f4c956ad | 674 | struct i915_suspend_saved_registers { |
ba8bbcf6 JB |
675 | u8 saveLBB; |
676 | u32 saveDSPACNTR; | |
677 | u32 saveDSPBCNTR; | |
e948e994 | 678 | u32 saveDSPARB; |
ba8bbcf6 JB |
679 | u32 savePIPEACONF; |
680 | u32 savePIPEBCONF; | |
681 | u32 savePIPEASRC; | |
682 | u32 savePIPEBSRC; | |
683 | u32 saveFPA0; | |
684 | u32 saveFPA1; | |
685 | u32 saveDPLL_A; | |
686 | u32 saveDPLL_A_MD; | |
687 | u32 saveHTOTAL_A; | |
688 | u32 saveHBLANK_A; | |
689 | u32 saveHSYNC_A; | |
690 | u32 saveVTOTAL_A; | |
691 | u32 saveVBLANK_A; | |
692 | u32 saveVSYNC_A; | |
693 | u32 saveBCLRPAT_A; | |
5586c8bc | 694 | u32 saveTRANSACONF; |
42048781 ZW |
695 | u32 saveTRANS_HTOTAL_A; |
696 | u32 saveTRANS_HBLANK_A; | |
697 | u32 saveTRANS_HSYNC_A; | |
698 | u32 saveTRANS_VTOTAL_A; | |
699 | u32 saveTRANS_VBLANK_A; | |
700 | u32 saveTRANS_VSYNC_A; | |
0da3ea12 | 701 | u32 savePIPEASTAT; |
ba8bbcf6 JB |
702 | u32 saveDSPASTRIDE; |
703 | u32 saveDSPASIZE; | |
704 | u32 saveDSPAPOS; | |
585fb111 | 705 | u32 saveDSPAADDR; |
ba8bbcf6 JB |
706 | u32 saveDSPASURF; |
707 | u32 saveDSPATILEOFF; | |
708 | u32 savePFIT_PGM_RATIOS; | |
0eb96d6e | 709 | u32 saveBLC_HIST_CTL; |
ba8bbcf6 JB |
710 | u32 saveBLC_PWM_CTL; |
711 | u32 saveBLC_PWM_CTL2; | |
42048781 ZW |
712 | u32 saveBLC_CPU_PWM_CTL; |
713 | u32 saveBLC_CPU_PWM_CTL2; | |
ba8bbcf6 JB |
714 | u32 saveFPB0; |
715 | u32 saveFPB1; | |
716 | u32 saveDPLL_B; | |
717 | u32 saveDPLL_B_MD; | |
718 | u32 saveHTOTAL_B; | |
719 | u32 saveHBLANK_B; | |
720 | u32 saveHSYNC_B; | |
721 | u32 saveVTOTAL_B; | |
722 | u32 saveVBLANK_B; | |
723 | u32 saveVSYNC_B; | |
724 | u32 saveBCLRPAT_B; | |
5586c8bc | 725 | u32 saveTRANSBCONF; |
42048781 ZW |
726 | u32 saveTRANS_HTOTAL_B; |
727 | u32 saveTRANS_HBLANK_B; | |
728 | u32 saveTRANS_HSYNC_B; | |
729 | u32 saveTRANS_VTOTAL_B; | |
730 | u32 saveTRANS_VBLANK_B; | |
731 | u32 saveTRANS_VSYNC_B; | |
0da3ea12 | 732 | u32 savePIPEBSTAT; |
ba8bbcf6 JB |
733 | u32 saveDSPBSTRIDE; |
734 | u32 saveDSPBSIZE; | |
735 | u32 saveDSPBPOS; | |
585fb111 | 736 | u32 saveDSPBADDR; |
ba8bbcf6 JB |
737 | u32 saveDSPBSURF; |
738 | u32 saveDSPBTILEOFF; | |
585fb111 JB |
739 | u32 saveVGA0; |
740 | u32 saveVGA1; | |
741 | u32 saveVGA_PD; | |
ba8bbcf6 JB |
742 | u32 saveVGACNTRL; |
743 | u32 saveADPA; | |
744 | u32 saveLVDS; | |
585fb111 JB |
745 | u32 savePP_ON_DELAYS; |
746 | u32 savePP_OFF_DELAYS; | |
ba8bbcf6 JB |
747 | u32 saveDVOA; |
748 | u32 saveDVOB; | |
749 | u32 saveDVOC; | |
750 | u32 savePP_ON; | |
751 | u32 savePP_OFF; | |
752 | u32 savePP_CONTROL; | |
585fb111 | 753 | u32 savePP_DIVISOR; |
ba8bbcf6 JB |
754 | u32 savePFIT_CONTROL; |
755 | u32 save_palette_a[256]; | |
756 | u32 save_palette_b[256]; | |
06027f91 | 757 | u32 saveDPFC_CB_BASE; |
ba8bbcf6 JB |
758 | u32 saveFBC_CFB_BASE; |
759 | u32 saveFBC_LL_BASE; | |
760 | u32 saveFBC_CONTROL; | |
761 | u32 saveFBC_CONTROL2; | |
0da3ea12 JB |
762 | u32 saveIER; |
763 | u32 saveIIR; | |
764 | u32 saveIMR; | |
42048781 ZW |
765 | u32 saveDEIER; |
766 | u32 saveDEIMR; | |
767 | u32 saveGTIER; | |
768 | u32 saveGTIMR; | |
769 | u32 saveFDI_RXA_IMR; | |
770 | u32 saveFDI_RXB_IMR; | |
1f84e550 | 771 | u32 saveCACHE_MODE_0; |
1f84e550 | 772 | u32 saveMI_ARB_STATE; |
ba8bbcf6 JB |
773 | u32 saveSWF0[16]; |
774 | u32 saveSWF1[16]; | |
775 | u32 saveSWF2[3]; | |
776 | u8 saveMSR; | |
777 | u8 saveSR[8]; | |
123f794f | 778 | u8 saveGR[25]; |
ba8bbcf6 | 779 | u8 saveAR_INDEX; |
a59e122a | 780 | u8 saveAR[21]; |
ba8bbcf6 | 781 | u8 saveDACMASK; |
a59e122a | 782 | u8 saveCR[37]; |
4b9de737 | 783 | uint64_t saveFENCE[I915_MAX_NUM_FENCES]; |
1fd1c624 EA |
784 | u32 saveCURACNTR; |
785 | u32 saveCURAPOS; | |
786 | u32 saveCURABASE; | |
787 | u32 saveCURBCNTR; | |
788 | u32 saveCURBPOS; | |
789 | u32 saveCURBBASE; | |
790 | u32 saveCURSIZE; | |
a4fc5ed6 KP |
791 | u32 saveDP_B; |
792 | u32 saveDP_C; | |
793 | u32 saveDP_D; | |
794 | u32 savePIPEA_GMCH_DATA_M; | |
795 | u32 savePIPEB_GMCH_DATA_M; | |
796 | u32 savePIPEA_GMCH_DATA_N; | |
797 | u32 savePIPEB_GMCH_DATA_N; | |
798 | u32 savePIPEA_DP_LINK_M; | |
799 | u32 savePIPEB_DP_LINK_M; | |
800 | u32 savePIPEA_DP_LINK_N; | |
801 | u32 savePIPEB_DP_LINK_N; | |
42048781 ZW |
802 | u32 saveFDI_RXA_CTL; |
803 | u32 saveFDI_TXA_CTL; | |
804 | u32 saveFDI_RXB_CTL; | |
805 | u32 saveFDI_TXB_CTL; | |
806 | u32 savePFA_CTL_1; | |
807 | u32 savePFB_CTL_1; | |
808 | u32 savePFA_WIN_SZ; | |
809 | u32 savePFB_WIN_SZ; | |
810 | u32 savePFA_WIN_POS; | |
811 | u32 savePFB_WIN_POS; | |
5586c8bc ZW |
812 | u32 savePCH_DREF_CONTROL; |
813 | u32 saveDISP_ARB_CTL; | |
814 | u32 savePIPEA_DATA_M1; | |
815 | u32 savePIPEA_DATA_N1; | |
816 | u32 savePIPEA_LINK_M1; | |
817 | u32 savePIPEA_LINK_N1; | |
818 | u32 savePIPEB_DATA_M1; | |
819 | u32 savePIPEB_DATA_N1; | |
820 | u32 savePIPEB_LINK_M1; | |
821 | u32 savePIPEB_LINK_N1; | |
b5b72e89 | 822 | u32 saveMCHBAR_RENDER_STANDBY; |
cda2bb78 | 823 | u32 savePCH_PORT_HOTPLUG; |
f4c956ad | 824 | }; |
c85aa885 DV |
825 | |
826 | struct intel_gen6_power_mgmt { | |
59cdb63d | 827 | /* work and pm_iir are protected by dev_priv->irq_lock */ |
c85aa885 DV |
828 | struct work_struct work; |
829 | u32 pm_iir; | |
59cdb63d DV |
830 | |
831 | /* On vlv we need to manually drop to Vmin with a delayed work. */ | |
832 | struct delayed_work vlv_work; | |
c85aa885 DV |
833 | |
834 | /* The below variables an all the rps hw state are protected by | |
835 | * dev->struct mutext. */ | |
836 | u8 cur_delay; | |
837 | u8 min_delay; | |
838 | u8 max_delay; | |
52ceb908 | 839 | u8 rpe_delay; |
31c77388 | 840 | u8 hw_max; |
1a01ab3b JB |
841 | |
842 | struct delayed_work delayed_resume_work; | |
4fc688ce JB |
843 | |
844 | /* | |
845 | * Protects RPS/RC6 register access and PCU communication. | |
846 | * Must be taken after struct_mutex if nested. | |
847 | */ | |
848 | struct mutex hw_lock; | |
c85aa885 DV |
849 | }; |
850 | ||
1a240d4d DV |
851 | /* defined intel_pm.c */ |
852 | extern spinlock_t mchdev_lock; | |
853 | ||
c85aa885 DV |
854 | struct intel_ilk_power_mgmt { |
855 | u8 cur_delay; | |
856 | u8 min_delay; | |
857 | u8 max_delay; | |
858 | u8 fmax; | |
859 | u8 fstart; | |
860 | ||
861 | u64 last_count1; | |
862 | unsigned long last_time1; | |
863 | unsigned long chipset_power; | |
864 | u64 last_count2; | |
865 | struct timespec last_time2; | |
866 | unsigned long gfx_power; | |
867 | u8 corr; | |
868 | ||
869 | int c_m; | |
870 | int r_t; | |
3e373948 DV |
871 | |
872 | struct drm_i915_gem_object *pwrctx; | |
873 | struct drm_i915_gem_object *renderctx; | |
c85aa885 DV |
874 | }; |
875 | ||
a38911a3 WX |
876 | /* Power well structure for haswell */ |
877 | struct i915_power_well { | |
878 | struct drm_device *device; | |
879 | spinlock_t lock; | |
880 | /* power well enable/disable usage count */ | |
881 | int count; | |
882 | int i915_request; | |
883 | }; | |
884 | ||
231f42a4 DV |
885 | struct i915_dri1_state { |
886 | unsigned allow_batchbuffer : 1; | |
887 | u32 __iomem *gfx_hws_cpu_addr; | |
888 | ||
889 | unsigned int cpp; | |
890 | int back_offset; | |
891 | int front_offset; | |
892 | int current_page; | |
893 | int page_flipping; | |
894 | ||
895 | uint32_t counter; | |
896 | }; | |
897 | ||
db1b76ca DV |
898 | struct i915_ums_state { |
899 | /** | |
900 | * Flag if the X Server, and thus DRM, is not currently in | |
901 | * control of the device. | |
902 | * | |
903 | * This is set between LeaveVT and EnterVT. It needs to be | |
904 | * replaced with a semaphore. It also needs to be | |
905 | * transitioned away from for kernel modesetting. | |
906 | */ | |
907 | int mm_suspended; | |
908 | }; | |
909 | ||
a4da4fa4 DV |
910 | struct intel_l3_parity { |
911 | u32 *remap_info; | |
912 | struct work_struct error_work; | |
913 | }; | |
914 | ||
4b5aed62 | 915 | struct i915_gem_mm { |
4b5aed62 DV |
916 | /** Memory allocator for GTT stolen memory */ |
917 | struct drm_mm stolen; | |
4b5aed62 DV |
918 | /** List of all objects in gtt_space. Used to restore gtt |
919 | * mappings on resume */ | |
920 | struct list_head bound_list; | |
921 | /** | |
922 | * List of objects which are not bound to the GTT (thus | |
923 | * are idle and not used by the GPU) but still have | |
924 | * (presumably uncached) pages still attached. | |
925 | */ | |
926 | struct list_head unbound_list; | |
927 | ||
928 | /** Usable portion of the GTT for GEM */ | |
929 | unsigned long stolen_base; /* limited to low memory (32-bit) */ | |
930 | ||
4b5aed62 DV |
931 | /** PPGTT used for aliasing the PPGTT with the GTT */ |
932 | struct i915_hw_ppgtt *aliasing_ppgtt; | |
933 | ||
934 | struct shrinker inactive_shrinker; | |
935 | bool shrinker_no_lock_stealing; | |
936 | ||
4b5aed62 DV |
937 | /** LRU list of objects with fence regs on them. */ |
938 | struct list_head fence_list; | |
939 | ||
940 | /** | |
941 | * We leave the user IRQ off as much as possible, | |
942 | * but this means that requests will finish and never | |
943 | * be retired once the system goes idle. Set a timer to | |
944 | * fire periodically while the ring is running. When it | |
945 | * fires, go retire requests. | |
946 | */ | |
947 | struct delayed_work retire_work; | |
948 | ||
949 | /** | |
950 | * Are we in a non-interruptible section of code like | |
951 | * modesetting? | |
952 | */ | |
953 | bool interruptible; | |
954 | ||
4b5aed62 DV |
955 | /** Bit 6 swizzling required for X tiling */ |
956 | uint32_t bit_6_swizzle_x; | |
957 | /** Bit 6 swizzling required for Y tiling */ | |
958 | uint32_t bit_6_swizzle_y; | |
959 | ||
960 | /* storage for physical objects */ | |
961 | struct drm_i915_gem_phys_object *phys_objs[I915_MAX_PHYS_OBJECT]; | |
962 | ||
963 | /* accounting, useful for userland debugging */ | |
c20e8355 | 964 | spinlock_t object_stat_lock; |
4b5aed62 DV |
965 | size_t object_memory; |
966 | u32 object_count; | |
967 | }; | |
968 | ||
edc3d884 MK |
969 | struct drm_i915_error_state_buf { |
970 | unsigned bytes; | |
971 | unsigned size; | |
972 | int err; | |
973 | u8 *buf; | |
974 | loff_t start; | |
975 | loff_t pos; | |
976 | }; | |
977 | ||
fc16b48b MK |
978 | struct i915_error_state_file_priv { |
979 | struct drm_device *dev; | |
980 | struct drm_i915_error_state *error; | |
981 | }; | |
982 | ||
99584db3 DV |
983 | struct i915_gpu_error { |
984 | /* For hangcheck timer */ | |
985 | #define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */ | |
986 | #define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD) | |
987 | struct timer_list hangcheck_timer; | |
99584db3 DV |
988 | |
989 | /* For reset and error_state handling. */ | |
990 | spinlock_t lock; | |
991 | /* Protected by the above dev->gpu_error.lock. */ | |
992 | struct drm_i915_error_state *first_error; | |
993 | struct work_struct work; | |
99584db3 DV |
994 | |
995 | unsigned long last_reset; | |
996 | ||
1f83fee0 | 997 | /** |
f69061be | 998 | * State variable and reset counter controlling the reset flow |
1f83fee0 | 999 | * |
f69061be DV |
1000 | * Upper bits are for the reset counter. This counter is used by the |
1001 | * wait_seqno code to race-free noticed that a reset event happened and | |
1002 | * that it needs to restart the entire ioctl (since most likely the | |
1003 | * seqno it waited for won't ever signal anytime soon). | |
1004 | * | |
1005 | * This is important for lock-free wait paths, where no contended lock | |
1006 | * naturally enforces the correct ordering between the bail-out of the | |
1007 | * waiter and the gpu reset work code. | |
1f83fee0 DV |
1008 | * |
1009 | * Lowest bit controls the reset state machine: Set means a reset is in | |
1010 | * progress. This state will (presuming we don't have any bugs) decay | |
1011 | * into either unset (successful reset) or the special WEDGED value (hw | |
1012 | * terminally sour). All waiters on the reset_queue will be woken when | |
1013 | * that happens. | |
1014 | */ | |
1015 | atomic_t reset_counter; | |
1016 | ||
1017 | /** | |
1018 | * Special values/flags for reset_counter | |
1019 | * | |
1020 | * Note that the code relies on | |
1021 | * I915_WEDGED & I915_RESET_IN_PROGRESS_FLAG | |
1022 | * being true. | |
1023 | */ | |
1024 | #define I915_RESET_IN_PROGRESS_FLAG 1 | |
1025 | #define I915_WEDGED 0xffffffff | |
1026 | ||
1027 | /** | |
1028 | * Waitqueue to signal when the reset has completed. Used by clients | |
1029 | * that wait for dev_priv->mm.wedged to settle. | |
1030 | */ | |
1031 | wait_queue_head_t reset_queue; | |
33196ded | 1032 | |
99584db3 DV |
1033 | /* For gpu hang simulation. */ |
1034 | unsigned int stop_rings; | |
1035 | }; | |
1036 | ||
b8efb17b ZR |
1037 | enum modeset_restore { |
1038 | MODESET_ON_LID_OPEN, | |
1039 | MODESET_DONE, | |
1040 | MODESET_SUSPENDED, | |
1041 | }; | |
1042 | ||
41aa3448 RV |
1043 | struct intel_vbt_data { |
1044 | struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */ | |
1045 | struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */ | |
1046 | ||
1047 | /* Feature bits */ | |
1048 | unsigned int int_tv_support:1; | |
1049 | unsigned int lvds_dither:1; | |
1050 | unsigned int lvds_vbt:1; | |
1051 | unsigned int int_crt_support:1; | |
1052 | unsigned int lvds_use_ssc:1; | |
1053 | unsigned int display_clock_mode:1; | |
1054 | unsigned int fdi_rx_polarity_inverted:1; | |
1055 | int lvds_ssc_freq; | |
1056 | unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */ | |
1057 | ||
1058 | /* eDP */ | |
1059 | int edp_rate; | |
1060 | int edp_lanes; | |
1061 | int edp_preemphasis; | |
1062 | int edp_vswing; | |
1063 | bool edp_initialized; | |
1064 | bool edp_support; | |
1065 | int edp_bpp; | |
1066 | struct edp_power_seq edp_pps; | |
1067 | ||
1068 | int crt_ddc_pin; | |
1069 | ||
1070 | int child_dev_num; | |
1071 | struct child_device_config *child_dev; | |
1072 | }; | |
1073 | ||
77c122bc VS |
1074 | enum intel_ddb_partitioning { |
1075 | INTEL_DDB_PART_1_2, | |
1076 | INTEL_DDB_PART_5_6, /* IVB+ */ | |
1077 | }; | |
1078 | ||
1fd527cc VS |
1079 | struct intel_wm_level { |
1080 | bool enable; | |
1081 | uint32_t pri_val; | |
1082 | uint32_t spr_val; | |
1083 | uint32_t cur_val; | |
1084 | uint32_t fbc_val; | |
1085 | }; | |
1086 | ||
c67a470b PZ |
1087 | /* |
1088 | * This struct tracks the state needed for the Package C8+ feature. | |
1089 | * | |
1090 | * Package states C8 and deeper are really deep PC states that can only be | |
1091 | * reached when all the devices on the system allow it, so even if the graphics | |
1092 | * device allows PC8+, it doesn't mean the system will actually get to these | |
1093 | * states. | |
1094 | * | |
1095 | * Our driver only allows PC8+ when all the outputs are disabled, the power well | |
1096 | * is disabled and the GPU is idle. When these conditions are met, we manually | |
1097 | * do the other conditions: disable the interrupts, clocks and switch LCPLL | |
1098 | * refclk to Fclk. | |
1099 | * | |
1100 | * When we really reach PC8 or deeper states (not just when we allow it) we lose | |
1101 | * the state of some registers, so when we come back from PC8+ we need to | |
1102 | * restore this state. We don't get into PC8+ if we're not in RC6, so we don't | |
1103 | * need to take care of the registers kept by RC6. | |
1104 | * | |
1105 | * The interrupt disabling is part of the requirements. We can only leave the | |
1106 | * PCH HPD interrupts enabled. If we're in PC8+ and we get another interrupt we | |
1107 | * can lock the machine. | |
1108 | * | |
1109 | * Ideally every piece of our code that needs PC8+ disabled would call | |
1110 | * hsw_disable_package_c8, which would increment disable_count and prevent the | |
1111 | * system from reaching PC8+. But we don't have a symmetric way to do this for | |
1112 | * everything, so we have the requirements_met and gpu_idle variables. When we | |
1113 | * switch requirements_met or gpu_idle to true we decrease disable_count, and | |
1114 | * increase it in the opposite case. The requirements_met variable is true when | |
1115 | * all the CRTCs, encoders and the power well are disabled. The gpu_idle | |
1116 | * variable is true when the GPU is idle. | |
1117 | * | |
1118 | * In addition to everything, we only actually enable PC8+ if disable_count | |
1119 | * stays at zero for at least some seconds. This is implemented with the | |
1120 | * enable_work variable. We do this so we don't enable/disable PC8 dozens of | |
1121 | * consecutive times when all screens are disabled and some background app | |
1122 | * queries the state of our connectors, or we have some application constantly | |
1123 | * waking up to use the GPU. Only after the enable_work function actually | |
1124 | * enables PC8+ the "enable" variable will become true, which means that it can | |
1125 | * be false even if disable_count is 0. | |
1126 | * | |
1127 | * The irqs_disabled variable becomes true exactly after we disable the IRQs and | |
1128 | * goes back to false exactly before we reenable the IRQs. We use this variable | |
1129 | * to check if someone is trying to enable/disable IRQs while they're supposed | |
1130 | * to be disabled. This shouldn't happen and we'll print some error messages in | |
1131 | * case it happens, but if it actually happens we'll also update the variables | |
1132 | * inside struct regsave so when we restore the IRQs they will contain the | |
1133 | * latest expected values. | |
1134 | * | |
1135 | * For more, read "Display Sequences for Package C8" on our documentation. | |
1136 | */ | |
1137 | struct i915_package_c8 { | |
1138 | bool requirements_met; | |
1139 | bool gpu_idle; | |
1140 | bool irqs_disabled; | |
1141 | /* Only true after the delayed work task actually enables it. */ | |
1142 | bool enabled; | |
1143 | int disable_count; | |
1144 | struct mutex lock; | |
1145 | struct delayed_work enable_work; | |
1146 | ||
1147 | struct { | |
1148 | uint32_t deimr; | |
1149 | uint32_t sdeimr; | |
1150 | uint32_t gtimr; | |
1151 | uint32_t gtier; | |
1152 | uint32_t gen6_pmimr; | |
1153 | } regsave; | |
1154 | }; | |
1155 | ||
f4c956ad DV |
1156 | typedef struct drm_i915_private { |
1157 | struct drm_device *dev; | |
42dcedd4 | 1158 | struct kmem_cache *slab; |
f4c956ad DV |
1159 | |
1160 | const struct intel_device_info *info; | |
1161 | ||
1162 | int relative_constants_mode; | |
1163 | ||
1164 | void __iomem *regs; | |
1165 | ||
907b28c5 | 1166 | struct intel_uncore uncore; |
f4c956ad DV |
1167 | |
1168 | struct intel_gmbus gmbus[GMBUS_NUM_PORTS]; | |
1169 | ||
28c70f16 | 1170 | |
f4c956ad DV |
1171 | /** gmbus_mutex protects against concurrent usage of the single hw gmbus |
1172 | * controller on different i2c buses. */ | |
1173 | struct mutex gmbus_mutex; | |
1174 | ||
1175 | /** | |
1176 | * Base address of the gmbus and gpio block. | |
1177 | */ | |
1178 | uint32_t gpio_mmio_base; | |
1179 | ||
28c70f16 DV |
1180 | wait_queue_head_t gmbus_wait_queue; |
1181 | ||
f4c956ad DV |
1182 | struct pci_dev *bridge_dev; |
1183 | struct intel_ring_buffer ring[I915_NUM_RINGS]; | |
f72b3435 | 1184 | uint32_t last_seqno, next_seqno; |
f4c956ad DV |
1185 | |
1186 | drm_dma_handle_t *status_page_dmah; | |
f4c956ad DV |
1187 | struct resource mch_res; |
1188 | ||
1189 | atomic_t irq_received; | |
1190 | ||
1191 | /* protects the irq masks */ | |
1192 | spinlock_t irq_lock; | |
1193 | ||
9ee32fea DV |
1194 | /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */ |
1195 | struct pm_qos_request pm_qos; | |
1196 | ||
f4c956ad | 1197 | /* DPIO indirect register protection */ |
09153000 | 1198 | struct mutex dpio_lock; |
f4c956ad DV |
1199 | |
1200 | /** Cached value of IMR to avoid reads in updating the bitfield */ | |
f4c956ad DV |
1201 | u32 irq_mask; |
1202 | u32 gt_irq_mask; | |
605cd25b | 1203 | u32 pm_irq_mask; |
f4c956ad | 1204 | |
f4c956ad | 1205 | struct work_struct hotplug_work; |
52d7eced | 1206 | bool enable_hotplug_processing; |
b543fb04 EE |
1207 | struct { |
1208 | unsigned long hpd_last_jiffies; | |
1209 | int hpd_cnt; | |
1210 | enum { | |
1211 | HPD_ENABLED = 0, | |
1212 | HPD_DISABLED = 1, | |
1213 | HPD_MARK_DISABLED = 2 | |
1214 | } hpd_mark; | |
1215 | } hpd_stats[HPD_NUM_PINS]; | |
142e2398 | 1216 | u32 hpd_event_bits; |
ac4c16c5 | 1217 | struct timer_list hotplug_reenable_timer; |
f4c956ad | 1218 | |
7f1f3851 | 1219 | int num_plane; |
f4c956ad | 1220 | |
5c3fe8b0 | 1221 | struct i915_fbc fbc; |
f4c956ad | 1222 | struct intel_opregion opregion; |
41aa3448 | 1223 | struct intel_vbt_data vbt; |
f4c956ad DV |
1224 | |
1225 | /* overlay */ | |
1226 | struct intel_overlay *overlay; | |
2c6602df | 1227 | unsigned int sprite_scaling_enabled; |
f4c956ad | 1228 | |
31ad8ec6 JN |
1229 | /* backlight */ |
1230 | struct { | |
1231 | int level; | |
1232 | bool enabled; | |
8ba2d185 | 1233 | spinlock_t lock; /* bl registers and the above bl fields */ |
31ad8ec6 JN |
1234 | struct backlight_device *device; |
1235 | } backlight; | |
1236 | ||
f4c956ad | 1237 | /* LVDS info */ |
f4c956ad DV |
1238 | bool no_aux_handshake; |
1239 | ||
f4c956ad DV |
1240 | struct drm_i915_fence_reg fence_regs[I915_MAX_NUM_FENCES]; /* assume 965 */ |
1241 | int fence_reg_start; /* 4 if userland hasn't ioctl'd us yet */ | |
1242 | int num_fence_regs; /* 8 on pre-965, 16 otherwise */ | |
1243 | ||
1244 | unsigned int fsb_freq, mem_freq, is_ddr3; | |
1245 | ||
645416f5 DV |
1246 | /** |
1247 | * wq - Driver workqueue for GEM. | |
1248 | * | |
1249 | * NOTE: Work items scheduled here are not allowed to grab any modeset | |
1250 | * locks, for otherwise the flushing done in the pageflip code will | |
1251 | * result in deadlocks. | |
1252 | */ | |
f4c956ad DV |
1253 | struct workqueue_struct *wq; |
1254 | ||
1255 | /* Display functions */ | |
1256 | struct drm_i915_display_funcs display; | |
1257 | ||
1258 | /* PCH chipset type */ | |
1259 | enum intel_pch pch_type; | |
17a303ec | 1260 | unsigned short pch_id; |
f4c956ad DV |
1261 | |
1262 | unsigned long quirks; | |
1263 | ||
b8efb17b ZR |
1264 | enum modeset_restore modeset_restore; |
1265 | struct mutex modeset_restore_lock; | |
673a394b | 1266 | |
a7bbbd63 | 1267 | struct list_head vm_list; /* Global list of all address spaces */ |
853ba5d2 | 1268 | struct i915_gtt gtt; /* VMA representing the global address space */ |
5d4545ae | 1269 | |
4b5aed62 | 1270 | struct i915_gem_mm mm; |
8781342d | 1271 | |
8781342d DV |
1272 | /* Kernel Modesetting */ |
1273 | ||
9b9d172d | 1274 | struct sdvo_device_mapping sdvo_mappings[2]; |
652c393a | 1275 | |
27f8227b JB |
1276 | struct drm_crtc *plane_to_crtc_mapping[3]; |
1277 | struct drm_crtc *pipe_to_crtc_mapping[3]; | |
6b95a207 KH |
1278 | wait_queue_head_t pending_flip_queue; |
1279 | ||
e72f9fbf DV |
1280 | int num_shared_dpll; |
1281 | struct intel_shared_dpll shared_dplls[I915_NUM_PLLS]; | |
6441ab5f | 1282 | struct intel_ddi_plls ddi_plls; |
ee7b9f93 | 1283 | |
652c393a JB |
1284 | /* Reclocking support */ |
1285 | bool render_reclock_avail; | |
1286 | bool lvds_downclock_avail; | |
18f9ed12 ZY |
1287 | /* indicates the reduced downclock for LVDS*/ |
1288 | int lvds_downclock; | |
652c393a | 1289 | u16 orig_clock; |
f97108d1 | 1290 | |
c4804411 | 1291 | bool mchbar_need_disable; |
f97108d1 | 1292 | |
a4da4fa4 DV |
1293 | struct intel_l3_parity l3_parity; |
1294 | ||
59124506 BW |
1295 | /* Cannot be determined by PCIID. You must always read a register. */ |
1296 | size_t ellc_size; | |
1297 | ||
c6a828d3 | 1298 | /* gen6+ rps state */ |
c85aa885 | 1299 | struct intel_gen6_power_mgmt rps; |
c6a828d3 | 1300 | |
20e4d407 DV |
1301 | /* ilk-only ips/rps state. Everything in here is protected by the global |
1302 | * mchdev_lock in intel_pm.c */ | |
c85aa885 | 1303 | struct intel_ilk_power_mgmt ips; |
b5e50c3f | 1304 | |
a38911a3 WX |
1305 | /* Haswell power well */ |
1306 | struct i915_power_well power_well; | |
1307 | ||
3f51e471 RV |
1308 | enum no_psr_reason no_psr_reason; |
1309 | ||
99584db3 | 1310 | struct i915_gpu_error gpu_error; |
ae681d96 | 1311 | |
c9cddffc JB |
1312 | struct drm_i915_gem_object *vlv_pctx; |
1313 | ||
8be48d92 DA |
1314 | /* list of fbdev register on this device */ |
1315 | struct intel_fbdev *fbdev; | |
e953fd7b | 1316 | |
073f34d9 JB |
1317 | /* |
1318 | * The console may be contended at resume, but we don't | |
1319 | * want it to block on it. | |
1320 | */ | |
1321 | struct work_struct console_resume_work; | |
1322 | ||
e953fd7b | 1323 | struct drm_property *broadcast_rgb_property; |
3f43c48d | 1324 | struct drm_property *force_audio_property; |
e3689190 | 1325 | |
254f965c BW |
1326 | bool hw_contexts_disabled; |
1327 | uint32_t hw_context_size; | |
f4c956ad | 1328 | |
3e68320e | 1329 | u32 fdi_rx_config; |
68d18ad7 | 1330 | |
f4c956ad | 1331 | struct i915_suspend_saved_registers regfile; |
231f42a4 | 1332 | |
53615a5e VS |
1333 | struct { |
1334 | /* | |
1335 | * Raw watermark latency values: | |
1336 | * in 0.1us units for WM0, | |
1337 | * in 0.5us units for WM1+. | |
1338 | */ | |
1339 | /* primary */ | |
1340 | uint16_t pri_latency[5]; | |
1341 | /* sprite */ | |
1342 | uint16_t spr_latency[5]; | |
1343 | /* cursor */ | |
1344 | uint16_t cur_latency[5]; | |
1345 | } wm; | |
1346 | ||
c67a470b PZ |
1347 | struct i915_package_c8 pc8; |
1348 | ||
231f42a4 DV |
1349 | /* Old dri1 support infrastructure, beware the dragons ya fools entering |
1350 | * here! */ | |
1351 | struct i915_dri1_state dri1; | |
db1b76ca DV |
1352 | /* Old ums support infrastructure, same warning applies. */ |
1353 | struct i915_ums_state ums; | |
1da177e4 LT |
1354 | } drm_i915_private_t; |
1355 | ||
2c1792a1 CW |
1356 | static inline struct drm_i915_private *to_i915(const struct drm_device *dev) |
1357 | { | |
1358 | return dev->dev_private; | |
1359 | } | |
1360 | ||
b4519513 CW |
1361 | /* Iterate over initialised rings */ |
1362 | #define for_each_ring(ring__, dev_priv__, i__) \ | |
1363 | for ((i__) = 0; (i__) < I915_NUM_RINGS; (i__)++) \ | |
1364 | if (((ring__) = &(dev_priv__)->ring[(i__)]), intel_ring_initialized((ring__))) | |
1365 | ||
b1d7e4b4 WF |
1366 | enum hdmi_force_audio { |
1367 | HDMI_AUDIO_OFF_DVI = -2, /* no aux data for HDMI-DVI converter */ | |
1368 | HDMI_AUDIO_OFF, /* force turn off HDMI audio */ | |
1369 | HDMI_AUDIO_AUTO, /* trust EDID */ | |
1370 | HDMI_AUDIO_ON, /* force turn on HDMI audio */ | |
1371 | }; | |
1372 | ||
190d6cd5 | 1373 | #define I915_GTT_OFFSET_NONE ((u32)-1) |
ed2f3452 | 1374 | |
37e680a1 CW |
1375 | struct drm_i915_gem_object_ops { |
1376 | /* Interface between the GEM object and its backing storage. | |
1377 | * get_pages() is called once prior to the use of the associated set | |
1378 | * of pages before to binding them into the GTT, and put_pages() is | |
1379 | * called after we no longer need them. As we expect there to be | |
1380 | * associated cost with migrating pages between the backing storage | |
1381 | * and making them available for the GPU (e.g. clflush), we may hold | |
1382 | * onto the pages after they are no longer referenced by the GPU | |
1383 | * in case they may be used again shortly (for example migrating the | |
1384 | * pages to a different memory domain within the GTT). put_pages() | |
1385 | * will therefore most likely be called when the object itself is | |
1386 | * being released or under memory pressure (where we attempt to | |
1387 | * reap pages for the shrinker). | |
1388 | */ | |
1389 | int (*get_pages)(struct drm_i915_gem_object *); | |
1390 | void (*put_pages)(struct drm_i915_gem_object *); | |
1391 | }; | |
1392 | ||
673a394b | 1393 | struct drm_i915_gem_object { |
c397b908 | 1394 | struct drm_gem_object base; |
673a394b | 1395 | |
37e680a1 CW |
1396 | const struct drm_i915_gem_object_ops *ops; |
1397 | ||
2f633156 BW |
1398 | /** List of VMAs backed by this object */ |
1399 | struct list_head vma_list; | |
1400 | ||
c1ad11fc CW |
1401 | /** Stolen memory for this object, instead of being backed by shmem. */ |
1402 | struct drm_mm_node *stolen; | |
35c20a60 | 1403 | struct list_head global_list; |
673a394b | 1404 | |
69dc4987 | 1405 | struct list_head ring_list; |
b25cb2f8 BW |
1406 | /** Used in execbuf to temporarily hold a ref */ |
1407 | struct list_head obj_exec_link; | |
673a394b EA |
1408 | |
1409 | /** | |
65ce3027 CW |
1410 | * This is set if the object is on the active lists (has pending |
1411 | * rendering and so a non-zero seqno), and is not set if it i s on | |
1412 | * inactive (ready to be unbound) list. | |
673a394b | 1413 | */ |
0206e353 | 1414 | unsigned int active:1; |
673a394b EA |
1415 | |
1416 | /** | |
1417 | * This is set if the object has been written to since last bound | |
1418 | * to the GTT | |
1419 | */ | |
0206e353 | 1420 | unsigned int dirty:1; |
778c3544 DV |
1421 | |
1422 | /** | |
1423 | * Fence register bits (if any) for this object. Will be set | |
1424 | * as needed when mapped into the GTT. | |
1425 | * Protected by dev->struct_mutex. | |
778c3544 | 1426 | */ |
4b9de737 | 1427 | signed int fence_reg:I915_MAX_NUM_FENCE_BITS; |
778c3544 | 1428 | |
778c3544 DV |
1429 | /** |
1430 | * Advice: are the backing pages purgeable? | |
1431 | */ | |
0206e353 | 1432 | unsigned int madv:2; |
778c3544 | 1433 | |
778c3544 DV |
1434 | /** |
1435 | * Current tiling mode for the object. | |
1436 | */ | |
0206e353 | 1437 | unsigned int tiling_mode:2; |
5d82e3e6 CW |
1438 | /** |
1439 | * Whether the tiling parameters for the currently associated fence | |
1440 | * register have changed. Note that for the purposes of tracking | |
1441 | * tiling changes we also treat the unfenced register, the register | |
1442 | * slot that the object occupies whilst it executes a fenced | |
1443 | * command (such as BLT on gen2/3), as a "fence". | |
1444 | */ | |
1445 | unsigned int fence_dirty:1; | |
778c3544 DV |
1446 | |
1447 | /** How many users have pinned this object in GTT space. The following | |
1448 | * users can each hold at most one reference: pwrite/pread, pin_ioctl | |
1449 | * (via user_pin_count), execbuffer (objects are not allowed multiple | |
1450 | * times for the same batchbuffer), and the framebuffer code. When | |
1451 | * switching/pageflipping, the framebuffer code has at most two buffers | |
1452 | * pinned per crtc. | |
1453 | * | |
1454 | * In the worst case this is 1 + 1 + 1 + 2*2 = 7. That would fit into 3 | |
1455 | * bits with absolutely no headroom. So use 4 bits. */ | |
0206e353 | 1456 | unsigned int pin_count:4; |
778c3544 | 1457 | #define DRM_I915_GEM_OBJECT_MAX_PIN_COUNT 0xf |
673a394b | 1458 | |
75e9e915 DV |
1459 | /** |
1460 | * Is the object at the current location in the gtt mappable and | |
1461 | * fenceable? Used to avoid costly recalculations. | |
1462 | */ | |
0206e353 | 1463 | unsigned int map_and_fenceable:1; |
75e9e915 | 1464 | |
fb7d516a DV |
1465 | /** |
1466 | * Whether the current gtt mapping needs to be mappable (and isn't just | |
1467 | * mappable by accident). Track pin and fault separate for a more | |
1468 | * accurate mappable working set. | |
1469 | */ | |
0206e353 AJ |
1470 | unsigned int fault_mappable:1; |
1471 | unsigned int pin_mappable:1; | |
cc98b413 | 1472 | unsigned int pin_display:1; |
fb7d516a | 1473 | |
caea7476 CW |
1474 | /* |
1475 | * Is the GPU currently using a fence to access this buffer, | |
1476 | */ | |
1477 | unsigned int pending_fenced_gpu_access:1; | |
1478 | unsigned int fenced_gpu_access:1; | |
1479 | ||
651d794f | 1480 | unsigned int cache_level:3; |
93dfb40c | 1481 | |
7bddb01f | 1482 | unsigned int has_aliasing_ppgtt_mapping:1; |
74898d7e | 1483 | unsigned int has_global_gtt_mapping:1; |
9da3da66 | 1484 | unsigned int has_dma_mapping:1; |
7bddb01f | 1485 | |
9da3da66 | 1486 | struct sg_table *pages; |
a5570178 | 1487 | int pages_pin_count; |
673a394b | 1488 | |
1286ff73 | 1489 | /* prime dma-buf support */ |
9a70cc2a DA |
1490 | void *dma_buf_vmapping; |
1491 | int vmapping_count; | |
1492 | ||
caea7476 CW |
1493 | struct intel_ring_buffer *ring; |
1494 | ||
1c293ea3 | 1495 | /** Breadcrumb of last rendering to the buffer. */ |
0201f1ec CW |
1496 | uint32_t last_read_seqno; |
1497 | uint32_t last_write_seqno; | |
caea7476 CW |
1498 | /** Breadcrumb of last fenced GPU access to the buffer. */ |
1499 | uint32_t last_fenced_seqno; | |
673a394b | 1500 | |
778c3544 | 1501 | /** Current tiling stride for the object, if it's tiled. */ |
de151cf6 | 1502 | uint32_t stride; |
673a394b | 1503 | |
280b713b | 1504 | /** Record of address bit 17 of each page at last unbind. */ |
d312ec25 | 1505 | unsigned long *bit_17; |
280b713b | 1506 | |
79e53945 JB |
1507 | /** User space pin count and filp owning the pin */ |
1508 | uint32_t user_pin_count; | |
1509 | struct drm_file *pin_filp; | |
71acb5eb DA |
1510 | |
1511 | /** for phy allocated objects */ | |
1512 | struct drm_i915_gem_phys_object *phys_obj; | |
673a394b | 1513 | }; |
b45305fc | 1514 | #define to_gem_object(obj) (&((struct drm_i915_gem_object *)(obj))->base) |
673a394b | 1515 | |
62b8b215 | 1516 | #define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base) |
23010e43 | 1517 | |
673a394b EA |
1518 | /** |
1519 | * Request queue structure. | |
1520 | * | |
1521 | * The request queue allows us to note sequence numbers that have been emitted | |
1522 | * and may be associated with active buffers to be retired. | |
1523 | * | |
1524 | * By keeping this list, we can avoid having to do questionable | |
1525 | * sequence-number comparisons on buffer last_rendering_seqnos, and associate | |
1526 | * an emission time with seqnos for tracking how far ahead of the GPU we are. | |
1527 | */ | |
1528 | struct drm_i915_gem_request { | |
852835f3 ZN |
1529 | /** On Which ring this request was generated */ |
1530 | struct intel_ring_buffer *ring; | |
1531 | ||
673a394b EA |
1532 | /** GEM sequence number associated with this request. */ |
1533 | uint32_t seqno; | |
1534 | ||
7d736f4f MK |
1535 | /** Position in the ringbuffer of the start of the request */ |
1536 | u32 head; | |
1537 | ||
1538 | /** Position in the ringbuffer of the end of the request */ | |
a71d8d94 CW |
1539 | u32 tail; |
1540 | ||
0e50e96b MK |
1541 | /** Context related to this request */ |
1542 | struct i915_hw_context *ctx; | |
1543 | ||
7d736f4f MK |
1544 | /** Batch buffer related to this request if any */ |
1545 | struct drm_i915_gem_object *batch_obj; | |
1546 | ||
673a394b EA |
1547 | /** Time at which this request was emitted, in jiffies. */ |
1548 | unsigned long emitted_jiffies; | |
1549 | ||
b962442e | 1550 | /** global list entry for this request */ |
673a394b | 1551 | struct list_head list; |
b962442e | 1552 | |
f787a5f5 | 1553 | struct drm_i915_file_private *file_priv; |
b962442e EA |
1554 | /** file_priv list entry for this request */ |
1555 | struct list_head client_list; | |
673a394b EA |
1556 | }; |
1557 | ||
1558 | struct drm_i915_file_private { | |
1559 | struct { | |
99057c81 | 1560 | spinlock_t lock; |
b962442e | 1561 | struct list_head request_list; |
673a394b | 1562 | } mm; |
40521054 | 1563 | struct idr context_idr; |
e59ec13d MK |
1564 | |
1565 | struct i915_ctx_hang_stats hang_stats; | |
673a394b EA |
1566 | }; |
1567 | ||
2c1792a1 | 1568 | #define INTEL_INFO(dev) (to_i915(dev)->info) |
cae5852d ZN |
1569 | |
1570 | #define IS_I830(dev) ((dev)->pci_device == 0x3577) | |
1571 | #define IS_845G(dev) ((dev)->pci_device == 0x2562) | |
1572 | #define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x) | |
1573 | #define IS_I865G(dev) ((dev)->pci_device == 0x2572) | |
1574 | #define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g) | |
1575 | #define IS_I915GM(dev) ((dev)->pci_device == 0x2592) | |
1576 | #define IS_I945G(dev) ((dev)->pci_device == 0x2772) | |
1577 | #define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm) | |
1578 | #define IS_BROADWATER(dev) (INTEL_INFO(dev)->is_broadwater) | |
1579 | #define IS_CRESTLINE(dev) (INTEL_INFO(dev)->is_crestline) | |
1580 | #define IS_GM45(dev) ((dev)->pci_device == 0x2A42) | |
1581 | #define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x) | |
1582 | #define IS_PINEVIEW_G(dev) ((dev)->pci_device == 0xa001) | |
1583 | #define IS_PINEVIEW_M(dev) ((dev)->pci_device == 0xa011) | |
1584 | #define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview) | |
1585 | #define IS_G33(dev) (INTEL_INFO(dev)->is_g33) | |
cae5852d | 1586 | #define IS_IRONLAKE_M(dev) ((dev)->pci_device == 0x0046) |
4b65177b | 1587 | #define IS_IVYBRIDGE(dev) (INTEL_INFO(dev)->is_ivybridge) |
8ab43976 JB |
1588 | #define IS_IVB_GT1(dev) ((dev)->pci_device == 0x0156 || \ |
1589 | (dev)->pci_device == 0x0152 || \ | |
1590 | (dev)->pci_device == 0x015a) | |
6547fbdb DV |
1591 | #define IS_SNB_GT1(dev) ((dev)->pci_device == 0x0102 || \ |
1592 | (dev)->pci_device == 0x0106 || \ | |
1593 | (dev)->pci_device == 0x010A) | |
70a3eb7a | 1594 | #define IS_VALLEYVIEW(dev) (INTEL_INFO(dev)->is_valleyview) |
4cae9ae0 | 1595 | #define IS_HASWELL(dev) (INTEL_INFO(dev)->is_haswell) |
cae5852d | 1596 | #define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile) |
ed1c9e2c PZ |
1597 | #define IS_HSW_EARLY_SDV(dev) (IS_HASWELL(dev) && \ |
1598 | ((dev)->pci_device & 0xFF00) == 0x0C00) | |
d567b07f PZ |
1599 | #define IS_ULT(dev) (IS_HASWELL(dev) && \ |
1600 | ((dev)->pci_device & 0xFF00) == 0x0A00) | |
cae5852d | 1601 | |
85436696 JB |
1602 | /* |
1603 | * The genX designation typically refers to the render engine, so render | |
1604 | * capability related checks should use IS_GEN, while display and other checks | |
1605 | * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular | |
1606 | * chips, etc.). | |
1607 | */ | |
cae5852d ZN |
1608 | #define IS_GEN2(dev) (INTEL_INFO(dev)->gen == 2) |
1609 | #define IS_GEN3(dev) (INTEL_INFO(dev)->gen == 3) | |
1610 | #define IS_GEN4(dev) (INTEL_INFO(dev)->gen == 4) | |
1611 | #define IS_GEN5(dev) (INTEL_INFO(dev)->gen == 5) | |
1612 | #define IS_GEN6(dev) (INTEL_INFO(dev)->gen == 6) | |
85436696 | 1613 | #define IS_GEN7(dev) (INTEL_INFO(dev)->gen == 7) |
cae5852d ZN |
1614 | |
1615 | #define HAS_BSD(dev) (INTEL_INFO(dev)->has_bsd_ring) | |
1616 | #define HAS_BLT(dev) (INTEL_INFO(dev)->has_blt_ring) | |
f72a1183 | 1617 | #define HAS_VEBOX(dev) (INTEL_INFO(dev)->has_vebox_ring) |
3d29b842 | 1618 | #define HAS_LLC(dev) (INTEL_INFO(dev)->has_llc) |
651d794f | 1619 | #define HAS_WT(dev) (IS_HASWELL(dev) && to_i915(dev)->ellc_size) |
cae5852d ZN |
1620 | #define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws) |
1621 | ||
254f965c | 1622 | #define HAS_HW_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 6) |
93553609 | 1623 | #define HAS_ALIASING_PPGTT(dev) (INTEL_INFO(dev)->gen >=6 && !IS_VALLEYVIEW(dev)) |
1d2a314c | 1624 | |
05394f39 | 1625 | #define HAS_OVERLAY(dev) (INTEL_INFO(dev)->has_overlay) |
cae5852d ZN |
1626 | #define OVERLAY_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->overlay_needs_physical) |
1627 | ||
b45305fc DV |
1628 | /* Early gen2 have a totally busted CS tlb and require pinned batches. */ |
1629 | #define HAS_BROKEN_CS_TLB(dev) (IS_I830(dev) || IS_845G(dev)) | |
1630 | ||
cae5852d ZN |
1631 | /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte |
1632 | * rows, which changed the alignment requirements and fence programming. | |
1633 | */ | |
1634 | #define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \ | |
1635 | IS_I915GM(dev))) | |
1636 | #define SUPPORTS_DIGITAL_OUTPUTS(dev) (!IS_GEN2(dev) && !IS_PINEVIEW(dev)) | |
1637 | #define SUPPORTS_INTEGRATED_HDMI(dev) (IS_G4X(dev) || IS_GEN5(dev)) | |
1638 | #define SUPPORTS_INTEGRATED_DP(dev) (IS_G4X(dev) || IS_GEN5(dev)) | |
1639 | #define SUPPORTS_EDP(dev) (IS_IRONLAKE_M(dev)) | |
1640 | #define SUPPORTS_TV(dev) (INTEL_INFO(dev)->supports_tv) | |
1641 | #define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug) | |
cae5852d ZN |
1642 | |
1643 | #define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2) | |
1644 | #define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr) | |
1645 | #define I915_HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc) | |
cae5852d | 1646 | |
f5adf94e DL |
1647 | #define HAS_IPS(dev) (IS_ULT(dev)) |
1648 | ||
dd93be58 | 1649 | #define HAS_DDI(dev) (INTEL_INFO(dev)->has_ddi) |
86d52df6 | 1650 | #define HAS_POWER_WELL(dev) (IS_HASWELL(dev)) |
30568c45 | 1651 | #define HAS_FPGA_DBG_UNCLAIMED(dev) (INTEL_INFO(dev)->has_fpga_dbg) |
affa9354 | 1652 | |
17a303ec PZ |
1653 | #define INTEL_PCH_DEVICE_ID_MASK 0xff00 |
1654 | #define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00 | |
1655 | #define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00 | |
1656 | #define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00 | |
1657 | #define INTEL_PCH_LPT_DEVICE_ID_TYPE 0x8c00 | |
1658 | #define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE 0x9c00 | |
1659 | ||
2c1792a1 | 1660 | #define INTEL_PCH_TYPE(dev) (to_i915(dev)->pch_type) |
eb877ebf | 1661 | #define HAS_PCH_LPT(dev) (INTEL_PCH_TYPE(dev) == PCH_LPT) |
cae5852d ZN |
1662 | #define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT) |
1663 | #define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX) | |
40c7ead9 | 1664 | #define HAS_PCH_NOP(dev) (INTEL_PCH_TYPE(dev) == PCH_NOP) |
45e6e3a1 | 1665 | #define HAS_PCH_SPLIT(dev) (INTEL_PCH_TYPE(dev) != PCH_NONE) |
cae5852d | 1666 | |
b7884eb4 DV |
1667 | #define HAS_FORCE_WAKE(dev) (INTEL_INFO(dev)->has_force_wake) |
1668 | ||
f27b9265 | 1669 | #define HAS_L3_GPU_CACHE(dev) (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) |
e1ef7cc2 | 1670 | |
c8735b0c BW |
1671 | #define GT_FREQUENCY_MULTIPLIER 50 |
1672 | ||
05394f39 CW |
1673 | #include "i915_trace.h" |
1674 | ||
83b7f9ac ED |
1675 | /** |
1676 | * RC6 is a special power stage which allows the GPU to enter an very | |
1677 | * low-voltage mode when idle, using down to 0V while at this stage. This | |
1678 | * stage is entered automatically when the GPU is idle when RC6 support is | |
1679 | * enabled, and as soon as new workload arises GPU wakes up automatically as well. | |
1680 | * | |
1681 | * There are different RC6 modes available in Intel GPU, which differentiate | |
1682 | * among each other with the latency required to enter and leave RC6 and | |
1683 | * voltage consumed by the GPU in different states. | |
1684 | * | |
1685 | * The combination of the following flags define which states GPU is allowed | |
1686 | * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and | |
1687 | * RC6pp is deepest RC6. Their support by hardware varies according to the | |
1688 | * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one | |
1689 | * which brings the most power savings; deeper states save more power, but | |
1690 | * require higher latency to switch to and wake up. | |
1691 | */ | |
1692 | #define INTEL_RC6_ENABLE (1<<0) | |
1693 | #define INTEL_RC6p_ENABLE (1<<1) | |
1694 | #define INTEL_RC6pp_ENABLE (1<<2) | |
1695 | ||
baa70943 | 1696 | extern const struct drm_ioctl_desc i915_ioctls[]; |
b3a83639 | 1697 | extern int i915_max_ioctl; |
a35d9d3c BW |
1698 | extern unsigned int i915_fbpercrtc __always_unused; |
1699 | extern int i915_panel_ignore_lid __read_mostly; | |
1700 | extern unsigned int i915_powersave __read_mostly; | |
f45b5557 | 1701 | extern int i915_semaphores __read_mostly; |
a35d9d3c | 1702 | extern unsigned int i915_lvds_downclock __read_mostly; |
121d527a | 1703 | extern int i915_lvds_channel_mode __read_mostly; |
4415e63b | 1704 | extern int i915_panel_use_ssc __read_mostly; |
a35d9d3c | 1705 | extern int i915_vbt_sdvo_panel_type __read_mostly; |
c0f372b3 | 1706 | extern int i915_enable_rc6 __read_mostly; |
4415e63b | 1707 | extern int i915_enable_fbc __read_mostly; |
a35d9d3c | 1708 | extern bool i915_enable_hangcheck __read_mostly; |
650dc07e | 1709 | extern int i915_enable_ppgtt __read_mostly; |
105b7c11 | 1710 | extern int i915_enable_psr __read_mostly; |
0a3af268 | 1711 | extern unsigned int i915_preliminary_hw_support __read_mostly; |
2124b72e | 1712 | extern int i915_disable_power_well __read_mostly; |
3c4ca58c | 1713 | extern int i915_enable_ips __read_mostly; |
2385bdf0 | 1714 | extern bool i915_fastboot __read_mostly; |
c67a470b | 1715 | extern int i915_enable_pc8 __read_mostly; |
90058745 | 1716 | extern int i915_pc8_timeout __read_mostly; |
0b74b508 | 1717 | extern bool i915_prefault_disable __read_mostly; |
b3a83639 | 1718 | |
6a9ee8af DA |
1719 | extern int i915_suspend(struct drm_device *dev, pm_message_t state); |
1720 | extern int i915_resume(struct drm_device *dev); | |
7c1c2871 DA |
1721 | extern int i915_master_create(struct drm_device *dev, struct drm_master *master); |
1722 | extern void i915_master_destroy(struct drm_device *dev, struct drm_master *master); | |
1723 | ||
1da177e4 | 1724 | /* i915_dma.c */ |
d05c617e | 1725 | void i915_update_dri1_breadcrumb(struct drm_device *dev); |
84b1fd10 | 1726 | extern void i915_kernel_lost_context(struct drm_device * dev); |
22eae947 | 1727 | extern int i915_driver_load(struct drm_device *, unsigned long flags); |
ba8bbcf6 | 1728 | extern int i915_driver_unload(struct drm_device *); |
673a394b | 1729 | extern int i915_driver_open(struct drm_device *dev, struct drm_file *file_priv); |
84b1fd10 | 1730 | extern void i915_driver_lastclose(struct drm_device * dev); |
6c340eac EA |
1731 | extern void i915_driver_preclose(struct drm_device *dev, |
1732 | struct drm_file *file_priv); | |
673a394b EA |
1733 | extern void i915_driver_postclose(struct drm_device *dev, |
1734 | struct drm_file *file_priv); | |
84b1fd10 | 1735 | extern int i915_driver_device_is_agp(struct drm_device * dev); |
c43b5634 | 1736 | #ifdef CONFIG_COMPAT |
0d6aa60b DA |
1737 | extern long i915_compat_ioctl(struct file *filp, unsigned int cmd, |
1738 | unsigned long arg); | |
c43b5634 | 1739 | #endif |
673a394b | 1740 | extern int i915_emit_box(struct drm_device *dev, |
c4e7a414 CW |
1741 | struct drm_clip_rect *box, |
1742 | int DR1, int DR4); | |
8e96d9c4 | 1743 | extern int intel_gpu_reset(struct drm_device *dev); |
d4b8bb2a | 1744 | extern int i915_reset(struct drm_device *dev); |
7648fa99 JB |
1745 | extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv); |
1746 | extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv); | |
1747 | extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv); | |
1748 | extern void i915_update_gfx_val(struct drm_i915_private *dev_priv); | |
1749 | ||
073f34d9 | 1750 | extern void intel_console_resume(struct work_struct *work); |
af6061af | 1751 | |
1da177e4 | 1752 | /* i915_irq.c */ |
10cd45b6 | 1753 | void i915_queue_hangcheck(struct drm_device *dev); |
527f9e90 | 1754 | void i915_handle_error(struct drm_device *dev, bool wedged); |
1da177e4 | 1755 | |
f71d4af4 | 1756 | extern void intel_irq_init(struct drm_device *dev); |
e1b4d303 | 1757 | extern void intel_pm_init(struct drm_device *dev); |
20afbda2 | 1758 | extern void intel_hpd_init(struct drm_device *dev); |
907b28c5 CW |
1759 | extern void intel_pm_init(struct drm_device *dev); |
1760 | ||
1761 | extern void intel_uncore_sanitize(struct drm_device *dev); | |
1762 | extern void intel_uncore_early_sanitize(struct drm_device *dev); | |
1763 | extern void intel_uncore_init(struct drm_device *dev); | |
907b28c5 CW |
1764 | extern void intel_uncore_clear_errors(struct drm_device *dev); |
1765 | extern void intel_uncore_check_errors(struct drm_device *dev); | |
b1f14ad0 | 1766 | |
7c463586 KP |
1767 | void |
1768 | i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask); | |
1769 | ||
1770 | void | |
1771 | i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask); | |
1772 | ||
673a394b EA |
1773 | /* i915_gem.c */ |
1774 | int i915_gem_init_ioctl(struct drm_device *dev, void *data, | |
1775 | struct drm_file *file_priv); | |
1776 | int i915_gem_create_ioctl(struct drm_device *dev, void *data, | |
1777 | struct drm_file *file_priv); | |
1778 | int i915_gem_pread_ioctl(struct drm_device *dev, void *data, | |
1779 | struct drm_file *file_priv); | |
1780 | int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data, | |
1781 | struct drm_file *file_priv); | |
1782 | int i915_gem_mmap_ioctl(struct drm_device *dev, void *data, | |
1783 | struct drm_file *file_priv); | |
de151cf6 JB |
1784 | int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data, |
1785 | struct drm_file *file_priv); | |
673a394b EA |
1786 | int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data, |
1787 | struct drm_file *file_priv); | |
1788 | int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data, | |
1789 | struct drm_file *file_priv); | |
1790 | int i915_gem_execbuffer(struct drm_device *dev, void *data, | |
1791 | struct drm_file *file_priv); | |
76446cac JB |
1792 | int i915_gem_execbuffer2(struct drm_device *dev, void *data, |
1793 | struct drm_file *file_priv); | |
673a394b EA |
1794 | int i915_gem_pin_ioctl(struct drm_device *dev, void *data, |
1795 | struct drm_file *file_priv); | |
1796 | int i915_gem_unpin_ioctl(struct drm_device *dev, void *data, | |
1797 | struct drm_file *file_priv); | |
1798 | int i915_gem_busy_ioctl(struct drm_device *dev, void *data, | |
1799 | struct drm_file *file_priv); | |
199adf40 BW |
1800 | int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data, |
1801 | struct drm_file *file); | |
1802 | int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data, | |
1803 | struct drm_file *file); | |
673a394b EA |
1804 | int i915_gem_throttle_ioctl(struct drm_device *dev, void *data, |
1805 | struct drm_file *file_priv); | |
3ef94daa CW |
1806 | int i915_gem_madvise_ioctl(struct drm_device *dev, void *data, |
1807 | struct drm_file *file_priv); | |
673a394b EA |
1808 | int i915_gem_entervt_ioctl(struct drm_device *dev, void *data, |
1809 | struct drm_file *file_priv); | |
1810 | int i915_gem_leavevt_ioctl(struct drm_device *dev, void *data, | |
1811 | struct drm_file *file_priv); | |
1812 | int i915_gem_set_tiling(struct drm_device *dev, void *data, | |
1813 | struct drm_file *file_priv); | |
1814 | int i915_gem_get_tiling(struct drm_device *dev, void *data, | |
1815 | struct drm_file *file_priv); | |
5a125c3c EA |
1816 | int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data, |
1817 | struct drm_file *file_priv); | |
23ba4fd0 BW |
1818 | int i915_gem_wait_ioctl(struct drm_device *dev, void *data, |
1819 | struct drm_file *file_priv); | |
673a394b | 1820 | void i915_gem_load(struct drm_device *dev); |
42dcedd4 CW |
1821 | void *i915_gem_object_alloc(struct drm_device *dev); |
1822 | void i915_gem_object_free(struct drm_i915_gem_object *obj); | |
673a394b | 1823 | int i915_gem_init_object(struct drm_gem_object *obj); |
37e680a1 CW |
1824 | void i915_gem_object_init(struct drm_i915_gem_object *obj, |
1825 | const struct drm_i915_gem_object_ops *ops); | |
05394f39 CW |
1826 | struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev, |
1827 | size_t size); | |
673a394b | 1828 | void i915_gem_free_object(struct drm_gem_object *obj); |
2f633156 | 1829 | void i915_gem_vma_destroy(struct i915_vma *vma); |
42dcedd4 | 1830 | |
2021746e | 1831 | int __must_check i915_gem_object_pin(struct drm_i915_gem_object *obj, |
c37e2204 | 1832 | struct i915_address_space *vm, |
2021746e | 1833 | uint32_t alignment, |
86a1ee26 CW |
1834 | bool map_and_fenceable, |
1835 | bool nonblocking); | |
05394f39 | 1836 | void i915_gem_object_unpin(struct drm_i915_gem_object *obj); |
07fe0b12 BW |
1837 | int __must_check i915_vma_unbind(struct i915_vma *vma); |
1838 | int __must_check i915_gem_object_ggtt_unbind(struct drm_i915_gem_object *obj); | |
dd624afd | 1839 | int i915_gem_object_put_pages(struct drm_i915_gem_object *obj); |
05394f39 | 1840 | void i915_gem_release_mmap(struct drm_i915_gem_object *obj); |
673a394b | 1841 | void i915_gem_lastclose(struct drm_device *dev); |
f787a5f5 | 1842 | |
37e680a1 | 1843 | int __must_check i915_gem_object_get_pages(struct drm_i915_gem_object *obj); |
9da3da66 CW |
1844 | static inline struct page *i915_gem_object_get_page(struct drm_i915_gem_object *obj, int n) |
1845 | { | |
67d5a50c ID |
1846 | struct sg_page_iter sg_iter; |
1847 | ||
1848 | for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, n) | |
2db76d7c | 1849 | return sg_page_iter_page(&sg_iter); |
67d5a50c ID |
1850 | |
1851 | return NULL; | |
9da3da66 | 1852 | } |
a5570178 CW |
1853 | static inline void i915_gem_object_pin_pages(struct drm_i915_gem_object *obj) |
1854 | { | |
1855 | BUG_ON(obj->pages == NULL); | |
1856 | obj->pages_pin_count++; | |
1857 | } | |
1858 | static inline void i915_gem_object_unpin_pages(struct drm_i915_gem_object *obj) | |
1859 | { | |
1860 | BUG_ON(obj->pages_pin_count == 0); | |
1861 | obj->pages_pin_count--; | |
1862 | } | |
1863 | ||
54cf91dc | 1864 | int __must_check i915_mutex_lock_interruptible(struct drm_device *dev); |
2911a35b BW |
1865 | int i915_gem_object_sync(struct drm_i915_gem_object *obj, |
1866 | struct intel_ring_buffer *to); | |
54cf91dc | 1867 | void i915_gem_object_move_to_active(struct drm_i915_gem_object *obj, |
9d773091 | 1868 | struct intel_ring_buffer *ring); |
54cf91dc | 1869 | |
ff72145b DA |
1870 | int i915_gem_dumb_create(struct drm_file *file_priv, |
1871 | struct drm_device *dev, | |
1872 | struct drm_mode_create_dumb *args); | |
1873 | int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev, | |
1874 | uint32_t handle, uint64_t *offset); | |
f787a5f5 CW |
1875 | /** |
1876 | * Returns true if seq1 is later than seq2. | |
1877 | */ | |
1878 | static inline bool | |
1879 | i915_seqno_passed(uint32_t seq1, uint32_t seq2) | |
1880 | { | |
1881 | return (int32_t)(seq1 - seq2) >= 0; | |
1882 | } | |
1883 | ||
fca26bb4 MK |
1884 | int __must_check i915_gem_get_seqno(struct drm_device *dev, u32 *seqno); |
1885 | int __must_check i915_gem_set_seqno(struct drm_device *dev, u32 seqno); | |
06d98131 | 1886 | int __must_check i915_gem_object_get_fence(struct drm_i915_gem_object *obj); |
d9e86c0e | 1887 | int __must_check i915_gem_object_put_fence(struct drm_i915_gem_object *obj); |
2021746e | 1888 | |
9a5a53b3 | 1889 | static inline bool |
1690e1eb CW |
1890 | i915_gem_object_pin_fence(struct drm_i915_gem_object *obj) |
1891 | { | |
1892 | if (obj->fence_reg != I915_FENCE_REG_NONE) { | |
1893 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; | |
1894 | dev_priv->fence_regs[obj->fence_reg].pin_count++; | |
9a5a53b3 CW |
1895 | return true; |
1896 | } else | |
1897 | return false; | |
1690e1eb CW |
1898 | } |
1899 | ||
1900 | static inline void | |
1901 | i915_gem_object_unpin_fence(struct drm_i915_gem_object *obj) | |
1902 | { | |
1903 | if (obj->fence_reg != I915_FENCE_REG_NONE) { | |
1904 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; | |
b8c3af76 | 1905 | WARN_ON(dev_priv->fence_regs[obj->fence_reg].pin_count <= 0); |
1690e1eb CW |
1906 | dev_priv->fence_regs[obj->fence_reg].pin_count--; |
1907 | } | |
1908 | } | |
1909 | ||
b09a1fec | 1910 | void i915_gem_retire_requests(struct drm_device *dev); |
a71d8d94 | 1911 | void i915_gem_retire_requests_ring(struct intel_ring_buffer *ring); |
33196ded | 1912 | int __must_check i915_gem_check_wedge(struct i915_gpu_error *error, |
d6b2c790 | 1913 | bool interruptible); |
1f83fee0 DV |
1914 | static inline bool i915_reset_in_progress(struct i915_gpu_error *error) |
1915 | { | |
1916 | return unlikely(atomic_read(&error->reset_counter) | |
1917 | & I915_RESET_IN_PROGRESS_FLAG); | |
1918 | } | |
1919 | ||
1920 | static inline bool i915_terminally_wedged(struct i915_gpu_error *error) | |
1921 | { | |
1922 | return atomic_read(&error->reset_counter) == I915_WEDGED; | |
1923 | } | |
a71d8d94 | 1924 | |
069efc1d | 1925 | void i915_gem_reset(struct drm_device *dev); |
000433b6 | 1926 | bool i915_gem_clflush_object(struct drm_i915_gem_object *obj, bool force); |
a8198eea | 1927 | int __must_check i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj); |
1070a42b | 1928 | int __must_check i915_gem_init(struct drm_device *dev); |
f691e2f4 | 1929 | int __must_check i915_gem_init_hw(struct drm_device *dev); |
b9524a1e | 1930 | void i915_gem_l3_remap(struct drm_device *dev); |
f691e2f4 | 1931 | void i915_gem_init_swizzling(struct drm_device *dev); |
79e53945 | 1932 | void i915_gem_cleanup_ringbuffer(struct drm_device *dev); |
b2da9fe5 | 1933 | int __must_check i915_gpu_idle(struct drm_device *dev); |
2021746e | 1934 | int __must_check i915_gem_idle(struct drm_device *dev); |
0025c077 MK |
1935 | int __i915_add_request(struct intel_ring_buffer *ring, |
1936 | struct drm_file *file, | |
7d736f4f | 1937 | struct drm_i915_gem_object *batch_obj, |
0025c077 MK |
1938 | u32 *seqno); |
1939 | #define i915_add_request(ring, seqno) \ | |
854c94a7 | 1940 | __i915_add_request(ring, NULL, NULL, seqno) |
199b2bc2 BW |
1941 | int __must_check i915_wait_seqno(struct intel_ring_buffer *ring, |
1942 | uint32_t seqno); | |
de151cf6 | 1943 | int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf); |
2021746e CW |
1944 | int __must_check |
1945 | i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, | |
1946 | bool write); | |
1947 | int __must_check | |
dabdfe02 CW |
1948 | i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write); |
1949 | int __must_check | |
2da3b9b9 CW |
1950 | i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj, |
1951 | u32 alignment, | |
2021746e | 1952 | struct intel_ring_buffer *pipelined); |
cc98b413 | 1953 | void i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object *obj); |
71acb5eb | 1954 | int i915_gem_attach_phys_object(struct drm_device *dev, |
05394f39 | 1955 | struct drm_i915_gem_object *obj, |
6eeefaf3 CW |
1956 | int id, |
1957 | int align); | |
71acb5eb | 1958 | void i915_gem_detach_phys_object(struct drm_device *dev, |
05394f39 | 1959 | struct drm_i915_gem_object *obj); |
71acb5eb | 1960 | void i915_gem_free_all_phys_object(struct drm_device *dev); |
05394f39 | 1961 | void i915_gem_release(struct drm_device *dev, struct drm_file *file); |
673a394b | 1962 | |
0fa87796 ID |
1963 | uint32_t |
1964 | i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode); | |
467cffba | 1965 | uint32_t |
d865110c ID |
1966 | i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size, |
1967 | int tiling_mode, bool fenced); | |
467cffba | 1968 | |
e4ffd173 CW |
1969 | int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj, |
1970 | enum i915_cache_level cache_level); | |
1971 | ||
1286ff73 DV |
1972 | struct drm_gem_object *i915_gem_prime_import(struct drm_device *dev, |
1973 | struct dma_buf *dma_buf); | |
1974 | ||
1975 | struct dma_buf *i915_gem_prime_export(struct drm_device *dev, | |
1976 | struct drm_gem_object *gem_obj, int flags); | |
1977 | ||
19b2dbde CW |
1978 | void i915_gem_restore_fences(struct drm_device *dev); |
1979 | ||
a70a3148 BW |
1980 | unsigned long i915_gem_obj_offset(struct drm_i915_gem_object *o, |
1981 | struct i915_address_space *vm); | |
1982 | bool i915_gem_obj_bound_any(struct drm_i915_gem_object *o); | |
1983 | bool i915_gem_obj_bound(struct drm_i915_gem_object *o, | |
1984 | struct i915_address_space *vm); | |
1985 | unsigned long i915_gem_obj_size(struct drm_i915_gem_object *o, | |
1986 | struct i915_address_space *vm); | |
1987 | struct i915_vma *i915_gem_obj_to_vma(struct drm_i915_gem_object *obj, | |
1988 | struct i915_address_space *vm); | |
accfef2e BW |
1989 | struct i915_vma * |
1990 | i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object *obj, | |
1991 | struct i915_address_space *vm); | |
a70a3148 BW |
1992 | /* Some GGTT VM helpers */ |
1993 | #define obj_to_ggtt(obj) \ | |
1994 | (&((struct drm_i915_private *)(obj)->base.dev->dev_private)->gtt.base) | |
1995 | static inline bool i915_is_ggtt(struct i915_address_space *vm) | |
1996 | { | |
1997 | struct i915_address_space *ggtt = | |
1998 | &((struct drm_i915_private *)(vm)->dev->dev_private)->gtt.base; | |
1999 | return vm == ggtt; | |
2000 | } | |
2001 | ||
2002 | static inline bool i915_gem_obj_ggtt_bound(struct drm_i915_gem_object *obj) | |
2003 | { | |
2004 | return i915_gem_obj_bound(obj, obj_to_ggtt(obj)); | |
2005 | } | |
2006 | ||
2007 | static inline unsigned long | |
2008 | i915_gem_obj_ggtt_offset(struct drm_i915_gem_object *obj) | |
2009 | { | |
2010 | return i915_gem_obj_offset(obj, obj_to_ggtt(obj)); | |
2011 | } | |
2012 | ||
2013 | static inline unsigned long | |
2014 | i915_gem_obj_ggtt_size(struct drm_i915_gem_object *obj) | |
2015 | { | |
2016 | return i915_gem_obj_size(obj, obj_to_ggtt(obj)); | |
2017 | } | |
c37e2204 BW |
2018 | |
2019 | static inline int __must_check | |
2020 | i915_gem_obj_ggtt_pin(struct drm_i915_gem_object *obj, | |
2021 | uint32_t alignment, | |
2022 | bool map_and_fenceable, | |
2023 | bool nonblocking) | |
2024 | { | |
2025 | return i915_gem_object_pin(obj, obj_to_ggtt(obj), alignment, | |
2026 | map_and_fenceable, nonblocking); | |
2027 | } | |
a70a3148 BW |
2028 | #undef obj_to_ggtt |
2029 | ||
254f965c BW |
2030 | /* i915_gem_context.c */ |
2031 | void i915_gem_context_init(struct drm_device *dev); | |
2032 | void i915_gem_context_fini(struct drm_device *dev); | |
254f965c | 2033 | void i915_gem_context_close(struct drm_device *dev, struct drm_file *file); |
e0556841 BW |
2034 | int i915_switch_context(struct intel_ring_buffer *ring, |
2035 | struct drm_file *file, int to_id); | |
dce3271b MK |
2036 | void i915_gem_context_free(struct kref *ctx_ref); |
2037 | static inline void i915_gem_context_reference(struct i915_hw_context *ctx) | |
2038 | { | |
2039 | kref_get(&ctx->ref); | |
2040 | } | |
2041 | ||
2042 | static inline void i915_gem_context_unreference(struct i915_hw_context *ctx) | |
2043 | { | |
2044 | kref_put(&ctx->ref, i915_gem_context_free); | |
2045 | } | |
2046 | ||
c0bb617a | 2047 | struct i915_ctx_hang_stats * __must_check |
11fa3384 | 2048 | i915_gem_context_get_hang_stats(struct drm_device *dev, |
c0bb617a MK |
2049 | struct drm_file *file, |
2050 | u32 id); | |
84624813 BW |
2051 | int i915_gem_context_create_ioctl(struct drm_device *dev, void *data, |
2052 | struct drm_file *file); | |
2053 | int i915_gem_context_destroy_ioctl(struct drm_device *dev, void *data, | |
2054 | struct drm_file *file); | |
1286ff73 | 2055 | |
76aaf220 | 2056 | /* i915_gem_gtt.c */ |
1d2a314c | 2057 | void i915_gem_cleanup_aliasing_ppgtt(struct drm_device *dev); |
7bddb01f DV |
2058 | void i915_ppgtt_bind_object(struct i915_hw_ppgtt *ppgtt, |
2059 | struct drm_i915_gem_object *obj, | |
2060 | enum i915_cache_level cache_level); | |
2061 | void i915_ppgtt_unbind_object(struct i915_hw_ppgtt *ppgtt, | |
2062 | struct drm_i915_gem_object *obj); | |
1d2a314c | 2063 | |
76aaf220 | 2064 | void i915_gem_restore_gtt_mappings(struct drm_device *dev); |
74163907 DV |
2065 | int __must_check i915_gem_gtt_prepare_object(struct drm_i915_gem_object *obj); |
2066 | void i915_gem_gtt_bind_object(struct drm_i915_gem_object *obj, | |
e4ffd173 | 2067 | enum i915_cache_level cache_level); |
05394f39 | 2068 | void i915_gem_gtt_unbind_object(struct drm_i915_gem_object *obj); |
74163907 | 2069 | void i915_gem_gtt_finish_object(struct drm_i915_gem_object *obj); |
d7e5008f BW |
2070 | void i915_gem_init_global_gtt(struct drm_device *dev); |
2071 | void i915_gem_setup_global_gtt(struct drm_device *dev, unsigned long start, | |
2072 | unsigned long mappable_end, unsigned long end); | |
e76e9aeb | 2073 | int i915_gem_gtt_init(struct drm_device *dev); |
d09105c6 | 2074 | static inline void i915_gem_chipset_flush(struct drm_device *dev) |
e76e9aeb BW |
2075 | { |
2076 | if (INTEL_INFO(dev)->gen < 6) | |
2077 | intel_gtt_chipset_flush(); | |
2078 | } | |
2079 | ||
76aaf220 | 2080 | |
b47eb4a2 | 2081 | /* i915_gem_evict.c */ |
f6cd1f15 BW |
2082 | int __must_check i915_gem_evict_something(struct drm_device *dev, |
2083 | struct i915_address_space *vm, | |
2084 | int min_size, | |
42d6ab48 CW |
2085 | unsigned alignment, |
2086 | unsigned cache_level, | |
86a1ee26 CW |
2087 | bool mappable, |
2088 | bool nonblock); | |
6c085a72 | 2089 | int i915_gem_evict_everything(struct drm_device *dev); |
b47eb4a2 | 2090 | |
9797fbfb CW |
2091 | /* i915_gem_stolen.c */ |
2092 | int i915_gem_init_stolen(struct drm_device *dev); | |
11be49eb CW |
2093 | int i915_gem_stolen_setup_compression(struct drm_device *dev, int size); |
2094 | void i915_gem_stolen_cleanup_compression(struct drm_device *dev); | |
9797fbfb | 2095 | void i915_gem_cleanup_stolen(struct drm_device *dev); |
0104fdbb CW |
2096 | struct drm_i915_gem_object * |
2097 | i915_gem_object_create_stolen(struct drm_device *dev, u32 size); | |
866d12b4 CW |
2098 | struct drm_i915_gem_object * |
2099 | i915_gem_object_create_stolen_for_preallocated(struct drm_device *dev, | |
2100 | u32 stolen_offset, | |
2101 | u32 gtt_offset, | |
2102 | u32 size); | |
0104fdbb | 2103 | void i915_gem_object_release_stolen(struct drm_i915_gem_object *obj); |
9797fbfb | 2104 | |
673a394b | 2105 | /* i915_gem_tiling.c */ |
2c1792a1 | 2106 | static inline bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj) |
e9b73c67 CW |
2107 | { |
2108 | drm_i915_private_t *dev_priv = obj->base.dev->dev_private; | |
2109 | ||
2110 | return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 && | |
2111 | obj->tiling_mode != I915_TILING_NONE; | |
2112 | } | |
2113 | ||
673a394b | 2114 | void i915_gem_detect_bit_6_swizzle(struct drm_device *dev); |
05394f39 CW |
2115 | void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj); |
2116 | void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj); | |
673a394b EA |
2117 | |
2118 | /* i915_gem_debug.c */ | |
23bc5982 CW |
2119 | #if WATCH_LISTS |
2120 | int i915_verify_lists(struct drm_device *dev); | |
673a394b | 2121 | #else |
23bc5982 | 2122 | #define i915_verify_lists(dev) 0 |
673a394b | 2123 | #endif |
1da177e4 | 2124 | |
2017263e | 2125 | /* i915_debugfs.c */ |
27c202ad BG |
2126 | int i915_debugfs_init(struct drm_minor *minor); |
2127 | void i915_debugfs_cleanup(struct drm_minor *minor); | |
84734a04 MK |
2128 | |
2129 | /* i915_gpu_error.c */ | |
edc3d884 MK |
2130 | __printf(2, 3) |
2131 | void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...); | |
fc16b48b MK |
2132 | int i915_error_state_to_str(struct drm_i915_error_state_buf *estr, |
2133 | const struct i915_error_state_file_priv *error); | |
4dc955f7 MK |
2134 | int i915_error_state_buf_init(struct drm_i915_error_state_buf *eb, |
2135 | size_t count, loff_t pos); | |
2136 | static inline void i915_error_state_buf_release( | |
2137 | struct drm_i915_error_state_buf *eb) | |
2138 | { | |
2139 | kfree(eb->buf); | |
2140 | } | |
84734a04 MK |
2141 | void i915_capture_error_state(struct drm_device *dev); |
2142 | void i915_error_state_get(struct drm_device *dev, | |
2143 | struct i915_error_state_file_priv *error_priv); | |
2144 | void i915_error_state_put(struct i915_error_state_file_priv *error_priv); | |
2145 | void i915_destroy_error_state(struct drm_device *dev); | |
2146 | ||
2147 | void i915_get_extra_instdone(struct drm_device *dev, uint32_t *instdone); | |
2148 | const char *i915_cache_level_str(int type); | |
2017263e | 2149 | |
317c35d1 JB |
2150 | /* i915_suspend.c */ |
2151 | extern int i915_save_state(struct drm_device *dev); | |
2152 | extern int i915_restore_state(struct drm_device *dev); | |
0a3e67a4 | 2153 | |
d8157a36 DV |
2154 | /* i915_ums.c */ |
2155 | void i915_save_display_reg(struct drm_device *dev); | |
2156 | void i915_restore_display_reg(struct drm_device *dev); | |
317c35d1 | 2157 | |
0136db58 BW |
2158 | /* i915_sysfs.c */ |
2159 | void i915_setup_sysfs(struct drm_device *dev_priv); | |
2160 | void i915_teardown_sysfs(struct drm_device *dev_priv); | |
2161 | ||
f899fc64 CW |
2162 | /* intel_i2c.c */ |
2163 | extern int intel_setup_gmbus(struct drm_device *dev); | |
2164 | extern void intel_teardown_gmbus(struct drm_device *dev); | |
8f375e10 | 2165 | static inline bool intel_gmbus_is_port_valid(unsigned port) |
3bd7d909 | 2166 | { |
2ed06c93 | 2167 | return (port >= GMBUS_PORT_SSC && port <= GMBUS_PORT_DPD); |
3bd7d909 DK |
2168 | } |
2169 | ||
2170 | extern struct i2c_adapter *intel_gmbus_get_adapter( | |
2171 | struct drm_i915_private *dev_priv, unsigned port); | |
e957d772 CW |
2172 | extern void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed); |
2173 | extern void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit); | |
8f375e10 | 2174 | static inline bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter) |
b8232e90 CW |
2175 | { |
2176 | return container_of(adapter, struct intel_gmbus, adapter)->force_bit; | |
2177 | } | |
f899fc64 CW |
2178 | extern void intel_i2c_reset(struct drm_device *dev); |
2179 | ||
3b617967 | 2180 | /* intel_opregion.c */ |
44834a67 CW |
2181 | extern int intel_opregion_setup(struct drm_device *dev); |
2182 | #ifdef CONFIG_ACPI | |
2183 | extern void intel_opregion_init(struct drm_device *dev); | |
2184 | extern void intel_opregion_fini(struct drm_device *dev); | |
3b617967 | 2185 | extern void intel_opregion_asle_intr(struct drm_device *dev); |
65e082c9 | 2186 | #else |
44834a67 CW |
2187 | static inline void intel_opregion_init(struct drm_device *dev) { return; } |
2188 | static inline void intel_opregion_fini(struct drm_device *dev) { return; } | |
3b617967 | 2189 | static inline void intel_opregion_asle_intr(struct drm_device *dev) { return; } |
65e082c9 | 2190 | #endif |
8ee1c3db | 2191 | |
723bfd70 JB |
2192 | /* intel_acpi.c */ |
2193 | #ifdef CONFIG_ACPI | |
2194 | extern void intel_register_dsm_handler(void); | |
2195 | extern void intel_unregister_dsm_handler(void); | |
2196 | #else | |
2197 | static inline void intel_register_dsm_handler(void) { return; } | |
2198 | static inline void intel_unregister_dsm_handler(void) { return; } | |
2199 | #endif /* CONFIG_ACPI */ | |
2200 | ||
79e53945 | 2201 | /* modesetting */ |
f817586c | 2202 | extern void intel_modeset_init_hw(struct drm_device *dev); |
7d708ee4 | 2203 | extern void intel_modeset_suspend_hw(struct drm_device *dev); |
79e53945 | 2204 | extern void intel_modeset_init(struct drm_device *dev); |
2c7111db | 2205 | extern void intel_modeset_gem_init(struct drm_device *dev); |
79e53945 | 2206 | extern void intel_modeset_cleanup(struct drm_device *dev); |
28d52043 | 2207 | extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state); |
45e2b5f6 DV |
2208 | extern void intel_modeset_setup_hw_state(struct drm_device *dev, |
2209 | bool force_restore); | |
44cec740 | 2210 | extern void i915_redisable_vga(struct drm_device *dev); |
ee5382ae | 2211 | extern bool intel_fbc_enabled(struct drm_device *dev); |
43a9539f | 2212 | extern void intel_disable_fbc(struct drm_device *dev); |
7648fa99 | 2213 | extern bool ironlake_set_drps(struct drm_device *dev, u8 val); |
dde86e2d | 2214 | extern void intel_init_pch_refclk(struct drm_device *dev); |
3b8d8d91 | 2215 | extern void gen6_set_rps(struct drm_device *dev, u8 val); |
0a073b84 JB |
2216 | extern void valleyview_set_rps(struct drm_device *dev, u8 val); |
2217 | extern int valleyview_rps_max_freq(struct drm_i915_private *dev_priv); | |
2218 | extern int valleyview_rps_min_freq(struct drm_i915_private *dev_priv); | |
0206e353 AJ |
2219 | extern void intel_detect_pch(struct drm_device *dev); |
2220 | extern int intel_trans_dp_port_sel(struct drm_crtc *crtc); | |
0136db58 | 2221 | extern int intel_enable_rc6(const struct drm_device *dev); |
3bad0781 | 2222 | |
2911a35b | 2223 | extern bool i915_semaphore_is_enabled(struct drm_device *dev); |
c0c7babc BW |
2224 | int i915_reg_read_ioctl(struct drm_device *dev, void *data, |
2225 | struct drm_file *file); | |
575155a9 | 2226 | |
6ef3d427 CW |
2227 | /* overlay */ |
2228 | extern struct intel_overlay_error_state *intel_overlay_capture_error_state(struct drm_device *dev); | |
edc3d884 MK |
2229 | extern void intel_overlay_print_error_state(struct drm_i915_error_state_buf *e, |
2230 | struct intel_overlay_error_state *error); | |
c4a1d9e4 CW |
2231 | |
2232 | extern struct intel_display_error_state *intel_display_capture_error_state(struct drm_device *dev); | |
edc3d884 | 2233 | extern void intel_display_print_error_state(struct drm_i915_error_state_buf *e, |
c4a1d9e4 CW |
2234 | struct drm_device *dev, |
2235 | struct intel_display_error_state *error); | |
6ef3d427 | 2236 | |
b7287d80 BW |
2237 | /* On SNB platform, before reading ring registers forcewake bit |
2238 | * must be set to prevent GT core from power down and stale values being | |
2239 | * returned. | |
2240 | */ | |
fcca7926 BW |
2241 | void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv); |
2242 | void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv); | |
b7287d80 | 2243 | |
42c0526c BW |
2244 | int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u8 mbox, u32 *val); |
2245 | int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32 val); | |
59de0813 JN |
2246 | |
2247 | /* intel_sideband.c */ | |
64936258 JN |
2248 | u32 vlv_punit_read(struct drm_i915_private *dev_priv, u8 addr); |
2249 | void vlv_punit_write(struct drm_i915_private *dev_priv, u8 addr, u32 val); | |
2250 | u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr); | |
ae99258f JN |
2251 | u32 vlv_dpio_read(struct drm_i915_private *dev_priv, int reg); |
2252 | void vlv_dpio_write(struct drm_i915_private *dev_priv, int reg, u32 val); | |
59de0813 JN |
2253 | u32 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg, |
2254 | enum intel_sbi_destination destination); | |
2255 | void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value, | |
2256 | enum intel_sbi_destination destination); | |
0a073b84 | 2257 | |
855ba3be JB |
2258 | int vlv_gpu_freq(int ddr_freq, int val); |
2259 | int vlv_freq_opcode(int ddr_freq, int val); | |
42c0526c | 2260 | |
6af5d92f | 2261 | #define __i915_read(x) \ |
dba8e41f | 2262 | u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg, bool trace); |
6af5d92f CW |
2263 | __i915_read(8) |
2264 | __i915_read(16) | |
2265 | __i915_read(32) | |
2266 | __i915_read(64) | |
5f75377d KP |
2267 | #undef __i915_read |
2268 | ||
6af5d92f | 2269 | #define __i915_write(x) \ |
dba8e41f | 2270 | void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x val, bool trace); |
6af5d92f CW |
2271 | __i915_write(8) |
2272 | __i915_write(16) | |
2273 | __i915_write(32) | |
2274 | __i915_write(64) | |
5f75377d KP |
2275 | #undef __i915_write |
2276 | ||
dba8e41f CW |
2277 | #define I915_READ8(reg) i915_read8(dev_priv, (reg), true) |
2278 | #define I915_WRITE8(reg, val) i915_write8(dev_priv, (reg), (val), true) | |
5f75377d | 2279 | |
dba8e41f CW |
2280 | #define I915_READ16(reg) i915_read16(dev_priv, (reg), true) |
2281 | #define I915_WRITE16(reg, val) i915_write16(dev_priv, (reg), (val), true) | |
2282 | #define I915_READ16_NOTRACE(reg) i915_read16(dev_priv, (reg), false) | |
2283 | #define I915_WRITE16_NOTRACE(reg, val) i915_write16(dev_priv, (reg), (val), false) | |
5f75377d | 2284 | |
dba8e41f CW |
2285 | #define I915_READ(reg) i915_read32(dev_priv, (reg), true) |
2286 | #define I915_WRITE(reg, val) i915_write32(dev_priv, (reg), (val), true) | |
2287 | #define I915_READ_NOTRACE(reg) i915_read32(dev_priv, (reg), false) | |
2288 | #define I915_WRITE_NOTRACE(reg, val) i915_write32(dev_priv, (reg), (val), false) | |
5f75377d | 2289 | |
dba8e41f CW |
2290 | #define I915_WRITE64(reg, val) i915_write64(dev_priv, (reg), (val), true) |
2291 | #define I915_READ64(reg) i915_read64(dev_priv, (reg), true) | |
cae5852d ZN |
2292 | |
2293 | #define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg) | |
2294 | #define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg) | |
2295 | ||
55bc60db VS |
2296 | /* "Broadcast RGB" property */ |
2297 | #define INTEL_BROADCAST_RGB_AUTO 0 | |
2298 | #define INTEL_BROADCAST_RGB_FULL 1 | |
2299 | #define INTEL_BROADCAST_RGB_LIMITED 2 | |
ba4f01a3 | 2300 | |
766aa1c4 VS |
2301 | static inline uint32_t i915_vgacntrl_reg(struct drm_device *dev) |
2302 | { | |
2303 | if (HAS_PCH_SPLIT(dev)) | |
2304 | return CPU_VGACNTRL; | |
2305 | else if (IS_VALLEYVIEW(dev)) | |
2306 | return VLV_VGACNTRL; | |
2307 | else | |
2308 | return VGACNTRL; | |
2309 | } | |
2310 | ||
2bb4629a VS |
2311 | static inline void __user *to_user_ptr(u64 address) |
2312 | { | |
2313 | return (void __user *)(uintptr_t)address; | |
2314 | } | |
2315 | ||
df97729f ID |
2316 | static inline unsigned long msecs_to_jiffies_timeout(const unsigned int m) |
2317 | { | |
2318 | unsigned long j = msecs_to_jiffies(m); | |
2319 | ||
2320 | return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1); | |
2321 | } | |
2322 | ||
2323 | static inline unsigned long | |
2324 | timespec_to_jiffies_timeout(const struct timespec *value) | |
2325 | { | |
2326 | unsigned long j = timespec_to_jiffies(value); | |
2327 | ||
2328 | return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1); | |
2329 | } | |
2330 | ||
1da177e4 | 2331 | #endif |