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1da177e4 LT |
1 | /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*- |
2 | */ | |
0d6aa60b | 3 | /* |
bc54fd1a | 4 | * |
1da177e4 LT |
5 | * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. |
6 | * All Rights Reserved. | |
bc54fd1a DA |
7 | * |
8 | * Permission is hereby granted, free of charge, to any person obtaining a | |
9 | * copy of this software and associated documentation files (the | |
10 | * "Software"), to deal in the Software without restriction, including | |
11 | * without limitation the rights to use, copy, modify, merge, publish, | |
12 | * distribute, sub license, and/or sell copies of the Software, and to | |
13 | * permit persons to whom the Software is furnished to do so, subject to | |
14 | * the following conditions: | |
15 | * | |
16 | * The above copyright notice and this permission notice (including the | |
17 | * next paragraph) shall be included in all copies or substantial portions | |
18 | * of the Software. | |
19 | * | |
20 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS | |
21 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
22 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. | |
23 | * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR | |
24 | * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, | |
25 | * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE | |
26 | * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. | |
27 | * | |
0d6aa60b | 28 | */ |
1da177e4 LT |
29 | |
30 | #ifndef _I915_DRV_H_ | |
31 | #define _I915_DRV_H_ | |
32 | ||
e9b73c67 | 33 | #include <uapi/drm/i915_drm.h> |
93b81f51 | 34 | #include <uapi/drm/drm_fourcc.h> |
e9b73c67 | 35 | |
0839ccb8 | 36 | #include <linux/io-mapping.h> |
f899fc64 | 37 | #include <linux/i2c.h> |
c167a6fc | 38 | #include <linux/i2c-algo-bit.h> |
aaa6fd2a | 39 | #include <linux/backlight.h> |
5cc9ed4b | 40 | #include <linux/hashtable.h> |
2911a35b | 41 | #include <linux/intel-iommu.h> |
742cbee8 | 42 | #include <linux/kref.h> |
9ee32fea | 43 | #include <linux/pm_qos.h> |
d07f0e59 | 44 | #include <linux/reservation.h> |
e73bdd20 CW |
45 | #include <linux/shmem_fs.h> |
46 | ||
47 | #include <drm/drmP.h> | |
48 | #include <drm/intel-gtt.h> | |
49 | #include <drm/drm_legacy.h> /* for struct drm_dma_handle */ | |
50 | #include <drm/drm_gem.h> | |
3b96a0b1 | 51 | #include <drm/drm_auth.h> |
e73bdd20 CW |
52 | |
53 | #include "i915_params.h" | |
54 | #include "i915_reg.h" | |
55 | ||
56 | #include "intel_bios.h" | |
ac7f11c6 | 57 | #include "intel_dpll_mgr.h" |
e73bdd20 CW |
58 | #include "intel_guc.h" |
59 | #include "intel_lrc.h" | |
60 | #include "intel_ringbuffer.h" | |
61 | ||
d501b1d2 | 62 | #include "i915_gem.h" |
b42fe9ca JL |
63 | #include "i915_gem_fence_reg.h" |
64 | #include "i915_gem_object.h" | |
e73bdd20 CW |
65 | #include "i915_gem_gtt.h" |
66 | #include "i915_gem_render_state.h" | |
05235c53 | 67 | #include "i915_gem_request.h" |
73cb9701 | 68 | #include "i915_gem_timeline.h" |
585fb111 | 69 | |
b42fe9ca JL |
70 | #include "i915_vma.h" |
71 | ||
0ad35fed ZW |
72 | #include "intel_gvt.h" |
73 | ||
1da177e4 LT |
74 | /* General customization: |
75 | */ | |
76 | ||
1da177e4 LT |
77 | #define DRIVER_NAME "i915" |
78 | #define DRIVER_DESC "Intel Graphics" | |
e9cbc4bd DV |
79 | #define DRIVER_DATE "20161121" |
80 | #define DRIVER_TIMESTAMP 1479717903 | |
1da177e4 | 81 | |
c883ef1b | 82 | #undef WARN_ON |
5f77eeb0 DV |
83 | /* Many gcc seem to no see through this and fall over :( */ |
84 | #if 0 | |
85 | #define WARN_ON(x) ({ \ | |
86 | bool __i915_warn_cond = (x); \ | |
87 | if (__builtin_constant_p(__i915_warn_cond)) \ | |
88 | BUILD_BUG_ON(__i915_warn_cond); \ | |
89 | WARN(__i915_warn_cond, "WARN_ON(" #x ")"); }) | |
90 | #else | |
152b2262 | 91 | #define WARN_ON(x) WARN((x), "%s", "WARN_ON(" __stringify(x) ")") |
5f77eeb0 DV |
92 | #endif |
93 | ||
cd9bfacb | 94 | #undef WARN_ON_ONCE |
152b2262 | 95 | #define WARN_ON_ONCE(x) WARN_ONCE((x), "%s", "WARN_ON_ONCE(" __stringify(x) ")") |
cd9bfacb | 96 | |
5f77eeb0 DV |
97 | #define MISSING_CASE(x) WARN(1, "Missing switch case (%lu) in %s\n", \ |
98 | (long) (x), __func__); | |
c883ef1b | 99 | |
e2c719b7 RC |
100 | /* Use I915_STATE_WARN(x) and I915_STATE_WARN_ON() (rather than WARN() and |
101 | * WARN_ON()) for hw state sanity checks to check for unexpected conditions | |
102 | * which may not necessarily be a user visible problem. This will either | |
103 | * WARN() or DRM_ERROR() depending on the verbose_checks moduleparam, to | |
104 | * enable distros and users to tailor their preferred amount of i915 abrt | |
105 | * spam. | |
106 | */ | |
107 | #define I915_STATE_WARN(condition, format...) ({ \ | |
108 | int __ret_warn_on = !!(condition); \ | |
32753cb8 JL |
109 | if (unlikely(__ret_warn_on)) \ |
110 | if (!WARN(i915.verbose_state_checks, format)) \ | |
e2c719b7 | 111 | DRM_ERROR(format); \ |
e2c719b7 RC |
112 | unlikely(__ret_warn_on); \ |
113 | }) | |
114 | ||
152b2262 JL |
115 | #define I915_STATE_WARN_ON(x) \ |
116 | I915_STATE_WARN((x), "%s", "WARN_ON(" __stringify(x) ")") | |
c883ef1b | 117 | |
4fec15d1 ID |
118 | bool __i915_inject_load_failure(const char *func, int line); |
119 | #define i915_inject_load_failure() \ | |
120 | __i915_inject_load_failure(__func__, __LINE__) | |
121 | ||
42a8ca4c JN |
122 | static inline const char *yesno(bool v) |
123 | { | |
124 | return v ? "yes" : "no"; | |
125 | } | |
126 | ||
87ad3212 JN |
127 | static inline const char *onoff(bool v) |
128 | { | |
129 | return v ? "on" : "off"; | |
130 | } | |
131 | ||
08c4d7fc TU |
132 | static inline const char *enableddisabled(bool v) |
133 | { | |
134 | return v ? "enabled" : "disabled"; | |
135 | } | |
136 | ||
317c35d1 | 137 | enum pipe { |
752aa88a | 138 | INVALID_PIPE = -1, |
317c35d1 JB |
139 | PIPE_A = 0, |
140 | PIPE_B, | |
9db4a9c7 | 141 | PIPE_C, |
a57c774a AK |
142 | _PIPE_EDP, |
143 | I915_MAX_PIPES = _PIPE_EDP | |
317c35d1 | 144 | }; |
9db4a9c7 | 145 | #define pipe_name(p) ((p) + 'A') |
317c35d1 | 146 | |
a5c961d1 PZ |
147 | enum transcoder { |
148 | TRANSCODER_A = 0, | |
149 | TRANSCODER_B, | |
150 | TRANSCODER_C, | |
a57c774a | 151 | TRANSCODER_EDP, |
4d1de975 JN |
152 | TRANSCODER_DSI_A, |
153 | TRANSCODER_DSI_C, | |
a57c774a | 154 | I915_MAX_TRANSCODERS |
a5c961d1 | 155 | }; |
da205630 JN |
156 | |
157 | static inline const char *transcoder_name(enum transcoder transcoder) | |
158 | { | |
159 | switch (transcoder) { | |
160 | case TRANSCODER_A: | |
161 | return "A"; | |
162 | case TRANSCODER_B: | |
163 | return "B"; | |
164 | case TRANSCODER_C: | |
165 | return "C"; | |
166 | case TRANSCODER_EDP: | |
167 | return "EDP"; | |
4d1de975 JN |
168 | case TRANSCODER_DSI_A: |
169 | return "DSI A"; | |
170 | case TRANSCODER_DSI_C: | |
171 | return "DSI C"; | |
da205630 JN |
172 | default: |
173 | return "<invalid>"; | |
174 | } | |
175 | } | |
a5c961d1 | 176 | |
4d1de975 JN |
177 | static inline bool transcoder_is_dsi(enum transcoder transcoder) |
178 | { | |
179 | return transcoder == TRANSCODER_DSI_A || transcoder == TRANSCODER_DSI_C; | |
180 | } | |
181 | ||
84139d1e | 182 | /* |
b14e5848 VS |
183 | * Global legacy plane identifier. Valid only for primary/sprite |
184 | * planes on pre-g4x, and only for primary planes on g4x+. | |
84139d1e | 185 | */ |
80824003 | 186 | enum plane { |
b14e5848 | 187 | PLANE_A, |
80824003 | 188 | PLANE_B, |
9db4a9c7 | 189 | PLANE_C, |
80824003 | 190 | }; |
9db4a9c7 | 191 | #define plane_name(p) ((p) + 'A') |
52440211 | 192 | |
580503c7 | 193 | #define sprite_name(p, s) ((p) * INTEL_INFO(dev_priv)->num_sprites[(p)] + (s) + 'A') |
06da8da2 | 194 | |
b14e5848 VS |
195 | /* |
196 | * Per-pipe plane identifier. | |
197 | * I915_MAX_PLANES in the enum below is the maximum (across all platforms) | |
198 | * number of planes per CRTC. Not all platforms really have this many planes, | |
199 | * which means some arrays of size I915_MAX_PLANES may have unused entries | |
200 | * between the topmost sprite plane and the cursor plane. | |
201 | * | |
202 | * This is expected to be passed to various register macros | |
203 | * (eg. PLANE_CTL(), PS_PLANE_SEL(), etc.) so adjust with care. | |
204 | */ | |
205 | enum plane_id { | |
206 | PLANE_PRIMARY, | |
207 | PLANE_SPRITE0, | |
208 | PLANE_SPRITE1, | |
209 | PLANE_CURSOR, | |
210 | I915_MAX_PLANES, | |
211 | }; | |
212 | ||
d97d7b48 VS |
213 | #define for_each_plane_id_on_crtc(__crtc, __p) \ |
214 | for ((__p) = PLANE_PRIMARY; (__p) < I915_MAX_PLANES; (__p)++) \ | |
215 | for_each_if ((__crtc)->plane_ids_mask & BIT(__p)) | |
216 | ||
2b139522 | 217 | enum port { |
03cdc1d4 | 218 | PORT_NONE = -1, |
2b139522 ED |
219 | PORT_A = 0, |
220 | PORT_B, | |
221 | PORT_C, | |
222 | PORT_D, | |
223 | PORT_E, | |
224 | I915_MAX_PORTS | |
225 | }; | |
226 | #define port_name(p) ((p) + 'A') | |
227 | ||
a09caddd | 228 | #define I915_NUM_PHYS_VLV 2 |
e4607fcf CML |
229 | |
230 | enum dpio_channel { | |
231 | DPIO_CH0, | |
232 | DPIO_CH1 | |
233 | }; | |
234 | ||
235 | enum dpio_phy { | |
236 | DPIO_PHY0, | |
237 | DPIO_PHY1 | |
238 | }; | |
239 | ||
b97186f0 PZ |
240 | enum intel_display_power_domain { |
241 | POWER_DOMAIN_PIPE_A, | |
242 | POWER_DOMAIN_PIPE_B, | |
243 | POWER_DOMAIN_PIPE_C, | |
244 | POWER_DOMAIN_PIPE_A_PANEL_FITTER, | |
245 | POWER_DOMAIN_PIPE_B_PANEL_FITTER, | |
246 | POWER_DOMAIN_PIPE_C_PANEL_FITTER, | |
247 | POWER_DOMAIN_TRANSCODER_A, | |
248 | POWER_DOMAIN_TRANSCODER_B, | |
249 | POWER_DOMAIN_TRANSCODER_C, | |
f52e353e | 250 | POWER_DOMAIN_TRANSCODER_EDP, |
4d1de975 JN |
251 | POWER_DOMAIN_TRANSCODER_DSI_A, |
252 | POWER_DOMAIN_TRANSCODER_DSI_C, | |
6331a704 PJ |
253 | POWER_DOMAIN_PORT_DDI_A_LANES, |
254 | POWER_DOMAIN_PORT_DDI_B_LANES, | |
255 | POWER_DOMAIN_PORT_DDI_C_LANES, | |
256 | POWER_DOMAIN_PORT_DDI_D_LANES, | |
257 | POWER_DOMAIN_PORT_DDI_E_LANES, | |
319be8ae ID |
258 | POWER_DOMAIN_PORT_DSI, |
259 | POWER_DOMAIN_PORT_CRT, | |
260 | POWER_DOMAIN_PORT_OTHER, | |
cdf8dd7f | 261 | POWER_DOMAIN_VGA, |
fbeeaa23 | 262 | POWER_DOMAIN_AUDIO, |
bd2bb1b9 | 263 | POWER_DOMAIN_PLLS, |
1407121a S |
264 | POWER_DOMAIN_AUX_A, |
265 | POWER_DOMAIN_AUX_B, | |
266 | POWER_DOMAIN_AUX_C, | |
267 | POWER_DOMAIN_AUX_D, | |
f0ab43e6 | 268 | POWER_DOMAIN_GMBUS, |
dfa57627 | 269 | POWER_DOMAIN_MODESET, |
baa70707 | 270 | POWER_DOMAIN_INIT, |
bddc7645 ID |
271 | |
272 | POWER_DOMAIN_NUM, | |
b97186f0 PZ |
273 | }; |
274 | ||
275 | #define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A) | |
276 | #define POWER_DOMAIN_PIPE_PANEL_FITTER(pipe) \ | |
277 | ((pipe) + POWER_DOMAIN_PIPE_A_PANEL_FITTER) | |
f52e353e ID |
278 | #define POWER_DOMAIN_TRANSCODER(tran) \ |
279 | ((tran) == TRANSCODER_EDP ? POWER_DOMAIN_TRANSCODER_EDP : \ | |
280 | (tran) + POWER_DOMAIN_TRANSCODER_A) | |
b97186f0 | 281 | |
1d843f9d EE |
282 | enum hpd_pin { |
283 | HPD_NONE = 0, | |
1d843f9d EE |
284 | HPD_TV = HPD_NONE, /* TV is known to be unreliable */ |
285 | HPD_CRT, | |
286 | HPD_SDVO_B, | |
287 | HPD_SDVO_C, | |
cc24fcdc | 288 | HPD_PORT_A, |
1d843f9d EE |
289 | HPD_PORT_B, |
290 | HPD_PORT_C, | |
291 | HPD_PORT_D, | |
26951caf | 292 | HPD_PORT_E, |
1d843f9d EE |
293 | HPD_NUM_PINS |
294 | }; | |
295 | ||
c91711f9 JN |
296 | #define for_each_hpd_pin(__pin) \ |
297 | for ((__pin) = (HPD_NONE + 1); (__pin) < HPD_NUM_PINS; (__pin)++) | |
298 | ||
5fcece80 JN |
299 | struct i915_hotplug { |
300 | struct work_struct hotplug_work; | |
301 | ||
302 | struct { | |
303 | unsigned long last_jiffies; | |
304 | int count; | |
305 | enum { | |
306 | HPD_ENABLED = 0, | |
307 | HPD_DISABLED = 1, | |
308 | HPD_MARK_DISABLED = 2 | |
309 | } state; | |
310 | } stats[HPD_NUM_PINS]; | |
311 | u32 event_bits; | |
312 | struct delayed_work reenable_work; | |
313 | ||
314 | struct intel_digital_port *irq_port[I915_MAX_PORTS]; | |
315 | u32 long_port_mask; | |
316 | u32 short_port_mask; | |
317 | struct work_struct dig_port_work; | |
318 | ||
19625e85 L |
319 | struct work_struct poll_init_work; |
320 | bool poll_enabled; | |
321 | ||
5fcece80 JN |
322 | /* |
323 | * if we get a HPD irq from DP and a HPD irq from non-DP | |
324 | * the non-DP HPD could block the workqueue on a mode config | |
325 | * mutex getting, that userspace may have taken. However | |
326 | * userspace is waiting on the DP workqueue to run which is | |
327 | * blocked behind the non-DP one. | |
328 | */ | |
329 | struct workqueue_struct *dp_wq; | |
330 | }; | |
331 | ||
2a2d5482 CW |
332 | #define I915_GEM_GPU_DOMAINS \ |
333 | (I915_GEM_DOMAIN_RENDER | \ | |
334 | I915_GEM_DOMAIN_SAMPLER | \ | |
335 | I915_GEM_DOMAIN_COMMAND | \ | |
336 | I915_GEM_DOMAIN_INSTRUCTION | \ | |
337 | I915_GEM_DOMAIN_VERTEX) | |
62fdfeaf | 338 | |
055e393f DL |
339 | #define for_each_pipe(__dev_priv, __p) \ |
340 | for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++) | |
6831f3e3 VS |
341 | #define for_each_pipe_masked(__dev_priv, __p, __mask) \ |
342 | for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++) \ | |
343 | for_each_if ((__mask) & (1 << (__p))) | |
8b364b41 | 344 | #define for_each_universal_plane(__dev_priv, __pipe, __p) \ |
dd740780 DL |
345 | for ((__p) = 0; \ |
346 | (__p) < INTEL_INFO(__dev_priv)->num_sprites[(__pipe)] + 1; \ | |
347 | (__p)++) | |
3bdcfc0c DL |
348 | #define for_each_sprite(__dev_priv, __p, __s) \ |
349 | for ((__s) = 0; \ | |
350 | (__s) < INTEL_INFO(__dev_priv)->num_sprites[(__p)]; \ | |
351 | (__s)++) | |
9db4a9c7 | 352 | |
c3aeadc8 JN |
353 | #define for_each_port_masked(__port, __ports_mask) \ |
354 | for ((__port) = PORT_A; (__port) < I915_MAX_PORTS; (__port)++) \ | |
355 | for_each_if ((__ports_mask) & (1 << (__port))) | |
356 | ||
d79b814d | 357 | #define for_each_crtc(dev, crtc) \ |
91c8a326 | 358 | list_for_each_entry(crtc, &(dev)->mode_config.crtc_list, head) |
d79b814d | 359 | |
27321ae8 ML |
360 | #define for_each_intel_plane(dev, intel_plane) \ |
361 | list_for_each_entry(intel_plane, \ | |
91c8a326 | 362 | &(dev)->mode_config.plane_list, \ |
27321ae8 ML |
363 | base.head) |
364 | ||
c107acfe | 365 | #define for_each_intel_plane_mask(dev, intel_plane, plane_mask) \ |
91c8a326 CW |
366 | list_for_each_entry(intel_plane, \ |
367 | &(dev)->mode_config.plane_list, \ | |
c107acfe MR |
368 | base.head) \ |
369 | for_each_if ((plane_mask) & \ | |
370 | (1 << drm_plane_index(&intel_plane->base))) | |
371 | ||
262cd2e1 VS |
372 | #define for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) \ |
373 | list_for_each_entry(intel_plane, \ | |
374 | &(dev)->mode_config.plane_list, \ | |
375 | base.head) \ | |
95150bdf | 376 | for_each_if ((intel_plane)->pipe == (intel_crtc)->pipe) |
262cd2e1 | 377 | |
91c8a326 CW |
378 | #define for_each_intel_crtc(dev, intel_crtc) \ |
379 | list_for_each_entry(intel_crtc, \ | |
380 | &(dev)->mode_config.crtc_list, \ | |
381 | base.head) | |
d063ae48 | 382 | |
91c8a326 CW |
383 | #define for_each_intel_crtc_mask(dev, intel_crtc, crtc_mask) \ |
384 | list_for_each_entry(intel_crtc, \ | |
385 | &(dev)->mode_config.crtc_list, \ | |
386 | base.head) \ | |
98d39494 MR |
387 | for_each_if ((crtc_mask) & (1 << drm_crtc_index(&intel_crtc->base))) |
388 | ||
b2784e15 DL |
389 | #define for_each_intel_encoder(dev, intel_encoder) \ |
390 | list_for_each_entry(intel_encoder, \ | |
391 | &(dev)->mode_config.encoder_list, \ | |
392 | base.head) | |
393 | ||
3a3371ff ACO |
394 | #define for_each_intel_connector(dev, intel_connector) \ |
395 | list_for_each_entry(intel_connector, \ | |
91c8a326 | 396 | &(dev)->mode_config.connector_list, \ |
3a3371ff ACO |
397 | base.head) |
398 | ||
6c2b7c12 DV |
399 | #define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \ |
400 | list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \ | |
95150bdf | 401 | for_each_if ((intel_encoder)->base.crtc == (__crtc)) |
6c2b7c12 | 402 | |
53f5e3ca JB |
403 | #define for_each_connector_on_encoder(dev, __encoder, intel_connector) \ |
404 | list_for_each_entry((intel_connector), &(dev)->mode_config.connector_list, base.head) \ | |
95150bdf | 405 | for_each_if ((intel_connector)->base.encoder == (__encoder)) |
53f5e3ca | 406 | |
b04c5bd6 BF |
407 | #define for_each_power_domain(domain, mask) \ |
408 | for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \ | |
95150bdf | 409 | for_each_if ((1 << (domain)) & (mask)) |
b04c5bd6 | 410 | |
e7b903d2 | 411 | struct drm_i915_private; |
ad46cb53 | 412 | struct i915_mm_struct; |
5cc9ed4b | 413 | struct i915_mmu_object; |
e7b903d2 | 414 | |
a6f766f3 CW |
415 | struct drm_i915_file_private { |
416 | struct drm_i915_private *dev_priv; | |
417 | struct drm_file *file; | |
418 | ||
419 | struct { | |
420 | spinlock_t lock; | |
421 | struct list_head request_list; | |
d0bc54f2 CW |
422 | /* 20ms is a fairly arbitrary limit (greater than the average frame time) |
423 | * chosen to prevent the CPU getting more than a frame ahead of the GPU | |
424 | * (when using lax throttling for the frontbuffer). We also use it to | |
425 | * offer free GPU waitboosts for severely congested workloads. | |
426 | */ | |
427 | #define DRM_I915_THROTTLE_JIFFIES msecs_to_jiffies(20) | |
a6f766f3 CW |
428 | } mm; |
429 | struct idr context_idr; | |
430 | ||
2e1b8730 CW |
431 | struct intel_rps_client { |
432 | struct list_head link; | |
433 | unsigned boosts; | |
434 | } rps; | |
a6f766f3 | 435 | |
c80ff16e | 436 | unsigned int bsd_engine; |
b083a087 MK |
437 | |
438 | /* Client can have a maximum of 3 contexts banned before | |
439 | * it is denied of creating new contexts. As one context | |
440 | * ban needs 4 consecutive hangs, and more if there is | |
441 | * progress in between, this is a last resort stop gap measure | |
442 | * to limit the badly behaving clients access to gpu. | |
443 | */ | |
444 | #define I915_MAX_CLIENT_CONTEXT_BANS 3 | |
445 | int context_bans; | |
a6f766f3 CW |
446 | }; |
447 | ||
e69d0bc1 DV |
448 | /* Used by dp and fdi links */ |
449 | struct intel_link_m_n { | |
450 | uint32_t tu; | |
451 | uint32_t gmch_m; | |
452 | uint32_t gmch_n; | |
453 | uint32_t link_m; | |
454 | uint32_t link_n; | |
455 | }; | |
456 | ||
457 | void intel_link_compute_m_n(int bpp, int nlanes, | |
458 | int pixel_clock, int link_clock, | |
459 | struct intel_link_m_n *m_n); | |
460 | ||
1da177e4 LT |
461 | /* Interface history: |
462 | * | |
463 | * 1.1: Original. | |
0d6aa60b DA |
464 | * 1.2: Add Power Management |
465 | * 1.3: Add vblank support | |
de227f5f | 466 | * 1.4: Fix cmdbuffer path, add heap destroy |
702880f2 | 467 | * 1.5: Add vblank pipe configuration |
2228ed67 MD |
468 | * 1.6: - New ioctl for scheduling buffer swaps on vertical blank |
469 | * - Support vertical blank on secondary display pipe | |
1da177e4 LT |
470 | */ |
471 | #define DRIVER_MAJOR 1 | |
2228ed67 | 472 | #define DRIVER_MINOR 6 |
1da177e4 LT |
473 | #define DRIVER_PATCHLEVEL 0 |
474 | ||
0a3e67a4 JB |
475 | struct opregion_header; |
476 | struct opregion_acpi; | |
477 | struct opregion_swsci; | |
478 | struct opregion_asle; | |
479 | ||
8ee1c3db | 480 | struct intel_opregion { |
115719fc WD |
481 | struct opregion_header *header; |
482 | struct opregion_acpi *acpi; | |
483 | struct opregion_swsci *swsci; | |
ebde53c7 JN |
484 | u32 swsci_gbda_sub_functions; |
485 | u32 swsci_sbcb_sub_functions; | |
115719fc | 486 | struct opregion_asle *asle; |
04ebaadb | 487 | void *rvda; |
82730385 | 488 | const void *vbt; |
ada8f955 | 489 | u32 vbt_size; |
115719fc | 490 | u32 *lid_state; |
91a60f20 | 491 | struct work_struct asle_work; |
8ee1c3db | 492 | }; |
44834a67 | 493 | #define OPREGION_SIZE (8*1024) |
8ee1c3db | 494 | |
6ef3d427 CW |
495 | struct intel_overlay; |
496 | struct intel_overlay_error_state; | |
497 | ||
9b9d172d | 498 | struct sdvo_device_mapping { |
e957d772 | 499 | u8 initialized; |
9b9d172d | 500 | u8 dvo_port; |
501 | u8 slave_addr; | |
502 | u8 dvo_wiring; | |
e957d772 | 503 | u8 i2c_pin; |
b1083333 | 504 | u8 ddc_pin; |
9b9d172d | 505 | }; |
506 | ||
7bd688cd | 507 | struct intel_connector; |
820d2d77 | 508 | struct intel_encoder; |
ccf010fb | 509 | struct intel_atomic_state; |
5cec258b | 510 | struct intel_crtc_state; |
5724dbd1 | 511 | struct intel_initial_plane_config; |
0e8ffe1b | 512 | struct intel_crtc; |
ee9300bb DV |
513 | struct intel_limit; |
514 | struct dpll; | |
b8cecdf5 | 515 | |
e70236a8 | 516 | struct drm_i915_display_funcs { |
1353c4fb | 517 | int (*get_display_clock_speed)(struct drm_i915_private *dev_priv); |
ef0f5e93 | 518 | int (*get_fifo_size)(struct drm_i915_private *dev_priv, int plane); |
e3bddded | 519 | int (*compute_pipe_wm)(struct intel_crtc_state *cstate); |
ed4a6a7c MR |
520 | int (*compute_intermediate_wm)(struct drm_device *dev, |
521 | struct intel_crtc *intel_crtc, | |
522 | struct intel_crtc_state *newstate); | |
ccf010fb ML |
523 | void (*initial_watermarks)(struct intel_atomic_state *state, |
524 | struct intel_crtc_state *cstate); | |
525 | void (*atomic_update_watermarks)(struct intel_atomic_state *state, | |
526 | struct intel_crtc_state *cstate); | |
527 | void (*optimize_watermarks)(struct intel_atomic_state *state, | |
528 | struct intel_crtc_state *cstate); | |
98d39494 | 529 | int (*compute_global_watermarks)(struct drm_atomic_state *state); |
432081bc | 530 | void (*update_wm)(struct intel_crtc *crtc); |
27c329ed ML |
531 | int (*modeset_calc_cdclk)(struct drm_atomic_state *state); |
532 | void (*modeset_commit_cdclk)(struct drm_atomic_state *state); | |
0e8ffe1b DV |
533 | /* Returns the active state of the crtc, and if the crtc is active, |
534 | * fills out the pipe-config with the hw state. */ | |
535 | bool (*get_pipe_config)(struct intel_crtc *, | |
5cec258b | 536 | struct intel_crtc_state *); |
5724dbd1 DL |
537 | void (*get_initial_plane_config)(struct intel_crtc *, |
538 | struct intel_initial_plane_config *); | |
190f68c5 ACO |
539 | int (*crtc_compute_clock)(struct intel_crtc *crtc, |
540 | struct intel_crtc_state *crtc_state); | |
4a806558 ML |
541 | void (*crtc_enable)(struct intel_crtc_state *pipe_config, |
542 | struct drm_atomic_state *old_state); | |
543 | void (*crtc_disable)(struct intel_crtc_state *old_crtc_state, | |
544 | struct drm_atomic_state *old_state); | |
896e5bb0 L |
545 | void (*update_crtcs)(struct drm_atomic_state *state, |
546 | unsigned int *crtc_vblank_mask); | |
69bfe1a9 JN |
547 | void (*audio_codec_enable)(struct drm_connector *connector, |
548 | struct intel_encoder *encoder, | |
5e7234c9 | 549 | const struct drm_display_mode *adjusted_mode); |
69bfe1a9 | 550 | void (*audio_codec_disable)(struct intel_encoder *encoder); |
674cf967 | 551 | void (*fdi_link_train)(struct drm_crtc *crtc); |
46f16e63 | 552 | void (*init_clock_gating)(struct drm_i915_private *dev_priv); |
5a21b665 DV |
553 | int (*queue_flip)(struct drm_device *dev, struct drm_crtc *crtc, |
554 | struct drm_framebuffer *fb, | |
555 | struct drm_i915_gem_object *obj, | |
556 | struct drm_i915_gem_request *req, | |
557 | uint32_t flags); | |
91d14251 | 558 | void (*hpd_irq_setup)(struct drm_i915_private *dev_priv); |
e70236a8 JB |
559 | /* clock updates for mode set */ |
560 | /* cursor updates */ | |
561 | /* render clock increase/decrease */ | |
562 | /* display clock increase/decrease */ | |
563 | /* pll clock increase/decrease */ | |
8563b1e8 | 564 | |
b95c5321 ML |
565 | void (*load_csc_matrix)(struct drm_crtc_state *crtc_state); |
566 | void (*load_luts)(struct drm_crtc_state *crtc_state); | |
e70236a8 JB |
567 | }; |
568 | ||
48c1026a MK |
569 | enum forcewake_domain_id { |
570 | FW_DOMAIN_ID_RENDER = 0, | |
571 | FW_DOMAIN_ID_BLITTER, | |
572 | FW_DOMAIN_ID_MEDIA, | |
573 | ||
574 | FW_DOMAIN_ID_COUNT | |
575 | }; | |
576 | ||
577 | enum forcewake_domains { | |
578 | FORCEWAKE_RENDER = (1 << FW_DOMAIN_ID_RENDER), | |
579 | FORCEWAKE_BLITTER = (1 << FW_DOMAIN_ID_BLITTER), | |
580 | FORCEWAKE_MEDIA = (1 << FW_DOMAIN_ID_MEDIA), | |
581 | FORCEWAKE_ALL = (FORCEWAKE_RENDER | | |
582 | FORCEWAKE_BLITTER | | |
583 | FORCEWAKE_MEDIA) | |
584 | }; | |
585 | ||
3756685a TU |
586 | #define FW_REG_READ (1) |
587 | #define FW_REG_WRITE (2) | |
588 | ||
85ee17eb PP |
589 | enum decoupled_power_domain { |
590 | GEN9_DECOUPLED_PD_BLITTER = 0, | |
591 | GEN9_DECOUPLED_PD_RENDER, | |
592 | GEN9_DECOUPLED_PD_MEDIA, | |
593 | GEN9_DECOUPLED_PD_ALL | |
594 | }; | |
595 | ||
596 | enum decoupled_ops { | |
597 | GEN9_DECOUPLED_OP_WRITE = 0, | |
598 | GEN9_DECOUPLED_OP_READ | |
599 | }; | |
600 | ||
3756685a TU |
601 | enum forcewake_domains |
602 | intel_uncore_forcewake_for_reg(struct drm_i915_private *dev_priv, | |
603 | i915_reg_t reg, unsigned int op); | |
604 | ||
907b28c5 | 605 | struct intel_uncore_funcs { |
c8d9a590 | 606 | void (*force_wake_get)(struct drm_i915_private *dev_priv, |
48c1026a | 607 | enum forcewake_domains domains); |
c8d9a590 | 608 | void (*force_wake_put)(struct drm_i915_private *dev_priv, |
48c1026a | 609 | enum forcewake_domains domains); |
0b274481 | 610 | |
f0f59a00 VS |
611 | uint8_t (*mmio_readb)(struct drm_i915_private *dev_priv, i915_reg_t r, bool trace); |
612 | uint16_t (*mmio_readw)(struct drm_i915_private *dev_priv, i915_reg_t r, bool trace); | |
613 | uint32_t (*mmio_readl)(struct drm_i915_private *dev_priv, i915_reg_t r, bool trace); | |
614 | uint64_t (*mmio_readq)(struct drm_i915_private *dev_priv, i915_reg_t r, bool trace); | |
0b274481 | 615 | |
f0f59a00 | 616 | void (*mmio_writeb)(struct drm_i915_private *dev_priv, i915_reg_t r, |
0b274481 | 617 | uint8_t val, bool trace); |
f0f59a00 | 618 | void (*mmio_writew)(struct drm_i915_private *dev_priv, i915_reg_t r, |
0b274481 | 619 | uint16_t val, bool trace); |
f0f59a00 | 620 | void (*mmio_writel)(struct drm_i915_private *dev_priv, i915_reg_t r, |
0b274481 | 621 | uint32_t val, bool trace); |
990bbdad CW |
622 | }; |
623 | ||
15157970 TU |
624 | struct intel_forcewake_range { |
625 | u32 start; | |
626 | u32 end; | |
627 | ||
628 | enum forcewake_domains domains; | |
629 | }; | |
630 | ||
907b28c5 CW |
631 | struct intel_uncore { |
632 | spinlock_t lock; /** lock is also taken in irq contexts. */ | |
633 | ||
15157970 TU |
634 | const struct intel_forcewake_range *fw_domains_table; |
635 | unsigned int fw_domains_table_entries; | |
636 | ||
907b28c5 CW |
637 | struct intel_uncore_funcs funcs; |
638 | ||
639 | unsigned fifo_count; | |
003342a5 | 640 | |
48c1026a | 641 | enum forcewake_domains fw_domains; |
003342a5 | 642 | enum forcewake_domains fw_domains_active; |
b2cff0db CW |
643 | |
644 | struct intel_uncore_forcewake_domain { | |
645 | struct drm_i915_private *i915; | |
48c1026a | 646 | enum forcewake_domain_id id; |
33c582c1 | 647 | enum forcewake_domains mask; |
b2cff0db | 648 | unsigned wake_count; |
a57a4a67 | 649 | struct hrtimer timer; |
f0f59a00 | 650 | i915_reg_t reg_set; |
05a2fb15 MK |
651 | u32 val_set; |
652 | u32 val_clear; | |
f0f59a00 VS |
653 | i915_reg_t reg_ack; |
654 | i915_reg_t reg_post; | |
05a2fb15 | 655 | u32 val_reset; |
b2cff0db | 656 | } fw_domain[FW_DOMAIN_ID_COUNT]; |
75714940 MK |
657 | |
658 | int unclaimed_mmio_check; | |
b2cff0db CW |
659 | }; |
660 | ||
661 | /* Iterate over initialised fw domains */ | |
33c582c1 TU |
662 | #define for_each_fw_domain_masked(domain__, mask__, dev_priv__) \ |
663 | for ((domain__) = &(dev_priv__)->uncore.fw_domain[0]; \ | |
664 | (domain__) < &(dev_priv__)->uncore.fw_domain[FW_DOMAIN_ID_COUNT]; \ | |
665 | (domain__)++) \ | |
666 | for_each_if ((mask__) & (domain__)->mask) | |
667 | ||
668 | #define for_each_fw_domain(domain__, dev_priv__) \ | |
669 | for_each_fw_domain_masked(domain__, FORCEWAKE_ALL, dev_priv__) | |
907b28c5 | 670 | |
b6e7d894 DL |
671 | #define CSR_VERSION(major, minor) ((major) << 16 | (minor)) |
672 | #define CSR_VERSION_MAJOR(version) ((version) >> 16) | |
673 | #define CSR_VERSION_MINOR(version) ((version) & 0xffff) | |
674 | ||
eb805623 | 675 | struct intel_csr { |
8144ac59 | 676 | struct work_struct work; |
eb805623 | 677 | const char *fw_path; |
a7f749f9 | 678 | uint32_t *dmc_payload; |
eb805623 | 679 | uint32_t dmc_fw_size; |
b6e7d894 | 680 | uint32_t version; |
eb805623 | 681 | uint32_t mmio_count; |
f0f59a00 | 682 | i915_reg_t mmioaddr[8]; |
eb805623 | 683 | uint32_t mmiodata[8]; |
832dba88 | 684 | uint32_t dc_state; |
a37baf3b | 685 | uint32_t allowed_dc_mask; |
eb805623 DV |
686 | }; |
687 | ||
604db650 | 688 | #define DEV_INFO_FOR_EACH_FLAG(func) \ |
566c56a4 | 689 | /* Keep is_* in chronological order */ \ |
604db650 JL |
690 | func(is_mobile); \ |
691 | func(is_i85x); \ | |
692 | func(is_i915g); \ | |
693 | func(is_i945gm); \ | |
694 | func(is_g33); \ | |
604db650 JL |
695 | func(is_g4x); \ |
696 | func(is_pineview); \ | |
697 | func(is_broadwater); \ | |
698 | func(is_crestline); \ | |
699 | func(is_ivybridge); \ | |
700 | func(is_valleyview); \ | |
701 | func(is_cherryview); \ | |
702 | func(is_haswell); \ | |
703 | func(is_broadwell); \ | |
704 | func(is_skylake); \ | |
705 | func(is_broxton); \ | |
706 | func(is_kabylake); \ | |
c007fb4a | 707 | func(is_alpha_support); \ |
566c56a4 | 708 | /* Keep has_* in alphabetical order */ \ |
dfc5148f | 709 | func(has_64bit_reloc); \ |
604db650 | 710 | func(has_csr); \ |
566c56a4 | 711 | func(has_ddi); \ |
604db650 | 712 | func(has_dp_mst); \ |
566c56a4 JL |
713 | func(has_fbc); \ |
714 | func(has_fpga_dbg); \ | |
604db650 | 715 | func(has_gmbus_irq); \ |
604db650 JL |
716 | func(has_gmch_display); \ |
717 | func(has_guc); \ | |
604db650 | 718 | func(has_hotplug); \ |
566c56a4 JL |
719 | func(has_hw_contexts); \ |
720 | func(has_l3_dpf); \ | |
604db650 | 721 | func(has_llc); \ |
566c56a4 JL |
722 | func(has_logical_ring_contexts); \ |
723 | func(has_overlay); \ | |
724 | func(has_pipe_cxsr); \ | |
725 | func(has_pooled_eu); \ | |
726 | func(has_psr); \ | |
727 | func(has_rc6); \ | |
728 | func(has_rc6p); \ | |
729 | func(has_resource_streamer); \ | |
730 | func(has_runtime_pm); \ | |
604db650 | 731 | func(has_snoop); \ |
566c56a4 JL |
732 | func(cursor_needs_physical); \ |
733 | func(hws_needs_physical); \ | |
734 | func(overlay_needs_physical); \ | |
85ee17eb PP |
735 | func(supports_tv); \ |
736 | func(has_decoupled_mmio) | |
c96ea64e | 737 | |
915490d5 | 738 | struct sseu_dev_info { |
f08a0c92 | 739 | u8 slice_mask; |
57ec171e | 740 | u8 subslice_mask; |
915490d5 ID |
741 | u8 eu_total; |
742 | u8 eu_per_subslice; | |
43b67998 ID |
743 | u8 min_eu_in_pool; |
744 | /* For each slice, which subslice(s) has(have) 7 EUs (bitfield)? */ | |
745 | u8 subslice_7eu[3]; | |
746 | u8 has_slice_pg:1; | |
747 | u8 has_subslice_pg:1; | |
748 | u8 has_eu_pg:1; | |
915490d5 ID |
749 | }; |
750 | ||
57ec171e ID |
751 | static inline unsigned int sseu_subslice_total(const struct sseu_dev_info *sseu) |
752 | { | |
753 | return hweight8(sseu->slice_mask) * hweight8(sseu->subslice_mask); | |
754 | } | |
755 | ||
cfdf1fa2 | 756 | struct intel_device_info { |
10fce67a | 757 | u32 display_mmio_offset; |
87f1f465 | 758 | u16 device_id; |
ac208a8b | 759 | u8 num_pipes; |
d615a166 | 760 | u8 num_sprites[I915_MAX_PIPES]; |
c96c3a8c | 761 | u8 gen; |
ae5702d2 | 762 | u16 gen_mask; |
73ae478c | 763 | u8 ring_mask; /* Rings supported by the HW */ |
c1bb1145 | 764 | u8 num_rings; |
604db650 JL |
765 | #define DEFINE_FLAG(name) u8 name:1 |
766 | DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG); | |
767 | #undef DEFINE_FLAG | |
6f3fff60 | 768 | u16 ddb_size; /* in blocks */ |
a57c774a AK |
769 | /* Register offsets for the various display pipes and transcoders */ |
770 | int pipe_offsets[I915_MAX_TRANSCODERS]; | |
771 | int trans_offsets[I915_MAX_TRANSCODERS]; | |
a57c774a | 772 | int palette_offsets[I915_MAX_PIPES]; |
5efb3e28 | 773 | int cursor_offsets[I915_MAX_PIPES]; |
3873218f JM |
774 | |
775 | /* Slice/subslice/EU info */ | |
43b67998 | 776 | struct sseu_dev_info sseu; |
82cf435b LL |
777 | |
778 | struct color_luts { | |
779 | u16 degamma_lut_size; | |
780 | u16 gamma_lut_size; | |
781 | } color; | |
cfdf1fa2 KH |
782 | }; |
783 | ||
2bd160a1 CW |
784 | struct intel_display_error_state; |
785 | ||
786 | struct drm_i915_error_state { | |
787 | struct kref ref; | |
788 | struct timeval time; | |
de867c20 CW |
789 | struct timeval boottime; |
790 | struct timeval uptime; | |
2bd160a1 | 791 | |
9f267eb8 CW |
792 | struct drm_i915_private *i915; |
793 | ||
2bd160a1 CW |
794 | char error_msg[128]; |
795 | bool simulated; | |
796 | int iommu; | |
797 | u32 reset_count; | |
798 | u32 suspend_count; | |
799 | struct intel_device_info device_info; | |
800 | ||
801 | /* Generic register state */ | |
802 | u32 eir; | |
803 | u32 pgtbl_er; | |
804 | u32 ier; | |
805 | u32 gtier[4]; | |
806 | u32 ccid; | |
807 | u32 derrmr; | |
808 | u32 forcewake; | |
809 | u32 error; /* gen6+ */ | |
810 | u32 err_int; /* gen7 */ | |
811 | u32 fault_data0; /* gen8, gen9 */ | |
812 | u32 fault_data1; /* gen8, gen9 */ | |
813 | u32 done_reg; | |
814 | u32 gac_eco; | |
815 | u32 gam_ecochk; | |
816 | u32 gab_ctl; | |
817 | u32 gfx_mode; | |
d636951e | 818 | |
2bd160a1 CW |
819 | u64 fence[I915_MAX_NUM_FENCES]; |
820 | struct intel_overlay_error_state *overlay; | |
821 | struct intel_display_error_state *display; | |
51d545d0 | 822 | struct drm_i915_error_object *semaphore; |
27b85bea | 823 | struct drm_i915_error_object *guc_log; |
2bd160a1 CW |
824 | |
825 | struct drm_i915_error_engine { | |
826 | int engine_id; | |
827 | /* Software tracked state */ | |
828 | bool waiting; | |
829 | int num_waiters; | |
3fe3b030 MK |
830 | unsigned long hangcheck_timestamp; |
831 | bool hangcheck_stalled; | |
2bd160a1 CW |
832 | enum intel_engine_hangcheck_action hangcheck_action; |
833 | struct i915_address_space *vm; | |
834 | int num_requests; | |
835 | ||
cdb324bd CW |
836 | /* position of active request inside the ring */ |
837 | u32 rq_head, rq_post, rq_tail; | |
838 | ||
2bd160a1 CW |
839 | /* our own tracking of ring head and tail */ |
840 | u32 cpu_ring_head; | |
841 | u32 cpu_ring_tail; | |
842 | ||
843 | u32 last_seqno; | |
2bd160a1 CW |
844 | |
845 | /* Register state */ | |
846 | u32 start; | |
847 | u32 tail; | |
848 | u32 head; | |
849 | u32 ctl; | |
21a2c58a | 850 | u32 mode; |
2bd160a1 CW |
851 | u32 hws; |
852 | u32 ipeir; | |
853 | u32 ipehr; | |
2bd160a1 CW |
854 | u32 bbstate; |
855 | u32 instpm; | |
856 | u32 instps; | |
857 | u32 seqno; | |
858 | u64 bbaddr; | |
859 | u64 acthd; | |
860 | u32 fault_reg; | |
861 | u64 faddr; | |
862 | u32 rc_psmi; /* sleep state */ | |
863 | u32 semaphore_mboxes[I915_NUM_ENGINES - 1]; | |
d636951e | 864 | struct intel_instdone instdone; |
2bd160a1 CW |
865 | |
866 | struct drm_i915_error_object { | |
2bd160a1 | 867 | u64 gtt_offset; |
03382dfb | 868 | u64 gtt_size; |
0a97015d CW |
869 | int page_count; |
870 | int unused; | |
2bd160a1 CW |
871 | u32 *pages[0]; |
872 | } *ringbuffer, *batchbuffer, *wa_batchbuffer, *ctx, *hws_page; | |
873 | ||
874 | struct drm_i915_error_object *wa_ctx; | |
875 | ||
876 | struct drm_i915_error_request { | |
877 | long jiffies; | |
c84455b4 | 878 | pid_t pid; |
35ca039e | 879 | u32 context; |
84102171 | 880 | int ban_score; |
2bd160a1 CW |
881 | u32 seqno; |
882 | u32 head; | |
883 | u32 tail; | |
35ca039e | 884 | } *requests, execlist[2]; |
2bd160a1 CW |
885 | |
886 | struct drm_i915_error_waiter { | |
887 | char comm[TASK_COMM_LEN]; | |
888 | pid_t pid; | |
889 | u32 seqno; | |
890 | } *waiters; | |
891 | ||
892 | struct { | |
893 | u32 gfx_mode; | |
894 | union { | |
895 | u64 pdp[4]; | |
896 | u32 pp_dir_base; | |
897 | }; | |
898 | } vm_info; | |
899 | ||
900 | pid_t pid; | |
901 | char comm[TASK_COMM_LEN]; | |
b083a087 | 902 | int context_bans; |
2bd160a1 CW |
903 | } engine[I915_NUM_ENGINES]; |
904 | ||
905 | struct drm_i915_error_buffer { | |
906 | u32 size; | |
907 | u32 name; | |
908 | u32 rseqno[I915_NUM_ENGINES], wseqno; | |
909 | u64 gtt_offset; | |
910 | u32 read_domains; | |
911 | u32 write_domain; | |
912 | s32 fence_reg:I915_MAX_NUM_FENCE_BITS; | |
913 | u32 tiling:2; | |
914 | u32 dirty:1; | |
915 | u32 purgeable:1; | |
916 | u32 userptr:1; | |
917 | s32 engine:4; | |
918 | u32 cache_level:3; | |
919 | } *active_bo[I915_NUM_ENGINES], *pinned_bo; | |
920 | u32 active_bo_count[I915_NUM_ENGINES], pinned_bo_count; | |
921 | struct i915_address_space *active_vm[I915_NUM_ENGINES]; | |
922 | }; | |
923 | ||
7faf1ab2 DV |
924 | enum i915_cache_level { |
925 | I915_CACHE_NONE = 0, | |
350ec881 CW |
926 | I915_CACHE_LLC, /* also used for snoopable memory on non-LLC */ |
927 | I915_CACHE_L3_LLC, /* gen7+, L3 sits between the domain specifc | |
928 | caches, eg sampler/render caches, and the | |
929 | large Last-Level-Cache. LLC is coherent with | |
930 | the CPU, but L3 is only visible to the GPU. */ | |
651d794f | 931 | I915_CACHE_WT, /* hsw:gt3e WriteThrough for scanouts */ |
7faf1ab2 DV |
932 | }; |
933 | ||
821d66dd | 934 | #define DEFAULT_CONTEXT_HANDLE 0 |
b1b38278 | 935 | |
31b7a88d | 936 | /** |
e2efd130 | 937 | * struct i915_gem_context - as the name implies, represents a context. |
31b7a88d OM |
938 | * @ref: reference count. |
939 | * @user_handle: userspace tracking identity for this context. | |
940 | * @remap_slice: l3 row remapping information. | |
b1b38278 DW |
941 | * @flags: context specific flags: |
942 | * CONTEXT_NO_ZEROMAP: do not allow mapping things to page 0. | |
31b7a88d OM |
943 | * @file_priv: filp associated with this context (NULL for global default |
944 | * context). | |
945 | * @hang_stats: information about the role of this context in possible GPU | |
946 | * hangs. | |
7df113e4 | 947 | * @ppgtt: virtual memory space used by this context. |
31b7a88d OM |
948 | * @legacy_hw_ctx: render context backing object and whether it is correctly |
949 | * initialized (legacy ring submission mechanism only). | |
950 | * @link: link in the global list of contexts. | |
951 | * | |
952 | * Contexts are memory images used by the hardware to store copies of their | |
953 | * internal state. | |
954 | */ | |
e2efd130 | 955 | struct i915_gem_context { |
dce3271b | 956 | struct kref ref; |
9ea4feec | 957 | struct drm_i915_private *i915; |
40521054 | 958 | struct drm_i915_file_private *file_priv; |
ae6c4806 | 959 | struct i915_hw_ppgtt *ppgtt; |
c84455b4 | 960 | struct pid *pid; |
562f5d45 | 961 | const char *name; |
a33afea5 | 962 | |
8d59bc6a | 963 | unsigned long flags; |
bc3d6744 CW |
964 | #define CONTEXT_NO_ZEROMAP BIT(0) |
965 | #define CONTEXT_NO_ERROR_CAPTURE BIT(1) | |
0be81156 DG |
966 | |
967 | /* Unique identifier for this context, used by the hw for tracking */ | |
968 | unsigned int hw_id; | |
8d59bc6a | 969 | u32 user_handle; |
9f792eba | 970 | int priority; /* greater priorities are serviced first */ |
5d1808ec | 971 | |
0cb26a8e CW |
972 | u32 ggtt_alignment; |
973 | ||
9021ad03 | 974 | struct intel_context { |
bf3783e5 | 975 | struct i915_vma *state; |
7e37f889 | 976 | struct intel_ring *ring; |
82352e90 | 977 | uint32_t *lrc_reg_state; |
8d59bc6a CW |
978 | u64 lrc_desc; |
979 | int pin_count; | |
24f1d3cc | 980 | bool initialised; |
666796da | 981 | } engine[I915_NUM_ENGINES]; |
bcd794c2 | 982 | u32 ring_size; |
c01fc532 | 983 | u32 desc_template; |
3c7ba635 | 984 | struct atomic_notifier_head status_notifier; |
80a9a8db | 985 | bool execlists_force_single_submission; |
c9e003af | 986 | |
a33afea5 | 987 | struct list_head link; |
8d59bc6a CW |
988 | |
989 | u8 remap_slice; | |
50e046b6 | 990 | bool closed:1; |
bc1d53c6 MK |
991 | bool bannable:1; |
992 | bool banned:1; | |
993 | ||
994 | unsigned int guilty_count; /* guilty of a hang */ | |
995 | unsigned int active_count; /* active during hang */ | |
996 | ||
997 | #define CONTEXT_SCORE_GUILTY 10 | |
998 | #define CONTEXT_SCORE_BAN_THRESHOLD 40 | |
999 | /* Accumulated score of hangs caused by this context */ | |
1000 | int ban_score; | |
40521054 BW |
1001 | }; |
1002 | ||
a4001f1b PZ |
1003 | enum fb_op_origin { |
1004 | ORIGIN_GTT, | |
1005 | ORIGIN_CPU, | |
1006 | ORIGIN_CS, | |
1007 | ORIGIN_FLIP, | |
74b4ea1e | 1008 | ORIGIN_DIRTYFB, |
a4001f1b PZ |
1009 | }; |
1010 | ||
ab34a7e8 | 1011 | struct intel_fbc { |
25ad93fd PZ |
1012 | /* This is always the inner lock when overlapping with struct_mutex and |
1013 | * it's the outer lock when overlapping with stolen_lock. */ | |
1014 | struct mutex lock; | |
5e59f717 | 1015 | unsigned threshold; |
dbef0f15 PZ |
1016 | unsigned int possible_framebuffer_bits; |
1017 | unsigned int busy_bits; | |
010cf73d | 1018 | unsigned int visible_pipes_mask; |
e35fef21 | 1019 | struct intel_crtc *crtc; |
5c3fe8b0 | 1020 | |
c4213885 | 1021 | struct drm_mm_node compressed_fb; |
5c3fe8b0 BW |
1022 | struct drm_mm_node *compressed_llb; |
1023 | ||
da46f936 RV |
1024 | bool false_color; |
1025 | ||
d029bcad | 1026 | bool enabled; |
0e631adc | 1027 | bool active; |
9adccc60 | 1028 | |
61a585d6 PZ |
1029 | bool underrun_detected; |
1030 | struct work_struct underrun_work; | |
1031 | ||
aaf78d27 PZ |
1032 | struct intel_fbc_state_cache { |
1033 | struct { | |
1034 | unsigned int mode_flags; | |
1035 | uint32_t hsw_bdw_pixel_rate; | |
1036 | } crtc; | |
1037 | ||
1038 | struct { | |
1039 | unsigned int rotation; | |
1040 | int src_w; | |
1041 | int src_h; | |
1042 | bool visible; | |
1043 | } plane; | |
1044 | ||
1045 | struct { | |
1046 | u64 ilk_ggtt_offset; | |
aaf78d27 PZ |
1047 | uint32_t pixel_format; |
1048 | unsigned int stride; | |
1049 | int fence_reg; | |
1050 | unsigned int tiling_mode; | |
1051 | } fb; | |
1052 | } state_cache; | |
1053 | ||
b183b3f1 PZ |
1054 | struct intel_fbc_reg_params { |
1055 | struct { | |
1056 | enum pipe pipe; | |
1057 | enum plane plane; | |
1058 | unsigned int fence_y_offset; | |
1059 | } crtc; | |
1060 | ||
1061 | struct { | |
1062 | u64 ggtt_offset; | |
b183b3f1 PZ |
1063 | uint32_t pixel_format; |
1064 | unsigned int stride; | |
1065 | int fence_reg; | |
1066 | } fb; | |
1067 | ||
1068 | int cfb_size; | |
1069 | } params; | |
1070 | ||
5c3fe8b0 | 1071 | struct intel_fbc_work { |
128d7356 | 1072 | bool scheduled; |
ca18d51d | 1073 | u32 scheduled_vblank; |
128d7356 | 1074 | struct work_struct work; |
128d7356 | 1075 | } work; |
5c3fe8b0 | 1076 | |
bf6189c6 | 1077 | const char *no_fbc_reason; |
b5e50c3f JB |
1078 | }; |
1079 | ||
96178eeb VK |
1080 | /** |
1081 | * HIGH_RR is the highest eDP panel refresh rate read from EDID | |
1082 | * LOW_RR is the lowest eDP panel refresh rate found from EDID | |
1083 | * parsing for same resolution. | |
1084 | */ | |
1085 | enum drrs_refresh_rate_type { | |
1086 | DRRS_HIGH_RR, | |
1087 | DRRS_LOW_RR, | |
1088 | DRRS_MAX_RR, /* RR count */ | |
1089 | }; | |
1090 | ||
1091 | enum drrs_support_type { | |
1092 | DRRS_NOT_SUPPORTED = 0, | |
1093 | STATIC_DRRS_SUPPORT = 1, | |
1094 | SEAMLESS_DRRS_SUPPORT = 2 | |
439d7ac0 PB |
1095 | }; |
1096 | ||
2807cf69 | 1097 | struct intel_dp; |
96178eeb VK |
1098 | struct i915_drrs { |
1099 | struct mutex mutex; | |
1100 | struct delayed_work work; | |
1101 | struct intel_dp *dp; | |
1102 | unsigned busy_frontbuffer_bits; | |
1103 | enum drrs_refresh_rate_type refresh_rate_type; | |
1104 | enum drrs_support_type type; | |
1105 | }; | |
1106 | ||
a031d709 | 1107 | struct i915_psr { |
f0355c4a | 1108 | struct mutex lock; |
a031d709 RV |
1109 | bool sink_support; |
1110 | bool source_ok; | |
2807cf69 | 1111 | struct intel_dp *enabled; |
7c8f8a70 RV |
1112 | bool active; |
1113 | struct delayed_work work; | |
9ca15301 | 1114 | unsigned busy_frontbuffer_bits; |
474d1ec4 SJ |
1115 | bool psr2_support; |
1116 | bool aux_frame_sync; | |
60e5ffe3 | 1117 | bool link_standby; |
3f51e471 | 1118 | }; |
5c3fe8b0 | 1119 | |
3bad0781 | 1120 | enum intel_pch { |
f0350830 | 1121 | PCH_NONE = 0, /* No PCH present */ |
3bad0781 ZW |
1122 | PCH_IBX, /* Ibexpeak PCH */ |
1123 | PCH_CPT, /* Cougarpoint PCH */ | |
eb877ebf | 1124 | PCH_LPT, /* Lynxpoint PCH */ |
e7e7ea20 | 1125 | PCH_SPT, /* Sunrisepoint PCH */ |
22dea0be | 1126 | PCH_KBP, /* Kabypoint PCH */ |
40c7ead9 | 1127 | PCH_NOP, |
3bad0781 ZW |
1128 | }; |
1129 | ||
988d6ee8 PZ |
1130 | enum intel_sbi_destination { |
1131 | SBI_ICLK, | |
1132 | SBI_MPHY, | |
1133 | }; | |
1134 | ||
b690e96c | 1135 | #define QUIRK_PIPEA_FORCE (1<<0) |
435793df | 1136 | #define QUIRK_LVDS_SSC_DISABLE (1<<1) |
4dca20ef | 1137 | #define QUIRK_INVERT_BRIGHTNESS (1<<2) |
9c72cc6f | 1138 | #define QUIRK_BACKLIGHT_PRESENT (1<<3) |
b6b5d049 | 1139 | #define QUIRK_PIPEB_FORCE (1<<4) |
656bfa3a | 1140 | #define QUIRK_PIN_SWIZZLED_PAGES (1<<5) |
b690e96c | 1141 | |
8be48d92 | 1142 | struct intel_fbdev; |
1630fe75 | 1143 | struct intel_fbc_work; |
38651674 | 1144 | |
c2b9152f DV |
1145 | struct intel_gmbus { |
1146 | struct i2c_adapter adapter; | |
3e4d44e0 | 1147 | #define GMBUS_FORCE_BIT_RETRY (1U << 31) |
f2ce9faf | 1148 | u32 force_bit; |
c2b9152f | 1149 | u32 reg0; |
f0f59a00 | 1150 | i915_reg_t gpio_reg; |
c167a6fc | 1151 | struct i2c_algo_bit_data bit_algo; |
c2b9152f DV |
1152 | struct drm_i915_private *dev_priv; |
1153 | }; | |
1154 | ||
f4c956ad | 1155 | struct i915_suspend_saved_registers { |
e948e994 | 1156 | u32 saveDSPARB; |
ba8bbcf6 | 1157 | u32 saveFBC_CONTROL; |
1f84e550 | 1158 | u32 saveCACHE_MODE_0; |
1f84e550 | 1159 | u32 saveMI_ARB_STATE; |
ba8bbcf6 JB |
1160 | u32 saveSWF0[16]; |
1161 | u32 saveSWF1[16]; | |
85fa792b | 1162 | u32 saveSWF3[3]; |
4b9de737 | 1163 | uint64_t saveFENCE[I915_MAX_NUM_FENCES]; |
cda2bb78 | 1164 | u32 savePCH_PORT_HOTPLUG; |
9f49c376 | 1165 | u16 saveGCDGMBUS; |
f4c956ad | 1166 | }; |
c85aa885 | 1167 | |
ddeea5b0 ID |
1168 | struct vlv_s0ix_state { |
1169 | /* GAM */ | |
1170 | u32 wr_watermark; | |
1171 | u32 gfx_prio_ctrl; | |
1172 | u32 arb_mode; | |
1173 | u32 gfx_pend_tlb0; | |
1174 | u32 gfx_pend_tlb1; | |
1175 | u32 lra_limits[GEN7_LRA_LIMITS_REG_NUM]; | |
1176 | u32 media_max_req_count; | |
1177 | u32 gfx_max_req_count; | |
1178 | u32 render_hwsp; | |
1179 | u32 ecochk; | |
1180 | u32 bsd_hwsp; | |
1181 | u32 blt_hwsp; | |
1182 | u32 tlb_rd_addr; | |
1183 | ||
1184 | /* MBC */ | |
1185 | u32 g3dctl; | |
1186 | u32 gsckgctl; | |
1187 | u32 mbctl; | |
1188 | ||
1189 | /* GCP */ | |
1190 | u32 ucgctl1; | |
1191 | u32 ucgctl3; | |
1192 | u32 rcgctl1; | |
1193 | u32 rcgctl2; | |
1194 | u32 rstctl; | |
1195 | u32 misccpctl; | |
1196 | ||
1197 | /* GPM */ | |
1198 | u32 gfxpause; | |
1199 | u32 rpdeuhwtc; | |
1200 | u32 rpdeuc; | |
1201 | u32 ecobus; | |
1202 | u32 pwrdwnupctl; | |
1203 | u32 rp_down_timeout; | |
1204 | u32 rp_deucsw; | |
1205 | u32 rcubmabdtmr; | |
1206 | u32 rcedata; | |
1207 | u32 spare2gh; | |
1208 | ||
1209 | /* Display 1 CZ domain */ | |
1210 | u32 gt_imr; | |
1211 | u32 gt_ier; | |
1212 | u32 pm_imr; | |
1213 | u32 pm_ier; | |
1214 | u32 gt_scratch[GEN7_GT_SCRATCH_REG_NUM]; | |
1215 | ||
1216 | /* GT SA CZ domain */ | |
1217 | u32 tilectl; | |
1218 | u32 gt_fifoctl; | |
1219 | u32 gtlc_wake_ctrl; | |
1220 | u32 gtlc_survive; | |
1221 | u32 pmwgicz; | |
1222 | ||
1223 | /* Display 2 CZ domain */ | |
1224 | u32 gu_ctl0; | |
1225 | u32 gu_ctl1; | |
9c25210f | 1226 | u32 pcbr; |
ddeea5b0 ID |
1227 | u32 clock_gate_dis2; |
1228 | }; | |
1229 | ||
bf225f20 CW |
1230 | struct intel_rps_ei { |
1231 | u32 cz_clock; | |
1232 | u32 render_c0; | |
1233 | u32 media_c0; | |
31685c25 D |
1234 | }; |
1235 | ||
c85aa885 | 1236 | struct intel_gen6_power_mgmt { |
d4d70aa5 ID |
1237 | /* |
1238 | * work, interrupts_enabled and pm_iir are protected by | |
1239 | * dev_priv->irq_lock | |
1240 | */ | |
c85aa885 | 1241 | struct work_struct work; |
d4d70aa5 | 1242 | bool interrupts_enabled; |
c85aa885 | 1243 | u32 pm_iir; |
59cdb63d | 1244 | |
b20e3cfe | 1245 | /* PM interrupt bits that should never be masked */ |
1800ad25 SAK |
1246 | u32 pm_intr_keep; |
1247 | ||
b39fb297 BW |
1248 | /* Frequencies are stored in potentially platform dependent multiples. |
1249 | * In other words, *_freq needs to be multiplied by X to be interesting. | |
1250 | * Soft limits are those which are used for the dynamic reclocking done | |
1251 | * by the driver (raise frequencies under heavy loads, and lower for | |
1252 | * lighter loads). Hard limits are those imposed by the hardware. | |
1253 | * | |
1254 | * A distinction is made for overclocking, which is never enabled by | |
1255 | * default, and is considered to be above the hard limit if it's | |
1256 | * possible at all. | |
1257 | */ | |
1258 | u8 cur_freq; /* Current frequency (cached, may not == HW) */ | |
1259 | u8 min_freq_softlimit; /* Minimum frequency permitted by the driver */ | |
1260 | u8 max_freq_softlimit; /* Max frequency permitted by the driver */ | |
1261 | u8 max_freq; /* Maximum frequency, RP0 if not overclocking */ | |
1262 | u8 min_freq; /* AKA RPn. Minimum frequency */ | |
29ecd78d | 1263 | u8 boost_freq; /* Frequency to request when wait boosting */ |
aed242ff | 1264 | u8 idle_freq; /* Frequency to request when we are idle */ |
b39fb297 BW |
1265 | u8 efficient_freq; /* AKA RPe. Pre-determined balanced frequency */ |
1266 | u8 rp1_freq; /* "less than" RP0 power/freqency */ | |
1267 | u8 rp0_freq; /* Non-overclocked max frequency. */ | |
c30fec65 | 1268 | u16 gpll_ref_freq; /* vlv/chv GPLL reference frequency */ |
1a01ab3b | 1269 | |
8fb55197 CW |
1270 | u8 up_threshold; /* Current %busy required to uplock */ |
1271 | u8 down_threshold; /* Current %busy required to downclock */ | |
1272 | ||
dd75fdc8 CW |
1273 | int last_adj; |
1274 | enum { LOW_POWER, BETWEEN, HIGH_POWER } power; | |
1275 | ||
8d3afd7d CW |
1276 | spinlock_t client_lock; |
1277 | struct list_head clients; | |
1278 | bool client_boost; | |
1279 | ||
c0951f0c | 1280 | bool enabled; |
54b4f68f | 1281 | struct delayed_work autoenable_work; |
1854d5ca | 1282 | unsigned boosts; |
4fc688ce | 1283 | |
bf225f20 CW |
1284 | /* manual wa residency calculations */ |
1285 | struct intel_rps_ei up_ei, down_ei; | |
1286 | ||
4fc688ce JB |
1287 | /* |
1288 | * Protects RPS/RC6 register access and PCU communication. | |
8d3afd7d CW |
1289 | * Must be taken after struct_mutex if nested. Note that |
1290 | * this lock may be held for long periods of time when | |
1291 | * talking to hw - so only take it when talking to hw! | |
4fc688ce JB |
1292 | */ |
1293 | struct mutex hw_lock; | |
c85aa885 DV |
1294 | }; |
1295 | ||
1a240d4d DV |
1296 | /* defined intel_pm.c */ |
1297 | extern spinlock_t mchdev_lock; | |
1298 | ||
c85aa885 DV |
1299 | struct intel_ilk_power_mgmt { |
1300 | u8 cur_delay; | |
1301 | u8 min_delay; | |
1302 | u8 max_delay; | |
1303 | u8 fmax; | |
1304 | u8 fstart; | |
1305 | ||
1306 | u64 last_count1; | |
1307 | unsigned long last_time1; | |
1308 | unsigned long chipset_power; | |
1309 | u64 last_count2; | |
5ed0bdf2 | 1310 | u64 last_time2; |
c85aa885 DV |
1311 | unsigned long gfx_power; |
1312 | u8 corr; | |
1313 | ||
1314 | int c_m; | |
1315 | int r_t; | |
1316 | }; | |
1317 | ||
c6cb582e ID |
1318 | struct drm_i915_private; |
1319 | struct i915_power_well; | |
1320 | ||
1321 | struct i915_power_well_ops { | |
1322 | /* | |
1323 | * Synchronize the well's hw state to match the current sw state, for | |
1324 | * example enable/disable it based on the current refcount. Called | |
1325 | * during driver init and resume time, possibly after first calling | |
1326 | * the enable/disable handlers. | |
1327 | */ | |
1328 | void (*sync_hw)(struct drm_i915_private *dev_priv, | |
1329 | struct i915_power_well *power_well); | |
1330 | /* | |
1331 | * Enable the well and resources that depend on it (for example | |
1332 | * interrupts located on the well). Called after the 0->1 refcount | |
1333 | * transition. | |
1334 | */ | |
1335 | void (*enable)(struct drm_i915_private *dev_priv, | |
1336 | struct i915_power_well *power_well); | |
1337 | /* | |
1338 | * Disable the well and resources that depend on it. Called after | |
1339 | * the 1->0 refcount transition. | |
1340 | */ | |
1341 | void (*disable)(struct drm_i915_private *dev_priv, | |
1342 | struct i915_power_well *power_well); | |
1343 | /* Returns the hw enabled state. */ | |
1344 | bool (*is_enabled)(struct drm_i915_private *dev_priv, | |
1345 | struct i915_power_well *power_well); | |
1346 | }; | |
1347 | ||
a38911a3 WX |
1348 | /* Power well structure for haswell */ |
1349 | struct i915_power_well { | |
c1ca727f | 1350 | const char *name; |
6f3ef5dd | 1351 | bool always_on; |
a38911a3 WX |
1352 | /* power well enable/disable usage count */ |
1353 | int count; | |
bfafe93a ID |
1354 | /* cached hw enabled state */ |
1355 | bool hw_enabled; | |
c1ca727f | 1356 | unsigned long domains; |
01c3faa7 ACO |
1357 | /* unique identifier for this power well */ |
1358 | unsigned long id; | |
362624c9 ACO |
1359 | /* |
1360 | * Arbitraty data associated with this power well. Platform and power | |
1361 | * well specific. | |
1362 | */ | |
1363 | unsigned long data; | |
c6cb582e | 1364 | const struct i915_power_well_ops *ops; |
a38911a3 WX |
1365 | }; |
1366 | ||
83c00f55 | 1367 | struct i915_power_domains { |
baa70707 ID |
1368 | /* |
1369 | * Power wells needed for initialization at driver init and suspend | |
1370 | * time are on. They are kept on until after the first modeset. | |
1371 | */ | |
1372 | bool init_power_on; | |
0d116a29 | 1373 | bool initializing; |
c1ca727f | 1374 | int power_well_count; |
baa70707 | 1375 | |
83c00f55 | 1376 | struct mutex lock; |
1da51581 | 1377 | int domain_use_count[POWER_DOMAIN_NUM]; |
c1ca727f | 1378 | struct i915_power_well *power_wells; |
83c00f55 ID |
1379 | }; |
1380 | ||
35a85ac6 | 1381 | #define MAX_L3_SLICES 2 |
a4da4fa4 | 1382 | struct intel_l3_parity { |
35a85ac6 | 1383 | u32 *remap_info[MAX_L3_SLICES]; |
a4da4fa4 | 1384 | struct work_struct error_work; |
35a85ac6 | 1385 | int which_slice; |
a4da4fa4 DV |
1386 | }; |
1387 | ||
4b5aed62 | 1388 | struct i915_gem_mm { |
4b5aed62 DV |
1389 | /** Memory allocator for GTT stolen memory */ |
1390 | struct drm_mm stolen; | |
92e97d2f PZ |
1391 | /** Protects the usage of the GTT stolen memory allocator. This is |
1392 | * always the inner lock when overlapping with struct_mutex. */ | |
1393 | struct mutex stolen_lock; | |
1394 | ||
4b5aed62 DV |
1395 | /** List of all objects in gtt_space. Used to restore gtt |
1396 | * mappings on resume */ | |
1397 | struct list_head bound_list; | |
1398 | /** | |
1399 | * List of objects which are not bound to the GTT (thus | |
fbbd37b3 CW |
1400 | * are idle and not used by the GPU). These objects may or may |
1401 | * not actually have any pages attached. | |
4b5aed62 DV |
1402 | */ |
1403 | struct list_head unbound_list; | |
1404 | ||
275f039d CW |
1405 | /** List of all objects in gtt_space, currently mmaped by userspace. |
1406 | * All objects within this list must also be on bound_list. | |
1407 | */ | |
1408 | struct list_head userfault_list; | |
1409 | ||
fbbd37b3 CW |
1410 | /** |
1411 | * List of objects which are pending destruction. | |
1412 | */ | |
1413 | struct llist_head free_list; | |
1414 | struct work_struct free_work; | |
1415 | ||
4b5aed62 DV |
1416 | /** Usable portion of the GTT for GEM */ |
1417 | unsigned long stolen_base; /* limited to low memory (32-bit) */ | |
1418 | ||
4b5aed62 DV |
1419 | /** PPGTT used for aliasing the PPGTT with the GTT */ |
1420 | struct i915_hw_ppgtt *aliasing_ppgtt; | |
1421 | ||
2cfcd32a | 1422 | struct notifier_block oom_notifier; |
e87666b5 | 1423 | struct notifier_block vmap_notifier; |
ceabbba5 | 1424 | struct shrinker shrinker; |
4b5aed62 | 1425 | |
4b5aed62 DV |
1426 | /** LRU list of objects with fence regs on them. */ |
1427 | struct list_head fence_list; | |
1428 | ||
4b5aed62 DV |
1429 | /** |
1430 | * Are we in a non-interruptible section of code like | |
1431 | * modesetting? | |
1432 | */ | |
1433 | bool interruptible; | |
1434 | ||
bdf1e7e3 | 1435 | /* the indicator for dispatch video commands on two BSD rings */ |
6f633402 | 1436 | atomic_t bsd_engine_dispatch_index; |
bdf1e7e3 | 1437 | |
4b5aed62 DV |
1438 | /** Bit 6 swizzling required for X tiling */ |
1439 | uint32_t bit_6_swizzle_x; | |
1440 | /** Bit 6 swizzling required for Y tiling */ | |
1441 | uint32_t bit_6_swizzle_y; | |
1442 | ||
4b5aed62 | 1443 | /* accounting, useful for userland debugging */ |
c20e8355 | 1444 | spinlock_t object_stat_lock; |
3ef7f228 | 1445 | u64 object_memory; |
4b5aed62 DV |
1446 | u32 object_count; |
1447 | }; | |
1448 | ||
edc3d884 | 1449 | struct drm_i915_error_state_buf { |
0a4cd7c8 | 1450 | struct drm_i915_private *i915; |
edc3d884 MK |
1451 | unsigned bytes; |
1452 | unsigned size; | |
1453 | int err; | |
1454 | u8 *buf; | |
1455 | loff_t start; | |
1456 | loff_t pos; | |
1457 | }; | |
1458 | ||
fc16b48b MK |
1459 | struct i915_error_state_file_priv { |
1460 | struct drm_device *dev; | |
1461 | struct drm_i915_error_state *error; | |
1462 | }; | |
1463 | ||
b52992c0 CW |
1464 | #define I915_RESET_TIMEOUT (10 * HZ) /* 10s */ |
1465 | #define I915_FENCE_TIMEOUT (10 * HZ) /* 10s */ | |
1466 | ||
3fe3b030 MK |
1467 | #define I915_ENGINE_DEAD_TIMEOUT (4 * HZ) /* Seqno, head and subunits dead */ |
1468 | #define I915_SEQNO_DEAD_TIMEOUT (12 * HZ) /* Seqno dead with active head */ | |
1469 | ||
99584db3 DV |
1470 | struct i915_gpu_error { |
1471 | /* For hangcheck timer */ | |
1472 | #define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */ | |
1473 | #define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD) | |
be62acb4 | 1474 | |
737b1506 | 1475 | struct delayed_work hangcheck_work; |
99584db3 DV |
1476 | |
1477 | /* For reset and error_state handling. */ | |
1478 | spinlock_t lock; | |
1479 | /* Protected by the above dev->gpu_error.lock. */ | |
1480 | struct drm_i915_error_state *first_error; | |
094f9a54 CW |
1481 | |
1482 | unsigned long missed_irq_rings; | |
1483 | ||
1f83fee0 | 1484 | /** |
2ac0f450 | 1485 | * State variable controlling the reset flow and count |
1f83fee0 | 1486 | * |
2ac0f450 | 1487 | * This is a counter which gets incremented when reset is triggered, |
8af29b0c CW |
1488 | * |
1489 | * Before the reset commences, the I915_RESET_IN_PROGRESS bit is set | |
1490 | * meaning that any waiters holding onto the struct_mutex should | |
1491 | * relinquish the lock immediately in order for the reset to start. | |
2ac0f450 MK |
1492 | * |
1493 | * If reset is not completed succesfully, the I915_WEDGE bit is | |
1494 | * set meaning that hardware is terminally sour and there is no | |
1495 | * recovery. All waiters on the reset_queue will be woken when | |
1496 | * that happens. | |
1497 | * | |
1498 | * This counter is used by the wait_seqno code to notice that reset | |
1499 | * event happened and it needs to restart the entire ioctl (since most | |
1500 | * likely the seqno it waited for won't ever signal anytime soon). | |
f69061be DV |
1501 | * |
1502 | * This is important for lock-free wait paths, where no contended lock | |
1503 | * naturally enforces the correct ordering between the bail-out of the | |
1504 | * waiter and the gpu reset work code. | |
1f83fee0 | 1505 | */ |
8af29b0c | 1506 | unsigned long reset_count; |
1f83fee0 | 1507 | |
8af29b0c CW |
1508 | unsigned long flags; |
1509 | #define I915_RESET_IN_PROGRESS 0 | |
1510 | #define I915_WEDGED (BITS_PER_LONG - 1) | |
1f83fee0 | 1511 | |
1f15b76f CW |
1512 | /** |
1513 | * Waitqueue to signal when a hang is detected. Used to for waiters | |
1514 | * to release the struct_mutex for the reset to procede. | |
1515 | */ | |
1516 | wait_queue_head_t wait_queue; | |
1517 | ||
1f83fee0 DV |
1518 | /** |
1519 | * Waitqueue to signal when the reset has completed. Used by clients | |
1520 | * that wait for dev_priv->mm.wedged to settle. | |
1521 | */ | |
1522 | wait_queue_head_t reset_queue; | |
33196ded | 1523 | |
094f9a54 | 1524 | /* For missed irq/seqno simulation. */ |
688e6c72 | 1525 | unsigned long test_irq_rings; |
99584db3 DV |
1526 | }; |
1527 | ||
b8efb17b ZR |
1528 | enum modeset_restore { |
1529 | MODESET_ON_LID_OPEN, | |
1530 | MODESET_DONE, | |
1531 | MODESET_SUSPENDED, | |
1532 | }; | |
1533 | ||
500ea70d RV |
1534 | #define DP_AUX_A 0x40 |
1535 | #define DP_AUX_B 0x10 | |
1536 | #define DP_AUX_C 0x20 | |
1537 | #define DP_AUX_D 0x30 | |
1538 | ||
11c1b657 XZ |
1539 | #define DDC_PIN_B 0x05 |
1540 | #define DDC_PIN_C 0x04 | |
1541 | #define DDC_PIN_D 0x06 | |
1542 | ||
6acab15a | 1543 | struct ddi_vbt_port_info { |
ce4dd49e DL |
1544 | /* |
1545 | * This is an index in the HDMI/DVI DDI buffer translation table. | |
1546 | * The special value HDMI_LEVEL_SHIFT_UNKNOWN means the VBT didn't | |
1547 | * populate this field. | |
1548 | */ | |
1549 | #define HDMI_LEVEL_SHIFT_UNKNOWN 0xff | |
6acab15a | 1550 | uint8_t hdmi_level_shift; |
311a2094 PZ |
1551 | |
1552 | uint8_t supports_dvi:1; | |
1553 | uint8_t supports_hdmi:1; | |
1554 | uint8_t supports_dp:1; | |
500ea70d RV |
1555 | |
1556 | uint8_t alternate_aux_channel; | |
11c1b657 | 1557 | uint8_t alternate_ddc_pin; |
75067dde AK |
1558 | |
1559 | uint8_t dp_boost_level; | |
1560 | uint8_t hdmi_boost_level; | |
6acab15a PZ |
1561 | }; |
1562 | ||
bfd7ebda RV |
1563 | enum psr_lines_to_wait { |
1564 | PSR_0_LINES_TO_WAIT = 0, | |
1565 | PSR_1_LINE_TO_WAIT, | |
1566 | PSR_4_LINES_TO_WAIT, | |
1567 | PSR_8_LINES_TO_WAIT | |
83a7280e PB |
1568 | }; |
1569 | ||
41aa3448 RV |
1570 | struct intel_vbt_data { |
1571 | struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */ | |
1572 | struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */ | |
1573 | ||
1574 | /* Feature bits */ | |
1575 | unsigned int int_tv_support:1; | |
1576 | unsigned int lvds_dither:1; | |
1577 | unsigned int lvds_vbt:1; | |
1578 | unsigned int int_crt_support:1; | |
1579 | unsigned int lvds_use_ssc:1; | |
1580 | unsigned int display_clock_mode:1; | |
1581 | unsigned int fdi_rx_polarity_inverted:1; | |
3e845c7a | 1582 | unsigned int panel_type:4; |
41aa3448 RV |
1583 | int lvds_ssc_freq; |
1584 | unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */ | |
1585 | ||
83a7280e PB |
1586 | enum drrs_support_type drrs_type; |
1587 | ||
6aa23e65 JN |
1588 | struct { |
1589 | int rate; | |
1590 | int lanes; | |
1591 | int preemphasis; | |
1592 | int vswing; | |
06411f08 | 1593 | bool low_vswing; |
6aa23e65 JN |
1594 | bool initialized; |
1595 | bool support; | |
1596 | int bpp; | |
1597 | struct edp_power_seq pps; | |
1598 | } edp; | |
41aa3448 | 1599 | |
bfd7ebda RV |
1600 | struct { |
1601 | bool full_link; | |
1602 | bool require_aux_wakeup; | |
1603 | int idle_frames; | |
1604 | enum psr_lines_to_wait lines_to_wait; | |
1605 | int tp1_wakeup_time; | |
1606 | int tp2_tp3_wakeup_time; | |
1607 | } psr; | |
1608 | ||
f00076d2 JN |
1609 | struct { |
1610 | u16 pwm_freq_hz; | |
39fbc9c8 | 1611 | bool present; |
f00076d2 | 1612 | bool active_low_pwm; |
1de6068e | 1613 | u8 min_brightness; /* min_brightness/255 of max */ |
9a41e17d | 1614 | enum intel_backlight_type type; |
f00076d2 JN |
1615 | } backlight; |
1616 | ||
d17c5443 SK |
1617 | /* MIPI DSI */ |
1618 | struct { | |
1619 | u16 panel_id; | |
d3b542fc SK |
1620 | struct mipi_config *config; |
1621 | struct mipi_pps_data *pps; | |
1622 | u8 seq_version; | |
1623 | u32 size; | |
1624 | u8 *data; | |
8d3ed2f3 | 1625 | const u8 *sequence[MIPI_SEQ_MAX]; |
d17c5443 SK |
1626 | } dsi; |
1627 | ||
41aa3448 RV |
1628 | int crt_ddc_pin; |
1629 | ||
1630 | int child_dev_num; | |
768f69c9 | 1631 | union child_device_config *child_dev; |
6acab15a PZ |
1632 | |
1633 | struct ddi_vbt_port_info ddi_port_info[I915_MAX_PORTS]; | |
9d6c875d | 1634 | struct sdvo_device_mapping sdvo_mappings[2]; |
41aa3448 RV |
1635 | }; |
1636 | ||
77c122bc VS |
1637 | enum intel_ddb_partitioning { |
1638 | INTEL_DDB_PART_1_2, | |
1639 | INTEL_DDB_PART_5_6, /* IVB+ */ | |
1640 | }; | |
1641 | ||
1fd527cc VS |
1642 | struct intel_wm_level { |
1643 | bool enable; | |
1644 | uint32_t pri_val; | |
1645 | uint32_t spr_val; | |
1646 | uint32_t cur_val; | |
1647 | uint32_t fbc_val; | |
1648 | }; | |
1649 | ||
820c1980 | 1650 | struct ilk_wm_values { |
609cedef VS |
1651 | uint32_t wm_pipe[3]; |
1652 | uint32_t wm_lp[3]; | |
1653 | uint32_t wm_lp_spr[3]; | |
1654 | uint32_t wm_linetime[3]; | |
1655 | bool enable_fbc_wm; | |
1656 | enum intel_ddb_partitioning partitioning; | |
1657 | }; | |
1658 | ||
262cd2e1 VS |
1659 | struct vlv_pipe_wm { |
1660 | uint16_t primary; | |
1661 | uint16_t sprite[2]; | |
1662 | uint8_t cursor; | |
1663 | }; | |
ae80152d | 1664 | |
262cd2e1 VS |
1665 | struct vlv_sr_wm { |
1666 | uint16_t plane; | |
1667 | uint8_t cursor; | |
1668 | }; | |
ae80152d | 1669 | |
262cd2e1 VS |
1670 | struct vlv_wm_values { |
1671 | struct vlv_pipe_wm pipe[3]; | |
1672 | struct vlv_sr_wm sr; | |
0018fda1 VS |
1673 | struct { |
1674 | uint8_t cursor; | |
1675 | uint8_t sprite[2]; | |
1676 | uint8_t primary; | |
1677 | } ddl[3]; | |
6eb1a681 VS |
1678 | uint8_t level; |
1679 | bool cxsr; | |
0018fda1 VS |
1680 | }; |
1681 | ||
c193924e | 1682 | struct skl_ddb_entry { |
16160e3d | 1683 | uint16_t start, end; /* in number of blocks, 'end' is exclusive */ |
c193924e DL |
1684 | }; |
1685 | ||
1686 | static inline uint16_t skl_ddb_entry_size(const struct skl_ddb_entry *entry) | |
1687 | { | |
16160e3d | 1688 | return entry->end - entry->start; |
c193924e DL |
1689 | } |
1690 | ||
08db6652 DL |
1691 | static inline bool skl_ddb_entry_equal(const struct skl_ddb_entry *e1, |
1692 | const struct skl_ddb_entry *e2) | |
1693 | { | |
1694 | if (e1->start == e2->start && e1->end == e2->end) | |
1695 | return true; | |
1696 | ||
1697 | return false; | |
1698 | } | |
1699 | ||
c193924e | 1700 | struct skl_ddb_allocation { |
2cd601c6 | 1701 | struct skl_ddb_entry plane[I915_MAX_PIPES][I915_MAX_PLANES]; /* packed/uv */ |
4969d33e | 1702 | struct skl_ddb_entry y_plane[I915_MAX_PIPES][I915_MAX_PLANES]; |
c193924e DL |
1703 | }; |
1704 | ||
2ac96d2a | 1705 | struct skl_wm_values { |
2b4b9f35 | 1706 | unsigned dirty_pipes; |
c193924e | 1707 | struct skl_ddb_allocation ddb; |
2ac96d2a PB |
1708 | }; |
1709 | ||
1710 | struct skl_wm_level { | |
a62163e9 L |
1711 | bool plane_en; |
1712 | uint16_t plane_res_b; | |
1713 | uint8_t plane_res_l; | |
2ac96d2a PB |
1714 | }; |
1715 | ||
c67a470b | 1716 | /* |
765dab67 PZ |
1717 | * This struct helps tracking the state needed for runtime PM, which puts the |
1718 | * device in PCI D3 state. Notice that when this happens, nothing on the | |
1719 | * graphics device works, even register access, so we don't get interrupts nor | |
1720 | * anything else. | |
c67a470b | 1721 | * |
765dab67 PZ |
1722 | * Every piece of our code that needs to actually touch the hardware needs to |
1723 | * either call intel_runtime_pm_get or call intel_display_power_get with the | |
1724 | * appropriate power domain. | |
a8a8bd54 | 1725 | * |
765dab67 PZ |
1726 | * Our driver uses the autosuspend delay feature, which means we'll only really |
1727 | * suspend if we stay with zero refcount for a certain amount of time. The | |
f458ebbc | 1728 | * default value is currently very conservative (see intel_runtime_pm_enable), but |
765dab67 | 1729 | * it can be changed with the standard runtime PM files from sysfs. |
c67a470b PZ |
1730 | * |
1731 | * The irqs_disabled variable becomes true exactly after we disable the IRQs and | |
1732 | * goes back to false exactly before we reenable the IRQs. We use this variable | |
1733 | * to check if someone is trying to enable/disable IRQs while they're supposed | |
1734 | * to be disabled. This shouldn't happen and we'll print some error messages in | |
730488b2 | 1735 | * case it happens. |
c67a470b | 1736 | * |
765dab67 | 1737 | * For more, read the Documentation/power/runtime_pm.txt. |
c67a470b | 1738 | */ |
5d584b2e | 1739 | struct i915_runtime_pm { |
1f814dac | 1740 | atomic_t wakeref_count; |
5d584b2e | 1741 | bool suspended; |
2aeb7d3a | 1742 | bool irqs_enabled; |
c67a470b PZ |
1743 | }; |
1744 | ||
926321d5 DV |
1745 | enum intel_pipe_crc_source { |
1746 | INTEL_PIPE_CRC_SOURCE_NONE, | |
1747 | INTEL_PIPE_CRC_SOURCE_PLANE1, | |
1748 | INTEL_PIPE_CRC_SOURCE_PLANE2, | |
1749 | INTEL_PIPE_CRC_SOURCE_PF, | |
5b3a856b | 1750 | INTEL_PIPE_CRC_SOURCE_PIPE, |
3d099a05 DV |
1751 | /* TV/DP on pre-gen5/vlv can't use the pipe source. */ |
1752 | INTEL_PIPE_CRC_SOURCE_TV, | |
1753 | INTEL_PIPE_CRC_SOURCE_DP_B, | |
1754 | INTEL_PIPE_CRC_SOURCE_DP_C, | |
1755 | INTEL_PIPE_CRC_SOURCE_DP_D, | |
46a19188 | 1756 | INTEL_PIPE_CRC_SOURCE_AUTO, |
926321d5 DV |
1757 | INTEL_PIPE_CRC_SOURCE_MAX, |
1758 | }; | |
1759 | ||
8bf1e9f1 | 1760 | struct intel_pipe_crc_entry { |
ac2300d4 | 1761 | uint32_t frame; |
8bf1e9f1 SH |
1762 | uint32_t crc[5]; |
1763 | }; | |
1764 | ||
b2c88f5b | 1765 | #define INTEL_PIPE_CRC_ENTRIES_NR 128 |
8bf1e9f1 | 1766 | struct intel_pipe_crc { |
d538bbdf DL |
1767 | spinlock_t lock; |
1768 | bool opened; /* exclusive access to the result file */ | |
e5f75aca | 1769 | struct intel_pipe_crc_entry *entries; |
926321d5 | 1770 | enum intel_pipe_crc_source source; |
d538bbdf | 1771 | int head, tail; |
07144428 | 1772 | wait_queue_head_t wq; |
8bf1e9f1 SH |
1773 | }; |
1774 | ||
f99d7069 | 1775 | struct i915_frontbuffer_tracking { |
b5add959 | 1776 | spinlock_t lock; |
f99d7069 DV |
1777 | |
1778 | /* | |
1779 | * Tracking bits for delayed frontbuffer flushing du to gpu activity or | |
1780 | * scheduled flips. | |
1781 | */ | |
1782 | unsigned busy_bits; | |
1783 | unsigned flip_bits; | |
1784 | }; | |
1785 | ||
7225342a | 1786 | struct i915_wa_reg { |
f0f59a00 | 1787 | i915_reg_t addr; |
7225342a MK |
1788 | u32 value; |
1789 | /* bitmask representing WA bits */ | |
1790 | u32 mask; | |
1791 | }; | |
1792 | ||
33136b06 AS |
1793 | /* |
1794 | * RING_MAX_NONPRIV_SLOTS is per-engine but at this point we are only | |
1795 | * allowing it for RCS as we don't foresee any requirement of having | |
1796 | * a whitelist for other engines. When it is really required for | |
1797 | * other engines then the limit need to be increased. | |
1798 | */ | |
1799 | #define I915_MAX_WA_REGS (16 + RING_MAX_NONPRIV_SLOTS) | |
7225342a MK |
1800 | |
1801 | struct i915_workarounds { | |
1802 | struct i915_wa_reg reg[I915_MAX_WA_REGS]; | |
1803 | u32 count; | |
666796da | 1804 | u32 hw_whitelist_count[I915_NUM_ENGINES]; |
7225342a MK |
1805 | }; |
1806 | ||
cf9d2890 YZ |
1807 | struct i915_virtual_gpu { |
1808 | bool active; | |
1809 | }; | |
1810 | ||
aa363136 MR |
1811 | /* used in computing the new watermarks state */ |
1812 | struct intel_wm_config { | |
1813 | unsigned int num_pipes_active; | |
1814 | bool sprites_enabled; | |
1815 | bool sprites_scaled; | |
1816 | }; | |
1817 | ||
d7965152 RB |
1818 | struct i915_oa_format { |
1819 | u32 format; | |
1820 | int size; | |
1821 | }; | |
1822 | ||
8a3003dd RB |
1823 | struct i915_oa_reg { |
1824 | i915_reg_t addr; | |
1825 | u32 value; | |
1826 | }; | |
1827 | ||
eec688e1 RB |
1828 | struct i915_perf_stream; |
1829 | ||
1830 | struct i915_perf_stream_ops { | |
1831 | /* Enables the collection of HW samples, either in response to | |
1832 | * I915_PERF_IOCTL_ENABLE or implicitly called when stream is | |
1833 | * opened without I915_PERF_FLAG_DISABLED. | |
1834 | */ | |
1835 | void (*enable)(struct i915_perf_stream *stream); | |
1836 | ||
1837 | /* Disables the collection of HW samples, either in response to | |
1838 | * I915_PERF_IOCTL_DISABLE or implicitly called before | |
1839 | * destroying the stream. | |
1840 | */ | |
1841 | void (*disable)(struct i915_perf_stream *stream); | |
1842 | ||
eec688e1 RB |
1843 | /* Call poll_wait, passing a wait queue that will be woken |
1844 | * once there is something ready to read() for the stream | |
1845 | */ | |
1846 | void (*poll_wait)(struct i915_perf_stream *stream, | |
1847 | struct file *file, | |
1848 | poll_table *wait); | |
1849 | ||
1850 | /* For handling a blocking read, wait until there is something | |
1851 | * to ready to read() for the stream. E.g. wait on the same | |
d7965152 | 1852 | * wait queue that would be passed to poll_wait(). |
eec688e1 RB |
1853 | */ |
1854 | int (*wait_unlocked)(struct i915_perf_stream *stream); | |
1855 | ||
1856 | /* read - Copy buffered metrics as records to userspace | |
1857 | * @buf: the userspace, destination buffer | |
1858 | * @count: the number of bytes to copy, requested by userspace | |
1859 | * @offset: zero at the start of the read, updated as the read | |
1860 | * proceeds, it represents how many bytes have been | |
1861 | * copied so far and the buffer offset for copying the | |
1862 | * next record. | |
1863 | * | |
1864 | * Copy as many buffered i915 perf samples and records for | |
1865 | * this stream to userspace as will fit in the given buffer. | |
1866 | * | |
1867 | * Only write complete records; returning -ENOSPC if there | |
1868 | * isn't room for a complete record. | |
1869 | * | |
1870 | * Return any error condition that results in a short read | |
1871 | * such as -ENOSPC or -EFAULT, even though these may be | |
1872 | * squashed before returning to userspace. | |
1873 | */ | |
1874 | int (*read)(struct i915_perf_stream *stream, | |
1875 | char __user *buf, | |
1876 | size_t count, | |
1877 | size_t *offset); | |
1878 | ||
1879 | /* Cleanup any stream specific resources. | |
1880 | * | |
1881 | * The stream will always be disabled before this is called. | |
1882 | */ | |
1883 | void (*destroy)(struct i915_perf_stream *stream); | |
1884 | }; | |
1885 | ||
1886 | struct i915_perf_stream { | |
1887 | struct drm_i915_private *dev_priv; | |
1888 | ||
1889 | struct list_head link; | |
1890 | ||
1891 | u32 sample_flags; | |
d7965152 | 1892 | int sample_size; |
eec688e1 RB |
1893 | |
1894 | struct i915_gem_context *ctx; | |
1895 | bool enabled; | |
1896 | ||
d7965152 RB |
1897 | const struct i915_perf_stream_ops *ops; |
1898 | }; | |
1899 | ||
1900 | struct i915_oa_ops { | |
1901 | void (*init_oa_buffer)(struct drm_i915_private *dev_priv); | |
1902 | int (*enable_metric_set)(struct drm_i915_private *dev_priv); | |
1903 | void (*disable_metric_set)(struct drm_i915_private *dev_priv); | |
1904 | void (*oa_enable)(struct drm_i915_private *dev_priv); | |
1905 | void (*oa_disable)(struct drm_i915_private *dev_priv); | |
1906 | void (*update_oacontrol)(struct drm_i915_private *dev_priv); | |
1907 | void (*update_hw_ctx_id_locked)(struct drm_i915_private *dev_priv, | |
1908 | u32 ctx_id); | |
1909 | int (*read)(struct i915_perf_stream *stream, | |
1910 | char __user *buf, | |
1911 | size_t count, | |
1912 | size_t *offset); | |
1913 | bool (*oa_buffer_is_empty)(struct drm_i915_private *dev_priv); | |
eec688e1 RB |
1914 | }; |
1915 | ||
77fec556 | 1916 | struct drm_i915_private { |
8f460e2c CW |
1917 | struct drm_device drm; |
1918 | ||
efab6d8d | 1919 | struct kmem_cache *objects; |
e20d2ab7 | 1920 | struct kmem_cache *vmas; |
efab6d8d | 1921 | struct kmem_cache *requests; |
52e54209 | 1922 | struct kmem_cache *dependencies; |
f4c956ad | 1923 | |
5c969aa7 | 1924 | const struct intel_device_info info; |
f4c956ad DV |
1925 | |
1926 | int relative_constants_mode; | |
1927 | ||
1928 | void __iomem *regs; | |
1929 | ||
907b28c5 | 1930 | struct intel_uncore uncore; |
f4c956ad | 1931 | |
cf9d2890 YZ |
1932 | struct i915_virtual_gpu vgpu; |
1933 | ||
feddf6e8 | 1934 | struct intel_gvt *gvt; |
0ad35fed | 1935 | |
33a732f4 AD |
1936 | struct intel_guc guc; |
1937 | ||
eb805623 DV |
1938 | struct intel_csr csr; |
1939 | ||
5ea6e5e3 | 1940 | struct intel_gmbus gmbus[GMBUS_NUM_PINS]; |
28c70f16 | 1941 | |
f4c956ad DV |
1942 | /** gmbus_mutex protects against concurrent usage of the single hw gmbus |
1943 | * controller on different i2c buses. */ | |
1944 | struct mutex gmbus_mutex; | |
1945 | ||
1946 | /** | |
1947 | * Base address of the gmbus and gpio block. | |
1948 | */ | |
1949 | uint32_t gpio_mmio_base; | |
1950 | ||
b6fdd0f2 SS |
1951 | /* MMIO base address for MIPI regs */ |
1952 | uint32_t mipi_mmio_base; | |
1953 | ||
443a389f VS |
1954 | uint32_t psr_mmio_base; |
1955 | ||
44cb734c ID |
1956 | uint32_t pps_mmio_base; |
1957 | ||
28c70f16 DV |
1958 | wait_queue_head_t gmbus_wait_queue; |
1959 | ||
f4c956ad | 1960 | struct pci_dev *bridge_dev; |
0ca5fa3a | 1961 | struct i915_gem_context *kernel_context; |
3b3f1650 | 1962 | struct intel_engine_cs *engine[I915_NUM_ENGINES]; |
51d545d0 | 1963 | struct i915_vma *semaphore; |
f4c956ad | 1964 | |
ba8286fa | 1965 | struct drm_dma_handle *status_page_dmah; |
f4c956ad DV |
1966 | struct resource mch_res; |
1967 | ||
f4c956ad DV |
1968 | /* protects the irq masks */ |
1969 | spinlock_t irq_lock; | |
1970 | ||
84c33a64 SG |
1971 | /* protects the mmio flip data */ |
1972 | spinlock_t mmio_flip_lock; | |
1973 | ||
f8b79e58 ID |
1974 | bool display_irqs_enabled; |
1975 | ||
9ee32fea DV |
1976 | /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */ |
1977 | struct pm_qos_request pm_qos; | |
1978 | ||
a580516d VS |
1979 | /* Sideband mailbox protection */ |
1980 | struct mutex sb_lock; | |
f4c956ad DV |
1981 | |
1982 | /** Cached value of IMR to avoid reads in updating the bitfield */ | |
abd58f01 BW |
1983 | union { |
1984 | u32 irq_mask; | |
1985 | u32 de_irq_mask[I915_MAX_PIPES]; | |
1986 | }; | |
f4c956ad | 1987 | u32 gt_irq_mask; |
f4e9af4f AG |
1988 | u32 pm_imr; |
1989 | u32 pm_ier; | |
a6706b45 | 1990 | u32 pm_rps_events; |
26705e20 | 1991 | u32 pm_guc_events; |
91d181dd | 1992 | u32 pipestat_irq_mask[I915_MAX_PIPES]; |
f4c956ad | 1993 | |
5fcece80 | 1994 | struct i915_hotplug hotplug; |
ab34a7e8 | 1995 | struct intel_fbc fbc; |
439d7ac0 | 1996 | struct i915_drrs drrs; |
f4c956ad | 1997 | struct intel_opregion opregion; |
41aa3448 | 1998 | struct intel_vbt_data vbt; |
f4c956ad | 1999 | |
d9ceb816 JB |
2000 | bool preserve_bios_swizzle; |
2001 | ||
f4c956ad DV |
2002 | /* overlay */ |
2003 | struct intel_overlay *overlay; | |
f4c956ad | 2004 | |
58c68779 | 2005 | /* backlight registers and fields in struct intel_panel */ |
07f11d49 | 2006 | struct mutex backlight_lock; |
31ad8ec6 | 2007 | |
f4c956ad | 2008 | /* LVDS info */ |
f4c956ad DV |
2009 | bool no_aux_handshake; |
2010 | ||
e39b999a VS |
2011 | /* protects panel power sequencer state */ |
2012 | struct mutex pps_mutex; | |
2013 | ||
f4c956ad | 2014 | struct drm_i915_fence_reg fence_regs[I915_MAX_NUM_FENCES]; /* assume 965 */ |
f4c956ad DV |
2015 | int num_fence_regs; /* 8 on pre-965, 16 otherwise */ |
2016 | ||
2017 | unsigned int fsb_freq, mem_freq, is_ddr3; | |
b2045352 | 2018 | unsigned int skl_preferred_vco_freq; |
8d96561a VS |
2019 | unsigned int cdclk_freq, max_cdclk_freq; |
2020 | ||
2021 | /* | |
2022 | * For reading holding any crtc lock is sufficient, | |
2023 | * for writing must hold all of them. | |
2024 | */ | |
2025 | unsigned int atomic_cdclk_freq; | |
2026 | ||
adafdc6f | 2027 | unsigned int max_dotclk_freq; |
e7dc33f3 | 2028 | unsigned int rawclk_freq; |
6bcda4f0 | 2029 | unsigned int hpll_freq; |
bfa7df01 | 2030 | unsigned int czclk_freq; |
f4c956ad | 2031 | |
63911d72 | 2032 | struct { |
709e05c3 | 2033 | unsigned int vco, ref; |
63911d72 VS |
2034 | } cdclk_pll; |
2035 | ||
645416f5 DV |
2036 | /** |
2037 | * wq - Driver workqueue for GEM. | |
2038 | * | |
2039 | * NOTE: Work items scheduled here are not allowed to grab any modeset | |
2040 | * locks, for otherwise the flushing done in the pageflip code will | |
2041 | * result in deadlocks. | |
2042 | */ | |
f4c956ad DV |
2043 | struct workqueue_struct *wq; |
2044 | ||
2045 | /* Display functions */ | |
2046 | struct drm_i915_display_funcs display; | |
2047 | ||
2048 | /* PCH chipset type */ | |
2049 | enum intel_pch pch_type; | |
17a303ec | 2050 | unsigned short pch_id; |
f4c956ad DV |
2051 | |
2052 | unsigned long quirks; | |
2053 | ||
b8efb17b ZR |
2054 | enum modeset_restore modeset_restore; |
2055 | struct mutex modeset_restore_lock; | |
e2c8b870 | 2056 | struct drm_atomic_state *modeset_restore_state; |
73974893 | 2057 | struct drm_modeset_acquire_ctx reset_ctx; |
673a394b | 2058 | |
a7bbbd63 | 2059 | struct list_head vm_list; /* Global list of all address spaces */ |
62106b4f | 2060 | struct i915_ggtt ggtt; /* VM representing the global address space */ |
5d4545ae | 2061 | |
4b5aed62 | 2062 | struct i915_gem_mm mm; |
ad46cb53 CW |
2063 | DECLARE_HASHTABLE(mm_structs, 7); |
2064 | struct mutex mm_lock; | |
8781342d | 2065 | |
5d1808ec CW |
2066 | /* The hw wants to have a stable context identifier for the lifetime |
2067 | * of the context (for OA, PASID, faults, etc). This is limited | |
2068 | * in execlists to 21 bits. | |
2069 | */ | |
2070 | struct ida context_hw_ida; | |
2071 | #define MAX_CONTEXT_HW_ID (1<<21) /* exclusive */ | |
2072 | ||
8781342d DV |
2073 | /* Kernel Modesetting */ |
2074 | ||
e2af48c6 VS |
2075 | struct intel_crtc *plane_to_crtc_mapping[I915_MAX_PIPES]; |
2076 | struct intel_crtc *pipe_to_crtc_mapping[I915_MAX_PIPES]; | |
6b95a207 KH |
2077 | wait_queue_head_t pending_flip_queue; |
2078 | ||
c4597872 DV |
2079 | #ifdef CONFIG_DEBUG_FS |
2080 | struct intel_pipe_crc pipe_crc[I915_MAX_PIPES]; | |
2081 | #endif | |
2082 | ||
565602d7 | 2083 | /* dpll and cdclk state is protected by connection_mutex */ |
e72f9fbf DV |
2084 | int num_shared_dpll; |
2085 | struct intel_shared_dpll shared_dplls[I915_NUM_PLLS]; | |
f9476a6c | 2086 | const struct intel_dpll_mgr *dpll_mgr; |
565602d7 | 2087 | |
fbf6d879 ML |
2088 | /* |
2089 | * dpll_lock serializes intel_{prepare,enable,disable}_shared_dpll. | |
2090 | * Must be global rather than per dpll, because on some platforms | |
2091 | * plls share registers. | |
2092 | */ | |
2093 | struct mutex dpll_lock; | |
2094 | ||
565602d7 ML |
2095 | unsigned int active_crtcs; |
2096 | unsigned int min_pixclk[I915_MAX_PIPES]; | |
2097 | ||
e4607fcf | 2098 | int dpio_phy_iosf_port[I915_NUM_PHYS_VLV]; |
ee7b9f93 | 2099 | |
7225342a | 2100 | struct i915_workarounds workarounds; |
888b5995 | 2101 | |
f99d7069 DV |
2102 | struct i915_frontbuffer_tracking fb_tracking; |
2103 | ||
652c393a | 2104 | u16 orig_clock; |
f97108d1 | 2105 | |
c4804411 | 2106 | bool mchbar_need_disable; |
f97108d1 | 2107 | |
a4da4fa4 DV |
2108 | struct intel_l3_parity l3_parity; |
2109 | ||
59124506 | 2110 | /* Cannot be determined by PCIID. You must always read a register. */ |
3accaf7e | 2111 | u32 edram_cap; |
59124506 | 2112 | |
c6a828d3 | 2113 | /* gen6+ rps state */ |
c85aa885 | 2114 | struct intel_gen6_power_mgmt rps; |
c6a828d3 | 2115 | |
20e4d407 DV |
2116 | /* ilk-only ips/rps state. Everything in here is protected by the global |
2117 | * mchdev_lock in intel_pm.c */ | |
c85aa885 | 2118 | struct intel_ilk_power_mgmt ips; |
b5e50c3f | 2119 | |
83c00f55 | 2120 | struct i915_power_domains power_domains; |
a38911a3 | 2121 | |
a031d709 | 2122 | struct i915_psr psr; |
3f51e471 | 2123 | |
99584db3 | 2124 | struct i915_gpu_error gpu_error; |
ae681d96 | 2125 | |
c9cddffc JB |
2126 | struct drm_i915_gem_object *vlv_pctx; |
2127 | ||
0695726e | 2128 | #ifdef CONFIG_DRM_FBDEV_EMULATION |
8be48d92 DA |
2129 | /* list of fbdev register on this device */ |
2130 | struct intel_fbdev *fbdev; | |
82e3b8c1 | 2131 | struct work_struct fbdev_suspend_work; |
4520f53a | 2132 | #endif |
e953fd7b CW |
2133 | |
2134 | struct drm_property *broadcast_rgb_property; | |
3f43c48d | 2135 | struct drm_property *force_audio_property; |
e3689190 | 2136 | |
58fddc28 | 2137 | /* hda/i915 audio component */ |
51e1d83c | 2138 | struct i915_audio_component *audio_component; |
58fddc28 | 2139 | bool audio_component_registered; |
4a21ef7d LY |
2140 | /** |
2141 | * av_mutex - mutex for audio/video sync | |
2142 | * | |
2143 | */ | |
2144 | struct mutex av_mutex; | |
58fddc28 | 2145 | |
254f965c | 2146 | uint32_t hw_context_size; |
a33afea5 | 2147 | struct list_head context_list; |
f4c956ad | 2148 | |
3e68320e | 2149 | u32 fdi_rx_config; |
68d18ad7 | 2150 | |
c231775c | 2151 | /* Shadow for DISPLAY_PHY_CONTROL which can't be safely read */ |
70722468 | 2152 | u32 chv_phy_control; |
c231775c VS |
2153 | /* |
2154 | * Shadows for CHV DPLL_MD regs to keep the state | |
2155 | * checker somewhat working in the presence hardware | |
2156 | * crappiness (can't read out DPLL_MD for pipes B & C). | |
2157 | */ | |
2158 | u32 chv_dpll_md[I915_MAX_PIPES]; | |
adc7f04b | 2159 | u32 bxt_phy_grc; |
70722468 | 2160 | |
842f1c8b | 2161 | u32 suspend_count; |
bc87229f | 2162 | bool suspended_to_idle; |
f4c956ad | 2163 | struct i915_suspend_saved_registers regfile; |
ddeea5b0 | 2164 | struct vlv_s0ix_state vlv_s0ix_state; |
231f42a4 | 2165 | |
656d1b89 | 2166 | enum { |
16dcdc4e PZ |
2167 | I915_SAGV_UNKNOWN = 0, |
2168 | I915_SAGV_DISABLED, | |
2169 | I915_SAGV_ENABLED, | |
2170 | I915_SAGV_NOT_CONTROLLED | |
2171 | } sagv_status; | |
656d1b89 | 2172 | |
53615a5e VS |
2173 | struct { |
2174 | /* | |
2175 | * Raw watermark latency values: | |
2176 | * in 0.1us units for WM0, | |
2177 | * in 0.5us units for WM1+. | |
2178 | */ | |
2179 | /* primary */ | |
2180 | uint16_t pri_latency[5]; | |
2181 | /* sprite */ | |
2182 | uint16_t spr_latency[5]; | |
2183 | /* cursor */ | |
2184 | uint16_t cur_latency[5]; | |
2af30a5c PB |
2185 | /* |
2186 | * Raw watermark memory latency values | |
2187 | * for SKL for all 8 levels | |
2188 | * in 1us units. | |
2189 | */ | |
2190 | uint16_t skl_latency[8]; | |
609cedef VS |
2191 | |
2192 | /* current hardware state */ | |
2d41c0b5 PB |
2193 | union { |
2194 | struct ilk_wm_values hw; | |
2195 | struct skl_wm_values skl_hw; | |
0018fda1 | 2196 | struct vlv_wm_values vlv; |
2d41c0b5 | 2197 | }; |
58590c14 VS |
2198 | |
2199 | uint8_t max_level; | |
ed4a6a7c MR |
2200 | |
2201 | /* | |
2202 | * Should be held around atomic WM register writing; also | |
2203 | * protects * intel_crtc->wm.active and | |
2204 | * cstate->wm.need_postvbl_update. | |
2205 | */ | |
2206 | struct mutex wm_mutex; | |
279e99d7 MR |
2207 | |
2208 | /* | |
2209 | * Set during HW readout of watermarks/DDB. Some platforms | |
2210 | * need to know when we're still using BIOS-provided values | |
2211 | * (which we don't fully trust). | |
2212 | */ | |
2213 | bool distrust_bios_wm; | |
53615a5e VS |
2214 | } wm; |
2215 | ||
8a187455 PZ |
2216 | struct i915_runtime_pm pm; |
2217 | ||
eec688e1 RB |
2218 | struct { |
2219 | bool initialized; | |
d7965152 | 2220 | |
442b8c06 | 2221 | struct kobject *metrics_kobj; |
ccdf6341 | 2222 | struct ctl_table_header *sysctl_header; |
442b8c06 | 2223 | |
eec688e1 RB |
2224 | struct mutex lock; |
2225 | struct list_head streams; | |
8a3003dd | 2226 | |
d7965152 RB |
2227 | spinlock_t hook_lock; |
2228 | ||
8a3003dd | 2229 | struct { |
d7965152 RB |
2230 | struct i915_perf_stream *exclusive_stream; |
2231 | ||
2232 | u32 specific_ctx_id; | |
2233 | struct i915_vma *pinned_rcs_vma; | |
2234 | ||
2235 | struct hrtimer poll_check_timer; | |
2236 | wait_queue_head_t poll_wq; | |
2237 | bool pollin; | |
2238 | ||
2239 | bool periodic; | |
2240 | int period_exponent; | |
2241 | int timestamp_frequency; | |
2242 | ||
2243 | int tail_margin; | |
2244 | ||
2245 | int metrics_set; | |
8a3003dd RB |
2246 | |
2247 | const struct i915_oa_reg *mux_regs; | |
2248 | int mux_regs_len; | |
2249 | const struct i915_oa_reg *b_counter_regs; | |
2250 | int b_counter_regs_len; | |
d7965152 RB |
2251 | |
2252 | struct { | |
2253 | struct i915_vma *vma; | |
2254 | u8 *vaddr; | |
2255 | int format; | |
2256 | int format_size; | |
2257 | } oa_buffer; | |
2258 | ||
2259 | u32 gen7_latched_oastatus1; | |
2260 | ||
2261 | struct i915_oa_ops ops; | |
2262 | const struct i915_oa_format *oa_formats; | |
2263 | int n_builtin_sets; | |
8a3003dd | 2264 | } oa; |
eec688e1 RB |
2265 | } perf; |
2266 | ||
a83014d3 OM |
2267 | /* Abstract the submission mechanism (legacy ringbuffer or execlists) away */ |
2268 | struct { | |
821ed7df | 2269 | void (*resume)(struct drm_i915_private *); |
117897f4 | 2270 | void (*cleanup_engine)(struct intel_engine_cs *engine); |
67d97da3 | 2271 | |
73cb9701 CW |
2272 | struct list_head timelines; |
2273 | struct i915_gem_timeline global_timeline; | |
28176ef4 | 2274 | u32 active_requests; |
73cb9701 | 2275 | |
67d97da3 CW |
2276 | /** |
2277 | * Is the GPU currently considered idle, or busy executing | |
2278 | * userspace requests? Whilst idle, we allow runtime power | |
2279 | * management to power down the hardware and display clocks. | |
2280 | * In order to reduce the effect on performance, there | |
2281 | * is a slight delay before we do so. | |
2282 | */ | |
67d97da3 CW |
2283 | bool awake; |
2284 | ||
2285 | /** | |
2286 | * We leave the user IRQ off as much as possible, | |
2287 | * but this means that requests will finish and never | |
2288 | * be retired once the system goes idle. Set a timer to | |
2289 | * fire periodically while the ring is running. When it | |
2290 | * fires, go retire requests. | |
2291 | */ | |
2292 | struct delayed_work retire_work; | |
2293 | ||
2294 | /** | |
2295 | * When we detect an idle GPU, we want to turn on | |
2296 | * powersaving features. So once we see that there | |
2297 | * are no more requests outstanding and no more | |
2298 | * arrive within a small period of time, we fire | |
2299 | * off the idle_work. | |
2300 | */ | |
2301 | struct delayed_work idle_work; | |
de867c20 CW |
2302 | |
2303 | ktime_t last_init_time; | |
a83014d3 OM |
2304 | } gt; |
2305 | ||
3be60de9 VS |
2306 | /* perform PHY state sanity checks? */ |
2307 | bool chv_phy_assert[2]; | |
2308 | ||
f9318941 PD |
2309 | /* Used to save the pipe-to-encoder mapping for audio */ |
2310 | struct intel_encoder *av_enc_map[I915_MAX_PIPES]; | |
0bdf5a05 | 2311 | |
bdf1e7e3 DV |
2312 | /* |
2313 | * NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch | |
2314 | * will be rejected. Instead look for a better place. | |
2315 | */ | |
77fec556 | 2316 | }; |
1da177e4 | 2317 | |
2c1792a1 CW |
2318 | static inline struct drm_i915_private *to_i915(const struct drm_device *dev) |
2319 | { | |
091387c1 | 2320 | return container_of(dev, struct drm_i915_private, drm); |
2c1792a1 CW |
2321 | } |
2322 | ||
c49d13ee | 2323 | static inline struct drm_i915_private *kdev_to_i915(struct device *kdev) |
888d0d42 | 2324 | { |
c49d13ee | 2325 | return to_i915(dev_get_drvdata(kdev)); |
888d0d42 ID |
2326 | } |
2327 | ||
33a732f4 AD |
2328 | static inline struct drm_i915_private *guc_to_i915(struct intel_guc *guc) |
2329 | { | |
2330 | return container_of(guc, struct drm_i915_private, guc); | |
2331 | } | |
2332 | ||
b4ac5afc | 2333 | /* Simple iterator over all initialised engines */ |
3b3f1650 AG |
2334 | #define for_each_engine(engine__, dev_priv__, id__) \ |
2335 | for ((id__) = 0; \ | |
2336 | (id__) < I915_NUM_ENGINES; \ | |
2337 | (id__)++) \ | |
2338 | for_each_if ((engine__) = (dev_priv__)->engine[(id__)]) | |
c3232b18 | 2339 | |
bafb0fce CW |
2340 | #define __mask_next_bit(mask) ({ \ |
2341 | int __idx = ffs(mask) - 1; \ | |
2342 | mask &= ~BIT(__idx); \ | |
2343 | __idx; \ | |
2344 | }) | |
2345 | ||
c3232b18 | 2346 | /* Iterator over subset of engines selected by mask */ |
bafb0fce CW |
2347 | #define for_each_engine_masked(engine__, dev_priv__, mask__, tmp__) \ |
2348 | for (tmp__ = mask__ & INTEL_INFO(dev_priv__)->ring_mask; \ | |
3b3f1650 | 2349 | tmp__ ? (engine__ = (dev_priv__)->engine[__mask_next_bit(tmp__)]), 1 : 0; ) |
ee4b6faf | 2350 | |
b1d7e4b4 WF |
2351 | enum hdmi_force_audio { |
2352 | HDMI_AUDIO_OFF_DVI = -2, /* no aux data for HDMI-DVI converter */ | |
2353 | HDMI_AUDIO_OFF, /* force turn off HDMI audio */ | |
2354 | HDMI_AUDIO_AUTO, /* trust EDID */ | |
2355 | HDMI_AUDIO_ON, /* force turn on HDMI audio */ | |
2356 | }; | |
2357 | ||
190d6cd5 | 2358 | #define I915_GTT_OFFSET_NONE ((u32)-1) |
ed2f3452 | 2359 | |
a071fa00 DV |
2360 | /* |
2361 | * Frontbuffer tracking bits. Set in obj->frontbuffer_bits while a gem bo is | |
d1b9d039 | 2362 | * considered to be the frontbuffer for the given plane interface-wise. This |
a071fa00 DV |
2363 | * doesn't mean that the hw necessarily already scans it out, but that any |
2364 | * rendering (by the cpu or gpu) will land in the frontbuffer eventually. | |
2365 | * | |
2366 | * We have one bit per pipe and per scanout plane type. | |
2367 | */ | |
d1b9d039 SAK |
2368 | #define INTEL_MAX_SPRITE_BITS_PER_PIPE 5 |
2369 | #define INTEL_FRONTBUFFER_BITS_PER_PIPE 8 | |
a071fa00 DV |
2370 | #define INTEL_FRONTBUFFER_PRIMARY(pipe) \ |
2371 | (1 << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))) | |
2372 | #define INTEL_FRONTBUFFER_CURSOR(pipe) \ | |
d1b9d039 SAK |
2373 | (1 << (1 + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))) |
2374 | #define INTEL_FRONTBUFFER_SPRITE(pipe, plane) \ | |
2375 | (1 << (2 + plane + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))) | |
a071fa00 | 2376 | #define INTEL_FRONTBUFFER_OVERLAY(pipe) \ |
d1b9d039 | 2377 | (1 << (2 + INTEL_MAX_SPRITE_BITS_PER_PIPE + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))) |
cc36513c | 2378 | #define INTEL_FRONTBUFFER_ALL_MASK(pipe) \ |
d1b9d039 | 2379 | (0xff << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))) |
a071fa00 | 2380 | |
85d1225e DG |
2381 | /* |
2382 | * Optimised SGL iterator for GEM objects | |
2383 | */ | |
2384 | static __always_inline struct sgt_iter { | |
2385 | struct scatterlist *sgp; | |
2386 | union { | |
2387 | unsigned long pfn; | |
2388 | dma_addr_t dma; | |
2389 | }; | |
2390 | unsigned int curr; | |
2391 | unsigned int max; | |
2392 | } __sgt_iter(struct scatterlist *sgl, bool dma) { | |
2393 | struct sgt_iter s = { .sgp = sgl }; | |
2394 | ||
2395 | if (s.sgp) { | |
2396 | s.max = s.curr = s.sgp->offset; | |
2397 | s.max += s.sgp->length; | |
2398 | if (dma) | |
2399 | s.dma = sg_dma_address(s.sgp); | |
2400 | else | |
2401 | s.pfn = page_to_pfn(sg_page(s.sgp)); | |
2402 | } | |
2403 | ||
2404 | return s; | |
2405 | } | |
2406 | ||
96d77634 CW |
2407 | static inline struct scatterlist *____sg_next(struct scatterlist *sg) |
2408 | { | |
2409 | ++sg; | |
2410 | if (unlikely(sg_is_chain(sg))) | |
2411 | sg = sg_chain_ptr(sg); | |
2412 | return sg; | |
2413 | } | |
2414 | ||
63d15326 DG |
2415 | /** |
2416 | * __sg_next - return the next scatterlist entry in a list | |
2417 | * @sg: The current sg entry | |
2418 | * | |
2419 | * Description: | |
2420 | * If the entry is the last, return NULL; otherwise, step to the next | |
2421 | * element in the array (@sg@+1). If that's a chain pointer, follow it; | |
2422 | * otherwise just return the pointer to the current element. | |
2423 | **/ | |
2424 | static inline struct scatterlist *__sg_next(struct scatterlist *sg) | |
2425 | { | |
2426 | #ifdef CONFIG_DEBUG_SG | |
2427 | BUG_ON(sg->sg_magic != SG_MAGIC); | |
2428 | #endif | |
96d77634 | 2429 | return sg_is_last(sg) ? NULL : ____sg_next(sg); |
63d15326 DG |
2430 | } |
2431 | ||
85d1225e DG |
2432 | /** |
2433 | * for_each_sgt_dma - iterate over the DMA addresses of the given sg_table | |
2434 | * @__dmap: DMA address (output) | |
2435 | * @__iter: 'struct sgt_iter' (iterator state, internal) | |
2436 | * @__sgt: sg_table to iterate over (input) | |
2437 | */ | |
2438 | #define for_each_sgt_dma(__dmap, __iter, __sgt) \ | |
2439 | for ((__iter) = __sgt_iter((__sgt)->sgl, true); \ | |
2440 | ((__dmap) = (__iter).dma + (__iter).curr); \ | |
2441 | (((__iter).curr += PAGE_SIZE) < (__iter).max) || \ | |
63d15326 | 2442 | ((__iter) = __sgt_iter(__sg_next((__iter).sgp), true), 0)) |
85d1225e DG |
2443 | |
2444 | /** | |
2445 | * for_each_sgt_page - iterate over the pages of the given sg_table | |
2446 | * @__pp: page pointer (output) | |
2447 | * @__iter: 'struct sgt_iter' (iterator state, internal) | |
2448 | * @__sgt: sg_table to iterate over (input) | |
2449 | */ | |
2450 | #define for_each_sgt_page(__pp, __iter, __sgt) \ | |
2451 | for ((__iter) = __sgt_iter((__sgt)->sgl, false); \ | |
2452 | ((__pp) = (__iter).pfn == 0 ? NULL : \ | |
2453 | pfn_to_page((__iter).pfn + ((__iter).curr >> PAGE_SHIFT))); \ | |
2454 | (((__iter).curr += PAGE_SIZE) < (__iter).max) || \ | |
63d15326 | 2455 | ((__iter) = __sgt_iter(__sg_next((__iter).sgp), false), 0)) |
a071fa00 | 2456 | |
5ca43ef0 TU |
2457 | static inline const struct intel_device_info * |
2458 | intel_info(const struct drm_i915_private *dev_priv) | |
2459 | { | |
2460 | return &dev_priv->info; | |
2461 | } | |
2462 | ||
2463 | #define INTEL_INFO(dev_priv) intel_info((dev_priv)) | |
50a0bc90 | 2464 | |
55b8f2a7 | 2465 | #define INTEL_GEN(dev_priv) ((dev_priv)->info.gen) |
50a0bc90 | 2466 | #define INTEL_DEVID(dev_priv) ((dev_priv)->info.device_id) |
cae5852d | 2467 | |
e87a005d | 2468 | #define REVID_FOREVER 0xff |
4805fe82 | 2469 | #define INTEL_REVID(dev_priv) ((dev_priv)->drm.pdev->revision) |
ac657f64 TU |
2470 | |
2471 | #define GEN_FOREVER (0) | |
2472 | /* | |
2473 | * Returns true if Gen is in inclusive range [Start, End]. | |
2474 | * | |
2475 | * Use GEN_FOREVER for unbound start and or end. | |
2476 | */ | |
c1812bdb | 2477 | #define IS_GEN(dev_priv, s, e) ({ \ |
ac657f64 TU |
2478 | unsigned int __s = (s), __e = (e); \ |
2479 | BUILD_BUG_ON(!__builtin_constant_p(s)); \ | |
2480 | BUILD_BUG_ON(!__builtin_constant_p(e)); \ | |
2481 | if ((__s) != GEN_FOREVER) \ | |
2482 | __s = (s) - 1; \ | |
2483 | if ((__e) == GEN_FOREVER) \ | |
2484 | __e = BITS_PER_LONG - 1; \ | |
2485 | else \ | |
2486 | __e = (e) - 1; \ | |
c1812bdb | 2487 | !!((dev_priv)->info.gen_mask & GENMASK((__e), (__s))); \ |
ac657f64 TU |
2488 | }) |
2489 | ||
e87a005d JN |
2490 | /* |
2491 | * Return true if revision is in range [since,until] inclusive. | |
2492 | * | |
2493 | * Use 0 for open-ended since, and REVID_FOREVER for open-ended until. | |
2494 | */ | |
2495 | #define IS_REVID(p, since, until) \ | |
2496 | (INTEL_REVID(p) >= (since) && INTEL_REVID(p) <= (until)) | |
2497 | ||
50a0bc90 TU |
2498 | #define IS_I830(dev_priv) (INTEL_DEVID(dev_priv) == 0x3577) |
2499 | #define IS_845G(dev_priv) (INTEL_DEVID(dev_priv) == 0x2562) | |
a9097be4 | 2500 | #define IS_I85X(dev_priv) ((dev_priv)->info.is_i85x) |
50a0bc90 | 2501 | #define IS_I865G(dev_priv) (INTEL_DEVID(dev_priv) == 0x2572) |
a9097be4 | 2502 | #define IS_I915G(dev_priv) ((dev_priv)->info.is_i915g) |
50a0bc90 TU |
2503 | #define IS_I915GM(dev_priv) (INTEL_DEVID(dev_priv) == 0x2592) |
2504 | #define IS_I945G(dev_priv) (INTEL_DEVID(dev_priv) == 0x2772) | |
a9097be4 | 2505 | #define IS_I945GM(dev_priv) ((dev_priv)->info.is_i945gm) |
a26e5239 VS |
2506 | #define IS_BROADWATER(dev_priv) ((dev_priv)->info.is_broadwater) |
2507 | #define IS_CRESTLINE(dev_priv) ((dev_priv)->info.is_crestline) | |
50a0bc90 | 2508 | #define IS_GM45(dev_priv) (INTEL_DEVID(dev_priv) == 0x2A42) |
9beb5fea | 2509 | #define IS_G4X(dev_priv) ((dev_priv)->info.is_g4x) |
50a0bc90 TU |
2510 | #define IS_PINEVIEW_G(dev_priv) (INTEL_DEVID(dev_priv) == 0xa001) |
2511 | #define IS_PINEVIEW_M(dev_priv) (INTEL_DEVID(dev_priv) == 0xa011) | |
9b1e14f4 | 2512 | #define IS_PINEVIEW(dev_priv) ((dev_priv)->info.is_pineview) |
a9097be4 | 2513 | #define IS_G33(dev_priv) ((dev_priv)->info.is_g33) |
50a0bc90 | 2514 | #define IS_IRONLAKE_M(dev_priv) (INTEL_DEVID(dev_priv) == 0x0046) |
fd6b8f43 | 2515 | #define IS_IVYBRIDGE(dev_priv) ((dev_priv)->info.is_ivybridge) |
50a0bc90 TU |
2516 | #define IS_IVB_GT1(dev_priv) (INTEL_DEVID(dev_priv) == 0x0156 || \ |
2517 | INTEL_DEVID(dev_priv) == 0x0152 || \ | |
2518 | INTEL_DEVID(dev_priv) == 0x015a) | |
11a914c2 | 2519 | #define IS_VALLEYVIEW(dev_priv) ((dev_priv)->info.is_valleyview) |
920a14b2 | 2520 | #define IS_CHERRYVIEW(dev_priv) ((dev_priv)->info.is_cherryview) |
772c2a51 | 2521 | #define IS_HASWELL(dev_priv) ((dev_priv)->info.is_haswell) |
8652744b | 2522 | #define IS_BROADWELL(dev_priv) ((dev_priv)->info.is_broadwell) |
d9486e65 | 2523 | #define IS_SKYLAKE(dev_priv) ((dev_priv)->info.is_skylake) |
e2d214ae | 2524 | #define IS_BROXTON(dev_priv) ((dev_priv)->info.is_broxton) |
0853723b | 2525 | #define IS_KABYLAKE(dev_priv) ((dev_priv)->info.is_kabylake) |
646d5772 | 2526 | #define IS_MOBILE(dev_priv) ((dev_priv)->info.is_mobile) |
50a0bc90 TU |
2527 | #define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \ |
2528 | (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0C00) | |
2529 | #define IS_BDW_ULT(dev_priv) (IS_BROADWELL(dev_priv) && \ | |
2530 | ((INTEL_DEVID(dev_priv) & 0xf) == 0x6 || \ | |
2531 | (INTEL_DEVID(dev_priv) & 0xf) == 0xb || \ | |
2532 | (INTEL_DEVID(dev_priv) & 0xf) == 0xe)) | |
ebb72aad | 2533 | /* ULX machines are also considered ULT. */ |
50a0bc90 TU |
2534 | #define IS_BDW_ULX(dev_priv) (IS_BROADWELL(dev_priv) && \ |
2535 | (INTEL_DEVID(dev_priv) & 0xf) == 0xe) | |
2536 | #define IS_BDW_GT3(dev_priv) (IS_BROADWELL(dev_priv) && \ | |
2537 | (INTEL_DEVID(dev_priv) & 0x00F0) == 0x0020) | |
2538 | #define IS_HSW_ULT(dev_priv) (IS_HASWELL(dev_priv) && \ | |
2539 | (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0A00) | |
2540 | #define IS_HSW_GT3(dev_priv) (IS_HASWELL(dev_priv) && \ | |
2541 | (INTEL_DEVID(dev_priv) & 0x00F0) == 0x0020) | |
9bbfd20a | 2542 | /* ULX machines are also considered ULT. */ |
50a0bc90 TU |
2543 | #define IS_HSW_ULX(dev_priv) (INTEL_DEVID(dev_priv) == 0x0A0E || \ |
2544 | INTEL_DEVID(dev_priv) == 0x0A1E) | |
2545 | #define IS_SKL_ULT(dev_priv) (INTEL_DEVID(dev_priv) == 0x1906 || \ | |
2546 | INTEL_DEVID(dev_priv) == 0x1913 || \ | |
2547 | INTEL_DEVID(dev_priv) == 0x1916 || \ | |
2548 | INTEL_DEVID(dev_priv) == 0x1921 || \ | |
2549 | INTEL_DEVID(dev_priv) == 0x1926) | |
2550 | #define IS_SKL_ULX(dev_priv) (INTEL_DEVID(dev_priv) == 0x190E || \ | |
2551 | INTEL_DEVID(dev_priv) == 0x1915 || \ | |
2552 | INTEL_DEVID(dev_priv) == 0x191E) | |
2553 | #define IS_KBL_ULT(dev_priv) (INTEL_DEVID(dev_priv) == 0x5906 || \ | |
2554 | INTEL_DEVID(dev_priv) == 0x5913 || \ | |
2555 | INTEL_DEVID(dev_priv) == 0x5916 || \ | |
2556 | INTEL_DEVID(dev_priv) == 0x5921 || \ | |
2557 | INTEL_DEVID(dev_priv) == 0x5926) | |
2558 | #define IS_KBL_ULX(dev_priv) (INTEL_DEVID(dev_priv) == 0x590E || \ | |
2559 | INTEL_DEVID(dev_priv) == 0x5915 || \ | |
2560 | INTEL_DEVID(dev_priv) == 0x591E) | |
2561 | #define IS_SKL_GT3(dev_priv) (IS_SKYLAKE(dev_priv) && \ | |
2562 | (INTEL_DEVID(dev_priv) & 0x00F0) == 0x0020) | |
2563 | #define IS_SKL_GT4(dev_priv) (IS_SKYLAKE(dev_priv) && \ | |
2564 | (INTEL_DEVID(dev_priv) & 0x00F0) == 0x0030) | |
7a58bad0 | 2565 | |
c007fb4a | 2566 | #define IS_ALPHA_SUPPORT(intel_info) ((intel_info)->is_alpha_support) |
cae5852d | 2567 | |
ef712bb4 JN |
2568 | #define SKL_REVID_A0 0x0 |
2569 | #define SKL_REVID_B0 0x1 | |
2570 | #define SKL_REVID_C0 0x2 | |
2571 | #define SKL_REVID_D0 0x3 | |
2572 | #define SKL_REVID_E0 0x4 | |
2573 | #define SKL_REVID_F0 0x5 | |
4ba9c1f7 MK |
2574 | #define SKL_REVID_G0 0x6 |
2575 | #define SKL_REVID_H0 0x7 | |
ef712bb4 | 2576 | |
e87a005d JN |
2577 | #define IS_SKL_REVID(p, since, until) (IS_SKYLAKE(p) && IS_REVID(p, since, until)) |
2578 | ||
ef712bb4 | 2579 | #define BXT_REVID_A0 0x0 |
fffda3f4 | 2580 | #define BXT_REVID_A1 0x1 |
ef712bb4 JN |
2581 | #define BXT_REVID_B0 0x3 |
2582 | #define BXT_REVID_C0 0x9 | |
6c74c87f | 2583 | |
e2d214ae TU |
2584 | #define IS_BXT_REVID(dev_priv, since, until) \ |
2585 | (IS_BROXTON(dev_priv) && IS_REVID(dev_priv, since, until)) | |
e87a005d | 2586 | |
c033a37c MK |
2587 | #define KBL_REVID_A0 0x0 |
2588 | #define KBL_REVID_B0 0x1 | |
fe905819 MK |
2589 | #define KBL_REVID_C0 0x2 |
2590 | #define KBL_REVID_D0 0x3 | |
2591 | #define KBL_REVID_E0 0x4 | |
c033a37c | 2592 | |
0853723b TU |
2593 | #define IS_KBL_REVID(dev_priv, since, until) \ |
2594 | (IS_KABYLAKE(dev_priv) && IS_REVID(dev_priv, since, until)) | |
c033a37c | 2595 | |
85436696 JB |
2596 | /* |
2597 | * The genX designation typically refers to the render engine, so render | |
2598 | * capability related checks should use IS_GEN, while display and other checks | |
2599 | * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular | |
2600 | * chips, etc.). | |
2601 | */ | |
5db94019 TU |
2602 | #define IS_GEN2(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(1))) |
2603 | #define IS_GEN3(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(2))) | |
2604 | #define IS_GEN4(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(3))) | |
2605 | #define IS_GEN5(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(4))) | |
2606 | #define IS_GEN6(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(5))) | |
2607 | #define IS_GEN7(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(6))) | |
2608 | #define IS_GEN8(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(7))) | |
2609 | #define IS_GEN9(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(8))) | |
cae5852d | 2610 | |
a19d6ff2 TU |
2611 | #define ENGINE_MASK(id) BIT(id) |
2612 | #define RENDER_RING ENGINE_MASK(RCS) | |
2613 | #define BSD_RING ENGINE_MASK(VCS) | |
2614 | #define BLT_RING ENGINE_MASK(BCS) | |
2615 | #define VEBOX_RING ENGINE_MASK(VECS) | |
2616 | #define BSD2_RING ENGINE_MASK(VCS2) | |
2617 | #define ALL_ENGINES (~0) | |
2618 | ||
2619 | #define HAS_ENGINE(dev_priv, id) \ | |
0031fb96 | 2620 | (!!((dev_priv)->info.ring_mask & ENGINE_MASK(id))) |
a19d6ff2 TU |
2621 | |
2622 | #define HAS_BSD(dev_priv) HAS_ENGINE(dev_priv, VCS) | |
2623 | #define HAS_BSD2(dev_priv) HAS_ENGINE(dev_priv, VCS2) | |
2624 | #define HAS_BLT(dev_priv) HAS_ENGINE(dev_priv, BCS) | |
2625 | #define HAS_VEBOX(dev_priv) HAS_ENGINE(dev_priv, VECS) | |
2626 | ||
0031fb96 TU |
2627 | #define HAS_LLC(dev_priv) ((dev_priv)->info.has_llc) |
2628 | #define HAS_SNOOP(dev_priv) ((dev_priv)->info.has_snoop) | |
2629 | #define HAS_EDRAM(dev_priv) (!!((dev_priv)->edram_cap & EDRAM_ENABLED)) | |
8652744b TU |
2630 | #define HAS_WT(dev_priv) ((IS_HASWELL(dev_priv) || \ |
2631 | IS_BROADWELL(dev_priv)) && HAS_EDRAM(dev_priv)) | |
cae5852d | 2632 | |
0031fb96 | 2633 | #define HWS_NEEDS_PHYSICAL(dev_priv) ((dev_priv)->info.hws_needs_physical) |
1d2a314c | 2634 | |
0031fb96 TU |
2635 | #define HAS_HW_CONTEXTS(dev_priv) ((dev_priv)->info.has_hw_contexts) |
2636 | #define HAS_LOGICAL_RING_CONTEXTS(dev_priv) \ | |
2637 | ((dev_priv)->info.has_logical_ring_contexts) | |
2638 | #define USES_PPGTT(dev_priv) (i915.enable_ppgtt) | |
2639 | #define USES_FULL_PPGTT(dev_priv) (i915.enable_ppgtt >= 2) | |
2640 | #define USES_FULL_48BIT_PPGTT(dev_priv) (i915.enable_ppgtt == 3) | |
2641 | ||
2642 | #define HAS_OVERLAY(dev_priv) ((dev_priv)->info.has_overlay) | |
2643 | #define OVERLAY_NEEDS_PHYSICAL(dev_priv) \ | |
2644 | ((dev_priv)->info.overlay_needs_physical) | |
cae5852d | 2645 | |
b45305fc | 2646 | /* Early gen2 have a totally busted CS tlb and require pinned batches. */ |
50a0bc90 | 2647 | #define HAS_BROKEN_CS_TLB(dev_priv) (IS_I830(dev_priv) || IS_845G(dev_priv)) |
06e668ac MK |
2648 | |
2649 | /* WaRsDisableCoarsePowerGating:skl,bxt */ | |
61251512 TU |
2650 | #define NEEDS_WaRsDisableCoarsePowerGating(dev_priv) \ |
2651 | (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1) || \ | |
2652 | IS_SKL_GT3(dev_priv) || \ | |
2653 | IS_SKL_GT4(dev_priv)) | |
185c66e5 | 2654 | |
4e6b788c DV |
2655 | /* |
2656 | * dp aux and gmbus irq on gen4 seems to be able to generate legacy interrupts | |
2657 | * even when in MSI mode. This results in spurious interrupt warnings if the | |
2658 | * legacy irq no. is shared with another device. The kernel then disables that | |
2659 | * interrupt source and so prevents the other device from working properly. | |
2660 | */ | |
0031fb96 TU |
2661 | #define HAS_AUX_IRQ(dev_priv) ((dev_priv)->info.gen >= 5) |
2662 | #define HAS_GMBUS_IRQ(dev_priv) ((dev_priv)->info.has_gmbus_irq) | |
b45305fc | 2663 | |
cae5852d ZN |
2664 | /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte |
2665 | * rows, which changed the alignment requirements and fence programming. | |
2666 | */ | |
50a0bc90 TU |
2667 | #define HAS_128_BYTE_Y_TILING(dev_priv) (!IS_GEN2(dev_priv) && \ |
2668 | !(IS_I915G(dev_priv) || \ | |
2669 | IS_I915GM(dev_priv))) | |
56b857a5 TU |
2670 | #define SUPPORTS_TV(dev_priv) ((dev_priv)->info.supports_tv) |
2671 | #define I915_HAS_HOTPLUG(dev_priv) ((dev_priv)->info.has_hotplug) | |
cae5852d | 2672 | |
56b857a5 TU |
2673 | #define HAS_FW_BLC(dev_priv) (INTEL_GEN(dev_priv) > 2) |
2674 | #define HAS_PIPE_CXSR(dev_priv) ((dev_priv)->info.has_pipe_cxsr) | |
2675 | #define HAS_FBC(dev_priv) ((dev_priv)->info.has_fbc) | |
cae5852d | 2676 | |
50a0bc90 | 2677 | #define HAS_IPS(dev_priv) (IS_HSW_ULT(dev_priv) || IS_BROADWELL(dev_priv)) |
f5adf94e | 2678 | |
56b857a5 | 2679 | #define HAS_DP_MST(dev_priv) ((dev_priv)->info.has_dp_mst) |
0c9b3715 | 2680 | |
56b857a5 TU |
2681 | #define HAS_DDI(dev_priv) ((dev_priv)->info.has_ddi) |
2682 | #define HAS_FPGA_DBG_UNCLAIMED(dev_priv) ((dev_priv)->info.has_fpga_dbg) | |
2683 | #define HAS_PSR(dev_priv) ((dev_priv)->info.has_psr) | |
2684 | #define HAS_RC6(dev_priv) ((dev_priv)->info.has_rc6) | |
2685 | #define HAS_RC6p(dev_priv) ((dev_priv)->info.has_rc6p) | |
affa9354 | 2686 | |
56b857a5 | 2687 | #define HAS_CSR(dev_priv) ((dev_priv)->info.has_csr) |
eb805623 | 2688 | |
6772ffe0 | 2689 | #define HAS_RUNTIME_PM(dev_priv) ((dev_priv)->info.has_runtime_pm) |
dfc5148f JL |
2690 | #define HAS_64BIT_RELOC(dev_priv) ((dev_priv)->info.has_64bit_reloc) |
2691 | ||
1a3d1898 DG |
2692 | /* |
2693 | * For now, anything with a GuC requires uCode loading, and then supports | |
2694 | * command submission once loaded. But these are logically independent | |
2695 | * properties, so we have separate macros to test them. | |
2696 | */ | |
4805fe82 TU |
2697 | #define HAS_GUC(dev_priv) ((dev_priv)->info.has_guc) |
2698 | #define HAS_GUC_UCODE(dev_priv) (HAS_GUC(dev_priv)) | |
2699 | #define HAS_GUC_SCHED(dev_priv) (HAS_GUC(dev_priv)) | |
33a732f4 | 2700 | |
4805fe82 | 2701 | #define HAS_RESOURCE_STREAMER(dev_priv) ((dev_priv)->info.has_resource_streamer) |
a9ed33ca | 2702 | |
4805fe82 | 2703 | #define HAS_POOLED_EU(dev_priv) ((dev_priv)->info.has_pooled_eu) |
33e141ed | 2704 | |
17a303ec PZ |
2705 | #define INTEL_PCH_DEVICE_ID_MASK 0xff00 |
2706 | #define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00 | |
2707 | #define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00 | |
2708 | #define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00 | |
2709 | #define INTEL_PCH_LPT_DEVICE_ID_TYPE 0x8c00 | |
2710 | #define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE 0x9c00 | |
e7e7ea20 S |
2711 | #define INTEL_PCH_SPT_DEVICE_ID_TYPE 0xA100 |
2712 | #define INTEL_PCH_SPT_LP_DEVICE_ID_TYPE 0x9D00 | |
22dea0be | 2713 | #define INTEL_PCH_KBP_DEVICE_ID_TYPE 0xA200 |
30c964a6 | 2714 | #define INTEL_PCH_P2X_DEVICE_ID_TYPE 0x7100 |
1844a66b | 2715 | #define INTEL_PCH_P3X_DEVICE_ID_TYPE 0x7000 |
39bfcd52 | 2716 | #define INTEL_PCH_QEMU_DEVICE_ID_TYPE 0x2900 /* qemu q35 has 2918 */ |
17a303ec | 2717 | |
6e266956 TU |
2718 | #define INTEL_PCH_TYPE(dev_priv) ((dev_priv)->pch_type) |
2719 | #define HAS_PCH_KBP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_KBP) | |
2720 | #define HAS_PCH_SPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_SPT) | |
2721 | #define HAS_PCH_LPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_LPT) | |
4f8036a2 TU |
2722 | #define HAS_PCH_LPT_LP(dev_priv) \ |
2723 | ((dev_priv)->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) | |
2724 | #define HAS_PCH_LPT_H(dev_priv) \ | |
2725 | ((dev_priv)->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE) | |
6e266956 TU |
2726 | #define HAS_PCH_CPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_CPT) |
2727 | #define HAS_PCH_IBX(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_IBX) | |
2728 | #define HAS_PCH_NOP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_NOP) | |
2729 | #define HAS_PCH_SPLIT(dev_priv) (INTEL_PCH_TYPE(dev_priv) != PCH_NONE) | |
cae5852d | 2730 | |
49cff963 | 2731 | #define HAS_GMCH_DISPLAY(dev_priv) ((dev_priv)->info.has_gmch_display) |
5fafe292 | 2732 | |
6389dd83 SS |
2733 | #define HAS_LSPCON(dev_priv) (IS_GEN9(dev_priv)) |
2734 | ||
040d2baa | 2735 | /* DPF == dynamic parity feature */ |
3c9192bc | 2736 | #define HAS_L3_DPF(dev_priv) ((dev_priv)->info.has_l3_dpf) |
50a0bc90 TU |
2737 | #define NUM_L3_SLICES(dev_priv) (IS_HSW_GT3(dev_priv) ? \ |
2738 | 2 : HAS_L3_DPF(dev_priv)) | |
e1ef7cc2 | 2739 | |
c8735b0c | 2740 | #define GT_FREQUENCY_MULTIPLIER 50 |
de43ae9d | 2741 | #define GEN9_FREQ_SCALER 3 |
c8735b0c | 2742 | |
85ee17eb PP |
2743 | #define HAS_DECOUPLED_MMIO(dev_priv) (INTEL_INFO(dev_priv)->has_decoupled_mmio) |
2744 | ||
05394f39 CW |
2745 | #include "i915_trace.h" |
2746 | ||
48f112fe CW |
2747 | static inline bool intel_scanout_needs_vtd_wa(struct drm_i915_private *dev_priv) |
2748 | { | |
2749 | #ifdef CONFIG_INTEL_IOMMU | |
2750 | if (INTEL_GEN(dev_priv) >= 6 && intel_iommu_gfx_mapped) | |
2751 | return true; | |
2752 | #endif | |
2753 | return false; | |
2754 | } | |
2755 | ||
1751fcf9 ML |
2756 | extern int i915_suspend_switcheroo(struct drm_device *dev, pm_message_t state); |
2757 | extern int i915_resume_switcheroo(struct drm_device *dev); | |
7c1c2871 | 2758 | |
c033666a | 2759 | int intel_sanitize_enable_ppgtt(struct drm_i915_private *dev_priv, |
351c3b53 | 2760 | int enable_ppgtt); |
0e4ca100 | 2761 | |
39df9190 CW |
2762 | bool intel_sanitize_semaphores(struct drm_i915_private *dev_priv, int value); |
2763 | ||
0673ad47 | 2764 | /* i915_drv.c */ |
d15d7538 ID |
2765 | void __printf(3, 4) |
2766 | __i915_printk(struct drm_i915_private *dev_priv, const char *level, | |
2767 | const char *fmt, ...); | |
2768 | ||
2769 | #define i915_report_error(dev_priv, fmt, ...) \ | |
2770 | __i915_printk(dev_priv, KERN_ERR, fmt, ##__VA_ARGS__) | |
2771 | ||
c43b5634 | 2772 | #ifdef CONFIG_COMPAT |
0d6aa60b DA |
2773 | extern long i915_compat_ioctl(struct file *filp, unsigned int cmd, |
2774 | unsigned long arg); | |
55edf41b JN |
2775 | #else |
2776 | #define i915_compat_ioctl NULL | |
c43b5634 | 2777 | #endif |
efab0698 JN |
2778 | extern const struct dev_pm_ops i915_pm_ops; |
2779 | ||
2780 | extern int i915_driver_load(struct pci_dev *pdev, | |
2781 | const struct pci_device_id *ent); | |
2782 | extern void i915_driver_unload(struct drm_device *dev); | |
dc97997a CW |
2783 | extern int intel_gpu_reset(struct drm_i915_private *dev_priv, u32 engine_mask); |
2784 | extern bool intel_has_gpu_reset(struct drm_i915_private *dev_priv); | |
780f262a | 2785 | extern void i915_reset(struct drm_i915_private *dev_priv); |
6b332fa2 | 2786 | extern int intel_guc_reset(struct drm_i915_private *dev_priv); |
fc0768ce | 2787 | extern void intel_engine_init_hangcheck(struct intel_engine_cs *engine); |
3ac168a7 | 2788 | extern void intel_hangcheck_init(struct drm_i915_private *dev_priv); |
7648fa99 JB |
2789 | extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv); |
2790 | extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv); | |
2791 | extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv); | |
2792 | extern void i915_update_gfx_val(struct drm_i915_private *dev_priv); | |
650ad970 | 2793 | int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool on); |
7648fa99 | 2794 | |
77913b39 | 2795 | /* intel_hotplug.c */ |
91d14251 TU |
2796 | void intel_hpd_irq_handler(struct drm_i915_private *dev_priv, |
2797 | u32 pin_mask, u32 long_mask); | |
77913b39 JN |
2798 | void intel_hpd_init(struct drm_i915_private *dev_priv); |
2799 | void intel_hpd_init_work(struct drm_i915_private *dev_priv); | |
2800 | void intel_hpd_cancel_work(struct drm_i915_private *dev_priv); | |
cc24fcdc | 2801 | bool intel_hpd_pin_to_port(enum hpd_pin pin, enum port *port); |
b236d7c8 L |
2802 | bool intel_hpd_disable(struct drm_i915_private *dev_priv, enum hpd_pin pin); |
2803 | void intel_hpd_enable(struct drm_i915_private *dev_priv, enum hpd_pin pin); | |
77913b39 | 2804 | |
1da177e4 | 2805 | /* i915_irq.c */ |
26a02b8f CW |
2806 | static inline void i915_queue_hangcheck(struct drm_i915_private *dev_priv) |
2807 | { | |
2808 | unsigned long delay; | |
2809 | ||
2810 | if (unlikely(!i915.enable_hangcheck)) | |
2811 | return; | |
2812 | ||
2813 | /* Don't continually defer the hangcheck so that it is always run at | |
2814 | * least once after work has been scheduled on any ring. Otherwise, | |
2815 | * we will ignore a hung ring if a second ring is kept busy. | |
2816 | */ | |
2817 | ||
2818 | delay = round_jiffies_up_relative(DRM_I915_HANGCHECK_JIFFIES); | |
2819 | queue_delayed_work(system_long_wq, | |
2820 | &dev_priv->gpu_error.hangcheck_work, delay); | |
2821 | } | |
2822 | ||
58174462 | 2823 | __printf(3, 4) |
c033666a CW |
2824 | void i915_handle_error(struct drm_i915_private *dev_priv, |
2825 | u32 engine_mask, | |
58174462 | 2826 | const char *fmt, ...); |
1da177e4 | 2827 | |
b963291c | 2828 | extern void intel_irq_init(struct drm_i915_private *dev_priv); |
2aeb7d3a DV |
2829 | int intel_irq_install(struct drm_i915_private *dev_priv); |
2830 | void intel_irq_uninstall(struct drm_i915_private *dev_priv); | |
907b28c5 | 2831 | |
dc97997a CW |
2832 | extern void intel_uncore_sanitize(struct drm_i915_private *dev_priv); |
2833 | extern void intel_uncore_early_sanitize(struct drm_i915_private *dev_priv, | |
10018603 | 2834 | bool restore_forcewake); |
dc97997a | 2835 | extern void intel_uncore_init(struct drm_i915_private *dev_priv); |
fc97618b | 2836 | extern bool intel_uncore_unclaimed_mmio(struct drm_i915_private *dev_priv); |
bc3b9346 | 2837 | extern bool intel_uncore_arm_unclaimed_mmio_detection(struct drm_i915_private *dev_priv); |
dc97997a CW |
2838 | extern void intel_uncore_fini(struct drm_i915_private *dev_priv); |
2839 | extern void intel_uncore_forcewake_reset(struct drm_i915_private *dev_priv, | |
2840 | bool restore); | |
48c1026a | 2841 | const char *intel_uncore_forcewake_domain_to_str(const enum forcewake_domain_id id); |
59bad947 | 2842 | void intel_uncore_forcewake_get(struct drm_i915_private *dev_priv, |
48c1026a | 2843 | enum forcewake_domains domains); |
59bad947 | 2844 | void intel_uncore_forcewake_put(struct drm_i915_private *dev_priv, |
48c1026a | 2845 | enum forcewake_domains domains); |
a6111f7b CW |
2846 | /* Like above but the caller must manage the uncore.lock itself. |
2847 | * Must be used with I915_READ_FW and friends. | |
2848 | */ | |
2849 | void intel_uncore_forcewake_get__locked(struct drm_i915_private *dev_priv, | |
2850 | enum forcewake_domains domains); | |
2851 | void intel_uncore_forcewake_put__locked(struct drm_i915_private *dev_priv, | |
2852 | enum forcewake_domains domains); | |
3accaf7e MK |
2853 | u64 intel_uncore_edram_size(struct drm_i915_private *dev_priv); |
2854 | ||
59bad947 | 2855 | void assert_forcewakes_inactive(struct drm_i915_private *dev_priv); |
0ad35fed | 2856 | |
1758b90e CW |
2857 | int intel_wait_for_register(struct drm_i915_private *dev_priv, |
2858 | i915_reg_t reg, | |
2859 | const u32 mask, | |
2860 | const u32 value, | |
2861 | const unsigned long timeout_ms); | |
2862 | int intel_wait_for_register_fw(struct drm_i915_private *dev_priv, | |
2863 | i915_reg_t reg, | |
2864 | const u32 mask, | |
2865 | const u32 value, | |
2866 | const unsigned long timeout_ms); | |
2867 | ||
0ad35fed ZW |
2868 | static inline bool intel_gvt_active(struct drm_i915_private *dev_priv) |
2869 | { | |
feddf6e8 | 2870 | return dev_priv->gvt; |
0ad35fed ZW |
2871 | } |
2872 | ||
c033666a | 2873 | static inline bool intel_vgpu_active(struct drm_i915_private *dev_priv) |
cf9d2890 | 2874 | { |
c033666a | 2875 | return dev_priv->vgpu.active; |
cf9d2890 | 2876 | } |
b1f14ad0 | 2877 | |
7c463586 | 2878 | void |
50227e1c | 2879 | i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe, |
755e9019 | 2880 | u32 status_mask); |
7c463586 KP |
2881 | |
2882 | void | |
50227e1c | 2883 | i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe, |
755e9019 | 2884 | u32 status_mask); |
7c463586 | 2885 | |
f8b79e58 ID |
2886 | void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv); |
2887 | void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv); | |
0706f17c EE |
2888 | void i915_hotplug_interrupt_update(struct drm_i915_private *dev_priv, |
2889 | uint32_t mask, | |
2890 | uint32_t bits); | |
fbdedaea VS |
2891 | void ilk_update_display_irq(struct drm_i915_private *dev_priv, |
2892 | uint32_t interrupt_mask, | |
2893 | uint32_t enabled_irq_mask); | |
2894 | static inline void | |
2895 | ilk_enable_display_irq(struct drm_i915_private *dev_priv, uint32_t bits) | |
2896 | { | |
2897 | ilk_update_display_irq(dev_priv, bits, bits); | |
2898 | } | |
2899 | static inline void | |
2900 | ilk_disable_display_irq(struct drm_i915_private *dev_priv, uint32_t bits) | |
2901 | { | |
2902 | ilk_update_display_irq(dev_priv, bits, 0); | |
2903 | } | |
013d3752 VS |
2904 | void bdw_update_pipe_irq(struct drm_i915_private *dev_priv, |
2905 | enum pipe pipe, | |
2906 | uint32_t interrupt_mask, | |
2907 | uint32_t enabled_irq_mask); | |
2908 | static inline void bdw_enable_pipe_irq(struct drm_i915_private *dev_priv, | |
2909 | enum pipe pipe, uint32_t bits) | |
2910 | { | |
2911 | bdw_update_pipe_irq(dev_priv, pipe, bits, bits); | |
2912 | } | |
2913 | static inline void bdw_disable_pipe_irq(struct drm_i915_private *dev_priv, | |
2914 | enum pipe pipe, uint32_t bits) | |
2915 | { | |
2916 | bdw_update_pipe_irq(dev_priv, pipe, bits, 0); | |
2917 | } | |
47339cd9 DV |
2918 | void ibx_display_interrupt_update(struct drm_i915_private *dev_priv, |
2919 | uint32_t interrupt_mask, | |
2920 | uint32_t enabled_irq_mask); | |
14443261 VS |
2921 | static inline void |
2922 | ibx_enable_display_interrupt(struct drm_i915_private *dev_priv, uint32_t bits) | |
2923 | { | |
2924 | ibx_display_interrupt_update(dev_priv, bits, bits); | |
2925 | } | |
2926 | static inline void | |
2927 | ibx_disable_display_interrupt(struct drm_i915_private *dev_priv, uint32_t bits) | |
2928 | { | |
2929 | ibx_display_interrupt_update(dev_priv, bits, 0); | |
2930 | } | |
2931 | ||
673a394b | 2932 | /* i915_gem.c */ |
673a394b EA |
2933 | int i915_gem_create_ioctl(struct drm_device *dev, void *data, |
2934 | struct drm_file *file_priv); | |
2935 | int i915_gem_pread_ioctl(struct drm_device *dev, void *data, | |
2936 | struct drm_file *file_priv); | |
2937 | int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data, | |
2938 | struct drm_file *file_priv); | |
2939 | int i915_gem_mmap_ioctl(struct drm_device *dev, void *data, | |
2940 | struct drm_file *file_priv); | |
de151cf6 JB |
2941 | int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data, |
2942 | struct drm_file *file_priv); | |
673a394b EA |
2943 | int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data, |
2944 | struct drm_file *file_priv); | |
2945 | int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data, | |
2946 | struct drm_file *file_priv); | |
2947 | int i915_gem_execbuffer(struct drm_device *dev, void *data, | |
2948 | struct drm_file *file_priv); | |
76446cac JB |
2949 | int i915_gem_execbuffer2(struct drm_device *dev, void *data, |
2950 | struct drm_file *file_priv); | |
673a394b EA |
2951 | int i915_gem_busy_ioctl(struct drm_device *dev, void *data, |
2952 | struct drm_file *file_priv); | |
199adf40 BW |
2953 | int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data, |
2954 | struct drm_file *file); | |
2955 | int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data, | |
2956 | struct drm_file *file); | |
673a394b EA |
2957 | int i915_gem_throttle_ioctl(struct drm_device *dev, void *data, |
2958 | struct drm_file *file_priv); | |
3ef94daa CW |
2959 | int i915_gem_madvise_ioctl(struct drm_device *dev, void *data, |
2960 | struct drm_file *file_priv); | |
673a394b EA |
2961 | int i915_gem_set_tiling(struct drm_device *dev, void *data, |
2962 | struct drm_file *file_priv); | |
2963 | int i915_gem_get_tiling(struct drm_device *dev, void *data, | |
2964 | struct drm_file *file_priv); | |
72778cb2 | 2965 | void i915_gem_init_userptr(struct drm_i915_private *dev_priv); |
5cc9ed4b CW |
2966 | int i915_gem_userptr_ioctl(struct drm_device *dev, void *data, |
2967 | struct drm_file *file); | |
5a125c3c EA |
2968 | int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data, |
2969 | struct drm_file *file_priv); | |
23ba4fd0 BW |
2970 | int i915_gem_wait_ioctl(struct drm_device *dev, void *data, |
2971 | struct drm_file *file_priv); | |
73cb9701 | 2972 | int i915_gem_load_init(struct drm_device *dev); |
d64aa096 | 2973 | void i915_gem_load_cleanup(struct drm_device *dev); |
40ae4e16 | 2974 | void i915_gem_load_init_fences(struct drm_i915_private *dev_priv); |
6a800eab | 2975 | int i915_gem_freeze(struct drm_i915_private *dev_priv); |
461fb99c CW |
2976 | int i915_gem_freeze_late(struct drm_i915_private *dev_priv); |
2977 | ||
42dcedd4 CW |
2978 | void *i915_gem_object_alloc(struct drm_device *dev); |
2979 | void i915_gem_object_free(struct drm_i915_gem_object *obj); | |
37e680a1 CW |
2980 | void i915_gem_object_init(struct drm_i915_gem_object *obj, |
2981 | const struct drm_i915_gem_object_ops *ops); | |
d37cd8a8 | 2982 | struct drm_i915_gem_object *i915_gem_object_create(struct drm_device *dev, |
b4bcbe2a | 2983 | u64 size); |
ea70299d DG |
2984 | struct drm_i915_gem_object *i915_gem_object_create_from_data( |
2985 | struct drm_device *dev, const void *data, size_t size); | |
b1f788c6 | 2986 | void i915_gem_close_object(struct drm_gem_object *gem, struct drm_file *file); |
673a394b | 2987 | void i915_gem_free_object(struct drm_gem_object *obj); |
42dcedd4 | 2988 | |
058d88c4 | 2989 | struct i915_vma * __must_check |
ec7adb6e JL |
2990 | i915_gem_object_ggtt_pin(struct drm_i915_gem_object *obj, |
2991 | const struct i915_ggtt_view *view, | |
91b2db6f | 2992 | u64 size, |
2ffffd0f CW |
2993 | u64 alignment, |
2994 | u64 flags); | |
fe14d5f4 | 2995 | |
aa653a68 | 2996 | int i915_gem_object_unbind(struct drm_i915_gem_object *obj); |
05394f39 | 2997 | void i915_gem_release_mmap(struct drm_i915_gem_object *obj); |
f787a5f5 | 2998 | |
7c108fd8 CW |
2999 | void i915_gem_runtime_suspend(struct drm_i915_private *dev_priv); |
3000 | ||
a4f5ea64 | 3001 | static inline int __sg_page_count(const struct scatterlist *sg) |
9da3da66 | 3002 | { |
ee286370 CW |
3003 | return sg->length >> PAGE_SHIFT; |
3004 | } | |
67d5a50c | 3005 | |
96d77634 CW |
3006 | struct scatterlist * |
3007 | i915_gem_object_get_sg(struct drm_i915_gem_object *obj, | |
3008 | unsigned int n, unsigned int *offset); | |
341be1cd | 3009 | |
96d77634 CW |
3010 | struct page * |
3011 | i915_gem_object_get_page(struct drm_i915_gem_object *obj, | |
3012 | unsigned int n); | |
67d5a50c | 3013 | |
96d77634 CW |
3014 | struct page * |
3015 | i915_gem_object_get_dirty_page(struct drm_i915_gem_object *obj, | |
3016 | unsigned int n); | |
67d5a50c | 3017 | |
96d77634 CW |
3018 | dma_addr_t |
3019 | i915_gem_object_get_dma_address(struct drm_i915_gem_object *obj, | |
3020 | unsigned long n); | |
ee286370 | 3021 | |
03ac84f1 CW |
3022 | void __i915_gem_object_set_pages(struct drm_i915_gem_object *obj, |
3023 | struct sg_table *pages); | |
a4f5ea64 CW |
3024 | int __i915_gem_object_get_pages(struct drm_i915_gem_object *obj); |
3025 | ||
3026 | static inline int __must_check | |
3027 | i915_gem_object_pin_pages(struct drm_i915_gem_object *obj) | |
3028 | { | |
1233e2db | 3029 | might_lock(&obj->mm.lock); |
a4f5ea64 | 3030 | |
1233e2db | 3031 | if (atomic_inc_not_zero(&obj->mm.pages_pin_count)) |
a4f5ea64 CW |
3032 | return 0; |
3033 | ||
3034 | return __i915_gem_object_get_pages(obj); | |
3035 | } | |
3036 | ||
3037 | static inline void | |
3038 | __i915_gem_object_pin_pages(struct drm_i915_gem_object *obj) | |
a5570178 | 3039 | { |
a4f5ea64 CW |
3040 | GEM_BUG_ON(!obj->mm.pages); |
3041 | ||
1233e2db | 3042 | atomic_inc(&obj->mm.pages_pin_count); |
a4f5ea64 CW |
3043 | } |
3044 | ||
3045 | static inline bool | |
3046 | i915_gem_object_has_pinned_pages(struct drm_i915_gem_object *obj) | |
3047 | { | |
1233e2db | 3048 | return atomic_read(&obj->mm.pages_pin_count); |
a4f5ea64 CW |
3049 | } |
3050 | ||
3051 | static inline void | |
3052 | __i915_gem_object_unpin_pages(struct drm_i915_gem_object *obj) | |
3053 | { | |
a4f5ea64 CW |
3054 | GEM_BUG_ON(!i915_gem_object_has_pinned_pages(obj)); |
3055 | GEM_BUG_ON(!obj->mm.pages); | |
3056 | ||
1233e2db CW |
3057 | atomic_dec(&obj->mm.pages_pin_count); |
3058 | GEM_BUG_ON(atomic_read(&obj->mm.pages_pin_count) < obj->bind_count); | |
a5570178 | 3059 | } |
0a798eb9 | 3060 | |
1233e2db CW |
3061 | static inline void |
3062 | i915_gem_object_unpin_pages(struct drm_i915_gem_object *obj) | |
a5570178 | 3063 | { |
a4f5ea64 | 3064 | __i915_gem_object_unpin_pages(obj); |
a5570178 CW |
3065 | } |
3066 | ||
548625ee CW |
3067 | enum i915_mm_subclass { /* lockdep subclass for obj->mm.lock */ |
3068 | I915_MM_NORMAL = 0, | |
3069 | I915_MM_SHRINKER | |
3070 | }; | |
3071 | ||
3072 | void __i915_gem_object_put_pages(struct drm_i915_gem_object *obj, | |
3073 | enum i915_mm_subclass subclass); | |
03ac84f1 | 3074 | void __i915_gem_object_invalidate(struct drm_i915_gem_object *obj); |
a4f5ea64 | 3075 | |
d31d7cb1 CW |
3076 | enum i915_map_type { |
3077 | I915_MAP_WB = 0, | |
3078 | I915_MAP_WC, | |
3079 | }; | |
3080 | ||
0a798eb9 CW |
3081 | /** |
3082 | * i915_gem_object_pin_map - return a contiguous mapping of the entire object | |
3083 | * @obj - the object to map into kernel address space | |
d31d7cb1 | 3084 | * @type - the type of mapping, used to select pgprot_t |
0a798eb9 CW |
3085 | * |
3086 | * Calls i915_gem_object_pin_pages() to prevent reaping of the object's | |
3087 | * pages and then returns a contiguous mapping of the backing storage into | |
d31d7cb1 CW |
3088 | * the kernel address space. Based on the @type of mapping, the PTE will be |
3089 | * set to either WriteBack or WriteCombine (via pgprot_t). | |
0a798eb9 | 3090 | * |
1233e2db CW |
3091 | * The caller is responsible for calling i915_gem_object_unpin_map() when the |
3092 | * mapping is no longer required. | |
0a798eb9 | 3093 | * |
8305216f DG |
3094 | * Returns the pointer through which to access the mapped object, or an |
3095 | * ERR_PTR() on error. | |
0a798eb9 | 3096 | */ |
d31d7cb1 CW |
3097 | void *__must_check i915_gem_object_pin_map(struct drm_i915_gem_object *obj, |
3098 | enum i915_map_type type); | |
0a798eb9 CW |
3099 | |
3100 | /** | |
3101 | * i915_gem_object_unpin_map - releases an earlier mapping | |
3102 | * @obj - the object to unmap | |
3103 | * | |
3104 | * After pinning the object and mapping its pages, once you are finished | |
3105 | * with your access, call i915_gem_object_unpin_map() to release the pin | |
3106 | * upon the mapping. Once the pin count reaches zero, that mapping may be | |
3107 | * removed. | |
0a798eb9 CW |
3108 | */ |
3109 | static inline void i915_gem_object_unpin_map(struct drm_i915_gem_object *obj) | |
3110 | { | |
0a798eb9 CW |
3111 | i915_gem_object_unpin_pages(obj); |
3112 | } | |
3113 | ||
43394c7d CW |
3114 | int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj, |
3115 | unsigned int *needs_clflush); | |
3116 | int i915_gem_obj_prepare_shmem_write(struct drm_i915_gem_object *obj, | |
3117 | unsigned int *needs_clflush); | |
3118 | #define CLFLUSH_BEFORE 0x1 | |
3119 | #define CLFLUSH_AFTER 0x2 | |
3120 | #define CLFLUSH_FLAGS (CLFLUSH_BEFORE | CLFLUSH_AFTER) | |
3121 | ||
3122 | static inline void | |
3123 | i915_gem_obj_finish_shmem_access(struct drm_i915_gem_object *obj) | |
3124 | { | |
3125 | i915_gem_object_unpin_pages(obj); | |
3126 | } | |
3127 | ||
54cf91dc | 3128 | int __must_check i915_mutex_lock_interruptible(struct drm_device *dev); |
e2d05a8b | 3129 | void i915_vma_move_to_active(struct i915_vma *vma, |
5cf3d280 CW |
3130 | struct drm_i915_gem_request *req, |
3131 | unsigned int flags); | |
ff72145b DA |
3132 | int i915_gem_dumb_create(struct drm_file *file_priv, |
3133 | struct drm_device *dev, | |
3134 | struct drm_mode_create_dumb *args); | |
da6b51d0 DA |
3135 | int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev, |
3136 | uint32_t handle, uint64_t *offset); | |
4cc69075 | 3137 | int i915_gem_mmap_gtt_version(void); |
85d1225e DG |
3138 | |
3139 | void i915_gem_track_fb(struct drm_i915_gem_object *old, | |
3140 | struct drm_i915_gem_object *new, | |
3141 | unsigned frontbuffer_bits); | |
3142 | ||
73cb9701 | 3143 | int __must_check i915_gem_set_global_seqno(struct drm_device *dev, u32 seqno); |
1690e1eb | 3144 | |
8d9fc7fd | 3145 | struct drm_i915_gem_request * |
0bc40be8 | 3146 | i915_gem_find_active_request(struct intel_engine_cs *engine); |
8d9fc7fd | 3147 | |
67d97da3 | 3148 | void i915_gem_retire_requests(struct drm_i915_private *dev_priv); |
84c33a64 | 3149 | |
1f83fee0 DV |
3150 | static inline bool i915_reset_in_progress(struct i915_gpu_error *error) |
3151 | { | |
8af29b0c | 3152 | return unlikely(test_bit(I915_RESET_IN_PROGRESS, &error->flags)); |
c19ae989 CW |
3153 | } |
3154 | ||
8af29b0c | 3155 | static inline bool i915_terminally_wedged(struct i915_gpu_error *error) |
c19ae989 | 3156 | { |
8af29b0c | 3157 | return unlikely(test_bit(I915_WEDGED, &error->flags)); |
1f83fee0 DV |
3158 | } |
3159 | ||
8af29b0c | 3160 | static inline bool i915_reset_in_progress_or_wedged(struct i915_gpu_error *error) |
1f83fee0 | 3161 | { |
8af29b0c | 3162 | return i915_reset_in_progress(error) | i915_terminally_wedged(error); |
2ac0f450 MK |
3163 | } |
3164 | ||
3165 | static inline u32 i915_reset_count(struct i915_gpu_error *error) | |
3166 | { | |
8af29b0c | 3167 | return READ_ONCE(error->reset_count); |
1f83fee0 | 3168 | } |
a71d8d94 | 3169 | |
821ed7df CW |
3170 | void i915_gem_reset(struct drm_i915_private *dev_priv); |
3171 | void i915_gem_set_wedged(struct drm_i915_private *dev_priv); | |
d0da48cf | 3172 | void i915_gem_clflush_object(struct drm_i915_gem_object *obj, bool force); |
1070a42b | 3173 | int __must_check i915_gem_init(struct drm_device *dev); |
f691e2f4 | 3174 | int __must_check i915_gem_init_hw(struct drm_device *dev); |
c6be607a | 3175 | void i915_gem_init_swizzling(struct drm_i915_private *dev_priv); |
117897f4 | 3176 | void i915_gem_cleanup_engines(struct drm_device *dev); |
dcff85c8 | 3177 | int __must_check i915_gem_wait_for_idle(struct drm_i915_private *dev_priv, |
ea746f36 | 3178 | unsigned int flags); |
45c5f202 | 3179 | int __must_check i915_gem_suspend(struct drm_device *dev); |
5ab57c70 | 3180 | void i915_gem_resume(struct drm_device *dev); |
de151cf6 | 3181 | int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf); |
e95433c7 CW |
3182 | int i915_gem_object_wait(struct drm_i915_gem_object *obj, |
3183 | unsigned int flags, | |
3184 | long timeout, | |
3185 | struct intel_rps_client *rps); | |
6b5e90f5 CW |
3186 | int i915_gem_object_wait_priority(struct drm_i915_gem_object *obj, |
3187 | unsigned int flags, | |
3188 | int priority); | |
3189 | #define I915_PRIORITY_DISPLAY I915_PRIORITY_MAX | |
3190 | ||
2e2f351d | 3191 | int __must_check |
2021746e CW |
3192 | i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, |
3193 | bool write); | |
3194 | int __must_check | |
dabdfe02 | 3195 | i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write); |
058d88c4 | 3196 | struct i915_vma * __must_check |
2da3b9b9 CW |
3197 | i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj, |
3198 | u32 alignment, | |
e6617330 | 3199 | const struct i915_ggtt_view *view); |
058d88c4 | 3200 | void i915_gem_object_unpin_from_display_plane(struct i915_vma *vma); |
00731155 | 3201 | int i915_gem_object_attach_phys(struct drm_i915_gem_object *obj, |
6eeefaf3 | 3202 | int align); |
b29c19b6 | 3203 | int i915_gem_open(struct drm_device *dev, struct drm_file *file); |
05394f39 | 3204 | void i915_gem_release(struct drm_device *dev, struct drm_file *file); |
673a394b | 3205 | |
a9f1481f CW |
3206 | u64 i915_gem_get_ggtt_size(struct drm_i915_private *dev_priv, u64 size, |
3207 | int tiling_mode); | |
3208 | u64 i915_gem_get_ggtt_alignment(struct drm_i915_private *dev_priv, u64 size, | |
ad1a7d20 | 3209 | int tiling_mode, bool fenced); |
467cffba | 3210 | |
e4ffd173 CW |
3211 | int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj, |
3212 | enum i915_cache_level cache_level); | |
3213 | ||
1286ff73 DV |
3214 | struct drm_gem_object *i915_gem_prime_import(struct drm_device *dev, |
3215 | struct dma_buf *dma_buf); | |
3216 | ||
3217 | struct dma_buf *i915_gem_prime_export(struct drm_device *dev, | |
3218 | struct drm_gem_object *gem_obj, int flags); | |
3219 | ||
fe14d5f4 | 3220 | struct i915_vma * |
ec7adb6e | 3221 | i915_gem_obj_to_vma(struct drm_i915_gem_object *obj, |
058d88c4 CW |
3222 | struct i915_address_space *vm, |
3223 | const struct i915_ggtt_view *view); | |
fe14d5f4 | 3224 | |
accfef2e BW |
3225 | struct i915_vma * |
3226 | i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object *obj, | |
058d88c4 CW |
3227 | struct i915_address_space *vm, |
3228 | const struct i915_ggtt_view *view); | |
5c2abbea | 3229 | |
841cd773 DV |
3230 | static inline struct i915_hw_ppgtt * |
3231 | i915_vm_to_ppgtt(struct i915_address_space *vm) | |
3232 | { | |
841cd773 DV |
3233 | return container_of(vm, struct i915_hw_ppgtt, base); |
3234 | } | |
3235 | ||
058d88c4 CW |
3236 | static inline struct i915_vma * |
3237 | i915_gem_object_to_ggtt(struct drm_i915_gem_object *obj, | |
3238 | const struct i915_ggtt_view *view) | |
a70a3148 | 3239 | { |
058d88c4 | 3240 | return i915_gem_obj_to_vma(obj, &to_i915(obj->base.dev)->ggtt.base, view); |
a70a3148 BW |
3241 | } |
3242 | ||
058d88c4 CW |
3243 | static inline unsigned long |
3244 | i915_gem_object_ggtt_offset(struct drm_i915_gem_object *o, | |
3245 | const struct i915_ggtt_view *view) | |
e6617330 | 3246 | { |
bde13ebd | 3247 | return i915_ggtt_offset(i915_gem_object_to_ggtt(o, view)); |
e6617330 | 3248 | } |
b287110e | 3249 | |
b42fe9ca | 3250 | /* i915_gem_fence_reg.c */ |
49ef5294 CW |
3251 | int __must_check i915_vma_get_fence(struct i915_vma *vma); |
3252 | int __must_check i915_vma_put_fence(struct i915_vma *vma); | |
3253 | ||
4362f4f6 | 3254 | void i915_gem_restore_fences(struct drm_i915_private *dev_priv); |
41a36b73 | 3255 | |
4362f4f6 | 3256 | void i915_gem_detect_bit_6_swizzle(struct drm_i915_private *dev_priv); |
03ac84f1 CW |
3257 | void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj, |
3258 | struct sg_table *pages); | |
3259 | void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj, | |
3260 | struct sg_table *pages); | |
7f96ecaf | 3261 | |
254f965c | 3262 | /* i915_gem_context.c */ |
8245be31 | 3263 | int __must_check i915_gem_context_init(struct drm_device *dev); |
b2e862d0 | 3264 | void i915_gem_context_lost(struct drm_i915_private *dev_priv); |
254f965c | 3265 | void i915_gem_context_fini(struct drm_device *dev); |
e422b888 | 3266 | int i915_gem_context_open(struct drm_device *dev, struct drm_file *file); |
254f965c | 3267 | void i915_gem_context_close(struct drm_device *dev, struct drm_file *file); |
ba01cc93 | 3268 | int i915_switch_context(struct drm_i915_gem_request *req); |
945657b4 | 3269 | int i915_gem_switch_to_kernel_context(struct drm_i915_private *dev_priv); |
07c9a21a CW |
3270 | struct i915_vma * |
3271 | i915_gem_context_pin_legacy(struct i915_gem_context *ctx, | |
3272 | unsigned int flags); | |
dce3271b | 3273 | void i915_gem_context_free(struct kref *ctx_ref); |
c8c35799 ZW |
3274 | struct i915_gem_context * |
3275 | i915_gem_context_create_gvt(struct drm_device *dev); | |
ca585b5d CW |
3276 | |
3277 | static inline struct i915_gem_context * | |
3278 | i915_gem_context_lookup(struct drm_i915_file_private *file_priv, u32 id) | |
3279 | { | |
3280 | struct i915_gem_context *ctx; | |
3281 | ||
091387c1 | 3282 | lockdep_assert_held(&file_priv->dev_priv->drm.struct_mutex); |
ca585b5d CW |
3283 | |
3284 | ctx = idr_find(&file_priv->context_idr, id); | |
3285 | if (!ctx) | |
3286 | return ERR_PTR(-ENOENT); | |
3287 | ||
3288 | return ctx; | |
3289 | } | |
3290 | ||
9a6feaf0 CW |
3291 | static inline struct i915_gem_context * |
3292 | i915_gem_context_get(struct i915_gem_context *ctx) | |
dce3271b | 3293 | { |
691e6415 | 3294 | kref_get(&ctx->ref); |
9a6feaf0 | 3295 | return ctx; |
dce3271b MK |
3296 | } |
3297 | ||
9a6feaf0 | 3298 | static inline void i915_gem_context_put(struct i915_gem_context *ctx) |
dce3271b | 3299 | { |
091387c1 | 3300 | lockdep_assert_held(&ctx->i915->drm.struct_mutex); |
691e6415 | 3301 | kref_put(&ctx->ref, i915_gem_context_free); |
dce3271b MK |
3302 | } |
3303 | ||
80b204bc CW |
3304 | static inline struct intel_timeline * |
3305 | i915_gem_context_lookup_timeline(struct i915_gem_context *ctx, | |
3306 | struct intel_engine_cs *engine) | |
3307 | { | |
3308 | struct i915_address_space *vm; | |
3309 | ||
3310 | vm = ctx->ppgtt ? &ctx->ppgtt->base : &ctx->i915->ggtt.base; | |
3311 | return &vm->timeline.engine[engine->id]; | |
3312 | } | |
3313 | ||
e2efd130 | 3314 | static inline bool i915_gem_context_is_default(const struct i915_gem_context *c) |
3fac8978 | 3315 | { |
821d66dd | 3316 | return c->user_handle == DEFAULT_CONTEXT_HANDLE; |
3fac8978 MK |
3317 | } |
3318 | ||
84624813 BW |
3319 | int i915_gem_context_create_ioctl(struct drm_device *dev, void *data, |
3320 | struct drm_file *file); | |
3321 | int i915_gem_context_destroy_ioctl(struct drm_device *dev, void *data, | |
3322 | struct drm_file *file); | |
c9dc0f35 CW |
3323 | int i915_gem_context_getparam_ioctl(struct drm_device *dev, void *data, |
3324 | struct drm_file *file_priv); | |
3325 | int i915_gem_context_setparam_ioctl(struct drm_device *dev, void *data, | |
3326 | struct drm_file *file_priv); | |
d538704b CW |
3327 | int i915_gem_context_reset_stats_ioctl(struct drm_device *dev, void *data, |
3328 | struct drm_file *file); | |
1286ff73 | 3329 | |
eec688e1 RB |
3330 | int i915_perf_open_ioctl(struct drm_device *dev, void *data, |
3331 | struct drm_file *file); | |
3332 | ||
679845ed | 3333 | /* i915_gem_evict.c */ |
e522ac23 | 3334 | int __must_check i915_gem_evict_something(struct i915_address_space *vm, |
2ffffd0f | 3335 | u64 min_size, u64 alignment, |
679845ed | 3336 | unsigned cache_level, |
2ffffd0f | 3337 | u64 start, u64 end, |
1ec9e26d | 3338 | unsigned flags); |
506a8e87 | 3339 | int __must_check i915_gem_evict_for_vma(struct i915_vma *target); |
679845ed | 3340 | int i915_gem_evict_vm(struct i915_address_space *vm, bool do_idle); |
1d2a314c | 3341 | |
0260c420 | 3342 | /* belongs in i915_gem_gtt.h */ |
c033666a | 3343 | static inline void i915_gem_chipset_flush(struct drm_i915_private *dev_priv) |
e76e9aeb | 3344 | { |
600f4368 | 3345 | wmb(); |
c033666a | 3346 | if (INTEL_GEN(dev_priv) < 6) |
e76e9aeb BW |
3347 | intel_gtt_chipset_flush(); |
3348 | } | |
246cbfb5 | 3349 | |
9797fbfb | 3350 | /* i915_gem_stolen.c */ |
d713fd49 PZ |
3351 | int i915_gem_stolen_insert_node(struct drm_i915_private *dev_priv, |
3352 | struct drm_mm_node *node, u64 size, | |
3353 | unsigned alignment); | |
a9da512b PZ |
3354 | int i915_gem_stolen_insert_node_in_range(struct drm_i915_private *dev_priv, |
3355 | struct drm_mm_node *node, u64 size, | |
3356 | unsigned alignment, u64 start, | |
3357 | u64 end); | |
d713fd49 PZ |
3358 | void i915_gem_stolen_remove_node(struct drm_i915_private *dev_priv, |
3359 | struct drm_mm_node *node); | |
7ace3d30 | 3360 | int i915_gem_init_stolen(struct drm_i915_private *dev_priv); |
9797fbfb | 3361 | void i915_gem_cleanup_stolen(struct drm_device *dev); |
0104fdbb CW |
3362 | struct drm_i915_gem_object * |
3363 | i915_gem_object_create_stolen(struct drm_device *dev, u32 size); | |
866d12b4 CW |
3364 | struct drm_i915_gem_object * |
3365 | i915_gem_object_create_stolen_for_preallocated(struct drm_device *dev, | |
3366 | u32 stolen_offset, | |
3367 | u32 gtt_offset, | |
3368 | u32 size); | |
9797fbfb | 3369 | |
920cf419 CW |
3370 | /* i915_gem_internal.c */ |
3371 | struct drm_i915_gem_object * | |
3372 | i915_gem_object_create_internal(struct drm_i915_private *dev_priv, | |
3373 | unsigned int size); | |
3374 | ||
be6a0376 DV |
3375 | /* i915_gem_shrinker.c */ |
3376 | unsigned long i915_gem_shrink(struct drm_i915_private *dev_priv, | |
14387540 | 3377 | unsigned long target, |
be6a0376 DV |
3378 | unsigned flags); |
3379 | #define I915_SHRINK_PURGEABLE 0x1 | |
3380 | #define I915_SHRINK_UNBOUND 0x2 | |
3381 | #define I915_SHRINK_BOUND 0x4 | |
5763ff04 | 3382 | #define I915_SHRINK_ACTIVE 0x8 |
eae2c43b | 3383 | #define I915_SHRINK_VMAPS 0x10 |
be6a0376 DV |
3384 | unsigned long i915_gem_shrink_all(struct drm_i915_private *dev_priv); |
3385 | void i915_gem_shrinker_init(struct drm_i915_private *dev_priv); | |
a8a40589 | 3386 | void i915_gem_shrinker_cleanup(struct drm_i915_private *dev_priv); |
be6a0376 DV |
3387 | |
3388 | ||
673a394b | 3389 | /* i915_gem_tiling.c */ |
2c1792a1 | 3390 | static inline bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj) |
e9b73c67 | 3391 | { |
091387c1 | 3392 | struct drm_i915_private *dev_priv = to_i915(obj->base.dev); |
e9b73c67 CW |
3393 | |
3394 | return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 && | |
3e510a8e | 3395 | i915_gem_object_is_tiled(obj); |
e9b73c67 CW |
3396 | } |
3397 | ||
2017263e | 3398 | /* i915_debugfs.c */ |
f8c168fa | 3399 | #ifdef CONFIG_DEBUG_FS |
1dac891c CW |
3400 | int i915_debugfs_register(struct drm_i915_private *dev_priv); |
3401 | void i915_debugfs_unregister(struct drm_i915_private *dev_priv); | |
249e87de | 3402 | int i915_debugfs_connector_add(struct drm_connector *connector); |
36cdd013 | 3403 | void intel_display_crc_init(struct drm_i915_private *dev_priv); |
07144428 | 3404 | #else |
8d35acba CW |
3405 | static inline int i915_debugfs_register(struct drm_i915_private *dev_priv) {return 0;} |
3406 | static inline void i915_debugfs_unregister(struct drm_i915_private *dev_priv) {} | |
101057fa DV |
3407 | static inline int i915_debugfs_connector_add(struct drm_connector *connector) |
3408 | { return 0; } | |
ce5e2ac1 | 3409 | static inline void intel_display_crc_init(struct drm_i915_private *dev_priv) {} |
07144428 | 3410 | #endif |
84734a04 MK |
3411 | |
3412 | /* i915_gpu_error.c */ | |
98a2f411 CW |
3413 | #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR) |
3414 | ||
edc3d884 MK |
3415 | __printf(2, 3) |
3416 | void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...); | |
fc16b48b MK |
3417 | int i915_error_state_to_str(struct drm_i915_error_state_buf *estr, |
3418 | const struct i915_error_state_file_priv *error); | |
4dc955f7 | 3419 | int i915_error_state_buf_init(struct drm_i915_error_state_buf *eb, |
0a4cd7c8 | 3420 | struct drm_i915_private *i915, |
4dc955f7 MK |
3421 | size_t count, loff_t pos); |
3422 | static inline void i915_error_state_buf_release( | |
3423 | struct drm_i915_error_state_buf *eb) | |
3424 | { | |
3425 | kfree(eb->buf); | |
3426 | } | |
c033666a CW |
3427 | void i915_capture_error_state(struct drm_i915_private *dev_priv, |
3428 | u32 engine_mask, | |
58174462 | 3429 | const char *error_msg); |
84734a04 MK |
3430 | void i915_error_state_get(struct drm_device *dev, |
3431 | struct i915_error_state_file_priv *error_priv); | |
3432 | void i915_error_state_put(struct i915_error_state_file_priv *error_priv); | |
3433 | void i915_destroy_error_state(struct drm_device *dev); | |
3434 | ||
98a2f411 CW |
3435 | #else |
3436 | ||
3437 | static inline void i915_capture_error_state(struct drm_i915_private *dev_priv, | |
3438 | u32 engine_mask, | |
3439 | const char *error_msg) | |
3440 | { | |
3441 | } | |
3442 | ||
3443 | static inline void i915_destroy_error_state(struct drm_device *dev) | |
3444 | { | |
3445 | } | |
3446 | ||
3447 | #endif | |
3448 | ||
0a4cd7c8 | 3449 | const char *i915_cache_level_str(struct drm_i915_private *i915, int type); |
2017263e | 3450 | |
351e3db2 | 3451 | /* i915_cmd_parser.c */ |
1ca3712c | 3452 | int i915_cmd_parser_get_version(struct drm_i915_private *dev_priv); |
7756e454 | 3453 | void intel_engine_init_cmd_parser(struct intel_engine_cs *engine); |
33a051a5 | 3454 | void intel_engine_cleanup_cmd_parser(struct intel_engine_cs *engine); |
33a051a5 CW |
3455 | int intel_engine_cmd_parser(struct intel_engine_cs *engine, |
3456 | struct drm_i915_gem_object *batch_obj, | |
3457 | struct drm_i915_gem_object *shadow_batch_obj, | |
3458 | u32 batch_start_offset, | |
3459 | u32 batch_len, | |
3460 | bool is_master); | |
351e3db2 | 3461 | |
eec688e1 RB |
3462 | /* i915_perf.c */ |
3463 | extern void i915_perf_init(struct drm_i915_private *dev_priv); | |
3464 | extern void i915_perf_fini(struct drm_i915_private *dev_priv); | |
442b8c06 RB |
3465 | extern void i915_perf_register(struct drm_i915_private *dev_priv); |
3466 | extern void i915_perf_unregister(struct drm_i915_private *dev_priv); | |
eec688e1 | 3467 | |
317c35d1 JB |
3468 | /* i915_suspend.c */ |
3469 | extern int i915_save_state(struct drm_device *dev); | |
3470 | extern int i915_restore_state(struct drm_device *dev); | |
0a3e67a4 | 3471 | |
0136db58 | 3472 | /* i915_sysfs.c */ |
694c2828 DW |
3473 | void i915_setup_sysfs(struct drm_i915_private *dev_priv); |
3474 | void i915_teardown_sysfs(struct drm_i915_private *dev_priv); | |
0136db58 | 3475 | |
f899fc64 CW |
3476 | /* intel_i2c.c */ |
3477 | extern int intel_setup_gmbus(struct drm_device *dev); | |
3478 | extern void intel_teardown_gmbus(struct drm_device *dev); | |
88ac7939 JN |
3479 | extern bool intel_gmbus_is_valid_pin(struct drm_i915_private *dev_priv, |
3480 | unsigned int pin); | |
3bd7d909 | 3481 | |
0184df46 JN |
3482 | extern struct i2c_adapter * |
3483 | intel_gmbus_get_adapter(struct drm_i915_private *dev_priv, unsigned int pin); | |
e957d772 CW |
3484 | extern void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed); |
3485 | extern void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit); | |
8f375e10 | 3486 | static inline bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter) |
b8232e90 CW |
3487 | { |
3488 | return container_of(adapter, struct intel_gmbus, adapter)->force_bit; | |
3489 | } | |
f899fc64 CW |
3490 | extern void intel_i2c_reset(struct drm_device *dev); |
3491 | ||
8b8e1a89 | 3492 | /* intel_bios.c */ |
98f3a1dc | 3493 | int intel_bios_init(struct drm_i915_private *dev_priv); |
f0067a31 | 3494 | bool intel_bios_is_valid_vbt(const void *buf, size_t size); |
3bdd14d5 | 3495 | bool intel_bios_is_tv_present(struct drm_i915_private *dev_priv); |
5a69d13d | 3496 | bool intel_bios_is_lvds_present(struct drm_i915_private *dev_priv, u8 *i2c_pin); |
22f35042 | 3497 | bool intel_bios_is_port_present(struct drm_i915_private *dev_priv, enum port port); |
951d9efe | 3498 | bool intel_bios_is_port_edp(struct drm_i915_private *dev_priv, enum port port); |
d6199256 | 3499 | bool intel_bios_is_port_dp_dual_mode(struct drm_i915_private *dev_priv, enum port port); |
7137aec1 | 3500 | bool intel_bios_is_dsi_present(struct drm_i915_private *dev_priv, enum port *port); |
d252bf68 SS |
3501 | bool intel_bios_is_port_hpd_inverted(struct drm_i915_private *dev_priv, |
3502 | enum port port); | |
6389dd83 SS |
3503 | bool intel_bios_is_lspcon_present(struct drm_i915_private *dev_priv, |
3504 | enum port port); | |
3505 | ||
8b8e1a89 | 3506 | |
3b617967 | 3507 | /* intel_opregion.c */ |
44834a67 | 3508 | #ifdef CONFIG_ACPI |
6f9f4b7a | 3509 | extern int intel_opregion_setup(struct drm_i915_private *dev_priv); |
03d92e47 CW |
3510 | extern void intel_opregion_register(struct drm_i915_private *dev_priv); |
3511 | extern void intel_opregion_unregister(struct drm_i915_private *dev_priv); | |
91d14251 | 3512 | extern void intel_opregion_asle_intr(struct drm_i915_private *dev_priv); |
9c4b0a68 JN |
3513 | extern int intel_opregion_notify_encoder(struct intel_encoder *intel_encoder, |
3514 | bool enable); | |
6f9f4b7a | 3515 | extern int intel_opregion_notify_adapter(struct drm_i915_private *dev_priv, |
ecbc5cf3 | 3516 | pci_power_t state); |
6f9f4b7a | 3517 | extern int intel_opregion_get_panel_type(struct drm_i915_private *dev_priv); |
65e082c9 | 3518 | #else |
6f9f4b7a | 3519 | static inline int intel_opregion_setup(struct drm_i915_private *dev) { return 0; } |
bdaa2dfb RD |
3520 | static inline void intel_opregion_register(struct drm_i915_private *dev_priv) { } |
3521 | static inline void intel_opregion_unregister(struct drm_i915_private *dev_priv) { } | |
91d14251 TU |
3522 | static inline void intel_opregion_asle_intr(struct drm_i915_private *dev_priv) |
3523 | { | |
3524 | } | |
9c4b0a68 JN |
3525 | static inline int |
3526 | intel_opregion_notify_encoder(struct intel_encoder *intel_encoder, bool enable) | |
3527 | { | |
3528 | return 0; | |
3529 | } | |
ecbc5cf3 | 3530 | static inline int |
6f9f4b7a | 3531 | intel_opregion_notify_adapter(struct drm_i915_private *dev, pci_power_t state) |
ecbc5cf3 JN |
3532 | { |
3533 | return 0; | |
3534 | } | |
6f9f4b7a | 3535 | static inline int intel_opregion_get_panel_type(struct drm_i915_private *dev) |
a0562819 VS |
3536 | { |
3537 | return -ENODEV; | |
3538 | } | |
65e082c9 | 3539 | #endif |
8ee1c3db | 3540 | |
723bfd70 JB |
3541 | /* intel_acpi.c */ |
3542 | #ifdef CONFIG_ACPI | |
3543 | extern void intel_register_dsm_handler(void); | |
3544 | extern void intel_unregister_dsm_handler(void); | |
3545 | #else | |
3546 | static inline void intel_register_dsm_handler(void) { return; } | |
3547 | static inline void intel_unregister_dsm_handler(void) { return; } | |
3548 | #endif /* CONFIG_ACPI */ | |
3549 | ||
94b4f3ba CW |
3550 | /* intel_device_info.c */ |
3551 | static inline struct intel_device_info * | |
3552 | mkwrite_device_info(struct drm_i915_private *dev_priv) | |
3553 | { | |
3554 | return (struct intel_device_info *)&dev_priv->info; | |
3555 | } | |
3556 | ||
3557 | void intel_device_info_runtime_init(struct drm_i915_private *dev_priv); | |
3558 | void intel_device_info_dump(struct drm_i915_private *dev_priv); | |
3559 | ||
79e53945 | 3560 | /* modesetting */ |
f817586c | 3561 | extern void intel_modeset_init_hw(struct drm_device *dev); |
b079bd17 | 3562 | extern int intel_modeset_init(struct drm_device *dev); |
2c7111db | 3563 | extern void intel_modeset_gem_init(struct drm_device *dev); |
79e53945 | 3564 | extern void intel_modeset_cleanup(struct drm_device *dev); |
1ebaa0b9 | 3565 | extern int intel_connector_register(struct drm_connector *); |
c191eca1 | 3566 | extern void intel_connector_unregister(struct drm_connector *); |
6315b5d3 TU |
3567 | extern int intel_modeset_vga_set_state(struct drm_i915_private *dev_priv, |
3568 | bool state); | |
043e9bda | 3569 | extern void intel_display_resume(struct drm_device *dev); |
29b74b7f TU |
3570 | extern void i915_redisable_vga(struct drm_i915_private *dev_priv); |
3571 | extern void i915_redisable_vga_power_on(struct drm_i915_private *dev_priv); | |
91d14251 | 3572 | extern bool ironlake_set_drps(struct drm_i915_private *dev_priv, u8 val); |
c39055b0 | 3573 | extern void intel_init_pch_refclk(struct drm_i915_private *dev_priv); |
dc97997a | 3574 | extern void intel_set_rps(struct drm_i915_private *dev_priv, u8 val); |
5209b1f4 ID |
3575 | extern void intel_set_memory_cxsr(struct drm_i915_private *dev_priv, |
3576 | bool enable); | |
3bad0781 | 3577 | |
c0c7babc BW |
3578 | int i915_reg_read_ioctl(struct drm_device *dev, void *data, |
3579 | struct drm_file *file); | |
575155a9 | 3580 | |
6ef3d427 | 3581 | /* overlay */ |
c033666a CW |
3582 | extern struct intel_overlay_error_state * |
3583 | intel_overlay_capture_error_state(struct drm_i915_private *dev_priv); | |
edc3d884 MK |
3584 | extern void intel_overlay_print_error_state(struct drm_i915_error_state_buf *e, |
3585 | struct intel_overlay_error_state *error); | |
c4a1d9e4 | 3586 | |
c033666a CW |
3587 | extern struct intel_display_error_state * |
3588 | intel_display_capture_error_state(struct drm_i915_private *dev_priv); | |
edc3d884 | 3589 | extern void intel_display_print_error_state(struct drm_i915_error_state_buf *e, |
5f56d5f9 | 3590 | struct drm_i915_private *dev_priv, |
c4a1d9e4 | 3591 | struct intel_display_error_state *error); |
6ef3d427 | 3592 | |
151a49d0 TR |
3593 | int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val); |
3594 | int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u32 mbox, u32 val); | |
59de0813 JN |
3595 | |
3596 | /* intel_sideband.c */ | |
707b6e3d D |
3597 | u32 vlv_punit_read(struct drm_i915_private *dev_priv, u32 addr); |
3598 | void vlv_punit_write(struct drm_i915_private *dev_priv, u32 addr, u32 val); | |
64936258 | 3599 | u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr); |
dfb19ed2 D |
3600 | u32 vlv_iosf_sb_read(struct drm_i915_private *dev_priv, u8 port, u32 reg); |
3601 | void vlv_iosf_sb_write(struct drm_i915_private *dev_priv, u8 port, u32 reg, u32 val); | |
e9f882a3 JN |
3602 | u32 vlv_cck_read(struct drm_i915_private *dev_priv, u32 reg); |
3603 | void vlv_cck_write(struct drm_i915_private *dev_priv, u32 reg, u32 val); | |
3604 | u32 vlv_ccu_read(struct drm_i915_private *dev_priv, u32 reg); | |
3605 | void vlv_ccu_write(struct drm_i915_private *dev_priv, u32 reg, u32 val); | |
f3419158 JB |
3606 | u32 vlv_bunit_read(struct drm_i915_private *dev_priv, u32 reg); |
3607 | void vlv_bunit_write(struct drm_i915_private *dev_priv, u32 reg, u32 val); | |
5e69f97f CML |
3608 | u32 vlv_dpio_read(struct drm_i915_private *dev_priv, enum pipe pipe, int reg); |
3609 | void vlv_dpio_write(struct drm_i915_private *dev_priv, enum pipe pipe, int reg, u32 val); | |
59de0813 JN |
3610 | u32 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg, |
3611 | enum intel_sbi_destination destination); | |
3612 | void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value, | |
3613 | enum intel_sbi_destination destination); | |
e9fe51c6 SK |
3614 | u32 vlv_flisdsi_read(struct drm_i915_private *dev_priv, u32 reg); |
3615 | void vlv_flisdsi_write(struct drm_i915_private *dev_priv, u32 reg, u32 val); | |
0a073b84 | 3616 | |
b7fa22d8 | 3617 | /* intel_dpio_phy.c */ |
ed37892e ACO |
3618 | void bxt_port_to_phy_channel(enum port port, |
3619 | enum dpio_phy *phy, enum dpio_channel *ch); | |
b6e08203 ACO |
3620 | void bxt_ddi_phy_set_signal_level(struct drm_i915_private *dev_priv, |
3621 | enum port port, u32 margin, u32 scale, | |
3622 | u32 enable, u32 deemphasis); | |
47a6bc61 ACO |
3623 | void bxt_ddi_phy_init(struct drm_i915_private *dev_priv, enum dpio_phy phy); |
3624 | void bxt_ddi_phy_uninit(struct drm_i915_private *dev_priv, enum dpio_phy phy); | |
3625 | bool bxt_ddi_phy_is_enabled(struct drm_i915_private *dev_priv, | |
3626 | enum dpio_phy phy); | |
3627 | bool bxt_ddi_phy_verify_state(struct drm_i915_private *dev_priv, | |
3628 | enum dpio_phy phy); | |
3629 | uint8_t bxt_ddi_phy_calc_lane_lat_optim_mask(struct intel_encoder *encoder, | |
3630 | uint8_t lane_count); | |
3631 | void bxt_ddi_phy_set_lane_optim_mask(struct intel_encoder *encoder, | |
3632 | uint8_t lane_lat_optim_mask); | |
3633 | uint8_t bxt_ddi_phy_get_lane_lat_optim_mask(struct intel_encoder *encoder); | |
3634 | ||
b7fa22d8 ACO |
3635 | void chv_set_phy_signal_level(struct intel_encoder *encoder, |
3636 | u32 deemph_reg_value, u32 margin_reg_value, | |
3637 | bool uniq_trans_scale); | |
844b2f9a ACO |
3638 | void chv_data_lane_soft_reset(struct intel_encoder *encoder, |
3639 | bool reset); | |
419b1b7a | 3640 | void chv_phy_pre_pll_enable(struct intel_encoder *encoder); |
e7d2a717 ACO |
3641 | void chv_phy_pre_encoder_enable(struct intel_encoder *encoder); |
3642 | void chv_phy_release_cl2_override(struct intel_encoder *encoder); | |
204970b5 | 3643 | void chv_phy_post_pll_disable(struct intel_encoder *encoder); |
b7fa22d8 | 3644 | |
53d98725 ACO |
3645 | void vlv_set_phy_signal_level(struct intel_encoder *encoder, |
3646 | u32 demph_reg_value, u32 preemph_reg_value, | |
3647 | u32 uniqtranscale_reg_value, u32 tx3_demph); | |
6da2e616 | 3648 | void vlv_phy_pre_pll_enable(struct intel_encoder *encoder); |
5f68c275 | 3649 | void vlv_phy_pre_encoder_enable(struct intel_encoder *encoder); |
0f572ebe | 3650 | void vlv_phy_reset_lanes(struct intel_encoder *encoder); |
53d98725 | 3651 | |
616bc820 VS |
3652 | int intel_gpu_freq(struct drm_i915_private *dev_priv, int val); |
3653 | int intel_freq_opcode(struct drm_i915_private *dev_priv, int val); | |
c8d9a590 | 3654 | |
0b274481 BW |
3655 | #define I915_READ8(reg) dev_priv->uncore.funcs.mmio_readb(dev_priv, (reg), true) |
3656 | #define I915_WRITE8(reg, val) dev_priv->uncore.funcs.mmio_writeb(dev_priv, (reg), (val), true) | |
3657 | ||
3658 | #define I915_READ16(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), true) | |
3659 | #define I915_WRITE16(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), true) | |
3660 | #define I915_READ16_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), false) | |
3661 | #define I915_WRITE16_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), false) | |
3662 | ||
3663 | #define I915_READ(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), true) | |
3664 | #define I915_WRITE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), true) | |
3665 | #define I915_READ_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), false) | |
3666 | #define I915_WRITE_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), false) | |
3667 | ||
698b3135 CW |
3668 | /* Be very careful with read/write 64-bit values. On 32-bit machines, they |
3669 | * will be implemented using 2 32-bit writes in an arbitrary order with | |
3670 | * an arbitrary delay between them. This can cause the hardware to | |
3671 | * act upon the intermediate value, possibly leading to corruption and | |
b18c1bb4 CW |
3672 | * machine death. For this reason we do not support I915_WRITE64, or |
3673 | * dev_priv->uncore.funcs.mmio_writeq. | |
3674 | * | |
3675 | * When reading a 64-bit value as two 32-bit values, the delay may cause | |
3676 | * the two reads to mismatch, e.g. a timestamp overflowing. Also note that | |
3677 | * occasionally a 64-bit register does not actualy support a full readq | |
3678 | * and must be read using two 32-bit reads. | |
3679 | * | |
3680 | * You have been warned. | |
698b3135 | 3681 | */ |
0b274481 | 3682 | #define I915_READ64(reg) dev_priv->uncore.funcs.mmio_readq(dev_priv, (reg), true) |
cae5852d | 3683 | |
50877445 | 3684 | #define I915_READ64_2x32(lower_reg, upper_reg) ({ \ |
acd29f7b CW |
3685 | u32 upper, lower, old_upper, loop = 0; \ |
3686 | upper = I915_READ(upper_reg); \ | |
ee0a227b | 3687 | do { \ |
acd29f7b | 3688 | old_upper = upper; \ |
ee0a227b | 3689 | lower = I915_READ(lower_reg); \ |
acd29f7b CW |
3690 | upper = I915_READ(upper_reg); \ |
3691 | } while (upper != old_upper && loop++ < 2); \ | |
ee0a227b | 3692 | (u64)upper << 32 | lower; }) |
50877445 | 3693 | |
cae5852d ZN |
3694 | #define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg) |
3695 | #define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg) | |
3696 | ||
75aa3f63 VS |
3697 | #define __raw_read(x, s) \ |
3698 | static inline uint##x##_t __raw_i915_read##x(struct drm_i915_private *dev_priv, \ | |
f0f59a00 | 3699 | i915_reg_t reg) \ |
75aa3f63 | 3700 | { \ |
f0f59a00 | 3701 | return read##s(dev_priv->regs + i915_mmio_reg_offset(reg)); \ |
75aa3f63 VS |
3702 | } |
3703 | ||
3704 | #define __raw_write(x, s) \ | |
3705 | static inline void __raw_i915_write##x(struct drm_i915_private *dev_priv, \ | |
f0f59a00 | 3706 | i915_reg_t reg, uint##x##_t val) \ |
75aa3f63 | 3707 | { \ |
f0f59a00 | 3708 | write##s(val, dev_priv->regs + i915_mmio_reg_offset(reg)); \ |
75aa3f63 VS |
3709 | } |
3710 | __raw_read(8, b) | |
3711 | __raw_read(16, w) | |
3712 | __raw_read(32, l) | |
3713 | __raw_read(64, q) | |
3714 | ||
3715 | __raw_write(8, b) | |
3716 | __raw_write(16, w) | |
3717 | __raw_write(32, l) | |
3718 | __raw_write(64, q) | |
3719 | ||
3720 | #undef __raw_read | |
3721 | #undef __raw_write | |
3722 | ||
a6111f7b | 3723 | /* These are untraced mmio-accessors that are only valid to be used inside |
aafee2eb | 3724 | * critical sections, such as inside IRQ handlers, where forcewake is explicitly |
a6111f7b | 3725 | * controlled. |
aafee2eb | 3726 | * |
a6111f7b | 3727 | * Think twice, and think again, before using these. |
aafee2eb AH |
3728 | * |
3729 | * As an example, these accessors can possibly be used between: | |
3730 | * | |
3731 | * spin_lock_irq(&dev_priv->uncore.lock); | |
3732 | * intel_uncore_forcewake_get__locked(); | |
3733 | * | |
3734 | * and | |
3735 | * | |
3736 | * intel_uncore_forcewake_put__locked(); | |
3737 | * spin_unlock_irq(&dev_priv->uncore.lock); | |
3738 | * | |
3739 | * | |
3740 | * Note: some registers may not need forcewake held, so | |
3741 | * intel_uncore_forcewake_{get,put} can be omitted, see | |
3742 | * intel_uncore_forcewake_for_reg(). | |
3743 | * | |
3744 | * Certain architectures will die if the same cacheline is concurrently accessed | |
3745 | * by different clients (e.g. on Ivybridge). Access to registers should | |
3746 | * therefore generally be serialised, by either the dev_priv->uncore.lock or | |
3747 | * a more localised lock guarding all access to that bank of registers. | |
a6111f7b | 3748 | */ |
75aa3f63 VS |
3749 | #define I915_READ_FW(reg__) __raw_i915_read32(dev_priv, (reg__)) |
3750 | #define I915_WRITE_FW(reg__, val__) __raw_i915_write32(dev_priv, (reg__), (val__)) | |
76f8421f | 3751 | #define I915_WRITE64_FW(reg__, val__) __raw_i915_write64(dev_priv, (reg__), (val__)) |
a6111f7b CW |
3752 | #define POSTING_READ_FW(reg__) (void)I915_READ_FW(reg__) |
3753 | ||
55bc60db VS |
3754 | /* "Broadcast RGB" property */ |
3755 | #define INTEL_BROADCAST_RGB_AUTO 0 | |
3756 | #define INTEL_BROADCAST_RGB_FULL 1 | |
3757 | #define INTEL_BROADCAST_RGB_LIMITED 2 | |
ba4f01a3 | 3758 | |
920a14b2 | 3759 | static inline i915_reg_t i915_vgacntrl_reg(struct drm_i915_private *dev_priv) |
766aa1c4 | 3760 | { |
920a14b2 | 3761 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) |
766aa1c4 | 3762 | return VLV_VGACNTRL; |
920a14b2 | 3763 | else if (INTEL_GEN(dev_priv) >= 5) |
92e23b99 | 3764 | return CPU_VGACNTRL; |
766aa1c4 VS |
3765 | else |
3766 | return VGACNTRL; | |
3767 | } | |
3768 | ||
df97729f ID |
3769 | static inline unsigned long msecs_to_jiffies_timeout(const unsigned int m) |
3770 | { | |
3771 | unsigned long j = msecs_to_jiffies(m); | |
3772 | ||
3773 | return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1); | |
3774 | } | |
3775 | ||
7bd0e226 DV |
3776 | static inline unsigned long nsecs_to_jiffies_timeout(const u64 n) |
3777 | { | |
3778 | return min_t(u64, MAX_JIFFY_OFFSET, nsecs_to_jiffies64(n) + 1); | |
3779 | } | |
3780 | ||
df97729f ID |
3781 | static inline unsigned long |
3782 | timespec_to_jiffies_timeout(const struct timespec *value) | |
3783 | { | |
3784 | unsigned long j = timespec_to_jiffies(value); | |
3785 | ||
3786 | return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1); | |
3787 | } | |
3788 | ||
dce56b3c PZ |
3789 | /* |
3790 | * If you need to wait X milliseconds between events A and B, but event B | |
3791 | * doesn't happen exactly after event A, you record the timestamp (jiffies) of | |
3792 | * when event A happened, then just before event B you call this function and | |
3793 | * pass the timestamp as the first argument, and X as the second argument. | |
3794 | */ | |
3795 | static inline void | |
3796 | wait_remaining_ms_from_jiffies(unsigned long timestamp_jiffies, int to_wait_ms) | |
3797 | { | |
ec5e0cfb | 3798 | unsigned long target_jiffies, tmp_jiffies, remaining_jiffies; |
dce56b3c PZ |
3799 | |
3800 | /* | |
3801 | * Don't re-read the value of "jiffies" every time since it may change | |
3802 | * behind our back and break the math. | |
3803 | */ | |
3804 | tmp_jiffies = jiffies; | |
3805 | target_jiffies = timestamp_jiffies + | |
3806 | msecs_to_jiffies_timeout(to_wait_ms); | |
3807 | ||
3808 | if (time_after(target_jiffies, tmp_jiffies)) { | |
ec5e0cfb ID |
3809 | remaining_jiffies = target_jiffies - tmp_jiffies; |
3810 | while (remaining_jiffies) | |
3811 | remaining_jiffies = | |
3812 | schedule_timeout_uninterruptible(remaining_jiffies); | |
dce56b3c PZ |
3813 | } |
3814 | } | |
221fe799 CW |
3815 | |
3816 | static inline bool | |
3817 | __i915_request_irq_complete(struct drm_i915_gem_request *req) | |
688e6c72 | 3818 | { |
f69a02c9 CW |
3819 | struct intel_engine_cs *engine = req->engine; |
3820 | ||
7ec2c73b CW |
3821 | /* Before we do the heavier coherent read of the seqno, |
3822 | * check the value (hopefully) in the CPU cacheline. | |
3823 | */ | |
65e4760e | 3824 | if (__i915_gem_request_completed(req)) |
7ec2c73b CW |
3825 | return true; |
3826 | ||
688e6c72 CW |
3827 | /* Ensure our read of the seqno is coherent so that we |
3828 | * do not "miss an interrupt" (i.e. if this is the last | |
3829 | * request and the seqno write from the GPU is not visible | |
3830 | * by the time the interrupt fires, we will see that the | |
3831 | * request is incomplete and go back to sleep awaiting | |
3832 | * another interrupt that will never come.) | |
3833 | * | |
3834 | * Strictly, we only need to do this once after an interrupt, | |
3835 | * but it is easier and safer to do it every time the waiter | |
3836 | * is woken. | |
3837 | */ | |
3d5564e9 | 3838 | if (engine->irq_seqno_barrier && |
dbd6ef29 | 3839 | rcu_access_pointer(engine->breadcrumbs.irq_seqno_bh) == current && |
aca34b6e | 3840 | cmpxchg_relaxed(&engine->breadcrumbs.irq_posted, 1, 0)) { |
99fe4a5f CW |
3841 | struct task_struct *tsk; |
3842 | ||
3d5564e9 CW |
3843 | /* The ordering of irq_posted versus applying the barrier |
3844 | * is crucial. The clearing of the current irq_posted must | |
3845 | * be visible before we perform the barrier operation, | |
3846 | * such that if a subsequent interrupt arrives, irq_posted | |
3847 | * is reasserted and our task rewoken (which causes us to | |
3848 | * do another __i915_request_irq_complete() immediately | |
3849 | * and reapply the barrier). Conversely, if the clear | |
3850 | * occurs after the barrier, then an interrupt that arrived | |
3851 | * whilst we waited on the barrier would not trigger a | |
3852 | * barrier on the next pass, and the read may not see the | |
3853 | * seqno update. | |
3854 | */ | |
f69a02c9 | 3855 | engine->irq_seqno_barrier(engine); |
99fe4a5f CW |
3856 | |
3857 | /* If we consume the irq, but we are no longer the bottom-half, | |
3858 | * the real bottom-half may not have serialised their own | |
3859 | * seqno check with the irq-barrier (i.e. may have inspected | |
3860 | * the seqno before we believe it coherent since they see | |
3861 | * irq_posted == false but we are still running). | |
3862 | */ | |
3863 | rcu_read_lock(); | |
dbd6ef29 | 3864 | tsk = rcu_dereference(engine->breadcrumbs.irq_seqno_bh); |
99fe4a5f CW |
3865 | if (tsk && tsk != current) |
3866 | /* Note that if the bottom-half is changed as we | |
3867 | * are sending the wake-up, the new bottom-half will | |
3868 | * be woken by whomever made the change. We only have | |
3869 | * to worry about when we steal the irq-posted for | |
3870 | * ourself. | |
3871 | */ | |
3872 | wake_up_process(tsk); | |
3873 | rcu_read_unlock(); | |
3874 | ||
65e4760e | 3875 | if (__i915_gem_request_completed(req)) |
7ec2c73b CW |
3876 | return true; |
3877 | } | |
688e6c72 | 3878 | |
688e6c72 CW |
3879 | return false; |
3880 | } | |
3881 | ||
0b1de5d5 CW |
3882 | void i915_memcpy_init_early(struct drm_i915_private *dev_priv); |
3883 | bool i915_memcpy_from_wc(void *dst, const void *src, unsigned long len); | |
3884 | ||
c58305af CW |
3885 | /* i915_mm.c */ |
3886 | int remap_io_mapping(struct vm_area_struct *vma, | |
3887 | unsigned long addr, unsigned long pfn, unsigned long size, | |
3888 | struct io_mapping *iomap); | |
3889 | ||
4b30cb23 CW |
3890 | #define ptr_mask_bits(ptr) ({ \ |
3891 | unsigned long __v = (unsigned long)(ptr); \ | |
3892 | (typeof(ptr))(__v & PAGE_MASK); \ | |
3893 | }) | |
3894 | ||
d31d7cb1 CW |
3895 | #define ptr_unpack_bits(ptr, bits) ({ \ |
3896 | unsigned long __v = (unsigned long)(ptr); \ | |
3897 | (bits) = __v & ~PAGE_MASK; \ | |
3898 | (typeof(ptr))(__v & PAGE_MASK); \ | |
3899 | }) | |
3900 | ||
3901 | #define ptr_pack_bits(ptr, bits) \ | |
3902 | ((typeof(ptr))((unsigned long)(ptr) | (bits))) | |
3903 | ||
78ef2d9a CW |
3904 | #define fetch_and_zero(ptr) ({ \ |
3905 | typeof(*ptr) __T = *(ptr); \ | |
3906 | *(ptr) = (typeof(*ptr))0; \ | |
3907 | __T; \ | |
3908 | }) | |
3909 | ||
1da177e4 | 3910 | #endif |