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Commit | Line | Data |
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673a394b EA |
1 | /* |
2 | * Copyright © 2008 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | * | |
26 | */ | |
27 | ||
760285e7 | 28 | #include <drm/drmP.h> |
0de23977 | 29 | #include <drm/drm_vma_manager.h> |
760285e7 | 30 | #include <drm/i915_drm.h> |
673a394b | 31 | #include "i915_drv.h" |
1c5d22f7 | 32 | #include "i915_trace.h" |
652c393a | 33 | #include "intel_drv.h" |
2cfcd32a | 34 | #include <linux/oom.h> |
5949eac4 | 35 | #include <linux/shmem_fs.h> |
5a0e3ad6 | 36 | #include <linux/slab.h> |
673a394b | 37 | #include <linux/swap.h> |
79e53945 | 38 | #include <linux/pci.h> |
1286ff73 | 39 | #include <linux/dma-buf.h> |
673a394b | 40 | |
05394f39 | 41 | static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj); |
2c22569b CW |
42 | static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj, |
43 | bool force); | |
07fe0b12 | 44 | static __must_check int |
23f54483 BW |
45 | i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj, |
46 | bool readonly); | |
c8725f3d CW |
47 | static void |
48 | i915_gem_object_retire(struct drm_i915_gem_object *obj); | |
49 | ||
61050808 CW |
50 | static void i915_gem_write_fence(struct drm_device *dev, int reg, |
51 | struct drm_i915_gem_object *obj); | |
52 | static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj, | |
53 | struct drm_i915_fence_reg *fence, | |
54 | bool enable); | |
55 | ||
ceabbba5 | 56 | static unsigned long i915_gem_shrinker_count(struct shrinker *shrinker, |
7dc19d5a | 57 | struct shrink_control *sc); |
ceabbba5 | 58 | static unsigned long i915_gem_shrinker_scan(struct shrinker *shrinker, |
7dc19d5a | 59 | struct shrink_control *sc); |
2cfcd32a CW |
60 | static int i915_gem_shrinker_oom(struct notifier_block *nb, |
61 | unsigned long event, | |
62 | void *ptr); | |
d9973b43 | 63 | static unsigned long i915_gem_shrink_all(struct drm_i915_private *dev_priv); |
31169714 | 64 | |
c76ce038 CW |
65 | static bool cpu_cache_is_coherent(struct drm_device *dev, |
66 | enum i915_cache_level level) | |
67 | { | |
68 | return HAS_LLC(dev) || level != I915_CACHE_NONE; | |
69 | } | |
70 | ||
2c22569b CW |
71 | static bool cpu_write_needs_clflush(struct drm_i915_gem_object *obj) |
72 | { | |
73 | if (!cpu_cache_is_coherent(obj->base.dev, obj->cache_level)) | |
74 | return true; | |
75 | ||
76 | return obj->pin_display; | |
77 | } | |
78 | ||
61050808 CW |
79 | static inline void i915_gem_object_fence_lost(struct drm_i915_gem_object *obj) |
80 | { | |
81 | if (obj->tiling_mode) | |
82 | i915_gem_release_mmap(obj); | |
83 | ||
84 | /* As we do not have an associated fence register, we will force | |
85 | * a tiling change if we ever need to acquire one. | |
86 | */ | |
5d82e3e6 | 87 | obj->fence_dirty = false; |
61050808 CW |
88 | obj->fence_reg = I915_FENCE_REG_NONE; |
89 | } | |
90 | ||
73aa808f CW |
91 | /* some bookkeeping */ |
92 | static void i915_gem_info_add_obj(struct drm_i915_private *dev_priv, | |
93 | size_t size) | |
94 | { | |
c20e8355 | 95 | spin_lock(&dev_priv->mm.object_stat_lock); |
73aa808f CW |
96 | dev_priv->mm.object_count++; |
97 | dev_priv->mm.object_memory += size; | |
c20e8355 | 98 | spin_unlock(&dev_priv->mm.object_stat_lock); |
73aa808f CW |
99 | } |
100 | ||
101 | static void i915_gem_info_remove_obj(struct drm_i915_private *dev_priv, | |
102 | size_t size) | |
103 | { | |
c20e8355 | 104 | spin_lock(&dev_priv->mm.object_stat_lock); |
73aa808f CW |
105 | dev_priv->mm.object_count--; |
106 | dev_priv->mm.object_memory -= size; | |
c20e8355 | 107 | spin_unlock(&dev_priv->mm.object_stat_lock); |
73aa808f CW |
108 | } |
109 | ||
21dd3734 | 110 | static int |
33196ded | 111 | i915_gem_wait_for_error(struct i915_gpu_error *error) |
30dbf0c0 | 112 | { |
30dbf0c0 CW |
113 | int ret; |
114 | ||
7abb690a DV |
115 | #define EXIT_COND (!i915_reset_in_progress(error) || \ |
116 | i915_terminally_wedged(error)) | |
1f83fee0 | 117 | if (EXIT_COND) |
30dbf0c0 CW |
118 | return 0; |
119 | ||
0a6759c6 DV |
120 | /* |
121 | * Only wait 10 seconds for the gpu reset to complete to avoid hanging | |
122 | * userspace. If it takes that long something really bad is going on and | |
123 | * we should simply try to bail out and fail as gracefully as possible. | |
124 | */ | |
1f83fee0 DV |
125 | ret = wait_event_interruptible_timeout(error->reset_queue, |
126 | EXIT_COND, | |
127 | 10*HZ); | |
0a6759c6 DV |
128 | if (ret == 0) { |
129 | DRM_ERROR("Timed out waiting for the gpu reset to complete\n"); | |
130 | return -EIO; | |
131 | } else if (ret < 0) { | |
30dbf0c0 | 132 | return ret; |
0a6759c6 | 133 | } |
1f83fee0 | 134 | #undef EXIT_COND |
30dbf0c0 | 135 | |
21dd3734 | 136 | return 0; |
30dbf0c0 CW |
137 | } |
138 | ||
54cf91dc | 139 | int i915_mutex_lock_interruptible(struct drm_device *dev) |
76c1dec1 | 140 | { |
33196ded | 141 | struct drm_i915_private *dev_priv = dev->dev_private; |
76c1dec1 CW |
142 | int ret; |
143 | ||
33196ded | 144 | ret = i915_gem_wait_for_error(&dev_priv->gpu_error); |
76c1dec1 CW |
145 | if (ret) |
146 | return ret; | |
147 | ||
148 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
149 | if (ret) | |
150 | return ret; | |
151 | ||
23bc5982 | 152 | WARN_ON(i915_verify_lists(dev)); |
76c1dec1 CW |
153 | return 0; |
154 | } | |
30dbf0c0 | 155 | |
7d1c4804 | 156 | static inline bool |
05394f39 | 157 | i915_gem_object_is_inactive(struct drm_i915_gem_object *obj) |
7d1c4804 | 158 | { |
9843877d | 159 | return i915_gem_obj_bound_any(obj) && !obj->active; |
7d1c4804 CW |
160 | } |
161 | ||
79e53945 JB |
162 | int |
163 | i915_gem_init_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 164 | struct drm_file *file) |
79e53945 | 165 | { |
93d18799 | 166 | struct drm_i915_private *dev_priv = dev->dev_private; |
79e53945 | 167 | struct drm_i915_gem_init *args = data; |
2021746e | 168 | |
7bb6fb8d DV |
169 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
170 | return -ENODEV; | |
171 | ||
2021746e CW |
172 | if (args->gtt_start >= args->gtt_end || |
173 | (args->gtt_end | args->gtt_start) & (PAGE_SIZE - 1)) | |
174 | return -EINVAL; | |
79e53945 | 175 | |
f534bc0b DV |
176 | /* GEM with user mode setting was never supported on ilk and later. */ |
177 | if (INTEL_INFO(dev)->gen >= 5) | |
178 | return -ENODEV; | |
179 | ||
79e53945 | 180 | mutex_lock(&dev->struct_mutex); |
d7e5008f BW |
181 | i915_gem_setup_global_gtt(dev, args->gtt_start, args->gtt_end, |
182 | args->gtt_end); | |
93d18799 | 183 | dev_priv->gtt.mappable_end = args->gtt_end; |
673a394b EA |
184 | mutex_unlock(&dev->struct_mutex); |
185 | ||
2021746e | 186 | return 0; |
673a394b EA |
187 | } |
188 | ||
5a125c3c EA |
189 | int |
190 | i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 191 | struct drm_file *file) |
5a125c3c | 192 | { |
73aa808f | 193 | struct drm_i915_private *dev_priv = dev->dev_private; |
5a125c3c | 194 | struct drm_i915_gem_get_aperture *args = data; |
6299f992 CW |
195 | struct drm_i915_gem_object *obj; |
196 | size_t pinned; | |
5a125c3c | 197 | |
6299f992 | 198 | pinned = 0; |
73aa808f | 199 | mutex_lock(&dev->struct_mutex); |
35c20a60 | 200 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) |
d7f46fc4 | 201 | if (i915_gem_obj_is_pinned(obj)) |
f343c5f6 | 202 | pinned += i915_gem_obj_ggtt_size(obj); |
73aa808f | 203 | mutex_unlock(&dev->struct_mutex); |
5a125c3c | 204 | |
853ba5d2 | 205 | args->aper_size = dev_priv->gtt.base.total; |
0206e353 | 206 | args->aper_available_size = args->aper_size - pinned; |
6299f992 | 207 | |
5a125c3c EA |
208 | return 0; |
209 | } | |
210 | ||
00731155 CW |
211 | static void i915_gem_object_detach_phys(struct drm_i915_gem_object *obj) |
212 | { | |
213 | drm_dma_handle_t *phys = obj->phys_handle; | |
214 | ||
215 | if (!phys) | |
216 | return; | |
217 | ||
218 | if (obj->madv == I915_MADV_WILLNEED) { | |
219 | struct address_space *mapping = file_inode(obj->base.filp)->i_mapping; | |
220 | char *vaddr = phys->vaddr; | |
221 | int i; | |
222 | ||
223 | for (i = 0; i < obj->base.size / PAGE_SIZE; i++) { | |
224 | struct page *page = shmem_read_mapping_page(mapping, i); | |
225 | if (!IS_ERR(page)) { | |
226 | char *dst = kmap_atomic(page); | |
227 | memcpy(dst, vaddr, PAGE_SIZE); | |
228 | drm_clflush_virt_range(dst, PAGE_SIZE); | |
229 | kunmap_atomic(dst); | |
230 | ||
231 | set_page_dirty(page); | |
232 | mark_page_accessed(page); | |
233 | page_cache_release(page); | |
234 | } | |
235 | vaddr += PAGE_SIZE; | |
236 | } | |
237 | i915_gem_chipset_flush(obj->base.dev); | |
238 | } | |
239 | ||
240 | #ifdef CONFIG_X86 | |
241 | set_memory_wb((unsigned long)phys->vaddr, phys->size / PAGE_SIZE); | |
242 | #endif | |
243 | drm_pci_free(obj->base.dev, phys); | |
244 | obj->phys_handle = NULL; | |
245 | } | |
246 | ||
247 | int | |
248 | i915_gem_object_attach_phys(struct drm_i915_gem_object *obj, | |
249 | int align) | |
250 | { | |
251 | drm_dma_handle_t *phys; | |
252 | struct address_space *mapping; | |
253 | char *vaddr; | |
254 | int i; | |
255 | ||
256 | if (obj->phys_handle) { | |
257 | if ((unsigned long)obj->phys_handle->vaddr & (align -1)) | |
258 | return -EBUSY; | |
259 | ||
260 | return 0; | |
261 | } | |
262 | ||
263 | if (obj->madv != I915_MADV_WILLNEED) | |
264 | return -EFAULT; | |
265 | ||
266 | if (obj->base.filp == NULL) | |
267 | return -EINVAL; | |
268 | ||
269 | /* create a new object */ | |
270 | phys = drm_pci_alloc(obj->base.dev, obj->base.size, align); | |
271 | if (!phys) | |
272 | return -ENOMEM; | |
273 | ||
274 | vaddr = phys->vaddr; | |
275 | #ifdef CONFIG_X86 | |
276 | set_memory_wc((unsigned long)vaddr, phys->size / PAGE_SIZE); | |
277 | #endif | |
278 | mapping = file_inode(obj->base.filp)->i_mapping; | |
279 | for (i = 0; i < obj->base.size / PAGE_SIZE; i++) { | |
280 | struct page *page; | |
281 | char *src; | |
282 | ||
283 | page = shmem_read_mapping_page(mapping, i); | |
284 | if (IS_ERR(page)) { | |
285 | #ifdef CONFIG_X86 | |
286 | set_memory_wb((unsigned long)phys->vaddr, phys->size / PAGE_SIZE); | |
287 | #endif | |
288 | drm_pci_free(obj->base.dev, phys); | |
289 | return PTR_ERR(page); | |
290 | } | |
291 | ||
292 | src = kmap_atomic(page); | |
293 | memcpy(vaddr, src, PAGE_SIZE); | |
294 | kunmap_atomic(src); | |
295 | ||
296 | mark_page_accessed(page); | |
297 | page_cache_release(page); | |
298 | ||
299 | vaddr += PAGE_SIZE; | |
300 | } | |
301 | ||
302 | obj->phys_handle = phys; | |
303 | return 0; | |
304 | } | |
305 | ||
306 | static int | |
307 | i915_gem_phys_pwrite(struct drm_i915_gem_object *obj, | |
308 | struct drm_i915_gem_pwrite *args, | |
309 | struct drm_file *file_priv) | |
310 | { | |
311 | struct drm_device *dev = obj->base.dev; | |
312 | void *vaddr = obj->phys_handle->vaddr + args->offset; | |
313 | char __user *user_data = to_user_ptr(args->data_ptr); | |
314 | ||
315 | if (__copy_from_user_inatomic_nocache(vaddr, user_data, args->size)) { | |
316 | unsigned long unwritten; | |
317 | ||
318 | /* The physical object once assigned is fixed for the lifetime | |
319 | * of the obj, so we can safely drop the lock and continue | |
320 | * to access vaddr. | |
321 | */ | |
322 | mutex_unlock(&dev->struct_mutex); | |
323 | unwritten = copy_from_user(vaddr, user_data, args->size); | |
324 | mutex_lock(&dev->struct_mutex); | |
325 | if (unwritten) | |
326 | return -EFAULT; | |
327 | } | |
328 | ||
329 | i915_gem_chipset_flush(dev); | |
330 | return 0; | |
331 | } | |
332 | ||
42dcedd4 CW |
333 | void *i915_gem_object_alloc(struct drm_device *dev) |
334 | { | |
335 | struct drm_i915_private *dev_priv = dev->dev_private; | |
fac15c10 | 336 | return kmem_cache_zalloc(dev_priv->slab, GFP_KERNEL); |
42dcedd4 CW |
337 | } |
338 | ||
339 | void i915_gem_object_free(struct drm_i915_gem_object *obj) | |
340 | { | |
341 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; | |
342 | kmem_cache_free(dev_priv->slab, obj); | |
343 | } | |
344 | ||
ff72145b DA |
345 | static int |
346 | i915_gem_create(struct drm_file *file, | |
347 | struct drm_device *dev, | |
348 | uint64_t size, | |
349 | uint32_t *handle_p) | |
673a394b | 350 | { |
05394f39 | 351 | struct drm_i915_gem_object *obj; |
a1a2d1d3 PP |
352 | int ret; |
353 | u32 handle; | |
673a394b | 354 | |
ff72145b | 355 | size = roundup(size, PAGE_SIZE); |
8ffc0246 CW |
356 | if (size == 0) |
357 | return -EINVAL; | |
673a394b EA |
358 | |
359 | /* Allocate the new object */ | |
ff72145b | 360 | obj = i915_gem_alloc_object(dev, size); |
673a394b EA |
361 | if (obj == NULL) |
362 | return -ENOMEM; | |
363 | ||
05394f39 | 364 | ret = drm_gem_handle_create(file, &obj->base, &handle); |
202f2fef | 365 | /* drop reference from allocate - handle holds it now */ |
d861e338 DV |
366 | drm_gem_object_unreference_unlocked(&obj->base); |
367 | if (ret) | |
368 | return ret; | |
202f2fef | 369 | |
ff72145b | 370 | *handle_p = handle; |
673a394b EA |
371 | return 0; |
372 | } | |
373 | ||
ff72145b DA |
374 | int |
375 | i915_gem_dumb_create(struct drm_file *file, | |
376 | struct drm_device *dev, | |
377 | struct drm_mode_create_dumb *args) | |
378 | { | |
379 | /* have to work out size/pitch and return them */ | |
de45eaf7 | 380 | args->pitch = ALIGN(args->width * DIV_ROUND_UP(args->bpp, 8), 64); |
ff72145b DA |
381 | args->size = args->pitch * args->height; |
382 | return i915_gem_create(file, dev, | |
383 | args->size, &args->handle); | |
384 | } | |
385 | ||
ff72145b DA |
386 | /** |
387 | * Creates a new mm object and returns a handle to it. | |
388 | */ | |
389 | int | |
390 | i915_gem_create_ioctl(struct drm_device *dev, void *data, | |
391 | struct drm_file *file) | |
392 | { | |
393 | struct drm_i915_gem_create *args = data; | |
63ed2cb2 | 394 | |
ff72145b DA |
395 | return i915_gem_create(file, dev, |
396 | args->size, &args->handle); | |
397 | } | |
398 | ||
8461d226 DV |
399 | static inline int |
400 | __copy_to_user_swizzled(char __user *cpu_vaddr, | |
401 | const char *gpu_vaddr, int gpu_offset, | |
402 | int length) | |
403 | { | |
404 | int ret, cpu_offset = 0; | |
405 | ||
406 | while (length > 0) { | |
407 | int cacheline_end = ALIGN(gpu_offset + 1, 64); | |
408 | int this_length = min(cacheline_end - gpu_offset, length); | |
409 | int swizzled_gpu_offset = gpu_offset ^ 64; | |
410 | ||
411 | ret = __copy_to_user(cpu_vaddr + cpu_offset, | |
412 | gpu_vaddr + swizzled_gpu_offset, | |
413 | this_length); | |
414 | if (ret) | |
415 | return ret + length; | |
416 | ||
417 | cpu_offset += this_length; | |
418 | gpu_offset += this_length; | |
419 | length -= this_length; | |
420 | } | |
421 | ||
422 | return 0; | |
423 | } | |
424 | ||
8c59967c | 425 | static inline int |
4f0c7cfb BW |
426 | __copy_from_user_swizzled(char *gpu_vaddr, int gpu_offset, |
427 | const char __user *cpu_vaddr, | |
8c59967c DV |
428 | int length) |
429 | { | |
430 | int ret, cpu_offset = 0; | |
431 | ||
432 | while (length > 0) { | |
433 | int cacheline_end = ALIGN(gpu_offset + 1, 64); | |
434 | int this_length = min(cacheline_end - gpu_offset, length); | |
435 | int swizzled_gpu_offset = gpu_offset ^ 64; | |
436 | ||
437 | ret = __copy_from_user(gpu_vaddr + swizzled_gpu_offset, | |
438 | cpu_vaddr + cpu_offset, | |
439 | this_length); | |
440 | if (ret) | |
441 | return ret + length; | |
442 | ||
443 | cpu_offset += this_length; | |
444 | gpu_offset += this_length; | |
445 | length -= this_length; | |
446 | } | |
447 | ||
448 | return 0; | |
449 | } | |
450 | ||
4c914c0c BV |
451 | /* |
452 | * Pins the specified object's pages and synchronizes the object with | |
453 | * GPU accesses. Sets needs_clflush to non-zero if the caller should | |
454 | * flush the object from the CPU cache. | |
455 | */ | |
456 | int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj, | |
457 | int *needs_clflush) | |
458 | { | |
459 | int ret; | |
460 | ||
461 | *needs_clflush = 0; | |
462 | ||
463 | if (!obj->base.filp) | |
464 | return -EINVAL; | |
465 | ||
466 | if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU)) { | |
467 | /* If we're not in the cpu read domain, set ourself into the gtt | |
468 | * read domain and manually flush cachelines (if required). This | |
469 | * optimizes for the case when the gpu will dirty the data | |
470 | * anyway again before the next pread happens. */ | |
471 | *needs_clflush = !cpu_cache_is_coherent(obj->base.dev, | |
472 | obj->cache_level); | |
473 | ret = i915_gem_object_wait_rendering(obj, true); | |
474 | if (ret) | |
475 | return ret; | |
c8725f3d CW |
476 | |
477 | i915_gem_object_retire(obj); | |
4c914c0c BV |
478 | } |
479 | ||
480 | ret = i915_gem_object_get_pages(obj); | |
481 | if (ret) | |
482 | return ret; | |
483 | ||
484 | i915_gem_object_pin_pages(obj); | |
485 | ||
486 | return ret; | |
487 | } | |
488 | ||
d174bd64 DV |
489 | /* Per-page copy function for the shmem pread fastpath. |
490 | * Flushes invalid cachelines before reading the target if | |
491 | * needs_clflush is set. */ | |
eb01459f | 492 | static int |
d174bd64 DV |
493 | shmem_pread_fast(struct page *page, int shmem_page_offset, int page_length, |
494 | char __user *user_data, | |
495 | bool page_do_bit17_swizzling, bool needs_clflush) | |
496 | { | |
497 | char *vaddr; | |
498 | int ret; | |
499 | ||
e7e58eb5 | 500 | if (unlikely(page_do_bit17_swizzling)) |
d174bd64 DV |
501 | return -EINVAL; |
502 | ||
503 | vaddr = kmap_atomic(page); | |
504 | if (needs_clflush) | |
505 | drm_clflush_virt_range(vaddr + shmem_page_offset, | |
506 | page_length); | |
507 | ret = __copy_to_user_inatomic(user_data, | |
508 | vaddr + shmem_page_offset, | |
509 | page_length); | |
510 | kunmap_atomic(vaddr); | |
511 | ||
f60d7f0c | 512 | return ret ? -EFAULT : 0; |
d174bd64 DV |
513 | } |
514 | ||
23c18c71 DV |
515 | static void |
516 | shmem_clflush_swizzled_range(char *addr, unsigned long length, | |
517 | bool swizzled) | |
518 | { | |
e7e58eb5 | 519 | if (unlikely(swizzled)) { |
23c18c71 DV |
520 | unsigned long start = (unsigned long) addr; |
521 | unsigned long end = (unsigned long) addr + length; | |
522 | ||
523 | /* For swizzling simply ensure that we always flush both | |
524 | * channels. Lame, but simple and it works. Swizzled | |
525 | * pwrite/pread is far from a hotpath - current userspace | |
526 | * doesn't use it at all. */ | |
527 | start = round_down(start, 128); | |
528 | end = round_up(end, 128); | |
529 | ||
530 | drm_clflush_virt_range((void *)start, end - start); | |
531 | } else { | |
532 | drm_clflush_virt_range(addr, length); | |
533 | } | |
534 | ||
535 | } | |
536 | ||
d174bd64 DV |
537 | /* Only difference to the fast-path function is that this can handle bit17 |
538 | * and uses non-atomic copy and kmap functions. */ | |
539 | static int | |
540 | shmem_pread_slow(struct page *page, int shmem_page_offset, int page_length, | |
541 | char __user *user_data, | |
542 | bool page_do_bit17_swizzling, bool needs_clflush) | |
543 | { | |
544 | char *vaddr; | |
545 | int ret; | |
546 | ||
547 | vaddr = kmap(page); | |
548 | if (needs_clflush) | |
23c18c71 DV |
549 | shmem_clflush_swizzled_range(vaddr + shmem_page_offset, |
550 | page_length, | |
551 | page_do_bit17_swizzling); | |
d174bd64 DV |
552 | |
553 | if (page_do_bit17_swizzling) | |
554 | ret = __copy_to_user_swizzled(user_data, | |
555 | vaddr, shmem_page_offset, | |
556 | page_length); | |
557 | else | |
558 | ret = __copy_to_user(user_data, | |
559 | vaddr + shmem_page_offset, | |
560 | page_length); | |
561 | kunmap(page); | |
562 | ||
f60d7f0c | 563 | return ret ? - EFAULT : 0; |
d174bd64 DV |
564 | } |
565 | ||
eb01459f | 566 | static int |
dbf7bff0 DV |
567 | i915_gem_shmem_pread(struct drm_device *dev, |
568 | struct drm_i915_gem_object *obj, | |
569 | struct drm_i915_gem_pread *args, | |
570 | struct drm_file *file) | |
eb01459f | 571 | { |
8461d226 | 572 | char __user *user_data; |
eb01459f | 573 | ssize_t remain; |
8461d226 | 574 | loff_t offset; |
eb2c0c81 | 575 | int shmem_page_offset, page_length, ret = 0; |
8461d226 | 576 | int obj_do_bit17_swizzling, page_do_bit17_swizzling; |
96d79b52 | 577 | int prefaulted = 0; |
8489731c | 578 | int needs_clflush = 0; |
67d5a50c | 579 | struct sg_page_iter sg_iter; |
eb01459f | 580 | |
2bb4629a | 581 | user_data = to_user_ptr(args->data_ptr); |
eb01459f EA |
582 | remain = args->size; |
583 | ||
8461d226 | 584 | obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj); |
eb01459f | 585 | |
4c914c0c | 586 | ret = i915_gem_obj_prepare_shmem_read(obj, &needs_clflush); |
f60d7f0c CW |
587 | if (ret) |
588 | return ret; | |
589 | ||
8461d226 | 590 | offset = args->offset; |
eb01459f | 591 | |
67d5a50c ID |
592 | for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, |
593 | offset >> PAGE_SHIFT) { | |
2db76d7c | 594 | struct page *page = sg_page_iter_page(&sg_iter); |
9da3da66 CW |
595 | |
596 | if (remain <= 0) | |
597 | break; | |
598 | ||
eb01459f EA |
599 | /* Operation in this page |
600 | * | |
eb01459f | 601 | * shmem_page_offset = offset within page in shmem file |
eb01459f EA |
602 | * page_length = bytes to copy for this page |
603 | */ | |
c8cbbb8b | 604 | shmem_page_offset = offset_in_page(offset); |
eb01459f EA |
605 | page_length = remain; |
606 | if ((shmem_page_offset + page_length) > PAGE_SIZE) | |
607 | page_length = PAGE_SIZE - shmem_page_offset; | |
eb01459f | 608 | |
8461d226 DV |
609 | page_do_bit17_swizzling = obj_do_bit17_swizzling && |
610 | (page_to_phys(page) & (1 << 17)) != 0; | |
611 | ||
d174bd64 DV |
612 | ret = shmem_pread_fast(page, shmem_page_offset, page_length, |
613 | user_data, page_do_bit17_swizzling, | |
614 | needs_clflush); | |
615 | if (ret == 0) | |
616 | goto next_page; | |
dbf7bff0 | 617 | |
dbf7bff0 DV |
618 | mutex_unlock(&dev->struct_mutex); |
619 | ||
d330a953 | 620 | if (likely(!i915.prefault_disable) && !prefaulted) { |
f56f821f | 621 | ret = fault_in_multipages_writeable(user_data, remain); |
96d79b52 DV |
622 | /* Userspace is tricking us, but we've already clobbered |
623 | * its pages with the prefault and promised to write the | |
624 | * data up to the first fault. Hence ignore any errors | |
625 | * and just continue. */ | |
626 | (void)ret; | |
627 | prefaulted = 1; | |
628 | } | |
eb01459f | 629 | |
d174bd64 DV |
630 | ret = shmem_pread_slow(page, shmem_page_offset, page_length, |
631 | user_data, page_do_bit17_swizzling, | |
632 | needs_clflush); | |
eb01459f | 633 | |
dbf7bff0 | 634 | mutex_lock(&dev->struct_mutex); |
f60d7f0c | 635 | |
f60d7f0c | 636 | if (ret) |
8461d226 | 637 | goto out; |
8461d226 | 638 | |
17793c9a | 639 | next_page: |
eb01459f | 640 | remain -= page_length; |
8461d226 | 641 | user_data += page_length; |
eb01459f EA |
642 | offset += page_length; |
643 | } | |
644 | ||
4f27b75d | 645 | out: |
f60d7f0c CW |
646 | i915_gem_object_unpin_pages(obj); |
647 | ||
eb01459f EA |
648 | return ret; |
649 | } | |
650 | ||
673a394b EA |
651 | /** |
652 | * Reads data from the object referenced by handle. | |
653 | * | |
654 | * On error, the contents of *data are undefined. | |
655 | */ | |
656 | int | |
657 | i915_gem_pread_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 658 | struct drm_file *file) |
673a394b EA |
659 | { |
660 | struct drm_i915_gem_pread *args = data; | |
05394f39 | 661 | struct drm_i915_gem_object *obj; |
35b62a89 | 662 | int ret = 0; |
673a394b | 663 | |
51311d0a CW |
664 | if (args->size == 0) |
665 | return 0; | |
666 | ||
667 | if (!access_ok(VERIFY_WRITE, | |
2bb4629a | 668 | to_user_ptr(args->data_ptr), |
51311d0a CW |
669 | args->size)) |
670 | return -EFAULT; | |
671 | ||
4f27b75d | 672 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 673 | if (ret) |
4f27b75d | 674 | return ret; |
673a394b | 675 | |
05394f39 | 676 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 677 | if (&obj->base == NULL) { |
1d7cfea1 CW |
678 | ret = -ENOENT; |
679 | goto unlock; | |
4f27b75d | 680 | } |
673a394b | 681 | |
7dcd2499 | 682 | /* Bounds check source. */ |
05394f39 CW |
683 | if (args->offset > obj->base.size || |
684 | args->size > obj->base.size - args->offset) { | |
ce9d419d | 685 | ret = -EINVAL; |
35b62a89 | 686 | goto out; |
ce9d419d CW |
687 | } |
688 | ||
1286ff73 DV |
689 | /* prime objects have no backing filp to GEM pread/pwrite |
690 | * pages from. | |
691 | */ | |
692 | if (!obj->base.filp) { | |
693 | ret = -EINVAL; | |
694 | goto out; | |
695 | } | |
696 | ||
db53a302 CW |
697 | trace_i915_gem_object_pread(obj, args->offset, args->size); |
698 | ||
dbf7bff0 | 699 | ret = i915_gem_shmem_pread(dev, obj, args, file); |
673a394b | 700 | |
35b62a89 | 701 | out: |
05394f39 | 702 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 703 | unlock: |
4f27b75d | 704 | mutex_unlock(&dev->struct_mutex); |
eb01459f | 705 | return ret; |
673a394b EA |
706 | } |
707 | ||
0839ccb8 KP |
708 | /* This is the fast write path which cannot handle |
709 | * page faults in the source data | |
9b7530cc | 710 | */ |
0839ccb8 KP |
711 | |
712 | static inline int | |
713 | fast_user_write(struct io_mapping *mapping, | |
714 | loff_t page_base, int page_offset, | |
715 | char __user *user_data, | |
716 | int length) | |
9b7530cc | 717 | { |
4f0c7cfb BW |
718 | void __iomem *vaddr_atomic; |
719 | void *vaddr; | |
0839ccb8 | 720 | unsigned long unwritten; |
9b7530cc | 721 | |
3e4d3af5 | 722 | vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base); |
4f0c7cfb BW |
723 | /* We can use the cpu mem copy function because this is X86. */ |
724 | vaddr = (void __force*)vaddr_atomic + page_offset; | |
725 | unwritten = __copy_from_user_inatomic_nocache(vaddr, | |
0839ccb8 | 726 | user_data, length); |
3e4d3af5 | 727 | io_mapping_unmap_atomic(vaddr_atomic); |
fbd5a26d | 728 | return unwritten; |
0839ccb8 KP |
729 | } |
730 | ||
3de09aa3 EA |
731 | /** |
732 | * This is the fast pwrite path, where we copy the data directly from the | |
733 | * user into the GTT, uncached. | |
734 | */ | |
673a394b | 735 | static int |
05394f39 CW |
736 | i915_gem_gtt_pwrite_fast(struct drm_device *dev, |
737 | struct drm_i915_gem_object *obj, | |
3de09aa3 | 738 | struct drm_i915_gem_pwrite *args, |
05394f39 | 739 | struct drm_file *file) |
673a394b | 740 | { |
3e31c6c0 | 741 | struct drm_i915_private *dev_priv = dev->dev_private; |
673a394b | 742 | ssize_t remain; |
0839ccb8 | 743 | loff_t offset, page_base; |
673a394b | 744 | char __user *user_data; |
935aaa69 DV |
745 | int page_offset, page_length, ret; |
746 | ||
1ec9e26d | 747 | ret = i915_gem_obj_ggtt_pin(obj, 0, PIN_MAPPABLE | PIN_NONBLOCK); |
935aaa69 DV |
748 | if (ret) |
749 | goto out; | |
750 | ||
751 | ret = i915_gem_object_set_to_gtt_domain(obj, true); | |
752 | if (ret) | |
753 | goto out_unpin; | |
754 | ||
755 | ret = i915_gem_object_put_fence(obj); | |
756 | if (ret) | |
757 | goto out_unpin; | |
673a394b | 758 | |
2bb4629a | 759 | user_data = to_user_ptr(args->data_ptr); |
673a394b | 760 | remain = args->size; |
673a394b | 761 | |
f343c5f6 | 762 | offset = i915_gem_obj_ggtt_offset(obj) + args->offset; |
673a394b EA |
763 | |
764 | while (remain > 0) { | |
765 | /* Operation in this page | |
766 | * | |
0839ccb8 KP |
767 | * page_base = page offset within aperture |
768 | * page_offset = offset within page | |
769 | * page_length = bytes to copy for this page | |
673a394b | 770 | */ |
c8cbbb8b CW |
771 | page_base = offset & PAGE_MASK; |
772 | page_offset = offset_in_page(offset); | |
0839ccb8 KP |
773 | page_length = remain; |
774 | if ((page_offset + remain) > PAGE_SIZE) | |
775 | page_length = PAGE_SIZE - page_offset; | |
776 | ||
0839ccb8 | 777 | /* If we get a fault while copying data, then (presumably) our |
3de09aa3 EA |
778 | * source page isn't available. Return the error and we'll |
779 | * retry in the slow path. | |
0839ccb8 | 780 | */ |
5d4545ae | 781 | if (fast_user_write(dev_priv->gtt.mappable, page_base, |
935aaa69 DV |
782 | page_offset, user_data, page_length)) { |
783 | ret = -EFAULT; | |
784 | goto out_unpin; | |
785 | } | |
673a394b | 786 | |
0839ccb8 KP |
787 | remain -= page_length; |
788 | user_data += page_length; | |
789 | offset += page_length; | |
673a394b | 790 | } |
673a394b | 791 | |
935aaa69 | 792 | out_unpin: |
d7f46fc4 | 793 | i915_gem_object_ggtt_unpin(obj); |
935aaa69 | 794 | out: |
3de09aa3 | 795 | return ret; |
673a394b EA |
796 | } |
797 | ||
d174bd64 DV |
798 | /* Per-page copy function for the shmem pwrite fastpath. |
799 | * Flushes invalid cachelines before writing to the target if | |
800 | * needs_clflush_before is set and flushes out any written cachelines after | |
801 | * writing if needs_clflush is set. */ | |
3043c60c | 802 | static int |
d174bd64 DV |
803 | shmem_pwrite_fast(struct page *page, int shmem_page_offset, int page_length, |
804 | char __user *user_data, | |
805 | bool page_do_bit17_swizzling, | |
806 | bool needs_clflush_before, | |
807 | bool needs_clflush_after) | |
673a394b | 808 | { |
d174bd64 | 809 | char *vaddr; |
673a394b | 810 | int ret; |
3de09aa3 | 811 | |
e7e58eb5 | 812 | if (unlikely(page_do_bit17_swizzling)) |
d174bd64 | 813 | return -EINVAL; |
3de09aa3 | 814 | |
d174bd64 DV |
815 | vaddr = kmap_atomic(page); |
816 | if (needs_clflush_before) | |
817 | drm_clflush_virt_range(vaddr + shmem_page_offset, | |
818 | page_length); | |
c2831a94 CW |
819 | ret = __copy_from_user_inatomic(vaddr + shmem_page_offset, |
820 | user_data, page_length); | |
d174bd64 DV |
821 | if (needs_clflush_after) |
822 | drm_clflush_virt_range(vaddr + shmem_page_offset, | |
823 | page_length); | |
824 | kunmap_atomic(vaddr); | |
3de09aa3 | 825 | |
755d2218 | 826 | return ret ? -EFAULT : 0; |
3de09aa3 EA |
827 | } |
828 | ||
d174bd64 DV |
829 | /* Only difference to the fast-path function is that this can handle bit17 |
830 | * and uses non-atomic copy and kmap functions. */ | |
3043c60c | 831 | static int |
d174bd64 DV |
832 | shmem_pwrite_slow(struct page *page, int shmem_page_offset, int page_length, |
833 | char __user *user_data, | |
834 | bool page_do_bit17_swizzling, | |
835 | bool needs_clflush_before, | |
836 | bool needs_clflush_after) | |
673a394b | 837 | { |
d174bd64 DV |
838 | char *vaddr; |
839 | int ret; | |
e5281ccd | 840 | |
d174bd64 | 841 | vaddr = kmap(page); |
e7e58eb5 | 842 | if (unlikely(needs_clflush_before || page_do_bit17_swizzling)) |
23c18c71 DV |
843 | shmem_clflush_swizzled_range(vaddr + shmem_page_offset, |
844 | page_length, | |
845 | page_do_bit17_swizzling); | |
d174bd64 DV |
846 | if (page_do_bit17_swizzling) |
847 | ret = __copy_from_user_swizzled(vaddr, shmem_page_offset, | |
e5281ccd CW |
848 | user_data, |
849 | page_length); | |
d174bd64 DV |
850 | else |
851 | ret = __copy_from_user(vaddr + shmem_page_offset, | |
852 | user_data, | |
853 | page_length); | |
854 | if (needs_clflush_after) | |
23c18c71 DV |
855 | shmem_clflush_swizzled_range(vaddr + shmem_page_offset, |
856 | page_length, | |
857 | page_do_bit17_swizzling); | |
d174bd64 | 858 | kunmap(page); |
40123c1f | 859 | |
755d2218 | 860 | return ret ? -EFAULT : 0; |
40123c1f EA |
861 | } |
862 | ||
40123c1f | 863 | static int |
e244a443 DV |
864 | i915_gem_shmem_pwrite(struct drm_device *dev, |
865 | struct drm_i915_gem_object *obj, | |
866 | struct drm_i915_gem_pwrite *args, | |
867 | struct drm_file *file) | |
40123c1f | 868 | { |
40123c1f | 869 | ssize_t remain; |
8c59967c DV |
870 | loff_t offset; |
871 | char __user *user_data; | |
eb2c0c81 | 872 | int shmem_page_offset, page_length, ret = 0; |
8c59967c | 873 | int obj_do_bit17_swizzling, page_do_bit17_swizzling; |
e244a443 | 874 | int hit_slowpath = 0; |
58642885 DV |
875 | int needs_clflush_after = 0; |
876 | int needs_clflush_before = 0; | |
67d5a50c | 877 | struct sg_page_iter sg_iter; |
40123c1f | 878 | |
2bb4629a | 879 | user_data = to_user_ptr(args->data_ptr); |
40123c1f EA |
880 | remain = args->size; |
881 | ||
8c59967c | 882 | obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj); |
40123c1f | 883 | |
58642885 DV |
884 | if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) { |
885 | /* If we're not in the cpu write domain, set ourself into the gtt | |
886 | * write domain and manually flush cachelines (if required). This | |
887 | * optimizes for the case when the gpu will use the data | |
888 | * right away and we therefore have to clflush anyway. */ | |
2c22569b | 889 | needs_clflush_after = cpu_write_needs_clflush(obj); |
23f54483 BW |
890 | ret = i915_gem_object_wait_rendering(obj, false); |
891 | if (ret) | |
892 | return ret; | |
c8725f3d CW |
893 | |
894 | i915_gem_object_retire(obj); | |
58642885 | 895 | } |
c76ce038 CW |
896 | /* Same trick applies to invalidate partially written cachelines read |
897 | * before writing. */ | |
898 | if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) | |
899 | needs_clflush_before = | |
900 | !cpu_cache_is_coherent(dev, obj->cache_level); | |
58642885 | 901 | |
755d2218 CW |
902 | ret = i915_gem_object_get_pages(obj); |
903 | if (ret) | |
904 | return ret; | |
905 | ||
906 | i915_gem_object_pin_pages(obj); | |
907 | ||
673a394b | 908 | offset = args->offset; |
05394f39 | 909 | obj->dirty = 1; |
673a394b | 910 | |
67d5a50c ID |
911 | for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, |
912 | offset >> PAGE_SHIFT) { | |
2db76d7c | 913 | struct page *page = sg_page_iter_page(&sg_iter); |
58642885 | 914 | int partial_cacheline_write; |
e5281ccd | 915 | |
9da3da66 CW |
916 | if (remain <= 0) |
917 | break; | |
918 | ||
40123c1f EA |
919 | /* Operation in this page |
920 | * | |
40123c1f | 921 | * shmem_page_offset = offset within page in shmem file |
40123c1f EA |
922 | * page_length = bytes to copy for this page |
923 | */ | |
c8cbbb8b | 924 | shmem_page_offset = offset_in_page(offset); |
40123c1f EA |
925 | |
926 | page_length = remain; | |
927 | if ((shmem_page_offset + page_length) > PAGE_SIZE) | |
928 | page_length = PAGE_SIZE - shmem_page_offset; | |
40123c1f | 929 | |
58642885 DV |
930 | /* If we don't overwrite a cacheline completely we need to be |
931 | * careful to have up-to-date data by first clflushing. Don't | |
932 | * overcomplicate things and flush the entire patch. */ | |
933 | partial_cacheline_write = needs_clflush_before && | |
934 | ((shmem_page_offset | page_length) | |
935 | & (boot_cpu_data.x86_clflush_size - 1)); | |
936 | ||
8c59967c DV |
937 | page_do_bit17_swizzling = obj_do_bit17_swizzling && |
938 | (page_to_phys(page) & (1 << 17)) != 0; | |
939 | ||
d174bd64 DV |
940 | ret = shmem_pwrite_fast(page, shmem_page_offset, page_length, |
941 | user_data, page_do_bit17_swizzling, | |
942 | partial_cacheline_write, | |
943 | needs_clflush_after); | |
944 | if (ret == 0) | |
945 | goto next_page; | |
e244a443 DV |
946 | |
947 | hit_slowpath = 1; | |
e244a443 | 948 | mutex_unlock(&dev->struct_mutex); |
d174bd64 DV |
949 | ret = shmem_pwrite_slow(page, shmem_page_offset, page_length, |
950 | user_data, page_do_bit17_swizzling, | |
951 | partial_cacheline_write, | |
952 | needs_clflush_after); | |
40123c1f | 953 | |
e244a443 | 954 | mutex_lock(&dev->struct_mutex); |
755d2218 | 955 | |
755d2218 | 956 | if (ret) |
8c59967c | 957 | goto out; |
8c59967c | 958 | |
17793c9a | 959 | next_page: |
40123c1f | 960 | remain -= page_length; |
8c59967c | 961 | user_data += page_length; |
40123c1f | 962 | offset += page_length; |
673a394b EA |
963 | } |
964 | ||
fbd5a26d | 965 | out: |
755d2218 CW |
966 | i915_gem_object_unpin_pages(obj); |
967 | ||
e244a443 | 968 | if (hit_slowpath) { |
8dcf015e DV |
969 | /* |
970 | * Fixup: Flush cpu caches in case we didn't flush the dirty | |
971 | * cachelines in-line while writing and the object moved | |
972 | * out of the cpu write domain while we've dropped the lock. | |
973 | */ | |
974 | if (!needs_clflush_after && | |
975 | obj->base.write_domain != I915_GEM_DOMAIN_CPU) { | |
000433b6 CW |
976 | if (i915_gem_clflush_object(obj, obj->pin_display)) |
977 | i915_gem_chipset_flush(dev); | |
e244a443 | 978 | } |
8c59967c | 979 | } |
673a394b | 980 | |
58642885 | 981 | if (needs_clflush_after) |
e76e9aeb | 982 | i915_gem_chipset_flush(dev); |
58642885 | 983 | |
40123c1f | 984 | return ret; |
673a394b EA |
985 | } |
986 | ||
987 | /** | |
988 | * Writes data to the object referenced by handle. | |
989 | * | |
990 | * On error, the contents of the buffer that were to be modified are undefined. | |
991 | */ | |
992 | int | |
993 | i915_gem_pwrite_ioctl(struct drm_device *dev, void *data, | |
fbd5a26d | 994 | struct drm_file *file) |
673a394b EA |
995 | { |
996 | struct drm_i915_gem_pwrite *args = data; | |
05394f39 | 997 | struct drm_i915_gem_object *obj; |
51311d0a CW |
998 | int ret; |
999 | ||
1000 | if (args->size == 0) | |
1001 | return 0; | |
1002 | ||
1003 | if (!access_ok(VERIFY_READ, | |
2bb4629a | 1004 | to_user_ptr(args->data_ptr), |
51311d0a CW |
1005 | args->size)) |
1006 | return -EFAULT; | |
1007 | ||
d330a953 | 1008 | if (likely(!i915.prefault_disable)) { |
0b74b508 XZ |
1009 | ret = fault_in_multipages_readable(to_user_ptr(args->data_ptr), |
1010 | args->size); | |
1011 | if (ret) | |
1012 | return -EFAULT; | |
1013 | } | |
673a394b | 1014 | |
fbd5a26d | 1015 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 1016 | if (ret) |
fbd5a26d | 1017 | return ret; |
1d7cfea1 | 1018 | |
05394f39 | 1019 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 1020 | if (&obj->base == NULL) { |
1d7cfea1 CW |
1021 | ret = -ENOENT; |
1022 | goto unlock; | |
fbd5a26d | 1023 | } |
673a394b | 1024 | |
7dcd2499 | 1025 | /* Bounds check destination. */ |
05394f39 CW |
1026 | if (args->offset > obj->base.size || |
1027 | args->size > obj->base.size - args->offset) { | |
ce9d419d | 1028 | ret = -EINVAL; |
35b62a89 | 1029 | goto out; |
ce9d419d CW |
1030 | } |
1031 | ||
1286ff73 DV |
1032 | /* prime objects have no backing filp to GEM pread/pwrite |
1033 | * pages from. | |
1034 | */ | |
1035 | if (!obj->base.filp) { | |
1036 | ret = -EINVAL; | |
1037 | goto out; | |
1038 | } | |
1039 | ||
db53a302 CW |
1040 | trace_i915_gem_object_pwrite(obj, args->offset, args->size); |
1041 | ||
935aaa69 | 1042 | ret = -EFAULT; |
673a394b EA |
1043 | /* We can only do the GTT pwrite on untiled buffers, as otherwise |
1044 | * it would end up going through the fenced access, and we'll get | |
1045 | * different detiling behavior between reading and writing. | |
1046 | * pread/pwrite currently are reading and writing from the CPU | |
1047 | * perspective, requiring manual detiling by the client. | |
1048 | */ | |
00731155 CW |
1049 | if (obj->phys_handle) { |
1050 | ret = i915_gem_phys_pwrite(obj, args, file); | |
5c0480f2 DV |
1051 | goto out; |
1052 | } | |
1053 | ||
2c22569b CW |
1054 | if (obj->tiling_mode == I915_TILING_NONE && |
1055 | obj->base.write_domain != I915_GEM_DOMAIN_CPU && | |
1056 | cpu_write_needs_clflush(obj)) { | |
fbd5a26d | 1057 | ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file); |
935aaa69 DV |
1058 | /* Note that the gtt paths might fail with non-page-backed user |
1059 | * pointers (e.g. gtt mappings when moving data between | |
1060 | * textures). Fallback to the shmem path in that case. */ | |
fbd5a26d | 1061 | } |
673a394b | 1062 | |
86a1ee26 | 1063 | if (ret == -EFAULT || ret == -ENOSPC) |
935aaa69 | 1064 | ret = i915_gem_shmem_pwrite(dev, obj, args, file); |
5c0480f2 | 1065 | |
35b62a89 | 1066 | out: |
05394f39 | 1067 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 1068 | unlock: |
fbd5a26d | 1069 | mutex_unlock(&dev->struct_mutex); |
673a394b EA |
1070 | return ret; |
1071 | } | |
1072 | ||
b361237b | 1073 | int |
33196ded | 1074 | i915_gem_check_wedge(struct i915_gpu_error *error, |
b361237b CW |
1075 | bool interruptible) |
1076 | { | |
1f83fee0 | 1077 | if (i915_reset_in_progress(error)) { |
b361237b CW |
1078 | /* Non-interruptible callers can't handle -EAGAIN, hence return |
1079 | * -EIO unconditionally for these. */ | |
1080 | if (!interruptible) | |
1081 | return -EIO; | |
1082 | ||
1f83fee0 DV |
1083 | /* Recovery complete, but the reset failed ... */ |
1084 | if (i915_terminally_wedged(error)) | |
b361237b CW |
1085 | return -EIO; |
1086 | ||
6689c167 MA |
1087 | /* |
1088 | * Check if GPU Reset is in progress - we need intel_ring_begin | |
1089 | * to work properly to reinit the hw state while the gpu is | |
1090 | * still marked as reset-in-progress. Handle this with a flag. | |
1091 | */ | |
1092 | if (!error->reload_in_reset) | |
1093 | return -EAGAIN; | |
b361237b CW |
1094 | } |
1095 | ||
1096 | return 0; | |
1097 | } | |
1098 | ||
1099 | /* | |
1100 | * Compare seqno against outstanding lazy request. Emit a request if they are | |
1101 | * equal. | |
1102 | */ | |
84c33a64 | 1103 | int |
a4872ba6 | 1104 | i915_gem_check_olr(struct intel_engine_cs *ring, u32 seqno) |
b361237b CW |
1105 | { |
1106 | int ret; | |
1107 | ||
1108 | BUG_ON(!mutex_is_locked(&ring->dev->struct_mutex)); | |
1109 | ||
1110 | ret = 0; | |
1823521d | 1111 | if (seqno == ring->outstanding_lazy_seqno) |
0025c077 | 1112 | ret = i915_add_request(ring, NULL); |
b361237b CW |
1113 | |
1114 | return ret; | |
1115 | } | |
1116 | ||
094f9a54 CW |
1117 | static void fake_irq(unsigned long data) |
1118 | { | |
1119 | wake_up_process((struct task_struct *)data); | |
1120 | } | |
1121 | ||
1122 | static bool missed_irq(struct drm_i915_private *dev_priv, | |
a4872ba6 | 1123 | struct intel_engine_cs *ring) |
094f9a54 CW |
1124 | { |
1125 | return test_bit(ring->id, &dev_priv->gpu_error.missed_irq_rings); | |
1126 | } | |
1127 | ||
b29c19b6 CW |
1128 | static bool can_wait_boost(struct drm_i915_file_private *file_priv) |
1129 | { | |
1130 | if (file_priv == NULL) | |
1131 | return true; | |
1132 | ||
1133 | return !atomic_xchg(&file_priv->rps_wait_boost, true); | |
1134 | } | |
1135 | ||
b361237b CW |
1136 | /** |
1137 | * __wait_seqno - wait until execution of seqno has finished | |
1138 | * @ring: the ring expected to report seqno | |
1139 | * @seqno: duh! | |
f69061be | 1140 | * @reset_counter: reset sequence associated with the given seqno |
b361237b CW |
1141 | * @interruptible: do an interruptible wait (normally yes) |
1142 | * @timeout: in - how long to wait (NULL forever); out - how much time remaining | |
1143 | * | |
f69061be DV |
1144 | * Note: It is of utmost importance that the passed in seqno and reset_counter |
1145 | * values have been read by the caller in an smp safe manner. Where read-side | |
1146 | * locks are involved, it is sufficient to read the reset_counter before | |
1147 | * unlocking the lock that protects the seqno. For lockless tricks, the | |
1148 | * reset_counter _must_ be read before, and an appropriate smp_rmb must be | |
1149 | * inserted. | |
1150 | * | |
b361237b CW |
1151 | * Returns 0 if the seqno was found within the alloted time. Else returns the |
1152 | * errno with remaining time filled in timeout argument. | |
1153 | */ | |
a4872ba6 | 1154 | static int __wait_seqno(struct intel_engine_cs *ring, u32 seqno, |
f69061be | 1155 | unsigned reset_counter, |
b29c19b6 | 1156 | bool interruptible, |
5ed0bdf2 | 1157 | s64 *timeout, |
b29c19b6 | 1158 | struct drm_i915_file_private *file_priv) |
b361237b | 1159 | { |
3d13ef2e | 1160 | struct drm_device *dev = ring->dev; |
3e31c6c0 | 1161 | struct drm_i915_private *dev_priv = dev->dev_private; |
168c3f21 MK |
1162 | const bool irq_test_in_progress = |
1163 | ACCESS_ONCE(dev_priv->gpu_error.test_irq_rings) & intel_ring_flag(ring); | |
094f9a54 | 1164 | DEFINE_WAIT(wait); |
47e9766d | 1165 | unsigned long timeout_expire; |
5ed0bdf2 | 1166 | s64 before, now; |
b361237b CW |
1167 | int ret; |
1168 | ||
9df7575f | 1169 | WARN(!intel_irqs_enabled(dev_priv), "IRQs disabled"); |
c67a470b | 1170 | |
b361237b CW |
1171 | if (i915_seqno_passed(ring->get_seqno(ring, true), seqno)) |
1172 | return 0; | |
1173 | ||
5ed0bdf2 | 1174 | timeout_expire = timeout ? jiffies + nsecs_to_jiffies((u64)*timeout) : 0; |
b361237b | 1175 | |
ec5cc0f9 | 1176 | if (INTEL_INFO(dev)->gen >= 6 && ring->id == RCS && can_wait_boost(file_priv)) { |
b29c19b6 CW |
1177 | gen6_rps_boost(dev_priv); |
1178 | if (file_priv) | |
1179 | mod_delayed_work(dev_priv->wq, | |
1180 | &file_priv->mm.idle_work, | |
1181 | msecs_to_jiffies(100)); | |
1182 | } | |
1183 | ||
168c3f21 | 1184 | if (!irq_test_in_progress && WARN_ON(!ring->irq_get(ring))) |
b361237b CW |
1185 | return -ENODEV; |
1186 | ||
094f9a54 CW |
1187 | /* Record current time in case interrupted by signal, or wedged */ |
1188 | trace_i915_gem_request_wait_begin(ring, seqno); | |
5ed0bdf2 | 1189 | before = ktime_get_raw_ns(); |
094f9a54 CW |
1190 | for (;;) { |
1191 | struct timer_list timer; | |
b361237b | 1192 | |
094f9a54 CW |
1193 | prepare_to_wait(&ring->irq_queue, &wait, |
1194 | interruptible ? TASK_INTERRUPTIBLE : TASK_UNINTERRUPTIBLE); | |
b361237b | 1195 | |
f69061be DV |
1196 | /* We need to check whether any gpu reset happened in between |
1197 | * the caller grabbing the seqno and now ... */ | |
094f9a54 CW |
1198 | if (reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter)) { |
1199 | /* ... but upgrade the -EAGAIN to an -EIO if the gpu | |
1200 | * is truely gone. */ | |
1201 | ret = i915_gem_check_wedge(&dev_priv->gpu_error, interruptible); | |
1202 | if (ret == 0) | |
1203 | ret = -EAGAIN; | |
1204 | break; | |
1205 | } | |
f69061be | 1206 | |
094f9a54 CW |
1207 | if (i915_seqno_passed(ring->get_seqno(ring, false), seqno)) { |
1208 | ret = 0; | |
1209 | break; | |
1210 | } | |
b361237b | 1211 | |
094f9a54 CW |
1212 | if (interruptible && signal_pending(current)) { |
1213 | ret = -ERESTARTSYS; | |
1214 | break; | |
1215 | } | |
1216 | ||
47e9766d | 1217 | if (timeout && time_after_eq(jiffies, timeout_expire)) { |
094f9a54 CW |
1218 | ret = -ETIME; |
1219 | break; | |
1220 | } | |
1221 | ||
1222 | timer.function = NULL; | |
1223 | if (timeout || missed_irq(dev_priv, ring)) { | |
47e9766d MK |
1224 | unsigned long expire; |
1225 | ||
094f9a54 | 1226 | setup_timer_on_stack(&timer, fake_irq, (unsigned long)current); |
47e9766d | 1227 | expire = missed_irq(dev_priv, ring) ? jiffies + 1 : timeout_expire; |
094f9a54 CW |
1228 | mod_timer(&timer, expire); |
1229 | } | |
1230 | ||
5035c275 | 1231 | io_schedule(); |
094f9a54 | 1232 | |
094f9a54 CW |
1233 | if (timer.function) { |
1234 | del_singleshot_timer_sync(&timer); | |
1235 | destroy_timer_on_stack(&timer); | |
1236 | } | |
1237 | } | |
5ed0bdf2 | 1238 | now = ktime_get_raw_ns(); |
094f9a54 | 1239 | trace_i915_gem_request_wait_end(ring, seqno); |
b361237b | 1240 | |
168c3f21 MK |
1241 | if (!irq_test_in_progress) |
1242 | ring->irq_put(ring); | |
094f9a54 CW |
1243 | |
1244 | finish_wait(&ring->irq_queue, &wait); | |
b361237b CW |
1245 | |
1246 | if (timeout) { | |
5ed0bdf2 TG |
1247 | s64 tres = *timeout - (now - before); |
1248 | ||
1249 | *timeout = tres < 0 ? 0 : tres; | |
b361237b CW |
1250 | } |
1251 | ||
094f9a54 | 1252 | return ret; |
b361237b CW |
1253 | } |
1254 | ||
1255 | /** | |
1256 | * Waits for a sequence number to be signaled, and cleans up the | |
1257 | * request and object lists appropriately for that event. | |
1258 | */ | |
1259 | int | |
a4872ba6 | 1260 | i915_wait_seqno(struct intel_engine_cs *ring, uint32_t seqno) |
b361237b CW |
1261 | { |
1262 | struct drm_device *dev = ring->dev; | |
1263 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1264 | bool interruptible = dev_priv->mm.interruptible; | |
1265 | int ret; | |
1266 | ||
1267 | BUG_ON(!mutex_is_locked(&dev->struct_mutex)); | |
1268 | BUG_ON(seqno == 0); | |
1269 | ||
33196ded | 1270 | ret = i915_gem_check_wedge(&dev_priv->gpu_error, interruptible); |
b361237b CW |
1271 | if (ret) |
1272 | return ret; | |
1273 | ||
1274 | ret = i915_gem_check_olr(ring, seqno); | |
1275 | if (ret) | |
1276 | return ret; | |
1277 | ||
f69061be DV |
1278 | return __wait_seqno(ring, seqno, |
1279 | atomic_read(&dev_priv->gpu_error.reset_counter), | |
b29c19b6 | 1280 | interruptible, NULL, NULL); |
b361237b CW |
1281 | } |
1282 | ||
d26e3af8 CW |
1283 | static int |
1284 | i915_gem_object_wait_rendering__tail(struct drm_i915_gem_object *obj, | |
a4872ba6 | 1285 | struct intel_engine_cs *ring) |
d26e3af8 | 1286 | { |
c8725f3d CW |
1287 | if (!obj->active) |
1288 | return 0; | |
d26e3af8 CW |
1289 | |
1290 | /* Manually manage the write flush as we may have not yet | |
1291 | * retired the buffer. | |
1292 | * | |
1293 | * Note that the last_write_seqno is always the earlier of | |
1294 | * the two (read/write) seqno, so if we haved successfully waited, | |
1295 | * we know we have passed the last write. | |
1296 | */ | |
1297 | obj->last_write_seqno = 0; | |
d26e3af8 CW |
1298 | |
1299 | return 0; | |
1300 | } | |
1301 | ||
b361237b CW |
1302 | /** |
1303 | * Ensures that all rendering to the object has completed and the object is | |
1304 | * safe to unbind from the GTT or access from the CPU. | |
1305 | */ | |
1306 | static __must_check int | |
1307 | i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj, | |
1308 | bool readonly) | |
1309 | { | |
a4872ba6 | 1310 | struct intel_engine_cs *ring = obj->ring; |
b361237b CW |
1311 | u32 seqno; |
1312 | int ret; | |
1313 | ||
1314 | seqno = readonly ? obj->last_write_seqno : obj->last_read_seqno; | |
1315 | if (seqno == 0) | |
1316 | return 0; | |
1317 | ||
1318 | ret = i915_wait_seqno(ring, seqno); | |
1319 | if (ret) | |
1320 | return ret; | |
1321 | ||
d26e3af8 | 1322 | return i915_gem_object_wait_rendering__tail(obj, ring); |
b361237b CW |
1323 | } |
1324 | ||
3236f57a CW |
1325 | /* A nonblocking variant of the above wait. This is a highly dangerous routine |
1326 | * as the object state may change during this call. | |
1327 | */ | |
1328 | static __must_check int | |
1329 | i915_gem_object_wait_rendering__nonblocking(struct drm_i915_gem_object *obj, | |
6e4930f6 | 1330 | struct drm_i915_file_private *file_priv, |
3236f57a CW |
1331 | bool readonly) |
1332 | { | |
1333 | struct drm_device *dev = obj->base.dev; | |
1334 | struct drm_i915_private *dev_priv = dev->dev_private; | |
a4872ba6 | 1335 | struct intel_engine_cs *ring = obj->ring; |
f69061be | 1336 | unsigned reset_counter; |
3236f57a CW |
1337 | u32 seqno; |
1338 | int ret; | |
1339 | ||
1340 | BUG_ON(!mutex_is_locked(&dev->struct_mutex)); | |
1341 | BUG_ON(!dev_priv->mm.interruptible); | |
1342 | ||
1343 | seqno = readonly ? obj->last_write_seqno : obj->last_read_seqno; | |
1344 | if (seqno == 0) | |
1345 | return 0; | |
1346 | ||
33196ded | 1347 | ret = i915_gem_check_wedge(&dev_priv->gpu_error, true); |
3236f57a CW |
1348 | if (ret) |
1349 | return ret; | |
1350 | ||
1351 | ret = i915_gem_check_olr(ring, seqno); | |
1352 | if (ret) | |
1353 | return ret; | |
1354 | ||
f69061be | 1355 | reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter); |
3236f57a | 1356 | mutex_unlock(&dev->struct_mutex); |
6e4930f6 | 1357 | ret = __wait_seqno(ring, seqno, reset_counter, true, NULL, file_priv); |
3236f57a | 1358 | mutex_lock(&dev->struct_mutex); |
d26e3af8 CW |
1359 | if (ret) |
1360 | return ret; | |
3236f57a | 1361 | |
d26e3af8 | 1362 | return i915_gem_object_wait_rendering__tail(obj, ring); |
3236f57a CW |
1363 | } |
1364 | ||
673a394b | 1365 | /** |
2ef7eeaa EA |
1366 | * Called when user space prepares to use an object with the CPU, either |
1367 | * through the mmap ioctl's mapping or a GTT mapping. | |
673a394b EA |
1368 | */ |
1369 | int | |
1370 | i915_gem_set_domain_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 1371 | struct drm_file *file) |
673a394b EA |
1372 | { |
1373 | struct drm_i915_gem_set_domain *args = data; | |
05394f39 | 1374 | struct drm_i915_gem_object *obj; |
2ef7eeaa EA |
1375 | uint32_t read_domains = args->read_domains; |
1376 | uint32_t write_domain = args->write_domain; | |
673a394b EA |
1377 | int ret; |
1378 | ||
2ef7eeaa | 1379 | /* Only handle setting domains to types used by the CPU. */ |
21d509e3 | 1380 | if (write_domain & I915_GEM_GPU_DOMAINS) |
2ef7eeaa EA |
1381 | return -EINVAL; |
1382 | ||
21d509e3 | 1383 | if (read_domains & I915_GEM_GPU_DOMAINS) |
2ef7eeaa EA |
1384 | return -EINVAL; |
1385 | ||
1386 | /* Having something in the write domain implies it's in the read | |
1387 | * domain, and only that read domain. Enforce that in the request. | |
1388 | */ | |
1389 | if (write_domain != 0 && read_domains != write_domain) | |
1390 | return -EINVAL; | |
1391 | ||
76c1dec1 | 1392 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 1393 | if (ret) |
76c1dec1 | 1394 | return ret; |
1d7cfea1 | 1395 | |
05394f39 | 1396 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 1397 | if (&obj->base == NULL) { |
1d7cfea1 CW |
1398 | ret = -ENOENT; |
1399 | goto unlock; | |
76c1dec1 | 1400 | } |
673a394b | 1401 | |
3236f57a CW |
1402 | /* Try to flush the object off the GPU without holding the lock. |
1403 | * We will repeat the flush holding the lock in the normal manner | |
1404 | * to catch cases where we are gazumped. | |
1405 | */ | |
6e4930f6 CW |
1406 | ret = i915_gem_object_wait_rendering__nonblocking(obj, |
1407 | file->driver_priv, | |
1408 | !write_domain); | |
3236f57a CW |
1409 | if (ret) |
1410 | goto unref; | |
1411 | ||
2ef7eeaa EA |
1412 | if (read_domains & I915_GEM_DOMAIN_GTT) { |
1413 | ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0); | |
02354392 EA |
1414 | |
1415 | /* Silently promote "you're not bound, there was nothing to do" | |
1416 | * to success, since the client was just asking us to | |
1417 | * make sure everything was done. | |
1418 | */ | |
1419 | if (ret == -EINVAL) | |
1420 | ret = 0; | |
2ef7eeaa | 1421 | } else { |
e47c68e9 | 1422 | ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0); |
2ef7eeaa EA |
1423 | } |
1424 | ||
3236f57a | 1425 | unref: |
05394f39 | 1426 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 1427 | unlock: |
673a394b EA |
1428 | mutex_unlock(&dev->struct_mutex); |
1429 | return ret; | |
1430 | } | |
1431 | ||
1432 | /** | |
1433 | * Called when user space has done writes to this buffer | |
1434 | */ | |
1435 | int | |
1436 | i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 1437 | struct drm_file *file) |
673a394b EA |
1438 | { |
1439 | struct drm_i915_gem_sw_finish *args = data; | |
05394f39 | 1440 | struct drm_i915_gem_object *obj; |
673a394b EA |
1441 | int ret = 0; |
1442 | ||
76c1dec1 | 1443 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 1444 | if (ret) |
76c1dec1 | 1445 | return ret; |
1d7cfea1 | 1446 | |
05394f39 | 1447 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 1448 | if (&obj->base == NULL) { |
1d7cfea1 CW |
1449 | ret = -ENOENT; |
1450 | goto unlock; | |
673a394b EA |
1451 | } |
1452 | ||
673a394b | 1453 | /* Pinned buffers may be scanout, so flush the cache */ |
2c22569b CW |
1454 | if (obj->pin_display) |
1455 | i915_gem_object_flush_cpu_write_domain(obj, true); | |
e47c68e9 | 1456 | |
05394f39 | 1457 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 1458 | unlock: |
673a394b EA |
1459 | mutex_unlock(&dev->struct_mutex); |
1460 | return ret; | |
1461 | } | |
1462 | ||
1463 | /** | |
1464 | * Maps the contents of an object, returning the address it is mapped | |
1465 | * into. | |
1466 | * | |
1467 | * While the mapping holds a reference on the contents of the object, it doesn't | |
1468 | * imply a ref on the object itself. | |
1469 | */ | |
1470 | int | |
1471 | i915_gem_mmap_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 1472 | struct drm_file *file) |
673a394b EA |
1473 | { |
1474 | struct drm_i915_gem_mmap *args = data; | |
1475 | struct drm_gem_object *obj; | |
673a394b EA |
1476 | unsigned long addr; |
1477 | ||
05394f39 | 1478 | obj = drm_gem_object_lookup(dev, file, args->handle); |
673a394b | 1479 | if (obj == NULL) |
bf79cb91 | 1480 | return -ENOENT; |
673a394b | 1481 | |
1286ff73 DV |
1482 | /* prime objects have no backing filp to GEM mmap |
1483 | * pages from. | |
1484 | */ | |
1485 | if (!obj->filp) { | |
1486 | drm_gem_object_unreference_unlocked(obj); | |
1487 | return -EINVAL; | |
1488 | } | |
1489 | ||
6be5ceb0 | 1490 | addr = vm_mmap(obj->filp, 0, args->size, |
673a394b EA |
1491 | PROT_READ | PROT_WRITE, MAP_SHARED, |
1492 | args->offset); | |
bc9025bd | 1493 | drm_gem_object_unreference_unlocked(obj); |
673a394b EA |
1494 | if (IS_ERR((void *)addr)) |
1495 | return addr; | |
1496 | ||
1497 | args->addr_ptr = (uint64_t) addr; | |
1498 | ||
1499 | return 0; | |
1500 | } | |
1501 | ||
de151cf6 JB |
1502 | /** |
1503 | * i915_gem_fault - fault a page into the GTT | |
1504 | * vma: VMA in question | |
1505 | * vmf: fault info | |
1506 | * | |
1507 | * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped | |
1508 | * from userspace. The fault handler takes care of binding the object to | |
1509 | * the GTT (if needed), allocating and programming a fence register (again, | |
1510 | * only if needed based on whether the old reg is still valid or the object | |
1511 | * is tiled) and inserting a new PTE into the faulting process. | |
1512 | * | |
1513 | * Note that the faulting process may involve evicting existing objects | |
1514 | * from the GTT and/or fence registers to make room. So performance may | |
1515 | * suffer if the GTT working set is large or there are few fence registers | |
1516 | * left. | |
1517 | */ | |
1518 | int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf) | |
1519 | { | |
05394f39 CW |
1520 | struct drm_i915_gem_object *obj = to_intel_bo(vma->vm_private_data); |
1521 | struct drm_device *dev = obj->base.dev; | |
3e31c6c0 | 1522 | struct drm_i915_private *dev_priv = dev->dev_private; |
de151cf6 JB |
1523 | pgoff_t page_offset; |
1524 | unsigned long pfn; | |
1525 | int ret = 0; | |
0f973f27 | 1526 | bool write = !!(vmf->flags & FAULT_FLAG_WRITE); |
de151cf6 | 1527 | |
f65c9168 PZ |
1528 | intel_runtime_pm_get(dev_priv); |
1529 | ||
de151cf6 JB |
1530 | /* We don't use vmf->pgoff since that has the fake offset */ |
1531 | page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >> | |
1532 | PAGE_SHIFT; | |
1533 | ||
d9bc7e9f CW |
1534 | ret = i915_mutex_lock_interruptible(dev); |
1535 | if (ret) | |
1536 | goto out; | |
a00b10c3 | 1537 | |
db53a302 CW |
1538 | trace_i915_gem_object_fault(obj, page_offset, true, write); |
1539 | ||
6e4930f6 CW |
1540 | /* Try to flush the object off the GPU first without holding the lock. |
1541 | * Upon reacquiring the lock, we will perform our sanity checks and then | |
1542 | * repeat the flush holding the lock in the normal manner to catch cases | |
1543 | * where we are gazumped. | |
1544 | */ | |
1545 | ret = i915_gem_object_wait_rendering__nonblocking(obj, NULL, !write); | |
1546 | if (ret) | |
1547 | goto unlock; | |
1548 | ||
eb119bd6 CW |
1549 | /* Access to snoopable pages through the GTT is incoherent. */ |
1550 | if (obj->cache_level != I915_CACHE_NONE && !HAS_LLC(dev)) { | |
ddeff6ee | 1551 | ret = -EFAULT; |
eb119bd6 CW |
1552 | goto unlock; |
1553 | } | |
1554 | ||
d9bc7e9f | 1555 | /* Now bind it into the GTT if needed */ |
1ec9e26d | 1556 | ret = i915_gem_obj_ggtt_pin(obj, 0, PIN_MAPPABLE); |
c9839303 CW |
1557 | if (ret) |
1558 | goto unlock; | |
4a684a41 | 1559 | |
c9839303 CW |
1560 | ret = i915_gem_object_set_to_gtt_domain(obj, write); |
1561 | if (ret) | |
1562 | goto unpin; | |
74898d7e | 1563 | |
06d98131 | 1564 | ret = i915_gem_object_get_fence(obj); |
d9e86c0e | 1565 | if (ret) |
c9839303 | 1566 | goto unpin; |
7d1c4804 | 1567 | |
b90b91d8 | 1568 | /* Finally, remap it using the new GTT offset */ |
f343c5f6 BW |
1569 | pfn = dev_priv->gtt.mappable_base + i915_gem_obj_ggtt_offset(obj); |
1570 | pfn >>= PAGE_SHIFT; | |
de151cf6 | 1571 | |
b90b91d8 | 1572 | if (!obj->fault_mappable) { |
beff0d0f VS |
1573 | unsigned long size = min_t(unsigned long, |
1574 | vma->vm_end - vma->vm_start, | |
1575 | obj->base.size); | |
b90b91d8 CW |
1576 | int i; |
1577 | ||
beff0d0f | 1578 | for (i = 0; i < size >> PAGE_SHIFT; i++) { |
b90b91d8 CW |
1579 | ret = vm_insert_pfn(vma, |
1580 | (unsigned long)vma->vm_start + i * PAGE_SIZE, | |
1581 | pfn + i); | |
1582 | if (ret) | |
1583 | break; | |
1584 | } | |
1585 | ||
1586 | obj->fault_mappable = true; | |
1587 | } else | |
1588 | ret = vm_insert_pfn(vma, | |
1589 | (unsigned long)vmf->virtual_address, | |
1590 | pfn + page_offset); | |
c9839303 | 1591 | unpin: |
d7f46fc4 | 1592 | i915_gem_object_ggtt_unpin(obj); |
c715089f | 1593 | unlock: |
de151cf6 | 1594 | mutex_unlock(&dev->struct_mutex); |
d9bc7e9f | 1595 | out: |
de151cf6 | 1596 | switch (ret) { |
d9bc7e9f | 1597 | case -EIO: |
2232f031 DV |
1598 | /* |
1599 | * We eat errors when the gpu is terminally wedged to avoid | |
1600 | * userspace unduly crashing (gl has no provisions for mmaps to | |
1601 | * fail). But any other -EIO isn't ours (e.g. swap in failure) | |
1602 | * and so needs to be reported. | |
1603 | */ | |
1604 | if (!i915_terminally_wedged(&dev_priv->gpu_error)) { | |
f65c9168 PZ |
1605 | ret = VM_FAULT_SIGBUS; |
1606 | break; | |
1607 | } | |
045e769a | 1608 | case -EAGAIN: |
571c608d DV |
1609 | /* |
1610 | * EAGAIN means the gpu is hung and we'll wait for the error | |
1611 | * handler to reset everything when re-faulting in | |
1612 | * i915_mutex_lock_interruptible. | |
d9bc7e9f | 1613 | */ |
c715089f CW |
1614 | case 0: |
1615 | case -ERESTARTSYS: | |
bed636ab | 1616 | case -EINTR: |
e79e0fe3 DR |
1617 | case -EBUSY: |
1618 | /* | |
1619 | * EBUSY is ok: this just means that another thread | |
1620 | * already did the job. | |
1621 | */ | |
f65c9168 PZ |
1622 | ret = VM_FAULT_NOPAGE; |
1623 | break; | |
de151cf6 | 1624 | case -ENOMEM: |
f65c9168 PZ |
1625 | ret = VM_FAULT_OOM; |
1626 | break; | |
a7c2e1aa | 1627 | case -ENOSPC: |
45d67817 | 1628 | case -EFAULT: |
f65c9168 PZ |
1629 | ret = VM_FAULT_SIGBUS; |
1630 | break; | |
de151cf6 | 1631 | default: |
a7c2e1aa | 1632 | WARN_ONCE(ret, "unhandled error in i915_gem_fault: %i\n", ret); |
f65c9168 PZ |
1633 | ret = VM_FAULT_SIGBUS; |
1634 | break; | |
de151cf6 | 1635 | } |
f65c9168 PZ |
1636 | |
1637 | intel_runtime_pm_put(dev_priv); | |
1638 | return ret; | |
de151cf6 JB |
1639 | } |
1640 | ||
901782b2 CW |
1641 | /** |
1642 | * i915_gem_release_mmap - remove physical page mappings | |
1643 | * @obj: obj in question | |
1644 | * | |
af901ca1 | 1645 | * Preserve the reservation of the mmapping with the DRM core code, but |
901782b2 CW |
1646 | * relinquish ownership of the pages back to the system. |
1647 | * | |
1648 | * It is vital that we remove the page mapping if we have mapped a tiled | |
1649 | * object through the GTT and then lose the fence register due to | |
1650 | * resource pressure. Similarly if the object has been moved out of the | |
1651 | * aperture, than pages mapped into userspace must be revoked. Removing the | |
1652 | * mapping will then trigger a page fault on the next user access, allowing | |
1653 | * fixup by i915_gem_fault(). | |
1654 | */ | |
d05ca301 | 1655 | void |
05394f39 | 1656 | i915_gem_release_mmap(struct drm_i915_gem_object *obj) |
901782b2 | 1657 | { |
6299f992 CW |
1658 | if (!obj->fault_mappable) |
1659 | return; | |
901782b2 | 1660 | |
6796cb16 DH |
1661 | drm_vma_node_unmap(&obj->base.vma_node, |
1662 | obj->base.dev->anon_inode->i_mapping); | |
6299f992 | 1663 | obj->fault_mappable = false; |
901782b2 CW |
1664 | } |
1665 | ||
eedd10f4 CW |
1666 | void |
1667 | i915_gem_release_all_mmaps(struct drm_i915_private *dev_priv) | |
1668 | { | |
1669 | struct drm_i915_gem_object *obj; | |
1670 | ||
1671 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) | |
1672 | i915_gem_release_mmap(obj); | |
1673 | } | |
1674 | ||
0fa87796 | 1675 | uint32_t |
e28f8711 | 1676 | i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode) |
92b88aeb | 1677 | { |
e28f8711 | 1678 | uint32_t gtt_size; |
92b88aeb CW |
1679 | |
1680 | if (INTEL_INFO(dev)->gen >= 4 || | |
e28f8711 CW |
1681 | tiling_mode == I915_TILING_NONE) |
1682 | return size; | |
92b88aeb CW |
1683 | |
1684 | /* Previous chips need a power-of-two fence region when tiling */ | |
1685 | if (INTEL_INFO(dev)->gen == 3) | |
e28f8711 | 1686 | gtt_size = 1024*1024; |
92b88aeb | 1687 | else |
e28f8711 | 1688 | gtt_size = 512*1024; |
92b88aeb | 1689 | |
e28f8711 CW |
1690 | while (gtt_size < size) |
1691 | gtt_size <<= 1; | |
92b88aeb | 1692 | |
e28f8711 | 1693 | return gtt_size; |
92b88aeb CW |
1694 | } |
1695 | ||
de151cf6 JB |
1696 | /** |
1697 | * i915_gem_get_gtt_alignment - return required GTT alignment for an object | |
1698 | * @obj: object to check | |
1699 | * | |
1700 | * Return the required GTT alignment for an object, taking into account | |
5e783301 | 1701 | * potential fence register mapping. |
de151cf6 | 1702 | */ |
d865110c ID |
1703 | uint32_t |
1704 | i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size, | |
1705 | int tiling_mode, bool fenced) | |
de151cf6 | 1706 | { |
de151cf6 JB |
1707 | /* |
1708 | * Minimum alignment is 4k (GTT page size), but might be greater | |
1709 | * if a fence register is needed for the object. | |
1710 | */ | |
d865110c | 1711 | if (INTEL_INFO(dev)->gen >= 4 || (!fenced && IS_G33(dev)) || |
e28f8711 | 1712 | tiling_mode == I915_TILING_NONE) |
de151cf6 JB |
1713 | return 4096; |
1714 | ||
a00b10c3 CW |
1715 | /* |
1716 | * Previous chips need to be aligned to the size of the smallest | |
1717 | * fence register that can contain the object. | |
1718 | */ | |
e28f8711 | 1719 | return i915_gem_get_gtt_size(dev, size, tiling_mode); |
a00b10c3 CW |
1720 | } |
1721 | ||
d8cb5086 CW |
1722 | static int i915_gem_object_create_mmap_offset(struct drm_i915_gem_object *obj) |
1723 | { | |
1724 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; | |
1725 | int ret; | |
1726 | ||
0de23977 | 1727 | if (drm_vma_node_has_offset(&obj->base.vma_node)) |
d8cb5086 CW |
1728 | return 0; |
1729 | ||
da494d7c DV |
1730 | dev_priv->mm.shrinker_no_lock_stealing = true; |
1731 | ||
d8cb5086 CW |
1732 | ret = drm_gem_create_mmap_offset(&obj->base); |
1733 | if (ret != -ENOSPC) | |
da494d7c | 1734 | goto out; |
d8cb5086 CW |
1735 | |
1736 | /* Badly fragmented mmap space? The only way we can recover | |
1737 | * space is by destroying unwanted objects. We can't randomly release | |
1738 | * mmap_offsets as userspace expects them to be persistent for the | |
1739 | * lifetime of the objects. The closest we can is to release the | |
1740 | * offsets on purgeable objects by truncating it and marking it purged, | |
1741 | * which prevents userspace from ever using that object again. | |
1742 | */ | |
21ab4e74 CW |
1743 | i915_gem_shrink(dev_priv, |
1744 | obj->base.size >> PAGE_SHIFT, | |
1745 | I915_SHRINK_BOUND | | |
1746 | I915_SHRINK_UNBOUND | | |
1747 | I915_SHRINK_PURGEABLE); | |
d8cb5086 CW |
1748 | ret = drm_gem_create_mmap_offset(&obj->base); |
1749 | if (ret != -ENOSPC) | |
da494d7c | 1750 | goto out; |
d8cb5086 CW |
1751 | |
1752 | i915_gem_shrink_all(dev_priv); | |
da494d7c DV |
1753 | ret = drm_gem_create_mmap_offset(&obj->base); |
1754 | out: | |
1755 | dev_priv->mm.shrinker_no_lock_stealing = false; | |
1756 | ||
1757 | return ret; | |
d8cb5086 CW |
1758 | } |
1759 | ||
1760 | static void i915_gem_object_free_mmap_offset(struct drm_i915_gem_object *obj) | |
1761 | { | |
d8cb5086 CW |
1762 | drm_gem_free_mmap_offset(&obj->base); |
1763 | } | |
1764 | ||
de151cf6 | 1765 | int |
ff72145b DA |
1766 | i915_gem_mmap_gtt(struct drm_file *file, |
1767 | struct drm_device *dev, | |
1768 | uint32_t handle, | |
1769 | uint64_t *offset) | |
de151cf6 | 1770 | { |
da761a6e | 1771 | struct drm_i915_private *dev_priv = dev->dev_private; |
05394f39 | 1772 | struct drm_i915_gem_object *obj; |
de151cf6 JB |
1773 | int ret; |
1774 | ||
76c1dec1 | 1775 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 1776 | if (ret) |
76c1dec1 | 1777 | return ret; |
de151cf6 | 1778 | |
ff72145b | 1779 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle)); |
c8725226 | 1780 | if (&obj->base == NULL) { |
1d7cfea1 CW |
1781 | ret = -ENOENT; |
1782 | goto unlock; | |
1783 | } | |
de151cf6 | 1784 | |
5d4545ae | 1785 | if (obj->base.size > dev_priv->gtt.mappable_end) { |
da761a6e | 1786 | ret = -E2BIG; |
ff56b0bc | 1787 | goto out; |
da761a6e CW |
1788 | } |
1789 | ||
05394f39 | 1790 | if (obj->madv != I915_MADV_WILLNEED) { |
bd9b6a4e | 1791 | DRM_DEBUG("Attempting to mmap a purgeable buffer\n"); |
8c99e57d | 1792 | ret = -EFAULT; |
1d7cfea1 | 1793 | goto out; |
ab18282d CW |
1794 | } |
1795 | ||
d8cb5086 CW |
1796 | ret = i915_gem_object_create_mmap_offset(obj); |
1797 | if (ret) | |
1798 | goto out; | |
de151cf6 | 1799 | |
0de23977 | 1800 | *offset = drm_vma_node_offset_addr(&obj->base.vma_node); |
de151cf6 | 1801 | |
1d7cfea1 | 1802 | out: |
05394f39 | 1803 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 1804 | unlock: |
de151cf6 | 1805 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 1806 | return ret; |
de151cf6 JB |
1807 | } |
1808 | ||
ff72145b DA |
1809 | /** |
1810 | * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing | |
1811 | * @dev: DRM device | |
1812 | * @data: GTT mapping ioctl data | |
1813 | * @file: GEM object info | |
1814 | * | |
1815 | * Simply returns the fake offset to userspace so it can mmap it. | |
1816 | * The mmap call will end up in drm_gem_mmap(), which will set things | |
1817 | * up so we can get faults in the handler above. | |
1818 | * | |
1819 | * The fault handler will take care of binding the object into the GTT | |
1820 | * (since it may have been evicted to make room for something), allocating | |
1821 | * a fence register, and mapping the appropriate aperture address into | |
1822 | * userspace. | |
1823 | */ | |
1824 | int | |
1825 | i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data, | |
1826 | struct drm_file *file) | |
1827 | { | |
1828 | struct drm_i915_gem_mmap_gtt *args = data; | |
1829 | ||
ff72145b DA |
1830 | return i915_gem_mmap_gtt(file, dev, args->handle, &args->offset); |
1831 | } | |
1832 | ||
5537252b CW |
1833 | static inline int |
1834 | i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj) | |
1835 | { | |
1836 | return obj->madv == I915_MADV_DONTNEED; | |
1837 | } | |
1838 | ||
225067ee DV |
1839 | /* Immediately discard the backing storage */ |
1840 | static void | |
1841 | i915_gem_object_truncate(struct drm_i915_gem_object *obj) | |
e5281ccd | 1842 | { |
4d6294bf | 1843 | i915_gem_object_free_mmap_offset(obj); |
1286ff73 | 1844 | |
4d6294bf CW |
1845 | if (obj->base.filp == NULL) |
1846 | return; | |
e5281ccd | 1847 | |
225067ee DV |
1848 | /* Our goal here is to return as much of the memory as |
1849 | * is possible back to the system as we are called from OOM. | |
1850 | * To do this we must instruct the shmfs to drop all of its | |
1851 | * backing pages, *now*. | |
1852 | */ | |
5537252b | 1853 | shmem_truncate_range(file_inode(obj->base.filp), 0, (loff_t)-1); |
225067ee DV |
1854 | obj->madv = __I915_MADV_PURGED; |
1855 | } | |
e5281ccd | 1856 | |
5537252b CW |
1857 | /* Try to discard unwanted pages */ |
1858 | static void | |
1859 | i915_gem_object_invalidate(struct drm_i915_gem_object *obj) | |
225067ee | 1860 | { |
5537252b CW |
1861 | struct address_space *mapping; |
1862 | ||
1863 | switch (obj->madv) { | |
1864 | case I915_MADV_DONTNEED: | |
1865 | i915_gem_object_truncate(obj); | |
1866 | case __I915_MADV_PURGED: | |
1867 | return; | |
1868 | } | |
1869 | ||
1870 | if (obj->base.filp == NULL) | |
1871 | return; | |
1872 | ||
1873 | mapping = file_inode(obj->base.filp)->i_mapping, | |
1874 | invalidate_mapping_pages(mapping, 0, (loff_t)-1); | |
e5281ccd CW |
1875 | } |
1876 | ||
5cdf5881 | 1877 | static void |
05394f39 | 1878 | i915_gem_object_put_pages_gtt(struct drm_i915_gem_object *obj) |
673a394b | 1879 | { |
90797e6d ID |
1880 | struct sg_page_iter sg_iter; |
1881 | int ret; | |
1286ff73 | 1882 | |
05394f39 | 1883 | BUG_ON(obj->madv == __I915_MADV_PURGED); |
673a394b | 1884 | |
6c085a72 CW |
1885 | ret = i915_gem_object_set_to_cpu_domain(obj, true); |
1886 | if (ret) { | |
1887 | /* In the event of a disaster, abandon all caches and | |
1888 | * hope for the best. | |
1889 | */ | |
1890 | WARN_ON(ret != -EIO); | |
2c22569b | 1891 | i915_gem_clflush_object(obj, true); |
6c085a72 CW |
1892 | obj->base.read_domains = obj->base.write_domain = I915_GEM_DOMAIN_CPU; |
1893 | } | |
1894 | ||
6dacfd2f | 1895 | if (i915_gem_object_needs_bit17_swizzle(obj)) |
280b713b EA |
1896 | i915_gem_object_save_bit_17_swizzle(obj); |
1897 | ||
05394f39 CW |
1898 | if (obj->madv == I915_MADV_DONTNEED) |
1899 | obj->dirty = 0; | |
3ef94daa | 1900 | |
90797e6d | 1901 | for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, 0) { |
2db76d7c | 1902 | struct page *page = sg_page_iter_page(&sg_iter); |
9da3da66 | 1903 | |
05394f39 | 1904 | if (obj->dirty) |
9da3da66 | 1905 | set_page_dirty(page); |
3ef94daa | 1906 | |
05394f39 | 1907 | if (obj->madv == I915_MADV_WILLNEED) |
9da3da66 | 1908 | mark_page_accessed(page); |
3ef94daa | 1909 | |
9da3da66 | 1910 | page_cache_release(page); |
3ef94daa | 1911 | } |
05394f39 | 1912 | obj->dirty = 0; |
673a394b | 1913 | |
9da3da66 CW |
1914 | sg_free_table(obj->pages); |
1915 | kfree(obj->pages); | |
37e680a1 | 1916 | } |
6c085a72 | 1917 | |
dd624afd | 1918 | int |
37e680a1 CW |
1919 | i915_gem_object_put_pages(struct drm_i915_gem_object *obj) |
1920 | { | |
1921 | const struct drm_i915_gem_object_ops *ops = obj->ops; | |
1922 | ||
2f745ad3 | 1923 | if (obj->pages == NULL) |
37e680a1 CW |
1924 | return 0; |
1925 | ||
a5570178 CW |
1926 | if (obj->pages_pin_count) |
1927 | return -EBUSY; | |
1928 | ||
9843877d | 1929 | BUG_ON(i915_gem_obj_bound_any(obj)); |
3e123027 | 1930 | |
a2165e31 CW |
1931 | /* ->put_pages might need to allocate memory for the bit17 swizzle |
1932 | * array, hence protect them from being reaped by removing them from gtt | |
1933 | * lists early. */ | |
35c20a60 | 1934 | list_del(&obj->global_list); |
a2165e31 | 1935 | |
37e680a1 | 1936 | ops->put_pages(obj); |
05394f39 | 1937 | obj->pages = NULL; |
37e680a1 | 1938 | |
5537252b | 1939 | i915_gem_object_invalidate(obj); |
6c085a72 CW |
1940 | |
1941 | return 0; | |
1942 | } | |
1943 | ||
21ab4e74 CW |
1944 | unsigned long |
1945 | i915_gem_shrink(struct drm_i915_private *dev_priv, | |
1946 | long target, unsigned flags) | |
6c085a72 | 1947 | { |
21ab4e74 | 1948 | const bool purgeable_only = flags & I915_SHRINK_PURGEABLE; |
d9973b43 | 1949 | unsigned long count = 0; |
6c085a72 | 1950 | |
57094f82 | 1951 | /* |
c8725f3d | 1952 | * As we may completely rewrite the (un)bound list whilst unbinding |
57094f82 CW |
1953 | * (due to retiring requests) we have to strictly process only |
1954 | * one element of the list at the time, and recheck the list | |
1955 | * on every iteration. | |
c8725f3d CW |
1956 | * |
1957 | * In particular, we must hold a reference whilst removing the | |
1958 | * object as we may end up waiting for and/or retiring the objects. | |
1959 | * This might release the final reference (held by the active list) | |
1960 | * and result in the object being freed from under us. This is | |
1961 | * similar to the precautions the eviction code must take whilst | |
1962 | * removing objects. | |
1963 | * | |
1964 | * Also note that although these lists do not hold a reference to | |
1965 | * the object we can safely grab one here: The final object | |
1966 | * unreferencing and the bound_list are both protected by the | |
1967 | * dev->struct_mutex and so we won't ever be able to observe an | |
1968 | * object on the bound_list with a reference count equals 0. | |
57094f82 | 1969 | */ |
21ab4e74 CW |
1970 | if (flags & I915_SHRINK_UNBOUND) { |
1971 | struct list_head still_in_list; | |
c8725f3d | 1972 | |
21ab4e74 CW |
1973 | INIT_LIST_HEAD(&still_in_list); |
1974 | while (count < target && !list_empty(&dev_priv->mm.unbound_list)) { | |
1975 | struct drm_i915_gem_object *obj; | |
c8725f3d | 1976 | |
21ab4e74 CW |
1977 | obj = list_first_entry(&dev_priv->mm.unbound_list, |
1978 | typeof(*obj), global_list); | |
1979 | list_move_tail(&obj->global_list, &still_in_list); | |
c8725f3d | 1980 | |
21ab4e74 CW |
1981 | if (!i915_gem_object_is_purgeable(obj) && purgeable_only) |
1982 | continue; | |
c8725f3d | 1983 | |
21ab4e74 CW |
1984 | drm_gem_object_reference(&obj->base); |
1985 | ||
1986 | if (i915_gem_object_put_pages(obj) == 0) | |
1987 | count += obj->base.size >> PAGE_SHIFT; | |
1988 | ||
1989 | drm_gem_object_unreference(&obj->base); | |
1990 | } | |
1991 | list_splice(&still_in_list, &dev_priv->mm.unbound_list); | |
c8725f3d | 1992 | } |
c8725f3d | 1993 | |
21ab4e74 CW |
1994 | if (flags & I915_SHRINK_BOUND) { |
1995 | struct list_head still_in_list; | |
80dcfdbd | 1996 | |
21ab4e74 CW |
1997 | INIT_LIST_HEAD(&still_in_list); |
1998 | while (count < target && !list_empty(&dev_priv->mm.bound_list)) { | |
1999 | struct drm_i915_gem_object *obj; | |
2000 | struct i915_vma *vma, *v; | |
57094f82 | 2001 | |
21ab4e74 CW |
2002 | obj = list_first_entry(&dev_priv->mm.bound_list, |
2003 | typeof(*obj), global_list); | |
2004 | list_move_tail(&obj->global_list, &still_in_list); | |
80dcfdbd | 2005 | |
21ab4e74 CW |
2006 | if (!i915_gem_object_is_purgeable(obj) && purgeable_only) |
2007 | continue; | |
57094f82 | 2008 | |
21ab4e74 | 2009 | drm_gem_object_reference(&obj->base); |
80dcfdbd | 2010 | |
21ab4e74 CW |
2011 | list_for_each_entry_safe(vma, v, &obj->vma_list, vma_link) |
2012 | if (i915_vma_unbind(vma)) | |
2013 | break; | |
57094f82 | 2014 | |
21ab4e74 CW |
2015 | if (i915_gem_object_put_pages(obj) == 0) |
2016 | count += obj->base.size >> PAGE_SHIFT; | |
2017 | ||
2018 | drm_gem_object_unreference(&obj->base); | |
2019 | } | |
2020 | list_splice(&still_in_list, &dev_priv->mm.bound_list); | |
6c085a72 CW |
2021 | } |
2022 | ||
2023 | return count; | |
2024 | } | |
2025 | ||
d9973b43 | 2026 | static unsigned long |
6c085a72 CW |
2027 | i915_gem_shrink_all(struct drm_i915_private *dev_priv) |
2028 | { | |
6c085a72 | 2029 | i915_gem_evict_everything(dev_priv->dev); |
21ab4e74 CW |
2030 | return i915_gem_shrink(dev_priv, LONG_MAX, |
2031 | I915_SHRINK_BOUND | I915_SHRINK_UNBOUND); | |
225067ee DV |
2032 | } |
2033 | ||
37e680a1 | 2034 | static int |
6c085a72 | 2035 | i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj) |
e5281ccd | 2036 | { |
6c085a72 | 2037 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
e5281ccd CW |
2038 | int page_count, i; |
2039 | struct address_space *mapping; | |
9da3da66 CW |
2040 | struct sg_table *st; |
2041 | struct scatterlist *sg; | |
90797e6d | 2042 | struct sg_page_iter sg_iter; |
e5281ccd | 2043 | struct page *page; |
90797e6d | 2044 | unsigned long last_pfn = 0; /* suppress gcc warning */ |
6c085a72 | 2045 | gfp_t gfp; |
e5281ccd | 2046 | |
6c085a72 CW |
2047 | /* Assert that the object is not currently in any GPU domain. As it |
2048 | * wasn't in the GTT, there shouldn't be any way it could have been in | |
2049 | * a GPU cache | |
2050 | */ | |
2051 | BUG_ON(obj->base.read_domains & I915_GEM_GPU_DOMAINS); | |
2052 | BUG_ON(obj->base.write_domain & I915_GEM_GPU_DOMAINS); | |
2053 | ||
9da3da66 CW |
2054 | st = kmalloc(sizeof(*st), GFP_KERNEL); |
2055 | if (st == NULL) | |
2056 | return -ENOMEM; | |
2057 | ||
05394f39 | 2058 | page_count = obj->base.size / PAGE_SIZE; |
9da3da66 | 2059 | if (sg_alloc_table(st, page_count, GFP_KERNEL)) { |
9da3da66 | 2060 | kfree(st); |
e5281ccd | 2061 | return -ENOMEM; |
9da3da66 | 2062 | } |
e5281ccd | 2063 | |
9da3da66 CW |
2064 | /* Get the list of pages out of our struct file. They'll be pinned |
2065 | * at this point until we release them. | |
2066 | * | |
2067 | * Fail silently without starting the shrinker | |
2068 | */ | |
496ad9aa | 2069 | mapping = file_inode(obj->base.filp)->i_mapping; |
6c085a72 | 2070 | gfp = mapping_gfp_mask(mapping); |
caf49191 | 2071 | gfp |= __GFP_NORETRY | __GFP_NOWARN | __GFP_NO_KSWAPD; |
6c085a72 | 2072 | gfp &= ~(__GFP_IO | __GFP_WAIT); |
90797e6d ID |
2073 | sg = st->sgl; |
2074 | st->nents = 0; | |
2075 | for (i = 0; i < page_count; i++) { | |
6c085a72 CW |
2076 | page = shmem_read_mapping_page_gfp(mapping, i, gfp); |
2077 | if (IS_ERR(page)) { | |
21ab4e74 CW |
2078 | i915_gem_shrink(dev_priv, |
2079 | page_count, | |
2080 | I915_SHRINK_BOUND | | |
2081 | I915_SHRINK_UNBOUND | | |
2082 | I915_SHRINK_PURGEABLE); | |
6c085a72 CW |
2083 | page = shmem_read_mapping_page_gfp(mapping, i, gfp); |
2084 | } | |
2085 | if (IS_ERR(page)) { | |
2086 | /* We've tried hard to allocate the memory by reaping | |
2087 | * our own buffer, now let the real VM do its job and | |
2088 | * go down in flames if truly OOM. | |
2089 | */ | |
6c085a72 | 2090 | i915_gem_shrink_all(dev_priv); |
f461d1be | 2091 | page = shmem_read_mapping_page(mapping, i); |
6c085a72 CW |
2092 | if (IS_ERR(page)) |
2093 | goto err_pages; | |
6c085a72 | 2094 | } |
426729dc KRW |
2095 | #ifdef CONFIG_SWIOTLB |
2096 | if (swiotlb_nr_tbl()) { | |
2097 | st->nents++; | |
2098 | sg_set_page(sg, page, PAGE_SIZE, 0); | |
2099 | sg = sg_next(sg); | |
2100 | continue; | |
2101 | } | |
2102 | #endif | |
90797e6d ID |
2103 | if (!i || page_to_pfn(page) != last_pfn + 1) { |
2104 | if (i) | |
2105 | sg = sg_next(sg); | |
2106 | st->nents++; | |
2107 | sg_set_page(sg, page, PAGE_SIZE, 0); | |
2108 | } else { | |
2109 | sg->length += PAGE_SIZE; | |
2110 | } | |
2111 | last_pfn = page_to_pfn(page); | |
3bbbe706 DV |
2112 | |
2113 | /* Check that the i965g/gm workaround works. */ | |
2114 | WARN_ON((gfp & __GFP_DMA32) && (last_pfn >= 0x00100000UL)); | |
e5281ccd | 2115 | } |
426729dc KRW |
2116 | #ifdef CONFIG_SWIOTLB |
2117 | if (!swiotlb_nr_tbl()) | |
2118 | #endif | |
2119 | sg_mark_end(sg); | |
74ce6b6c CW |
2120 | obj->pages = st; |
2121 | ||
6dacfd2f | 2122 | if (i915_gem_object_needs_bit17_swizzle(obj)) |
e5281ccd CW |
2123 | i915_gem_object_do_bit_17_swizzle(obj); |
2124 | ||
2125 | return 0; | |
2126 | ||
2127 | err_pages: | |
90797e6d ID |
2128 | sg_mark_end(sg); |
2129 | for_each_sg_page(st->sgl, &sg_iter, st->nents, 0) | |
2db76d7c | 2130 | page_cache_release(sg_page_iter_page(&sg_iter)); |
9da3da66 CW |
2131 | sg_free_table(st); |
2132 | kfree(st); | |
0820baf3 CW |
2133 | |
2134 | /* shmemfs first checks if there is enough memory to allocate the page | |
2135 | * and reports ENOSPC should there be insufficient, along with the usual | |
2136 | * ENOMEM for a genuine allocation failure. | |
2137 | * | |
2138 | * We use ENOSPC in our driver to mean that we have run out of aperture | |
2139 | * space and so want to translate the error from shmemfs back to our | |
2140 | * usual understanding of ENOMEM. | |
2141 | */ | |
2142 | if (PTR_ERR(page) == -ENOSPC) | |
2143 | return -ENOMEM; | |
2144 | else | |
2145 | return PTR_ERR(page); | |
673a394b EA |
2146 | } |
2147 | ||
37e680a1 CW |
2148 | /* Ensure that the associated pages are gathered from the backing storage |
2149 | * and pinned into our object. i915_gem_object_get_pages() may be called | |
2150 | * multiple times before they are released by a single call to | |
2151 | * i915_gem_object_put_pages() - once the pages are no longer referenced | |
2152 | * either as a result of memory pressure (reaping pages under the shrinker) | |
2153 | * or as the object is itself released. | |
2154 | */ | |
2155 | int | |
2156 | i915_gem_object_get_pages(struct drm_i915_gem_object *obj) | |
2157 | { | |
2158 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; | |
2159 | const struct drm_i915_gem_object_ops *ops = obj->ops; | |
2160 | int ret; | |
2161 | ||
2f745ad3 | 2162 | if (obj->pages) |
37e680a1 CW |
2163 | return 0; |
2164 | ||
43e28f09 | 2165 | if (obj->madv != I915_MADV_WILLNEED) { |
bd9b6a4e | 2166 | DRM_DEBUG("Attempting to obtain a purgeable object\n"); |
8c99e57d | 2167 | return -EFAULT; |
43e28f09 CW |
2168 | } |
2169 | ||
a5570178 CW |
2170 | BUG_ON(obj->pages_pin_count); |
2171 | ||
37e680a1 CW |
2172 | ret = ops->get_pages(obj); |
2173 | if (ret) | |
2174 | return ret; | |
2175 | ||
35c20a60 | 2176 | list_add_tail(&obj->global_list, &dev_priv->mm.unbound_list); |
37e680a1 | 2177 | return 0; |
673a394b EA |
2178 | } |
2179 | ||
e2d05a8b | 2180 | static void |
05394f39 | 2181 | i915_gem_object_move_to_active(struct drm_i915_gem_object *obj, |
a4872ba6 | 2182 | struct intel_engine_cs *ring) |
673a394b | 2183 | { |
9d773091 | 2184 | u32 seqno = intel_ring_get_seqno(ring); |
617dbe27 | 2185 | |
852835f3 | 2186 | BUG_ON(ring == NULL); |
02978ff5 CW |
2187 | if (obj->ring != ring && obj->last_write_seqno) { |
2188 | /* Keep the seqno relative to the current ring */ | |
2189 | obj->last_write_seqno = seqno; | |
2190 | } | |
05394f39 | 2191 | obj->ring = ring; |
673a394b EA |
2192 | |
2193 | /* Add a reference if we're newly entering the active list. */ | |
05394f39 CW |
2194 | if (!obj->active) { |
2195 | drm_gem_object_reference(&obj->base); | |
2196 | obj->active = 1; | |
673a394b | 2197 | } |
e35a41de | 2198 | |
05394f39 | 2199 | list_move_tail(&obj->ring_list, &ring->active_list); |
caea7476 | 2200 | |
0201f1ec | 2201 | obj->last_read_seqno = seqno; |
caea7476 CW |
2202 | } |
2203 | ||
e2d05a8b | 2204 | void i915_vma_move_to_active(struct i915_vma *vma, |
a4872ba6 | 2205 | struct intel_engine_cs *ring) |
e2d05a8b BW |
2206 | { |
2207 | list_move_tail(&vma->mm_list, &vma->vm->active_list); | |
2208 | return i915_gem_object_move_to_active(vma->obj, ring); | |
2209 | } | |
2210 | ||
caea7476 | 2211 | static void |
caea7476 | 2212 | i915_gem_object_move_to_inactive(struct drm_i915_gem_object *obj) |
ce44b0ea | 2213 | { |
ca191b13 | 2214 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
feb822cf BW |
2215 | struct i915_address_space *vm; |
2216 | struct i915_vma *vma; | |
ce44b0ea | 2217 | |
65ce3027 | 2218 | BUG_ON(obj->base.write_domain & ~I915_GEM_GPU_DOMAINS); |
05394f39 | 2219 | BUG_ON(!obj->active); |
caea7476 | 2220 | |
feb822cf BW |
2221 | list_for_each_entry(vm, &dev_priv->vm_list, global_link) { |
2222 | vma = i915_gem_obj_to_vma(obj, vm); | |
2223 | if (vma && !list_empty(&vma->mm_list)) | |
2224 | list_move_tail(&vma->mm_list, &vm->inactive_list); | |
2225 | } | |
caea7476 | 2226 | |
f99d7069 DV |
2227 | intel_fb_obj_flush(obj, true); |
2228 | ||
65ce3027 | 2229 | list_del_init(&obj->ring_list); |
caea7476 CW |
2230 | obj->ring = NULL; |
2231 | ||
65ce3027 CW |
2232 | obj->last_read_seqno = 0; |
2233 | obj->last_write_seqno = 0; | |
2234 | obj->base.write_domain = 0; | |
2235 | ||
2236 | obj->last_fenced_seqno = 0; | |
caea7476 CW |
2237 | |
2238 | obj->active = 0; | |
2239 | drm_gem_object_unreference(&obj->base); | |
2240 | ||
2241 | WARN_ON(i915_verify_lists(dev)); | |
ce44b0ea | 2242 | } |
673a394b | 2243 | |
c8725f3d CW |
2244 | static void |
2245 | i915_gem_object_retire(struct drm_i915_gem_object *obj) | |
2246 | { | |
a4872ba6 | 2247 | struct intel_engine_cs *ring = obj->ring; |
c8725f3d CW |
2248 | |
2249 | if (ring == NULL) | |
2250 | return; | |
2251 | ||
2252 | if (i915_seqno_passed(ring->get_seqno(ring, true), | |
2253 | obj->last_read_seqno)) | |
2254 | i915_gem_object_move_to_inactive(obj); | |
2255 | } | |
2256 | ||
9d773091 | 2257 | static int |
fca26bb4 | 2258 | i915_gem_init_seqno(struct drm_device *dev, u32 seqno) |
53d227f2 | 2259 | { |
9d773091 | 2260 | struct drm_i915_private *dev_priv = dev->dev_private; |
a4872ba6 | 2261 | struct intel_engine_cs *ring; |
9d773091 | 2262 | int ret, i, j; |
53d227f2 | 2263 | |
107f27a5 | 2264 | /* Carefully retire all requests without writing to the rings */ |
9d773091 | 2265 | for_each_ring(ring, dev_priv, i) { |
107f27a5 CW |
2266 | ret = intel_ring_idle(ring); |
2267 | if (ret) | |
2268 | return ret; | |
9d773091 | 2269 | } |
9d773091 | 2270 | i915_gem_retire_requests(dev); |
107f27a5 CW |
2271 | |
2272 | /* Finally reset hw state */ | |
9d773091 | 2273 | for_each_ring(ring, dev_priv, i) { |
fca26bb4 | 2274 | intel_ring_init_seqno(ring, seqno); |
498d2ac1 | 2275 | |
ebc348b2 BW |
2276 | for (j = 0; j < ARRAY_SIZE(ring->semaphore.sync_seqno); j++) |
2277 | ring->semaphore.sync_seqno[j] = 0; | |
9d773091 | 2278 | } |
53d227f2 | 2279 | |
9d773091 | 2280 | return 0; |
53d227f2 DV |
2281 | } |
2282 | ||
fca26bb4 MK |
2283 | int i915_gem_set_seqno(struct drm_device *dev, u32 seqno) |
2284 | { | |
2285 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2286 | int ret; | |
2287 | ||
2288 | if (seqno == 0) | |
2289 | return -EINVAL; | |
2290 | ||
2291 | /* HWS page needs to be set less than what we | |
2292 | * will inject to ring | |
2293 | */ | |
2294 | ret = i915_gem_init_seqno(dev, seqno - 1); | |
2295 | if (ret) | |
2296 | return ret; | |
2297 | ||
2298 | /* Carefully set the last_seqno value so that wrap | |
2299 | * detection still works | |
2300 | */ | |
2301 | dev_priv->next_seqno = seqno; | |
2302 | dev_priv->last_seqno = seqno - 1; | |
2303 | if (dev_priv->last_seqno == 0) | |
2304 | dev_priv->last_seqno--; | |
2305 | ||
2306 | return 0; | |
2307 | } | |
2308 | ||
9d773091 CW |
2309 | int |
2310 | i915_gem_get_seqno(struct drm_device *dev, u32 *seqno) | |
53d227f2 | 2311 | { |
9d773091 CW |
2312 | struct drm_i915_private *dev_priv = dev->dev_private; |
2313 | ||
2314 | /* reserve 0 for non-seqno */ | |
2315 | if (dev_priv->next_seqno == 0) { | |
fca26bb4 | 2316 | int ret = i915_gem_init_seqno(dev, 0); |
9d773091 CW |
2317 | if (ret) |
2318 | return ret; | |
53d227f2 | 2319 | |
9d773091 CW |
2320 | dev_priv->next_seqno = 1; |
2321 | } | |
53d227f2 | 2322 | |
f72b3435 | 2323 | *seqno = dev_priv->last_seqno = dev_priv->next_seqno++; |
9d773091 | 2324 | return 0; |
53d227f2 DV |
2325 | } |
2326 | ||
a4872ba6 | 2327 | int __i915_add_request(struct intel_engine_cs *ring, |
0025c077 | 2328 | struct drm_file *file, |
7d736f4f | 2329 | struct drm_i915_gem_object *obj, |
0025c077 | 2330 | u32 *out_seqno) |
673a394b | 2331 | { |
3e31c6c0 | 2332 | struct drm_i915_private *dev_priv = ring->dev->dev_private; |
acb868d3 | 2333 | struct drm_i915_gem_request *request; |
48e29f55 | 2334 | struct intel_ringbuffer *ringbuf; |
7d736f4f | 2335 | u32 request_ring_position, request_start; |
3cce469c CW |
2336 | int ret; |
2337 | ||
48e29f55 OM |
2338 | request = ring->preallocated_lazy_request; |
2339 | if (WARN_ON(request == NULL)) | |
2340 | return -ENOMEM; | |
2341 | ||
2342 | if (i915.enable_execlists) { | |
2343 | struct intel_context *ctx = request->ctx; | |
2344 | ringbuf = ctx->engine[ring->id].ringbuf; | |
2345 | } else | |
2346 | ringbuf = ring->buffer; | |
2347 | ||
2348 | request_start = intel_ring_get_tail(ringbuf); | |
cc889e0f DV |
2349 | /* |
2350 | * Emit any outstanding flushes - execbuf can fail to emit the flush | |
2351 | * after having emitted the batchbuffer command. Hence we need to fix | |
2352 | * things up similar to emitting the lazy request. The difference here | |
2353 | * is that the flush _must_ happen before the next request, no matter | |
2354 | * what. | |
2355 | */ | |
48e29f55 OM |
2356 | if (i915.enable_execlists) { |
2357 | ret = logical_ring_flush_all_caches(ringbuf); | |
2358 | if (ret) | |
2359 | return ret; | |
2360 | } else { | |
2361 | ret = intel_ring_flush_all_caches(ring); | |
2362 | if (ret) | |
2363 | return ret; | |
2364 | } | |
cc889e0f | 2365 | |
a71d8d94 CW |
2366 | /* Record the position of the start of the request so that |
2367 | * should we detect the updated seqno part-way through the | |
2368 | * GPU processing the request, we never over-estimate the | |
2369 | * position of the head. | |
2370 | */ | |
48e29f55 | 2371 | request_ring_position = intel_ring_get_tail(ringbuf); |
a71d8d94 | 2372 | |
48e29f55 OM |
2373 | if (i915.enable_execlists) { |
2374 | ret = ring->emit_request(ringbuf); | |
2375 | if (ret) | |
2376 | return ret; | |
2377 | } else { | |
2378 | ret = ring->add_request(ring); | |
2379 | if (ret) | |
2380 | return ret; | |
2381 | } | |
673a394b | 2382 | |
9d773091 | 2383 | request->seqno = intel_ring_get_seqno(ring); |
852835f3 | 2384 | request->ring = ring; |
7d736f4f | 2385 | request->head = request_start; |
a71d8d94 | 2386 | request->tail = request_ring_position; |
7d736f4f MK |
2387 | |
2388 | /* Whilst this request exists, batch_obj will be on the | |
2389 | * active_list, and so will hold the active reference. Only when this | |
2390 | * request is retired will the the batch_obj be moved onto the | |
2391 | * inactive_list and lose its active reference. Hence we do not need | |
2392 | * to explicitly hold another reference here. | |
2393 | */ | |
9a7e0c2a | 2394 | request->batch_obj = obj; |
0e50e96b | 2395 | |
48e29f55 OM |
2396 | if (!i915.enable_execlists) { |
2397 | /* Hold a reference to the current context so that we can inspect | |
2398 | * it later in case a hangcheck error event fires. | |
2399 | */ | |
2400 | request->ctx = ring->last_context; | |
2401 | if (request->ctx) | |
2402 | i915_gem_context_reference(request->ctx); | |
2403 | } | |
0e50e96b | 2404 | |
673a394b | 2405 | request->emitted_jiffies = jiffies; |
852835f3 | 2406 | list_add_tail(&request->list, &ring->request_list); |
3bb73aba | 2407 | request->file_priv = NULL; |
852835f3 | 2408 | |
db53a302 CW |
2409 | if (file) { |
2410 | struct drm_i915_file_private *file_priv = file->driver_priv; | |
2411 | ||
1c25595f | 2412 | spin_lock(&file_priv->mm.lock); |
f787a5f5 | 2413 | request->file_priv = file_priv; |
b962442e | 2414 | list_add_tail(&request->client_list, |
f787a5f5 | 2415 | &file_priv->mm.request_list); |
1c25595f | 2416 | spin_unlock(&file_priv->mm.lock); |
b962442e | 2417 | } |
673a394b | 2418 | |
9d773091 | 2419 | trace_i915_gem_request_add(ring, request->seqno); |
1823521d | 2420 | ring->outstanding_lazy_seqno = 0; |
3c0e234c | 2421 | ring->preallocated_lazy_request = NULL; |
db53a302 | 2422 | |
db1b76ca | 2423 | if (!dev_priv->ums.mm_suspended) { |
10cd45b6 MK |
2424 | i915_queue_hangcheck(ring->dev); |
2425 | ||
f62a0076 CW |
2426 | cancel_delayed_work_sync(&dev_priv->mm.idle_work); |
2427 | queue_delayed_work(dev_priv->wq, | |
2428 | &dev_priv->mm.retire_work, | |
2429 | round_jiffies_up_relative(HZ)); | |
2430 | intel_mark_busy(dev_priv->dev); | |
f65d9421 | 2431 | } |
cc889e0f | 2432 | |
acb868d3 | 2433 | if (out_seqno) |
9d773091 | 2434 | *out_seqno = request->seqno; |
3cce469c | 2435 | return 0; |
673a394b EA |
2436 | } |
2437 | ||
f787a5f5 CW |
2438 | static inline void |
2439 | i915_gem_request_remove_from_client(struct drm_i915_gem_request *request) | |
673a394b | 2440 | { |
1c25595f | 2441 | struct drm_i915_file_private *file_priv = request->file_priv; |
673a394b | 2442 | |
1c25595f CW |
2443 | if (!file_priv) |
2444 | return; | |
1c5d22f7 | 2445 | |
1c25595f | 2446 | spin_lock(&file_priv->mm.lock); |
b29c19b6 CW |
2447 | list_del(&request->client_list); |
2448 | request->file_priv = NULL; | |
1c25595f | 2449 | spin_unlock(&file_priv->mm.lock); |
673a394b | 2450 | } |
673a394b | 2451 | |
939fd762 | 2452 | static bool i915_context_is_banned(struct drm_i915_private *dev_priv, |
273497e5 | 2453 | const struct intel_context *ctx) |
be62acb4 | 2454 | { |
44e2c070 | 2455 | unsigned long elapsed; |
be62acb4 | 2456 | |
44e2c070 MK |
2457 | elapsed = get_seconds() - ctx->hang_stats.guilty_ts; |
2458 | ||
2459 | if (ctx->hang_stats.banned) | |
be62acb4 MK |
2460 | return true; |
2461 | ||
2462 | if (elapsed <= DRM_I915_CTX_BAN_PERIOD) { | |
ccc7bed0 | 2463 | if (!i915_gem_context_is_default(ctx)) { |
3fac8978 | 2464 | DRM_DEBUG("context hanging too fast, banning!\n"); |
ccc7bed0 | 2465 | return true; |
88b4aa87 MK |
2466 | } else if (i915_stop_ring_allow_ban(dev_priv)) { |
2467 | if (i915_stop_ring_allow_warn(dev_priv)) | |
2468 | DRM_ERROR("gpu hanging too fast, banning!\n"); | |
ccc7bed0 | 2469 | return true; |
3fac8978 | 2470 | } |
be62acb4 MK |
2471 | } |
2472 | ||
2473 | return false; | |
2474 | } | |
2475 | ||
939fd762 | 2476 | static void i915_set_reset_status(struct drm_i915_private *dev_priv, |
273497e5 | 2477 | struct intel_context *ctx, |
b6b0fac0 | 2478 | const bool guilty) |
aa60c664 | 2479 | { |
44e2c070 MK |
2480 | struct i915_ctx_hang_stats *hs; |
2481 | ||
2482 | if (WARN_ON(!ctx)) | |
2483 | return; | |
aa60c664 | 2484 | |
44e2c070 MK |
2485 | hs = &ctx->hang_stats; |
2486 | ||
2487 | if (guilty) { | |
939fd762 | 2488 | hs->banned = i915_context_is_banned(dev_priv, ctx); |
44e2c070 MK |
2489 | hs->batch_active++; |
2490 | hs->guilty_ts = get_seconds(); | |
2491 | } else { | |
2492 | hs->batch_pending++; | |
aa60c664 MK |
2493 | } |
2494 | } | |
2495 | ||
0e50e96b MK |
2496 | static void i915_gem_free_request(struct drm_i915_gem_request *request) |
2497 | { | |
2498 | list_del(&request->list); | |
2499 | i915_gem_request_remove_from_client(request); | |
2500 | ||
2501 | if (request->ctx) | |
2502 | i915_gem_context_unreference(request->ctx); | |
2503 | ||
2504 | kfree(request); | |
2505 | } | |
2506 | ||
8d9fc7fd | 2507 | struct drm_i915_gem_request * |
a4872ba6 | 2508 | i915_gem_find_active_request(struct intel_engine_cs *ring) |
9375e446 | 2509 | { |
4db080f9 | 2510 | struct drm_i915_gem_request *request; |
8d9fc7fd CW |
2511 | u32 completed_seqno; |
2512 | ||
2513 | completed_seqno = ring->get_seqno(ring, false); | |
4db080f9 CW |
2514 | |
2515 | list_for_each_entry(request, &ring->request_list, list) { | |
2516 | if (i915_seqno_passed(completed_seqno, request->seqno)) | |
2517 | continue; | |
aa60c664 | 2518 | |
b6b0fac0 | 2519 | return request; |
4db080f9 | 2520 | } |
b6b0fac0 MK |
2521 | |
2522 | return NULL; | |
2523 | } | |
2524 | ||
2525 | static void i915_gem_reset_ring_status(struct drm_i915_private *dev_priv, | |
a4872ba6 | 2526 | struct intel_engine_cs *ring) |
b6b0fac0 MK |
2527 | { |
2528 | struct drm_i915_gem_request *request; | |
2529 | bool ring_hung; | |
2530 | ||
8d9fc7fd | 2531 | request = i915_gem_find_active_request(ring); |
b6b0fac0 MK |
2532 | |
2533 | if (request == NULL) | |
2534 | return; | |
2535 | ||
2536 | ring_hung = ring->hangcheck.score >= HANGCHECK_SCORE_RING_HUNG; | |
2537 | ||
939fd762 | 2538 | i915_set_reset_status(dev_priv, request->ctx, ring_hung); |
b6b0fac0 MK |
2539 | |
2540 | list_for_each_entry_continue(request, &ring->request_list, list) | |
939fd762 | 2541 | i915_set_reset_status(dev_priv, request->ctx, false); |
4db080f9 | 2542 | } |
aa60c664 | 2543 | |
4db080f9 | 2544 | static void i915_gem_reset_ring_cleanup(struct drm_i915_private *dev_priv, |
a4872ba6 | 2545 | struct intel_engine_cs *ring) |
4db080f9 | 2546 | { |
dfaae392 | 2547 | while (!list_empty(&ring->active_list)) { |
05394f39 | 2548 | struct drm_i915_gem_object *obj; |
9375e446 | 2549 | |
05394f39 CW |
2550 | obj = list_first_entry(&ring->active_list, |
2551 | struct drm_i915_gem_object, | |
2552 | ring_list); | |
9375e446 | 2553 | |
05394f39 | 2554 | i915_gem_object_move_to_inactive(obj); |
673a394b | 2555 | } |
1d62beea BW |
2556 | |
2557 | /* | |
2558 | * We must free the requests after all the corresponding objects have | |
2559 | * been moved off active lists. Which is the same order as the normal | |
2560 | * retire_requests function does. This is important if object hold | |
2561 | * implicit references on things like e.g. ppgtt address spaces through | |
2562 | * the request. | |
2563 | */ | |
2564 | while (!list_empty(&ring->request_list)) { | |
2565 | struct drm_i915_gem_request *request; | |
2566 | ||
2567 | request = list_first_entry(&ring->request_list, | |
2568 | struct drm_i915_gem_request, | |
2569 | list); | |
2570 | ||
2571 | i915_gem_free_request(request); | |
2572 | } | |
e3efda49 | 2573 | |
cc9130be OM |
2574 | while (!list_empty(&ring->execlist_queue)) { |
2575 | struct intel_ctx_submit_request *submit_req; | |
2576 | ||
2577 | submit_req = list_first_entry(&ring->execlist_queue, | |
2578 | struct intel_ctx_submit_request, | |
2579 | execlist_link); | |
2580 | list_del(&submit_req->execlist_link); | |
2581 | intel_runtime_pm_put(dev_priv); | |
2582 | i915_gem_context_unreference(submit_req->ctx); | |
2583 | kfree(submit_req); | |
2584 | } | |
2585 | ||
e3efda49 CW |
2586 | /* These may not have been flush before the reset, do so now */ |
2587 | kfree(ring->preallocated_lazy_request); | |
2588 | ring->preallocated_lazy_request = NULL; | |
2589 | ring->outstanding_lazy_seqno = 0; | |
673a394b EA |
2590 | } |
2591 | ||
19b2dbde | 2592 | void i915_gem_restore_fences(struct drm_device *dev) |
312817a3 CW |
2593 | { |
2594 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2595 | int i; | |
2596 | ||
4b9de737 | 2597 | for (i = 0; i < dev_priv->num_fence_regs; i++) { |
312817a3 | 2598 | struct drm_i915_fence_reg *reg = &dev_priv->fence_regs[i]; |
7d2cb39c | 2599 | |
94a335db DV |
2600 | /* |
2601 | * Commit delayed tiling changes if we have an object still | |
2602 | * attached to the fence, otherwise just clear the fence. | |
2603 | */ | |
2604 | if (reg->obj) { | |
2605 | i915_gem_object_update_fence(reg->obj, reg, | |
2606 | reg->obj->tiling_mode); | |
2607 | } else { | |
2608 | i915_gem_write_fence(dev, i, NULL); | |
2609 | } | |
312817a3 CW |
2610 | } |
2611 | } | |
2612 | ||
069efc1d | 2613 | void i915_gem_reset(struct drm_device *dev) |
673a394b | 2614 | { |
77f01230 | 2615 | struct drm_i915_private *dev_priv = dev->dev_private; |
a4872ba6 | 2616 | struct intel_engine_cs *ring; |
1ec14ad3 | 2617 | int i; |
673a394b | 2618 | |
4db080f9 CW |
2619 | /* |
2620 | * Before we free the objects from the requests, we need to inspect | |
2621 | * them for finding the guilty party. As the requests only borrow | |
2622 | * their reference to the objects, the inspection must be done first. | |
2623 | */ | |
2624 | for_each_ring(ring, dev_priv, i) | |
2625 | i915_gem_reset_ring_status(dev_priv, ring); | |
2626 | ||
b4519513 | 2627 | for_each_ring(ring, dev_priv, i) |
4db080f9 | 2628 | i915_gem_reset_ring_cleanup(dev_priv, ring); |
dfaae392 | 2629 | |
acce9ffa BW |
2630 | i915_gem_context_reset(dev); |
2631 | ||
19b2dbde | 2632 | i915_gem_restore_fences(dev); |
673a394b EA |
2633 | } |
2634 | ||
2635 | /** | |
2636 | * This function clears the request list as sequence numbers are passed. | |
2637 | */ | |
1cf0ba14 | 2638 | void |
a4872ba6 | 2639 | i915_gem_retire_requests_ring(struct intel_engine_cs *ring) |
673a394b | 2640 | { |
673a394b EA |
2641 | uint32_t seqno; |
2642 | ||
db53a302 | 2643 | if (list_empty(&ring->request_list)) |
6c0594a3 KW |
2644 | return; |
2645 | ||
db53a302 | 2646 | WARN_ON(i915_verify_lists(ring->dev)); |
673a394b | 2647 | |
b2eadbc8 | 2648 | seqno = ring->get_seqno(ring, true); |
1ec14ad3 | 2649 | |
e9103038 CW |
2650 | /* Move any buffers on the active list that are no longer referenced |
2651 | * by the ringbuffer to the flushing/inactive lists as appropriate, | |
2652 | * before we free the context associated with the requests. | |
2653 | */ | |
2654 | while (!list_empty(&ring->active_list)) { | |
2655 | struct drm_i915_gem_object *obj; | |
2656 | ||
2657 | obj = list_first_entry(&ring->active_list, | |
2658 | struct drm_i915_gem_object, | |
2659 | ring_list); | |
2660 | ||
2661 | if (!i915_seqno_passed(seqno, obj->last_read_seqno)) | |
2662 | break; | |
2663 | ||
2664 | i915_gem_object_move_to_inactive(obj); | |
2665 | } | |
2666 | ||
2667 | ||
852835f3 | 2668 | while (!list_empty(&ring->request_list)) { |
673a394b | 2669 | struct drm_i915_gem_request *request; |
48e29f55 | 2670 | struct intel_ringbuffer *ringbuf; |
673a394b | 2671 | |
852835f3 | 2672 | request = list_first_entry(&ring->request_list, |
673a394b EA |
2673 | struct drm_i915_gem_request, |
2674 | list); | |
673a394b | 2675 | |
dfaae392 | 2676 | if (!i915_seqno_passed(seqno, request->seqno)) |
b84d5f0c CW |
2677 | break; |
2678 | ||
db53a302 | 2679 | trace_i915_gem_request_retire(ring, request->seqno); |
48e29f55 OM |
2680 | |
2681 | /* This is one of the few common intersection points | |
2682 | * between legacy ringbuffer submission and execlists: | |
2683 | * we need to tell them apart in order to find the correct | |
2684 | * ringbuffer to which the request belongs to. | |
2685 | */ | |
2686 | if (i915.enable_execlists) { | |
2687 | struct intel_context *ctx = request->ctx; | |
2688 | ringbuf = ctx->engine[ring->id].ringbuf; | |
2689 | } else | |
2690 | ringbuf = ring->buffer; | |
2691 | ||
a71d8d94 CW |
2692 | /* We know the GPU must have read the request to have |
2693 | * sent us the seqno + interrupt, so use the position | |
2694 | * of tail of the request to update the last known position | |
2695 | * of the GPU head. | |
2696 | */ | |
48e29f55 | 2697 | ringbuf->last_retired_head = request->tail; |
b84d5f0c | 2698 | |
0e50e96b | 2699 | i915_gem_free_request(request); |
b84d5f0c | 2700 | } |
673a394b | 2701 | |
db53a302 CW |
2702 | if (unlikely(ring->trace_irq_seqno && |
2703 | i915_seqno_passed(seqno, ring->trace_irq_seqno))) { | |
1ec14ad3 | 2704 | ring->irq_put(ring); |
db53a302 | 2705 | ring->trace_irq_seqno = 0; |
9d34e5db | 2706 | } |
23bc5982 | 2707 | |
db53a302 | 2708 | WARN_ON(i915_verify_lists(ring->dev)); |
673a394b EA |
2709 | } |
2710 | ||
b29c19b6 | 2711 | bool |
b09a1fec CW |
2712 | i915_gem_retire_requests(struct drm_device *dev) |
2713 | { | |
3e31c6c0 | 2714 | struct drm_i915_private *dev_priv = dev->dev_private; |
a4872ba6 | 2715 | struct intel_engine_cs *ring; |
b29c19b6 | 2716 | bool idle = true; |
1ec14ad3 | 2717 | int i; |
b09a1fec | 2718 | |
b29c19b6 | 2719 | for_each_ring(ring, dev_priv, i) { |
b4519513 | 2720 | i915_gem_retire_requests_ring(ring); |
b29c19b6 CW |
2721 | idle &= list_empty(&ring->request_list); |
2722 | } | |
2723 | ||
2724 | if (idle) | |
2725 | mod_delayed_work(dev_priv->wq, | |
2726 | &dev_priv->mm.idle_work, | |
2727 | msecs_to_jiffies(100)); | |
2728 | ||
2729 | return idle; | |
b09a1fec CW |
2730 | } |
2731 | ||
75ef9da2 | 2732 | static void |
673a394b EA |
2733 | i915_gem_retire_work_handler(struct work_struct *work) |
2734 | { | |
b29c19b6 CW |
2735 | struct drm_i915_private *dev_priv = |
2736 | container_of(work, typeof(*dev_priv), mm.retire_work.work); | |
2737 | struct drm_device *dev = dev_priv->dev; | |
0a58705b | 2738 | bool idle; |
673a394b | 2739 | |
891b48cf | 2740 | /* Come back later if the device is busy... */ |
b29c19b6 CW |
2741 | idle = false; |
2742 | if (mutex_trylock(&dev->struct_mutex)) { | |
2743 | idle = i915_gem_retire_requests(dev); | |
2744 | mutex_unlock(&dev->struct_mutex); | |
673a394b | 2745 | } |
b29c19b6 | 2746 | if (!idle) |
bcb45086 CW |
2747 | queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, |
2748 | round_jiffies_up_relative(HZ)); | |
b29c19b6 | 2749 | } |
0a58705b | 2750 | |
b29c19b6 CW |
2751 | static void |
2752 | i915_gem_idle_work_handler(struct work_struct *work) | |
2753 | { | |
2754 | struct drm_i915_private *dev_priv = | |
2755 | container_of(work, typeof(*dev_priv), mm.idle_work.work); | |
2756 | ||
2757 | intel_mark_idle(dev_priv->dev); | |
673a394b EA |
2758 | } |
2759 | ||
30dfebf3 DV |
2760 | /** |
2761 | * Ensures that an object will eventually get non-busy by flushing any required | |
2762 | * write domains, emitting any outstanding lazy request and retiring and | |
2763 | * completed requests. | |
2764 | */ | |
2765 | static int | |
2766 | i915_gem_object_flush_active(struct drm_i915_gem_object *obj) | |
2767 | { | |
2768 | int ret; | |
2769 | ||
2770 | if (obj->active) { | |
0201f1ec | 2771 | ret = i915_gem_check_olr(obj->ring, obj->last_read_seqno); |
30dfebf3 DV |
2772 | if (ret) |
2773 | return ret; | |
2774 | ||
30dfebf3 DV |
2775 | i915_gem_retire_requests_ring(obj->ring); |
2776 | } | |
2777 | ||
2778 | return 0; | |
2779 | } | |
2780 | ||
23ba4fd0 BW |
2781 | /** |
2782 | * i915_gem_wait_ioctl - implements DRM_IOCTL_I915_GEM_WAIT | |
2783 | * @DRM_IOCTL_ARGS: standard ioctl arguments | |
2784 | * | |
2785 | * Returns 0 if successful, else an error is returned with the remaining time in | |
2786 | * the timeout parameter. | |
2787 | * -ETIME: object is still busy after timeout | |
2788 | * -ERESTARTSYS: signal interrupted the wait | |
2789 | * -ENONENT: object doesn't exist | |
2790 | * Also possible, but rare: | |
2791 | * -EAGAIN: GPU wedged | |
2792 | * -ENOMEM: damn | |
2793 | * -ENODEV: Internal IRQ fail | |
2794 | * -E?: The add request failed | |
2795 | * | |
2796 | * The wait ioctl with a timeout of 0 reimplements the busy ioctl. With any | |
2797 | * non-zero timeout parameter the wait ioctl will wait for the given number of | |
2798 | * nanoseconds on an object becoming unbusy. Since the wait itself does so | |
2799 | * without holding struct_mutex the object may become re-busied before this | |
2800 | * function completes. A similar but shorter * race condition exists in the busy | |
2801 | * ioctl | |
2802 | */ | |
2803 | int | |
2804 | i915_gem_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *file) | |
2805 | { | |
3e31c6c0 | 2806 | struct drm_i915_private *dev_priv = dev->dev_private; |
23ba4fd0 BW |
2807 | struct drm_i915_gem_wait *args = data; |
2808 | struct drm_i915_gem_object *obj; | |
a4872ba6 | 2809 | struct intel_engine_cs *ring = NULL; |
f69061be | 2810 | unsigned reset_counter; |
23ba4fd0 BW |
2811 | u32 seqno = 0; |
2812 | int ret = 0; | |
2813 | ||
23ba4fd0 BW |
2814 | ret = i915_mutex_lock_interruptible(dev); |
2815 | if (ret) | |
2816 | return ret; | |
2817 | ||
2818 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->bo_handle)); | |
2819 | if (&obj->base == NULL) { | |
2820 | mutex_unlock(&dev->struct_mutex); | |
2821 | return -ENOENT; | |
2822 | } | |
2823 | ||
30dfebf3 DV |
2824 | /* Need to make sure the object gets inactive eventually. */ |
2825 | ret = i915_gem_object_flush_active(obj); | |
23ba4fd0 BW |
2826 | if (ret) |
2827 | goto out; | |
2828 | ||
2829 | if (obj->active) { | |
0201f1ec | 2830 | seqno = obj->last_read_seqno; |
23ba4fd0 BW |
2831 | ring = obj->ring; |
2832 | } | |
2833 | ||
2834 | if (seqno == 0) | |
2835 | goto out; | |
2836 | ||
23ba4fd0 | 2837 | /* Do this after OLR check to make sure we make forward progress polling |
5ed0bdf2 | 2838 | * on this IOCTL with a timeout <=0 (like busy ioctl) |
23ba4fd0 | 2839 | */ |
5ed0bdf2 | 2840 | if (args->timeout_ns <= 0) { |
23ba4fd0 BW |
2841 | ret = -ETIME; |
2842 | goto out; | |
2843 | } | |
2844 | ||
2845 | drm_gem_object_unreference(&obj->base); | |
f69061be | 2846 | reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter); |
23ba4fd0 BW |
2847 | mutex_unlock(&dev->struct_mutex); |
2848 | ||
5ed0bdf2 TG |
2849 | return __wait_seqno(ring, seqno, reset_counter, true, &args->timeout_ns, |
2850 | file->driver_priv); | |
23ba4fd0 BW |
2851 | |
2852 | out: | |
2853 | drm_gem_object_unreference(&obj->base); | |
2854 | mutex_unlock(&dev->struct_mutex); | |
2855 | return ret; | |
2856 | } | |
2857 | ||
5816d648 BW |
2858 | /** |
2859 | * i915_gem_object_sync - sync an object to a ring. | |
2860 | * | |
2861 | * @obj: object which may be in use on another ring. | |
2862 | * @to: ring we wish to use the object on. May be NULL. | |
2863 | * | |
2864 | * This code is meant to abstract object synchronization with the GPU. | |
2865 | * Calling with NULL implies synchronizing the object with the CPU | |
2866 | * rather than a particular GPU ring. | |
2867 | * | |
2868 | * Returns 0 if successful, else propagates up the lower layer error. | |
2869 | */ | |
2911a35b BW |
2870 | int |
2871 | i915_gem_object_sync(struct drm_i915_gem_object *obj, | |
a4872ba6 | 2872 | struct intel_engine_cs *to) |
2911a35b | 2873 | { |
a4872ba6 | 2874 | struct intel_engine_cs *from = obj->ring; |
2911a35b BW |
2875 | u32 seqno; |
2876 | int ret, idx; | |
2877 | ||
2878 | if (from == NULL || to == from) | |
2879 | return 0; | |
2880 | ||
5816d648 | 2881 | if (to == NULL || !i915_semaphore_is_enabled(obj->base.dev)) |
0201f1ec | 2882 | return i915_gem_object_wait_rendering(obj, false); |
2911a35b BW |
2883 | |
2884 | idx = intel_ring_sync_index(from, to); | |
2885 | ||
0201f1ec | 2886 | seqno = obj->last_read_seqno; |
ddd4dbc6 RV |
2887 | /* Optimization: Avoid semaphore sync when we are sure we already |
2888 | * waited for an object with higher seqno */ | |
ebc348b2 | 2889 | if (seqno <= from->semaphore.sync_seqno[idx]) |
2911a35b BW |
2890 | return 0; |
2891 | ||
b4aca010 BW |
2892 | ret = i915_gem_check_olr(obj->ring, seqno); |
2893 | if (ret) | |
2894 | return ret; | |
2911a35b | 2895 | |
b52b89da | 2896 | trace_i915_gem_ring_sync_to(from, to, seqno); |
ebc348b2 | 2897 | ret = to->semaphore.sync_to(to, from, seqno); |
e3a5a225 | 2898 | if (!ret) |
7b01e260 MK |
2899 | /* We use last_read_seqno because sync_to() |
2900 | * might have just caused seqno wrap under | |
2901 | * the radar. | |
2902 | */ | |
ebc348b2 | 2903 | from->semaphore.sync_seqno[idx] = obj->last_read_seqno; |
2911a35b | 2904 | |
e3a5a225 | 2905 | return ret; |
2911a35b BW |
2906 | } |
2907 | ||
b5ffc9bc CW |
2908 | static void i915_gem_object_finish_gtt(struct drm_i915_gem_object *obj) |
2909 | { | |
2910 | u32 old_write_domain, old_read_domains; | |
2911 | ||
b5ffc9bc CW |
2912 | /* Force a pagefault for domain tracking on next user access */ |
2913 | i915_gem_release_mmap(obj); | |
2914 | ||
b97c3d9c KP |
2915 | if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0) |
2916 | return; | |
2917 | ||
97c809fd CW |
2918 | /* Wait for any direct GTT access to complete */ |
2919 | mb(); | |
2920 | ||
b5ffc9bc CW |
2921 | old_read_domains = obj->base.read_domains; |
2922 | old_write_domain = obj->base.write_domain; | |
2923 | ||
2924 | obj->base.read_domains &= ~I915_GEM_DOMAIN_GTT; | |
2925 | obj->base.write_domain &= ~I915_GEM_DOMAIN_GTT; | |
2926 | ||
2927 | trace_i915_gem_object_change_domain(obj, | |
2928 | old_read_domains, | |
2929 | old_write_domain); | |
2930 | } | |
2931 | ||
07fe0b12 | 2932 | int i915_vma_unbind(struct i915_vma *vma) |
673a394b | 2933 | { |
07fe0b12 | 2934 | struct drm_i915_gem_object *obj = vma->obj; |
3e31c6c0 | 2935 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
43e28f09 | 2936 | int ret; |
673a394b | 2937 | |
07fe0b12 | 2938 | if (list_empty(&vma->vma_link)) |
673a394b EA |
2939 | return 0; |
2940 | ||
0ff501cb DV |
2941 | if (!drm_mm_node_allocated(&vma->node)) { |
2942 | i915_gem_vma_destroy(vma); | |
0ff501cb DV |
2943 | return 0; |
2944 | } | |
433544bd | 2945 | |
d7f46fc4 | 2946 | if (vma->pin_count) |
31d8d651 | 2947 | return -EBUSY; |
673a394b | 2948 | |
c4670ad0 CW |
2949 | BUG_ON(obj->pages == NULL); |
2950 | ||
a8198eea | 2951 | ret = i915_gem_object_finish_gpu(obj); |
1488fc08 | 2952 | if (ret) |
a8198eea CW |
2953 | return ret; |
2954 | /* Continue on if we fail due to EIO, the GPU is hung so we | |
2955 | * should be safe and we need to cleanup or else we might | |
2956 | * cause memory corruption through use-after-free. | |
2957 | */ | |
2958 | ||
1d1ef21d CW |
2959 | /* Throw away the active reference before moving to the unbound list */ |
2960 | i915_gem_object_retire(obj); | |
2961 | ||
8b1bc9b4 DV |
2962 | if (i915_is_ggtt(vma->vm)) { |
2963 | i915_gem_object_finish_gtt(obj); | |
5323fd04 | 2964 | |
8b1bc9b4 DV |
2965 | /* release the fence reg _after_ flushing */ |
2966 | ret = i915_gem_object_put_fence(obj); | |
2967 | if (ret) | |
2968 | return ret; | |
2969 | } | |
96b47b65 | 2970 | |
07fe0b12 | 2971 | trace_i915_vma_unbind(vma); |
db53a302 | 2972 | |
6f65e29a BW |
2973 | vma->unbind_vma(vma); |
2974 | ||
64bf9303 | 2975 | list_del_init(&vma->mm_list); |
5cacaac7 | 2976 | if (i915_is_ggtt(vma->vm)) |
e6a84468 | 2977 | obj->map_and_fenceable = false; |
673a394b | 2978 | |
2f633156 BW |
2979 | drm_mm_remove_node(&vma->node); |
2980 | i915_gem_vma_destroy(vma); | |
2981 | ||
2982 | /* Since the unbound list is global, only move to that list if | |
b93dab6e | 2983 | * no more VMAs exist. */ |
9490edb5 AR |
2984 | if (list_empty(&obj->vma_list)) { |
2985 | i915_gem_gtt_finish_object(obj); | |
2f633156 | 2986 | list_move_tail(&obj->global_list, &dev_priv->mm.unbound_list); |
9490edb5 | 2987 | } |
673a394b | 2988 | |
70903c3b CW |
2989 | /* And finally now the object is completely decoupled from this vma, |
2990 | * we can drop its hold on the backing storage and allow it to be | |
2991 | * reaped by the shrinker. | |
2992 | */ | |
2993 | i915_gem_object_unpin_pages(obj); | |
2994 | ||
88241785 | 2995 | return 0; |
54cf91dc CW |
2996 | } |
2997 | ||
b2da9fe5 | 2998 | int i915_gpu_idle(struct drm_device *dev) |
4df2faf4 | 2999 | { |
3e31c6c0 | 3000 | struct drm_i915_private *dev_priv = dev->dev_private; |
a4872ba6 | 3001 | struct intel_engine_cs *ring; |
1ec14ad3 | 3002 | int ret, i; |
4df2faf4 | 3003 | |
4df2faf4 | 3004 | /* Flush everything onto the inactive list. */ |
b4519513 | 3005 | for_each_ring(ring, dev_priv, i) { |
ecdb5fd8 TD |
3006 | if (!i915.enable_execlists) { |
3007 | ret = i915_switch_context(ring, ring->default_context); | |
3008 | if (ret) | |
3009 | return ret; | |
3010 | } | |
b6c7488d | 3011 | |
3e960501 | 3012 | ret = intel_ring_idle(ring); |
1ec14ad3 CW |
3013 | if (ret) |
3014 | return ret; | |
3015 | } | |
4df2faf4 | 3016 | |
8a1a49f9 | 3017 | return 0; |
4df2faf4 DV |
3018 | } |
3019 | ||
9ce079e4 CW |
3020 | static void i965_write_fence_reg(struct drm_device *dev, int reg, |
3021 | struct drm_i915_gem_object *obj) | |
de151cf6 | 3022 | { |
3e31c6c0 | 3023 | struct drm_i915_private *dev_priv = dev->dev_private; |
56c844e5 ID |
3024 | int fence_reg; |
3025 | int fence_pitch_shift; | |
de151cf6 | 3026 | |
56c844e5 ID |
3027 | if (INTEL_INFO(dev)->gen >= 6) { |
3028 | fence_reg = FENCE_REG_SANDYBRIDGE_0; | |
3029 | fence_pitch_shift = SANDYBRIDGE_FENCE_PITCH_SHIFT; | |
3030 | } else { | |
3031 | fence_reg = FENCE_REG_965_0; | |
3032 | fence_pitch_shift = I965_FENCE_PITCH_SHIFT; | |
3033 | } | |
3034 | ||
d18b9619 CW |
3035 | fence_reg += reg * 8; |
3036 | ||
3037 | /* To w/a incoherency with non-atomic 64-bit register updates, | |
3038 | * we split the 64-bit update into two 32-bit writes. In order | |
3039 | * for a partial fence not to be evaluated between writes, we | |
3040 | * precede the update with write to turn off the fence register, | |
3041 | * and only enable the fence as the last step. | |
3042 | * | |
3043 | * For extra levels of paranoia, we make sure each step lands | |
3044 | * before applying the next step. | |
3045 | */ | |
3046 | I915_WRITE(fence_reg, 0); | |
3047 | POSTING_READ(fence_reg); | |
3048 | ||
9ce079e4 | 3049 | if (obj) { |
f343c5f6 | 3050 | u32 size = i915_gem_obj_ggtt_size(obj); |
d18b9619 | 3051 | uint64_t val; |
de151cf6 | 3052 | |
f343c5f6 | 3053 | val = (uint64_t)((i915_gem_obj_ggtt_offset(obj) + size - 4096) & |
9ce079e4 | 3054 | 0xfffff000) << 32; |
f343c5f6 | 3055 | val |= i915_gem_obj_ggtt_offset(obj) & 0xfffff000; |
56c844e5 | 3056 | val |= (uint64_t)((obj->stride / 128) - 1) << fence_pitch_shift; |
9ce079e4 CW |
3057 | if (obj->tiling_mode == I915_TILING_Y) |
3058 | val |= 1 << I965_FENCE_TILING_Y_SHIFT; | |
3059 | val |= I965_FENCE_REG_VALID; | |
c6642782 | 3060 | |
d18b9619 CW |
3061 | I915_WRITE(fence_reg + 4, val >> 32); |
3062 | POSTING_READ(fence_reg + 4); | |
3063 | ||
3064 | I915_WRITE(fence_reg + 0, val); | |
3065 | POSTING_READ(fence_reg); | |
3066 | } else { | |
3067 | I915_WRITE(fence_reg + 4, 0); | |
3068 | POSTING_READ(fence_reg + 4); | |
3069 | } | |
de151cf6 JB |
3070 | } |
3071 | ||
9ce079e4 CW |
3072 | static void i915_write_fence_reg(struct drm_device *dev, int reg, |
3073 | struct drm_i915_gem_object *obj) | |
de151cf6 | 3074 | { |
3e31c6c0 | 3075 | struct drm_i915_private *dev_priv = dev->dev_private; |
9ce079e4 | 3076 | u32 val; |
de151cf6 | 3077 | |
9ce079e4 | 3078 | if (obj) { |
f343c5f6 | 3079 | u32 size = i915_gem_obj_ggtt_size(obj); |
9ce079e4 CW |
3080 | int pitch_val; |
3081 | int tile_width; | |
c6642782 | 3082 | |
f343c5f6 | 3083 | WARN((i915_gem_obj_ggtt_offset(obj) & ~I915_FENCE_START_MASK) || |
9ce079e4 | 3084 | (size & -size) != size || |
f343c5f6 BW |
3085 | (i915_gem_obj_ggtt_offset(obj) & (size - 1)), |
3086 | "object 0x%08lx [fenceable? %d] not 1M or pot-size (0x%08x) aligned\n", | |
3087 | i915_gem_obj_ggtt_offset(obj), obj->map_and_fenceable, size); | |
c6642782 | 3088 | |
9ce079e4 CW |
3089 | if (obj->tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev)) |
3090 | tile_width = 128; | |
3091 | else | |
3092 | tile_width = 512; | |
3093 | ||
3094 | /* Note: pitch better be a power of two tile widths */ | |
3095 | pitch_val = obj->stride / tile_width; | |
3096 | pitch_val = ffs(pitch_val) - 1; | |
3097 | ||
f343c5f6 | 3098 | val = i915_gem_obj_ggtt_offset(obj); |
9ce079e4 CW |
3099 | if (obj->tiling_mode == I915_TILING_Y) |
3100 | val |= 1 << I830_FENCE_TILING_Y_SHIFT; | |
3101 | val |= I915_FENCE_SIZE_BITS(size); | |
3102 | val |= pitch_val << I830_FENCE_PITCH_SHIFT; | |
3103 | val |= I830_FENCE_REG_VALID; | |
3104 | } else | |
3105 | val = 0; | |
3106 | ||
3107 | if (reg < 8) | |
3108 | reg = FENCE_REG_830_0 + reg * 4; | |
3109 | else | |
3110 | reg = FENCE_REG_945_8 + (reg - 8) * 4; | |
3111 | ||
3112 | I915_WRITE(reg, val); | |
3113 | POSTING_READ(reg); | |
de151cf6 JB |
3114 | } |
3115 | ||
9ce079e4 CW |
3116 | static void i830_write_fence_reg(struct drm_device *dev, int reg, |
3117 | struct drm_i915_gem_object *obj) | |
de151cf6 | 3118 | { |
3e31c6c0 | 3119 | struct drm_i915_private *dev_priv = dev->dev_private; |
de151cf6 | 3120 | uint32_t val; |
de151cf6 | 3121 | |
9ce079e4 | 3122 | if (obj) { |
f343c5f6 | 3123 | u32 size = i915_gem_obj_ggtt_size(obj); |
9ce079e4 | 3124 | uint32_t pitch_val; |
de151cf6 | 3125 | |
f343c5f6 | 3126 | WARN((i915_gem_obj_ggtt_offset(obj) & ~I830_FENCE_START_MASK) || |
9ce079e4 | 3127 | (size & -size) != size || |
f343c5f6 BW |
3128 | (i915_gem_obj_ggtt_offset(obj) & (size - 1)), |
3129 | "object 0x%08lx not 512K or pot-size 0x%08x aligned\n", | |
3130 | i915_gem_obj_ggtt_offset(obj), size); | |
e76a16de | 3131 | |
9ce079e4 CW |
3132 | pitch_val = obj->stride / 128; |
3133 | pitch_val = ffs(pitch_val) - 1; | |
de151cf6 | 3134 | |
f343c5f6 | 3135 | val = i915_gem_obj_ggtt_offset(obj); |
9ce079e4 CW |
3136 | if (obj->tiling_mode == I915_TILING_Y) |
3137 | val |= 1 << I830_FENCE_TILING_Y_SHIFT; | |
3138 | val |= I830_FENCE_SIZE_BITS(size); | |
3139 | val |= pitch_val << I830_FENCE_PITCH_SHIFT; | |
3140 | val |= I830_FENCE_REG_VALID; | |
3141 | } else | |
3142 | val = 0; | |
c6642782 | 3143 | |
9ce079e4 CW |
3144 | I915_WRITE(FENCE_REG_830_0 + reg * 4, val); |
3145 | POSTING_READ(FENCE_REG_830_0 + reg * 4); | |
3146 | } | |
3147 | ||
d0a57789 CW |
3148 | inline static bool i915_gem_object_needs_mb(struct drm_i915_gem_object *obj) |
3149 | { | |
3150 | return obj && obj->base.read_domains & I915_GEM_DOMAIN_GTT; | |
3151 | } | |
3152 | ||
9ce079e4 CW |
3153 | static void i915_gem_write_fence(struct drm_device *dev, int reg, |
3154 | struct drm_i915_gem_object *obj) | |
3155 | { | |
d0a57789 CW |
3156 | struct drm_i915_private *dev_priv = dev->dev_private; |
3157 | ||
3158 | /* Ensure that all CPU reads are completed before installing a fence | |
3159 | * and all writes before removing the fence. | |
3160 | */ | |
3161 | if (i915_gem_object_needs_mb(dev_priv->fence_regs[reg].obj)) | |
3162 | mb(); | |
3163 | ||
94a335db DV |
3164 | WARN(obj && (!obj->stride || !obj->tiling_mode), |
3165 | "bogus fence setup with stride: 0x%x, tiling mode: %i\n", | |
3166 | obj->stride, obj->tiling_mode); | |
3167 | ||
9ce079e4 | 3168 | switch (INTEL_INFO(dev)->gen) { |
5ab31333 | 3169 | case 8: |
9ce079e4 | 3170 | case 7: |
56c844e5 | 3171 | case 6: |
9ce079e4 CW |
3172 | case 5: |
3173 | case 4: i965_write_fence_reg(dev, reg, obj); break; | |
3174 | case 3: i915_write_fence_reg(dev, reg, obj); break; | |
3175 | case 2: i830_write_fence_reg(dev, reg, obj); break; | |
7dbf9d6e | 3176 | default: BUG(); |
9ce079e4 | 3177 | } |
d0a57789 CW |
3178 | |
3179 | /* And similarly be paranoid that no direct access to this region | |
3180 | * is reordered to before the fence is installed. | |
3181 | */ | |
3182 | if (i915_gem_object_needs_mb(obj)) | |
3183 | mb(); | |
de151cf6 JB |
3184 | } |
3185 | ||
61050808 CW |
3186 | static inline int fence_number(struct drm_i915_private *dev_priv, |
3187 | struct drm_i915_fence_reg *fence) | |
3188 | { | |
3189 | return fence - dev_priv->fence_regs; | |
3190 | } | |
3191 | ||
3192 | static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj, | |
3193 | struct drm_i915_fence_reg *fence, | |
3194 | bool enable) | |
3195 | { | |
2dc8aae0 | 3196 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
46a0b638 CW |
3197 | int reg = fence_number(dev_priv, fence); |
3198 | ||
3199 | i915_gem_write_fence(obj->base.dev, reg, enable ? obj : NULL); | |
61050808 CW |
3200 | |
3201 | if (enable) { | |
46a0b638 | 3202 | obj->fence_reg = reg; |
61050808 CW |
3203 | fence->obj = obj; |
3204 | list_move_tail(&fence->lru_list, &dev_priv->mm.fence_list); | |
3205 | } else { | |
3206 | obj->fence_reg = I915_FENCE_REG_NONE; | |
3207 | fence->obj = NULL; | |
3208 | list_del_init(&fence->lru_list); | |
3209 | } | |
94a335db | 3210 | obj->fence_dirty = false; |
61050808 CW |
3211 | } |
3212 | ||
d9e86c0e | 3213 | static int |
d0a57789 | 3214 | i915_gem_object_wait_fence(struct drm_i915_gem_object *obj) |
d9e86c0e | 3215 | { |
1c293ea3 | 3216 | if (obj->last_fenced_seqno) { |
86d5bc37 | 3217 | int ret = i915_wait_seqno(obj->ring, obj->last_fenced_seqno); |
18991845 CW |
3218 | if (ret) |
3219 | return ret; | |
d9e86c0e CW |
3220 | |
3221 | obj->last_fenced_seqno = 0; | |
d9e86c0e CW |
3222 | } |
3223 | ||
3224 | return 0; | |
3225 | } | |
3226 | ||
3227 | int | |
3228 | i915_gem_object_put_fence(struct drm_i915_gem_object *obj) | |
3229 | { | |
61050808 | 3230 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
f9c513e9 | 3231 | struct drm_i915_fence_reg *fence; |
d9e86c0e CW |
3232 | int ret; |
3233 | ||
d0a57789 | 3234 | ret = i915_gem_object_wait_fence(obj); |
d9e86c0e CW |
3235 | if (ret) |
3236 | return ret; | |
3237 | ||
61050808 CW |
3238 | if (obj->fence_reg == I915_FENCE_REG_NONE) |
3239 | return 0; | |
d9e86c0e | 3240 | |
f9c513e9 CW |
3241 | fence = &dev_priv->fence_regs[obj->fence_reg]; |
3242 | ||
aff10b30 DV |
3243 | if (WARN_ON(fence->pin_count)) |
3244 | return -EBUSY; | |
3245 | ||
61050808 | 3246 | i915_gem_object_fence_lost(obj); |
f9c513e9 | 3247 | i915_gem_object_update_fence(obj, fence, false); |
d9e86c0e CW |
3248 | |
3249 | return 0; | |
3250 | } | |
3251 | ||
3252 | static struct drm_i915_fence_reg * | |
a360bb1a | 3253 | i915_find_fence_reg(struct drm_device *dev) |
ae3db24a | 3254 | { |
ae3db24a | 3255 | struct drm_i915_private *dev_priv = dev->dev_private; |
8fe301ad | 3256 | struct drm_i915_fence_reg *reg, *avail; |
d9e86c0e | 3257 | int i; |
ae3db24a DV |
3258 | |
3259 | /* First try to find a free reg */ | |
d9e86c0e | 3260 | avail = NULL; |
ae3db24a DV |
3261 | for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) { |
3262 | reg = &dev_priv->fence_regs[i]; | |
3263 | if (!reg->obj) | |
d9e86c0e | 3264 | return reg; |
ae3db24a | 3265 | |
1690e1eb | 3266 | if (!reg->pin_count) |
d9e86c0e | 3267 | avail = reg; |
ae3db24a DV |
3268 | } |
3269 | ||
d9e86c0e | 3270 | if (avail == NULL) |
5dce5b93 | 3271 | goto deadlock; |
ae3db24a DV |
3272 | |
3273 | /* None available, try to steal one or wait for a user to finish */ | |
d9e86c0e | 3274 | list_for_each_entry(reg, &dev_priv->mm.fence_list, lru_list) { |
1690e1eb | 3275 | if (reg->pin_count) |
ae3db24a DV |
3276 | continue; |
3277 | ||
8fe301ad | 3278 | return reg; |
ae3db24a DV |
3279 | } |
3280 | ||
5dce5b93 CW |
3281 | deadlock: |
3282 | /* Wait for completion of pending flips which consume fences */ | |
3283 | if (intel_has_pending_fb_unpin(dev)) | |
3284 | return ERR_PTR(-EAGAIN); | |
3285 | ||
3286 | return ERR_PTR(-EDEADLK); | |
ae3db24a DV |
3287 | } |
3288 | ||
de151cf6 | 3289 | /** |
9a5a53b3 | 3290 | * i915_gem_object_get_fence - set up fencing for an object |
de151cf6 JB |
3291 | * @obj: object to map through a fence reg |
3292 | * | |
3293 | * When mapping objects through the GTT, userspace wants to be able to write | |
3294 | * to them without having to worry about swizzling if the object is tiled. | |
de151cf6 JB |
3295 | * This function walks the fence regs looking for a free one for @obj, |
3296 | * stealing one if it can't find any. | |
3297 | * | |
3298 | * It then sets up the reg based on the object's properties: address, pitch | |
3299 | * and tiling format. | |
9a5a53b3 CW |
3300 | * |
3301 | * For an untiled surface, this removes any existing fence. | |
de151cf6 | 3302 | */ |
8c4b8c3f | 3303 | int |
06d98131 | 3304 | i915_gem_object_get_fence(struct drm_i915_gem_object *obj) |
de151cf6 | 3305 | { |
05394f39 | 3306 | struct drm_device *dev = obj->base.dev; |
79e53945 | 3307 | struct drm_i915_private *dev_priv = dev->dev_private; |
14415745 | 3308 | bool enable = obj->tiling_mode != I915_TILING_NONE; |
d9e86c0e | 3309 | struct drm_i915_fence_reg *reg; |
ae3db24a | 3310 | int ret; |
de151cf6 | 3311 | |
14415745 CW |
3312 | /* Have we updated the tiling parameters upon the object and so |
3313 | * will need to serialise the write to the associated fence register? | |
3314 | */ | |
5d82e3e6 | 3315 | if (obj->fence_dirty) { |
d0a57789 | 3316 | ret = i915_gem_object_wait_fence(obj); |
14415745 CW |
3317 | if (ret) |
3318 | return ret; | |
3319 | } | |
9a5a53b3 | 3320 | |
d9e86c0e | 3321 | /* Just update our place in the LRU if our fence is getting reused. */ |
05394f39 CW |
3322 | if (obj->fence_reg != I915_FENCE_REG_NONE) { |
3323 | reg = &dev_priv->fence_regs[obj->fence_reg]; | |
5d82e3e6 | 3324 | if (!obj->fence_dirty) { |
14415745 CW |
3325 | list_move_tail(®->lru_list, |
3326 | &dev_priv->mm.fence_list); | |
3327 | return 0; | |
3328 | } | |
3329 | } else if (enable) { | |
e6a84468 CW |
3330 | if (WARN_ON(!obj->map_and_fenceable)) |
3331 | return -EINVAL; | |
3332 | ||
14415745 | 3333 | reg = i915_find_fence_reg(dev); |
5dce5b93 CW |
3334 | if (IS_ERR(reg)) |
3335 | return PTR_ERR(reg); | |
d9e86c0e | 3336 | |
14415745 CW |
3337 | if (reg->obj) { |
3338 | struct drm_i915_gem_object *old = reg->obj; | |
3339 | ||
d0a57789 | 3340 | ret = i915_gem_object_wait_fence(old); |
29c5a587 CW |
3341 | if (ret) |
3342 | return ret; | |
3343 | ||
14415745 | 3344 | i915_gem_object_fence_lost(old); |
29c5a587 | 3345 | } |
14415745 | 3346 | } else |
a09ba7fa | 3347 | return 0; |
a09ba7fa | 3348 | |
14415745 | 3349 | i915_gem_object_update_fence(obj, reg, enable); |
14415745 | 3350 | |
9ce079e4 | 3351 | return 0; |
de151cf6 JB |
3352 | } |
3353 | ||
4144f9b5 | 3354 | static bool i915_gem_valid_gtt_space(struct i915_vma *vma, |
42d6ab48 CW |
3355 | unsigned long cache_level) |
3356 | { | |
4144f9b5 | 3357 | struct drm_mm_node *gtt_space = &vma->node; |
42d6ab48 CW |
3358 | struct drm_mm_node *other; |
3359 | ||
4144f9b5 CW |
3360 | /* |
3361 | * On some machines we have to be careful when putting differing types | |
3362 | * of snoopable memory together to avoid the prefetcher crossing memory | |
3363 | * domains and dying. During vm initialisation, we decide whether or not | |
3364 | * these constraints apply and set the drm_mm.color_adjust | |
3365 | * appropriately. | |
42d6ab48 | 3366 | */ |
4144f9b5 | 3367 | if (vma->vm->mm.color_adjust == NULL) |
42d6ab48 CW |
3368 | return true; |
3369 | ||
c6cfb325 | 3370 | if (!drm_mm_node_allocated(gtt_space)) |
42d6ab48 CW |
3371 | return true; |
3372 | ||
3373 | if (list_empty(>t_space->node_list)) | |
3374 | return true; | |
3375 | ||
3376 | other = list_entry(gtt_space->node_list.prev, struct drm_mm_node, node_list); | |
3377 | if (other->allocated && !other->hole_follows && other->color != cache_level) | |
3378 | return false; | |
3379 | ||
3380 | other = list_entry(gtt_space->node_list.next, struct drm_mm_node, node_list); | |
3381 | if (other->allocated && !gtt_space->hole_follows && other->color != cache_level) | |
3382 | return false; | |
3383 | ||
3384 | return true; | |
3385 | } | |
3386 | ||
673a394b EA |
3387 | /** |
3388 | * Finds free space in the GTT aperture and binds the object there. | |
3389 | */ | |
262de145 | 3390 | static struct i915_vma * |
07fe0b12 BW |
3391 | i915_gem_object_bind_to_vm(struct drm_i915_gem_object *obj, |
3392 | struct i915_address_space *vm, | |
3393 | unsigned alignment, | |
d23db88c | 3394 | uint64_t flags) |
673a394b | 3395 | { |
05394f39 | 3396 | struct drm_device *dev = obj->base.dev; |
3e31c6c0 | 3397 | struct drm_i915_private *dev_priv = dev->dev_private; |
5e783301 | 3398 | u32 size, fence_size, fence_alignment, unfenced_alignment; |
d23db88c CW |
3399 | unsigned long start = |
3400 | flags & PIN_OFFSET_BIAS ? flags & PIN_OFFSET_MASK : 0; | |
3401 | unsigned long end = | |
1ec9e26d | 3402 | flags & PIN_MAPPABLE ? dev_priv->gtt.mappable_end : vm->total; |
2f633156 | 3403 | struct i915_vma *vma; |
07f73f69 | 3404 | int ret; |
673a394b | 3405 | |
e28f8711 CW |
3406 | fence_size = i915_gem_get_gtt_size(dev, |
3407 | obj->base.size, | |
3408 | obj->tiling_mode); | |
3409 | fence_alignment = i915_gem_get_gtt_alignment(dev, | |
3410 | obj->base.size, | |
d865110c | 3411 | obj->tiling_mode, true); |
e28f8711 | 3412 | unfenced_alignment = |
d865110c | 3413 | i915_gem_get_gtt_alignment(dev, |
1ec9e26d DV |
3414 | obj->base.size, |
3415 | obj->tiling_mode, false); | |
a00b10c3 | 3416 | |
673a394b | 3417 | if (alignment == 0) |
1ec9e26d | 3418 | alignment = flags & PIN_MAPPABLE ? fence_alignment : |
5e783301 | 3419 | unfenced_alignment; |
1ec9e26d | 3420 | if (flags & PIN_MAPPABLE && alignment & (fence_alignment - 1)) { |
bd9b6a4e | 3421 | DRM_DEBUG("Invalid object alignment requested %u\n", alignment); |
262de145 | 3422 | return ERR_PTR(-EINVAL); |
673a394b EA |
3423 | } |
3424 | ||
1ec9e26d | 3425 | size = flags & PIN_MAPPABLE ? fence_size : obj->base.size; |
a00b10c3 | 3426 | |
654fc607 CW |
3427 | /* If the object is bigger than the entire aperture, reject it early |
3428 | * before evicting everything in a vain attempt to find space. | |
3429 | */ | |
d23db88c CW |
3430 | if (obj->base.size > end) { |
3431 | DRM_DEBUG("Attempting to bind an object larger than the aperture: object=%zd > %s aperture=%lu\n", | |
a36689cb | 3432 | obj->base.size, |
1ec9e26d | 3433 | flags & PIN_MAPPABLE ? "mappable" : "total", |
d23db88c | 3434 | end); |
262de145 | 3435 | return ERR_PTR(-E2BIG); |
654fc607 CW |
3436 | } |
3437 | ||
37e680a1 | 3438 | ret = i915_gem_object_get_pages(obj); |
6c085a72 | 3439 | if (ret) |
262de145 | 3440 | return ERR_PTR(ret); |
6c085a72 | 3441 | |
fbdda6fb CW |
3442 | i915_gem_object_pin_pages(obj); |
3443 | ||
accfef2e | 3444 | vma = i915_gem_obj_lookup_or_create_vma(obj, vm); |
262de145 | 3445 | if (IS_ERR(vma)) |
bc6bc15b | 3446 | goto err_unpin; |
2f633156 | 3447 | |
0a9ae0d7 | 3448 | search_free: |
07fe0b12 | 3449 | ret = drm_mm_insert_node_in_range_generic(&vm->mm, &vma->node, |
0a9ae0d7 | 3450 | size, alignment, |
d23db88c CW |
3451 | obj->cache_level, |
3452 | start, end, | |
62347f9e LK |
3453 | DRM_MM_SEARCH_DEFAULT, |
3454 | DRM_MM_CREATE_DEFAULT); | |
dc9dd7a2 | 3455 | if (ret) { |
f6cd1f15 | 3456 | ret = i915_gem_evict_something(dev, vm, size, alignment, |
d23db88c CW |
3457 | obj->cache_level, |
3458 | start, end, | |
3459 | flags); | |
dc9dd7a2 CW |
3460 | if (ret == 0) |
3461 | goto search_free; | |
9731129c | 3462 | |
bc6bc15b | 3463 | goto err_free_vma; |
673a394b | 3464 | } |
4144f9b5 | 3465 | if (WARN_ON(!i915_gem_valid_gtt_space(vma, obj->cache_level))) { |
2f633156 | 3466 | ret = -EINVAL; |
bc6bc15b | 3467 | goto err_remove_node; |
673a394b EA |
3468 | } |
3469 | ||
74163907 | 3470 | ret = i915_gem_gtt_prepare_object(obj); |
2f633156 | 3471 | if (ret) |
bc6bc15b | 3472 | goto err_remove_node; |
673a394b | 3473 | |
35c20a60 | 3474 | list_move_tail(&obj->global_list, &dev_priv->mm.bound_list); |
ca191b13 | 3475 | list_add_tail(&vma->mm_list, &vm->inactive_list); |
bf1a1092 | 3476 | |
4bd561b3 BW |
3477 | if (i915_is_ggtt(vm)) { |
3478 | bool mappable, fenceable; | |
a00b10c3 | 3479 | |
49987099 DV |
3480 | fenceable = (vma->node.size == fence_size && |
3481 | (vma->node.start & (fence_alignment - 1)) == 0); | |
4bd561b3 | 3482 | |
49987099 DV |
3483 | mappable = (vma->node.start + obj->base.size <= |
3484 | dev_priv->gtt.mappable_end); | |
a00b10c3 | 3485 | |
5cacaac7 | 3486 | obj->map_and_fenceable = mappable && fenceable; |
4bd561b3 | 3487 | } |
75e9e915 | 3488 | |
1ec9e26d | 3489 | WARN_ON(flags & PIN_MAPPABLE && !obj->map_and_fenceable); |
75e9e915 | 3490 | |
1ec9e26d | 3491 | trace_i915_vma_bind(vma, flags); |
8ea99c92 DV |
3492 | vma->bind_vma(vma, obj->cache_level, |
3493 | flags & (PIN_MAPPABLE | PIN_GLOBAL) ? GLOBAL_BIND : 0); | |
3494 | ||
262de145 | 3495 | return vma; |
2f633156 | 3496 | |
bc6bc15b | 3497 | err_remove_node: |
6286ef9b | 3498 | drm_mm_remove_node(&vma->node); |
bc6bc15b | 3499 | err_free_vma: |
2f633156 | 3500 | i915_gem_vma_destroy(vma); |
262de145 | 3501 | vma = ERR_PTR(ret); |
bc6bc15b | 3502 | err_unpin: |
2f633156 | 3503 | i915_gem_object_unpin_pages(obj); |
262de145 | 3504 | return vma; |
673a394b EA |
3505 | } |
3506 | ||
000433b6 | 3507 | bool |
2c22569b CW |
3508 | i915_gem_clflush_object(struct drm_i915_gem_object *obj, |
3509 | bool force) | |
673a394b | 3510 | { |
673a394b EA |
3511 | /* If we don't have a page list set up, then we're not pinned |
3512 | * to GPU, and we can ignore the cache flush because it'll happen | |
3513 | * again at bind time. | |
3514 | */ | |
05394f39 | 3515 | if (obj->pages == NULL) |
000433b6 | 3516 | return false; |
673a394b | 3517 | |
769ce464 ID |
3518 | /* |
3519 | * Stolen memory is always coherent with the GPU as it is explicitly | |
3520 | * marked as wc by the system, or the system is cache-coherent. | |
3521 | */ | |
3522 | if (obj->stolen) | |
000433b6 | 3523 | return false; |
769ce464 | 3524 | |
9c23f7fc CW |
3525 | /* If the GPU is snooping the contents of the CPU cache, |
3526 | * we do not need to manually clear the CPU cache lines. However, | |
3527 | * the caches are only snooped when the render cache is | |
3528 | * flushed/invalidated. As we always have to emit invalidations | |
3529 | * and flushes when moving into and out of the RENDER domain, correct | |
3530 | * snooping behaviour occurs naturally as the result of our domain | |
3531 | * tracking. | |
3532 | */ | |
2c22569b | 3533 | if (!force && cpu_cache_is_coherent(obj->base.dev, obj->cache_level)) |
000433b6 | 3534 | return false; |
9c23f7fc | 3535 | |
1c5d22f7 | 3536 | trace_i915_gem_object_clflush(obj); |
9da3da66 | 3537 | drm_clflush_sg(obj->pages); |
000433b6 CW |
3538 | |
3539 | return true; | |
e47c68e9 EA |
3540 | } |
3541 | ||
3542 | /** Flushes the GTT write domain for the object if it's dirty. */ | |
3543 | static void | |
05394f39 | 3544 | i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj) |
e47c68e9 | 3545 | { |
1c5d22f7 CW |
3546 | uint32_t old_write_domain; |
3547 | ||
05394f39 | 3548 | if (obj->base.write_domain != I915_GEM_DOMAIN_GTT) |
e47c68e9 EA |
3549 | return; |
3550 | ||
63256ec5 | 3551 | /* No actual flushing is required for the GTT write domain. Writes |
e47c68e9 EA |
3552 | * to it immediately go to main memory as far as we know, so there's |
3553 | * no chipset flush. It also doesn't land in render cache. | |
63256ec5 CW |
3554 | * |
3555 | * However, we do have to enforce the order so that all writes through | |
3556 | * the GTT land before any writes to the device, such as updates to | |
3557 | * the GATT itself. | |
e47c68e9 | 3558 | */ |
63256ec5 CW |
3559 | wmb(); |
3560 | ||
05394f39 CW |
3561 | old_write_domain = obj->base.write_domain; |
3562 | obj->base.write_domain = 0; | |
1c5d22f7 | 3563 | |
f99d7069 DV |
3564 | intel_fb_obj_flush(obj, false); |
3565 | ||
1c5d22f7 | 3566 | trace_i915_gem_object_change_domain(obj, |
05394f39 | 3567 | obj->base.read_domains, |
1c5d22f7 | 3568 | old_write_domain); |
e47c68e9 EA |
3569 | } |
3570 | ||
3571 | /** Flushes the CPU write domain for the object if it's dirty. */ | |
3572 | static void | |
2c22569b CW |
3573 | i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj, |
3574 | bool force) | |
e47c68e9 | 3575 | { |
1c5d22f7 | 3576 | uint32_t old_write_domain; |
e47c68e9 | 3577 | |
05394f39 | 3578 | if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) |
e47c68e9 EA |
3579 | return; |
3580 | ||
000433b6 CW |
3581 | if (i915_gem_clflush_object(obj, force)) |
3582 | i915_gem_chipset_flush(obj->base.dev); | |
3583 | ||
05394f39 CW |
3584 | old_write_domain = obj->base.write_domain; |
3585 | obj->base.write_domain = 0; | |
1c5d22f7 | 3586 | |
f99d7069 DV |
3587 | intel_fb_obj_flush(obj, false); |
3588 | ||
1c5d22f7 | 3589 | trace_i915_gem_object_change_domain(obj, |
05394f39 | 3590 | obj->base.read_domains, |
1c5d22f7 | 3591 | old_write_domain); |
e47c68e9 EA |
3592 | } |
3593 | ||
2ef7eeaa EA |
3594 | /** |
3595 | * Moves a single object to the GTT read, and possibly write domain. | |
3596 | * | |
3597 | * This function returns when the move is complete, including waiting on | |
3598 | * flushes to occur. | |
3599 | */ | |
79e53945 | 3600 | int |
2021746e | 3601 | i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write) |
2ef7eeaa | 3602 | { |
3e31c6c0 | 3603 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
dc8cd1e7 | 3604 | struct i915_vma *vma = i915_gem_obj_to_ggtt(obj); |
1c5d22f7 | 3605 | uint32_t old_write_domain, old_read_domains; |
e47c68e9 | 3606 | int ret; |
2ef7eeaa | 3607 | |
02354392 | 3608 | /* Not valid to be called on unbound objects. */ |
dc8cd1e7 | 3609 | if (vma == NULL) |
02354392 EA |
3610 | return -EINVAL; |
3611 | ||
8d7e3de1 CW |
3612 | if (obj->base.write_domain == I915_GEM_DOMAIN_GTT) |
3613 | return 0; | |
3614 | ||
0201f1ec | 3615 | ret = i915_gem_object_wait_rendering(obj, !write); |
88241785 CW |
3616 | if (ret) |
3617 | return ret; | |
3618 | ||
c8725f3d | 3619 | i915_gem_object_retire(obj); |
2c22569b | 3620 | i915_gem_object_flush_cpu_write_domain(obj, false); |
1c5d22f7 | 3621 | |
d0a57789 CW |
3622 | /* Serialise direct access to this object with the barriers for |
3623 | * coherent writes from the GPU, by effectively invalidating the | |
3624 | * GTT domain upon first access. | |
3625 | */ | |
3626 | if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0) | |
3627 | mb(); | |
3628 | ||
05394f39 CW |
3629 | old_write_domain = obj->base.write_domain; |
3630 | old_read_domains = obj->base.read_domains; | |
1c5d22f7 | 3631 | |
e47c68e9 EA |
3632 | /* It should now be out of any other write domains, and we can update |
3633 | * the domain values for our changes. | |
3634 | */ | |
05394f39 CW |
3635 | BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) != 0); |
3636 | obj->base.read_domains |= I915_GEM_DOMAIN_GTT; | |
e47c68e9 | 3637 | if (write) { |
05394f39 CW |
3638 | obj->base.read_domains = I915_GEM_DOMAIN_GTT; |
3639 | obj->base.write_domain = I915_GEM_DOMAIN_GTT; | |
3640 | obj->dirty = 1; | |
2ef7eeaa EA |
3641 | } |
3642 | ||
f99d7069 DV |
3643 | if (write) |
3644 | intel_fb_obj_invalidate(obj, NULL); | |
3645 | ||
1c5d22f7 CW |
3646 | trace_i915_gem_object_change_domain(obj, |
3647 | old_read_domains, | |
3648 | old_write_domain); | |
3649 | ||
8325a09d | 3650 | /* And bump the LRU for this access */ |
dc8cd1e7 CW |
3651 | if (i915_gem_object_is_inactive(obj)) |
3652 | list_move_tail(&vma->mm_list, | |
3653 | &dev_priv->gtt.base.inactive_list); | |
8325a09d | 3654 | |
e47c68e9 EA |
3655 | return 0; |
3656 | } | |
3657 | ||
e4ffd173 CW |
3658 | int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj, |
3659 | enum i915_cache_level cache_level) | |
3660 | { | |
7bddb01f | 3661 | struct drm_device *dev = obj->base.dev; |
df6f783a | 3662 | struct i915_vma *vma, *next; |
e4ffd173 CW |
3663 | int ret; |
3664 | ||
3665 | if (obj->cache_level == cache_level) | |
3666 | return 0; | |
3667 | ||
d7f46fc4 | 3668 | if (i915_gem_obj_is_pinned(obj)) { |
e4ffd173 CW |
3669 | DRM_DEBUG("can not change the cache level of pinned objects\n"); |
3670 | return -EBUSY; | |
3671 | } | |
3672 | ||
df6f783a | 3673 | list_for_each_entry_safe(vma, next, &obj->vma_list, vma_link) { |
4144f9b5 | 3674 | if (!i915_gem_valid_gtt_space(vma, cache_level)) { |
07fe0b12 | 3675 | ret = i915_vma_unbind(vma); |
3089c6f2 BW |
3676 | if (ret) |
3677 | return ret; | |
3089c6f2 | 3678 | } |
42d6ab48 CW |
3679 | } |
3680 | ||
3089c6f2 | 3681 | if (i915_gem_obj_bound_any(obj)) { |
e4ffd173 CW |
3682 | ret = i915_gem_object_finish_gpu(obj); |
3683 | if (ret) | |
3684 | return ret; | |
3685 | ||
3686 | i915_gem_object_finish_gtt(obj); | |
3687 | ||
3688 | /* Before SandyBridge, you could not use tiling or fence | |
3689 | * registers with snooped memory, so relinquish any fences | |
3690 | * currently pointing to our region in the aperture. | |
3691 | */ | |
42d6ab48 | 3692 | if (INTEL_INFO(dev)->gen < 6) { |
e4ffd173 CW |
3693 | ret = i915_gem_object_put_fence(obj); |
3694 | if (ret) | |
3695 | return ret; | |
3696 | } | |
3697 | ||
6f65e29a | 3698 | list_for_each_entry(vma, &obj->vma_list, vma_link) |
8ea99c92 DV |
3699 | if (drm_mm_node_allocated(&vma->node)) |
3700 | vma->bind_vma(vma, cache_level, | |
3701 | obj->has_global_gtt_mapping ? GLOBAL_BIND : 0); | |
e4ffd173 CW |
3702 | } |
3703 | ||
2c22569b CW |
3704 | list_for_each_entry(vma, &obj->vma_list, vma_link) |
3705 | vma->node.color = cache_level; | |
3706 | obj->cache_level = cache_level; | |
3707 | ||
3708 | if (cpu_write_needs_clflush(obj)) { | |
e4ffd173 CW |
3709 | u32 old_read_domains, old_write_domain; |
3710 | ||
3711 | /* If we're coming from LLC cached, then we haven't | |
3712 | * actually been tracking whether the data is in the | |
3713 | * CPU cache or not, since we only allow one bit set | |
3714 | * in obj->write_domain and have been skipping the clflushes. | |
3715 | * Just set it to the CPU cache for now. | |
3716 | */ | |
c8725f3d | 3717 | i915_gem_object_retire(obj); |
e4ffd173 | 3718 | WARN_ON(obj->base.write_domain & ~I915_GEM_DOMAIN_CPU); |
e4ffd173 CW |
3719 | |
3720 | old_read_domains = obj->base.read_domains; | |
3721 | old_write_domain = obj->base.write_domain; | |
3722 | ||
3723 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; | |
3724 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; | |
3725 | ||
3726 | trace_i915_gem_object_change_domain(obj, | |
3727 | old_read_domains, | |
3728 | old_write_domain); | |
3729 | } | |
3730 | ||
e4ffd173 CW |
3731 | return 0; |
3732 | } | |
3733 | ||
199adf40 BW |
3734 | int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data, |
3735 | struct drm_file *file) | |
e6994aee | 3736 | { |
199adf40 | 3737 | struct drm_i915_gem_caching *args = data; |
e6994aee CW |
3738 | struct drm_i915_gem_object *obj; |
3739 | int ret; | |
3740 | ||
3741 | ret = i915_mutex_lock_interruptible(dev); | |
3742 | if (ret) | |
3743 | return ret; | |
3744 | ||
3745 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); | |
3746 | if (&obj->base == NULL) { | |
3747 | ret = -ENOENT; | |
3748 | goto unlock; | |
3749 | } | |
3750 | ||
651d794f CW |
3751 | switch (obj->cache_level) { |
3752 | case I915_CACHE_LLC: | |
3753 | case I915_CACHE_L3_LLC: | |
3754 | args->caching = I915_CACHING_CACHED; | |
3755 | break; | |
3756 | ||
4257d3ba CW |
3757 | case I915_CACHE_WT: |
3758 | args->caching = I915_CACHING_DISPLAY; | |
3759 | break; | |
3760 | ||
651d794f CW |
3761 | default: |
3762 | args->caching = I915_CACHING_NONE; | |
3763 | break; | |
3764 | } | |
e6994aee CW |
3765 | |
3766 | drm_gem_object_unreference(&obj->base); | |
3767 | unlock: | |
3768 | mutex_unlock(&dev->struct_mutex); | |
3769 | return ret; | |
3770 | } | |
3771 | ||
199adf40 BW |
3772 | int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data, |
3773 | struct drm_file *file) | |
e6994aee | 3774 | { |
199adf40 | 3775 | struct drm_i915_gem_caching *args = data; |
e6994aee CW |
3776 | struct drm_i915_gem_object *obj; |
3777 | enum i915_cache_level level; | |
3778 | int ret; | |
3779 | ||
199adf40 BW |
3780 | switch (args->caching) { |
3781 | case I915_CACHING_NONE: | |
e6994aee CW |
3782 | level = I915_CACHE_NONE; |
3783 | break; | |
199adf40 | 3784 | case I915_CACHING_CACHED: |
e6994aee CW |
3785 | level = I915_CACHE_LLC; |
3786 | break; | |
4257d3ba CW |
3787 | case I915_CACHING_DISPLAY: |
3788 | level = HAS_WT(dev) ? I915_CACHE_WT : I915_CACHE_NONE; | |
3789 | break; | |
e6994aee CW |
3790 | default: |
3791 | return -EINVAL; | |
3792 | } | |
3793 | ||
3bc2913e BW |
3794 | ret = i915_mutex_lock_interruptible(dev); |
3795 | if (ret) | |
3796 | return ret; | |
3797 | ||
e6994aee CW |
3798 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
3799 | if (&obj->base == NULL) { | |
3800 | ret = -ENOENT; | |
3801 | goto unlock; | |
3802 | } | |
3803 | ||
3804 | ret = i915_gem_object_set_cache_level(obj, level); | |
3805 | ||
3806 | drm_gem_object_unreference(&obj->base); | |
3807 | unlock: | |
3808 | mutex_unlock(&dev->struct_mutex); | |
3809 | return ret; | |
3810 | } | |
3811 | ||
cc98b413 CW |
3812 | static bool is_pin_display(struct drm_i915_gem_object *obj) |
3813 | { | |
19656430 OM |
3814 | struct i915_vma *vma; |
3815 | ||
19656430 OM |
3816 | vma = i915_gem_obj_to_ggtt(obj); |
3817 | if (!vma) | |
3818 | return false; | |
3819 | ||
cc98b413 CW |
3820 | /* There are 3 sources that pin objects: |
3821 | * 1. The display engine (scanouts, sprites, cursors); | |
3822 | * 2. Reservations for execbuffer; | |
3823 | * 3. The user. | |
3824 | * | |
3825 | * We can ignore reservations as we hold the struct_mutex and | |
3826 | * are only called outside of the reservation path. The user | |
3827 | * can only increment pin_count once, and so if after | |
3828 | * subtracting the potential reference by the user, any pin_count | |
3829 | * remains, it must be due to another use by the display engine. | |
3830 | */ | |
19656430 | 3831 | return vma->pin_count - !!obj->user_pin_count; |
cc98b413 CW |
3832 | } |
3833 | ||
b9241ea3 | 3834 | /* |
2da3b9b9 CW |
3835 | * Prepare buffer for display plane (scanout, cursors, etc). |
3836 | * Can be called from an uninterruptible phase (modesetting) and allows | |
3837 | * any flushes to be pipelined (for pageflips). | |
b9241ea3 ZW |
3838 | */ |
3839 | int | |
2da3b9b9 CW |
3840 | i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj, |
3841 | u32 alignment, | |
a4872ba6 | 3842 | struct intel_engine_cs *pipelined) |
b9241ea3 | 3843 | { |
2da3b9b9 | 3844 | u32 old_read_domains, old_write_domain; |
19656430 | 3845 | bool was_pin_display; |
b9241ea3 ZW |
3846 | int ret; |
3847 | ||
0be73284 | 3848 | if (pipelined != obj->ring) { |
2911a35b BW |
3849 | ret = i915_gem_object_sync(obj, pipelined); |
3850 | if (ret) | |
b9241ea3 ZW |
3851 | return ret; |
3852 | } | |
3853 | ||
cc98b413 CW |
3854 | /* Mark the pin_display early so that we account for the |
3855 | * display coherency whilst setting up the cache domains. | |
3856 | */ | |
19656430 | 3857 | was_pin_display = obj->pin_display; |
cc98b413 CW |
3858 | obj->pin_display = true; |
3859 | ||
a7ef0640 EA |
3860 | /* The display engine is not coherent with the LLC cache on gen6. As |
3861 | * a result, we make sure that the pinning that is about to occur is | |
3862 | * done with uncached PTEs. This is lowest common denominator for all | |
3863 | * chipsets. | |
3864 | * | |
3865 | * However for gen6+, we could do better by using the GFDT bit instead | |
3866 | * of uncaching, which would allow us to flush all the LLC-cached data | |
3867 | * with that bit in the PTE to main memory with just one PIPE_CONTROL. | |
3868 | */ | |
651d794f CW |
3869 | ret = i915_gem_object_set_cache_level(obj, |
3870 | HAS_WT(obj->base.dev) ? I915_CACHE_WT : I915_CACHE_NONE); | |
a7ef0640 | 3871 | if (ret) |
cc98b413 | 3872 | goto err_unpin_display; |
a7ef0640 | 3873 | |
2da3b9b9 CW |
3874 | /* As the user may map the buffer once pinned in the display plane |
3875 | * (e.g. libkms for the bootup splash), we have to ensure that we | |
3876 | * always use map_and_fenceable for all scanout buffers. | |
3877 | */ | |
1ec9e26d | 3878 | ret = i915_gem_obj_ggtt_pin(obj, alignment, PIN_MAPPABLE); |
2da3b9b9 | 3879 | if (ret) |
cc98b413 | 3880 | goto err_unpin_display; |
2da3b9b9 | 3881 | |
2c22569b | 3882 | i915_gem_object_flush_cpu_write_domain(obj, true); |
b118c1e3 | 3883 | |
2da3b9b9 | 3884 | old_write_domain = obj->base.write_domain; |
05394f39 | 3885 | old_read_domains = obj->base.read_domains; |
2da3b9b9 CW |
3886 | |
3887 | /* It should now be out of any other write domains, and we can update | |
3888 | * the domain values for our changes. | |
3889 | */ | |
e5f1d962 | 3890 | obj->base.write_domain = 0; |
05394f39 | 3891 | obj->base.read_domains |= I915_GEM_DOMAIN_GTT; |
b9241ea3 ZW |
3892 | |
3893 | trace_i915_gem_object_change_domain(obj, | |
3894 | old_read_domains, | |
2da3b9b9 | 3895 | old_write_domain); |
b9241ea3 ZW |
3896 | |
3897 | return 0; | |
cc98b413 CW |
3898 | |
3899 | err_unpin_display: | |
19656430 OM |
3900 | WARN_ON(was_pin_display != is_pin_display(obj)); |
3901 | obj->pin_display = was_pin_display; | |
cc98b413 CW |
3902 | return ret; |
3903 | } | |
3904 | ||
3905 | void | |
3906 | i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object *obj) | |
3907 | { | |
d7f46fc4 | 3908 | i915_gem_object_ggtt_unpin(obj); |
cc98b413 | 3909 | obj->pin_display = is_pin_display(obj); |
b9241ea3 ZW |
3910 | } |
3911 | ||
85345517 | 3912 | int |
a8198eea | 3913 | i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj) |
85345517 | 3914 | { |
88241785 CW |
3915 | int ret; |
3916 | ||
a8198eea | 3917 | if ((obj->base.read_domains & I915_GEM_GPU_DOMAINS) == 0) |
85345517 CW |
3918 | return 0; |
3919 | ||
0201f1ec | 3920 | ret = i915_gem_object_wait_rendering(obj, false); |
c501ae7f CW |
3921 | if (ret) |
3922 | return ret; | |
3923 | ||
a8198eea CW |
3924 | /* Ensure that we invalidate the GPU's caches and TLBs. */ |
3925 | obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS; | |
c501ae7f | 3926 | return 0; |
85345517 CW |
3927 | } |
3928 | ||
e47c68e9 EA |
3929 | /** |
3930 | * Moves a single object to the CPU read, and possibly write domain. | |
3931 | * | |
3932 | * This function returns when the move is complete, including waiting on | |
3933 | * flushes to occur. | |
3934 | */ | |
dabdfe02 | 3935 | int |
919926ae | 3936 | i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write) |
e47c68e9 | 3937 | { |
1c5d22f7 | 3938 | uint32_t old_write_domain, old_read_domains; |
e47c68e9 EA |
3939 | int ret; |
3940 | ||
8d7e3de1 CW |
3941 | if (obj->base.write_domain == I915_GEM_DOMAIN_CPU) |
3942 | return 0; | |
3943 | ||
0201f1ec | 3944 | ret = i915_gem_object_wait_rendering(obj, !write); |
88241785 CW |
3945 | if (ret) |
3946 | return ret; | |
3947 | ||
c8725f3d | 3948 | i915_gem_object_retire(obj); |
e47c68e9 | 3949 | i915_gem_object_flush_gtt_write_domain(obj); |
2ef7eeaa | 3950 | |
05394f39 CW |
3951 | old_write_domain = obj->base.write_domain; |
3952 | old_read_domains = obj->base.read_domains; | |
1c5d22f7 | 3953 | |
e47c68e9 | 3954 | /* Flush the CPU cache if it's still invalid. */ |
05394f39 | 3955 | if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) { |
2c22569b | 3956 | i915_gem_clflush_object(obj, false); |
2ef7eeaa | 3957 | |
05394f39 | 3958 | obj->base.read_domains |= I915_GEM_DOMAIN_CPU; |
2ef7eeaa EA |
3959 | } |
3960 | ||
3961 | /* It should now be out of any other write domains, and we can update | |
3962 | * the domain values for our changes. | |
3963 | */ | |
05394f39 | 3964 | BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) != 0); |
e47c68e9 EA |
3965 | |
3966 | /* If we're writing through the CPU, then the GPU read domains will | |
3967 | * need to be invalidated at next use. | |
3968 | */ | |
3969 | if (write) { | |
05394f39 CW |
3970 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; |
3971 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; | |
e47c68e9 | 3972 | } |
2ef7eeaa | 3973 | |
f99d7069 DV |
3974 | if (write) |
3975 | intel_fb_obj_invalidate(obj, NULL); | |
3976 | ||
1c5d22f7 CW |
3977 | trace_i915_gem_object_change_domain(obj, |
3978 | old_read_domains, | |
3979 | old_write_domain); | |
3980 | ||
2ef7eeaa EA |
3981 | return 0; |
3982 | } | |
3983 | ||
673a394b EA |
3984 | /* Throttle our rendering by waiting until the ring has completed our requests |
3985 | * emitted over 20 msec ago. | |
3986 | * | |
b962442e EA |
3987 | * Note that if we were to use the current jiffies each time around the loop, |
3988 | * we wouldn't escape the function with any frames outstanding if the time to | |
3989 | * render a frame was over 20ms. | |
3990 | * | |
673a394b EA |
3991 | * This should get us reasonable parallelism between CPU and GPU but also |
3992 | * relatively low latency when blocking on a particular request to finish. | |
3993 | */ | |
40a5f0de | 3994 | static int |
f787a5f5 | 3995 | i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file) |
40a5f0de | 3996 | { |
f787a5f5 CW |
3997 | struct drm_i915_private *dev_priv = dev->dev_private; |
3998 | struct drm_i915_file_private *file_priv = file->driver_priv; | |
b962442e | 3999 | unsigned long recent_enough = jiffies - msecs_to_jiffies(20); |
f787a5f5 | 4000 | struct drm_i915_gem_request *request; |
a4872ba6 | 4001 | struct intel_engine_cs *ring = NULL; |
f69061be | 4002 | unsigned reset_counter; |
f787a5f5 CW |
4003 | u32 seqno = 0; |
4004 | int ret; | |
93533c29 | 4005 | |
308887aa DV |
4006 | ret = i915_gem_wait_for_error(&dev_priv->gpu_error); |
4007 | if (ret) | |
4008 | return ret; | |
4009 | ||
4010 | ret = i915_gem_check_wedge(&dev_priv->gpu_error, false); | |
4011 | if (ret) | |
4012 | return ret; | |
e110e8d6 | 4013 | |
1c25595f | 4014 | spin_lock(&file_priv->mm.lock); |
f787a5f5 | 4015 | list_for_each_entry(request, &file_priv->mm.request_list, client_list) { |
b962442e EA |
4016 | if (time_after_eq(request->emitted_jiffies, recent_enough)) |
4017 | break; | |
40a5f0de | 4018 | |
f787a5f5 CW |
4019 | ring = request->ring; |
4020 | seqno = request->seqno; | |
b962442e | 4021 | } |
f69061be | 4022 | reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter); |
1c25595f | 4023 | spin_unlock(&file_priv->mm.lock); |
40a5f0de | 4024 | |
f787a5f5 CW |
4025 | if (seqno == 0) |
4026 | return 0; | |
2bc43b5c | 4027 | |
b29c19b6 | 4028 | ret = __wait_seqno(ring, seqno, reset_counter, true, NULL, NULL); |
f787a5f5 CW |
4029 | if (ret == 0) |
4030 | queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, 0); | |
40a5f0de EA |
4031 | |
4032 | return ret; | |
4033 | } | |
4034 | ||
d23db88c CW |
4035 | static bool |
4036 | i915_vma_misplaced(struct i915_vma *vma, uint32_t alignment, uint64_t flags) | |
4037 | { | |
4038 | struct drm_i915_gem_object *obj = vma->obj; | |
4039 | ||
4040 | if (alignment && | |
4041 | vma->node.start & (alignment - 1)) | |
4042 | return true; | |
4043 | ||
4044 | if (flags & PIN_MAPPABLE && !obj->map_and_fenceable) | |
4045 | return true; | |
4046 | ||
4047 | if (flags & PIN_OFFSET_BIAS && | |
4048 | vma->node.start < (flags & PIN_OFFSET_MASK)) | |
4049 | return true; | |
4050 | ||
4051 | return false; | |
4052 | } | |
4053 | ||
673a394b | 4054 | int |
05394f39 | 4055 | i915_gem_object_pin(struct drm_i915_gem_object *obj, |
c37e2204 | 4056 | struct i915_address_space *vm, |
05394f39 | 4057 | uint32_t alignment, |
d23db88c | 4058 | uint64_t flags) |
673a394b | 4059 | { |
6e7186af | 4060 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
07fe0b12 | 4061 | struct i915_vma *vma; |
673a394b EA |
4062 | int ret; |
4063 | ||
6e7186af BW |
4064 | if (WARN_ON(vm == &dev_priv->mm.aliasing_ppgtt->base)) |
4065 | return -ENODEV; | |
4066 | ||
bf3d149b | 4067 | if (WARN_ON(flags & (PIN_GLOBAL | PIN_MAPPABLE) && !i915_is_ggtt(vm))) |
1ec9e26d | 4068 | return -EINVAL; |
07fe0b12 BW |
4069 | |
4070 | vma = i915_gem_obj_to_vma(obj, vm); | |
07fe0b12 | 4071 | if (vma) { |
d7f46fc4 BW |
4072 | if (WARN_ON(vma->pin_count == DRM_I915_GEM_OBJECT_MAX_PIN_COUNT)) |
4073 | return -EBUSY; | |
4074 | ||
d23db88c | 4075 | if (i915_vma_misplaced(vma, alignment, flags)) { |
d7f46fc4 | 4076 | WARN(vma->pin_count, |
ae7d49d8 | 4077 | "bo is already pinned with incorrect alignment:" |
f343c5f6 | 4078 | " offset=%lx, req.alignment=%x, req.map_and_fenceable=%d," |
75e9e915 | 4079 | " obj->map_and_fenceable=%d\n", |
07fe0b12 | 4080 | i915_gem_obj_offset(obj, vm), alignment, |
d23db88c | 4081 | !!(flags & PIN_MAPPABLE), |
05394f39 | 4082 | obj->map_and_fenceable); |
07fe0b12 | 4083 | ret = i915_vma_unbind(vma); |
ac0c6b5a CW |
4084 | if (ret) |
4085 | return ret; | |
8ea99c92 DV |
4086 | |
4087 | vma = NULL; | |
ac0c6b5a CW |
4088 | } |
4089 | } | |
4090 | ||
8ea99c92 | 4091 | if (vma == NULL || !drm_mm_node_allocated(&vma->node)) { |
262de145 DV |
4092 | vma = i915_gem_object_bind_to_vm(obj, vm, alignment, flags); |
4093 | if (IS_ERR(vma)) | |
4094 | return PTR_ERR(vma); | |
22c344e9 | 4095 | } |
76446cac | 4096 | |
8ea99c92 DV |
4097 | if (flags & PIN_GLOBAL && !obj->has_global_gtt_mapping) |
4098 | vma->bind_vma(vma, obj->cache_level, GLOBAL_BIND); | |
74898d7e | 4099 | |
8ea99c92 | 4100 | vma->pin_count++; |
1ec9e26d DV |
4101 | if (flags & PIN_MAPPABLE) |
4102 | obj->pin_mappable |= true; | |
673a394b EA |
4103 | |
4104 | return 0; | |
4105 | } | |
4106 | ||
4107 | void | |
d7f46fc4 | 4108 | i915_gem_object_ggtt_unpin(struct drm_i915_gem_object *obj) |
673a394b | 4109 | { |
d7f46fc4 | 4110 | struct i915_vma *vma = i915_gem_obj_to_ggtt(obj); |
673a394b | 4111 | |
d7f46fc4 BW |
4112 | BUG_ON(!vma); |
4113 | BUG_ON(vma->pin_count == 0); | |
4114 | BUG_ON(!i915_gem_obj_ggtt_bound(obj)); | |
4115 | ||
4116 | if (--vma->pin_count == 0) | |
6299f992 | 4117 | obj->pin_mappable = false; |
673a394b EA |
4118 | } |
4119 | ||
d8ffa60b DV |
4120 | bool |
4121 | i915_gem_object_pin_fence(struct drm_i915_gem_object *obj) | |
4122 | { | |
4123 | if (obj->fence_reg != I915_FENCE_REG_NONE) { | |
4124 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; | |
4125 | struct i915_vma *ggtt_vma = i915_gem_obj_to_ggtt(obj); | |
4126 | ||
4127 | WARN_ON(!ggtt_vma || | |
4128 | dev_priv->fence_regs[obj->fence_reg].pin_count > | |
4129 | ggtt_vma->pin_count); | |
4130 | dev_priv->fence_regs[obj->fence_reg].pin_count++; | |
4131 | return true; | |
4132 | } else | |
4133 | return false; | |
4134 | } | |
4135 | ||
4136 | void | |
4137 | i915_gem_object_unpin_fence(struct drm_i915_gem_object *obj) | |
4138 | { | |
4139 | if (obj->fence_reg != I915_FENCE_REG_NONE) { | |
4140 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; | |
4141 | WARN_ON(dev_priv->fence_regs[obj->fence_reg].pin_count <= 0); | |
4142 | dev_priv->fence_regs[obj->fence_reg].pin_count--; | |
4143 | } | |
4144 | } | |
4145 | ||
673a394b EA |
4146 | int |
4147 | i915_gem_pin_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 4148 | struct drm_file *file) |
673a394b EA |
4149 | { |
4150 | struct drm_i915_gem_pin *args = data; | |
05394f39 | 4151 | struct drm_i915_gem_object *obj; |
673a394b EA |
4152 | int ret; |
4153 | ||
02f6bccc DV |
4154 | if (INTEL_INFO(dev)->gen >= 6) |
4155 | return -ENODEV; | |
4156 | ||
1d7cfea1 CW |
4157 | ret = i915_mutex_lock_interruptible(dev); |
4158 | if (ret) | |
4159 | return ret; | |
673a394b | 4160 | |
05394f39 | 4161 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 4162 | if (&obj->base == NULL) { |
1d7cfea1 CW |
4163 | ret = -ENOENT; |
4164 | goto unlock; | |
673a394b | 4165 | } |
673a394b | 4166 | |
05394f39 | 4167 | if (obj->madv != I915_MADV_WILLNEED) { |
bd9b6a4e | 4168 | DRM_DEBUG("Attempting to pin a purgeable buffer\n"); |
8c99e57d | 4169 | ret = -EFAULT; |
1d7cfea1 | 4170 | goto out; |
3ef94daa CW |
4171 | } |
4172 | ||
05394f39 | 4173 | if (obj->pin_filp != NULL && obj->pin_filp != file) { |
bd9b6a4e | 4174 | DRM_DEBUG("Already pinned in i915_gem_pin_ioctl(): %d\n", |
79e53945 | 4175 | args->handle); |
1d7cfea1 CW |
4176 | ret = -EINVAL; |
4177 | goto out; | |
79e53945 JB |
4178 | } |
4179 | ||
aa5f8021 DV |
4180 | if (obj->user_pin_count == ULONG_MAX) { |
4181 | ret = -EBUSY; | |
4182 | goto out; | |
4183 | } | |
4184 | ||
93be8788 | 4185 | if (obj->user_pin_count == 0) { |
1ec9e26d | 4186 | ret = i915_gem_obj_ggtt_pin(obj, args->alignment, PIN_MAPPABLE); |
1d7cfea1 CW |
4187 | if (ret) |
4188 | goto out; | |
673a394b EA |
4189 | } |
4190 | ||
93be8788 CW |
4191 | obj->user_pin_count++; |
4192 | obj->pin_filp = file; | |
4193 | ||
f343c5f6 | 4194 | args->offset = i915_gem_obj_ggtt_offset(obj); |
1d7cfea1 | 4195 | out: |
05394f39 | 4196 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 4197 | unlock: |
673a394b | 4198 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 4199 | return ret; |
673a394b EA |
4200 | } |
4201 | ||
4202 | int | |
4203 | i915_gem_unpin_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 4204 | struct drm_file *file) |
673a394b EA |
4205 | { |
4206 | struct drm_i915_gem_pin *args = data; | |
05394f39 | 4207 | struct drm_i915_gem_object *obj; |
76c1dec1 | 4208 | int ret; |
673a394b | 4209 | |
1d7cfea1 CW |
4210 | ret = i915_mutex_lock_interruptible(dev); |
4211 | if (ret) | |
4212 | return ret; | |
673a394b | 4213 | |
05394f39 | 4214 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 4215 | if (&obj->base == NULL) { |
1d7cfea1 CW |
4216 | ret = -ENOENT; |
4217 | goto unlock; | |
673a394b | 4218 | } |
76c1dec1 | 4219 | |
05394f39 | 4220 | if (obj->pin_filp != file) { |
bd9b6a4e | 4221 | DRM_DEBUG("Not pinned by caller in i915_gem_pin_ioctl(): %d\n", |
79e53945 | 4222 | args->handle); |
1d7cfea1 CW |
4223 | ret = -EINVAL; |
4224 | goto out; | |
79e53945 | 4225 | } |
05394f39 CW |
4226 | obj->user_pin_count--; |
4227 | if (obj->user_pin_count == 0) { | |
4228 | obj->pin_filp = NULL; | |
d7f46fc4 | 4229 | i915_gem_object_ggtt_unpin(obj); |
79e53945 | 4230 | } |
673a394b | 4231 | |
1d7cfea1 | 4232 | out: |
05394f39 | 4233 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 4234 | unlock: |
673a394b | 4235 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 4236 | return ret; |
673a394b EA |
4237 | } |
4238 | ||
4239 | int | |
4240 | i915_gem_busy_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 4241 | struct drm_file *file) |
673a394b EA |
4242 | { |
4243 | struct drm_i915_gem_busy *args = data; | |
05394f39 | 4244 | struct drm_i915_gem_object *obj; |
30dbf0c0 CW |
4245 | int ret; |
4246 | ||
76c1dec1 | 4247 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 4248 | if (ret) |
76c1dec1 | 4249 | return ret; |
673a394b | 4250 | |
05394f39 | 4251 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 4252 | if (&obj->base == NULL) { |
1d7cfea1 CW |
4253 | ret = -ENOENT; |
4254 | goto unlock; | |
673a394b | 4255 | } |
d1b851fc | 4256 | |
0be555b6 CW |
4257 | /* Count all active objects as busy, even if they are currently not used |
4258 | * by the gpu. Users of this interface expect objects to eventually | |
4259 | * become non-busy without any further actions, therefore emit any | |
4260 | * necessary flushes here. | |
c4de0a5d | 4261 | */ |
30dfebf3 | 4262 | ret = i915_gem_object_flush_active(obj); |
0be555b6 | 4263 | |
30dfebf3 | 4264 | args->busy = obj->active; |
e9808edd CW |
4265 | if (obj->ring) { |
4266 | BUILD_BUG_ON(I915_NUM_RINGS > 16); | |
4267 | args->busy |= intel_ring_flag(obj->ring) << 16; | |
4268 | } | |
673a394b | 4269 | |
05394f39 | 4270 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 4271 | unlock: |
673a394b | 4272 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 4273 | return ret; |
673a394b EA |
4274 | } |
4275 | ||
4276 | int | |
4277 | i915_gem_throttle_ioctl(struct drm_device *dev, void *data, | |
4278 | struct drm_file *file_priv) | |
4279 | { | |
0206e353 | 4280 | return i915_gem_ring_throttle(dev, file_priv); |
673a394b EA |
4281 | } |
4282 | ||
3ef94daa CW |
4283 | int |
4284 | i915_gem_madvise_ioctl(struct drm_device *dev, void *data, | |
4285 | struct drm_file *file_priv) | |
4286 | { | |
4287 | struct drm_i915_gem_madvise *args = data; | |
05394f39 | 4288 | struct drm_i915_gem_object *obj; |
76c1dec1 | 4289 | int ret; |
3ef94daa CW |
4290 | |
4291 | switch (args->madv) { | |
4292 | case I915_MADV_DONTNEED: | |
4293 | case I915_MADV_WILLNEED: | |
4294 | break; | |
4295 | default: | |
4296 | return -EINVAL; | |
4297 | } | |
4298 | ||
1d7cfea1 CW |
4299 | ret = i915_mutex_lock_interruptible(dev); |
4300 | if (ret) | |
4301 | return ret; | |
4302 | ||
05394f39 | 4303 | obj = to_intel_bo(drm_gem_object_lookup(dev, file_priv, args->handle)); |
c8725226 | 4304 | if (&obj->base == NULL) { |
1d7cfea1 CW |
4305 | ret = -ENOENT; |
4306 | goto unlock; | |
3ef94daa | 4307 | } |
3ef94daa | 4308 | |
d7f46fc4 | 4309 | if (i915_gem_obj_is_pinned(obj)) { |
1d7cfea1 CW |
4310 | ret = -EINVAL; |
4311 | goto out; | |
3ef94daa CW |
4312 | } |
4313 | ||
05394f39 CW |
4314 | if (obj->madv != __I915_MADV_PURGED) |
4315 | obj->madv = args->madv; | |
3ef94daa | 4316 | |
6c085a72 CW |
4317 | /* if the object is no longer attached, discard its backing storage */ |
4318 | if (i915_gem_object_is_purgeable(obj) && obj->pages == NULL) | |
2d7ef395 CW |
4319 | i915_gem_object_truncate(obj); |
4320 | ||
05394f39 | 4321 | args->retained = obj->madv != __I915_MADV_PURGED; |
bb6baf76 | 4322 | |
1d7cfea1 | 4323 | out: |
05394f39 | 4324 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 4325 | unlock: |
3ef94daa | 4326 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 4327 | return ret; |
3ef94daa CW |
4328 | } |
4329 | ||
37e680a1 CW |
4330 | void i915_gem_object_init(struct drm_i915_gem_object *obj, |
4331 | const struct drm_i915_gem_object_ops *ops) | |
0327d6ba | 4332 | { |
35c20a60 | 4333 | INIT_LIST_HEAD(&obj->global_list); |
0327d6ba | 4334 | INIT_LIST_HEAD(&obj->ring_list); |
b25cb2f8 | 4335 | INIT_LIST_HEAD(&obj->obj_exec_link); |
2f633156 | 4336 | INIT_LIST_HEAD(&obj->vma_list); |
0327d6ba | 4337 | |
37e680a1 CW |
4338 | obj->ops = ops; |
4339 | ||
0327d6ba CW |
4340 | obj->fence_reg = I915_FENCE_REG_NONE; |
4341 | obj->madv = I915_MADV_WILLNEED; | |
0327d6ba CW |
4342 | |
4343 | i915_gem_info_add_obj(obj->base.dev->dev_private, obj->base.size); | |
4344 | } | |
4345 | ||
37e680a1 CW |
4346 | static const struct drm_i915_gem_object_ops i915_gem_object_ops = { |
4347 | .get_pages = i915_gem_object_get_pages_gtt, | |
4348 | .put_pages = i915_gem_object_put_pages_gtt, | |
4349 | }; | |
4350 | ||
05394f39 CW |
4351 | struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev, |
4352 | size_t size) | |
ac52bc56 | 4353 | { |
c397b908 | 4354 | struct drm_i915_gem_object *obj; |
5949eac4 | 4355 | struct address_space *mapping; |
1a240d4d | 4356 | gfp_t mask; |
ac52bc56 | 4357 | |
42dcedd4 | 4358 | obj = i915_gem_object_alloc(dev); |
c397b908 DV |
4359 | if (obj == NULL) |
4360 | return NULL; | |
673a394b | 4361 | |
c397b908 | 4362 | if (drm_gem_object_init(dev, &obj->base, size) != 0) { |
42dcedd4 | 4363 | i915_gem_object_free(obj); |
c397b908 DV |
4364 | return NULL; |
4365 | } | |
673a394b | 4366 | |
bed1ea95 CW |
4367 | mask = GFP_HIGHUSER | __GFP_RECLAIMABLE; |
4368 | if (IS_CRESTLINE(dev) || IS_BROADWATER(dev)) { | |
4369 | /* 965gm cannot relocate objects above 4GiB. */ | |
4370 | mask &= ~__GFP_HIGHMEM; | |
4371 | mask |= __GFP_DMA32; | |
4372 | } | |
4373 | ||
496ad9aa | 4374 | mapping = file_inode(obj->base.filp)->i_mapping; |
bed1ea95 | 4375 | mapping_set_gfp_mask(mapping, mask); |
5949eac4 | 4376 | |
37e680a1 | 4377 | i915_gem_object_init(obj, &i915_gem_object_ops); |
73aa808f | 4378 | |
c397b908 DV |
4379 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; |
4380 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; | |
673a394b | 4381 | |
3d29b842 ED |
4382 | if (HAS_LLC(dev)) { |
4383 | /* On some devices, we can have the GPU use the LLC (the CPU | |
a1871112 EA |
4384 | * cache) for about a 10% performance improvement |
4385 | * compared to uncached. Graphics requests other than | |
4386 | * display scanout are coherent with the CPU in | |
4387 | * accessing this cache. This means in this mode we | |
4388 | * don't need to clflush on the CPU side, and on the | |
4389 | * GPU side we only need to flush internal caches to | |
4390 | * get data visible to the CPU. | |
4391 | * | |
4392 | * However, we maintain the display planes as UC, and so | |
4393 | * need to rebind when first used as such. | |
4394 | */ | |
4395 | obj->cache_level = I915_CACHE_LLC; | |
4396 | } else | |
4397 | obj->cache_level = I915_CACHE_NONE; | |
4398 | ||
d861e338 DV |
4399 | trace_i915_gem_object_create(obj); |
4400 | ||
05394f39 | 4401 | return obj; |
c397b908 DV |
4402 | } |
4403 | ||
340fbd8c CW |
4404 | static bool discard_backing_storage(struct drm_i915_gem_object *obj) |
4405 | { | |
4406 | /* If we are the last user of the backing storage (be it shmemfs | |
4407 | * pages or stolen etc), we know that the pages are going to be | |
4408 | * immediately released. In this case, we can then skip copying | |
4409 | * back the contents from the GPU. | |
4410 | */ | |
4411 | ||
4412 | if (obj->madv != I915_MADV_WILLNEED) | |
4413 | return false; | |
4414 | ||
4415 | if (obj->base.filp == NULL) | |
4416 | return true; | |
4417 | ||
4418 | /* At first glance, this looks racy, but then again so would be | |
4419 | * userspace racing mmap against close. However, the first external | |
4420 | * reference to the filp can only be obtained through the | |
4421 | * i915_gem_mmap_ioctl() which safeguards us against the user | |
4422 | * acquiring such a reference whilst we are in the middle of | |
4423 | * freeing the object. | |
4424 | */ | |
4425 | return atomic_long_read(&obj->base.filp->f_count) == 1; | |
4426 | } | |
4427 | ||
1488fc08 | 4428 | void i915_gem_free_object(struct drm_gem_object *gem_obj) |
673a394b | 4429 | { |
1488fc08 | 4430 | struct drm_i915_gem_object *obj = to_intel_bo(gem_obj); |
05394f39 | 4431 | struct drm_device *dev = obj->base.dev; |
3e31c6c0 | 4432 | struct drm_i915_private *dev_priv = dev->dev_private; |
07fe0b12 | 4433 | struct i915_vma *vma, *next; |
673a394b | 4434 | |
f65c9168 PZ |
4435 | intel_runtime_pm_get(dev_priv); |
4436 | ||
26e12f89 CW |
4437 | trace_i915_gem_object_destroy(obj); |
4438 | ||
07fe0b12 | 4439 | list_for_each_entry_safe(vma, next, &obj->vma_list, vma_link) { |
d7f46fc4 BW |
4440 | int ret; |
4441 | ||
4442 | vma->pin_count = 0; | |
4443 | ret = i915_vma_unbind(vma); | |
07fe0b12 BW |
4444 | if (WARN_ON(ret == -ERESTARTSYS)) { |
4445 | bool was_interruptible; | |
1488fc08 | 4446 | |
07fe0b12 BW |
4447 | was_interruptible = dev_priv->mm.interruptible; |
4448 | dev_priv->mm.interruptible = false; | |
1488fc08 | 4449 | |
07fe0b12 | 4450 | WARN_ON(i915_vma_unbind(vma)); |
1488fc08 | 4451 | |
07fe0b12 BW |
4452 | dev_priv->mm.interruptible = was_interruptible; |
4453 | } | |
1488fc08 CW |
4454 | } |
4455 | ||
00731155 CW |
4456 | i915_gem_object_detach_phys(obj); |
4457 | ||
1d64ae71 BW |
4458 | /* Stolen objects don't hold a ref, but do hold pin count. Fix that up |
4459 | * before progressing. */ | |
4460 | if (obj->stolen) | |
4461 | i915_gem_object_unpin_pages(obj); | |
4462 | ||
a071fa00 DV |
4463 | WARN_ON(obj->frontbuffer_bits); |
4464 | ||
401c29f6 BW |
4465 | if (WARN_ON(obj->pages_pin_count)) |
4466 | obj->pages_pin_count = 0; | |
340fbd8c | 4467 | if (discard_backing_storage(obj)) |
5537252b | 4468 | obj->madv = I915_MADV_DONTNEED; |
37e680a1 | 4469 | i915_gem_object_put_pages(obj); |
d8cb5086 | 4470 | i915_gem_object_free_mmap_offset(obj); |
de151cf6 | 4471 | |
9da3da66 CW |
4472 | BUG_ON(obj->pages); |
4473 | ||
2f745ad3 CW |
4474 | if (obj->base.import_attach) |
4475 | drm_prime_gem_destroy(&obj->base, NULL); | |
de151cf6 | 4476 | |
5cc9ed4b CW |
4477 | if (obj->ops->release) |
4478 | obj->ops->release(obj); | |
4479 | ||
05394f39 CW |
4480 | drm_gem_object_release(&obj->base); |
4481 | i915_gem_info_remove_obj(dev_priv, obj->base.size); | |
c397b908 | 4482 | |
05394f39 | 4483 | kfree(obj->bit_17); |
42dcedd4 | 4484 | i915_gem_object_free(obj); |
f65c9168 PZ |
4485 | |
4486 | intel_runtime_pm_put(dev_priv); | |
673a394b EA |
4487 | } |
4488 | ||
e656a6cb | 4489 | struct i915_vma *i915_gem_obj_to_vma(struct drm_i915_gem_object *obj, |
2f633156 | 4490 | struct i915_address_space *vm) |
e656a6cb DV |
4491 | { |
4492 | struct i915_vma *vma; | |
4493 | list_for_each_entry(vma, &obj->vma_list, vma_link) | |
4494 | if (vma->vm == vm) | |
4495 | return vma; | |
4496 | ||
4497 | return NULL; | |
4498 | } | |
4499 | ||
2f633156 BW |
4500 | void i915_gem_vma_destroy(struct i915_vma *vma) |
4501 | { | |
b9d06dd9 | 4502 | struct i915_address_space *vm = NULL; |
2f633156 | 4503 | WARN_ON(vma->node.allocated); |
aaa05667 CW |
4504 | |
4505 | /* Keep the vma as a placeholder in the execbuffer reservation lists */ | |
4506 | if (!list_empty(&vma->exec_list)) | |
4507 | return; | |
4508 | ||
b9d06dd9 | 4509 | vm = vma->vm; |
b9d06dd9 | 4510 | |
841cd773 DV |
4511 | if (!i915_is_ggtt(vm)) |
4512 | i915_ppgtt_put(i915_vm_to_ppgtt(vm)); | |
b9d06dd9 | 4513 | |
8b9c2b94 | 4514 | list_del(&vma->vma_link); |
b93dab6e | 4515 | |
2f633156 BW |
4516 | kfree(vma); |
4517 | } | |
4518 | ||
e3efda49 CW |
4519 | static void |
4520 | i915_gem_stop_ringbuffers(struct drm_device *dev) | |
4521 | { | |
4522 | struct drm_i915_private *dev_priv = dev->dev_private; | |
a4872ba6 | 4523 | struct intel_engine_cs *ring; |
e3efda49 CW |
4524 | int i; |
4525 | ||
4526 | for_each_ring(ring, dev_priv, i) | |
a83014d3 | 4527 | dev_priv->gt.stop_ring(ring); |
e3efda49 CW |
4528 | } |
4529 | ||
29105ccc | 4530 | int |
45c5f202 | 4531 | i915_gem_suspend(struct drm_device *dev) |
29105ccc | 4532 | { |
3e31c6c0 | 4533 | struct drm_i915_private *dev_priv = dev->dev_private; |
45c5f202 | 4534 | int ret = 0; |
28dfe52a | 4535 | |
45c5f202 | 4536 | mutex_lock(&dev->struct_mutex); |
f7403347 | 4537 | if (dev_priv->ums.mm_suspended) |
45c5f202 | 4538 | goto err; |
28dfe52a | 4539 | |
b2da9fe5 | 4540 | ret = i915_gpu_idle(dev); |
f7403347 | 4541 | if (ret) |
45c5f202 | 4542 | goto err; |
f7403347 | 4543 | |
b2da9fe5 | 4544 | i915_gem_retire_requests(dev); |
673a394b | 4545 | |
29105ccc | 4546 | /* Under UMS, be paranoid and evict. */ |
a39d7efc | 4547 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) |
6c085a72 | 4548 | i915_gem_evict_everything(dev); |
29105ccc | 4549 | |
29105ccc | 4550 | i915_kernel_lost_context(dev); |
e3efda49 | 4551 | i915_gem_stop_ringbuffers(dev); |
29105ccc | 4552 | |
45c5f202 CW |
4553 | /* Hack! Don't let anybody do execbuf while we don't control the chip. |
4554 | * We need to replace this with a semaphore, or something. | |
4555 | * And not confound ums.mm_suspended! | |
4556 | */ | |
4557 | dev_priv->ums.mm_suspended = !drm_core_check_feature(dev, | |
4558 | DRIVER_MODESET); | |
4559 | mutex_unlock(&dev->struct_mutex); | |
4560 | ||
4561 | del_timer_sync(&dev_priv->gpu_error.hangcheck_timer); | |
29105ccc | 4562 | cancel_delayed_work_sync(&dev_priv->mm.retire_work); |
274fa1c1 | 4563 | flush_delayed_work(&dev_priv->mm.idle_work); |
29105ccc | 4564 | |
673a394b | 4565 | return 0; |
45c5f202 CW |
4566 | |
4567 | err: | |
4568 | mutex_unlock(&dev->struct_mutex); | |
4569 | return ret; | |
673a394b EA |
4570 | } |
4571 | ||
a4872ba6 | 4572 | int i915_gem_l3_remap(struct intel_engine_cs *ring, int slice) |
b9524a1e | 4573 | { |
c3787e2e | 4574 | struct drm_device *dev = ring->dev; |
3e31c6c0 | 4575 | struct drm_i915_private *dev_priv = dev->dev_private; |
35a85ac6 BW |
4576 | u32 reg_base = GEN7_L3LOG_BASE + (slice * 0x200); |
4577 | u32 *remap_info = dev_priv->l3_parity.remap_info[slice]; | |
c3787e2e | 4578 | int i, ret; |
b9524a1e | 4579 | |
040d2baa | 4580 | if (!HAS_L3_DPF(dev) || !remap_info) |
c3787e2e | 4581 | return 0; |
b9524a1e | 4582 | |
c3787e2e BW |
4583 | ret = intel_ring_begin(ring, GEN7_L3LOG_SIZE / 4 * 3); |
4584 | if (ret) | |
4585 | return ret; | |
b9524a1e | 4586 | |
c3787e2e BW |
4587 | /* |
4588 | * Note: We do not worry about the concurrent register cacheline hang | |
4589 | * here because no other code should access these registers other than | |
4590 | * at initialization time. | |
4591 | */ | |
b9524a1e | 4592 | for (i = 0; i < GEN7_L3LOG_SIZE; i += 4) { |
c3787e2e BW |
4593 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); |
4594 | intel_ring_emit(ring, reg_base + i); | |
4595 | intel_ring_emit(ring, remap_info[i/4]); | |
b9524a1e BW |
4596 | } |
4597 | ||
c3787e2e | 4598 | intel_ring_advance(ring); |
b9524a1e | 4599 | |
c3787e2e | 4600 | return ret; |
b9524a1e BW |
4601 | } |
4602 | ||
f691e2f4 DV |
4603 | void i915_gem_init_swizzling(struct drm_device *dev) |
4604 | { | |
3e31c6c0 | 4605 | struct drm_i915_private *dev_priv = dev->dev_private; |
f691e2f4 | 4606 | |
11782b02 | 4607 | if (INTEL_INFO(dev)->gen < 5 || |
f691e2f4 DV |
4608 | dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE) |
4609 | return; | |
4610 | ||
4611 | I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) | | |
4612 | DISP_TILE_SURFACE_SWIZZLING); | |
4613 | ||
11782b02 DV |
4614 | if (IS_GEN5(dev)) |
4615 | return; | |
4616 | ||
f691e2f4 DV |
4617 | I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_SWZCTL); |
4618 | if (IS_GEN6(dev)) | |
6b26c86d | 4619 | I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB)); |
8782e26c | 4620 | else if (IS_GEN7(dev)) |
6b26c86d | 4621 | I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB)); |
31a5336e BW |
4622 | else if (IS_GEN8(dev)) |
4623 | I915_WRITE(GAMTARBMODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_BDW)); | |
8782e26c BW |
4624 | else |
4625 | BUG(); | |
f691e2f4 | 4626 | } |
e21af88d | 4627 | |
67b1b571 CW |
4628 | static bool |
4629 | intel_enable_blt(struct drm_device *dev) | |
4630 | { | |
4631 | if (!HAS_BLT(dev)) | |
4632 | return false; | |
4633 | ||
4634 | /* The blitter was dysfunctional on early prototypes */ | |
4635 | if (IS_GEN6(dev) && dev->pdev->revision < 8) { | |
4636 | DRM_INFO("BLT not supported on this pre-production hardware;" | |
4637 | " graphics performance will be degraded.\n"); | |
4638 | return false; | |
4639 | } | |
4640 | ||
4641 | return true; | |
4642 | } | |
4643 | ||
81e7f200 VS |
4644 | static void init_unused_ring(struct drm_device *dev, u32 base) |
4645 | { | |
4646 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4647 | ||
4648 | I915_WRITE(RING_CTL(base), 0); | |
4649 | I915_WRITE(RING_HEAD(base), 0); | |
4650 | I915_WRITE(RING_TAIL(base), 0); | |
4651 | I915_WRITE(RING_START(base), 0); | |
4652 | } | |
4653 | ||
4654 | static void init_unused_rings(struct drm_device *dev) | |
4655 | { | |
4656 | if (IS_I830(dev)) { | |
4657 | init_unused_ring(dev, PRB1_BASE); | |
4658 | init_unused_ring(dev, SRB0_BASE); | |
4659 | init_unused_ring(dev, SRB1_BASE); | |
4660 | init_unused_ring(dev, SRB2_BASE); | |
4661 | init_unused_ring(dev, SRB3_BASE); | |
4662 | } else if (IS_GEN2(dev)) { | |
4663 | init_unused_ring(dev, SRB0_BASE); | |
4664 | init_unused_ring(dev, SRB1_BASE); | |
4665 | } else if (IS_GEN3(dev)) { | |
4666 | init_unused_ring(dev, PRB1_BASE); | |
4667 | init_unused_ring(dev, PRB2_BASE); | |
4668 | } | |
4669 | } | |
4670 | ||
a83014d3 | 4671 | int i915_gem_init_rings(struct drm_device *dev) |
8187a2b7 | 4672 | { |
4fc7c971 | 4673 | struct drm_i915_private *dev_priv = dev->dev_private; |
8187a2b7 | 4674 | int ret; |
68f95ba9 | 4675 | |
81e7f200 VS |
4676 | /* |
4677 | * At least 830 can leave some of the unused rings | |
4678 | * "active" (ie. head != tail) after resume which | |
4679 | * will prevent c3 entry. Makes sure all unused rings | |
4680 | * are totally idle. | |
4681 | */ | |
4682 | init_unused_rings(dev); | |
4683 | ||
5c1143bb | 4684 | ret = intel_init_render_ring_buffer(dev); |
68f95ba9 | 4685 | if (ret) |
b6913e4b | 4686 | return ret; |
68f95ba9 CW |
4687 | |
4688 | if (HAS_BSD(dev)) { | |
5c1143bb | 4689 | ret = intel_init_bsd_ring_buffer(dev); |
68f95ba9 CW |
4690 | if (ret) |
4691 | goto cleanup_render_ring; | |
d1b851fc | 4692 | } |
68f95ba9 | 4693 | |
67b1b571 | 4694 | if (intel_enable_blt(dev)) { |
549f7365 CW |
4695 | ret = intel_init_blt_ring_buffer(dev); |
4696 | if (ret) | |
4697 | goto cleanup_bsd_ring; | |
4698 | } | |
4699 | ||
9a8a2213 BW |
4700 | if (HAS_VEBOX(dev)) { |
4701 | ret = intel_init_vebox_ring_buffer(dev); | |
4702 | if (ret) | |
4703 | goto cleanup_blt_ring; | |
4704 | } | |
4705 | ||
845f74a7 ZY |
4706 | if (HAS_BSD2(dev)) { |
4707 | ret = intel_init_bsd2_ring_buffer(dev); | |
4708 | if (ret) | |
4709 | goto cleanup_vebox_ring; | |
4710 | } | |
9a8a2213 | 4711 | |
99433931 | 4712 | ret = i915_gem_set_seqno(dev, ((u32)~0 - 0x1000)); |
4fc7c971 | 4713 | if (ret) |
845f74a7 | 4714 | goto cleanup_bsd2_ring; |
4fc7c971 BW |
4715 | |
4716 | return 0; | |
4717 | ||
845f74a7 ZY |
4718 | cleanup_bsd2_ring: |
4719 | intel_cleanup_ring_buffer(&dev_priv->ring[VCS2]); | |
9a8a2213 BW |
4720 | cleanup_vebox_ring: |
4721 | intel_cleanup_ring_buffer(&dev_priv->ring[VECS]); | |
4fc7c971 BW |
4722 | cleanup_blt_ring: |
4723 | intel_cleanup_ring_buffer(&dev_priv->ring[BCS]); | |
4724 | cleanup_bsd_ring: | |
4725 | intel_cleanup_ring_buffer(&dev_priv->ring[VCS]); | |
4726 | cleanup_render_ring: | |
4727 | intel_cleanup_ring_buffer(&dev_priv->ring[RCS]); | |
4728 | ||
4729 | return ret; | |
4730 | } | |
4731 | ||
4732 | int | |
4733 | i915_gem_init_hw(struct drm_device *dev) | |
4734 | { | |
3e31c6c0 | 4735 | struct drm_i915_private *dev_priv = dev->dev_private; |
35a85ac6 | 4736 | int ret, i; |
4fc7c971 BW |
4737 | |
4738 | if (INTEL_INFO(dev)->gen < 6 && !intel_enable_gtt()) | |
4739 | return -EIO; | |
4740 | ||
59124506 | 4741 | if (dev_priv->ellc_size) |
05e21cc4 | 4742 | I915_WRITE(HSW_IDICR, I915_READ(HSW_IDICR) | IDIHASHMSK(0xf)); |
4fc7c971 | 4743 | |
0bf21347 VS |
4744 | if (IS_HASWELL(dev)) |
4745 | I915_WRITE(MI_PREDICATE_RESULT_2, IS_HSW_GT3(dev) ? | |
4746 | LOWER_SLICE_ENABLED : LOWER_SLICE_DISABLED); | |
9435373e | 4747 | |
88a2b2a3 | 4748 | if (HAS_PCH_NOP(dev)) { |
6ba844b0 DV |
4749 | if (IS_IVYBRIDGE(dev)) { |
4750 | u32 temp = I915_READ(GEN7_MSG_CTL); | |
4751 | temp &= ~(WAIT_FOR_PCH_FLR_ACK | WAIT_FOR_PCH_RESET_ACK); | |
4752 | I915_WRITE(GEN7_MSG_CTL, temp); | |
4753 | } else if (INTEL_INFO(dev)->gen >= 7) { | |
4754 | u32 temp = I915_READ(HSW_NDE_RSTWRN_OPT); | |
4755 | temp &= ~RESET_PCH_HANDSHAKE_ENABLE; | |
4756 | I915_WRITE(HSW_NDE_RSTWRN_OPT, temp); | |
4757 | } | |
88a2b2a3 BW |
4758 | } |
4759 | ||
4fc7c971 BW |
4760 | i915_gem_init_swizzling(dev); |
4761 | ||
a83014d3 | 4762 | ret = dev_priv->gt.init_rings(dev); |
99433931 MK |
4763 | if (ret) |
4764 | return ret; | |
4765 | ||
c3787e2e BW |
4766 | for (i = 0; i < NUM_L3_SLICES(dev); i++) |
4767 | i915_gem_l3_remap(&dev_priv->ring[RCS], i); | |
4768 | ||
254f965c | 4769 | /* |
2fa48d8d BW |
4770 | * XXX: Contexts should only be initialized once. Doing a switch to the |
4771 | * default context switch however is something we'd like to do after | |
4772 | * reset or thaw (the latter may not actually be necessary for HW, but | |
4773 | * goes with our code better). Context switching requires rings (for | |
4774 | * the do_switch), but before enabling PPGTT. So don't move this. | |
254f965c | 4775 | */ |
2fa48d8d | 4776 | ret = i915_gem_context_enable(dev_priv); |
60990320 | 4777 | if (ret && ret != -EIO) { |
2fa48d8d | 4778 | DRM_ERROR("Context enable failed %d\n", ret); |
60990320 | 4779 | i915_gem_cleanup_ringbuffer(dev); |
82460d97 DV |
4780 | |
4781 | return ret; | |
4782 | } | |
4783 | ||
4784 | ret = i915_ppgtt_init_hw(dev); | |
4785 | if (ret && ret != -EIO) { | |
4786 | DRM_ERROR("PPGTT enable failed %d\n", ret); | |
4787 | i915_gem_cleanup_ringbuffer(dev); | |
b7c36d25 | 4788 | } |
e21af88d | 4789 | |
2fa48d8d | 4790 | return ret; |
8187a2b7 ZN |
4791 | } |
4792 | ||
1070a42b CW |
4793 | int i915_gem_init(struct drm_device *dev) |
4794 | { | |
4795 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1070a42b CW |
4796 | int ret; |
4797 | ||
127f1003 OM |
4798 | i915.enable_execlists = intel_sanitize_enable_execlists(dev, |
4799 | i915.enable_execlists); | |
4800 | ||
1070a42b | 4801 | mutex_lock(&dev->struct_mutex); |
d62b4892 JB |
4802 | |
4803 | if (IS_VALLEYVIEW(dev)) { | |
4804 | /* VLVA0 (potential hack), BIOS isn't actually waking us */ | |
981a5aea ID |
4805 | I915_WRITE(VLV_GTLC_WAKE_CTRL, VLV_GTLC_ALLOWWAKEREQ); |
4806 | if (wait_for((I915_READ(VLV_GTLC_PW_STATUS) & | |
4807 | VLV_GTLC_ALLOWWAKEACK), 10)) | |
d62b4892 JB |
4808 | DRM_DEBUG_DRIVER("allow wake ack timed out\n"); |
4809 | } | |
4810 | ||
a83014d3 OM |
4811 | if (!i915.enable_execlists) { |
4812 | dev_priv->gt.do_execbuf = i915_gem_ringbuffer_submission; | |
4813 | dev_priv->gt.init_rings = i915_gem_init_rings; | |
4814 | dev_priv->gt.cleanup_ring = intel_cleanup_ring_buffer; | |
4815 | dev_priv->gt.stop_ring = intel_stop_ring_buffer; | |
454afebd OM |
4816 | } else { |
4817 | dev_priv->gt.do_execbuf = intel_execlists_submission; | |
4818 | dev_priv->gt.init_rings = intel_logical_rings_init; | |
4819 | dev_priv->gt.cleanup_ring = intel_logical_ring_cleanup; | |
4820 | dev_priv->gt.stop_ring = intel_logical_ring_stop; | |
a83014d3 OM |
4821 | } |
4822 | ||
6c5566a8 DV |
4823 | ret = i915_gem_init_userptr(dev); |
4824 | if (ret) { | |
4825 | mutex_unlock(&dev->struct_mutex); | |
4826 | return ret; | |
4827 | } | |
4828 | ||
d7e5008f | 4829 | i915_gem_init_global_gtt(dev); |
d62b4892 | 4830 | |
2fa48d8d | 4831 | ret = i915_gem_context_init(dev); |
e3848694 MK |
4832 | if (ret) { |
4833 | mutex_unlock(&dev->struct_mutex); | |
2fa48d8d | 4834 | return ret; |
e3848694 | 4835 | } |
2fa48d8d | 4836 | |
1070a42b | 4837 | ret = i915_gem_init_hw(dev); |
60990320 CW |
4838 | if (ret == -EIO) { |
4839 | /* Allow ring initialisation to fail by marking the GPU as | |
4840 | * wedged. But we only want to do this where the GPU is angry, | |
4841 | * for all other failure, such as an allocation failure, bail. | |
4842 | */ | |
4843 | DRM_ERROR("Failed to initialize GPU, declaring it wedged\n"); | |
4844 | atomic_set_mask(I915_WEDGED, &dev_priv->gpu_error.reset_counter); | |
4845 | ret = 0; | |
1070a42b | 4846 | } |
60990320 | 4847 | mutex_unlock(&dev->struct_mutex); |
1070a42b | 4848 | |
53ca26ca DV |
4849 | /* Allow hardware batchbuffers unless told otherwise, but not for KMS. */ |
4850 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) | |
4851 | dev_priv->dri1.allow_batchbuffer = 1; | |
60990320 | 4852 | return ret; |
1070a42b CW |
4853 | } |
4854 | ||
8187a2b7 ZN |
4855 | void |
4856 | i915_gem_cleanup_ringbuffer(struct drm_device *dev) | |
4857 | { | |
3e31c6c0 | 4858 | struct drm_i915_private *dev_priv = dev->dev_private; |
a4872ba6 | 4859 | struct intel_engine_cs *ring; |
1ec14ad3 | 4860 | int i; |
8187a2b7 | 4861 | |
b4519513 | 4862 | for_each_ring(ring, dev_priv, i) |
a83014d3 | 4863 | dev_priv->gt.cleanup_ring(ring); |
8187a2b7 ZN |
4864 | } |
4865 | ||
673a394b EA |
4866 | int |
4867 | i915_gem_entervt_ioctl(struct drm_device *dev, void *data, | |
4868 | struct drm_file *file_priv) | |
4869 | { | |
db1b76ca | 4870 | struct drm_i915_private *dev_priv = dev->dev_private; |
b4519513 | 4871 | int ret; |
673a394b | 4872 | |
79e53945 JB |
4873 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
4874 | return 0; | |
4875 | ||
1f83fee0 | 4876 | if (i915_reset_in_progress(&dev_priv->gpu_error)) { |
673a394b | 4877 | DRM_ERROR("Reenabling wedged hardware, good luck\n"); |
1f83fee0 | 4878 | atomic_set(&dev_priv->gpu_error.reset_counter, 0); |
673a394b EA |
4879 | } |
4880 | ||
673a394b | 4881 | mutex_lock(&dev->struct_mutex); |
db1b76ca | 4882 | dev_priv->ums.mm_suspended = 0; |
9bb2d6f9 | 4883 | |
f691e2f4 | 4884 | ret = i915_gem_init_hw(dev); |
d816f6ac WF |
4885 | if (ret != 0) { |
4886 | mutex_unlock(&dev->struct_mutex); | |
9bb2d6f9 | 4887 | return ret; |
d816f6ac | 4888 | } |
9bb2d6f9 | 4889 | |
5cef07e1 | 4890 | BUG_ON(!list_empty(&dev_priv->gtt.base.active_list)); |
dbb19d30 | 4891 | |
bb0f1b5c | 4892 | ret = drm_irq_install(dev, dev->pdev->irq); |
5f35308b CW |
4893 | if (ret) |
4894 | goto cleanup_ringbuffer; | |
e090c53b | 4895 | mutex_unlock(&dev->struct_mutex); |
dbb19d30 | 4896 | |
673a394b | 4897 | return 0; |
5f35308b CW |
4898 | |
4899 | cleanup_ringbuffer: | |
5f35308b | 4900 | i915_gem_cleanup_ringbuffer(dev); |
db1b76ca | 4901 | dev_priv->ums.mm_suspended = 1; |
5f35308b CW |
4902 | mutex_unlock(&dev->struct_mutex); |
4903 | ||
4904 | return ret; | |
673a394b EA |
4905 | } |
4906 | ||
4907 | int | |
4908 | i915_gem_leavevt_ioctl(struct drm_device *dev, void *data, | |
4909 | struct drm_file *file_priv) | |
4910 | { | |
79e53945 JB |
4911 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
4912 | return 0; | |
4913 | ||
e090c53b | 4914 | mutex_lock(&dev->struct_mutex); |
dbb19d30 | 4915 | drm_irq_uninstall(dev); |
e090c53b | 4916 | mutex_unlock(&dev->struct_mutex); |
db1b76ca | 4917 | |
45c5f202 | 4918 | return i915_gem_suspend(dev); |
673a394b EA |
4919 | } |
4920 | ||
4921 | void | |
4922 | i915_gem_lastclose(struct drm_device *dev) | |
4923 | { | |
4924 | int ret; | |
673a394b | 4925 | |
e806b495 EA |
4926 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
4927 | return; | |
4928 | ||
45c5f202 | 4929 | ret = i915_gem_suspend(dev); |
6dbe2772 KP |
4930 | if (ret) |
4931 | DRM_ERROR("failed to idle hardware: %d\n", ret); | |
673a394b EA |
4932 | } |
4933 | ||
64193406 | 4934 | static void |
a4872ba6 | 4935 | init_ring_lists(struct intel_engine_cs *ring) |
64193406 CW |
4936 | { |
4937 | INIT_LIST_HEAD(&ring->active_list); | |
4938 | INIT_LIST_HEAD(&ring->request_list); | |
64193406 CW |
4939 | } |
4940 | ||
7e0d96bc BW |
4941 | void i915_init_vm(struct drm_i915_private *dev_priv, |
4942 | struct i915_address_space *vm) | |
fc8c067e | 4943 | { |
7e0d96bc BW |
4944 | if (!i915_is_ggtt(vm)) |
4945 | drm_mm_init(&vm->mm, vm->start, vm->total); | |
fc8c067e BW |
4946 | vm->dev = dev_priv->dev; |
4947 | INIT_LIST_HEAD(&vm->active_list); | |
4948 | INIT_LIST_HEAD(&vm->inactive_list); | |
4949 | INIT_LIST_HEAD(&vm->global_link); | |
f72d21ed | 4950 | list_add_tail(&vm->global_link, &dev_priv->vm_list); |
fc8c067e BW |
4951 | } |
4952 | ||
673a394b EA |
4953 | void |
4954 | i915_gem_load(struct drm_device *dev) | |
4955 | { | |
3e31c6c0 | 4956 | struct drm_i915_private *dev_priv = dev->dev_private; |
42dcedd4 CW |
4957 | int i; |
4958 | ||
4959 | dev_priv->slab = | |
4960 | kmem_cache_create("i915_gem_object", | |
4961 | sizeof(struct drm_i915_gem_object), 0, | |
4962 | SLAB_HWCACHE_ALIGN, | |
4963 | NULL); | |
673a394b | 4964 | |
fc8c067e BW |
4965 | INIT_LIST_HEAD(&dev_priv->vm_list); |
4966 | i915_init_vm(dev_priv, &dev_priv->gtt.base); | |
4967 | ||
a33afea5 | 4968 | INIT_LIST_HEAD(&dev_priv->context_list); |
6c085a72 CW |
4969 | INIT_LIST_HEAD(&dev_priv->mm.unbound_list); |
4970 | INIT_LIST_HEAD(&dev_priv->mm.bound_list); | |
a09ba7fa | 4971 | INIT_LIST_HEAD(&dev_priv->mm.fence_list); |
1ec14ad3 CW |
4972 | for (i = 0; i < I915_NUM_RINGS; i++) |
4973 | init_ring_lists(&dev_priv->ring[i]); | |
4b9de737 | 4974 | for (i = 0; i < I915_MAX_NUM_FENCES; i++) |
007cc8ac | 4975 | INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list); |
673a394b EA |
4976 | INIT_DELAYED_WORK(&dev_priv->mm.retire_work, |
4977 | i915_gem_retire_work_handler); | |
b29c19b6 CW |
4978 | INIT_DELAYED_WORK(&dev_priv->mm.idle_work, |
4979 | i915_gem_idle_work_handler); | |
1f83fee0 | 4980 | init_waitqueue_head(&dev_priv->gpu_error.reset_queue); |
31169714 | 4981 | |
94400120 | 4982 | /* On GEN3 we really need to make sure the ARB C3 LP bit is set */ |
dbb42748 | 4983 | if (!drm_core_check_feature(dev, DRIVER_MODESET) && IS_GEN3(dev)) { |
50743298 DV |
4984 | I915_WRITE(MI_ARB_STATE, |
4985 | _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE)); | |
94400120 DA |
4986 | } |
4987 | ||
72bfa19c CW |
4988 | dev_priv->relative_constants_mode = I915_EXEC_CONSTANTS_REL_GENERAL; |
4989 | ||
de151cf6 | 4990 | /* Old X drivers will take 0-2 for front, back, depth buffers */ |
b397c836 EA |
4991 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) |
4992 | dev_priv->fence_reg_start = 3; | |
de151cf6 | 4993 | |
42b5aeab VS |
4994 | if (INTEL_INFO(dev)->gen >= 7 && !IS_VALLEYVIEW(dev)) |
4995 | dev_priv->num_fence_regs = 32; | |
4996 | else if (INTEL_INFO(dev)->gen >= 4 || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) | |
de151cf6 JB |
4997 | dev_priv->num_fence_regs = 16; |
4998 | else | |
4999 | dev_priv->num_fence_regs = 8; | |
5000 | ||
b5aa8a0f | 5001 | /* Initialize fence registers to zero */ |
19b2dbde CW |
5002 | INIT_LIST_HEAD(&dev_priv->mm.fence_list); |
5003 | i915_gem_restore_fences(dev); | |
10ed13e4 | 5004 | |
673a394b | 5005 | i915_gem_detect_bit_6_swizzle(dev); |
6b95a207 | 5006 | init_waitqueue_head(&dev_priv->pending_flip_queue); |
17250b71 | 5007 | |
ce453d81 CW |
5008 | dev_priv->mm.interruptible = true; |
5009 | ||
ceabbba5 CW |
5010 | dev_priv->mm.shrinker.scan_objects = i915_gem_shrinker_scan; |
5011 | dev_priv->mm.shrinker.count_objects = i915_gem_shrinker_count; | |
5012 | dev_priv->mm.shrinker.seeks = DEFAULT_SEEKS; | |
5013 | register_shrinker(&dev_priv->mm.shrinker); | |
2cfcd32a CW |
5014 | |
5015 | dev_priv->mm.oom_notifier.notifier_call = i915_gem_shrinker_oom; | |
5016 | register_oom_notifier(&dev_priv->mm.oom_notifier); | |
f99d7069 DV |
5017 | |
5018 | mutex_init(&dev_priv->fb_tracking.lock); | |
673a394b | 5019 | } |
71acb5eb | 5020 | |
f787a5f5 | 5021 | void i915_gem_release(struct drm_device *dev, struct drm_file *file) |
b962442e | 5022 | { |
f787a5f5 | 5023 | struct drm_i915_file_private *file_priv = file->driver_priv; |
b962442e | 5024 | |
b29c19b6 CW |
5025 | cancel_delayed_work_sync(&file_priv->mm.idle_work); |
5026 | ||
b962442e EA |
5027 | /* Clean up our request list when the client is going away, so that |
5028 | * later retire_requests won't dereference our soon-to-be-gone | |
5029 | * file_priv. | |
5030 | */ | |
1c25595f | 5031 | spin_lock(&file_priv->mm.lock); |
f787a5f5 CW |
5032 | while (!list_empty(&file_priv->mm.request_list)) { |
5033 | struct drm_i915_gem_request *request; | |
5034 | ||
5035 | request = list_first_entry(&file_priv->mm.request_list, | |
5036 | struct drm_i915_gem_request, | |
5037 | client_list); | |
5038 | list_del(&request->client_list); | |
5039 | request->file_priv = NULL; | |
5040 | } | |
1c25595f | 5041 | spin_unlock(&file_priv->mm.lock); |
b962442e | 5042 | } |
31169714 | 5043 | |
b29c19b6 CW |
5044 | static void |
5045 | i915_gem_file_idle_work_handler(struct work_struct *work) | |
5046 | { | |
5047 | struct drm_i915_file_private *file_priv = | |
5048 | container_of(work, typeof(*file_priv), mm.idle_work.work); | |
5049 | ||
5050 | atomic_set(&file_priv->rps_wait_boost, false); | |
5051 | } | |
5052 | ||
5053 | int i915_gem_open(struct drm_device *dev, struct drm_file *file) | |
5054 | { | |
5055 | struct drm_i915_file_private *file_priv; | |
e422b888 | 5056 | int ret; |
b29c19b6 CW |
5057 | |
5058 | DRM_DEBUG_DRIVER("\n"); | |
5059 | ||
5060 | file_priv = kzalloc(sizeof(*file_priv), GFP_KERNEL); | |
5061 | if (!file_priv) | |
5062 | return -ENOMEM; | |
5063 | ||
5064 | file->driver_priv = file_priv; | |
5065 | file_priv->dev_priv = dev->dev_private; | |
ab0e7ff9 | 5066 | file_priv->file = file; |
b29c19b6 CW |
5067 | |
5068 | spin_lock_init(&file_priv->mm.lock); | |
5069 | INIT_LIST_HEAD(&file_priv->mm.request_list); | |
5070 | INIT_DELAYED_WORK(&file_priv->mm.idle_work, | |
5071 | i915_gem_file_idle_work_handler); | |
5072 | ||
e422b888 BW |
5073 | ret = i915_gem_context_open(dev, file); |
5074 | if (ret) | |
5075 | kfree(file_priv); | |
b29c19b6 | 5076 | |
e422b888 | 5077 | return ret; |
b29c19b6 CW |
5078 | } |
5079 | ||
a071fa00 DV |
5080 | void i915_gem_track_fb(struct drm_i915_gem_object *old, |
5081 | struct drm_i915_gem_object *new, | |
5082 | unsigned frontbuffer_bits) | |
5083 | { | |
5084 | if (old) { | |
5085 | WARN_ON(!mutex_is_locked(&old->base.dev->struct_mutex)); | |
5086 | WARN_ON(!(old->frontbuffer_bits & frontbuffer_bits)); | |
5087 | old->frontbuffer_bits &= ~frontbuffer_bits; | |
5088 | } | |
5089 | ||
5090 | if (new) { | |
5091 | WARN_ON(!mutex_is_locked(&new->base.dev->struct_mutex)); | |
5092 | WARN_ON(new->frontbuffer_bits & frontbuffer_bits); | |
5093 | new->frontbuffer_bits |= frontbuffer_bits; | |
5094 | } | |
5095 | } | |
5096 | ||
5774506f CW |
5097 | static bool mutex_is_locked_by(struct mutex *mutex, struct task_struct *task) |
5098 | { | |
5099 | if (!mutex_is_locked(mutex)) | |
5100 | return false; | |
5101 | ||
5102 | #if defined(CONFIG_SMP) || defined(CONFIG_DEBUG_MUTEXES) | |
5103 | return mutex->owner == task; | |
5104 | #else | |
5105 | /* Since UP may be pre-empted, we cannot assume that we own the lock */ | |
5106 | return false; | |
5107 | #endif | |
5108 | } | |
5109 | ||
b453c4db CW |
5110 | static bool i915_gem_shrinker_lock(struct drm_device *dev, bool *unlock) |
5111 | { | |
5112 | if (!mutex_trylock(&dev->struct_mutex)) { | |
5113 | if (!mutex_is_locked_by(&dev->struct_mutex, current)) | |
5114 | return false; | |
5115 | ||
5116 | if (to_i915(dev)->mm.shrinker_no_lock_stealing) | |
5117 | return false; | |
5118 | ||
5119 | *unlock = false; | |
5120 | } else | |
5121 | *unlock = true; | |
5122 | ||
5123 | return true; | |
5124 | } | |
5125 | ||
ceabbba5 CW |
5126 | static int num_vma_bound(struct drm_i915_gem_object *obj) |
5127 | { | |
5128 | struct i915_vma *vma; | |
5129 | int count = 0; | |
5130 | ||
5131 | list_for_each_entry(vma, &obj->vma_list, vma_link) | |
5132 | if (drm_mm_node_allocated(&vma->node)) | |
5133 | count++; | |
5134 | ||
5135 | return count; | |
5136 | } | |
5137 | ||
7dc19d5a | 5138 | static unsigned long |
ceabbba5 | 5139 | i915_gem_shrinker_count(struct shrinker *shrinker, struct shrink_control *sc) |
31169714 | 5140 | { |
17250b71 | 5141 | struct drm_i915_private *dev_priv = |
ceabbba5 | 5142 | container_of(shrinker, struct drm_i915_private, mm.shrinker); |
17250b71 | 5143 | struct drm_device *dev = dev_priv->dev; |
6c085a72 | 5144 | struct drm_i915_gem_object *obj; |
7dc19d5a | 5145 | unsigned long count; |
b453c4db | 5146 | bool unlock; |
17250b71 | 5147 | |
b453c4db CW |
5148 | if (!i915_gem_shrinker_lock(dev, &unlock)) |
5149 | return 0; | |
31169714 | 5150 | |
7dc19d5a | 5151 | count = 0; |
35c20a60 | 5152 | list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) |
a5570178 | 5153 | if (obj->pages_pin_count == 0) |
7dc19d5a | 5154 | count += obj->base.size >> PAGE_SHIFT; |
fcb4a578 BW |
5155 | |
5156 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) { | |
ceabbba5 CW |
5157 | if (!i915_gem_obj_is_pinned(obj) && |
5158 | obj->pages_pin_count == num_vma_bound(obj)) | |
7dc19d5a | 5159 | count += obj->base.size >> PAGE_SHIFT; |
fcb4a578 | 5160 | } |
17250b71 | 5161 | |
5774506f CW |
5162 | if (unlock) |
5163 | mutex_unlock(&dev->struct_mutex); | |
d9973b43 | 5164 | |
7dc19d5a | 5165 | return count; |
31169714 | 5166 | } |
a70a3148 BW |
5167 | |
5168 | /* All the new VM stuff */ | |
5169 | unsigned long i915_gem_obj_offset(struct drm_i915_gem_object *o, | |
5170 | struct i915_address_space *vm) | |
5171 | { | |
5172 | struct drm_i915_private *dev_priv = o->base.dev->dev_private; | |
5173 | struct i915_vma *vma; | |
5174 | ||
896ab1a5 | 5175 | WARN_ON(vm == &dev_priv->mm.aliasing_ppgtt->base); |
a70a3148 | 5176 | |
a70a3148 BW |
5177 | list_for_each_entry(vma, &o->vma_list, vma_link) { |
5178 | if (vma->vm == vm) | |
5179 | return vma->node.start; | |
5180 | ||
5181 | } | |
f25748ea DV |
5182 | WARN(1, "%s vma for this object not found.\n", |
5183 | i915_is_ggtt(vm) ? "global" : "ppgtt"); | |
a70a3148 BW |
5184 | return -1; |
5185 | } | |
5186 | ||
5187 | bool i915_gem_obj_bound(struct drm_i915_gem_object *o, | |
5188 | struct i915_address_space *vm) | |
5189 | { | |
5190 | struct i915_vma *vma; | |
5191 | ||
5192 | list_for_each_entry(vma, &o->vma_list, vma_link) | |
8b9c2b94 | 5193 | if (vma->vm == vm && drm_mm_node_allocated(&vma->node)) |
a70a3148 BW |
5194 | return true; |
5195 | ||
5196 | return false; | |
5197 | } | |
5198 | ||
5199 | bool i915_gem_obj_bound_any(struct drm_i915_gem_object *o) | |
5200 | { | |
5a1d5eb0 | 5201 | struct i915_vma *vma; |
a70a3148 | 5202 | |
5a1d5eb0 CW |
5203 | list_for_each_entry(vma, &o->vma_list, vma_link) |
5204 | if (drm_mm_node_allocated(&vma->node)) | |
a70a3148 BW |
5205 | return true; |
5206 | ||
5207 | return false; | |
5208 | } | |
5209 | ||
5210 | unsigned long i915_gem_obj_size(struct drm_i915_gem_object *o, | |
5211 | struct i915_address_space *vm) | |
5212 | { | |
5213 | struct drm_i915_private *dev_priv = o->base.dev->dev_private; | |
5214 | struct i915_vma *vma; | |
5215 | ||
896ab1a5 | 5216 | WARN_ON(vm == &dev_priv->mm.aliasing_ppgtt->base); |
a70a3148 BW |
5217 | |
5218 | BUG_ON(list_empty(&o->vma_list)); | |
5219 | ||
5220 | list_for_each_entry(vma, &o->vma_list, vma_link) | |
5221 | if (vma->vm == vm) | |
5222 | return vma->node.size; | |
5223 | ||
5224 | return 0; | |
5225 | } | |
5226 | ||
7dc19d5a | 5227 | static unsigned long |
ceabbba5 | 5228 | i915_gem_shrinker_scan(struct shrinker *shrinker, struct shrink_control *sc) |
7dc19d5a DC |
5229 | { |
5230 | struct drm_i915_private *dev_priv = | |
ceabbba5 | 5231 | container_of(shrinker, struct drm_i915_private, mm.shrinker); |
7dc19d5a | 5232 | struct drm_device *dev = dev_priv->dev; |
7dc19d5a | 5233 | unsigned long freed; |
b453c4db | 5234 | bool unlock; |
7dc19d5a | 5235 | |
b453c4db CW |
5236 | if (!i915_gem_shrinker_lock(dev, &unlock)) |
5237 | return SHRINK_STOP; | |
7dc19d5a | 5238 | |
21ab4e74 CW |
5239 | freed = i915_gem_shrink(dev_priv, |
5240 | sc->nr_to_scan, | |
5241 | I915_SHRINK_BOUND | | |
5242 | I915_SHRINK_UNBOUND | | |
5243 | I915_SHRINK_PURGEABLE); | |
d9973b43 | 5244 | if (freed < sc->nr_to_scan) |
21ab4e74 CW |
5245 | freed += i915_gem_shrink(dev_priv, |
5246 | sc->nr_to_scan - freed, | |
5247 | I915_SHRINK_BOUND | | |
5248 | I915_SHRINK_UNBOUND); | |
7dc19d5a DC |
5249 | if (unlock) |
5250 | mutex_unlock(&dev->struct_mutex); | |
d9973b43 | 5251 | |
7dc19d5a DC |
5252 | return freed; |
5253 | } | |
5c2abbea | 5254 | |
2cfcd32a CW |
5255 | static int |
5256 | i915_gem_shrinker_oom(struct notifier_block *nb, unsigned long event, void *ptr) | |
5257 | { | |
5258 | struct drm_i915_private *dev_priv = | |
5259 | container_of(nb, struct drm_i915_private, mm.oom_notifier); | |
5260 | struct drm_device *dev = dev_priv->dev; | |
5261 | struct drm_i915_gem_object *obj; | |
5262 | unsigned long timeout = msecs_to_jiffies(5000) + 1; | |
5263 | unsigned long pinned, bound, unbound, freed; | |
5264 | bool was_interruptible; | |
5265 | bool unlock; | |
5266 | ||
a1db2fa7 | 5267 | while (!i915_gem_shrinker_lock(dev, &unlock) && --timeout) { |
2cfcd32a | 5268 | schedule_timeout_killable(1); |
a1db2fa7 CW |
5269 | if (fatal_signal_pending(current)) |
5270 | return NOTIFY_DONE; | |
5271 | } | |
2cfcd32a CW |
5272 | if (timeout == 0) { |
5273 | pr_err("Unable to purge GPU memory due lock contention.\n"); | |
5274 | return NOTIFY_DONE; | |
5275 | } | |
5276 | ||
5277 | was_interruptible = dev_priv->mm.interruptible; | |
5278 | dev_priv->mm.interruptible = false; | |
5279 | ||
5280 | freed = i915_gem_shrink_all(dev_priv); | |
5281 | ||
5282 | dev_priv->mm.interruptible = was_interruptible; | |
5283 | ||
5284 | /* Because we may be allocating inside our own driver, we cannot | |
5285 | * assert that there are no objects with pinned pages that are not | |
5286 | * being pointed to by hardware. | |
5287 | */ | |
5288 | unbound = bound = pinned = 0; | |
5289 | list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) { | |
5290 | if (!obj->base.filp) /* not backed by a freeable object */ | |
5291 | continue; | |
5292 | ||
5293 | if (obj->pages_pin_count) | |
5294 | pinned += obj->base.size; | |
5295 | else | |
5296 | unbound += obj->base.size; | |
5297 | } | |
5298 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) { | |
5299 | if (!obj->base.filp) | |
5300 | continue; | |
5301 | ||
5302 | if (obj->pages_pin_count) | |
5303 | pinned += obj->base.size; | |
5304 | else | |
5305 | bound += obj->base.size; | |
5306 | } | |
5307 | ||
5308 | if (unlock) | |
5309 | mutex_unlock(&dev->struct_mutex); | |
5310 | ||
5311 | pr_info("Purging GPU memory, %lu bytes freed, %lu bytes still pinned.\n", | |
5312 | freed, pinned); | |
5313 | if (unbound || bound) | |
5314 | pr_err("%lu and %lu bytes still available in the " | |
5315 | "bound and unbound GPU page lists.\n", | |
5316 | bound, unbound); | |
5317 | ||
5318 | *(unsigned long *)ptr += freed; | |
5319 | return NOTIFY_DONE; | |
5320 | } | |
5321 | ||
5c2abbea BW |
5322 | struct i915_vma *i915_gem_obj_to_ggtt(struct drm_i915_gem_object *obj) |
5323 | { | |
5324 | struct i915_vma *vma; | |
5325 | ||
5c2abbea | 5326 | vma = list_first_entry(&obj->vma_list, typeof(*vma), vma_link); |
5dc383b0 | 5327 | if (vma->vm != i915_obj_to_ggtt(obj)) |
5c2abbea BW |
5328 | return NULL; |
5329 | ||
5330 | return vma; | |
5331 | } |