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Commit | Line | Data |
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673a394b EA |
1 | /* |
2 | * Copyright © 2008 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | * | |
26 | */ | |
27 | ||
760285e7 DH |
28 | #include <drm/drmP.h> |
29 | #include <drm/i915_drm.h> | |
673a394b | 30 | #include "i915_drv.h" |
1c5d22f7 | 31 | #include "i915_trace.h" |
652c393a | 32 | #include "intel_drv.h" |
5949eac4 | 33 | #include <linux/shmem_fs.h> |
5a0e3ad6 | 34 | #include <linux/slab.h> |
673a394b | 35 | #include <linux/swap.h> |
79e53945 | 36 | #include <linux/pci.h> |
1286ff73 | 37 | #include <linux/dma-buf.h> |
673a394b | 38 | |
05394f39 CW |
39 | static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj); |
40 | static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj); | |
88241785 CW |
41 | static __must_check int i915_gem_object_bind_to_gtt(struct drm_i915_gem_object *obj, |
42 | unsigned alignment, | |
86a1ee26 CW |
43 | bool map_and_fenceable, |
44 | bool nonblocking); | |
05394f39 CW |
45 | static int i915_gem_phys_pwrite(struct drm_device *dev, |
46 | struct drm_i915_gem_object *obj, | |
71acb5eb | 47 | struct drm_i915_gem_pwrite *args, |
05394f39 | 48 | struct drm_file *file); |
673a394b | 49 | |
61050808 CW |
50 | static void i915_gem_write_fence(struct drm_device *dev, int reg, |
51 | struct drm_i915_gem_object *obj); | |
52 | static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj, | |
53 | struct drm_i915_fence_reg *fence, | |
54 | bool enable); | |
55 | ||
17250b71 | 56 | static int i915_gem_inactive_shrink(struct shrinker *shrinker, |
1495f230 | 57 | struct shrink_control *sc); |
6c085a72 CW |
58 | static long i915_gem_purge(struct drm_i915_private *dev_priv, long target); |
59 | static void i915_gem_shrink_all(struct drm_i915_private *dev_priv); | |
8c59967c | 60 | static void i915_gem_object_truncate(struct drm_i915_gem_object *obj); |
31169714 | 61 | |
61050808 CW |
62 | static inline void i915_gem_object_fence_lost(struct drm_i915_gem_object *obj) |
63 | { | |
64 | if (obj->tiling_mode) | |
65 | i915_gem_release_mmap(obj); | |
66 | ||
67 | /* As we do not have an associated fence register, we will force | |
68 | * a tiling change if we ever need to acquire one. | |
69 | */ | |
5d82e3e6 | 70 | obj->fence_dirty = false; |
61050808 CW |
71 | obj->fence_reg = I915_FENCE_REG_NONE; |
72 | } | |
73 | ||
73aa808f CW |
74 | /* some bookkeeping */ |
75 | static void i915_gem_info_add_obj(struct drm_i915_private *dev_priv, | |
76 | size_t size) | |
77 | { | |
78 | dev_priv->mm.object_count++; | |
79 | dev_priv->mm.object_memory += size; | |
80 | } | |
81 | ||
82 | static void i915_gem_info_remove_obj(struct drm_i915_private *dev_priv, | |
83 | size_t size) | |
84 | { | |
85 | dev_priv->mm.object_count--; | |
86 | dev_priv->mm.object_memory -= size; | |
87 | } | |
88 | ||
21dd3734 | 89 | static int |
33196ded | 90 | i915_gem_wait_for_error(struct i915_gpu_error *error) |
30dbf0c0 | 91 | { |
33196ded | 92 | struct completion *x = &error->completion; |
30dbf0c0 CW |
93 | unsigned long flags; |
94 | int ret; | |
95 | ||
33196ded | 96 | if (!atomic_read(&error->wedged)) |
30dbf0c0 CW |
97 | return 0; |
98 | ||
0a6759c6 DV |
99 | /* |
100 | * Only wait 10 seconds for the gpu reset to complete to avoid hanging | |
101 | * userspace. If it takes that long something really bad is going on and | |
102 | * we should simply try to bail out and fail as gracefully as possible. | |
103 | */ | |
104 | ret = wait_for_completion_interruptible_timeout(x, 10*HZ); | |
105 | if (ret == 0) { | |
106 | DRM_ERROR("Timed out waiting for the gpu reset to complete\n"); | |
107 | return -EIO; | |
108 | } else if (ret < 0) { | |
30dbf0c0 | 109 | return ret; |
0a6759c6 | 110 | } |
30dbf0c0 | 111 | |
33196ded | 112 | if (atomic_read(&error->wedged)) { |
21dd3734 CW |
113 | /* GPU is hung, bump the completion count to account for |
114 | * the token we just consumed so that we never hit zero and | |
115 | * end up waiting upon a subsequent completion event that | |
116 | * will never happen. | |
117 | */ | |
118 | spin_lock_irqsave(&x->wait.lock, flags); | |
119 | x->done++; | |
120 | spin_unlock_irqrestore(&x->wait.lock, flags); | |
121 | } | |
122 | return 0; | |
30dbf0c0 CW |
123 | } |
124 | ||
54cf91dc | 125 | int i915_mutex_lock_interruptible(struct drm_device *dev) |
76c1dec1 | 126 | { |
33196ded | 127 | struct drm_i915_private *dev_priv = dev->dev_private; |
76c1dec1 CW |
128 | int ret; |
129 | ||
33196ded | 130 | ret = i915_gem_wait_for_error(&dev_priv->gpu_error); |
76c1dec1 CW |
131 | if (ret) |
132 | return ret; | |
133 | ||
134 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
135 | if (ret) | |
136 | return ret; | |
137 | ||
23bc5982 | 138 | WARN_ON(i915_verify_lists(dev)); |
76c1dec1 CW |
139 | return 0; |
140 | } | |
30dbf0c0 | 141 | |
7d1c4804 | 142 | static inline bool |
05394f39 | 143 | i915_gem_object_is_inactive(struct drm_i915_gem_object *obj) |
7d1c4804 | 144 | { |
6c085a72 | 145 | return obj->gtt_space && !obj->active; |
7d1c4804 CW |
146 | } |
147 | ||
79e53945 JB |
148 | int |
149 | i915_gem_init_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 150 | struct drm_file *file) |
79e53945 | 151 | { |
93d18799 | 152 | struct drm_i915_private *dev_priv = dev->dev_private; |
79e53945 | 153 | struct drm_i915_gem_init *args = data; |
2021746e | 154 | |
7bb6fb8d DV |
155 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
156 | return -ENODEV; | |
157 | ||
2021746e CW |
158 | if (args->gtt_start >= args->gtt_end || |
159 | (args->gtt_end | args->gtt_start) & (PAGE_SIZE - 1)) | |
160 | return -EINVAL; | |
79e53945 | 161 | |
f534bc0b DV |
162 | /* GEM with user mode setting was never supported on ilk and later. */ |
163 | if (INTEL_INFO(dev)->gen >= 5) | |
164 | return -ENODEV; | |
165 | ||
79e53945 | 166 | mutex_lock(&dev->struct_mutex); |
d7e5008f BW |
167 | i915_gem_setup_global_gtt(dev, args->gtt_start, args->gtt_end, |
168 | args->gtt_end); | |
93d18799 | 169 | dev_priv->gtt.mappable_end = args->gtt_end; |
673a394b EA |
170 | mutex_unlock(&dev->struct_mutex); |
171 | ||
2021746e | 172 | return 0; |
673a394b EA |
173 | } |
174 | ||
5a125c3c EA |
175 | int |
176 | i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 177 | struct drm_file *file) |
5a125c3c | 178 | { |
73aa808f | 179 | struct drm_i915_private *dev_priv = dev->dev_private; |
5a125c3c | 180 | struct drm_i915_gem_get_aperture *args = data; |
6299f992 CW |
181 | struct drm_i915_gem_object *obj; |
182 | size_t pinned; | |
5a125c3c | 183 | |
6299f992 | 184 | pinned = 0; |
73aa808f | 185 | mutex_lock(&dev->struct_mutex); |
6c085a72 | 186 | list_for_each_entry(obj, &dev_priv->mm.bound_list, gtt_list) |
1b50247a CW |
187 | if (obj->pin_count) |
188 | pinned += obj->gtt_space->size; | |
73aa808f | 189 | mutex_unlock(&dev->struct_mutex); |
5a125c3c | 190 | |
5d4545ae | 191 | args->aper_size = dev_priv->gtt.total; |
0206e353 | 192 | args->aper_available_size = args->aper_size - pinned; |
6299f992 | 193 | |
5a125c3c EA |
194 | return 0; |
195 | } | |
196 | ||
42dcedd4 CW |
197 | void *i915_gem_object_alloc(struct drm_device *dev) |
198 | { | |
199 | struct drm_i915_private *dev_priv = dev->dev_private; | |
200 | return kmem_cache_alloc(dev_priv->slab, GFP_KERNEL | __GFP_ZERO); | |
201 | } | |
202 | ||
203 | void i915_gem_object_free(struct drm_i915_gem_object *obj) | |
204 | { | |
205 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; | |
206 | kmem_cache_free(dev_priv->slab, obj); | |
207 | } | |
208 | ||
ff72145b DA |
209 | static int |
210 | i915_gem_create(struct drm_file *file, | |
211 | struct drm_device *dev, | |
212 | uint64_t size, | |
213 | uint32_t *handle_p) | |
673a394b | 214 | { |
05394f39 | 215 | struct drm_i915_gem_object *obj; |
a1a2d1d3 PP |
216 | int ret; |
217 | u32 handle; | |
673a394b | 218 | |
ff72145b | 219 | size = roundup(size, PAGE_SIZE); |
8ffc0246 CW |
220 | if (size == 0) |
221 | return -EINVAL; | |
673a394b EA |
222 | |
223 | /* Allocate the new object */ | |
ff72145b | 224 | obj = i915_gem_alloc_object(dev, size); |
673a394b EA |
225 | if (obj == NULL) |
226 | return -ENOMEM; | |
227 | ||
05394f39 | 228 | ret = drm_gem_handle_create(file, &obj->base, &handle); |
1dfd9754 | 229 | if (ret) { |
05394f39 CW |
230 | drm_gem_object_release(&obj->base); |
231 | i915_gem_info_remove_obj(dev->dev_private, obj->base.size); | |
42dcedd4 | 232 | i915_gem_object_free(obj); |
673a394b | 233 | return ret; |
1dfd9754 | 234 | } |
673a394b | 235 | |
202f2fef | 236 | /* drop reference from allocate - handle holds it now */ |
05394f39 | 237 | drm_gem_object_unreference(&obj->base); |
202f2fef CW |
238 | trace_i915_gem_object_create(obj); |
239 | ||
ff72145b | 240 | *handle_p = handle; |
673a394b EA |
241 | return 0; |
242 | } | |
243 | ||
ff72145b DA |
244 | int |
245 | i915_gem_dumb_create(struct drm_file *file, | |
246 | struct drm_device *dev, | |
247 | struct drm_mode_create_dumb *args) | |
248 | { | |
249 | /* have to work out size/pitch and return them */ | |
ed0291fd | 250 | args->pitch = ALIGN(args->width * ((args->bpp + 7) / 8), 64); |
ff72145b DA |
251 | args->size = args->pitch * args->height; |
252 | return i915_gem_create(file, dev, | |
253 | args->size, &args->handle); | |
254 | } | |
255 | ||
256 | int i915_gem_dumb_destroy(struct drm_file *file, | |
257 | struct drm_device *dev, | |
258 | uint32_t handle) | |
259 | { | |
260 | return drm_gem_handle_delete(file, handle); | |
261 | } | |
262 | ||
263 | /** | |
264 | * Creates a new mm object and returns a handle to it. | |
265 | */ | |
266 | int | |
267 | i915_gem_create_ioctl(struct drm_device *dev, void *data, | |
268 | struct drm_file *file) | |
269 | { | |
270 | struct drm_i915_gem_create *args = data; | |
63ed2cb2 | 271 | |
ff72145b DA |
272 | return i915_gem_create(file, dev, |
273 | args->size, &args->handle); | |
274 | } | |
275 | ||
8461d226 DV |
276 | static inline int |
277 | __copy_to_user_swizzled(char __user *cpu_vaddr, | |
278 | const char *gpu_vaddr, int gpu_offset, | |
279 | int length) | |
280 | { | |
281 | int ret, cpu_offset = 0; | |
282 | ||
283 | while (length > 0) { | |
284 | int cacheline_end = ALIGN(gpu_offset + 1, 64); | |
285 | int this_length = min(cacheline_end - gpu_offset, length); | |
286 | int swizzled_gpu_offset = gpu_offset ^ 64; | |
287 | ||
288 | ret = __copy_to_user(cpu_vaddr + cpu_offset, | |
289 | gpu_vaddr + swizzled_gpu_offset, | |
290 | this_length); | |
291 | if (ret) | |
292 | return ret + length; | |
293 | ||
294 | cpu_offset += this_length; | |
295 | gpu_offset += this_length; | |
296 | length -= this_length; | |
297 | } | |
298 | ||
299 | return 0; | |
300 | } | |
301 | ||
8c59967c | 302 | static inline int |
4f0c7cfb BW |
303 | __copy_from_user_swizzled(char *gpu_vaddr, int gpu_offset, |
304 | const char __user *cpu_vaddr, | |
8c59967c DV |
305 | int length) |
306 | { | |
307 | int ret, cpu_offset = 0; | |
308 | ||
309 | while (length > 0) { | |
310 | int cacheline_end = ALIGN(gpu_offset + 1, 64); | |
311 | int this_length = min(cacheline_end - gpu_offset, length); | |
312 | int swizzled_gpu_offset = gpu_offset ^ 64; | |
313 | ||
314 | ret = __copy_from_user(gpu_vaddr + swizzled_gpu_offset, | |
315 | cpu_vaddr + cpu_offset, | |
316 | this_length); | |
317 | if (ret) | |
318 | return ret + length; | |
319 | ||
320 | cpu_offset += this_length; | |
321 | gpu_offset += this_length; | |
322 | length -= this_length; | |
323 | } | |
324 | ||
325 | return 0; | |
326 | } | |
327 | ||
d174bd64 DV |
328 | /* Per-page copy function for the shmem pread fastpath. |
329 | * Flushes invalid cachelines before reading the target if | |
330 | * needs_clflush is set. */ | |
eb01459f | 331 | static int |
d174bd64 DV |
332 | shmem_pread_fast(struct page *page, int shmem_page_offset, int page_length, |
333 | char __user *user_data, | |
334 | bool page_do_bit17_swizzling, bool needs_clflush) | |
335 | { | |
336 | char *vaddr; | |
337 | int ret; | |
338 | ||
e7e58eb5 | 339 | if (unlikely(page_do_bit17_swizzling)) |
d174bd64 DV |
340 | return -EINVAL; |
341 | ||
342 | vaddr = kmap_atomic(page); | |
343 | if (needs_clflush) | |
344 | drm_clflush_virt_range(vaddr + shmem_page_offset, | |
345 | page_length); | |
346 | ret = __copy_to_user_inatomic(user_data, | |
347 | vaddr + shmem_page_offset, | |
348 | page_length); | |
349 | kunmap_atomic(vaddr); | |
350 | ||
f60d7f0c | 351 | return ret ? -EFAULT : 0; |
d174bd64 DV |
352 | } |
353 | ||
23c18c71 DV |
354 | static void |
355 | shmem_clflush_swizzled_range(char *addr, unsigned long length, | |
356 | bool swizzled) | |
357 | { | |
e7e58eb5 | 358 | if (unlikely(swizzled)) { |
23c18c71 DV |
359 | unsigned long start = (unsigned long) addr; |
360 | unsigned long end = (unsigned long) addr + length; | |
361 | ||
362 | /* For swizzling simply ensure that we always flush both | |
363 | * channels. Lame, but simple and it works. Swizzled | |
364 | * pwrite/pread is far from a hotpath - current userspace | |
365 | * doesn't use it at all. */ | |
366 | start = round_down(start, 128); | |
367 | end = round_up(end, 128); | |
368 | ||
369 | drm_clflush_virt_range((void *)start, end - start); | |
370 | } else { | |
371 | drm_clflush_virt_range(addr, length); | |
372 | } | |
373 | ||
374 | } | |
375 | ||
d174bd64 DV |
376 | /* Only difference to the fast-path function is that this can handle bit17 |
377 | * and uses non-atomic copy and kmap functions. */ | |
378 | static int | |
379 | shmem_pread_slow(struct page *page, int shmem_page_offset, int page_length, | |
380 | char __user *user_data, | |
381 | bool page_do_bit17_swizzling, bool needs_clflush) | |
382 | { | |
383 | char *vaddr; | |
384 | int ret; | |
385 | ||
386 | vaddr = kmap(page); | |
387 | if (needs_clflush) | |
23c18c71 DV |
388 | shmem_clflush_swizzled_range(vaddr + shmem_page_offset, |
389 | page_length, | |
390 | page_do_bit17_swizzling); | |
d174bd64 DV |
391 | |
392 | if (page_do_bit17_swizzling) | |
393 | ret = __copy_to_user_swizzled(user_data, | |
394 | vaddr, shmem_page_offset, | |
395 | page_length); | |
396 | else | |
397 | ret = __copy_to_user(user_data, | |
398 | vaddr + shmem_page_offset, | |
399 | page_length); | |
400 | kunmap(page); | |
401 | ||
f60d7f0c | 402 | return ret ? - EFAULT : 0; |
d174bd64 DV |
403 | } |
404 | ||
eb01459f | 405 | static int |
dbf7bff0 DV |
406 | i915_gem_shmem_pread(struct drm_device *dev, |
407 | struct drm_i915_gem_object *obj, | |
408 | struct drm_i915_gem_pread *args, | |
409 | struct drm_file *file) | |
eb01459f | 410 | { |
8461d226 | 411 | char __user *user_data; |
eb01459f | 412 | ssize_t remain; |
8461d226 | 413 | loff_t offset; |
eb2c0c81 | 414 | int shmem_page_offset, page_length, ret = 0; |
8461d226 | 415 | int obj_do_bit17_swizzling, page_do_bit17_swizzling; |
96d79b52 | 416 | int prefaulted = 0; |
8489731c | 417 | int needs_clflush = 0; |
9da3da66 CW |
418 | struct scatterlist *sg; |
419 | int i; | |
eb01459f | 420 | |
8461d226 | 421 | user_data = (char __user *) (uintptr_t) args->data_ptr; |
eb01459f EA |
422 | remain = args->size; |
423 | ||
8461d226 | 424 | obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj); |
eb01459f | 425 | |
8489731c DV |
426 | if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU)) { |
427 | /* If we're not in the cpu read domain, set ourself into the gtt | |
428 | * read domain and manually flush cachelines (if required). This | |
429 | * optimizes for the case when the gpu will dirty the data | |
430 | * anyway again before the next pread happens. */ | |
431 | if (obj->cache_level == I915_CACHE_NONE) | |
432 | needs_clflush = 1; | |
6c085a72 CW |
433 | if (obj->gtt_space) { |
434 | ret = i915_gem_object_set_to_gtt_domain(obj, false); | |
435 | if (ret) | |
436 | return ret; | |
437 | } | |
8489731c | 438 | } |
eb01459f | 439 | |
f60d7f0c CW |
440 | ret = i915_gem_object_get_pages(obj); |
441 | if (ret) | |
442 | return ret; | |
443 | ||
444 | i915_gem_object_pin_pages(obj); | |
445 | ||
8461d226 | 446 | offset = args->offset; |
eb01459f | 447 | |
9da3da66 | 448 | for_each_sg(obj->pages->sgl, sg, obj->pages->nents, i) { |
e5281ccd CW |
449 | struct page *page; |
450 | ||
9da3da66 CW |
451 | if (i < offset >> PAGE_SHIFT) |
452 | continue; | |
453 | ||
454 | if (remain <= 0) | |
455 | break; | |
456 | ||
eb01459f EA |
457 | /* Operation in this page |
458 | * | |
eb01459f | 459 | * shmem_page_offset = offset within page in shmem file |
eb01459f EA |
460 | * page_length = bytes to copy for this page |
461 | */ | |
c8cbbb8b | 462 | shmem_page_offset = offset_in_page(offset); |
eb01459f EA |
463 | page_length = remain; |
464 | if ((shmem_page_offset + page_length) > PAGE_SIZE) | |
465 | page_length = PAGE_SIZE - shmem_page_offset; | |
eb01459f | 466 | |
9da3da66 | 467 | page = sg_page(sg); |
8461d226 DV |
468 | page_do_bit17_swizzling = obj_do_bit17_swizzling && |
469 | (page_to_phys(page) & (1 << 17)) != 0; | |
470 | ||
d174bd64 DV |
471 | ret = shmem_pread_fast(page, shmem_page_offset, page_length, |
472 | user_data, page_do_bit17_swizzling, | |
473 | needs_clflush); | |
474 | if (ret == 0) | |
475 | goto next_page; | |
dbf7bff0 | 476 | |
dbf7bff0 DV |
477 | mutex_unlock(&dev->struct_mutex); |
478 | ||
96d79b52 | 479 | if (!prefaulted) { |
f56f821f | 480 | ret = fault_in_multipages_writeable(user_data, remain); |
96d79b52 DV |
481 | /* Userspace is tricking us, but we've already clobbered |
482 | * its pages with the prefault and promised to write the | |
483 | * data up to the first fault. Hence ignore any errors | |
484 | * and just continue. */ | |
485 | (void)ret; | |
486 | prefaulted = 1; | |
487 | } | |
eb01459f | 488 | |
d174bd64 DV |
489 | ret = shmem_pread_slow(page, shmem_page_offset, page_length, |
490 | user_data, page_do_bit17_swizzling, | |
491 | needs_clflush); | |
eb01459f | 492 | |
dbf7bff0 | 493 | mutex_lock(&dev->struct_mutex); |
f60d7f0c | 494 | |
dbf7bff0 | 495 | next_page: |
e5281ccd | 496 | mark_page_accessed(page); |
e5281ccd | 497 | |
f60d7f0c | 498 | if (ret) |
8461d226 | 499 | goto out; |
8461d226 | 500 | |
eb01459f | 501 | remain -= page_length; |
8461d226 | 502 | user_data += page_length; |
eb01459f EA |
503 | offset += page_length; |
504 | } | |
505 | ||
4f27b75d | 506 | out: |
f60d7f0c CW |
507 | i915_gem_object_unpin_pages(obj); |
508 | ||
eb01459f EA |
509 | return ret; |
510 | } | |
511 | ||
673a394b EA |
512 | /** |
513 | * Reads data from the object referenced by handle. | |
514 | * | |
515 | * On error, the contents of *data are undefined. | |
516 | */ | |
517 | int | |
518 | i915_gem_pread_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 519 | struct drm_file *file) |
673a394b EA |
520 | { |
521 | struct drm_i915_gem_pread *args = data; | |
05394f39 | 522 | struct drm_i915_gem_object *obj; |
35b62a89 | 523 | int ret = 0; |
673a394b | 524 | |
51311d0a CW |
525 | if (args->size == 0) |
526 | return 0; | |
527 | ||
528 | if (!access_ok(VERIFY_WRITE, | |
529 | (char __user *)(uintptr_t)args->data_ptr, | |
530 | args->size)) | |
531 | return -EFAULT; | |
532 | ||
4f27b75d | 533 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 534 | if (ret) |
4f27b75d | 535 | return ret; |
673a394b | 536 | |
05394f39 | 537 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 538 | if (&obj->base == NULL) { |
1d7cfea1 CW |
539 | ret = -ENOENT; |
540 | goto unlock; | |
4f27b75d | 541 | } |
673a394b | 542 | |
7dcd2499 | 543 | /* Bounds check source. */ |
05394f39 CW |
544 | if (args->offset > obj->base.size || |
545 | args->size > obj->base.size - args->offset) { | |
ce9d419d | 546 | ret = -EINVAL; |
35b62a89 | 547 | goto out; |
ce9d419d CW |
548 | } |
549 | ||
1286ff73 DV |
550 | /* prime objects have no backing filp to GEM pread/pwrite |
551 | * pages from. | |
552 | */ | |
553 | if (!obj->base.filp) { | |
554 | ret = -EINVAL; | |
555 | goto out; | |
556 | } | |
557 | ||
db53a302 CW |
558 | trace_i915_gem_object_pread(obj, args->offset, args->size); |
559 | ||
dbf7bff0 | 560 | ret = i915_gem_shmem_pread(dev, obj, args, file); |
673a394b | 561 | |
35b62a89 | 562 | out: |
05394f39 | 563 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 564 | unlock: |
4f27b75d | 565 | mutex_unlock(&dev->struct_mutex); |
eb01459f | 566 | return ret; |
673a394b EA |
567 | } |
568 | ||
0839ccb8 KP |
569 | /* This is the fast write path which cannot handle |
570 | * page faults in the source data | |
9b7530cc | 571 | */ |
0839ccb8 KP |
572 | |
573 | static inline int | |
574 | fast_user_write(struct io_mapping *mapping, | |
575 | loff_t page_base, int page_offset, | |
576 | char __user *user_data, | |
577 | int length) | |
9b7530cc | 578 | { |
4f0c7cfb BW |
579 | void __iomem *vaddr_atomic; |
580 | void *vaddr; | |
0839ccb8 | 581 | unsigned long unwritten; |
9b7530cc | 582 | |
3e4d3af5 | 583 | vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base); |
4f0c7cfb BW |
584 | /* We can use the cpu mem copy function because this is X86. */ |
585 | vaddr = (void __force*)vaddr_atomic + page_offset; | |
586 | unwritten = __copy_from_user_inatomic_nocache(vaddr, | |
0839ccb8 | 587 | user_data, length); |
3e4d3af5 | 588 | io_mapping_unmap_atomic(vaddr_atomic); |
fbd5a26d | 589 | return unwritten; |
0839ccb8 KP |
590 | } |
591 | ||
3de09aa3 EA |
592 | /** |
593 | * This is the fast pwrite path, where we copy the data directly from the | |
594 | * user into the GTT, uncached. | |
595 | */ | |
673a394b | 596 | static int |
05394f39 CW |
597 | i915_gem_gtt_pwrite_fast(struct drm_device *dev, |
598 | struct drm_i915_gem_object *obj, | |
3de09aa3 | 599 | struct drm_i915_gem_pwrite *args, |
05394f39 | 600 | struct drm_file *file) |
673a394b | 601 | { |
0839ccb8 | 602 | drm_i915_private_t *dev_priv = dev->dev_private; |
673a394b | 603 | ssize_t remain; |
0839ccb8 | 604 | loff_t offset, page_base; |
673a394b | 605 | char __user *user_data; |
935aaa69 DV |
606 | int page_offset, page_length, ret; |
607 | ||
86a1ee26 | 608 | ret = i915_gem_object_pin(obj, 0, true, true); |
935aaa69 DV |
609 | if (ret) |
610 | goto out; | |
611 | ||
612 | ret = i915_gem_object_set_to_gtt_domain(obj, true); | |
613 | if (ret) | |
614 | goto out_unpin; | |
615 | ||
616 | ret = i915_gem_object_put_fence(obj); | |
617 | if (ret) | |
618 | goto out_unpin; | |
673a394b EA |
619 | |
620 | user_data = (char __user *) (uintptr_t) args->data_ptr; | |
621 | remain = args->size; | |
673a394b | 622 | |
05394f39 | 623 | offset = obj->gtt_offset + args->offset; |
673a394b EA |
624 | |
625 | while (remain > 0) { | |
626 | /* Operation in this page | |
627 | * | |
0839ccb8 KP |
628 | * page_base = page offset within aperture |
629 | * page_offset = offset within page | |
630 | * page_length = bytes to copy for this page | |
673a394b | 631 | */ |
c8cbbb8b CW |
632 | page_base = offset & PAGE_MASK; |
633 | page_offset = offset_in_page(offset); | |
0839ccb8 KP |
634 | page_length = remain; |
635 | if ((page_offset + remain) > PAGE_SIZE) | |
636 | page_length = PAGE_SIZE - page_offset; | |
637 | ||
0839ccb8 | 638 | /* If we get a fault while copying data, then (presumably) our |
3de09aa3 EA |
639 | * source page isn't available. Return the error and we'll |
640 | * retry in the slow path. | |
0839ccb8 | 641 | */ |
5d4545ae | 642 | if (fast_user_write(dev_priv->gtt.mappable, page_base, |
935aaa69 DV |
643 | page_offset, user_data, page_length)) { |
644 | ret = -EFAULT; | |
645 | goto out_unpin; | |
646 | } | |
673a394b | 647 | |
0839ccb8 KP |
648 | remain -= page_length; |
649 | user_data += page_length; | |
650 | offset += page_length; | |
673a394b | 651 | } |
673a394b | 652 | |
935aaa69 DV |
653 | out_unpin: |
654 | i915_gem_object_unpin(obj); | |
655 | out: | |
3de09aa3 | 656 | return ret; |
673a394b EA |
657 | } |
658 | ||
d174bd64 DV |
659 | /* Per-page copy function for the shmem pwrite fastpath. |
660 | * Flushes invalid cachelines before writing to the target if | |
661 | * needs_clflush_before is set and flushes out any written cachelines after | |
662 | * writing if needs_clflush is set. */ | |
3043c60c | 663 | static int |
d174bd64 DV |
664 | shmem_pwrite_fast(struct page *page, int shmem_page_offset, int page_length, |
665 | char __user *user_data, | |
666 | bool page_do_bit17_swizzling, | |
667 | bool needs_clflush_before, | |
668 | bool needs_clflush_after) | |
673a394b | 669 | { |
d174bd64 | 670 | char *vaddr; |
673a394b | 671 | int ret; |
3de09aa3 | 672 | |
e7e58eb5 | 673 | if (unlikely(page_do_bit17_swizzling)) |
d174bd64 | 674 | return -EINVAL; |
3de09aa3 | 675 | |
d174bd64 DV |
676 | vaddr = kmap_atomic(page); |
677 | if (needs_clflush_before) | |
678 | drm_clflush_virt_range(vaddr + shmem_page_offset, | |
679 | page_length); | |
680 | ret = __copy_from_user_inatomic_nocache(vaddr + shmem_page_offset, | |
681 | user_data, | |
682 | page_length); | |
683 | if (needs_clflush_after) | |
684 | drm_clflush_virt_range(vaddr + shmem_page_offset, | |
685 | page_length); | |
686 | kunmap_atomic(vaddr); | |
3de09aa3 | 687 | |
755d2218 | 688 | return ret ? -EFAULT : 0; |
3de09aa3 EA |
689 | } |
690 | ||
d174bd64 DV |
691 | /* Only difference to the fast-path function is that this can handle bit17 |
692 | * and uses non-atomic copy and kmap functions. */ | |
3043c60c | 693 | static int |
d174bd64 DV |
694 | shmem_pwrite_slow(struct page *page, int shmem_page_offset, int page_length, |
695 | char __user *user_data, | |
696 | bool page_do_bit17_swizzling, | |
697 | bool needs_clflush_before, | |
698 | bool needs_clflush_after) | |
673a394b | 699 | { |
d174bd64 DV |
700 | char *vaddr; |
701 | int ret; | |
e5281ccd | 702 | |
d174bd64 | 703 | vaddr = kmap(page); |
e7e58eb5 | 704 | if (unlikely(needs_clflush_before || page_do_bit17_swizzling)) |
23c18c71 DV |
705 | shmem_clflush_swizzled_range(vaddr + shmem_page_offset, |
706 | page_length, | |
707 | page_do_bit17_swizzling); | |
d174bd64 DV |
708 | if (page_do_bit17_swizzling) |
709 | ret = __copy_from_user_swizzled(vaddr, shmem_page_offset, | |
e5281ccd CW |
710 | user_data, |
711 | page_length); | |
d174bd64 DV |
712 | else |
713 | ret = __copy_from_user(vaddr + shmem_page_offset, | |
714 | user_data, | |
715 | page_length); | |
716 | if (needs_clflush_after) | |
23c18c71 DV |
717 | shmem_clflush_swizzled_range(vaddr + shmem_page_offset, |
718 | page_length, | |
719 | page_do_bit17_swizzling); | |
d174bd64 | 720 | kunmap(page); |
40123c1f | 721 | |
755d2218 | 722 | return ret ? -EFAULT : 0; |
40123c1f EA |
723 | } |
724 | ||
40123c1f | 725 | static int |
e244a443 DV |
726 | i915_gem_shmem_pwrite(struct drm_device *dev, |
727 | struct drm_i915_gem_object *obj, | |
728 | struct drm_i915_gem_pwrite *args, | |
729 | struct drm_file *file) | |
40123c1f | 730 | { |
40123c1f | 731 | ssize_t remain; |
8c59967c DV |
732 | loff_t offset; |
733 | char __user *user_data; | |
eb2c0c81 | 734 | int shmem_page_offset, page_length, ret = 0; |
8c59967c | 735 | int obj_do_bit17_swizzling, page_do_bit17_swizzling; |
e244a443 | 736 | int hit_slowpath = 0; |
58642885 DV |
737 | int needs_clflush_after = 0; |
738 | int needs_clflush_before = 0; | |
9da3da66 CW |
739 | int i; |
740 | struct scatterlist *sg; | |
40123c1f | 741 | |
8c59967c | 742 | user_data = (char __user *) (uintptr_t) args->data_ptr; |
40123c1f EA |
743 | remain = args->size; |
744 | ||
8c59967c | 745 | obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj); |
40123c1f | 746 | |
58642885 DV |
747 | if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) { |
748 | /* If we're not in the cpu write domain, set ourself into the gtt | |
749 | * write domain and manually flush cachelines (if required). This | |
750 | * optimizes for the case when the gpu will use the data | |
751 | * right away and we therefore have to clflush anyway. */ | |
752 | if (obj->cache_level == I915_CACHE_NONE) | |
753 | needs_clflush_after = 1; | |
6c085a72 CW |
754 | if (obj->gtt_space) { |
755 | ret = i915_gem_object_set_to_gtt_domain(obj, true); | |
756 | if (ret) | |
757 | return ret; | |
758 | } | |
58642885 DV |
759 | } |
760 | /* Same trick applies for invalidate partially written cachelines before | |
761 | * writing. */ | |
762 | if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU) | |
763 | && obj->cache_level == I915_CACHE_NONE) | |
764 | needs_clflush_before = 1; | |
765 | ||
755d2218 CW |
766 | ret = i915_gem_object_get_pages(obj); |
767 | if (ret) | |
768 | return ret; | |
769 | ||
770 | i915_gem_object_pin_pages(obj); | |
771 | ||
673a394b | 772 | offset = args->offset; |
05394f39 | 773 | obj->dirty = 1; |
673a394b | 774 | |
9da3da66 | 775 | for_each_sg(obj->pages->sgl, sg, obj->pages->nents, i) { |
e5281ccd | 776 | struct page *page; |
58642885 | 777 | int partial_cacheline_write; |
e5281ccd | 778 | |
9da3da66 CW |
779 | if (i < offset >> PAGE_SHIFT) |
780 | continue; | |
781 | ||
782 | if (remain <= 0) | |
783 | break; | |
784 | ||
40123c1f EA |
785 | /* Operation in this page |
786 | * | |
40123c1f | 787 | * shmem_page_offset = offset within page in shmem file |
40123c1f EA |
788 | * page_length = bytes to copy for this page |
789 | */ | |
c8cbbb8b | 790 | shmem_page_offset = offset_in_page(offset); |
40123c1f EA |
791 | |
792 | page_length = remain; | |
793 | if ((shmem_page_offset + page_length) > PAGE_SIZE) | |
794 | page_length = PAGE_SIZE - shmem_page_offset; | |
40123c1f | 795 | |
58642885 DV |
796 | /* If we don't overwrite a cacheline completely we need to be |
797 | * careful to have up-to-date data by first clflushing. Don't | |
798 | * overcomplicate things and flush the entire patch. */ | |
799 | partial_cacheline_write = needs_clflush_before && | |
800 | ((shmem_page_offset | page_length) | |
801 | & (boot_cpu_data.x86_clflush_size - 1)); | |
802 | ||
9da3da66 | 803 | page = sg_page(sg); |
8c59967c DV |
804 | page_do_bit17_swizzling = obj_do_bit17_swizzling && |
805 | (page_to_phys(page) & (1 << 17)) != 0; | |
806 | ||
d174bd64 DV |
807 | ret = shmem_pwrite_fast(page, shmem_page_offset, page_length, |
808 | user_data, page_do_bit17_swizzling, | |
809 | partial_cacheline_write, | |
810 | needs_clflush_after); | |
811 | if (ret == 0) | |
812 | goto next_page; | |
e244a443 DV |
813 | |
814 | hit_slowpath = 1; | |
e244a443 | 815 | mutex_unlock(&dev->struct_mutex); |
d174bd64 DV |
816 | ret = shmem_pwrite_slow(page, shmem_page_offset, page_length, |
817 | user_data, page_do_bit17_swizzling, | |
818 | partial_cacheline_write, | |
819 | needs_clflush_after); | |
40123c1f | 820 | |
e244a443 | 821 | mutex_lock(&dev->struct_mutex); |
755d2218 | 822 | |
e244a443 | 823 | next_page: |
e5281ccd CW |
824 | set_page_dirty(page); |
825 | mark_page_accessed(page); | |
e5281ccd | 826 | |
755d2218 | 827 | if (ret) |
8c59967c | 828 | goto out; |
8c59967c | 829 | |
40123c1f | 830 | remain -= page_length; |
8c59967c | 831 | user_data += page_length; |
40123c1f | 832 | offset += page_length; |
673a394b EA |
833 | } |
834 | ||
fbd5a26d | 835 | out: |
755d2218 CW |
836 | i915_gem_object_unpin_pages(obj); |
837 | ||
e244a443 | 838 | if (hit_slowpath) { |
8dcf015e DV |
839 | /* |
840 | * Fixup: Flush cpu caches in case we didn't flush the dirty | |
841 | * cachelines in-line while writing and the object moved | |
842 | * out of the cpu write domain while we've dropped the lock. | |
843 | */ | |
844 | if (!needs_clflush_after && | |
845 | obj->base.write_domain != I915_GEM_DOMAIN_CPU) { | |
e244a443 | 846 | i915_gem_clflush_object(obj); |
e76e9aeb | 847 | i915_gem_chipset_flush(dev); |
e244a443 | 848 | } |
8c59967c | 849 | } |
673a394b | 850 | |
58642885 | 851 | if (needs_clflush_after) |
e76e9aeb | 852 | i915_gem_chipset_flush(dev); |
58642885 | 853 | |
40123c1f | 854 | return ret; |
673a394b EA |
855 | } |
856 | ||
857 | /** | |
858 | * Writes data to the object referenced by handle. | |
859 | * | |
860 | * On error, the contents of the buffer that were to be modified are undefined. | |
861 | */ | |
862 | int | |
863 | i915_gem_pwrite_ioctl(struct drm_device *dev, void *data, | |
fbd5a26d | 864 | struct drm_file *file) |
673a394b EA |
865 | { |
866 | struct drm_i915_gem_pwrite *args = data; | |
05394f39 | 867 | struct drm_i915_gem_object *obj; |
51311d0a CW |
868 | int ret; |
869 | ||
870 | if (args->size == 0) | |
871 | return 0; | |
872 | ||
873 | if (!access_ok(VERIFY_READ, | |
874 | (char __user *)(uintptr_t)args->data_ptr, | |
875 | args->size)) | |
876 | return -EFAULT; | |
877 | ||
f56f821f DV |
878 | ret = fault_in_multipages_readable((char __user *)(uintptr_t)args->data_ptr, |
879 | args->size); | |
51311d0a CW |
880 | if (ret) |
881 | return -EFAULT; | |
673a394b | 882 | |
fbd5a26d | 883 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 884 | if (ret) |
fbd5a26d | 885 | return ret; |
1d7cfea1 | 886 | |
05394f39 | 887 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 888 | if (&obj->base == NULL) { |
1d7cfea1 CW |
889 | ret = -ENOENT; |
890 | goto unlock; | |
fbd5a26d | 891 | } |
673a394b | 892 | |
7dcd2499 | 893 | /* Bounds check destination. */ |
05394f39 CW |
894 | if (args->offset > obj->base.size || |
895 | args->size > obj->base.size - args->offset) { | |
ce9d419d | 896 | ret = -EINVAL; |
35b62a89 | 897 | goto out; |
ce9d419d CW |
898 | } |
899 | ||
1286ff73 DV |
900 | /* prime objects have no backing filp to GEM pread/pwrite |
901 | * pages from. | |
902 | */ | |
903 | if (!obj->base.filp) { | |
904 | ret = -EINVAL; | |
905 | goto out; | |
906 | } | |
907 | ||
db53a302 CW |
908 | trace_i915_gem_object_pwrite(obj, args->offset, args->size); |
909 | ||
935aaa69 | 910 | ret = -EFAULT; |
673a394b EA |
911 | /* We can only do the GTT pwrite on untiled buffers, as otherwise |
912 | * it would end up going through the fenced access, and we'll get | |
913 | * different detiling behavior between reading and writing. | |
914 | * pread/pwrite currently are reading and writing from the CPU | |
915 | * perspective, requiring manual detiling by the client. | |
916 | */ | |
5c0480f2 | 917 | if (obj->phys_obj) { |
fbd5a26d | 918 | ret = i915_gem_phys_pwrite(dev, obj, args, file); |
5c0480f2 DV |
919 | goto out; |
920 | } | |
921 | ||
86a1ee26 | 922 | if (obj->cache_level == I915_CACHE_NONE && |
c07496fa | 923 | obj->tiling_mode == I915_TILING_NONE && |
5c0480f2 | 924 | obj->base.write_domain != I915_GEM_DOMAIN_CPU) { |
fbd5a26d | 925 | ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file); |
935aaa69 DV |
926 | /* Note that the gtt paths might fail with non-page-backed user |
927 | * pointers (e.g. gtt mappings when moving data between | |
928 | * textures). Fallback to the shmem path in that case. */ | |
fbd5a26d | 929 | } |
673a394b | 930 | |
86a1ee26 | 931 | if (ret == -EFAULT || ret == -ENOSPC) |
935aaa69 | 932 | ret = i915_gem_shmem_pwrite(dev, obj, args, file); |
5c0480f2 | 933 | |
35b62a89 | 934 | out: |
05394f39 | 935 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 936 | unlock: |
fbd5a26d | 937 | mutex_unlock(&dev->struct_mutex); |
673a394b EA |
938 | return ret; |
939 | } | |
940 | ||
b361237b | 941 | int |
33196ded | 942 | i915_gem_check_wedge(struct i915_gpu_error *error, |
b361237b CW |
943 | bool interruptible) |
944 | { | |
33196ded DV |
945 | if (atomic_read(&error->wedged)) { |
946 | struct completion *x = &error->completion; | |
b361237b CW |
947 | bool recovery_complete; |
948 | unsigned long flags; | |
949 | ||
950 | /* Give the error handler a chance to run. */ | |
951 | spin_lock_irqsave(&x->wait.lock, flags); | |
952 | recovery_complete = x->done > 0; | |
953 | spin_unlock_irqrestore(&x->wait.lock, flags); | |
954 | ||
955 | /* Non-interruptible callers can't handle -EAGAIN, hence return | |
956 | * -EIO unconditionally for these. */ | |
957 | if (!interruptible) | |
958 | return -EIO; | |
959 | ||
960 | /* Recovery complete, but still wedged means reset failure. */ | |
961 | if (recovery_complete) | |
962 | return -EIO; | |
963 | ||
964 | return -EAGAIN; | |
965 | } | |
966 | ||
967 | return 0; | |
968 | } | |
969 | ||
970 | /* | |
971 | * Compare seqno against outstanding lazy request. Emit a request if they are | |
972 | * equal. | |
973 | */ | |
974 | static int | |
975 | i915_gem_check_olr(struct intel_ring_buffer *ring, u32 seqno) | |
976 | { | |
977 | int ret; | |
978 | ||
979 | BUG_ON(!mutex_is_locked(&ring->dev->struct_mutex)); | |
980 | ||
981 | ret = 0; | |
982 | if (seqno == ring->outstanding_lazy_request) | |
983 | ret = i915_add_request(ring, NULL, NULL); | |
984 | ||
985 | return ret; | |
986 | } | |
987 | ||
988 | /** | |
989 | * __wait_seqno - wait until execution of seqno has finished | |
990 | * @ring: the ring expected to report seqno | |
991 | * @seqno: duh! | |
992 | * @interruptible: do an interruptible wait (normally yes) | |
993 | * @timeout: in - how long to wait (NULL forever); out - how much time remaining | |
994 | * | |
995 | * Returns 0 if the seqno was found within the alloted time. Else returns the | |
996 | * errno with remaining time filled in timeout argument. | |
997 | */ | |
998 | static int __wait_seqno(struct intel_ring_buffer *ring, u32 seqno, | |
999 | bool interruptible, struct timespec *timeout) | |
1000 | { | |
1001 | drm_i915_private_t *dev_priv = ring->dev->dev_private; | |
1002 | struct timespec before, now, wait_time={1,0}; | |
1003 | unsigned long timeout_jiffies; | |
1004 | long end; | |
1005 | bool wait_forever = true; | |
1006 | int ret; | |
1007 | ||
1008 | if (i915_seqno_passed(ring->get_seqno(ring, true), seqno)) | |
1009 | return 0; | |
1010 | ||
1011 | trace_i915_gem_request_wait_begin(ring, seqno); | |
1012 | ||
1013 | if (timeout != NULL) { | |
1014 | wait_time = *timeout; | |
1015 | wait_forever = false; | |
1016 | } | |
1017 | ||
1018 | timeout_jiffies = timespec_to_jiffies(&wait_time); | |
1019 | ||
1020 | if (WARN_ON(!ring->irq_get(ring))) | |
1021 | return -ENODEV; | |
1022 | ||
1023 | /* Record current time in case interrupted by signal, or wedged * */ | |
1024 | getrawmonotonic(&before); | |
1025 | ||
1026 | #define EXIT_COND \ | |
1027 | (i915_seqno_passed(ring->get_seqno(ring, false), seqno) || \ | |
33196ded | 1028 | atomic_read(&dev_priv->gpu_error.wedged)) |
b361237b CW |
1029 | do { |
1030 | if (interruptible) | |
1031 | end = wait_event_interruptible_timeout(ring->irq_queue, | |
1032 | EXIT_COND, | |
1033 | timeout_jiffies); | |
1034 | else | |
1035 | end = wait_event_timeout(ring->irq_queue, EXIT_COND, | |
1036 | timeout_jiffies); | |
1037 | ||
33196ded | 1038 | ret = i915_gem_check_wedge(&dev_priv->gpu_error, interruptible); |
b361237b CW |
1039 | if (ret) |
1040 | end = ret; | |
1041 | } while (end == 0 && wait_forever); | |
1042 | ||
1043 | getrawmonotonic(&now); | |
1044 | ||
1045 | ring->irq_put(ring); | |
1046 | trace_i915_gem_request_wait_end(ring, seqno); | |
1047 | #undef EXIT_COND | |
1048 | ||
1049 | if (timeout) { | |
1050 | struct timespec sleep_time = timespec_sub(now, before); | |
1051 | *timeout = timespec_sub(*timeout, sleep_time); | |
1052 | } | |
1053 | ||
1054 | switch (end) { | |
1055 | case -EIO: | |
1056 | case -EAGAIN: /* Wedged */ | |
1057 | case -ERESTARTSYS: /* Signal */ | |
1058 | return (int)end; | |
1059 | case 0: /* Timeout */ | |
1060 | if (timeout) | |
1061 | set_normalized_timespec(timeout, 0, 0); | |
1062 | return -ETIME; | |
1063 | default: /* Completed */ | |
1064 | WARN_ON(end < 0); /* We're not aware of other errors */ | |
1065 | return 0; | |
1066 | } | |
1067 | } | |
1068 | ||
1069 | /** | |
1070 | * Waits for a sequence number to be signaled, and cleans up the | |
1071 | * request and object lists appropriately for that event. | |
1072 | */ | |
1073 | int | |
1074 | i915_wait_seqno(struct intel_ring_buffer *ring, uint32_t seqno) | |
1075 | { | |
1076 | struct drm_device *dev = ring->dev; | |
1077 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1078 | bool interruptible = dev_priv->mm.interruptible; | |
1079 | int ret; | |
1080 | ||
1081 | BUG_ON(!mutex_is_locked(&dev->struct_mutex)); | |
1082 | BUG_ON(seqno == 0); | |
1083 | ||
33196ded | 1084 | ret = i915_gem_check_wedge(&dev_priv->gpu_error, interruptible); |
b361237b CW |
1085 | if (ret) |
1086 | return ret; | |
1087 | ||
1088 | ret = i915_gem_check_olr(ring, seqno); | |
1089 | if (ret) | |
1090 | return ret; | |
1091 | ||
1092 | return __wait_seqno(ring, seqno, interruptible, NULL); | |
1093 | } | |
1094 | ||
1095 | /** | |
1096 | * Ensures that all rendering to the object has completed and the object is | |
1097 | * safe to unbind from the GTT or access from the CPU. | |
1098 | */ | |
1099 | static __must_check int | |
1100 | i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj, | |
1101 | bool readonly) | |
1102 | { | |
1103 | struct intel_ring_buffer *ring = obj->ring; | |
1104 | u32 seqno; | |
1105 | int ret; | |
1106 | ||
1107 | seqno = readonly ? obj->last_write_seqno : obj->last_read_seqno; | |
1108 | if (seqno == 0) | |
1109 | return 0; | |
1110 | ||
1111 | ret = i915_wait_seqno(ring, seqno); | |
1112 | if (ret) | |
1113 | return ret; | |
1114 | ||
1115 | i915_gem_retire_requests_ring(ring); | |
1116 | ||
1117 | /* Manually manage the write flush as we may have not yet | |
1118 | * retired the buffer. | |
1119 | */ | |
1120 | if (obj->last_write_seqno && | |
1121 | i915_seqno_passed(seqno, obj->last_write_seqno)) { | |
1122 | obj->last_write_seqno = 0; | |
1123 | obj->base.write_domain &= ~I915_GEM_GPU_DOMAINS; | |
1124 | } | |
1125 | ||
1126 | return 0; | |
1127 | } | |
1128 | ||
3236f57a CW |
1129 | /* A nonblocking variant of the above wait. This is a highly dangerous routine |
1130 | * as the object state may change during this call. | |
1131 | */ | |
1132 | static __must_check int | |
1133 | i915_gem_object_wait_rendering__nonblocking(struct drm_i915_gem_object *obj, | |
1134 | bool readonly) | |
1135 | { | |
1136 | struct drm_device *dev = obj->base.dev; | |
1137 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1138 | struct intel_ring_buffer *ring = obj->ring; | |
1139 | u32 seqno; | |
1140 | int ret; | |
1141 | ||
1142 | BUG_ON(!mutex_is_locked(&dev->struct_mutex)); | |
1143 | BUG_ON(!dev_priv->mm.interruptible); | |
1144 | ||
1145 | seqno = readonly ? obj->last_write_seqno : obj->last_read_seqno; | |
1146 | if (seqno == 0) | |
1147 | return 0; | |
1148 | ||
33196ded | 1149 | ret = i915_gem_check_wedge(&dev_priv->gpu_error, true); |
3236f57a CW |
1150 | if (ret) |
1151 | return ret; | |
1152 | ||
1153 | ret = i915_gem_check_olr(ring, seqno); | |
1154 | if (ret) | |
1155 | return ret; | |
1156 | ||
1157 | mutex_unlock(&dev->struct_mutex); | |
1158 | ret = __wait_seqno(ring, seqno, true, NULL); | |
1159 | mutex_lock(&dev->struct_mutex); | |
1160 | ||
1161 | i915_gem_retire_requests_ring(ring); | |
1162 | ||
1163 | /* Manually manage the write flush as we may have not yet | |
1164 | * retired the buffer. | |
1165 | */ | |
1166 | if (obj->last_write_seqno && | |
1167 | i915_seqno_passed(seqno, obj->last_write_seqno)) { | |
1168 | obj->last_write_seqno = 0; | |
1169 | obj->base.write_domain &= ~I915_GEM_GPU_DOMAINS; | |
1170 | } | |
1171 | ||
1172 | return ret; | |
1173 | } | |
1174 | ||
673a394b | 1175 | /** |
2ef7eeaa EA |
1176 | * Called when user space prepares to use an object with the CPU, either |
1177 | * through the mmap ioctl's mapping or a GTT mapping. | |
673a394b EA |
1178 | */ |
1179 | int | |
1180 | i915_gem_set_domain_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 1181 | struct drm_file *file) |
673a394b EA |
1182 | { |
1183 | struct drm_i915_gem_set_domain *args = data; | |
05394f39 | 1184 | struct drm_i915_gem_object *obj; |
2ef7eeaa EA |
1185 | uint32_t read_domains = args->read_domains; |
1186 | uint32_t write_domain = args->write_domain; | |
673a394b EA |
1187 | int ret; |
1188 | ||
2ef7eeaa | 1189 | /* Only handle setting domains to types used by the CPU. */ |
21d509e3 | 1190 | if (write_domain & I915_GEM_GPU_DOMAINS) |
2ef7eeaa EA |
1191 | return -EINVAL; |
1192 | ||
21d509e3 | 1193 | if (read_domains & I915_GEM_GPU_DOMAINS) |
2ef7eeaa EA |
1194 | return -EINVAL; |
1195 | ||
1196 | /* Having something in the write domain implies it's in the read | |
1197 | * domain, and only that read domain. Enforce that in the request. | |
1198 | */ | |
1199 | if (write_domain != 0 && read_domains != write_domain) | |
1200 | return -EINVAL; | |
1201 | ||
76c1dec1 | 1202 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 1203 | if (ret) |
76c1dec1 | 1204 | return ret; |
1d7cfea1 | 1205 | |
05394f39 | 1206 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 1207 | if (&obj->base == NULL) { |
1d7cfea1 CW |
1208 | ret = -ENOENT; |
1209 | goto unlock; | |
76c1dec1 | 1210 | } |
673a394b | 1211 | |
3236f57a CW |
1212 | /* Try to flush the object off the GPU without holding the lock. |
1213 | * We will repeat the flush holding the lock in the normal manner | |
1214 | * to catch cases where we are gazumped. | |
1215 | */ | |
1216 | ret = i915_gem_object_wait_rendering__nonblocking(obj, !write_domain); | |
1217 | if (ret) | |
1218 | goto unref; | |
1219 | ||
2ef7eeaa EA |
1220 | if (read_domains & I915_GEM_DOMAIN_GTT) { |
1221 | ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0); | |
02354392 EA |
1222 | |
1223 | /* Silently promote "you're not bound, there was nothing to do" | |
1224 | * to success, since the client was just asking us to | |
1225 | * make sure everything was done. | |
1226 | */ | |
1227 | if (ret == -EINVAL) | |
1228 | ret = 0; | |
2ef7eeaa | 1229 | } else { |
e47c68e9 | 1230 | ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0); |
2ef7eeaa EA |
1231 | } |
1232 | ||
3236f57a | 1233 | unref: |
05394f39 | 1234 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 1235 | unlock: |
673a394b EA |
1236 | mutex_unlock(&dev->struct_mutex); |
1237 | return ret; | |
1238 | } | |
1239 | ||
1240 | /** | |
1241 | * Called when user space has done writes to this buffer | |
1242 | */ | |
1243 | int | |
1244 | i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 1245 | struct drm_file *file) |
673a394b EA |
1246 | { |
1247 | struct drm_i915_gem_sw_finish *args = data; | |
05394f39 | 1248 | struct drm_i915_gem_object *obj; |
673a394b EA |
1249 | int ret = 0; |
1250 | ||
76c1dec1 | 1251 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 1252 | if (ret) |
76c1dec1 | 1253 | return ret; |
1d7cfea1 | 1254 | |
05394f39 | 1255 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 1256 | if (&obj->base == NULL) { |
1d7cfea1 CW |
1257 | ret = -ENOENT; |
1258 | goto unlock; | |
673a394b EA |
1259 | } |
1260 | ||
673a394b | 1261 | /* Pinned buffers may be scanout, so flush the cache */ |
05394f39 | 1262 | if (obj->pin_count) |
e47c68e9 EA |
1263 | i915_gem_object_flush_cpu_write_domain(obj); |
1264 | ||
05394f39 | 1265 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 1266 | unlock: |
673a394b EA |
1267 | mutex_unlock(&dev->struct_mutex); |
1268 | return ret; | |
1269 | } | |
1270 | ||
1271 | /** | |
1272 | * Maps the contents of an object, returning the address it is mapped | |
1273 | * into. | |
1274 | * | |
1275 | * While the mapping holds a reference on the contents of the object, it doesn't | |
1276 | * imply a ref on the object itself. | |
1277 | */ | |
1278 | int | |
1279 | i915_gem_mmap_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 1280 | struct drm_file *file) |
673a394b EA |
1281 | { |
1282 | struct drm_i915_gem_mmap *args = data; | |
1283 | struct drm_gem_object *obj; | |
673a394b EA |
1284 | unsigned long addr; |
1285 | ||
05394f39 | 1286 | obj = drm_gem_object_lookup(dev, file, args->handle); |
673a394b | 1287 | if (obj == NULL) |
bf79cb91 | 1288 | return -ENOENT; |
673a394b | 1289 | |
1286ff73 DV |
1290 | /* prime objects have no backing filp to GEM mmap |
1291 | * pages from. | |
1292 | */ | |
1293 | if (!obj->filp) { | |
1294 | drm_gem_object_unreference_unlocked(obj); | |
1295 | return -EINVAL; | |
1296 | } | |
1297 | ||
6be5ceb0 | 1298 | addr = vm_mmap(obj->filp, 0, args->size, |
673a394b EA |
1299 | PROT_READ | PROT_WRITE, MAP_SHARED, |
1300 | args->offset); | |
bc9025bd | 1301 | drm_gem_object_unreference_unlocked(obj); |
673a394b EA |
1302 | if (IS_ERR((void *)addr)) |
1303 | return addr; | |
1304 | ||
1305 | args->addr_ptr = (uint64_t) addr; | |
1306 | ||
1307 | return 0; | |
1308 | } | |
1309 | ||
de151cf6 JB |
1310 | /** |
1311 | * i915_gem_fault - fault a page into the GTT | |
1312 | * vma: VMA in question | |
1313 | * vmf: fault info | |
1314 | * | |
1315 | * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped | |
1316 | * from userspace. The fault handler takes care of binding the object to | |
1317 | * the GTT (if needed), allocating and programming a fence register (again, | |
1318 | * only if needed based on whether the old reg is still valid or the object | |
1319 | * is tiled) and inserting a new PTE into the faulting process. | |
1320 | * | |
1321 | * Note that the faulting process may involve evicting existing objects | |
1322 | * from the GTT and/or fence registers to make room. So performance may | |
1323 | * suffer if the GTT working set is large or there are few fence registers | |
1324 | * left. | |
1325 | */ | |
1326 | int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf) | |
1327 | { | |
05394f39 CW |
1328 | struct drm_i915_gem_object *obj = to_intel_bo(vma->vm_private_data); |
1329 | struct drm_device *dev = obj->base.dev; | |
7d1c4804 | 1330 | drm_i915_private_t *dev_priv = dev->dev_private; |
de151cf6 JB |
1331 | pgoff_t page_offset; |
1332 | unsigned long pfn; | |
1333 | int ret = 0; | |
0f973f27 | 1334 | bool write = !!(vmf->flags & FAULT_FLAG_WRITE); |
de151cf6 JB |
1335 | |
1336 | /* We don't use vmf->pgoff since that has the fake offset */ | |
1337 | page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >> | |
1338 | PAGE_SHIFT; | |
1339 | ||
d9bc7e9f CW |
1340 | ret = i915_mutex_lock_interruptible(dev); |
1341 | if (ret) | |
1342 | goto out; | |
a00b10c3 | 1343 | |
db53a302 CW |
1344 | trace_i915_gem_object_fault(obj, page_offset, true, write); |
1345 | ||
eb119bd6 CW |
1346 | /* Access to snoopable pages through the GTT is incoherent. */ |
1347 | if (obj->cache_level != I915_CACHE_NONE && !HAS_LLC(dev)) { | |
1348 | ret = -EINVAL; | |
1349 | goto unlock; | |
1350 | } | |
1351 | ||
d9bc7e9f | 1352 | /* Now bind it into the GTT if needed */ |
c9839303 CW |
1353 | ret = i915_gem_object_pin(obj, 0, true, false); |
1354 | if (ret) | |
1355 | goto unlock; | |
4a684a41 | 1356 | |
c9839303 CW |
1357 | ret = i915_gem_object_set_to_gtt_domain(obj, write); |
1358 | if (ret) | |
1359 | goto unpin; | |
74898d7e | 1360 | |
06d98131 | 1361 | ret = i915_gem_object_get_fence(obj); |
d9e86c0e | 1362 | if (ret) |
c9839303 | 1363 | goto unpin; |
7d1c4804 | 1364 | |
6299f992 CW |
1365 | obj->fault_mappable = true; |
1366 | ||
5d4545ae | 1367 | pfn = ((dev_priv->gtt.mappable_base + obj->gtt_offset) >> PAGE_SHIFT) + |
de151cf6 JB |
1368 | page_offset; |
1369 | ||
1370 | /* Finally, remap it using the new GTT offset */ | |
1371 | ret = vm_insert_pfn(vma, (unsigned long)vmf->virtual_address, pfn); | |
c9839303 CW |
1372 | unpin: |
1373 | i915_gem_object_unpin(obj); | |
c715089f | 1374 | unlock: |
de151cf6 | 1375 | mutex_unlock(&dev->struct_mutex); |
d9bc7e9f | 1376 | out: |
de151cf6 | 1377 | switch (ret) { |
d9bc7e9f | 1378 | case -EIO: |
a9340cca DV |
1379 | /* If this -EIO is due to a gpu hang, give the reset code a |
1380 | * chance to clean up the mess. Otherwise return the proper | |
1381 | * SIGBUS. */ | |
33196ded | 1382 | if (!atomic_read(&dev_priv->gpu_error.wedged)) |
a9340cca | 1383 | return VM_FAULT_SIGBUS; |
045e769a | 1384 | case -EAGAIN: |
d9bc7e9f CW |
1385 | /* Give the error handler a chance to run and move the |
1386 | * objects off the GPU active list. Next time we service the | |
1387 | * fault, we should be able to transition the page into the | |
1388 | * GTT without touching the GPU (and so avoid further | |
1389 | * EIO/EGAIN). If the GPU is wedged, then there is no issue | |
1390 | * with coherency, just lost writes. | |
1391 | */ | |
045e769a | 1392 | set_need_resched(); |
c715089f CW |
1393 | case 0: |
1394 | case -ERESTARTSYS: | |
bed636ab | 1395 | case -EINTR: |
e79e0fe3 DR |
1396 | case -EBUSY: |
1397 | /* | |
1398 | * EBUSY is ok: this just means that another thread | |
1399 | * already did the job. | |
1400 | */ | |
c715089f | 1401 | return VM_FAULT_NOPAGE; |
de151cf6 | 1402 | case -ENOMEM: |
de151cf6 | 1403 | return VM_FAULT_OOM; |
a7c2e1aa DV |
1404 | case -ENOSPC: |
1405 | return VM_FAULT_SIGBUS; | |
de151cf6 | 1406 | default: |
a7c2e1aa | 1407 | WARN_ONCE(ret, "unhandled error in i915_gem_fault: %i\n", ret); |
c715089f | 1408 | return VM_FAULT_SIGBUS; |
de151cf6 JB |
1409 | } |
1410 | } | |
1411 | ||
901782b2 CW |
1412 | /** |
1413 | * i915_gem_release_mmap - remove physical page mappings | |
1414 | * @obj: obj in question | |
1415 | * | |
af901ca1 | 1416 | * Preserve the reservation of the mmapping with the DRM core code, but |
901782b2 CW |
1417 | * relinquish ownership of the pages back to the system. |
1418 | * | |
1419 | * It is vital that we remove the page mapping if we have mapped a tiled | |
1420 | * object through the GTT and then lose the fence register due to | |
1421 | * resource pressure. Similarly if the object has been moved out of the | |
1422 | * aperture, than pages mapped into userspace must be revoked. Removing the | |
1423 | * mapping will then trigger a page fault on the next user access, allowing | |
1424 | * fixup by i915_gem_fault(). | |
1425 | */ | |
d05ca301 | 1426 | void |
05394f39 | 1427 | i915_gem_release_mmap(struct drm_i915_gem_object *obj) |
901782b2 | 1428 | { |
6299f992 CW |
1429 | if (!obj->fault_mappable) |
1430 | return; | |
901782b2 | 1431 | |
f6e47884 CW |
1432 | if (obj->base.dev->dev_mapping) |
1433 | unmap_mapping_range(obj->base.dev->dev_mapping, | |
1434 | (loff_t)obj->base.map_list.hash.key<<PAGE_SHIFT, | |
1435 | obj->base.size, 1); | |
fb7d516a | 1436 | |
6299f992 | 1437 | obj->fault_mappable = false; |
901782b2 CW |
1438 | } |
1439 | ||
0fa87796 | 1440 | uint32_t |
e28f8711 | 1441 | i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode) |
92b88aeb | 1442 | { |
e28f8711 | 1443 | uint32_t gtt_size; |
92b88aeb CW |
1444 | |
1445 | if (INTEL_INFO(dev)->gen >= 4 || | |
e28f8711 CW |
1446 | tiling_mode == I915_TILING_NONE) |
1447 | return size; | |
92b88aeb CW |
1448 | |
1449 | /* Previous chips need a power-of-two fence region when tiling */ | |
1450 | if (INTEL_INFO(dev)->gen == 3) | |
e28f8711 | 1451 | gtt_size = 1024*1024; |
92b88aeb | 1452 | else |
e28f8711 | 1453 | gtt_size = 512*1024; |
92b88aeb | 1454 | |
e28f8711 CW |
1455 | while (gtt_size < size) |
1456 | gtt_size <<= 1; | |
92b88aeb | 1457 | |
e28f8711 | 1458 | return gtt_size; |
92b88aeb CW |
1459 | } |
1460 | ||
de151cf6 JB |
1461 | /** |
1462 | * i915_gem_get_gtt_alignment - return required GTT alignment for an object | |
1463 | * @obj: object to check | |
1464 | * | |
1465 | * Return the required GTT alignment for an object, taking into account | |
5e783301 | 1466 | * potential fence register mapping. |
de151cf6 | 1467 | */ |
d865110c ID |
1468 | uint32_t |
1469 | i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size, | |
1470 | int tiling_mode, bool fenced) | |
de151cf6 | 1471 | { |
de151cf6 JB |
1472 | /* |
1473 | * Minimum alignment is 4k (GTT page size), but might be greater | |
1474 | * if a fence register is needed for the object. | |
1475 | */ | |
d865110c | 1476 | if (INTEL_INFO(dev)->gen >= 4 || (!fenced && IS_G33(dev)) || |
e28f8711 | 1477 | tiling_mode == I915_TILING_NONE) |
de151cf6 JB |
1478 | return 4096; |
1479 | ||
a00b10c3 CW |
1480 | /* |
1481 | * Previous chips need to be aligned to the size of the smallest | |
1482 | * fence register that can contain the object. | |
1483 | */ | |
e28f8711 | 1484 | return i915_gem_get_gtt_size(dev, size, tiling_mode); |
a00b10c3 CW |
1485 | } |
1486 | ||
d8cb5086 CW |
1487 | static int i915_gem_object_create_mmap_offset(struct drm_i915_gem_object *obj) |
1488 | { | |
1489 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; | |
1490 | int ret; | |
1491 | ||
1492 | if (obj->base.map_list.map) | |
1493 | return 0; | |
1494 | ||
da494d7c DV |
1495 | dev_priv->mm.shrinker_no_lock_stealing = true; |
1496 | ||
d8cb5086 CW |
1497 | ret = drm_gem_create_mmap_offset(&obj->base); |
1498 | if (ret != -ENOSPC) | |
da494d7c | 1499 | goto out; |
d8cb5086 CW |
1500 | |
1501 | /* Badly fragmented mmap space? The only way we can recover | |
1502 | * space is by destroying unwanted objects. We can't randomly release | |
1503 | * mmap_offsets as userspace expects them to be persistent for the | |
1504 | * lifetime of the objects. The closest we can is to release the | |
1505 | * offsets on purgeable objects by truncating it and marking it purged, | |
1506 | * which prevents userspace from ever using that object again. | |
1507 | */ | |
1508 | i915_gem_purge(dev_priv, obj->base.size >> PAGE_SHIFT); | |
1509 | ret = drm_gem_create_mmap_offset(&obj->base); | |
1510 | if (ret != -ENOSPC) | |
da494d7c | 1511 | goto out; |
d8cb5086 CW |
1512 | |
1513 | i915_gem_shrink_all(dev_priv); | |
da494d7c DV |
1514 | ret = drm_gem_create_mmap_offset(&obj->base); |
1515 | out: | |
1516 | dev_priv->mm.shrinker_no_lock_stealing = false; | |
1517 | ||
1518 | return ret; | |
d8cb5086 CW |
1519 | } |
1520 | ||
1521 | static void i915_gem_object_free_mmap_offset(struct drm_i915_gem_object *obj) | |
1522 | { | |
1523 | if (!obj->base.map_list.map) | |
1524 | return; | |
1525 | ||
1526 | drm_gem_free_mmap_offset(&obj->base); | |
1527 | } | |
1528 | ||
de151cf6 | 1529 | int |
ff72145b DA |
1530 | i915_gem_mmap_gtt(struct drm_file *file, |
1531 | struct drm_device *dev, | |
1532 | uint32_t handle, | |
1533 | uint64_t *offset) | |
de151cf6 | 1534 | { |
da761a6e | 1535 | struct drm_i915_private *dev_priv = dev->dev_private; |
05394f39 | 1536 | struct drm_i915_gem_object *obj; |
de151cf6 JB |
1537 | int ret; |
1538 | ||
76c1dec1 | 1539 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 1540 | if (ret) |
76c1dec1 | 1541 | return ret; |
de151cf6 | 1542 | |
ff72145b | 1543 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle)); |
c8725226 | 1544 | if (&obj->base == NULL) { |
1d7cfea1 CW |
1545 | ret = -ENOENT; |
1546 | goto unlock; | |
1547 | } | |
de151cf6 | 1548 | |
5d4545ae | 1549 | if (obj->base.size > dev_priv->gtt.mappable_end) { |
da761a6e | 1550 | ret = -E2BIG; |
ff56b0bc | 1551 | goto out; |
da761a6e CW |
1552 | } |
1553 | ||
05394f39 | 1554 | if (obj->madv != I915_MADV_WILLNEED) { |
ab18282d | 1555 | DRM_ERROR("Attempting to mmap a purgeable buffer\n"); |
1d7cfea1 CW |
1556 | ret = -EINVAL; |
1557 | goto out; | |
ab18282d CW |
1558 | } |
1559 | ||
d8cb5086 CW |
1560 | ret = i915_gem_object_create_mmap_offset(obj); |
1561 | if (ret) | |
1562 | goto out; | |
de151cf6 | 1563 | |
ff72145b | 1564 | *offset = (u64)obj->base.map_list.hash.key << PAGE_SHIFT; |
de151cf6 | 1565 | |
1d7cfea1 | 1566 | out: |
05394f39 | 1567 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 1568 | unlock: |
de151cf6 | 1569 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 1570 | return ret; |
de151cf6 JB |
1571 | } |
1572 | ||
ff72145b DA |
1573 | /** |
1574 | * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing | |
1575 | * @dev: DRM device | |
1576 | * @data: GTT mapping ioctl data | |
1577 | * @file: GEM object info | |
1578 | * | |
1579 | * Simply returns the fake offset to userspace so it can mmap it. | |
1580 | * The mmap call will end up in drm_gem_mmap(), which will set things | |
1581 | * up so we can get faults in the handler above. | |
1582 | * | |
1583 | * The fault handler will take care of binding the object into the GTT | |
1584 | * (since it may have been evicted to make room for something), allocating | |
1585 | * a fence register, and mapping the appropriate aperture address into | |
1586 | * userspace. | |
1587 | */ | |
1588 | int | |
1589 | i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data, | |
1590 | struct drm_file *file) | |
1591 | { | |
1592 | struct drm_i915_gem_mmap_gtt *args = data; | |
1593 | ||
ff72145b DA |
1594 | return i915_gem_mmap_gtt(file, dev, args->handle, &args->offset); |
1595 | } | |
1596 | ||
225067ee DV |
1597 | /* Immediately discard the backing storage */ |
1598 | static void | |
1599 | i915_gem_object_truncate(struct drm_i915_gem_object *obj) | |
e5281ccd | 1600 | { |
e5281ccd | 1601 | struct inode *inode; |
e5281ccd | 1602 | |
4d6294bf | 1603 | i915_gem_object_free_mmap_offset(obj); |
1286ff73 | 1604 | |
4d6294bf CW |
1605 | if (obj->base.filp == NULL) |
1606 | return; | |
e5281ccd | 1607 | |
225067ee DV |
1608 | /* Our goal here is to return as much of the memory as |
1609 | * is possible back to the system as we are called from OOM. | |
1610 | * To do this we must instruct the shmfs to drop all of its | |
1611 | * backing pages, *now*. | |
1612 | */ | |
05394f39 | 1613 | inode = obj->base.filp->f_path.dentry->d_inode; |
225067ee | 1614 | shmem_truncate_range(inode, 0, (loff_t)-1); |
e5281ccd | 1615 | |
225067ee DV |
1616 | obj->madv = __I915_MADV_PURGED; |
1617 | } | |
e5281ccd | 1618 | |
225067ee DV |
1619 | static inline int |
1620 | i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj) | |
1621 | { | |
1622 | return obj->madv == I915_MADV_DONTNEED; | |
e5281ccd CW |
1623 | } |
1624 | ||
5cdf5881 | 1625 | static void |
05394f39 | 1626 | i915_gem_object_put_pages_gtt(struct drm_i915_gem_object *obj) |
673a394b | 1627 | { |
05394f39 | 1628 | int page_count = obj->base.size / PAGE_SIZE; |
9da3da66 | 1629 | struct scatterlist *sg; |
6c085a72 | 1630 | int ret, i; |
1286ff73 | 1631 | |
05394f39 | 1632 | BUG_ON(obj->madv == __I915_MADV_PURGED); |
673a394b | 1633 | |
6c085a72 CW |
1634 | ret = i915_gem_object_set_to_cpu_domain(obj, true); |
1635 | if (ret) { | |
1636 | /* In the event of a disaster, abandon all caches and | |
1637 | * hope for the best. | |
1638 | */ | |
1639 | WARN_ON(ret != -EIO); | |
1640 | i915_gem_clflush_object(obj); | |
1641 | obj->base.read_domains = obj->base.write_domain = I915_GEM_DOMAIN_CPU; | |
1642 | } | |
1643 | ||
6dacfd2f | 1644 | if (i915_gem_object_needs_bit17_swizzle(obj)) |
280b713b EA |
1645 | i915_gem_object_save_bit_17_swizzle(obj); |
1646 | ||
05394f39 CW |
1647 | if (obj->madv == I915_MADV_DONTNEED) |
1648 | obj->dirty = 0; | |
3ef94daa | 1649 | |
9da3da66 CW |
1650 | for_each_sg(obj->pages->sgl, sg, page_count, i) { |
1651 | struct page *page = sg_page(sg); | |
1652 | ||
05394f39 | 1653 | if (obj->dirty) |
9da3da66 | 1654 | set_page_dirty(page); |
3ef94daa | 1655 | |
05394f39 | 1656 | if (obj->madv == I915_MADV_WILLNEED) |
9da3da66 | 1657 | mark_page_accessed(page); |
3ef94daa | 1658 | |
9da3da66 | 1659 | page_cache_release(page); |
3ef94daa | 1660 | } |
05394f39 | 1661 | obj->dirty = 0; |
673a394b | 1662 | |
9da3da66 CW |
1663 | sg_free_table(obj->pages); |
1664 | kfree(obj->pages); | |
37e680a1 | 1665 | } |
6c085a72 | 1666 | |
dd624afd | 1667 | int |
37e680a1 CW |
1668 | i915_gem_object_put_pages(struct drm_i915_gem_object *obj) |
1669 | { | |
1670 | const struct drm_i915_gem_object_ops *ops = obj->ops; | |
1671 | ||
2f745ad3 | 1672 | if (obj->pages == NULL) |
37e680a1 CW |
1673 | return 0; |
1674 | ||
1675 | BUG_ON(obj->gtt_space); | |
6c085a72 | 1676 | |
a5570178 CW |
1677 | if (obj->pages_pin_count) |
1678 | return -EBUSY; | |
1679 | ||
a2165e31 CW |
1680 | /* ->put_pages might need to allocate memory for the bit17 swizzle |
1681 | * array, hence protect them from being reaped by removing them from gtt | |
1682 | * lists early. */ | |
1683 | list_del(&obj->gtt_list); | |
1684 | ||
37e680a1 | 1685 | ops->put_pages(obj); |
05394f39 | 1686 | obj->pages = NULL; |
37e680a1 | 1687 | |
6c085a72 CW |
1688 | if (i915_gem_object_is_purgeable(obj)) |
1689 | i915_gem_object_truncate(obj); | |
1690 | ||
1691 | return 0; | |
1692 | } | |
1693 | ||
1694 | static long | |
1695 | i915_gem_purge(struct drm_i915_private *dev_priv, long target) | |
1696 | { | |
1697 | struct drm_i915_gem_object *obj, *next; | |
1698 | long count = 0; | |
1699 | ||
1700 | list_for_each_entry_safe(obj, next, | |
1701 | &dev_priv->mm.unbound_list, | |
1702 | gtt_list) { | |
1703 | if (i915_gem_object_is_purgeable(obj) && | |
37e680a1 | 1704 | i915_gem_object_put_pages(obj) == 0) { |
6c085a72 CW |
1705 | count += obj->base.size >> PAGE_SHIFT; |
1706 | if (count >= target) | |
1707 | return count; | |
1708 | } | |
1709 | } | |
1710 | ||
1711 | list_for_each_entry_safe(obj, next, | |
1712 | &dev_priv->mm.inactive_list, | |
1713 | mm_list) { | |
1714 | if (i915_gem_object_is_purgeable(obj) && | |
1715 | i915_gem_object_unbind(obj) == 0 && | |
37e680a1 | 1716 | i915_gem_object_put_pages(obj) == 0) { |
6c085a72 CW |
1717 | count += obj->base.size >> PAGE_SHIFT; |
1718 | if (count >= target) | |
1719 | return count; | |
1720 | } | |
1721 | } | |
1722 | ||
1723 | return count; | |
1724 | } | |
1725 | ||
1726 | static void | |
1727 | i915_gem_shrink_all(struct drm_i915_private *dev_priv) | |
1728 | { | |
1729 | struct drm_i915_gem_object *obj, *next; | |
1730 | ||
1731 | i915_gem_evict_everything(dev_priv->dev); | |
1732 | ||
1733 | list_for_each_entry_safe(obj, next, &dev_priv->mm.unbound_list, gtt_list) | |
37e680a1 | 1734 | i915_gem_object_put_pages(obj); |
225067ee DV |
1735 | } |
1736 | ||
37e680a1 | 1737 | static int |
6c085a72 | 1738 | i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj) |
e5281ccd | 1739 | { |
6c085a72 | 1740 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
e5281ccd CW |
1741 | int page_count, i; |
1742 | struct address_space *mapping; | |
9da3da66 CW |
1743 | struct sg_table *st; |
1744 | struct scatterlist *sg; | |
e5281ccd | 1745 | struct page *page; |
6c085a72 | 1746 | gfp_t gfp; |
e5281ccd | 1747 | |
6c085a72 CW |
1748 | /* Assert that the object is not currently in any GPU domain. As it |
1749 | * wasn't in the GTT, there shouldn't be any way it could have been in | |
1750 | * a GPU cache | |
1751 | */ | |
1752 | BUG_ON(obj->base.read_domains & I915_GEM_GPU_DOMAINS); | |
1753 | BUG_ON(obj->base.write_domain & I915_GEM_GPU_DOMAINS); | |
1754 | ||
9da3da66 CW |
1755 | st = kmalloc(sizeof(*st), GFP_KERNEL); |
1756 | if (st == NULL) | |
1757 | return -ENOMEM; | |
1758 | ||
05394f39 | 1759 | page_count = obj->base.size / PAGE_SIZE; |
9da3da66 CW |
1760 | if (sg_alloc_table(st, page_count, GFP_KERNEL)) { |
1761 | sg_free_table(st); | |
1762 | kfree(st); | |
e5281ccd | 1763 | return -ENOMEM; |
9da3da66 | 1764 | } |
e5281ccd | 1765 | |
9da3da66 CW |
1766 | /* Get the list of pages out of our struct file. They'll be pinned |
1767 | * at this point until we release them. | |
1768 | * | |
1769 | * Fail silently without starting the shrinker | |
1770 | */ | |
6c085a72 CW |
1771 | mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping; |
1772 | gfp = mapping_gfp_mask(mapping); | |
caf49191 | 1773 | gfp |= __GFP_NORETRY | __GFP_NOWARN | __GFP_NO_KSWAPD; |
6c085a72 | 1774 | gfp &= ~(__GFP_IO | __GFP_WAIT); |
9da3da66 | 1775 | for_each_sg(st->sgl, sg, page_count, i) { |
6c085a72 CW |
1776 | page = shmem_read_mapping_page_gfp(mapping, i, gfp); |
1777 | if (IS_ERR(page)) { | |
1778 | i915_gem_purge(dev_priv, page_count); | |
1779 | page = shmem_read_mapping_page_gfp(mapping, i, gfp); | |
1780 | } | |
1781 | if (IS_ERR(page)) { | |
1782 | /* We've tried hard to allocate the memory by reaping | |
1783 | * our own buffer, now let the real VM do its job and | |
1784 | * go down in flames if truly OOM. | |
1785 | */ | |
caf49191 | 1786 | gfp &= ~(__GFP_NORETRY | __GFP_NOWARN | __GFP_NO_KSWAPD); |
6c085a72 CW |
1787 | gfp |= __GFP_IO | __GFP_WAIT; |
1788 | ||
1789 | i915_gem_shrink_all(dev_priv); | |
1790 | page = shmem_read_mapping_page_gfp(mapping, i, gfp); | |
1791 | if (IS_ERR(page)) | |
1792 | goto err_pages; | |
1793 | ||
caf49191 | 1794 | gfp |= __GFP_NORETRY | __GFP_NOWARN | __GFP_NO_KSWAPD; |
6c085a72 CW |
1795 | gfp &= ~(__GFP_IO | __GFP_WAIT); |
1796 | } | |
e5281ccd | 1797 | |
9da3da66 | 1798 | sg_set_page(sg, page, PAGE_SIZE, 0); |
e5281ccd CW |
1799 | } |
1800 | ||
74ce6b6c CW |
1801 | obj->pages = st; |
1802 | ||
6dacfd2f | 1803 | if (i915_gem_object_needs_bit17_swizzle(obj)) |
e5281ccd CW |
1804 | i915_gem_object_do_bit_17_swizzle(obj); |
1805 | ||
1806 | return 0; | |
1807 | ||
1808 | err_pages: | |
9da3da66 CW |
1809 | for_each_sg(st->sgl, sg, i, page_count) |
1810 | page_cache_release(sg_page(sg)); | |
1811 | sg_free_table(st); | |
1812 | kfree(st); | |
e5281ccd | 1813 | return PTR_ERR(page); |
673a394b EA |
1814 | } |
1815 | ||
37e680a1 CW |
1816 | /* Ensure that the associated pages are gathered from the backing storage |
1817 | * and pinned into our object. i915_gem_object_get_pages() may be called | |
1818 | * multiple times before they are released by a single call to | |
1819 | * i915_gem_object_put_pages() - once the pages are no longer referenced | |
1820 | * either as a result of memory pressure (reaping pages under the shrinker) | |
1821 | * or as the object is itself released. | |
1822 | */ | |
1823 | int | |
1824 | i915_gem_object_get_pages(struct drm_i915_gem_object *obj) | |
1825 | { | |
1826 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; | |
1827 | const struct drm_i915_gem_object_ops *ops = obj->ops; | |
1828 | int ret; | |
1829 | ||
2f745ad3 | 1830 | if (obj->pages) |
37e680a1 CW |
1831 | return 0; |
1832 | ||
43e28f09 CW |
1833 | if (obj->madv != I915_MADV_WILLNEED) { |
1834 | DRM_ERROR("Attempting to obtain a purgeable object\n"); | |
1835 | return -EINVAL; | |
1836 | } | |
1837 | ||
a5570178 CW |
1838 | BUG_ON(obj->pages_pin_count); |
1839 | ||
37e680a1 CW |
1840 | ret = ops->get_pages(obj); |
1841 | if (ret) | |
1842 | return ret; | |
1843 | ||
1844 | list_add_tail(&obj->gtt_list, &dev_priv->mm.unbound_list); | |
1845 | return 0; | |
673a394b EA |
1846 | } |
1847 | ||
54cf91dc | 1848 | void |
05394f39 | 1849 | i915_gem_object_move_to_active(struct drm_i915_gem_object *obj, |
9d773091 | 1850 | struct intel_ring_buffer *ring) |
673a394b | 1851 | { |
05394f39 | 1852 | struct drm_device *dev = obj->base.dev; |
69dc4987 | 1853 | struct drm_i915_private *dev_priv = dev->dev_private; |
9d773091 | 1854 | u32 seqno = intel_ring_get_seqno(ring); |
617dbe27 | 1855 | |
852835f3 | 1856 | BUG_ON(ring == NULL); |
05394f39 | 1857 | obj->ring = ring; |
673a394b EA |
1858 | |
1859 | /* Add a reference if we're newly entering the active list. */ | |
05394f39 CW |
1860 | if (!obj->active) { |
1861 | drm_gem_object_reference(&obj->base); | |
1862 | obj->active = 1; | |
673a394b | 1863 | } |
e35a41de | 1864 | |
673a394b | 1865 | /* Move from whatever list we were on to the tail of execution. */ |
05394f39 CW |
1866 | list_move_tail(&obj->mm_list, &dev_priv->mm.active_list); |
1867 | list_move_tail(&obj->ring_list, &ring->active_list); | |
caea7476 | 1868 | |
0201f1ec | 1869 | obj->last_read_seqno = seqno; |
caea7476 | 1870 | |
7dd49065 | 1871 | if (obj->fenced_gpu_access) { |
caea7476 | 1872 | obj->last_fenced_seqno = seqno; |
caea7476 | 1873 | |
7dd49065 CW |
1874 | /* Bump MRU to take account of the delayed flush */ |
1875 | if (obj->fence_reg != I915_FENCE_REG_NONE) { | |
1876 | struct drm_i915_fence_reg *reg; | |
1877 | ||
1878 | reg = &dev_priv->fence_regs[obj->fence_reg]; | |
1879 | list_move_tail(®->lru_list, | |
1880 | &dev_priv->mm.fence_list); | |
1881 | } | |
caea7476 CW |
1882 | } |
1883 | } | |
1884 | ||
1885 | static void | |
caea7476 | 1886 | i915_gem_object_move_to_inactive(struct drm_i915_gem_object *obj) |
ce44b0ea | 1887 | { |
05394f39 | 1888 | struct drm_device *dev = obj->base.dev; |
caea7476 | 1889 | struct drm_i915_private *dev_priv = dev->dev_private; |
ce44b0ea | 1890 | |
65ce3027 | 1891 | BUG_ON(obj->base.write_domain & ~I915_GEM_GPU_DOMAINS); |
05394f39 | 1892 | BUG_ON(!obj->active); |
caea7476 | 1893 | |
f047e395 CW |
1894 | if (obj->pin_count) /* are we a framebuffer? */ |
1895 | intel_mark_fb_idle(obj); | |
caea7476 | 1896 | |
1b50247a | 1897 | list_move_tail(&obj->mm_list, &dev_priv->mm.inactive_list); |
caea7476 | 1898 | |
65ce3027 | 1899 | list_del_init(&obj->ring_list); |
caea7476 CW |
1900 | obj->ring = NULL; |
1901 | ||
65ce3027 CW |
1902 | obj->last_read_seqno = 0; |
1903 | obj->last_write_seqno = 0; | |
1904 | obj->base.write_domain = 0; | |
1905 | ||
1906 | obj->last_fenced_seqno = 0; | |
caea7476 | 1907 | obj->fenced_gpu_access = false; |
caea7476 CW |
1908 | |
1909 | obj->active = 0; | |
1910 | drm_gem_object_unreference(&obj->base); | |
1911 | ||
1912 | WARN_ON(i915_verify_lists(dev)); | |
ce44b0ea | 1913 | } |
673a394b | 1914 | |
9d773091 | 1915 | static int |
fca26bb4 | 1916 | i915_gem_init_seqno(struct drm_device *dev, u32 seqno) |
53d227f2 | 1917 | { |
9d773091 CW |
1918 | struct drm_i915_private *dev_priv = dev->dev_private; |
1919 | struct intel_ring_buffer *ring; | |
1920 | int ret, i, j; | |
53d227f2 | 1921 | |
107f27a5 | 1922 | /* Carefully retire all requests without writing to the rings */ |
9d773091 | 1923 | for_each_ring(ring, dev_priv, i) { |
107f27a5 CW |
1924 | ret = intel_ring_idle(ring); |
1925 | if (ret) | |
1926 | return ret; | |
9d773091 | 1927 | } |
9d773091 | 1928 | i915_gem_retire_requests(dev); |
107f27a5 CW |
1929 | |
1930 | /* Finally reset hw state */ | |
9d773091 | 1931 | for_each_ring(ring, dev_priv, i) { |
fca26bb4 | 1932 | intel_ring_init_seqno(ring, seqno); |
498d2ac1 | 1933 | |
9d773091 CW |
1934 | for (j = 0; j < ARRAY_SIZE(ring->sync_seqno); j++) |
1935 | ring->sync_seqno[j] = 0; | |
1936 | } | |
53d227f2 | 1937 | |
9d773091 | 1938 | return 0; |
53d227f2 DV |
1939 | } |
1940 | ||
fca26bb4 MK |
1941 | int i915_gem_set_seqno(struct drm_device *dev, u32 seqno) |
1942 | { | |
1943 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1944 | int ret; | |
1945 | ||
1946 | if (seqno == 0) | |
1947 | return -EINVAL; | |
1948 | ||
1949 | /* HWS page needs to be set less than what we | |
1950 | * will inject to ring | |
1951 | */ | |
1952 | ret = i915_gem_init_seqno(dev, seqno - 1); | |
1953 | if (ret) | |
1954 | return ret; | |
1955 | ||
1956 | /* Carefully set the last_seqno value so that wrap | |
1957 | * detection still works | |
1958 | */ | |
1959 | dev_priv->next_seqno = seqno; | |
1960 | dev_priv->last_seqno = seqno - 1; | |
1961 | if (dev_priv->last_seqno == 0) | |
1962 | dev_priv->last_seqno--; | |
1963 | ||
1964 | return 0; | |
1965 | } | |
1966 | ||
9d773091 CW |
1967 | int |
1968 | i915_gem_get_seqno(struct drm_device *dev, u32 *seqno) | |
53d227f2 | 1969 | { |
9d773091 CW |
1970 | struct drm_i915_private *dev_priv = dev->dev_private; |
1971 | ||
1972 | /* reserve 0 for non-seqno */ | |
1973 | if (dev_priv->next_seqno == 0) { | |
fca26bb4 | 1974 | int ret = i915_gem_init_seqno(dev, 0); |
9d773091 CW |
1975 | if (ret) |
1976 | return ret; | |
53d227f2 | 1977 | |
9d773091 CW |
1978 | dev_priv->next_seqno = 1; |
1979 | } | |
53d227f2 | 1980 | |
f72b3435 | 1981 | *seqno = dev_priv->last_seqno = dev_priv->next_seqno++; |
9d773091 | 1982 | return 0; |
53d227f2 DV |
1983 | } |
1984 | ||
3cce469c | 1985 | int |
db53a302 | 1986 | i915_add_request(struct intel_ring_buffer *ring, |
f787a5f5 | 1987 | struct drm_file *file, |
acb868d3 | 1988 | u32 *out_seqno) |
673a394b | 1989 | { |
db53a302 | 1990 | drm_i915_private_t *dev_priv = ring->dev->dev_private; |
acb868d3 | 1991 | struct drm_i915_gem_request *request; |
a71d8d94 | 1992 | u32 request_ring_position; |
673a394b | 1993 | int was_empty; |
3cce469c CW |
1994 | int ret; |
1995 | ||
cc889e0f DV |
1996 | /* |
1997 | * Emit any outstanding flushes - execbuf can fail to emit the flush | |
1998 | * after having emitted the batchbuffer command. Hence we need to fix | |
1999 | * things up similar to emitting the lazy request. The difference here | |
2000 | * is that the flush _must_ happen before the next request, no matter | |
2001 | * what. | |
2002 | */ | |
a7b9761d CW |
2003 | ret = intel_ring_flush_all_caches(ring); |
2004 | if (ret) | |
2005 | return ret; | |
cc889e0f | 2006 | |
acb868d3 CW |
2007 | request = kmalloc(sizeof(*request), GFP_KERNEL); |
2008 | if (request == NULL) | |
2009 | return -ENOMEM; | |
cc889e0f | 2010 | |
673a394b | 2011 | |
a71d8d94 CW |
2012 | /* Record the position of the start of the request so that |
2013 | * should we detect the updated seqno part-way through the | |
2014 | * GPU processing the request, we never over-estimate the | |
2015 | * position of the head. | |
2016 | */ | |
2017 | request_ring_position = intel_ring_get_tail(ring); | |
2018 | ||
9d773091 | 2019 | ret = ring->add_request(ring); |
3bb73aba CW |
2020 | if (ret) { |
2021 | kfree(request); | |
2022 | return ret; | |
2023 | } | |
673a394b | 2024 | |
9d773091 | 2025 | request->seqno = intel_ring_get_seqno(ring); |
852835f3 | 2026 | request->ring = ring; |
a71d8d94 | 2027 | request->tail = request_ring_position; |
673a394b | 2028 | request->emitted_jiffies = jiffies; |
852835f3 ZN |
2029 | was_empty = list_empty(&ring->request_list); |
2030 | list_add_tail(&request->list, &ring->request_list); | |
3bb73aba | 2031 | request->file_priv = NULL; |
852835f3 | 2032 | |
db53a302 CW |
2033 | if (file) { |
2034 | struct drm_i915_file_private *file_priv = file->driver_priv; | |
2035 | ||
1c25595f | 2036 | spin_lock(&file_priv->mm.lock); |
f787a5f5 | 2037 | request->file_priv = file_priv; |
b962442e | 2038 | list_add_tail(&request->client_list, |
f787a5f5 | 2039 | &file_priv->mm.request_list); |
1c25595f | 2040 | spin_unlock(&file_priv->mm.lock); |
b962442e | 2041 | } |
673a394b | 2042 | |
9d773091 | 2043 | trace_i915_gem_request_add(ring, request->seqno); |
5391d0cf | 2044 | ring->outstanding_lazy_request = 0; |
db53a302 | 2045 | |
f65d9421 | 2046 | if (!dev_priv->mm.suspended) { |
3e0dc6b0 | 2047 | if (i915_enable_hangcheck) { |
99584db3 | 2048 | mod_timer(&dev_priv->gpu_error.hangcheck_timer, |
cecc21fe | 2049 | round_jiffies_up(jiffies + DRM_I915_HANGCHECK_JIFFIES)); |
3e0dc6b0 | 2050 | } |
f047e395 | 2051 | if (was_empty) { |
b3b079db | 2052 | queue_delayed_work(dev_priv->wq, |
bcb45086 CW |
2053 | &dev_priv->mm.retire_work, |
2054 | round_jiffies_up_relative(HZ)); | |
f047e395 CW |
2055 | intel_mark_busy(dev_priv->dev); |
2056 | } | |
f65d9421 | 2057 | } |
cc889e0f | 2058 | |
acb868d3 | 2059 | if (out_seqno) |
9d773091 | 2060 | *out_seqno = request->seqno; |
3cce469c | 2061 | return 0; |
673a394b EA |
2062 | } |
2063 | ||
f787a5f5 CW |
2064 | static inline void |
2065 | i915_gem_request_remove_from_client(struct drm_i915_gem_request *request) | |
673a394b | 2066 | { |
1c25595f | 2067 | struct drm_i915_file_private *file_priv = request->file_priv; |
673a394b | 2068 | |
1c25595f CW |
2069 | if (!file_priv) |
2070 | return; | |
1c5d22f7 | 2071 | |
1c25595f | 2072 | spin_lock(&file_priv->mm.lock); |
09bfa517 HRK |
2073 | if (request->file_priv) { |
2074 | list_del(&request->client_list); | |
2075 | request->file_priv = NULL; | |
2076 | } | |
1c25595f | 2077 | spin_unlock(&file_priv->mm.lock); |
673a394b | 2078 | } |
673a394b | 2079 | |
dfaae392 CW |
2080 | static void i915_gem_reset_ring_lists(struct drm_i915_private *dev_priv, |
2081 | struct intel_ring_buffer *ring) | |
9375e446 | 2082 | { |
dfaae392 CW |
2083 | while (!list_empty(&ring->request_list)) { |
2084 | struct drm_i915_gem_request *request; | |
673a394b | 2085 | |
dfaae392 CW |
2086 | request = list_first_entry(&ring->request_list, |
2087 | struct drm_i915_gem_request, | |
2088 | list); | |
de151cf6 | 2089 | |
dfaae392 | 2090 | list_del(&request->list); |
f787a5f5 | 2091 | i915_gem_request_remove_from_client(request); |
dfaae392 CW |
2092 | kfree(request); |
2093 | } | |
673a394b | 2094 | |
dfaae392 | 2095 | while (!list_empty(&ring->active_list)) { |
05394f39 | 2096 | struct drm_i915_gem_object *obj; |
9375e446 | 2097 | |
05394f39 CW |
2098 | obj = list_first_entry(&ring->active_list, |
2099 | struct drm_i915_gem_object, | |
2100 | ring_list); | |
9375e446 | 2101 | |
05394f39 | 2102 | i915_gem_object_move_to_inactive(obj); |
673a394b EA |
2103 | } |
2104 | } | |
2105 | ||
312817a3 CW |
2106 | static void i915_gem_reset_fences(struct drm_device *dev) |
2107 | { | |
2108 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2109 | int i; | |
2110 | ||
4b9de737 | 2111 | for (i = 0; i < dev_priv->num_fence_regs; i++) { |
312817a3 | 2112 | struct drm_i915_fence_reg *reg = &dev_priv->fence_regs[i]; |
7d2cb39c | 2113 | |
ada726c7 | 2114 | i915_gem_write_fence(dev, i, NULL); |
7d2cb39c | 2115 | |
ada726c7 CW |
2116 | if (reg->obj) |
2117 | i915_gem_object_fence_lost(reg->obj); | |
7d2cb39c | 2118 | |
ada726c7 CW |
2119 | reg->pin_count = 0; |
2120 | reg->obj = NULL; | |
2121 | INIT_LIST_HEAD(®->lru_list); | |
312817a3 | 2122 | } |
ada726c7 CW |
2123 | |
2124 | INIT_LIST_HEAD(&dev_priv->mm.fence_list); | |
312817a3 CW |
2125 | } |
2126 | ||
069efc1d | 2127 | void i915_gem_reset(struct drm_device *dev) |
673a394b | 2128 | { |
77f01230 | 2129 | struct drm_i915_private *dev_priv = dev->dev_private; |
05394f39 | 2130 | struct drm_i915_gem_object *obj; |
b4519513 | 2131 | struct intel_ring_buffer *ring; |
1ec14ad3 | 2132 | int i; |
673a394b | 2133 | |
b4519513 CW |
2134 | for_each_ring(ring, dev_priv, i) |
2135 | i915_gem_reset_ring_lists(dev_priv, ring); | |
dfaae392 | 2136 | |
dfaae392 CW |
2137 | /* Move everything out of the GPU domains to ensure we do any |
2138 | * necessary invalidation upon reuse. | |
2139 | */ | |
05394f39 | 2140 | list_for_each_entry(obj, |
77f01230 | 2141 | &dev_priv->mm.inactive_list, |
69dc4987 | 2142 | mm_list) |
77f01230 | 2143 | { |
05394f39 | 2144 | obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS; |
77f01230 | 2145 | } |
069efc1d CW |
2146 | |
2147 | /* The fence registers are invalidated so clear them out */ | |
312817a3 | 2148 | i915_gem_reset_fences(dev); |
673a394b EA |
2149 | } |
2150 | ||
2151 | /** | |
2152 | * This function clears the request list as sequence numbers are passed. | |
2153 | */ | |
a71d8d94 | 2154 | void |
db53a302 | 2155 | i915_gem_retire_requests_ring(struct intel_ring_buffer *ring) |
673a394b | 2156 | { |
673a394b EA |
2157 | uint32_t seqno; |
2158 | ||
db53a302 | 2159 | if (list_empty(&ring->request_list)) |
6c0594a3 KW |
2160 | return; |
2161 | ||
db53a302 | 2162 | WARN_ON(i915_verify_lists(ring->dev)); |
673a394b | 2163 | |
b2eadbc8 | 2164 | seqno = ring->get_seqno(ring, true); |
1ec14ad3 | 2165 | |
852835f3 | 2166 | while (!list_empty(&ring->request_list)) { |
673a394b | 2167 | struct drm_i915_gem_request *request; |
673a394b | 2168 | |
852835f3 | 2169 | request = list_first_entry(&ring->request_list, |
673a394b EA |
2170 | struct drm_i915_gem_request, |
2171 | list); | |
673a394b | 2172 | |
dfaae392 | 2173 | if (!i915_seqno_passed(seqno, request->seqno)) |
b84d5f0c CW |
2174 | break; |
2175 | ||
db53a302 | 2176 | trace_i915_gem_request_retire(ring, request->seqno); |
a71d8d94 CW |
2177 | /* We know the GPU must have read the request to have |
2178 | * sent us the seqno + interrupt, so use the position | |
2179 | * of tail of the request to update the last known position | |
2180 | * of the GPU head. | |
2181 | */ | |
2182 | ring->last_retired_head = request->tail; | |
b84d5f0c CW |
2183 | |
2184 | list_del(&request->list); | |
f787a5f5 | 2185 | i915_gem_request_remove_from_client(request); |
b84d5f0c CW |
2186 | kfree(request); |
2187 | } | |
673a394b | 2188 | |
b84d5f0c CW |
2189 | /* Move any buffers on the active list that are no longer referenced |
2190 | * by the ringbuffer to the flushing/inactive lists as appropriate. | |
2191 | */ | |
2192 | while (!list_empty(&ring->active_list)) { | |
05394f39 | 2193 | struct drm_i915_gem_object *obj; |
b84d5f0c | 2194 | |
0206e353 | 2195 | obj = list_first_entry(&ring->active_list, |
05394f39 CW |
2196 | struct drm_i915_gem_object, |
2197 | ring_list); | |
673a394b | 2198 | |
0201f1ec | 2199 | if (!i915_seqno_passed(seqno, obj->last_read_seqno)) |
673a394b | 2200 | break; |
b84d5f0c | 2201 | |
65ce3027 | 2202 | i915_gem_object_move_to_inactive(obj); |
673a394b | 2203 | } |
9d34e5db | 2204 | |
db53a302 CW |
2205 | if (unlikely(ring->trace_irq_seqno && |
2206 | i915_seqno_passed(seqno, ring->trace_irq_seqno))) { | |
1ec14ad3 | 2207 | ring->irq_put(ring); |
db53a302 | 2208 | ring->trace_irq_seqno = 0; |
9d34e5db | 2209 | } |
23bc5982 | 2210 | |
db53a302 | 2211 | WARN_ON(i915_verify_lists(ring->dev)); |
673a394b EA |
2212 | } |
2213 | ||
b09a1fec CW |
2214 | void |
2215 | i915_gem_retire_requests(struct drm_device *dev) | |
2216 | { | |
2217 | drm_i915_private_t *dev_priv = dev->dev_private; | |
b4519513 | 2218 | struct intel_ring_buffer *ring; |
1ec14ad3 | 2219 | int i; |
b09a1fec | 2220 | |
b4519513 CW |
2221 | for_each_ring(ring, dev_priv, i) |
2222 | i915_gem_retire_requests_ring(ring); | |
b09a1fec CW |
2223 | } |
2224 | ||
75ef9da2 | 2225 | static void |
673a394b EA |
2226 | i915_gem_retire_work_handler(struct work_struct *work) |
2227 | { | |
2228 | drm_i915_private_t *dev_priv; | |
2229 | struct drm_device *dev; | |
b4519513 | 2230 | struct intel_ring_buffer *ring; |
0a58705b CW |
2231 | bool idle; |
2232 | int i; | |
673a394b EA |
2233 | |
2234 | dev_priv = container_of(work, drm_i915_private_t, | |
2235 | mm.retire_work.work); | |
2236 | dev = dev_priv->dev; | |
2237 | ||
891b48cf CW |
2238 | /* Come back later if the device is busy... */ |
2239 | if (!mutex_trylock(&dev->struct_mutex)) { | |
bcb45086 CW |
2240 | queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, |
2241 | round_jiffies_up_relative(HZ)); | |
891b48cf CW |
2242 | return; |
2243 | } | |
673a394b | 2244 | |
b09a1fec | 2245 | i915_gem_retire_requests(dev); |
673a394b | 2246 | |
0a58705b CW |
2247 | /* Send a periodic flush down the ring so we don't hold onto GEM |
2248 | * objects indefinitely. | |
673a394b | 2249 | */ |
0a58705b | 2250 | idle = true; |
b4519513 | 2251 | for_each_ring(ring, dev_priv, i) { |
3bb73aba CW |
2252 | if (ring->gpu_caches_dirty) |
2253 | i915_add_request(ring, NULL, NULL); | |
0a58705b CW |
2254 | |
2255 | idle &= list_empty(&ring->request_list); | |
673a394b EA |
2256 | } |
2257 | ||
0a58705b | 2258 | if (!dev_priv->mm.suspended && !idle) |
bcb45086 CW |
2259 | queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, |
2260 | round_jiffies_up_relative(HZ)); | |
f047e395 CW |
2261 | if (idle) |
2262 | intel_mark_idle(dev); | |
0a58705b | 2263 | |
673a394b | 2264 | mutex_unlock(&dev->struct_mutex); |
673a394b EA |
2265 | } |
2266 | ||
30dfebf3 DV |
2267 | /** |
2268 | * Ensures that an object will eventually get non-busy by flushing any required | |
2269 | * write domains, emitting any outstanding lazy request and retiring and | |
2270 | * completed requests. | |
2271 | */ | |
2272 | static int | |
2273 | i915_gem_object_flush_active(struct drm_i915_gem_object *obj) | |
2274 | { | |
2275 | int ret; | |
2276 | ||
2277 | if (obj->active) { | |
0201f1ec | 2278 | ret = i915_gem_check_olr(obj->ring, obj->last_read_seqno); |
30dfebf3 DV |
2279 | if (ret) |
2280 | return ret; | |
2281 | ||
30dfebf3 DV |
2282 | i915_gem_retire_requests_ring(obj->ring); |
2283 | } | |
2284 | ||
2285 | return 0; | |
2286 | } | |
2287 | ||
23ba4fd0 BW |
2288 | /** |
2289 | * i915_gem_wait_ioctl - implements DRM_IOCTL_I915_GEM_WAIT | |
2290 | * @DRM_IOCTL_ARGS: standard ioctl arguments | |
2291 | * | |
2292 | * Returns 0 if successful, else an error is returned with the remaining time in | |
2293 | * the timeout parameter. | |
2294 | * -ETIME: object is still busy after timeout | |
2295 | * -ERESTARTSYS: signal interrupted the wait | |
2296 | * -ENONENT: object doesn't exist | |
2297 | * Also possible, but rare: | |
2298 | * -EAGAIN: GPU wedged | |
2299 | * -ENOMEM: damn | |
2300 | * -ENODEV: Internal IRQ fail | |
2301 | * -E?: The add request failed | |
2302 | * | |
2303 | * The wait ioctl with a timeout of 0 reimplements the busy ioctl. With any | |
2304 | * non-zero timeout parameter the wait ioctl will wait for the given number of | |
2305 | * nanoseconds on an object becoming unbusy. Since the wait itself does so | |
2306 | * without holding struct_mutex the object may become re-busied before this | |
2307 | * function completes. A similar but shorter * race condition exists in the busy | |
2308 | * ioctl | |
2309 | */ | |
2310 | int | |
2311 | i915_gem_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *file) | |
2312 | { | |
2313 | struct drm_i915_gem_wait *args = data; | |
2314 | struct drm_i915_gem_object *obj; | |
2315 | struct intel_ring_buffer *ring = NULL; | |
eac1f14f | 2316 | struct timespec timeout_stack, *timeout = NULL; |
23ba4fd0 BW |
2317 | u32 seqno = 0; |
2318 | int ret = 0; | |
2319 | ||
eac1f14f BW |
2320 | if (args->timeout_ns >= 0) { |
2321 | timeout_stack = ns_to_timespec(args->timeout_ns); | |
2322 | timeout = &timeout_stack; | |
2323 | } | |
23ba4fd0 BW |
2324 | |
2325 | ret = i915_mutex_lock_interruptible(dev); | |
2326 | if (ret) | |
2327 | return ret; | |
2328 | ||
2329 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->bo_handle)); | |
2330 | if (&obj->base == NULL) { | |
2331 | mutex_unlock(&dev->struct_mutex); | |
2332 | return -ENOENT; | |
2333 | } | |
2334 | ||
30dfebf3 DV |
2335 | /* Need to make sure the object gets inactive eventually. */ |
2336 | ret = i915_gem_object_flush_active(obj); | |
23ba4fd0 BW |
2337 | if (ret) |
2338 | goto out; | |
2339 | ||
2340 | if (obj->active) { | |
0201f1ec | 2341 | seqno = obj->last_read_seqno; |
23ba4fd0 BW |
2342 | ring = obj->ring; |
2343 | } | |
2344 | ||
2345 | if (seqno == 0) | |
2346 | goto out; | |
2347 | ||
23ba4fd0 BW |
2348 | /* Do this after OLR check to make sure we make forward progress polling |
2349 | * on this IOCTL with a 0 timeout (like busy ioctl) | |
2350 | */ | |
2351 | if (!args->timeout_ns) { | |
2352 | ret = -ETIME; | |
2353 | goto out; | |
2354 | } | |
2355 | ||
2356 | drm_gem_object_unreference(&obj->base); | |
2357 | mutex_unlock(&dev->struct_mutex); | |
2358 | ||
eac1f14f BW |
2359 | ret = __wait_seqno(ring, seqno, true, timeout); |
2360 | if (timeout) { | |
2361 | WARN_ON(!timespec_valid(timeout)); | |
2362 | args->timeout_ns = timespec_to_ns(timeout); | |
2363 | } | |
23ba4fd0 BW |
2364 | return ret; |
2365 | ||
2366 | out: | |
2367 | drm_gem_object_unreference(&obj->base); | |
2368 | mutex_unlock(&dev->struct_mutex); | |
2369 | return ret; | |
2370 | } | |
2371 | ||
5816d648 BW |
2372 | /** |
2373 | * i915_gem_object_sync - sync an object to a ring. | |
2374 | * | |
2375 | * @obj: object which may be in use on another ring. | |
2376 | * @to: ring we wish to use the object on. May be NULL. | |
2377 | * | |
2378 | * This code is meant to abstract object synchronization with the GPU. | |
2379 | * Calling with NULL implies synchronizing the object with the CPU | |
2380 | * rather than a particular GPU ring. | |
2381 | * | |
2382 | * Returns 0 if successful, else propagates up the lower layer error. | |
2383 | */ | |
2911a35b BW |
2384 | int |
2385 | i915_gem_object_sync(struct drm_i915_gem_object *obj, | |
2386 | struct intel_ring_buffer *to) | |
2387 | { | |
2388 | struct intel_ring_buffer *from = obj->ring; | |
2389 | u32 seqno; | |
2390 | int ret, idx; | |
2391 | ||
2392 | if (from == NULL || to == from) | |
2393 | return 0; | |
2394 | ||
5816d648 | 2395 | if (to == NULL || !i915_semaphore_is_enabled(obj->base.dev)) |
0201f1ec | 2396 | return i915_gem_object_wait_rendering(obj, false); |
2911a35b BW |
2397 | |
2398 | idx = intel_ring_sync_index(from, to); | |
2399 | ||
0201f1ec | 2400 | seqno = obj->last_read_seqno; |
2911a35b BW |
2401 | if (seqno <= from->sync_seqno[idx]) |
2402 | return 0; | |
2403 | ||
b4aca010 BW |
2404 | ret = i915_gem_check_olr(obj->ring, seqno); |
2405 | if (ret) | |
2406 | return ret; | |
2911a35b | 2407 | |
1500f7ea | 2408 | ret = to->sync_to(to, from, seqno); |
e3a5a225 | 2409 | if (!ret) |
7b01e260 MK |
2410 | /* We use last_read_seqno because sync_to() |
2411 | * might have just caused seqno wrap under | |
2412 | * the radar. | |
2413 | */ | |
2414 | from->sync_seqno[idx] = obj->last_read_seqno; | |
2911a35b | 2415 | |
e3a5a225 | 2416 | return ret; |
2911a35b BW |
2417 | } |
2418 | ||
b5ffc9bc CW |
2419 | static void i915_gem_object_finish_gtt(struct drm_i915_gem_object *obj) |
2420 | { | |
2421 | u32 old_write_domain, old_read_domains; | |
2422 | ||
b5ffc9bc CW |
2423 | /* Act a barrier for all accesses through the GTT */ |
2424 | mb(); | |
2425 | ||
2426 | /* Force a pagefault for domain tracking on next user access */ | |
2427 | i915_gem_release_mmap(obj); | |
2428 | ||
b97c3d9c KP |
2429 | if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0) |
2430 | return; | |
2431 | ||
b5ffc9bc CW |
2432 | old_read_domains = obj->base.read_domains; |
2433 | old_write_domain = obj->base.write_domain; | |
2434 | ||
2435 | obj->base.read_domains &= ~I915_GEM_DOMAIN_GTT; | |
2436 | obj->base.write_domain &= ~I915_GEM_DOMAIN_GTT; | |
2437 | ||
2438 | trace_i915_gem_object_change_domain(obj, | |
2439 | old_read_domains, | |
2440 | old_write_domain); | |
2441 | } | |
2442 | ||
673a394b EA |
2443 | /** |
2444 | * Unbinds an object from the GTT aperture. | |
2445 | */ | |
0f973f27 | 2446 | int |
05394f39 | 2447 | i915_gem_object_unbind(struct drm_i915_gem_object *obj) |
673a394b | 2448 | { |
7bddb01f | 2449 | drm_i915_private_t *dev_priv = obj->base.dev->dev_private; |
43e28f09 | 2450 | int ret; |
673a394b | 2451 | |
05394f39 | 2452 | if (obj->gtt_space == NULL) |
673a394b EA |
2453 | return 0; |
2454 | ||
31d8d651 CW |
2455 | if (obj->pin_count) |
2456 | return -EBUSY; | |
673a394b | 2457 | |
c4670ad0 CW |
2458 | BUG_ON(obj->pages == NULL); |
2459 | ||
a8198eea | 2460 | ret = i915_gem_object_finish_gpu(obj); |
1488fc08 | 2461 | if (ret) |
a8198eea CW |
2462 | return ret; |
2463 | /* Continue on if we fail due to EIO, the GPU is hung so we | |
2464 | * should be safe and we need to cleanup or else we might | |
2465 | * cause memory corruption through use-after-free. | |
2466 | */ | |
2467 | ||
b5ffc9bc | 2468 | i915_gem_object_finish_gtt(obj); |
5323fd04 | 2469 | |
96b47b65 | 2470 | /* release the fence reg _after_ flushing */ |
d9e86c0e | 2471 | ret = i915_gem_object_put_fence(obj); |
1488fc08 | 2472 | if (ret) |
d9e86c0e | 2473 | return ret; |
96b47b65 | 2474 | |
db53a302 CW |
2475 | trace_i915_gem_object_unbind(obj); |
2476 | ||
74898d7e DV |
2477 | if (obj->has_global_gtt_mapping) |
2478 | i915_gem_gtt_unbind_object(obj); | |
7bddb01f DV |
2479 | if (obj->has_aliasing_ppgtt_mapping) { |
2480 | i915_ppgtt_unbind_object(dev_priv->mm.aliasing_ppgtt, obj); | |
2481 | obj->has_aliasing_ppgtt_mapping = 0; | |
2482 | } | |
74163907 | 2483 | i915_gem_gtt_finish_object(obj); |
7bddb01f | 2484 | |
6c085a72 CW |
2485 | list_del(&obj->mm_list); |
2486 | list_move_tail(&obj->gtt_list, &dev_priv->mm.unbound_list); | |
75e9e915 | 2487 | /* Avoid an unnecessary call to unbind on rebind. */ |
05394f39 | 2488 | obj->map_and_fenceable = true; |
673a394b | 2489 | |
05394f39 CW |
2490 | drm_mm_put_block(obj->gtt_space); |
2491 | obj->gtt_space = NULL; | |
2492 | obj->gtt_offset = 0; | |
673a394b | 2493 | |
88241785 | 2494 | return 0; |
54cf91dc CW |
2495 | } |
2496 | ||
b2da9fe5 | 2497 | int i915_gpu_idle(struct drm_device *dev) |
4df2faf4 DV |
2498 | { |
2499 | drm_i915_private_t *dev_priv = dev->dev_private; | |
b4519513 | 2500 | struct intel_ring_buffer *ring; |
1ec14ad3 | 2501 | int ret, i; |
4df2faf4 | 2502 | |
4df2faf4 | 2503 | /* Flush everything onto the inactive list. */ |
b4519513 | 2504 | for_each_ring(ring, dev_priv, i) { |
b6c7488d BW |
2505 | ret = i915_switch_context(ring, NULL, DEFAULT_CONTEXT_ID); |
2506 | if (ret) | |
2507 | return ret; | |
2508 | ||
3e960501 | 2509 | ret = intel_ring_idle(ring); |
1ec14ad3 CW |
2510 | if (ret) |
2511 | return ret; | |
2512 | } | |
4df2faf4 | 2513 | |
8a1a49f9 | 2514 | return 0; |
4df2faf4 DV |
2515 | } |
2516 | ||
9ce079e4 CW |
2517 | static void i965_write_fence_reg(struct drm_device *dev, int reg, |
2518 | struct drm_i915_gem_object *obj) | |
de151cf6 | 2519 | { |
de151cf6 | 2520 | drm_i915_private_t *dev_priv = dev->dev_private; |
56c844e5 ID |
2521 | int fence_reg; |
2522 | int fence_pitch_shift; | |
de151cf6 JB |
2523 | uint64_t val; |
2524 | ||
56c844e5 ID |
2525 | if (INTEL_INFO(dev)->gen >= 6) { |
2526 | fence_reg = FENCE_REG_SANDYBRIDGE_0; | |
2527 | fence_pitch_shift = SANDYBRIDGE_FENCE_PITCH_SHIFT; | |
2528 | } else { | |
2529 | fence_reg = FENCE_REG_965_0; | |
2530 | fence_pitch_shift = I965_FENCE_PITCH_SHIFT; | |
2531 | } | |
2532 | ||
9ce079e4 CW |
2533 | if (obj) { |
2534 | u32 size = obj->gtt_space->size; | |
de151cf6 | 2535 | |
9ce079e4 CW |
2536 | val = (uint64_t)((obj->gtt_offset + size - 4096) & |
2537 | 0xfffff000) << 32; | |
2538 | val |= obj->gtt_offset & 0xfffff000; | |
56c844e5 | 2539 | val |= (uint64_t)((obj->stride / 128) - 1) << fence_pitch_shift; |
9ce079e4 CW |
2540 | if (obj->tiling_mode == I915_TILING_Y) |
2541 | val |= 1 << I965_FENCE_TILING_Y_SHIFT; | |
2542 | val |= I965_FENCE_REG_VALID; | |
2543 | } else | |
2544 | val = 0; | |
c6642782 | 2545 | |
56c844e5 ID |
2546 | fence_reg += reg * 8; |
2547 | I915_WRITE64(fence_reg, val); | |
2548 | POSTING_READ(fence_reg); | |
de151cf6 JB |
2549 | } |
2550 | ||
9ce079e4 CW |
2551 | static void i915_write_fence_reg(struct drm_device *dev, int reg, |
2552 | struct drm_i915_gem_object *obj) | |
de151cf6 | 2553 | { |
de151cf6 | 2554 | drm_i915_private_t *dev_priv = dev->dev_private; |
9ce079e4 | 2555 | u32 val; |
de151cf6 | 2556 | |
9ce079e4 CW |
2557 | if (obj) { |
2558 | u32 size = obj->gtt_space->size; | |
2559 | int pitch_val; | |
2560 | int tile_width; | |
c6642782 | 2561 | |
9ce079e4 CW |
2562 | WARN((obj->gtt_offset & ~I915_FENCE_START_MASK) || |
2563 | (size & -size) != size || | |
2564 | (obj->gtt_offset & (size - 1)), | |
2565 | "object 0x%08x [fenceable? %d] not 1M or pot-size (0x%08x) aligned\n", | |
2566 | obj->gtt_offset, obj->map_and_fenceable, size); | |
c6642782 | 2567 | |
9ce079e4 CW |
2568 | if (obj->tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev)) |
2569 | tile_width = 128; | |
2570 | else | |
2571 | tile_width = 512; | |
2572 | ||
2573 | /* Note: pitch better be a power of two tile widths */ | |
2574 | pitch_val = obj->stride / tile_width; | |
2575 | pitch_val = ffs(pitch_val) - 1; | |
2576 | ||
2577 | val = obj->gtt_offset; | |
2578 | if (obj->tiling_mode == I915_TILING_Y) | |
2579 | val |= 1 << I830_FENCE_TILING_Y_SHIFT; | |
2580 | val |= I915_FENCE_SIZE_BITS(size); | |
2581 | val |= pitch_val << I830_FENCE_PITCH_SHIFT; | |
2582 | val |= I830_FENCE_REG_VALID; | |
2583 | } else | |
2584 | val = 0; | |
2585 | ||
2586 | if (reg < 8) | |
2587 | reg = FENCE_REG_830_0 + reg * 4; | |
2588 | else | |
2589 | reg = FENCE_REG_945_8 + (reg - 8) * 4; | |
2590 | ||
2591 | I915_WRITE(reg, val); | |
2592 | POSTING_READ(reg); | |
de151cf6 JB |
2593 | } |
2594 | ||
9ce079e4 CW |
2595 | static void i830_write_fence_reg(struct drm_device *dev, int reg, |
2596 | struct drm_i915_gem_object *obj) | |
de151cf6 | 2597 | { |
de151cf6 | 2598 | drm_i915_private_t *dev_priv = dev->dev_private; |
de151cf6 | 2599 | uint32_t val; |
de151cf6 | 2600 | |
9ce079e4 CW |
2601 | if (obj) { |
2602 | u32 size = obj->gtt_space->size; | |
2603 | uint32_t pitch_val; | |
de151cf6 | 2604 | |
9ce079e4 CW |
2605 | WARN((obj->gtt_offset & ~I830_FENCE_START_MASK) || |
2606 | (size & -size) != size || | |
2607 | (obj->gtt_offset & (size - 1)), | |
2608 | "object 0x%08x not 512K or pot-size 0x%08x aligned\n", | |
2609 | obj->gtt_offset, size); | |
e76a16de | 2610 | |
9ce079e4 CW |
2611 | pitch_val = obj->stride / 128; |
2612 | pitch_val = ffs(pitch_val) - 1; | |
de151cf6 | 2613 | |
9ce079e4 CW |
2614 | val = obj->gtt_offset; |
2615 | if (obj->tiling_mode == I915_TILING_Y) | |
2616 | val |= 1 << I830_FENCE_TILING_Y_SHIFT; | |
2617 | val |= I830_FENCE_SIZE_BITS(size); | |
2618 | val |= pitch_val << I830_FENCE_PITCH_SHIFT; | |
2619 | val |= I830_FENCE_REG_VALID; | |
2620 | } else | |
2621 | val = 0; | |
c6642782 | 2622 | |
9ce079e4 CW |
2623 | I915_WRITE(FENCE_REG_830_0 + reg * 4, val); |
2624 | POSTING_READ(FENCE_REG_830_0 + reg * 4); | |
2625 | } | |
2626 | ||
2627 | static void i915_gem_write_fence(struct drm_device *dev, int reg, | |
2628 | struct drm_i915_gem_object *obj) | |
2629 | { | |
2630 | switch (INTEL_INFO(dev)->gen) { | |
2631 | case 7: | |
56c844e5 | 2632 | case 6: |
9ce079e4 CW |
2633 | case 5: |
2634 | case 4: i965_write_fence_reg(dev, reg, obj); break; | |
2635 | case 3: i915_write_fence_reg(dev, reg, obj); break; | |
2636 | case 2: i830_write_fence_reg(dev, reg, obj); break; | |
7dbf9d6e | 2637 | default: BUG(); |
9ce079e4 | 2638 | } |
de151cf6 JB |
2639 | } |
2640 | ||
61050808 CW |
2641 | static inline int fence_number(struct drm_i915_private *dev_priv, |
2642 | struct drm_i915_fence_reg *fence) | |
2643 | { | |
2644 | return fence - dev_priv->fence_regs; | |
2645 | } | |
2646 | ||
2647 | static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj, | |
2648 | struct drm_i915_fence_reg *fence, | |
2649 | bool enable) | |
2650 | { | |
2651 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; | |
2652 | int reg = fence_number(dev_priv, fence); | |
2653 | ||
2654 | i915_gem_write_fence(obj->base.dev, reg, enable ? obj : NULL); | |
2655 | ||
2656 | if (enable) { | |
2657 | obj->fence_reg = reg; | |
2658 | fence->obj = obj; | |
2659 | list_move_tail(&fence->lru_list, &dev_priv->mm.fence_list); | |
2660 | } else { | |
2661 | obj->fence_reg = I915_FENCE_REG_NONE; | |
2662 | fence->obj = NULL; | |
2663 | list_del_init(&fence->lru_list); | |
2664 | } | |
2665 | } | |
2666 | ||
d9e86c0e | 2667 | static int |
a360bb1a | 2668 | i915_gem_object_flush_fence(struct drm_i915_gem_object *obj) |
d9e86c0e | 2669 | { |
1c293ea3 | 2670 | if (obj->last_fenced_seqno) { |
86d5bc37 | 2671 | int ret = i915_wait_seqno(obj->ring, obj->last_fenced_seqno); |
18991845 CW |
2672 | if (ret) |
2673 | return ret; | |
d9e86c0e CW |
2674 | |
2675 | obj->last_fenced_seqno = 0; | |
d9e86c0e CW |
2676 | } |
2677 | ||
63256ec5 CW |
2678 | /* Ensure that all CPU reads are completed before installing a fence |
2679 | * and all writes before removing the fence. | |
2680 | */ | |
2681 | if (obj->base.read_domains & I915_GEM_DOMAIN_GTT) | |
2682 | mb(); | |
2683 | ||
86d5bc37 | 2684 | obj->fenced_gpu_access = false; |
d9e86c0e CW |
2685 | return 0; |
2686 | } | |
2687 | ||
2688 | int | |
2689 | i915_gem_object_put_fence(struct drm_i915_gem_object *obj) | |
2690 | { | |
61050808 | 2691 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
d9e86c0e CW |
2692 | int ret; |
2693 | ||
a360bb1a | 2694 | ret = i915_gem_object_flush_fence(obj); |
d9e86c0e CW |
2695 | if (ret) |
2696 | return ret; | |
2697 | ||
61050808 CW |
2698 | if (obj->fence_reg == I915_FENCE_REG_NONE) |
2699 | return 0; | |
d9e86c0e | 2700 | |
61050808 CW |
2701 | i915_gem_object_update_fence(obj, |
2702 | &dev_priv->fence_regs[obj->fence_reg], | |
2703 | false); | |
2704 | i915_gem_object_fence_lost(obj); | |
d9e86c0e CW |
2705 | |
2706 | return 0; | |
2707 | } | |
2708 | ||
2709 | static struct drm_i915_fence_reg * | |
a360bb1a | 2710 | i915_find_fence_reg(struct drm_device *dev) |
ae3db24a | 2711 | { |
ae3db24a | 2712 | struct drm_i915_private *dev_priv = dev->dev_private; |
8fe301ad | 2713 | struct drm_i915_fence_reg *reg, *avail; |
d9e86c0e | 2714 | int i; |
ae3db24a DV |
2715 | |
2716 | /* First try to find a free reg */ | |
d9e86c0e | 2717 | avail = NULL; |
ae3db24a DV |
2718 | for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) { |
2719 | reg = &dev_priv->fence_regs[i]; | |
2720 | if (!reg->obj) | |
d9e86c0e | 2721 | return reg; |
ae3db24a | 2722 | |
1690e1eb | 2723 | if (!reg->pin_count) |
d9e86c0e | 2724 | avail = reg; |
ae3db24a DV |
2725 | } |
2726 | ||
d9e86c0e CW |
2727 | if (avail == NULL) |
2728 | return NULL; | |
ae3db24a DV |
2729 | |
2730 | /* None available, try to steal one or wait for a user to finish */ | |
d9e86c0e | 2731 | list_for_each_entry(reg, &dev_priv->mm.fence_list, lru_list) { |
1690e1eb | 2732 | if (reg->pin_count) |
ae3db24a DV |
2733 | continue; |
2734 | ||
8fe301ad | 2735 | return reg; |
ae3db24a DV |
2736 | } |
2737 | ||
8fe301ad | 2738 | return NULL; |
ae3db24a DV |
2739 | } |
2740 | ||
de151cf6 | 2741 | /** |
9a5a53b3 | 2742 | * i915_gem_object_get_fence - set up fencing for an object |
de151cf6 JB |
2743 | * @obj: object to map through a fence reg |
2744 | * | |
2745 | * When mapping objects through the GTT, userspace wants to be able to write | |
2746 | * to them without having to worry about swizzling if the object is tiled. | |
de151cf6 JB |
2747 | * This function walks the fence regs looking for a free one for @obj, |
2748 | * stealing one if it can't find any. | |
2749 | * | |
2750 | * It then sets up the reg based on the object's properties: address, pitch | |
2751 | * and tiling format. | |
9a5a53b3 CW |
2752 | * |
2753 | * For an untiled surface, this removes any existing fence. | |
de151cf6 | 2754 | */ |
8c4b8c3f | 2755 | int |
06d98131 | 2756 | i915_gem_object_get_fence(struct drm_i915_gem_object *obj) |
de151cf6 | 2757 | { |
05394f39 | 2758 | struct drm_device *dev = obj->base.dev; |
79e53945 | 2759 | struct drm_i915_private *dev_priv = dev->dev_private; |
14415745 | 2760 | bool enable = obj->tiling_mode != I915_TILING_NONE; |
d9e86c0e | 2761 | struct drm_i915_fence_reg *reg; |
ae3db24a | 2762 | int ret; |
de151cf6 | 2763 | |
14415745 CW |
2764 | /* Have we updated the tiling parameters upon the object and so |
2765 | * will need to serialise the write to the associated fence register? | |
2766 | */ | |
5d82e3e6 | 2767 | if (obj->fence_dirty) { |
14415745 CW |
2768 | ret = i915_gem_object_flush_fence(obj); |
2769 | if (ret) | |
2770 | return ret; | |
2771 | } | |
9a5a53b3 | 2772 | |
d9e86c0e | 2773 | /* Just update our place in the LRU if our fence is getting reused. */ |
05394f39 CW |
2774 | if (obj->fence_reg != I915_FENCE_REG_NONE) { |
2775 | reg = &dev_priv->fence_regs[obj->fence_reg]; | |
5d82e3e6 | 2776 | if (!obj->fence_dirty) { |
14415745 CW |
2777 | list_move_tail(®->lru_list, |
2778 | &dev_priv->mm.fence_list); | |
2779 | return 0; | |
2780 | } | |
2781 | } else if (enable) { | |
2782 | reg = i915_find_fence_reg(dev); | |
2783 | if (reg == NULL) | |
2784 | return -EDEADLK; | |
d9e86c0e | 2785 | |
14415745 CW |
2786 | if (reg->obj) { |
2787 | struct drm_i915_gem_object *old = reg->obj; | |
2788 | ||
2789 | ret = i915_gem_object_flush_fence(old); | |
29c5a587 CW |
2790 | if (ret) |
2791 | return ret; | |
2792 | ||
14415745 | 2793 | i915_gem_object_fence_lost(old); |
29c5a587 | 2794 | } |
14415745 | 2795 | } else |
a09ba7fa | 2796 | return 0; |
a09ba7fa | 2797 | |
14415745 | 2798 | i915_gem_object_update_fence(obj, reg, enable); |
5d82e3e6 | 2799 | obj->fence_dirty = false; |
14415745 | 2800 | |
9ce079e4 | 2801 | return 0; |
de151cf6 JB |
2802 | } |
2803 | ||
42d6ab48 CW |
2804 | static bool i915_gem_valid_gtt_space(struct drm_device *dev, |
2805 | struct drm_mm_node *gtt_space, | |
2806 | unsigned long cache_level) | |
2807 | { | |
2808 | struct drm_mm_node *other; | |
2809 | ||
2810 | /* On non-LLC machines we have to be careful when putting differing | |
2811 | * types of snoopable memory together to avoid the prefetcher | |
4239ca77 | 2812 | * crossing memory domains and dying. |
42d6ab48 CW |
2813 | */ |
2814 | if (HAS_LLC(dev)) | |
2815 | return true; | |
2816 | ||
2817 | if (gtt_space == NULL) | |
2818 | return true; | |
2819 | ||
2820 | if (list_empty(>t_space->node_list)) | |
2821 | return true; | |
2822 | ||
2823 | other = list_entry(gtt_space->node_list.prev, struct drm_mm_node, node_list); | |
2824 | if (other->allocated && !other->hole_follows && other->color != cache_level) | |
2825 | return false; | |
2826 | ||
2827 | other = list_entry(gtt_space->node_list.next, struct drm_mm_node, node_list); | |
2828 | if (other->allocated && !gtt_space->hole_follows && other->color != cache_level) | |
2829 | return false; | |
2830 | ||
2831 | return true; | |
2832 | } | |
2833 | ||
2834 | static void i915_gem_verify_gtt(struct drm_device *dev) | |
2835 | { | |
2836 | #if WATCH_GTT | |
2837 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2838 | struct drm_i915_gem_object *obj; | |
2839 | int err = 0; | |
2840 | ||
2841 | list_for_each_entry(obj, &dev_priv->mm.gtt_list, gtt_list) { | |
2842 | if (obj->gtt_space == NULL) { | |
2843 | printk(KERN_ERR "object found on GTT list with no space reserved\n"); | |
2844 | err++; | |
2845 | continue; | |
2846 | } | |
2847 | ||
2848 | if (obj->cache_level != obj->gtt_space->color) { | |
2849 | printk(KERN_ERR "object reserved space [%08lx, %08lx] with wrong color, cache_level=%x, color=%lx\n", | |
2850 | obj->gtt_space->start, | |
2851 | obj->gtt_space->start + obj->gtt_space->size, | |
2852 | obj->cache_level, | |
2853 | obj->gtt_space->color); | |
2854 | err++; | |
2855 | continue; | |
2856 | } | |
2857 | ||
2858 | if (!i915_gem_valid_gtt_space(dev, | |
2859 | obj->gtt_space, | |
2860 | obj->cache_level)) { | |
2861 | printk(KERN_ERR "invalid GTT space found at [%08lx, %08lx] - color=%x\n", | |
2862 | obj->gtt_space->start, | |
2863 | obj->gtt_space->start + obj->gtt_space->size, | |
2864 | obj->cache_level); | |
2865 | err++; | |
2866 | continue; | |
2867 | } | |
2868 | } | |
2869 | ||
2870 | WARN_ON(err); | |
2871 | #endif | |
2872 | } | |
2873 | ||
673a394b EA |
2874 | /** |
2875 | * Finds free space in the GTT aperture and binds the object there. | |
2876 | */ | |
2877 | static int | |
05394f39 | 2878 | i915_gem_object_bind_to_gtt(struct drm_i915_gem_object *obj, |
920afa77 | 2879 | unsigned alignment, |
86a1ee26 CW |
2880 | bool map_and_fenceable, |
2881 | bool nonblocking) | |
673a394b | 2882 | { |
05394f39 | 2883 | struct drm_device *dev = obj->base.dev; |
673a394b | 2884 | drm_i915_private_t *dev_priv = dev->dev_private; |
dc9dd7a2 | 2885 | struct drm_mm_node *node; |
5e783301 | 2886 | u32 size, fence_size, fence_alignment, unfenced_alignment; |
75e9e915 | 2887 | bool mappable, fenceable; |
07f73f69 | 2888 | int ret; |
673a394b | 2889 | |
e28f8711 CW |
2890 | fence_size = i915_gem_get_gtt_size(dev, |
2891 | obj->base.size, | |
2892 | obj->tiling_mode); | |
2893 | fence_alignment = i915_gem_get_gtt_alignment(dev, | |
2894 | obj->base.size, | |
d865110c | 2895 | obj->tiling_mode, true); |
e28f8711 | 2896 | unfenced_alignment = |
d865110c | 2897 | i915_gem_get_gtt_alignment(dev, |
e28f8711 | 2898 | obj->base.size, |
d865110c | 2899 | obj->tiling_mode, false); |
a00b10c3 | 2900 | |
673a394b | 2901 | if (alignment == 0) |
5e783301 DV |
2902 | alignment = map_and_fenceable ? fence_alignment : |
2903 | unfenced_alignment; | |
75e9e915 | 2904 | if (map_and_fenceable && alignment & (fence_alignment - 1)) { |
673a394b EA |
2905 | DRM_ERROR("Invalid object alignment requested %u\n", alignment); |
2906 | return -EINVAL; | |
2907 | } | |
2908 | ||
05394f39 | 2909 | size = map_and_fenceable ? fence_size : obj->base.size; |
a00b10c3 | 2910 | |
654fc607 CW |
2911 | /* If the object is bigger than the entire aperture, reject it early |
2912 | * before evicting everything in a vain attempt to find space. | |
2913 | */ | |
05394f39 | 2914 | if (obj->base.size > |
5d4545ae | 2915 | (map_and_fenceable ? dev_priv->gtt.mappable_end : dev_priv->gtt.total)) { |
654fc607 CW |
2916 | DRM_ERROR("Attempting to bind an object larger than the aperture\n"); |
2917 | return -E2BIG; | |
2918 | } | |
2919 | ||
37e680a1 | 2920 | ret = i915_gem_object_get_pages(obj); |
6c085a72 CW |
2921 | if (ret) |
2922 | return ret; | |
2923 | ||
fbdda6fb CW |
2924 | i915_gem_object_pin_pages(obj); |
2925 | ||
dc9dd7a2 CW |
2926 | node = kzalloc(sizeof(*node), GFP_KERNEL); |
2927 | if (node == NULL) { | |
2928 | i915_gem_object_unpin_pages(obj); | |
2929 | return -ENOMEM; | |
2930 | } | |
2931 | ||
673a394b | 2932 | search_free: |
75e9e915 | 2933 | if (map_and_fenceable) |
dc9dd7a2 CW |
2934 | ret = drm_mm_insert_node_in_range_generic(&dev_priv->mm.gtt_space, node, |
2935 | size, alignment, obj->cache_level, | |
5d4545ae | 2936 | 0, dev_priv->gtt.mappable_end); |
920afa77 | 2937 | else |
dc9dd7a2 CW |
2938 | ret = drm_mm_insert_node_generic(&dev_priv->mm.gtt_space, node, |
2939 | size, alignment, obj->cache_level); | |
2940 | if (ret) { | |
75e9e915 | 2941 | ret = i915_gem_evict_something(dev, size, alignment, |
42d6ab48 | 2942 | obj->cache_level, |
86a1ee26 CW |
2943 | map_and_fenceable, |
2944 | nonblocking); | |
dc9dd7a2 CW |
2945 | if (ret == 0) |
2946 | goto search_free; | |
9731129c | 2947 | |
dc9dd7a2 CW |
2948 | i915_gem_object_unpin_pages(obj); |
2949 | kfree(node); | |
2950 | return ret; | |
673a394b | 2951 | } |
dc9dd7a2 | 2952 | if (WARN_ON(!i915_gem_valid_gtt_space(dev, node, obj->cache_level))) { |
fbdda6fb | 2953 | i915_gem_object_unpin_pages(obj); |
dc9dd7a2 | 2954 | drm_mm_put_block(node); |
42d6ab48 | 2955 | return -EINVAL; |
673a394b EA |
2956 | } |
2957 | ||
74163907 | 2958 | ret = i915_gem_gtt_prepare_object(obj); |
7c2e6fdf | 2959 | if (ret) { |
fbdda6fb | 2960 | i915_gem_object_unpin_pages(obj); |
dc9dd7a2 | 2961 | drm_mm_put_block(node); |
6c085a72 | 2962 | return ret; |
673a394b | 2963 | } |
673a394b | 2964 | |
6c085a72 | 2965 | list_move_tail(&obj->gtt_list, &dev_priv->mm.bound_list); |
05394f39 | 2966 | list_add_tail(&obj->mm_list, &dev_priv->mm.inactive_list); |
bf1a1092 | 2967 | |
dc9dd7a2 CW |
2968 | obj->gtt_space = node; |
2969 | obj->gtt_offset = node->start; | |
1c5d22f7 | 2970 | |
75e9e915 | 2971 | fenceable = |
dc9dd7a2 CW |
2972 | node->size == fence_size && |
2973 | (node->start & (fence_alignment - 1)) == 0; | |
a00b10c3 | 2974 | |
75e9e915 | 2975 | mappable = |
5d4545ae | 2976 | obj->gtt_offset + obj->base.size <= dev_priv->gtt.mappable_end; |
a00b10c3 | 2977 | |
05394f39 | 2978 | obj->map_and_fenceable = mappable && fenceable; |
75e9e915 | 2979 | |
fbdda6fb | 2980 | i915_gem_object_unpin_pages(obj); |
db53a302 | 2981 | trace_i915_gem_object_bind(obj, map_and_fenceable); |
42d6ab48 | 2982 | i915_gem_verify_gtt(dev); |
673a394b EA |
2983 | return 0; |
2984 | } | |
2985 | ||
2986 | void | |
05394f39 | 2987 | i915_gem_clflush_object(struct drm_i915_gem_object *obj) |
673a394b | 2988 | { |
673a394b EA |
2989 | /* If we don't have a page list set up, then we're not pinned |
2990 | * to GPU, and we can ignore the cache flush because it'll happen | |
2991 | * again at bind time. | |
2992 | */ | |
05394f39 | 2993 | if (obj->pages == NULL) |
673a394b EA |
2994 | return; |
2995 | ||
9c23f7fc CW |
2996 | /* If the GPU is snooping the contents of the CPU cache, |
2997 | * we do not need to manually clear the CPU cache lines. However, | |
2998 | * the caches are only snooped when the render cache is | |
2999 | * flushed/invalidated. As we always have to emit invalidations | |
3000 | * and flushes when moving into and out of the RENDER domain, correct | |
3001 | * snooping behaviour occurs naturally as the result of our domain | |
3002 | * tracking. | |
3003 | */ | |
3004 | if (obj->cache_level != I915_CACHE_NONE) | |
3005 | return; | |
3006 | ||
1c5d22f7 | 3007 | trace_i915_gem_object_clflush(obj); |
cfa16a0d | 3008 | |
9da3da66 | 3009 | drm_clflush_sg(obj->pages); |
e47c68e9 EA |
3010 | } |
3011 | ||
3012 | /** Flushes the GTT write domain for the object if it's dirty. */ | |
3013 | static void | |
05394f39 | 3014 | i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj) |
e47c68e9 | 3015 | { |
1c5d22f7 CW |
3016 | uint32_t old_write_domain; |
3017 | ||
05394f39 | 3018 | if (obj->base.write_domain != I915_GEM_DOMAIN_GTT) |
e47c68e9 EA |
3019 | return; |
3020 | ||
63256ec5 | 3021 | /* No actual flushing is required for the GTT write domain. Writes |
e47c68e9 EA |
3022 | * to it immediately go to main memory as far as we know, so there's |
3023 | * no chipset flush. It also doesn't land in render cache. | |
63256ec5 CW |
3024 | * |
3025 | * However, we do have to enforce the order so that all writes through | |
3026 | * the GTT land before any writes to the device, such as updates to | |
3027 | * the GATT itself. | |
e47c68e9 | 3028 | */ |
63256ec5 CW |
3029 | wmb(); |
3030 | ||
05394f39 CW |
3031 | old_write_domain = obj->base.write_domain; |
3032 | obj->base.write_domain = 0; | |
1c5d22f7 CW |
3033 | |
3034 | trace_i915_gem_object_change_domain(obj, | |
05394f39 | 3035 | obj->base.read_domains, |
1c5d22f7 | 3036 | old_write_domain); |
e47c68e9 EA |
3037 | } |
3038 | ||
3039 | /** Flushes the CPU write domain for the object if it's dirty. */ | |
3040 | static void | |
05394f39 | 3041 | i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj) |
e47c68e9 | 3042 | { |
1c5d22f7 | 3043 | uint32_t old_write_domain; |
e47c68e9 | 3044 | |
05394f39 | 3045 | if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) |
e47c68e9 EA |
3046 | return; |
3047 | ||
3048 | i915_gem_clflush_object(obj); | |
e76e9aeb | 3049 | i915_gem_chipset_flush(obj->base.dev); |
05394f39 CW |
3050 | old_write_domain = obj->base.write_domain; |
3051 | obj->base.write_domain = 0; | |
1c5d22f7 CW |
3052 | |
3053 | trace_i915_gem_object_change_domain(obj, | |
05394f39 | 3054 | obj->base.read_domains, |
1c5d22f7 | 3055 | old_write_domain); |
e47c68e9 EA |
3056 | } |
3057 | ||
2ef7eeaa EA |
3058 | /** |
3059 | * Moves a single object to the GTT read, and possibly write domain. | |
3060 | * | |
3061 | * This function returns when the move is complete, including waiting on | |
3062 | * flushes to occur. | |
3063 | */ | |
79e53945 | 3064 | int |
2021746e | 3065 | i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write) |
2ef7eeaa | 3066 | { |
8325a09d | 3067 | drm_i915_private_t *dev_priv = obj->base.dev->dev_private; |
1c5d22f7 | 3068 | uint32_t old_write_domain, old_read_domains; |
e47c68e9 | 3069 | int ret; |
2ef7eeaa | 3070 | |
02354392 | 3071 | /* Not valid to be called on unbound objects. */ |
05394f39 | 3072 | if (obj->gtt_space == NULL) |
02354392 EA |
3073 | return -EINVAL; |
3074 | ||
8d7e3de1 CW |
3075 | if (obj->base.write_domain == I915_GEM_DOMAIN_GTT) |
3076 | return 0; | |
3077 | ||
0201f1ec | 3078 | ret = i915_gem_object_wait_rendering(obj, !write); |
88241785 CW |
3079 | if (ret) |
3080 | return ret; | |
3081 | ||
7213342d | 3082 | i915_gem_object_flush_cpu_write_domain(obj); |
1c5d22f7 | 3083 | |
05394f39 CW |
3084 | old_write_domain = obj->base.write_domain; |
3085 | old_read_domains = obj->base.read_domains; | |
1c5d22f7 | 3086 | |
e47c68e9 EA |
3087 | /* It should now be out of any other write domains, and we can update |
3088 | * the domain values for our changes. | |
3089 | */ | |
05394f39 CW |
3090 | BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) != 0); |
3091 | obj->base.read_domains |= I915_GEM_DOMAIN_GTT; | |
e47c68e9 | 3092 | if (write) { |
05394f39 CW |
3093 | obj->base.read_domains = I915_GEM_DOMAIN_GTT; |
3094 | obj->base.write_domain = I915_GEM_DOMAIN_GTT; | |
3095 | obj->dirty = 1; | |
2ef7eeaa EA |
3096 | } |
3097 | ||
1c5d22f7 CW |
3098 | trace_i915_gem_object_change_domain(obj, |
3099 | old_read_domains, | |
3100 | old_write_domain); | |
3101 | ||
8325a09d CW |
3102 | /* And bump the LRU for this access */ |
3103 | if (i915_gem_object_is_inactive(obj)) | |
3104 | list_move_tail(&obj->mm_list, &dev_priv->mm.inactive_list); | |
3105 | ||
e47c68e9 EA |
3106 | return 0; |
3107 | } | |
3108 | ||
e4ffd173 CW |
3109 | int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj, |
3110 | enum i915_cache_level cache_level) | |
3111 | { | |
7bddb01f DV |
3112 | struct drm_device *dev = obj->base.dev; |
3113 | drm_i915_private_t *dev_priv = dev->dev_private; | |
e4ffd173 CW |
3114 | int ret; |
3115 | ||
3116 | if (obj->cache_level == cache_level) | |
3117 | return 0; | |
3118 | ||
3119 | if (obj->pin_count) { | |
3120 | DRM_DEBUG("can not change the cache level of pinned objects\n"); | |
3121 | return -EBUSY; | |
3122 | } | |
3123 | ||
42d6ab48 CW |
3124 | if (!i915_gem_valid_gtt_space(dev, obj->gtt_space, cache_level)) { |
3125 | ret = i915_gem_object_unbind(obj); | |
3126 | if (ret) | |
3127 | return ret; | |
3128 | } | |
3129 | ||
e4ffd173 CW |
3130 | if (obj->gtt_space) { |
3131 | ret = i915_gem_object_finish_gpu(obj); | |
3132 | if (ret) | |
3133 | return ret; | |
3134 | ||
3135 | i915_gem_object_finish_gtt(obj); | |
3136 | ||
3137 | /* Before SandyBridge, you could not use tiling or fence | |
3138 | * registers with snooped memory, so relinquish any fences | |
3139 | * currently pointing to our region in the aperture. | |
3140 | */ | |
42d6ab48 | 3141 | if (INTEL_INFO(dev)->gen < 6) { |
e4ffd173 CW |
3142 | ret = i915_gem_object_put_fence(obj); |
3143 | if (ret) | |
3144 | return ret; | |
3145 | } | |
3146 | ||
74898d7e DV |
3147 | if (obj->has_global_gtt_mapping) |
3148 | i915_gem_gtt_bind_object(obj, cache_level); | |
7bddb01f DV |
3149 | if (obj->has_aliasing_ppgtt_mapping) |
3150 | i915_ppgtt_bind_object(dev_priv->mm.aliasing_ppgtt, | |
3151 | obj, cache_level); | |
42d6ab48 CW |
3152 | |
3153 | obj->gtt_space->color = cache_level; | |
e4ffd173 CW |
3154 | } |
3155 | ||
3156 | if (cache_level == I915_CACHE_NONE) { | |
3157 | u32 old_read_domains, old_write_domain; | |
3158 | ||
3159 | /* If we're coming from LLC cached, then we haven't | |
3160 | * actually been tracking whether the data is in the | |
3161 | * CPU cache or not, since we only allow one bit set | |
3162 | * in obj->write_domain and have been skipping the clflushes. | |
3163 | * Just set it to the CPU cache for now. | |
3164 | */ | |
3165 | WARN_ON(obj->base.write_domain & ~I915_GEM_DOMAIN_CPU); | |
3166 | WARN_ON(obj->base.read_domains & ~I915_GEM_DOMAIN_CPU); | |
3167 | ||
3168 | old_read_domains = obj->base.read_domains; | |
3169 | old_write_domain = obj->base.write_domain; | |
3170 | ||
3171 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; | |
3172 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; | |
3173 | ||
3174 | trace_i915_gem_object_change_domain(obj, | |
3175 | old_read_domains, | |
3176 | old_write_domain); | |
3177 | } | |
3178 | ||
3179 | obj->cache_level = cache_level; | |
42d6ab48 | 3180 | i915_gem_verify_gtt(dev); |
e4ffd173 CW |
3181 | return 0; |
3182 | } | |
3183 | ||
199adf40 BW |
3184 | int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data, |
3185 | struct drm_file *file) | |
e6994aee | 3186 | { |
199adf40 | 3187 | struct drm_i915_gem_caching *args = data; |
e6994aee CW |
3188 | struct drm_i915_gem_object *obj; |
3189 | int ret; | |
3190 | ||
3191 | ret = i915_mutex_lock_interruptible(dev); | |
3192 | if (ret) | |
3193 | return ret; | |
3194 | ||
3195 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); | |
3196 | if (&obj->base == NULL) { | |
3197 | ret = -ENOENT; | |
3198 | goto unlock; | |
3199 | } | |
3200 | ||
199adf40 | 3201 | args->caching = obj->cache_level != I915_CACHE_NONE; |
e6994aee CW |
3202 | |
3203 | drm_gem_object_unreference(&obj->base); | |
3204 | unlock: | |
3205 | mutex_unlock(&dev->struct_mutex); | |
3206 | return ret; | |
3207 | } | |
3208 | ||
199adf40 BW |
3209 | int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data, |
3210 | struct drm_file *file) | |
e6994aee | 3211 | { |
199adf40 | 3212 | struct drm_i915_gem_caching *args = data; |
e6994aee CW |
3213 | struct drm_i915_gem_object *obj; |
3214 | enum i915_cache_level level; | |
3215 | int ret; | |
3216 | ||
199adf40 BW |
3217 | switch (args->caching) { |
3218 | case I915_CACHING_NONE: | |
e6994aee CW |
3219 | level = I915_CACHE_NONE; |
3220 | break; | |
199adf40 | 3221 | case I915_CACHING_CACHED: |
e6994aee CW |
3222 | level = I915_CACHE_LLC; |
3223 | break; | |
3224 | default: | |
3225 | return -EINVAL; | |
3226 | } | |
3227 | ||
3bc2913e BW |
3228 | ret = i915_mutex_lock_interruptible(dev); |
3229 | if (ret) | |
3230 | return ret; | |
3231 | ||
e6994aee CW |
3232 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
3233 | if (&obj->base == NULL) { | |
3234 | ret = -ENOENT; | |
3235 | goto unlock; | |
3236 | } | |
3237 | ||
3238 | ret = i915_gem_object_set_cache_level(obj, level); | |
3239 | ||
3240 | drm_gem_object_unreference(&obj->base); | |
3241 | unlock: | |
3242 | mutex_unlock(&dev->struct_mutex); | |
3243 | return ret; | |
3244 | } | |
3245 | ||
b9241ea3 | 3246 | /* |
2da3b9b9 CW |
3247 | * Prepare buffer for display plane (scanout, cursors, etc). |
3248 | * Can be called from an uninterruptible phase (modesetting) and allows | |
3249 | * any flushes to be pipelined (for pageflips). | |
b9241ea3 ZW |
3250 | */ |
3251 | int | |
2da3b9b9 CW |
3252 | i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj, |
3253 | u32 alignment, | |
919926ae | 3254 | struct intel_ring_buffer *pipelined) |
b9241ea3 | 3255 | { |
2da3b9b9 | 3256 | u32 old_read_domains, old_write_domain; |
b9241ea3 ZW |
3257 | int ret; |
3258 | ||
0be73284 | 3259 | if (pipelined != obj->ring) { |
2911a35b BW |
3260 | ret = i915_gem_object_sync(obj, pipelined); |
3261 | if (ret) | |
b9241ea3 ZW |
3262 | return ret; |
3263 | } | |
3264 | ||
a7ef0640 EA |
3265 | /* The display engine is not coherent with the LLC cache on gen6. As |
3266 | * a result, we make sure that the pinning that is about to occur is | |
3267 | * done with uncached PTEs. This is lowest common denominator for all | |
3268 | * chipsets. | |
3269 | * | |
3270 | * However for gen6+, we could do better by using the GFDT bit instead | |
3271 | * of uncaching, which would allow us to flush all the LLC-cached data | |
3272 | * with that bit in the PTE to main memory with just one PIPE_CONTROL. | |
3273 | */ | |
3274 | ret = i915_gem_object_set_cache_level(obj, I915_CACHE_NONE); | |
3275 | if (ret) | |
3276 | return ret; | |
3277 | ||
2da3b9b9 CW |
3278 | /* As the user may map the buffer once pinned in the display plane |
3279 | * (e.g. libkms for the bootup splash), we have to ensure that we | |
3280 | * always use map_and_fenceable for all scanout buffers. | |
3281 | */ | |
86a1ee26 | 3282 | ret = i915_gem_object_pin(obj, alignment, true, false); |
2da3b9b9 CW |
3283 | if (ret) |
3284 | return ret; | |
3285 | ||
b118c1e3 CW |
3286 | i915_gem_object_flush_cpu_write_domain(obj); |
3287 | ||
2da3b9b9 | 3288 | old_write_domain = obj->base.write_domain; |
05394f39 | 3289 | old_read_domains = obj->base.read_domains; |
2da3b9b9 CW |
3290 | |
3291 | /* It should now be out of any other write domains, and we can update | |
3292 | * the domain values for our changes. | |
3293 | */ | |
e5f1d962 | 3294 | obj->base.write_domain = 0; |
05394f39 | 3295 | obj->base.read_domains |= I915_GEM_DOMAIN_GTT; |
b9241ea3 ZW |
3296 | |
3297 | trace_i915_gem_object_change_domain(obj, | |
3298 | old_read_domains, | |
2da3b9b9 | 3299 | old_write_domain); |
b9241ea3 ZW |
3300 | |
3301 | return 0; | |
3302 | } | |
3303 | ||
85345517 | 3304 | int |
a8198eea | 3305 | i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj) |
85345517 | 3306 | { |
88241785 CW |
3307 | int ret; |
3308 | ||
a8198eea | 3309 | if ((obj->base.read_domains & I915_GEM_GPU_DOMAINS) == 0) |
85345517 CW |
3310 | return 0; |
3311 | ||
0201f1ec | 3312 | ret = i915_gem_object_wait_rendering(obj, false); |
c501ae7f CW |
3313 | if (ret) |
3314 | return ret; | |
3315 | ||
a8198eea CW |
3316 | /* Ensure that we invalidate the GPU's caches and TLBs. */ |
3317 | obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS; | |
c501ae7f | 3318 | return 0; |
85345517 CW |
3319 | } |
3320 | ||
e47c68e9 EA |
3321 | /** |
3322 | * Moves a single object to the CPU read, and possibly write domain. | |
3323 | * | |
3324 | * This function returns when the move is complete, including waiting on | |
3325 | * flushes to occur. | |
3326 | */ | |
dabdfe02 | 3327 | int |
919926ae | 3328 | i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write) |
e47c68e9 | 3329 | { |
1c5d22f7 | 3330 | uint32_t old_write_domain, old_read_domains; |
e47c68e9 EA |
3331 | int ret; |
3332 | ||
8d7e3de1 CW |
3333 | if (obj->base.write_domain == I915_GEM_DOMAIN_CPU) |
3334 | return 0; | |
3335 | ||
0201f1ec | 3336 | ret = i915_gem_object_wait_rendering(obj, !write); |
88241785 CW |
3337 | if (ret) |
3338 | return ret; | |
3339 | ||
e47c68e9 | 3340 | i915_gem_object_flush_gtt_write_domain(obj); |
2ef7eeaa | 3341 | |
05394f39 CW |
3342 | old_write_domain = obj->base.write_domain; |
3343 | old_read_domains = obj->base.read_domains; | |
1c5d22f7 | 3344 | |
e47c68e9 | 3345 | /* Flush the CPU cache if it's still invalid. */ |
05394f39 | 3346 | if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) { |
2ef7eeaa | 3347 | i915_gem_clflush_object(obj); |
2ef7eeaa | 3348 | |
05394f39 | 3349 | obj->base.read_domains |= I915_GEM_DOMAIN_CPU; |
2ef7eeaa EA |
3350 | } |
3351 | ||
3352 | /* It should now be out of any other write domains, and we can update | |
3353 | * the domain values for our changes. | |
3354 | */ | |
05394f39 | 3355 | BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) != 0); |
e47c68e9 EA |
3356 | |
3357 | /* If we're writing through the CPU, then the GPU read domains will | |
3358 | * need to be invalidated at next use. | |
3359 | */ | |
3360 | if (write) { | |
05394f39 CW |
3361 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; |
3362 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; | |
e47c68e9 | 3363 | } |
2ef7eeaa | 3364 | |
1c5d22f7 CW |
3365 | trace_i915_gem_object_change_domain(obj, |
3366 | old_read_domains, | |
3367 | old_write_domain); | |
3368 | ||
2ef7eeaa EA |
3369 | return 0; |
3370 | } | |
3371 | ||
673a394b EA |
3372 | /* Throttle our rendering by waiting until the ring has completed our requests |
3373 | * emitted over 20 msec ago. | |
3374 | * | |
b962442e EA |
3375 | * Note that if we were to use the current jiffies each time around the loop, |
3376 | * we wouldn't escape the function with any frames outstanding if the time to | |
3377 | * render a frame was over 20ms. | |
3378 | * | |
673a394b EA |
3379 | * This should get us reasonable parallelism between CPU and GPU but also |
3380 | * relatively low latency when blocking on a particular request to finish. | |
3381 | */ | |
40a5f0de | 3382 | static int |
f787a5f5 | 3383 | i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file) |
40a5f0de | 3384 | { |
f787a5f5 CW |
3385 | struct drm_i915_private *dev_priv = dev->dev_private; |
3386 | struct drm_i915_file_private *file_priv = file->driver_priv; | |
b962442e | 3387 | unsigned long recent_enough = jiffies - msecs_to_jiffies(20); |
f787a5f5 CW |
3388 | struct drm_i915_gem_request *request; |
3389 | struct intel_ring_buffer *ring = NULL; | |
3390 | u32 seqno = 0; | |
3391 | int ret; | |
93533c29 | 3392 | |
308887aa DV |
3393 | ret = i915_gem_wait_for_error(&dev_priv->gpu_error); |
3394 | if (ret) | |
3395 | return ret; | |
3396 | ||
3397 | ret = i915_gem_check_wedge(&dev_priv->gpu_error, false); | |
3398 | if (ret) | |
3399 | return ret; | |
e110e8d6 | 3400 | |
1c25595f | 3401 | spin_lock(&file_priv->mm.lock); |
f787a5f5 | 3402 | list_for_each_entry(request, &file_priv->mm.request_list, client_list) { |
b962442e EA |
3403 | if (time_after_eq(request->emitted_jiffies, recent_enough)) |
3404 | break; | |
40a5f0de | 3405 | |
f787a5f5 CW |
3406 | ring = request->ring; |
3407 | seqno = request->seqno; | |
b962442e | 3408 | } |
1c25595f | 3409 | spin_unlock(&file_priv->mm.lock); |
40a5f0de | 3410 | |
f787a5f5 CW |
3411 | if (seqno == 0) |
3412 | return 0; | |
2bc43b5c | 3413 | |
5c81fe85 | 3414 | ret = __wait_seqno(ring, seqno, true, NULL); |
f787a5f5 CW |
3415 | if (ret == 0) |
3416 | queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, 0); | |
40a5f0de EA |
3417 | |
3418 | return ret; | |
3419 | } | |
3420 | ||
673a394b | 3421 | int |
05394f39 CW |
3422 | i915_gem_object_pin(struct drm_i915_gem_object *obj, |
3423 | uint32_t alignment, | |
86a1ee26 CW |
3424 | bool map_and_fenceable, |
3425 | bool nonblocking) | |
673a394b | 3426 | { |
673a394b EA |
3427 | int ret; |
3428 | ||
7e81a42e CW |
3429 | if (WARN_ON(obj->pin_count == DRM_I915_GEM_OBJECT_MAX_PIN_COUNT)) |
3430 | return -EBUSY; | |
ac0c6b5a | 3431 | |
05394f39 CW |
3432 | if (obj->gtt_space != NULL) { |
3433 | if ((alignment && obj->gtt_offset & (alignment - 1)) || | |
3434 | (map_and_fenceable && !obj->map_and_fenceable)) { | |
3435 | WARN(obj->pin_count, | |
ae7d49d8 | 3436 | "bo is already pinned with incorrect alignment:" |
75e9e915 DV |
3437 | " offset=%x, req.alignment=%x, req.map_and_fenceable=%d," |
3438 | " obj->map_and_fenceable=%d\n", | |
05394f39 | 3439 | obj->gtt_offset, alignment, |
75e9e915 | 3440 | map_and_fenceable, |
05394f39 | 3441 | obj->map_and_fenceable); |
ac0c6b5a CW |
3442 | ret = i915_gem_object_unbind(obj); |
3443 | if (ret) | |
3444 | return ret; | |
3445 | } | |
3446 | } | |
3447 | ||
05394f39 | 3448 | if (obj->gtt_space == NULL) { |
8742267a CW |
3449 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
3450 | ||
a00b10c3 | 3451 | ret = i915_gem_object_bind_to_gtt(obj, alignment, |
86a1ee26 CW |
3452 | map_and_fenceable, |
3453 | nonblocking); | |
9731129c | 3454 | if (ret) |
673a394b | 3455 | return ret; |
8742267a CW |
3456 | |
3457 | if (!dev_priv->mm.aliasing_ppgtt) | |
3458 | i915_gem_gtt_bind_object(obj, obj->cache_level); | |
22c344e9 | 3459 | } |
76446cac | 3460 | |
74898d7e DV |
3461 | if (!obj->has_global_gtt_mapping && map_and_fenceable) |
3462 | i915_gem_gtt_bind_object(obj, obj->cache_level); | |
3463 | ||
1b50247a | 3464 | obj->pin_count++; |
6299f992 | 3465 | obj->pin_mappable |= map_and_fenceable; |
673a394b EA |
3466 | |
3467 | return 0; | |
3468 | } | |
3469 | ||
3470 | void | |
05394f39 | 3471 | i915_gem_object_unpin(struct drm_i915_gem_object *obj) |
673a394b | 3472 | { |
05394f39 CW |
3473 | BUG_ON(obj->pin_count == 0); |
3474 | BUG_ON(obj->gtt_space == NULL); | |
673a394b | 3475 | |
1b50247a | 3476 | if (--obj->pin_count == 0) |
6299f992 | 3477 | obj->pin_mappable = false; |
673a394b EA |
3478 | } |
3479 | ||
3480 | int | |
3481 | i915_gem_pin_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 3482 | struct drm_file *file) |
673a394b EA |
3483 | { |
3484 | struct drm_i915_gem_pin *args = data; | |
05394f39 | 3485 | struct drm_i915_gem_object *obj; |
673a394b EA |
3486 | int ret; |
3487 | ||
1d7cfea1 CW |
3488 | ret = i915_mutex_lock_interruptible(dev); |
3489 | if (ret) | |
3490 | return ret; | |
673a394b | 3491 | |
05394f39 | 3492 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 3493 | if (&obj->base == NULL) { |
1d7cfea1 CW |
3494 | ret = -ENOENT; |
3495 | goto unlock; | |
673a394b | 3496 | } |
673a394b | 3497 | |
05394f39 | 3498 | if (obj->madv != I915_MADV_WILLNEED) { |
bb6baf76 | 3499 | DRM_ERROR("Attempting to pin a purgeable buffer\n"); |
1d7cfea1 CW |
3500 | ret = -EINVAL; |
3501 | goto out; | |
3ef94daa CW |
3502 | } |
3503 | ||
05394f39 | 3504 | if (obj->pin_filp != NULL && obj->pin_filp != file) { |
79e53945 JB |
3505 | DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n", |
3506 | args->handle); | |
1d7cfea1 CW |
3507 | ret = -EINVAL; |
3508 | goto out; | |
79e53945 JB |
3509 | } |
3510 | ||
05394f39 CW |
3511 | obj->user_pin_count++; |
3512 | obj->pin_filp = file; | |
3513 | if (obj->user_pin_count == 1) { | |
86a1ee26 | 3514 | ret = i915_gem_object_pin(obj, args->alignment, true, false); |
1d7cfea1 CW |
3515 | if (ret) |
3516 | goto out; | |
673a394b EA |
3517 | } |
3518 | ||
3519 | /* XXX - flush the CPU caches for pinned objects | |
3520 | * as the X server doesn't manage domains yet | |
3521 | */ | |
e47c68e9 | 3522 | i915_gem_object_flush_cpu_write_domain(obj); |
05394f39 | 3523 | args->offset = obj->gtt_offset; |
1d7cfea1 | 3524 | out: |
05394f39 | 3525 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 3526 | unlock: |
673a394b | 3527 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 3528 | return ret; |
673a394b EA |
3529 | } |
3530 | ||
3531 | int | |
3532 | i915_gem_unpin_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 3533 | struct drm_file *file) |
673a394b EA |
3534 | { |
3535 | struct drm_i915_gem_pin *args = data; | |
05394f39 | 3536 | struct drm_i915_gem_object *obj; |
76c1dec1 | 3537 | int ret; |
673a394b | 3538 | |
1d7cfea1 CW |
3539 | ret = i915_mutex_lock_interruptible(dev); |
3540 | if (ret) | |
3541 | return ret; | |
673a394b | 3542 | |
05394f39 | 3543 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 3544 | if (&obj->base == NULL) { |
1d7cfea1 CW |
3545 | ret = -ENOENT; |
3546 | goto unlock; | |
673a394b | 3547 | } |
76c1dec1 | 3548 | |
05394f39 | 3549 | if (obj->pin_filp != file) { |
79e53945 JB |
3550 | DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n", |
3551 | args->handle); | |
1d7cfea1 CW |
3552 | ret = -EINVAL; |
3553 | goto out; | |
79e53945 | 3554 | } |
05394f39 CW |
3555 | obj->user_pin_count--; |
3556 | if (obj->user_pin_count == 0) { | |
3557 | obj->pin_filp = NULL; | |
79e53945 JB |
3558 | i915_gem_object_unpin(obj); |
3559 | } | |
673a394b | 3560 | |
1d7cfea1 | 3561 | out: |
05394f39 | 3562 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 3563 | unlock: |
673a394b | 3564 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 3565 | return ret; |
673a394b EA |
3566 | } |
3567 | ||
3568 | int | |
3569 | i915_gem_busy_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 3570 | struct drm_file *file) |
673a394b EA |
3571 | { |
3572 | struct drm_i915_gem_busy *args = data; | |
05394f39 | 3573 | struct drm_i915_gem_object *obj; |
30dbf0c0 CW |
3574 | int ret; |
3575 | ||
76c1dec1 | 3576 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 3577 | if (ret) |
76c1dec1 | 3578 | return ret; |
673a394b | 3579 | |
05394f39 | 3580 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 3581 | if (&obj->base == NULL) { |
1d7cfea1 CW |
3582 | ret = -ENOENT; |
3583 | goto unlock; | |
673a394b | 3584 | } |
d1b851fc | 3585 | |
0be555b6 CW |
3586 | /* Count all active objects as busy, even if they are currently not used |
3587 | * by the gpu. Users of this interface expect objects to eventually | |
3588 | * become non-busy without any further actions, therefore emit any | |
3589 | * necessary flushes here. | |
c4de0a5d | 3590 | */ |
30dfebf3 | 3591 | ret = i915_gem_object_flush_active(obj); |
0be555b6 | 3592 | |
30dfebf3 | 3593 | args->busy = obj->active; |
e9808edd CW |
3594 | if (obj->ring) { |
3595 | BUILD_BUG_ON(I915_NUM_RINGS > 16); | |
3596 | args->busy |= intel_ring_flag(obj->ring) << 16; | |
3597 | } | |
673a394b | 3598 | |
05394f39 | 3599 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 3600 | unlock: |
673a394b | 3601 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 3602 | return ret; |
673a394b EA |
3603 | } |
3604 | ||
3605 | int | |
3606 | i915_gem_throttle_ioctl(struct drm_device *dev, void *data, | |
3607 | struct drm_file *file_priv) | |
3608 | { | |
0206e353 | 3609 | return i915_gem_ring_throttle(dev, file_priv); |
673a394b EA |
3610 | } |
3611 | ||
3ef94daa CW |
3612 | int |
3613 | i915_gem_madvise_ioctl(struct drm_device *dev, void *data, | |
3614 | struct drm_file *file_priv) | |
3615 | { | |
3616 | struct drm_i915_gem_madvise *args = data; | |
05394f39 | 3617 | struct drm_i915_gem_object *obj; |
76c1dec1 | 3618 | int ret; |
3ef94daa CW |
3619 | |
3620 | switch (args->madv) { | |
3621 | case I915_MADV_DONTNEED: | |
3622 | case I915_MADV_WILLNEED: | |
3623 | break; | |
3624 | default: | |
3625 | return -EINVAL; | |
3626 | } | |
3627 | ||
1d7cfea1 CW |
3628 | ret = i915_mutex_lock_interruptible(dev); |
3629 | if (ret) | |
3630 | return ret; | |
3631 | ||
05394f39 | 3632 | obj = to_intel_bo(drm_gem_object_lookup(dev, file_priv, args->handle)); |
c8725226 | 3633 | if (&obj->base == NULL) { |
1d7cfea1 CW |
3634 | ret = -ENOENT; |
3635 | goto unlock; | |
3ef94daa | 3636 | } |
3ef94daa | 3637 | |
05394f39 | 3638 | if (obj->pin_count) { |
1d7cfea1 CW |
3639 | ret = -EINVAL; |
3640 | goto out; | |
3ef94daa CW |
3641 | } |
3642 | ||
05394f39 CW |
3643 | if (obj->madv != __I915_MADV_PURGED) |
3644 | obj->madv = args->madv; | |
3ef94daa | 3645 | |
6c085a72 CW |
3646 | /* if the object is no longer attached, discard its backing storage */ |
3647 | if (i915_gem_object_is_purgeable(obj) && obj->pages == NULL) | |
2d7ef395 CW |
3648 | i915_gem_object_truncate(obj); |
3649 | ||
05394f39 | 3650 | args->retained = obj->madv != __I915_MADV_PURGED; |
bb6baf76 | 3651 | |
1d7cfea1 | 3652 | out: |
05394f39 | 3653 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 3654 | unlock: |
3ef94daa | 3655 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 3656 | return ret; |
3ef94daa CW |
3657 | } |
3658 | ||
37e680a1 CW |
3659 | void i915_gem_object_init(struct drm_i915_gem_object *obj, |
3660 | const struct drm_i915_gem_object_ops *ops) | |
0327d6ba | 3661 | { |
0327d6ba CW |
3662 | INIT_LIST_HEAD(&obj->mm_list); |
3663 | INIT_LIST_HEAD(&obj->gtt_list); | |
3664 | INIT_LIST_HEAD(&obj->ring_list); | |
3665 | INIT_LIST_HEAD(&obj->exec_list); | |
3666 | ||
37e680a1 CW |
3667 | obj->ops = ops; |
3668 | ||
0327d6ba CW |
3669 | obj->fence_reg = I915_FENCE_REG_NONE; |
3670 | obj->madv = I915_MADV_WILLNEED; | |
3671 | /* Avoid an unnecessary call to unbind on the first bind. */ | |
3672 | obj->map_and_fenceable = true; | |
3673 | ||
3674 | i915_gem_info_add_obj(obj->base.dev->dev_private, obj->base.size); | |
3675 | } | |
3676 | ||
37e680a1 CW |
3677 | static const struct drm_i915_gem_object_ops i915_gem_object_ops = { |
3678 | .get_pages = i915_gem_object_get_pages_gtt, | |
3679 | .put_pages = i915_gem_object_put_pages_gtt, | |
3680 | }; | |
3681 | ||
05394f39 CW |
3682 | struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev, |
3683 | size_t size) | |
ac52bc56 | 3684 | { |
c397b908 | 3685 | struct drm_i915_gem_object *obj; |
5949eac4 | 3686 | struct address_space *mapping; |
1a240d4d | 3687 | gfp_t mask; |
ac52bc56 | 3688 | |
42dcedd4 | 3689 | obj = i915_gem_object_alloc(dev); |
c397b908 DV |
3690 | if (obj == NULL) |
3691 | return NULL; | |
673a394b | 3692 | |
c397b908 | 3693 | if (drm_gem_object_init(dev, &obj->base, size) != 0) { |
42dcedd4 | 3694 | i915_gem_object_free(obj); |
c397b908 DV |
3695 | return NULL; |
3696 | } | |
673a394b | 3697 | |
bed1ea95 CW |
3698 | mask = GFP_HIGHUSER | __GFP_RECLAIMABLE; |
3699 | if (IS_CRESTLINE(dev) || IS_BROADWATER(dev)) { | |
3700 | /* 965gm cannot relocate objects above 4GiB. */ | |
3701 | mask &= ~__GFP_HIGHMEM; | |
3702 | mask |= __GFP_DMA32; | |
3703 | } | |
3704 | ||
5949eac4 | 3705 | mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping; |
bed1ea95 | 3706 | mapping_set_gfp_mask(mapping, mask); |
5949eac4 | 3707 | |
37e680a1 | 3708 | i915_gem_object_init(obj, &i915_gem_object_ops); |
73aa808f | 3709 | |
c397b908 DV |
3710 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; |
3711 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; | |
673a394b | 3712 | |
3d29b842 ED |
3713 | if (HAS_LLC(dev)) { |
3714 | /* On some devices, we can have the GPU use the LLC (the CPU | |
a1871112 EA |
3715 | * cache) for about a 10% performance improvement |
3716 | * compared to uncached. Graphics requests other than | |
3717 | * display scanout are coherent with the CPU in | |
3718 | * accessing this cache. This means in this mode we | |
3719 | * don't need to clflush on the CPU side, and on the | |
3720 | * GPU side we only need to flush internal caches to | |
3721 | * get data visible to the CPU. | |
3722 | * | |
3723 | * However, we maintain the display planes as UC, and so | |
3724 | * need to rebind when first used as such. | |
3725 | */ | |
3726 | obj->cache_level = I915_CACHE_LLC; | |
3727 | } else | |
3728 | obj->cache_level = I915_CACHE_NONE; | |
3729 | ||
05394f39 | 3730 | return obj; |
c397b908 DV |
3731 | } |
3732 | ||
3733 | int i915_gem_init_object(struct drm_gem_object *obj) | |
3734 | { | |
3735 | BUG(); | |
de151cf6 | 3736 | |
673a394b EA |
3737 | return 0; |
3738 | } | |
3739 | ||
1488fc08 | 3740 | void i915_gem_free_object(struct drm_gem_object *gem_obj) |
673a394b | 3741 | { |
1488fc08 | 3742 | struct drm_i915_gem_object *obj = to_intel_bo(gem_obj); |
05394f39 | 3743 | struct drm_device *dev = obj->base.dev; |
be72615b | 3744 | drm_i915_private_t *dev_priv = dev->dev_private; |
673a394b | 3745 | |
26e12f89 CW |
3746 | trace_i915_gem_object_destroy(obj); |
3747 | ||
1488fc08 CW |
3748 | if (obj->phys_obj) |
3749 | i915_gem_detach_phys_object(dev, obj); | |
3750 | ||
3751 | obj->pin_count = 0; | |
3752 | if (WARN_ON(i915_gem_object_unbind(obj) == -ERESTARTSYS)) { | |
3753 | bool was_interruptible; | |
3754 | ||
3755 | was_interruptible = dev_priv->mm.interruptible; | |
3756 | dev_priv->mm.interruptible = false; | |
3757 | ||
3758 | WARN_ON(i915_gem_object_unbind(obj)); | |
3759 | ||
3760 | dev_priv->mm.interruptible = was_interruptible; | |
3761 | } | |
3762 | ||
a5570178 | 3763 | obj->pages_pin_count = 0; |
37e680a1 | 3764 | i915_gem_object_put_pages(obj); |
d8cb5086 | 3765 | i915_gem_object_free_mmap_offset(obj); |
0104fdbb | 3766 | i915_gem_object_release_stolen(obj); |
de151cf6 | 3767 | |
9da3da66 CW |
3768 | BUG_ON(obj->pages); |
3769 | ||
2f745ad3 CW |
3770 | if (obj->base.import_attach) |
3771 | drm_prime_gem_destroy(&obj->base, NULL); | |
de151cf6 | 3772 | |
05394f39 CW |
3773 | drm_gem_object_release(&obj->base); |
3774 | i915_gem_info_remove_obj(dev_priv, obj->base.size); | |
c397b908 | 3775 | |
05394f39 | 3776 | kfree(obj->bit_17); |
42dcedd4 | 3777 | i915_gem_object_free(obj); |
673a394b EA |
3778 | } |
3779 | ||
29105ccc CW |
3780 | int |
3781 | i915_gem_idle(struct drm_device *dev) | |
3782 | { | |
3783 | drm_i915_private_t *dev_priv = dev->dev_private; | |
3784 | int ret; | |
28dfe52a | 3785 | |
29105ccc | 3786 | mutex_lock(&dev->struct_mutex); |
1c5d22f7 | 3787 | |
87acb0a5 | 3788 | if (dev_priv->mm.suspended) { |
29105ccc CW |
3789 | mutex_unlock(&dev->struct_mutex); |
3790 | return 0; | |
28dfe52a EA |
3791 | } |
3792 | ||
b2da9fe5 | 3793 | ret = i915_gpu_idle(dev); |
6dbe2772 KP |
3794 | if (ret) { |
3795 | mutex_unlock(&dev->struct_mutex); | |
673a394b | 3796 | return ret; |
6dbe2772 | 3797 | } |
b2da9fe5 | 3798 | i915_gem_retire_requests(dev); |
673a394b | 3799 | |
29105ccc | 3800 | /* Under UMS, be paranoid and evict. */ |
a39d7efc | 3801 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) |
6c085a72 | 3802 | i915_gem_evict_everything(dev); |
29105ccc | 3803 | |
312817a3 CW |
3804 | i915_gem_reset_fences(dev); |
3805 | ||
29105ccc CW |
3806 | /* Hack! Don't let anybody do execbuf while we don't control the chip. |
3807 | * We need to replace this with a semaphore, or something. | |
3808 | * And not confound mm.suspended! | |
3809 | */ | |
3810 | dev_priv->mm.suspended = 1; | |
99584db3 | 3811 | del_timer_sync(&dev_priv->gpu_error.hangcheck_timer); |
29105ccc CW |
3812 | |
3813 | i915_kernel_lost_context(dev); | |
6dbe2772 | 3814 | i915_gem_cleanup_ringbuffer(dev); |
29105ccc | 3815 | |
6dbe2772 KP |
3816 | mutex_unlock(&dev->struct_mutex); |
3817 | ||
29105ccc CW |
3818 | /* Cancel the retire work handler, which should be idle now. */ |
3819 | cancel_delayed_work_sync(&dev_priv->mm.retire_work); | |
3820 | ||
673a394b EA |
3821 | return 0; |
3822 | } | |
3823 | ||
b9524a1e BW |
3824 | void i915_gem_l3_remap(struct drm_device *dev) |
3825 | { | |
3826 | drm_i915_private_t *dev_priv = dev->dev_private; | |
3827 | u32 misccpctl; | |
3828 | int i; | |
3829 | ||
3830 | if (!IS_IVYBRIDGE(dev)) | |
3831 | return; | |
3832 | ||
a4da4fa4 | 3833 | if (!dev_priv->l3_parity.remap_info) |
b9524a1e BW |
3834 | return; |
3835 | ||
3836 | misccpctl = I915_READ(GEN7_MISCCPCTL); | |
3837 | I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE); | |
3838 | POSTING_READ(GEN7_MISCCPCTL); | |
3839 | ||
3840 | for (i = 0; i < GEN7_L3LOG_SIZE; i += 4) { | |
3841 | u32 remap = I915_READ(GEN7_L3LOG_BASE + i); | |
a4da4fa4 | 3842 | if (remap && remap != dev_priv->l3_parity.remap_info[i/4]) |
b9524a1e BW |
3843 | DRM_DEBUG("0x%x was already programmed to %x\n", |
3844 | GEN7_L3LOG_BASE + i, remap); | |
a4da4fa4 | 3845 | if (remap && !dev_priv->l3_parity.remap_info[i/4]) |
b9524a1e | 3846 | DRM_DEBUG_DRIVER("Clearing remapped register\n"); |
a4da4fa4 | 3847 | I915_WRITE(GEN7_L3LOG_BASE + i, dev_priv->l3_parity.remap_info[i/4]); |
b9524a1e BW |
3848 | } |
3849 | ||
3850 | /* Make sure all the writes land before disabling dop clock gating */ | |
3851 | POSTING_READ(GEN7_L3LOG_BASE); | |
3852 | ||
3853 | I915_WRITE(GEN7_MISCCPCTL, misccpctl); | |
3854 | } | |
3855 | ||
f691e2f4 DV |
3856 | void i915_gem_init_swizzling(struct drm_device *dev) |
3857 | { | |
3858 | drm_i915_private_t *dev_priv = dev->dev_private; | |
3859 | ||
11782b02 | 3860 | if (INTEL_INFO(dev)->gen < 5 || |
f691e2f4 DV |
3861 | dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE) |
3862 | return; | |
3863 | ||
3864 | I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) | | |
3865 | DISP_TILE_SURFACE_SWIZZLING); | |
3866 | ||
11782b02 DV |
3867 | if (IS_GEN5(dev)) |
3868 | return; | |
3869 | ||
f691e2f4 DV |
3870 | I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_SWZCTL); |
3871 | if (IS_GEN6(dev)) | |
6b26c86d | 3872 | I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB)); |
8782e26c | 3873 | else if (IS_GEN7(dev)) |
6b26c86d | 3874 | I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB)); |
8782e26c BW |
3875 | else |
3876 | BUG(); | |
f691e2f4 | 3877 | } |
e21af88d | 3878 | |
67b1b571 CW |
3879 | static bool |
3880 | intel_enable_blt(struct drm_device *dev) | |
3881 | { | |
3882 | if (!HAS_BLT(dev)) | |
3883 | return false; | |
3884 | ||
3885 | /* The blitter was dysfunctional on early prototypes */ | |
3886 | if (IS_GEN6(dev) && dev->pdev->revision < 8) { | |
3887 | DRM_INFO("BLT not supported on this pre-production hardware;" | |
3888 | " graphics performance will be degraded.\n"); | |
3889 | return false; | |
3890 | } | |
3891 | ||
3892 | return true; | |
3893 | } | |
3894 | ||
8187a2b7 | 3895 | int |
f691e2f4 | 3896 | i915_gem_init_hw(struct drm_device *dev) |
8187a2b7 ZN |
3897 | { |
3898 | drm_i915_private_t *dev_priv = dev->dev_private; | |
3899 | int ret; | |
68f95ba9 | 3900 | |
e76e9aeb | 3901 | if (INTEL_INFO(dev)->gen < 6 && !intel_enable_gtt()) |
8ecd1a66 DV |
3902 | return -EIO; |
3903 | ||
eda2d7f5 RV |
3904 | if (IS_HASWELL(dev) && (I915_READ(0x120010) == 1)) |
3905 | I915_WRITE(0x9008, I915_READ(0x9008) | 0xf0000); | |
3906 | ||
b9524a1e BW |
3907 | i915_gem_l3_remap(dev); |
3908 | ||
f691e2f4 DV |
3909 | i915_gem_init_swizzling(dev); |
3910 | ||
f7e98ad4 MK |
3911 | dev_priv->next_seqno = dev_priv->last_seqno = (u32)~0 - 0x1000; |
3912 | ||
5c1143bb | 3913 | ret = intel_init_render_ring_buffer(dev); |
68f95ba9 | 3914 | if (ret) |
b6913e4b | 3915 | return ret; |
68f95ba9 CW |
3916 | |
3917 | if (HAS_BSD(dev)) { | |
5c1143bb | 3918 | ret = intel_init_bsd_ring_buffer(dev); |
68f95ba9 CW |
3919 | if (ret) |
3920 | goto cleanup_render_ring; | |
d1b851fc | 3921 | } |
68f95ba9 | 3922 | |
67b1b571 | 3923 | if (intel_enable_blt(dev)) { |
549f7365 CW |
3924 | ret = intel_init_blt_ring_buffer(dev); |
3925 | if (ret) | |
3926 | goto cleanup_bsd_ring; | |
3927 | } | |
3928 | ||
254f965c BW |
3929 | /* |
3930 | * XXX: There was some w/a described somewhere suggesting loading | |
3931 | * contexts before PPGTT. | |
3932 | */ | |
3933 | i915_gem_context_init(dev); | |
e21af88d DV |
3934 | i915_gem_init_ppgtt(dev); |
3935 | ||
68f95ba9 CW |
3936 | return 0; |
3937 | ||
549f7365 | 3938 | cleanup_bsd_ring: |
1ec14ad3 | 3939 | intel_cleanup_ring_buffer(&dev_priv->ring[VCS]); |
68f95ba9 | 3940 | cleanup_render_ring: |
1ec14ad3 | 3941 | intel_cleanup_ring_buffer(&dev_priv->ring[RCS]); |
8187a2b7 ZN |
3942 | return ret; |
3943 | } | |
3944 | ||
1070a42b CW |
3945 | int i915_gem_init(struct drm_device *dev) |
3946 | { | |
3947 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1070a42b CW |
3948 | int ret; |
3949 | ||
1070a42b | 3950 | mutex_lock(&dev->struct_mutex); |
d7e5008f | 3951 | i915_gem_init_global_gtt(dev); |
1070a42b CW |
3952 | ret = i915_gem_init_hw(dev); |
3953 | mutex_unlock(&dev->struct_mutex); | |
3954 | if (ret) { | |
3955 | i915_gem_cleanup_aliasing_ppgtt(dev); | |
3956 | return ret; | |
3957 | } | |
3958 | ||
53ca26ca DV |
3959 | /* Allow hardware batchbuffers unless told otherwise, but not for KMS. */ |
3960 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) | |
3961 | dev_priv->dri1.allow_batchbuffer = 1; | |
1070a42b CW |
3962 | return 0; |
3963 | } | |
3964 | ||
8187a2b7 ZN |
3965 | void |
3966 | i915_gem_cleanup_ringbuffer(struct drm_device *dev) | |
3967 | { | |
3968 | drm_i915_private_t *dev_priv = dev->dev_private; | |
b4519513 | 3969 | struct intel_ring_buffer *ring; |
1ec14ad3 | 3970 | int i; |
8187a2b7 | 3971 | |
b4519513 CW |
3972 | for_each_ring(ring, dev_priv, i) |
3973 | intel_cleanup_ring_buffer(ring); | |
8187a2b7 ZN |
3974 | } |
3975 | ||
673a394b EA |
3976 | int |
3977 | i915_gem_entervt_ioctl(struct drm_device *dev, void *data, | |
3978 | struct drm_file *file_priv) | |
3979 | { | |
3980 | drm_i915_private_t *dev_priv = dev->dev_private; | |
b4519513 | 3981 | int ret; |
673a394b | 3982 | |
79e53945 JB |
3983 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
3984 | return 0; | |
3985 | ||
33196ded | 3986 | if (atomic_read(&dev_priv->gpu_error.wedged)) { |
673a394b | 3987 | DRM_ERROR("Reenabling wedged hardware, good luck\n"); |
33196ded | 3988 | atomic_set(&dev_priv->gpu_error.wedged, 0); |
673a394b EA |
3989 | } |
3990 | ||
673a394b | 3991 | mutex_lock(&dev->struct_mutex); |
9bb2d6f9 EA |
3992 | dev_priv->mm.suspended = 0; |
3993 | ||
f691e2f4 | 3994 | ret = i915_gem_init_hw(dev); |
d816f6ac WF |
3995 | if (ret != 0) { |
3996 | mutex_unlock(&dev->struct_mutex); | |
9bb2d6f9 | 3997 | return ret; |
d816f6ac | 3998 | } |
9bb2d6f9 | 3999 | |
69dc4987 | 4000 | BUG_ON(!list_empty(&dev_priv->mm.active_list)); |
673a394b | 4001 | mutex_unlock(&dev->struct_mutex); |
dbb19d30 | 4002 | |
5f35308b CW |
4003 | ret = drm_irq_install(dev); |
4004 | if (ret) | |
4005 | goto cleanup_ringbuffer; | |
dbb19d30 | 4006 | |
673a394b | 4007 | return 0; |
5f35308b CW |
4008 | |
4009 | cleanup_ringbuffer: | |
4010 | mutex_lock(&dev->struct_mutex); | |
4011 | i915_gem_cleanup_ringbuffer(dev); | |
4012 | dev_priv->mm.suspended = 1; | |
4013 | mutex_unlock(&dev->struct_mutex); | |
4014 | ||
4015 | return ret; | |
673a394b EA |
4016 | } |
4017 | ||
4018 | int | |
4019 | i915_gem_leavevt_ioctl(struct drm_device *dev, void *data, | |
4020 | struct drm_file *file_priv) | |
4021 | { | |
79e53945 JB |
4022 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
4023 | return 0; | |
4024 | ||
dbb19d30 | 4025 | drm_irq_uninstall(dev); |
e6890f6f | 4026 | return i915_gem_idle(dev); |
673a394b EA |
4027 | } |
4028 | ||
4029 | void | |
4030 | i915_gem_lastclose(struct drm_device *dev) | |
4031 | { | |
4032 | int ret; | |
673a394b | 4033 | |
e806b495 EA |
4034 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
4035 | return; | |
4036 | ||
6dbe2772 KP |
4037 | ret = i915_gem_idle(dev); |
4038 | if (ret) | |
4039 | DRM_ERROR("failed to idle hardware: %d\n", ret); | |
673a394b EA |
4040 | } |
4041 | ||
64193406 CW |
4042 | static void |
4043 | init_ring_lists(struct intel_ring_buffer *ring) | |
4044 | { | |
4045 | INIT_LIST_HEAD(&ring->active_list); | |
4046 | INIT_LIST_HEAD(&ring->request_list); | |
64193406 CW |
4047 | } |
4048 | ||
673a394b EA |
4049 | void |
4050 | i915_gem_load(struct drm_device *dev) | |
4051 | { | |
4052 | drm_i915_private_t *dev_priv = dev->dev_private; | |
42dcedd4 CW |
4053 | int i; |
4054 | ||
4055 | dev_priv->slab = | |
4056 | kmem_cache_create("i915_gem_object", | |
4057 | sizeof(struct drm_i915_gem_object), 0, | |
4058 | SLAB_HWCACHE_ALIGN, | |
4059 | NULL); | |
673a394b | 4060 | |
69dc4987 | 4061 | INIT_LIST_HEAD(&dev_priv->mm.active_list); |
673a394b | 4062 | INIT_LIST_HEAD(&dev_priv->mm.inactive_list); |
6c085a72 CW |
4063 | INIT_LIST_HEAD(&dev_priv->mm.unbound_list); |
4064 | INIT_LIST_HEAD(&dev_priv->mm.bound_list); | |
a09ba7fa | 4065 | INIT_LIST_HEAD(&dev_priv->mm.fence_list); |
1ec14ad3 CW |
4066 | for (i = 0; i < I915_NUM_RINGS; i++) |
4067 | init_ring_lists(&dev_priv->ring[i]); | |
4b9de737 | 4068 | for (i = 0; i < I915_MAX_NUM_FENCES; i++) |
007cc8ac | 4069 | INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list); |
673a394b EA |
4070 | INIT_DELAYED_WORK(&dev_priv->mm.retire_work, |
4071 | i915_gem_retire_work_handler); | |
99584db3 | 4072 | init_completion(&dev_priv->gpu_error.completion); |
31169714 | 4073 | |
94400120 DA |
4074 | /* On GEN3 we really need to make sure the ARB C3 LP bit is set */ |
4075 | if (IS_GEN3(dev)) { | |
50743298 DV |
4076 | I915_WRITE(MI_ARB_STATE, |
4077 | _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE)); | |
94400120 DA |
4078 | } |
4079 | ||
72bfa19c CW |
4080 | dev_priv->relative_constants_mode = I915_EXEC_CONSTANTS_REL_GENERAL; |
4081 | ||
de151cf6 | 4082 | /* Old X drivers will take 0-2 for front, back, depth buffers */ |
b397c836 EA |
4083 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) |
4084 | dev_priv->fence_reg_start = 3; | |
de151cf6 | 4085 | |
a6c45cf0 | 4086 | if (INTEL_INFO(dev)->gen >= 4 || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) |
de151cf6 JB |
4087 | dev_priv->num_fence_regs = 16; |
4088 | else | |
4089 | dev_priv->num_fence_regs = 8; | |
4090 | ||
b5aa8a0f | 4091 | /* Initialize fence registers to zero */ |
ada726c7 | 4092 | i915_gem_reset_fences(dev); |
10ed13e4 | 4093 | |
673a394b | 4094 | i915_gem_detect_bit_6_swizzle(dev); |
6b95a207 | 4095 | init_waitqueue_head(&dev_priv->pending_flip_queue); |
17250b71 | 4096 | |
ce453d81 CW |
4097 | dev_priv->mm.interruptible = true; |
4098 | ||
17250b71 CW |
4099 | dev_priv->mm.inactive_shrinker.shrink = i915_gem_inactive_shrink; |
4100 | dev_priv->mm.inactive_shrinker.seeks = DEFAULT_SEEKS; | |
4101 | register_shrinker(&dev_priv->mm.inactive_shrinker); | |
673a394b | 4102 | } |
71acb5eb DA |
4103 | |
4104 | /* | |
4105 | * Create a physically contiguous memory object for this object | |
4106 | * e.g. for cursor + overlay regs | |
4107 | */ | |
995b6762 CW |
4108 | static int i915_gem_init_phys_object(struct drm_device *dev, |
4109 | int id, int size, int align) | |
71acb5eb DA |
4110 | { |
4111 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4112 | struct drm_i915_gem_phys_object *phys_obj; | |
4113 | int ret; | |
4114 | ||
4115 | if (dev_priv->mm.phys_objs[id - 1] || !size) | |
4116 | return 0; | |
4117 | ||
9a298b2a | 4118 | phys_obj = kzalloc(sizeof(struct drm_i915_gem_phys_object), GFP_KERNEL); |
71acb5eb DA |
4119 | if (!phys_obj) |
4120 | return -ENOMEM; | |
4121 | ||
4122 | phys_obj->id = id; | |
4123 | ||
6eeefaf3 | 4124 | phys_obj->handle = drm_pci_alloc(dev, size, align); |
71acb5eb DA |
4125 | if (!phys_obj->handle) { |
4126 | ret = -ENOMEM; | |
4127 | goto kfree_obj; | |
4128 | } | |
4129 | #ifdef CONFIG_X86 | |
4130 | set_memory_wc((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE); | |
4131 | #endif | |
4132 | ||
4133 | dev_priv->mm.phys_objs[id - 1] = phys_obj; | |
4134 | ||
4135 | return 0; | |
4136 | kfree_obj: | |
9a298b2a | 4137 | kfree(phys_obj); |
71acb5eb DA |
4138 | return ret; |
4139 | } | |
4140 | ||
995b6762 | 4141 | static void i915_gem_free_phys_object(struct drm_device *dev, int id) |
71acb5eb DA |
4142 | { |
4143 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4144 | struct drm_i915_gem_phys_object *phys_obj; | |
4145 | ||
4146 | if (!dev_priv->mm.phys_objs[id - 1]) | |
4147 | return; | |
4148 | ||
4149 | phys_obj = dev_priv->mm.phys_objs[id - 1]; | |
4150 | if (phys_obj->cur_obj) { | |
4151 | i915_gem_detach_phys_object(dev, phys_obj->cur_obj); | |
4152 | } | |
4153 | ||
4154 | #ifdef CONFIG_X86 | |
4155 | set_memory_wb((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE); | |
4156 | #endif | |
4157 | drm_pci_free(dev, phys_obj->handle); | |
4158 | kfree(phys_obj); | |
4159 | dev_priv->mm.phys_objs[id - 1] = NULL; | |
4160 | } | |
4161 | ||
4162 | void i915_gem_free_all_phys_object(struct drm_device *dev) | |
4163 | { | |
4164 | int i; | |
4165 | ||
260883c8 | 4166 | for (i = I915_GEM_PHYS_CURSOR_0; i <= I915_MAX_PHYS_OBJECT; i++) |
71acb5eb DA |
4167 | i915_gem_free_phys_object(dev, i); |
4168 | } | |
4169 | ||
4170 | void i915_gem_detach_phys_object(struct drm_device *dev, | |
05394f39 | 4171 | struct drm_i915_gem_object *obj) |
71acb5eb | 4172 | { |
05394f39 | 4173 | struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping; |
e5281ccd | 4174 | char *vaddr; |
71acb5eb | 4175 | int i; |
71acb5eb DA |
4176 | int page_count; |
4177 | ||
05394f39 | 4178 | if (!obj->phys_obj) |
71acb5eb | 4179 | return; |
05394f39 | 4180 | vaddr = obj->phys_obj->handle->vaddr; |
71acb5eb | 4181 | |
05394f39 | 4182 | page_count = obj->base.size / PAGE_SIZE; |
71acb5eb | 4183 | for (i = 0; i < page_count; i++) { |
5949eac4 | 4184 | struct page *page = shmem_read_mapping_page(mapping, i); |
e5281ccd CW |
4185 | if (!IS_ERR(page)) { |
4186 | char *dst = kmap_atomic(page); | |
4187 | memcpy(dst, vaddr + i*PAGE_SIZE, PAGE_SIZE); | |
4188 | kunmap_atomic(dst); | |
4189 | ||
4190 | drm_clflush_pages(&page, 1); | |
4191 | ||
4192 | set_page_dirty(page); | |
4193 | mark_page_accessed(page); | |
4194 | page_cache_release(page); | |
4195 | } | |
71acb5eb | 4196 | } |
e76e9aeb | 4197 | i915_gem_chipset_flush(dev); |
d78b47b9 | 4198 | |
05394f39 CW |
4199 | obj->phys_obj->cur_obj = NULL; |
4200 | obj->phys_obj = NULL; | |
71acb5eb DA |
4201 | } |
4202 | ||
4203 | int | |
4204 | i915_gem_attach_phys_object(struct drm_device *dev, | |
05394f39 | 4205 | struct drm_i915_gem_object *obj, |
6eeefaf3 CW |
4206 | int id, |
4207 | int align) | |
71acb5eb | 4208 | { |
05394f39 | 4209 | struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping; |
71acb5eb | 4210 | drm_i915_private_t *dev_priv = dev->dev_private; |
71acb5eb DA |
4211 | int ret = 0; |
4212 | int page_count; | |
4213 | int i; | |
4214 | ||
4215 | if (id > I915_MAX_PHYS_OBJECT) | |
4216 | return -EINVAL; | |
4217 | ||
05394f39 CW |
4218 | if (obj->phys_obj) { |
4219 | if (obj->phys_obj->id == id) | |
71acb5eb DA |
4220 | return 0; |
4221 | i915_gem_detach_phys_object(dev, obj); | |
4222 | } | |
4223 | ||
71acb5eb DA |
4224 | /* create a new object */ |
4225 | if (!dev_priv->mm.phys_objs[id - 1]) { | |
4226 | ret = i915_gem_init_phys_object(dev, id, | |
05394f39 | 4227 | obj->base.size, align); |
71acb5eb | 4228 | if (ret) { |
05394f39 CW |
4229 | DRM_ERROR("failed to init phys object %d size: %zu\n", |
4230 | id, obj->base.size); | |
e5281ccd | 4231 | return ret; |
71acb5eb DA |
4232 | } |
4233 | } | |
4234 | ||
4235 | /* bind to the object */ | |
05394f39 CW |
4236 | obj->phys_obj = dev_priv->mm.phys_objs[id - 1]; |
4237 | obj->phys_obj->cur_obj = obj; | |
71acb5eb | 4238 | |
05394f39 | 4239 | page_count = obj->base.size / PAGE_SIZE; |
71acb5eb DA |
4240 | |
4241 | for (i = 0; i < page_count; i++) { | |
e5281ccd CW |
4242 | struct page *page; |
4243 | char *dst, *src; | |
4244 | ||
5949eac4 | 4245 | page = shmem_read_mapping_page(mapping, i); |
e5281ccd CW |
4246 | if (IS_ERR(page)) |
4247 | return PTR_ERR(page); | |
71acb5eb | 4248 | |
ff75b9bc | 4249 | src = kmap_atomic(page); |
05394f39 | 4250 | dst = obj->phys_obj->handle->vaddr + (i * PAGE_SIZE); |
71acb5eb | 4251 | memcpy(dst, src, PAGE_SIZE); |
3e4d3af5 | 4252 | kunmap_atomic(src); |
71acb5eb | 4253 | |
e5281ccd CW |
4254 | mark_page_accessed(page); |
4255 | page_cache_release(page); | |
4256 | } | |
d78b47b9 | 4257 | |
71acb5eb | 4258 | return 0; |
71acb5eb DA |
4259 | } |
4260 | ||
4261 | static int | |
05394f39 CW |
4262 | i915_gem_phys_pwrite(struct drm_device *dev, |
4263 | struct drm_i915_gem_object *obj, | |
71acb5eb DA |
4264 | struct drm_i915_gem_pwrite *args, |
4265 | struct drm_file *file_priv) | |
4266 | { | |
05394f39 | 4267 | void *vaddr = obj->phys_obj->handle->vaddr + args->offset; |
b47b30cc | 4268 | char __user *user_data = (char __user *) (uintptr_t) args->data_ptr; |
71acb5eb | 4269 | |
b47b30cc CW |
4270 | if (__copy_from_user_inatomic_nocache(vaddr, user_data, args->size)) { |
4271 | unsigned long unwritten; | |
4272 | ||
4273 | /* The physical object once assigned is fixed for the lifetime | |
4274 | * of the obj, so we can safely drop the lock and continue | |
4275 | * to access vaddr. | |
4276 | */ | |
4277 | mutex_unlock(&dev->struct_mutex); | |
4278 | unwritten = copy_from_user(vaddr, user_data, args->size); | |
4279 | mutex_lock(&dev->struct_mutex); | |
4280 | if (unwritten) | |
4281 | return -EFAULT; | |
4282 | } | |
71acb5eb | 4283 | |
e76e9aeb | 4284 | i915_gem_chipset_flush(dev); |
71acb5eb DA |
4285 | return 0; |
4286 | } | |
b962442e | 4287 | |
f787a5f5 | 4288 | void i915_gem_release(struct drm_device *dev, struct drm_file *file) |
b962442e | 4289 | { |
f787a5f5 | 4290 | struct drm_i915_file_private *file_priv = file->driver_priv; |
b962442e EA |
4291 | |
4292 | /* Clean up our request list when the client is going away, so that | |
4293 | * later retire_requests won't dereference our soon-to-be-gone | |
4294 | * file_priv. | |
4295 | */ | |
1c25595f | 4296 | spin_lock(&file_priv->mm.lock); |
f787a5f5 CW |
4297 | while (!list_empty(&file_priv->mm.request_list)) { |
4298 | struct drm_i915_gem_request *request; | |
4299 | ||
4300 | request = list_first_entry(&file_priv->mm.request_list, | |
4301 | struct drm_i915_gem_request, | |
4302 | client_list); | |
4303 | list_del(&request->client_list); | |
4304 | request->file_priv = NULL; | |
4305 | } | |
1c25595f | 4306 | spin_unlock(&file_priv->mm.lock); |
b962442e | 4307 | } |
31169714 | 4308 | |
5774506f CW |
4309 | static bool mutex_is_locked_by(struct mutex *mutex, struct task_struct *task) |
4310 | { | |
4311 | if (!mutex_is_locked(mutex)) | |
4312 | return false; | |
4313 | ||
4314 | #if defined(CONFIG_SMP) || defined(CONFIG_DEBUG_MUTEXES) | |
4315 | return mutex->owner == task; | |
4316 | #else | |
4317 | /* Since UP may be pre-empted, we cannot assume that we own the lock */ | |
4318 | return false; | |
4319 | #endif | |
4320 | } | |
4321 | ||
31169714 | 4322 | static int |
1495f230 | 4323 | i915_gem_inactive_shrink(struct shrinker *shrinker, struct shrink_control *sc) |
31169714 | 4324 | { |
17250b71 CW |
4325 | struct drm_i915_private *dev_priv = |
4326 | container_of(shrinker, | |
4327 | struct drm_i915_private, | |
4328 | mm.inactive_shrinker); | |
4329 | struct drm_device *dev = dev_priv->dev; | |
6c085a72 | 4330 | struct drm_i915_gem_object *obj; |
1495f230 | 4331 | int nr_to_scan = sc->nr_to_scan; |
5774506f | 4332 | bool unlock = true; |
17250b71 CW |
4333 | int cnt; |
4334 | ||
5774506f CW |
4335 | if (!mutex_trylock(&dev->struct_mutex)) { |
4336 | if (!mutex_is_locked_by(&dev->struct_mutex, current)) | |
4337 | return 0; | |
4338 | ||
677feac2 DV |
4339 | if (dev_priv->mm.shrinker_no_lock_stealing) |
4340 | return 0; | |
4341 | ||
5774506f CW |
4342 | unlock = false; |
4343 | } | |
31169714 | 4344 | |
6c085a72 CW |
4345 | if (nr_to_scan) { |
4346 | nr_to_scan -= i915_gem_purge(dev_priv, nr_to_scan); | |
4347 | if (nr_to_scan > 0) | |
4348 | i915_gem_shrink_all(dev_priv); | |
31169714 CW |
4349 | } |
4350 | ||
17250b71 | 4351 | cnt = 0; |
6c085a72 | 4352 | list_for_each_entry(obj, &dev_priv->mm.unbound_list, gtt_list) |
a5570178 CW |
4353 | if (obj->pages_pin_count == 0) |
4354 | cnt += obj->base.size >> PAGE_SHIFT; | |
6c085a72 | 4355 | list_for_each_entry(obj, &dev_priv->mm.bound_list, gtt_list) |
a5570178 | 4356 | if (obj->pin_count == 0 && obj->pages_pin_count == 0) |
6c085a72 | 4357 | cnt += obj->base.size >> PAGE_SHIFT; |
17250b71 | 4358 | |
5774506f CW |
4359 | if (unlock) |
4360 | mutex_unlock(&dev->struct_mutex); | |
6c085a72 | 4361 | return cnt; |
31169714 | 4362 | } |