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673a394b EA |
1 | /* |
2 | * Copyright © 2008 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | * | |
26 | */ | |
27 | ||
28 | #include "drmP.h" | |
29 | #include "drm.h" | |
30 | #include "i915_drm.h" | |
31 | #include "i915_drv.h" | |
1c5d22f7 | 32 | #include "i915_trace.h" |
652c393a | 33 | #include "intel_drv.h" |
5a0e3ad6 | 34 | #include <linux/slab.h> |
673a394b | 35 | #include <linux/swap.h> |
79e53945 | 36 | #include <linux/pci.h> |
f8f235e5 | 37 | #include <linux/intel-gtt.h> |
673a394b | 38 | |
0108a3ed | 39 | static uint32_t i915_gem_get_gtt_alignment(struct drm_gem_object *obj); |
ba3d8d74 DV |
40 | |
41 | static int i915_gem_object_flush_gpu_write_domain(struct drm_gem_object *obj, | |
42 | bool pipelined); | |
e47c68e9 EA |
43 | static void i915_gem_object_flush_gtt_write_domain(struct drm_gem_object *obj); |
44 | static void i915_gem_object_flush_cpu_write_domain(struct drm_gem_object *obj); | |
e47c68e9 EA |
45 | static int i915_gem_object_set_to_cpu_domain(struct drm_gem_object *obj, |
46 | int write); | |
47 | static int i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object *obj, | |
48 | uint64_t offset, | |
49 | uint64_t size); | |
50 | static void i915_gem_object_set_to_full_cpu_read_domain(struct drm_gem_object *obj); | |
2cf34d7b CW |
51 | static int i915_gem_object_wait_rendering(struct drm_gem_object *obj, |
52 | bool interruptible); | |
de151cf6 | 53 | static int i915_gem_object_bind_to_gtt(struct drm_gem_object *obj, |
920afa77 | 54 | unsigned alignment, bool mappable); |
de151cf6 | 55 | static void i915_gem_clear_fence_reg(struct drm_gem_object *obj); |
71acb5eb DA |
56 | static int i915_gem_phys_pwrite(struct drm_device *dev, struct drm_gem_object *obj, |
57 | struct drm_i915_gem_pwrite *args, | |
58 | struct drm_file *file_priv); | |
be72615b | 59 | static void i915_gem_free_object_tail(struct drm_gem_object *obj); |
673a394b | 60 | |
5cdf5881 CW |
61 | static int |
62 | i915_gem_object_get_pages(struct drm_gem_object *obj, | |
63 | gfp_t gfpmask); | |
64 | ||
65 | static void | |
66 | i915_gem_object_put_pages(struct drm_gem_object *obj); | |
67 | ||
17250b71 CW |
68 | static int i915_gem_inactive_shrink(struct shrinker *shrinker, |
69 | int nr_to_scan, | |
70 | gfp_t gfp_mask); | |
71 | ||
31169714 | 72 | |
73aa808f CW |
73 | /* some bookkeeping */ |
74 | static void i915_gem_info_add_obj(struct drm_i915_private *dev_priv, | |
75 | size_t size) | |
76 | { | |
77 | dev_priv->mm.object_count++; | |
78 | dev_priv->mm.object_memory += size; | |
79 | } | |
80 | ||
81 | static void i915_gem_info_remove_obj(struct drm_i915_private *dev_priv, | |
82 | size_t size) | |
83 | { | |
84 | dev_priv->mm.object_count--; | |
85 | dev_priv->mm.object_memory -= size; | |
86 | } | |
87 | ||
88 | static void i915_gem_info_add_gtt(struct drm_i915_private *dev_priv, | |
fb7d516a | 89 | struct drm_gem_object *obj) |
73aa808f | 90 | { |
fb7d516a | 91 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
73aa808f | 92 | dev_priv->mm.gtt_count++; |
fb7d516a DV |
93 | dev_priv->mm.gtt_memory += obj->size; |
94 | if (obj_priv->gtt_offset < dev_priv->mm.gtt_mappable_end) { | |
95 | dev_priv->mm.mappable_gtt_used += | |
96 | min_t(size_t, obj->size, | |
97 | dev_priv->mm.gtt_mappable_end | |
98 | - obj_priv->gtt_offset); | |
99 | } | |
73aa808f CW |
100 | } |
101 | ||
102 | static void i915_gem_info_remove_gtt(struct drm_i915_private *dev_priv, | |
fb7d516a | 103 | struct drm_gem_object *obj) |
73aa808f | 104 | { |
fb7d516a | 105 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
73aa808f | 106 | dev_priv->mm.gtt_count--; |
fb7d516a DV |
107 | dev_priv->mm.gtt_memory -= obj->size; |
108 | if (obj_priv->gtt_offset < dev_priv->mm.gtt_mappable_end) { | |
109 | dev_priv->mm.mappable_gtt_used -= | |
110 | min_t(size_t, obj->size, | |
111 | dev_priv->mm.gtt_mappable_end | |
112 | - obj_priv->gtt_offset); | |
113 | } | |
114 | } | |
115 | ||
116 | /** | |
117 | * Update the mappable working set counters. Call _only_ when there is a change | |
118 | * in one of (pin|fault)_mappable and update *_mappable _before_ calling. | |
119 | * @mappable: new state the changed mappable flag (either pin_ or fault_). | |
120 | */ | |
121 | static void | |
122 | i915_gem_info_update_mappable(struct drm_i915_private *dev_priv, | |
123 | struct drm_gem_object *obj, | |
124 | bool mappable) | |
125 | { | |
126 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); | |
127 | ||
128 | if (mappable) { | |
129 | if (obj_priv->pin_mappable && obj_priv->fault_mappable) | |
130 | /* Combined state was already mappable. */ | |
131 | return; | |
132 | dev_priv->mm.gtt_mappable_count++; | |
133 | dev_priv->mm.gtt_mappable_memory += obj->size; | |
134 | } else { | |
135 | if (obj_priv->pin_mappable || obj_priv->fault_mappable) | |
136 | /* Combined state still mappable. */ | |
137 | return; | |
138 | dev_priv->mm.gtt_mappable_count--; | |
139 | dev_priv->mm.gtt_mappable_memory -= obj->size; | |
140 | } | |
73aa808f CW |
141 | } |
142 | ||
143 | static void i915_gem_info_add_pin(struct drm_i915_private *dev_priv, | |
fb7d516a DV |
144 | struct drm_gem_object *obj, |
145 | bool mappable) | |
73aa808f | 146 | { |
fb7d516a | 147 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
73aa808f | 148 | dev_priv->mm.pin_count++; |
fb7d516a DV |
149 | dev_priv->mm.pin_memory += obj->size; |
150 | if (mappable) { | |
151 | obj_priv->pin_mappable = true; | |
152 | i915_gem_info_update_mappable(dev_priv, obj, true); | |
153 | } | |
73aa808f CW |
154 | } |
155 | ||
156 | static void i915_gem_info_remove_pin(struct drm_i915_private *dev_priv, | |
fb7d516a | 157 | struct drm_gem_object *obj) |
73aa808f | 158 | { |
fb7d516a | 159 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
73aa808f | 160 | dev_priv->mm.pin_count--; |
fb7d516a DV |
161 | dev_priv->mm.pin_memory -= obj->size; |
162 | if (obj_priv->pin_mappable) { | |
163 | obj_priv->pin_mappable = false; | |
164 | i915_gem_info_update_mappable(dev_priv, obj, false); | |
165 | } | |
73aa808f CW |
166 | } |
167 | ||
30dbf0c0 CW |
168 | int |
169 | i915_gem_check_is_wedged(struct drm_device *dev) | |
170 | { | |
171 | struct drm_i915_private *dev_priv = dev->dev_private; | |
172 | struct completion *x = &dev_priv->error_completion; | |
173 | unsigned long flags; | |
174 | int ret; | |
175 | ||
176 | if (!atomic_read(&dev_priv->mm.wedged)) | |
177 | return 0; | |
178 | ||
179 | ret = wait_for_completion_interruptible(x); | |
180 | if (ret) | |
181 | return ret; | |
182 | ||
183 | /* Success, we reset the GPU! */ | |
184 | if (!atomic_read(&dev_priv->mm.wedged)) | |
185 | return 0; | |
186 | ||
187 | /* GPU is hung, bump the completion count to account for | |
188 | * the token we just consumed so that we never hit zero and | |
189 | * end up waiting upon a subsequent completion event that | |
190 | * will never happen. | |
191 | */ | |
192 | spin_lock_irqsave(&x->wait.lock, flags); | |
193 | x->done++; | |
194 | spin_unlock_irqrestore(&x->wait.lock, flags); | |
195 | return -EIO; | |
196 | } | |
197 | ||
76c1dec1 CW |
198 | static int i915_mutex_lock_interruptible(struct drm_device *dev) |
199 | { | |
200 | struct drm_i915_private *dev_priv = dev->dev_private; | |
201 | int ret; | |
202 | ||
203 | ret = i915_gem_check_is_wedged(dev); | |
204 | if (ret) | |
205 | return ret; | |
206 | ||
207 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
208 | if (ret) | |
209 | return ret; | |
210 | ||
211 | if (atomic_read(&dev_priv->mm.wedged)) { | |
212 | mutex_unlock(&dev->struct_mutex); | |
213 | return -EAGAIN; | |
214 | } | |
215 | ||
23bc5982 | 216 | WARN_ON(i915_verify_lists(dev)); |
76c1dec1 CW |
217 | return 0; |
218 | } | |
30dbf0c0 | 219 | |
7d1c4804 CW |
220 | static inline bool |
221 | i915_gem_object_is_inactive(struct drm_i915_gem_object *obj_priv) | |
222 | { | |
223 | return obj_priv->gtt_space && | |
224 | !obj_priv->active && | |
225 | obj_priv->pin_count == 0; | |
226 | } | |
227 | ||
73aa808f CW |
228 | int i915_gem_do_init(struct drm_device *dev, |
229 | unsigned long start, | |
53984635 | 230 | unsigned long mappable_end, |
79e53945 | 231 | unsigned long end) |
673a394b EA |
232 | { |
233 | drm_i915_private_t *dev_priv = dev->dev_private; | |
673a394b | 234 | |
79e53945 JB |
235 | if (start >= end || |
236 | (start & (PAGE_SIZE - 1)) != 0 || | |
237 | (end & (PAGE_SIZE - 1)) != 0) { | |
673a394b EA |
238 | return -EINVAL; |
239 | } | |
240 | ||
79e53945 JB |
241 | drm_mm_init(&dev_priv->mm.gtt_space, start, |
242 | end - start); | |
673a394b | 243 | |
73aa808f | 244 | dev_priv->mm.gtt_total = end - start; |
fb7d516a | 245 | dev_priv->mm.mappable_gtt_total = min(end, mappable_end) - start; |
53984635 | 246 | dev_priv->mm.gtt_mappable_end = mappable_end; |
79e53945 JB |
247 | |
248 | return 0; | |
249 | } | |
673a394b | 250 | |
79e53945 JB |
251 | int |
252 | i915_gem_init_ioctl(struct drm_device *dev, void *data, | |
253 | struct drm_file *file_priv) | |
254 | { | |
255 | struct drm_i915_gem_init *args = data; | |
256 | int ret; | |
257 | ||
258 | mutex_lock(&dev->struct_mutex); | |
53984635 | 259 | ret = i915_gem_do_init(dev, args->gtt_start, args->gtt_end, args->gtt_end); |
673a394b EA |
260 | mutex_unlock(&dev->struct_mutex); |
261 | ||
79e53945 | 262 | return ret; |
673a394b EA |
263 | } |
264 | ||
5a125c3c EA |
265 | int |
266 | i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data, | |
267 | struct drm_file *file_priv) | |
268 | { | |
73aa808f | 269 | struct drm_i915_private *dev_priv = dev->dev_private; |
5a125c3c | 270 | struct drm_i915_gem_get_aperture *args = data; |
5a125c3c EA |
271 | |
272 | if (!(dev->driver->driver_features & DRIVER_GEM)) | |
273 | return -ENODEV; | |
274 | ||
73aa808f CW |
275 | mutex_lock(&dev->struct_mutex); |
276 | args->aper_size = dev_priv->mm.gtt_total; | |
277 | args->aper_available_size = args->aper_size - dev_priv->mm.pin_memory; | |
278 | mutex_unlock(&dev->struct_mutex); | |
5a125c3c EA |
279 | |
280 | return 0; | |
281 | } | |
282 | ||
673a394b EA |
283 | |
284 | /** | |
285 | * Creates a new mm object and returns a handle to it. | |
286 | */ | |
287 | int | |
288 | i915_gem_create_ioctl(struct drm_device *dev, void *data, | |
289 | struct drm_file *file_priv) | |
290 | { | |
291 | struct drm_i915_gem_create *args = data; | |
292 | struct drm_gem_object *obj; | |
a1a2d1d3 PP |
293 | int ret; |
294 | u32 handle; | |
673a394b EA |
295 | |
296 | args->size = roundup(args->size, PAGE_SIZE); | |
297 | ||
298 | /* Allocate the new object */ | |
ac52bc56 | 299 | obj = i915_gem_alloc_object(dev, args->size); |
673a394b EA |
300 | if (obj == NULL) |
301 | return -ENOMEM; | |
302 | ||
303 | ret = drm_gem_handle_create(file_priv, obj, &handle); | |
1dfd9754 | 304 | if (ret) { |
202f2fef CW |
305 | drm_gem_object_release(obj); |
306 | i915_gem_info_remove_obj(dev->dev_private, obj->size); | |
307 | kfree(obj); | |
673a394b | 308 | return ret; |
1dfd9754 | 309 | } |
673a394b | 310 | |
202f2fef CW |
311 | /* drop reference from allocate - handle holds it now */ |
312 | drm_gem_object_unreference(obj); | |
313 | trace_i915_gem_object_create(obj); | |
314 | ||
1dfd9754 | 315 | args->handle = handle; |
673a394b EA |
316 | return 0; |
317 | } | |
318 | ||
16e809ac DV |
319 | static bool |
320 | i915_gem_object_cpu_accessible(struct drm_i915_gem_object *obj) | |
321 | { | |
322 | struct drm_device *dev = obj->base.dev; | |
323 | drm_i915_private_t *dev_priv = dev->dev_private; | |
324 | ||
325 | return obj->gtt_space == NULL || | |
326 | obj->gtt_offset + obj->base.size <= dev_priv->mm.gtt_mappable_end; | |
327 | } | |
328 | ||
eb01459f EA |
329 | static inline int |
330 | fast_shmem_read(struct page **pages, | |
331 | loff_t page_base, int page_offset, | |
332 | char __user *data, | |
333 | int length) | |
334 | { | |
b5e4feb6 | 335 | char *vaddr; |
4f27b75d | 336 | int ret; |
eb01459f | 337 | |
3e4d3af5 | 338 | vaddr = kmap_atomic(pages[page_base >> PAGE_SHIFT]); |
4f27b75d | 339 | ret = __copy_to_user_inatomic(data, vaddr + page_offset, length); |
3e4d3af5 | 340 | kunmap_atomic(vaddr); |
eb01459f | 341 | |
4f27b75d | 342 | return ret; |
eb01459f EA |
343 | } |
344 | ||
280b713b EA |
345 | static int i915_gem_object_needs_bit17_swizzle(struct drm_gem_object *obj) |
346 | { | |
347 | drm_i915_private_t *dev_priv = obj->dev->dev_private; | |
23010e43 | 348 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
280b713b EA |
349 | |
350 | return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 && | |
351 | obj_priv->tiling_mode != I915_TILING_NONE; | |
352 | } | |
353 | ||
99a03df5 | 354 | static inline void |
40123c1f EA |
355 | slow_shmem_copy(struct page *dst_page, |
356 | int dst_offset, | |
357 | struct page *src_page, | |
358 | int src_offset, | |
359 | int length) | |
360 | { | |
361 | char *dst_vaddr, *src_vaddr; | |
362 | ||
99a03df5 CW |
363 | dst_vaddr = kmap(dst_page); |
364 | src_vaddr = kmap(src_page); | |
40123c1f EA |
365 | |
366 | memcpy(dst_vaddr + dst_offset, src_vaddr + src_offset, length); | |
367 | ||
99a03df5 CW |
368 | kunmap(src_page); |
369 | kunmap(dst_page); | |
40123c1f EA |
370 | } |
371 | ||
99a03df5 | 372 | static inline void |
280b713b EA |
373 | slow_shmem_bit17_copy(struct page *gpu_page, |
374 | int gpu_offset, | |
375 | struct page *cpu_page, | |
376 | int cpu_offset, | |
377 | int length, | |
378 | int is_read) | |
379 | { | |
380 | char *gpu_vaddr, *cpu_vaddr; | |
381 | ||
382 | /* Use the unswizzled path if this page isn't affected. */ | |
383 | if ((page_to_phys(gpu_page) & (1 << 17)) == 0) { | |
384 | if (is_read) | |
385 | return slow_shmem_copy(cpu_page, cpu_offset, | |
386 | gpu_page, gpu_offset, length); | |
387 | else | |
388 | return slow_shmem_copy(gpu_page, gpu_offset, | |
389 | cpu_page, cpu_offset, length); | |
390 | } | |
391 | ||
99a03df5 CW |
392 | gpu_vaddr = kmap(gpu_page); |
393 | cpu_vaddr = kmap(cpu_page); | |
280b713b EA |
394 | |
395 | /* Copy the data, XORing A6 with A17 (1). The user already knows he's | |
396 | * XORing with the other bits (A9 for Y, A9 and A10 for X) | |
397 | */ | |
398 | while (length > 0) { | |
399 | int cacheline_end = ALIGN(gpu_offset + 1, 64); | |
400 | int this_length = min(cacheline_end - gpu_offset, length); | |
401 | int swizzled_gpu_offset = gpu_offset ^ 64; | |
402 | ||
403 | if (is_read) { | |
404 | memcpy(cpu_vaddr + cpu_offset, | |
405 | gpu_vaddr + swizzled_gpu_offset, | |
406 | this_length); | |
407 | } else { | |
408 | memcpy(gpu_vaddr + swizzled_gpu_offset, | |
409 | cpu_vaddr + cpu_offset, | |
410 | this_length); | |
411 | } | |
412 | cpu_offset += this_length; | |
413 | gpu_offset += this_length; | |
414 | length -= this_length; | |
415 | } | |
416 | ||
99a03df5 CW |
417 | kunmap(cpu_page); |
418 | kunmap(gpu_page); | |
280b713b EA |
419 | } |
420 | ||
eb01459f EA |
421 | /** |
422 | * This is the fast shmem pread path, which attempts to copy_from_user directly | |
423 | * from the backing pages of the object to the user's address space. On a | |
424 | * fault, it fails so we can fall back to i915_gem_shmem_pwrite_slow(). | |
425 | */ | |
426 | static int | |
427 | i915_gem_shmem_pread_fast(struct drm_device *dev, struct drm_gem_object *obj, | |
428 | struct drm_i915_gem_pread *args, | |
429 | struct drm_file *file_priv) | |
430 | { | |
23010e43 | 431 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
eb01459f EA |
432 | ssize_t remain; |
433 | loff_t offset, page_base; | |
434 | char __user *user_data; | |
435 | int page_offset, page_length; | |
eb01459f EA |
436 | |
437 | user_data = (char __user *) (uintptr_t) args->data_ptr; | |
438 | remain = args->size; | |
439 | ||
23010e43 | 440 | obj_priv = to_intel_bo(obj); |
eb01459f EA |
441 | offset = args->offset; |
442 | ||
443 | while (remain > 0) { | |
444 | /* Operation in this page | |
445 | * | |
446 | * page_base = page offset within aperture | |
447 | * page_offset = offset within page | |
448 | * page_length = bytes to copy for this page | |
449 | */ | |
450 | page_base = (offset & ~(PAGE_SIZE-1)); | |
451 | page_offset = offset & (PAGE_SIZE-1); | |
452 | page_length = remain; | |
453 | if ((page_offset + remain) > PAGE_SIZE) | |
454 | page_length = PAGE_SIZE - page_offset; | |
455 | ||
4f27b75d CW |
456 | if (fast_shmem_read(obj_priv->pages, |
457 | page_base, page_offset, | |
458 | user_data, page_length)) | |
459 | return -EFAULT; | |
eb01459f EA |
460 | |
461 | remain -= page_length; | |
462 | user_data += page_length; | |
463 | offset += page_length; | |
464 | } | |
465 | ||
4f27b75d | 466 | return 0; |
eb01459f EA |
467 | } |
468 | ||
07f73f69 CW |
469 | static int |
470 | i915_gem_object_get_pages_or_evict(struct drm_gem_object *obj) | |
471 | { | |
472 | int ret; | |
473 | ||
4bdadb97 | 474 | ret = i915_gem_object_get_pages(obj, __GFP_NORETRY | __GFP_NOWARN); |
07f73f69 CW |
475 | |
476 | /* If we've insufficient memory to map in the pages, attempt | |
477 | * to make some space by throwing out some old buffers. | |
478 | */ | |
479 | if (ret == -ENOMEM) { | |
480 | struct drm_device *dev = obj->dev; | |
07f73f69 | 481 | |
0108a3ed | 482 | ret = i915_gem_evict_something(dev, obj->size, |
a6e0aa42 DV |
483 | i915_gem_get_gtt_alignment(obj), |
484 | false); | |
07f73f69 CW |
485 | if (ret) |
486 | return ret; | |
487 | ||
4bdadb97 | 488 | ret = i915_gem_object_get_pages(obj, 0); |
07f73f69 CW |
489 | } |
490 | ||
491 | return ret; | |
492 | } | |
493 | ||
eb01459f EA |
494 | /** |
495 | * This is the fallback shmem pread path, which allocates temporary storage | |
496 | * in kernel space to copy_to_user into outside of the struct_mutex, so we | |
497 | * can copy out of the object's backing pages while holding the struct mutex | |
498 | * and not take page faults. | |
499 | */ | |
500 | static int | |
501 | i915_gem_shmem_pread_slow(struct drm_device *dev, struct drm_gem_object *obj, | |
502 | struct drm_i915_gem_pread *args, | |
503 | struct drm_file *file_priv) | |
504 | { | |
23010e43 | 505 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
eb01459f EA |
506 | struct mm_struct *mm = current->mm; |
507 | struct page **user_pages; | |
508 | ssize_t remain; | |
509 | loff_t offset, pinned_pages, i; | |
510 | loff_t first_data_page, last_data_page, num_pages; | |
511 | int shmem_page_index, shmem_page_offset; | |
512 | int data_page_index, data_page_offset; | |
513 | int page_length; | |
514 | int ret; | |
515 | uint64_t data_ptr = args->data_ptr; | |
280b713b | 516 | int do_bit17_swizzling; |
eb01459f EA |
517 | |
518 | remain = args->size; | |
519 | ||
520 | /* Pin the user pages containing the data. We can't fault while | |
521 | * holding the struct mutex, yet we want to hold it while | |
522 | * dereferencing the user data. | |
523 | */ | |
524 | first_data_page = data_ptr / PAGE_SIZE; | |
525 | last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE; | |
526 | num_pages = last_data_page - first_data_page + 1; | |
527 | ||
4f27b75d | 528 | user_pages = drm_malloc_ab(num_pages, sizeof(struct page *)); |
eb01459f EA |
529 | if (user_pages == NULL) |
530 | return -ENOMEM; | |
531 | ||
4f27b75d | 532 | mutex_unlock(&dev->struct_mutex); |
eb01459f EA |
533 | down_read(&mm->mmap_sem); |
534 | pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr, | |
e5e9ecde | 535 | num_pages, 1, 0, user_pages, NULL); |
eb01459f | 536 | up_read(&mm->mmap_sem); |
4f27b75d | 537 | mutex_lock(&dev->struct_mutex); |
eb01459f EA |
538 | if (pinned_pages < num_pages) { |
539 | ret = -EFAULT; | |
4f27b75d | 540 | goto out; |
eb01459f EA |
541 | } |
542 | ||
4f27b75d CW |
543 | ret = i915_gem_object_set_cpu_read_domain_range(obj, |
544 | args->offset, | |
545 | args->size); | |
07f73f69 | 546 | if (ret) |
4f27b75d | 547 | goto out; |
eb01459f | 548 | |
4f27b75d | 549 | do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj); |
eb01459f | 550 | |
23010e43 | 551 | obj_priv = to_intel_bo(obj); |
eb01459f EA |
552 | offset = args->offset; |
553 | ||
554 | while (remain > 0) { | |
555 | /* Operation in this page | |
556 | * | |
557 | * shmem_page_index = page number within shmem file | |
558 | * shmem_page_offset = offset within page in shmem file | |
559 | * data_page_index = page number in get_user_pages return | |
560 | * data_page_offset = offset with data_page_index page. | |
561 | * page_length = bytes to copy for this page | |
562 | */ | |
563 | shmem_page_index = offset / PAGE_SIZE; | |
564 | shmem_page_offset = offset & ~PAGE_MASK; | |
565 | data_page_index = data_ptr / PAGE_SIZE - first_data_page; | |
566 | data_page_offset = data_ptr & ~PAGE_MASK; | |
567 | ||
568 | page_length = remain; | |
569 | if ((shmem_page_offset + page_length) > PAGE_SIZE) | |
570 | page_length = PAGE_SIZE - shmem_page_offset; | |
571 | if ((data_page_offset + page_length) > PAGE_SIZE) | |
572 | page_length = PAGE_SIZE - data_page_offset; | |
573 | ||
280b713b | 574 | if (do_bit17_swizzling) { |
99a03df5 | 575 | slow_shmem_bit17_copy(obj_priv->pages[shmem_page_index], |
280b713b | 576 | shmem_page_offset, |
99a03df5 CW |
577 | user_pages[data_page_index], |
578 | data_page_offset, | |
579 | page_length, | |
580 | 1); | |
581 | } else { | |
582 | slow_shmem_copy(user_pages[data_page_index], | |
583 | data_page_offset, | |
584 | obj_priv->pages[shmem_page_index], | |
585 | shmem_page_offset, | |
586 | page_length); | |
280b713b | 587 | } |
eb01459f EA |
588 | |
589 | remain -= page_length; | |
590 | data_ptr += page_length; | |
591 | offset += page_length; | |
592 | } | |
593 | ||
4f27b75d | 594 | out: |
eb01459f EA |
595 | for (i = 0; i < pinned_pages; i++) { |
596 | SetPageDirty(user_pages[i]); | |
597 | page_cache_release(user_pages[i]); | |
598 | } | |
8e7d2b2c | 599 | drm_free_large(user_pages); |
eb01459f EA |
600 | |
601 | return ret; | |
602 | } | |
603 | ||
673a394b EA |
604 | /** |
605 | * Reads data from the object referenced by handle. | |
606 | * | |
607 | * On error, the contents of *data are undefined. | |
608 | */ | |
609 | int | |
610 | i915_gem_pread_ioctl(struct drm_device *dev, void *data, | |
611 | struct drm_file *file_priv) | |
612 | { | |
613 | struct drm_i915_gem_pread *args = data; | |
614 | struct drm_gem_object *obj; | |
615 | struct drm_i915_gem_object *obj_priv; | |
35b62a89 | 616 | int ret = 0; |
673a394b | 617 | |
4f27b75d | 618 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 619 | if (ret) |
4f27b75d | 620 | return ret; |
673a394b EA |
621 | |
622 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); | |
1d7cfea1 CW |
623 | if (obj == NULL) { |
624 | ret = -ENOENT; | |
625 | goto unlock; | |
4f27b75d | 626 | } |
23010e43 | 627 | obj_priv = to_intel_bo(obj); |
673a394b | 628 | |
7dcd2499 CW |
629 | /* Bounds check source. */ |
630 | if (args->offset > obj->size || args->size > obj->size - args->offset) { | |
ce9d419d | 631 | ret = -EINVAL; |
35b62a89 | 632 | goto out; |
ce9d419d CW |
633 | } |
634 | ||
35b62a89 CW |
635 | if (args->size == 0) |
636 | goto out; | |
637 | ||
ce9d419d CW |
638 | if (!access_ok(VERIFY_WRITE, |
639 | (char __user *)(uintptr_t)args->data_ptr, | |
640 | args->size)) { | |
641 | ret = -EFAULT; | |
35b62a89 | 642 | goto out; |
673a394b EA |
643 | } |
644 | ||
b5e4feb6 CW |
645 | ret = fault_in_pages_writeable((char __user *)(uintptr_t)args->data_ptr, |
646 | args->size); | |
647 | if (ret) { | |
648 | ret = -EFAULT; | |
649 | goto out; | |
280b713b | 650 | } |
673a394b | 651 | |
4f27b75d CW |
652 | ret = i915_gem_object_get_pages_or_evict(obj); |
653 | if (ret) | |
654 | goto out; | |
655 | ||
656 | ret = i915_gem_object_set_cpu_read_domain_range(obj, | |
657 | args->offset, | |
658 | args->size); | |
659 | if (ret) | |
660 | goto out_put; | |
661 | ||
662 | ret = -EFAULT; | |
663 | if (!i915_gem_object_needs_bit17_swizzle(obj)) | |
280b713b | 664 | ret = i915_gem_shmem_pread_fast(dev, obj, args, file_priv); |
4f27b75d CW |
665 | if (ret == -EFAULT) |
666 | ret = i915_gem_shmem_pread_slow(dev, obj, args, file_priv); | |
673a394b | 667 | |
4f27b75d CW |
668 | out_put: |
669 | i915_gem_object_put_pages(obj); | |
35b62a89 | 670 | out: |
4f27b75d | 671 | drm_gem_object_unreference(obj); |
1d7cfea1 | 672 | unlock: |
4f27b75d | 673 | mutex_unlock(&dev->struct_mutex); |
eb01459f | 674 | return ret; |
673a394b EA |
675 | } |
676 | ||
0839ccb8 KP |
677 | /* This is the fast write path which cannot handle |
678 | * page faults in the source data | |
9b7530cc | 679 | */ |
0839ccb8 KP |
680 | |
681 | static inline int | |
682 | fast_user_write(struct io_mapping *mapping, | |
683 | loff_t page_base, int page_offset, | |
684 | char __user *user_data, | |
685 | int length) | |
9b7530cc | 686 | { |
9b7530cc | 687 | char *vaddr_atomic; |
0839ccb8 | 688 | unsigned long unwritten; |
9b7530cc | 689 | |
3e4d3af5 | 690 | vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base); |
0839ccb8 KP |
691 | unwritten = __copy_from_user_inatomic_nocache(vaddr_atomic + page_offset, |
692 | user_data, length); | |
3e4d3af5 | 693 | io_mapping_unmap_atomic(vaddr_atomic); |
fbd5a26d | 694 | return unwritten; |
0839ccb8 KP |
695 | } |
696 | ||
697 | /* Here's the write path which can sleep for | |
698 | * page faults | |
699 | */ | |
700 | ||
ab34c226 | 701 | static inline void |
3de09aa3 EA |
702 | slow_kernel_write(struct io_mapping *mapping, |
703 | loff_t gtt_base, int gtt_offset, | |
704 | struct page *user_page, int user_offset, | |
705 | int length) | |
0839ccb8 | 706 | { |
ab34c226 CW |
707 | char __iomem *dst_vaddr; |
708 | char *src_vaddr; | |
0839ccb8 | 709 | |
ab34c226 CW |
710 | dst_vaddr = io_mapping_map_wc(mapping, gtt_base); |
711 | src_vaddr = kmap(user_page); | |
712 | ||
713 | memcpy_toio(dst_vaddr + gtt_offset, | |
714 | src_vaddr + user_offset, | |
715 | length); | |
716 | ||
717 | kunmap(user_page); | |
718 | io_mapping_unmap(dst_vaddr); | |
9b7530cc LT |
719 | } |
720 | ||
40123c1f EA |
721 | static inline int |
722 | fast_shmem_write(struct page **pages, | |
723 | loff_t page_base, int page_offset, | |
724 | char __user *data, | |
725 | int length) | |
726 | { | |
b5e4feb6 | 727 | char *vaddr; |
fbd5a26d | 728 | int ret; |
40123c1f | 729 | |
3e4d3af5 | 730 | vaddr = kmap_atomic(pages[page_base >> PAGE_SHIFT]); |
fbd5a26d | 731 | ret = __copy_from_user_inatomic(vaddr + page_offset, data, length); |
3e4d3af5 | 732 | kunmap_atomic(vaddr); |
40123c1f | 733 | |
fbd5a26d | 734 | return ret; |
40123c1f EA |
735 | } |
736 | ||
3de09aa3 EA |
737 | /** |
738 | * This is the fast pwrite path, where we copy the data directly from the | |
739 | * user into the GTT, uncached. | |
740 | */ | |
673a394b | 741 | static int |
3de09aa3 EA |
742 | i915_gem_gtt_pwrite_fast(struct drm_device *dev, struct drm_gem_object *obj, |
743 | struct drm_i915_gem_pwrite *args, | |
744 | struct drm_file *file_priv) | |
673a394b | 745 | { |
23010e43 | 746 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
0839ccb8 | 747 | drm_i915_private_t *dev_priv = dev->dev_private; |
673a394b | 748 | ssize_t remain; |
0839ccb8 | 749 | loff_t offset, page_base; |
673a394b | 750 | char __user *user_data; |
0839ccb8 | 751 | int page_offset, page_length; |
673a394b EA |
752 | |
753 | user_data = (char __user *) (uintptr_t) args->data_ptr; | |
754 | remain = args->size; | |
673a394b | 755 | |
23010e43 | 756 | obj_priv = to_intel_bo(obj); |
673a394b | 757 | offset = obj_priv->gtt_offset + args->offset; |
673a394b EA |
758 | |
759 | while (remain > 0) { | |
760 | /* Operation in this page | |
761 | * | |
0839ccb8 KP |
762 | * page_base = page offset within aperture |
763 | * page_offset = offset within page | |
764 | * page_length = bytes to copy for this page | |
673a394b | 765 | */ |
0839ccb8 KP |
766 | page_base = (offset & ~(PAGE_SIZE-1)); |
767 | page_offset = offset & (PAGE_SIZE-1); | |
768 | page_length = remain; | |
769 | if ((page_offset + remain) > PAGE_SIZE) | |
770 | page_length = PAGE_SIZE - page_offset; | |
771 | ||
0839ccb8 | 772 | /* If we get a fault while copying data, then (presumably) our |
3de09aa3 EA |
773 | * source page isn't available. Return the error and we'll |
774 | * retry in the slow path. | |
0839ccb8 | 775 | */ |
fbd5a26d CW |
776 | if (fast_user_write(dev_priv->mm.gtt_mapping, page_base, |
777 | page_offset, user_data, page_length)) | |
778 | ||
779 | return -EFAULT; | |
673a394b | 780 | |
0839ccb8 KP |
781 | remain -= page_length; |
782 | user_data += page_length; | |
783 | offset += page_length; | |
673a394b | 784 | } |
673a394b | 785 | |
fbd5a26d | 786 | return 0; |
673a394b EA |
787 | } |
788 | ||
3de09aa3 EA |
789 | /** |
790 | * This is the fallback GTT pwrite path, which uses get_user_pages to pin | |
791 | * the memory and maps it using kmap_atomic for copying. | |
792 | * | |
793 | * This code resulted in x11perf -rgb10text consuming about 10% more CPU | |
794 | * than using i915_gem_gtt_pwrite_fast on a G45 (32-bit). | |
795 | */ | |
3043c60c | 796 | static int |
3de09aa3 EA |
797 | i915_gem_gtt_pwrite_slow(struct drm_device *dev, struct drm_gem_object *obj, |
798 | struct drm_i915_gem_pwrite *args, | |
799 | struct drm_file *file_priv) | |
673a394b | 800 | { |
23010e43 | 801 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
3de09aa3 EA |
802 | drm_i915_private_t *dev_priv = dev->dev_private; |
803 | ssize_t remain; | |
804 | loff_t gtt_page_base, offset; | |
805 | loff_t first_data_page, last_data_page, num_pages; | |
806 | loff_t pinned_pages, i; | |
807 | struct page **user_pages; | |
808 | struct mm_struct *mm = current->mm; | |
809 | int gtt_page_offset, data_page_offset, data_page_index, page_length; | |
673a394b | 810 | int ret; |
3de09aa3 EA |
811 | uint64_t data_ptr = args->data_ptr; |
812 | ||
813 | remain = args->size; | |
814 | ||
815 | /* Pin the user pages containing the data. We can't fault while | |
816 | * holding the struct mutex, and all of the pwrite implementations | |
817 | * want to hold it while dereferencing the user data. | |
818 | */ | |
819 | first_data_page = data_ptr / PAGE_SIZE; | |
820 | last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE; | |
821 | num_pages = last_data_page - first_data_page + 1; | |
822 | ||
fbd5a26d | 823 | user_pages = drm_malloc_ab(num_pages, sizeof(struct page *)); |
3de09aa3 EA |
824 | if (user_pages == NULL) |
825 | return -ENOMEM; | |
826 | ||
fbd5a26d | 827 | mutex_unlock(&dev->struct_mutex); |
3de09aa3 EA |
828 | down_read(&mm->mmap_sem); |
829 | pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr, | |
830 | num_pages, 0, 0, user_pages, NULL); | |
831 | up_read(&mm->mmap_sem); | |
fbd5a26d | 832 | mutex_lock(&dev->struct_mutex); |
3de09aa3 EA |
833 | if (pinned_pages < num_pages) { |
834 | ret = -EFAULT; | |
835 | goto out_unpin_pages; | |
836 | } | |
673a394b | 837 | |
3de09aa3 EA |
838 | ret = i915_gem_object_set_to_gtt_domain(obj, 1); |
839 | if (ret) | |
fbd5a26d | 840 | goto out_unpin_pages; |
3de09aa3 | 841 | |
23010e43 | 842 | obj_priv = to_intel_bo(obj); |
3de09aa3 EA |
843 | offset = obj_priv->gtt_offset + args->offset; |
844 | ||
845 | while (remain > 0) { | |
846 | /* Operation in this page | |
847 | * | |
848 | * gtt_page_base = page offset within aperture | |
849 | * gtt_page_offset = offset within page in aperture | |
850 | * data_page_index = page number in get_user_pages return | |
851 | * data_page_offset = offset with data_page_index page. | |
852 | * page_length = bytes to copy for this page | |
853 | */ | |
854 | gtt_page_base = offset & PAGE_MASK; | |
855 | gtt_page_offset = offset & ~PAGE_MASK; | |
856 | data_page_index = data_ptr / PAGE_SIZE - first_data_page; | |
857 | data_page_offset = data_ptr & ~PAGE_MASK; | |
858 | ||
859 | page_length = remain; | |
860 | if ((gtt_page_offset + page_length) > PAGE_SIZE) | |
861 | page_length = PAGE_SIZE - gtt_page_offset; | |
862 | if ((data_page_offset + page_length) > PAGE_SIZE) | |
863 | page_length = PAGE_SIZE - data_page_offset; | |
864 | ||
ab34c226 CW |
865 | slow_kernel_write(dev_priv->mm.gtt_mapping, |
866 | gtt_page_base, gtt_page_offset, | |
867 | user_pages[data_page_index], | |
868 | data_page_offset, | |
869 | page_length); | |
3de09aa3 EA |
870 | |
871 | remain -= page_length; | |
872 | offset += page_length; | |
873 | data_ptr += page_length; | |
874 | } | |
875 | ||
3de09aa3 EA |
876 | out_unpin_pages: |
877 | for (i = 0; i < pinned_pages; i++) | |
878 | page_cache_release(user_pages[i]); | |
8e7d2b2c | 879 | drm_free_large(user_pages); |
3de09aa3 EA |
880 | |
881 | return ret; | |
882 | } | |
883 | ||
40123c1f EA |
884 | /** |
885 | * This is the fast shmem pwrite path, which attempts to directly | |
886 | * copy_from_user into the kmapped pages backing the object. | |
887 | */ | |
3043c60c | 888 | static int |
40123c1f EA |
889 | i915_gem_shmem_pwrite_fast(struct drm_device *dev, struct drm_gem_object *obj, |
890 | struct drm_i915_gem_pwrite *args, | |
891 | struct drm_file *file_priv) | |
673a394b | 892 | { |
23010e43 | 893 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
40123c1f EA |
894 | ssize_t remain; |
895 | loff_t offset, page_base; | |
896 | char __user *user_data; | |
897 | int page_offset, page_length; | |
40123c1f EA |
898 | |
899 | user_data = (char __user *) (uintptr_t) args->data_ptr; | |
900 | remain = args->size; | |
673a394b | 901 | |
23010e43 | 902 | obj_priv = to_intel_bo(obj); |
40123c1f EA |
903 | offset = args->offset; |
904 | obj_priv->dirty = 1; | |
905 | ||
906 | while (remain > 0) { | |
907 | /* Operation in this page | |
908 | * | |
909 | * page_base = page offset within aperture | |
910 | * page_offset = offset within page | |
911 | * page_length = bytes to copy for this page | |
912 | */ | |
913 | page_base = (offset & ~(PAGE_SIZE-1)); | |
914 | page_offset = offset & (PAGE_SIZE-1); | |
915 | page_length = remain; | |
916 | if ((page_offset + remain) > PAGE_SIZE) | |
917 | page_length = PAGE_SIZE - page_offset; | |
918 | ||
fbd5a26d | 919 | if (fast_shmem_write(obj_priv->pages, |
40123c1f | 920 | page_base, page_offset, |
fbd5a26d CW |
921 | user_data, page_length)) |
922 | return -EFAULT; | |
40123c1f EA |
923 | |
924 | remain -= page_length; | |
925 | user_data += page_length; | |
926 | offset += page_length; | |
927 | } | |
928 | ||
fbd5a26d | 929 | return 0; |
40123c1f EA |
930 | } |
931 | ||
932 | /** | |
933 | * This is the fallback shmem pwrite path, which uses get_user_pages to pin | |
934 | * the memory and maps it using kmap_atomic for copying. | |
935 | * | |
936 | * This avoids taking mmap_sem for faulting on the user's address while the | |
937 | * struct_mutex is held. | |
938 | */ | |
939 | static int | |
940 | i915_gem_shmem_pwrite_slow(struct drm_device *dev, struct drm_gem_object *obj, | |
941 | struct drm_i915_gem_pwrite *args, | |
942 | struct drm_file *file_priv) | |
943 | { | |
23010e43 | 944 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
40123c1f EA |
945 | struct mm_struct *mm = current->mm; |
946 | struct page **user_pages; | |
947 | ssize_t remain; | |
948 | loff_t offset, pinned_pages, i; | |
949 | loff_t first_data_page, last_data_page, num_pages; | |
950 | int shmem_page_index, shmem_page_offset; | |
951 | int data_page_index, data_page_offset; | |
952 | int page_length; | |
953 | int ret; | |
954 | uint64_t data_ptr = args->data_ptr; | |
280b713b | 955 | int do_bit17_swizzling; |
40123c1f EA |
956 | |
957 | remain = args->size; | |
958 | ||
959 | /* Pin the user pages containing the data. We can't fault while | |
960 | * holding the struct mutex, and all of the pwrite implementations | |
961 | * want to hold it while dereferencing the user data. | |
962 | */ | |
963 | first_data_page = data_ptr / PAGE_SIZE; | |
964 | last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE; | |
965 | num_pages = last_data_page - first_data_page + 1; | |
966 | ||
4f27b75d | 967 | user_pages = drm_malloc_ab(num_pages, sizeof(struct page *)); |
40123c1f EA |
968 | if (user_pages == NULL) |
969 | return -ENOMEM; | |
970 | ||
fbd5a26d | 971 | mutex_unlock(&dev->struct_mutex); |
40123c1f EA |
972 | down_read(&mm->mmap_sem); |
973 | pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr, | |
974 | num_pages, 0, 0, user_pages, NULL); | |
975 | up_read(&mm->mmap_sem); | |
fbd5a26d | 976 | mutex_lock(&dev->struct_mutex); |
40123c1f EA |
977 | if (pinned_pages < num_pages) { |
978 | ret = -EFAULT; | |
fbd5a26d | 979 | goto out; |
673a394b EA |
980 | } |
981 | ||
fbd5a26d | 982 | ret = i915_gem_object_set_to_cpu_domain(obj, 1); |
07f73f69 | 983 | if (ret) |
fbd5a26d | 984 | goto out; |
40123c1f | 985 | |
fbd5a26d | 986 | do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj); |
40123c1f | 987 | |
23010e43 | 988 | obj_priv = to_intel_bo(obj); |
673a394b | 989 | offset = args->offset; |
40123c1f | 990 | obj_priv->dirty = 1; |
673a394b | 991 | |
40123c1f EA |
992 | while (remain > 0) { |
993 | /* Operation in this page | |
994 | * | |
995 | * shmem_page_index = page number within shmem file | |
996 | * shmem_page_offset = offset within page in shmem file | |
997 | * data_page_index = page number in get_user_pages return | |
998 | * data_page_offset = offset with data_page_index page. | |
999 | * page_length = bytes to copy for this page | |
1000 | */ | |
1001 | shmem_page_index = offset / PAGE_SIZE; | |
1002 | shmem_page_offset = offset & ~PAGE_MASK; | |
1003 | data_page_index = data_ptr / PAGE_SIZE - first_data_page; | |
1004 | data_page_offset = data_ptr & ~PAGE_MASK; | |
1005 | ||
1006 | page_length = remain; | |
1007 | if ((shmem_page_offset + page_length) > PAGE_SIZE) | |
1008 | page_length = PAGE_SIZE - shmem_page_offset; | |
1009 | if ((data_page_offset + page_length) > PAGE_SIZE) | |
1010 | page_length = PAGE_SIZE - data_page_offset; | |
1011 | ||
280b713b | 1012 | if (do_bit17_swizzling) { |
99a03df5 | 1013 | slow_shmem_bit17_copy(obj_priv->pages[shmem_page_index], |
280b713b EA |
1014 | shmem_page_offset, |
1015 | user_pages[data_page_index], | |
1016 | data_page_offset, | |
99a03df5 CW |
1017 | page_length, |
1018 | 0); | |
1019 | } else { | |
1020 | slow_shmem_copy(obj_priv->pages[shmem_page_index], | |
1021 | shmem_page_offset, | |
1022 | user_pages[data_page_index], | |
1023 | data_page_offset, | |
1024 | page_length); | |
280b713b | 1025 | } |
40123c1f EA |
1026 | |
1027 | remain -= page_length; | |
1028 | data_ptr += page_length; | |
1029 | offset += page_length; | |
673a394b EA |
1030 | } |
1031 | ||
fbd5a26d | 1032 | out: |
40123c1f EA |
1033 | for (i = 0; i < pinned_pages; i++) |
1034 | page_cache_release(user_pages[i]); | |
8e7d2b2c | 1035 | drm_free_large(user_pages); |
673a394b | 1036 | |
40123c1f | 1037 | return ret; |
673a394b EA |
1038 | } |
1039 | ||
1040 | /** | |
1041 | * Writes data to the object referenced by handle. | |
1042 | * | |
1043 | * On error, the contents of the buffer that were to be modified are undefined. | |
1044 | */ | |
1045 | int | |
1046 | i915_gem_pwrite_ioctl(struct drm_device *dev, void *data, | |
fbd5a26d | 1047 | struct drm_file *file) |
673a394b EA |
1048 | { |
1049 | struct drm_i915_gem_pwrite *args = data; | |
1050 | struct drm_gem_object *obj; | |
1051 | struct drm_i915_gem_object *obj_priv; | |
1052 | int ret = 0; | |
1053 | ||
fbd5a26d | 1054 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 1055 | if (ret) |
fbd5a26d | 1056 | return ret; |
1d7cfea1 CW |
1057 | |
1058 | obj = drm_gem_object_lookup(dev, file, args->handle); | |
1059 | if (obj == NULL) { | |
1060 | ret = -ENOENT; | |
1061 | goto unlock; | |
fbd5a26d | 1062 | } |
23010e43 | 1063 | obj_priv = to_intel_bo(obj); |
673a394b | 1064 | |
fbd5a26d | 1065 | |
7dcd2499 CW |
1066 | /* Bounds check destination. */ |
1067 | if (args->offset > obj->size || args->size > obj->size - args->offset) { | |
ce9d419d | 1068 | ret = -EINVAL; |
35b62a89 | 1069 | goto out; |
ce9d419d CW |
1070 | } |
1071 | ||
35b62a89 CW |
1072 | if (args->size == 0) |
1073 | goto out; | |
1074 | ||
ce9d419d CW |
1075 | if (!access_ok(VERIFY_READ, |
1076 | (char __user *)(uintptr_t)args->data_ptr, | |
1077 | args->size)) { | |
1078 | ret = -EFAULT; | |
35b62a89 | 1079 | goto out; |
673a394b EA |
1080 | } |
1081 | ||
b5e4feb6 CW |
1082 | ret = fault_in_pages_readable((char __user *)(uintptr_t)args->data_ptr, |
1083 | args->size); | |
1084 | if (ret) { | |
1085 | ret = -EFAULT; | |
1086 | goto out; | |
673a394b EA |
1087 | } |
1088 | ||
1089 | /* We can only do the GTT pwrite on untiled buffers, as otherwise | |
1090 | * it would end up going through the fenced access, and we'll get | |
1091 | * different detiling behavior between reading and writing. | |
1092 | * pread/pwrite currently are reading and writing from the CPU | |
1093 | * perspective, requiring manual detiling by the client. | |
1094 | */ | |
71acb5eb | 1095 | if (obj_priv->phys_obj) |
fbd5a26d | 1096 | ret = i915_gem_phys_pwrite(dev, obj, args, file); |
71acb5eb | 1097 | else if (obj_priv->tiling_mode == I915_TILING_NONE && |
5cdf5881 | 1098 | obj_priv->gtt_space && |
9b8c4a0b | 1099 | obj->write_domain != I915_GEM_DOMAIN_CPU) { |
920afa77 | 1100 | ret = i915_gem_object_pin(obj, 0, true); |
fbd5a26d CW |
1101 | if (ret) |
1102 | goto out; | |
1103 | ||
1104 | ret = i915_gem_object_set_to_gtt_domain(obj, 1); | |
1105 | if (ret) | |
1106 | goto out_unpin; | |
1107 | ||
1108 | ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file); | |
1109 | if (ret == -EFAULT) | |
1110 | ret = i915_gem_gtt_pwrite_slow(dev, obj, args, file); | |
1111 | ||
1112 | out_unpin: | |
1113 | i915_gem_object_unpin(obj); | |
40123c1f | 1114 | } else { |
fbd5a26d CW |
1115 | ret = i915_gem_object_get_pages_or_evict(obj); |
1116 | if (ret) | |
1117 | goto out; | |
673a394b | 1118 | |
fbd5a26d CW |
1119 | ret = i915_gem_object_set_to_cpu_domain(obj, 1); |
1120 | if (ret) | |
1121 | goto out_put; | |
673a394b | 1122 | |
fbd5a26d CW |
1123 | ret = -EFAULT; |
1124 | if (!i915_gem_object_needs_bit17_swizzle(obj)) | |
1125 | ret = i915_gem_shmem_pwrite_fast(dev, obj, args, file); | |
1126 | if (ret == -EFAULT) | |
1127 | ret = i915_gem_shmem_pwrite_slow(dev, obj, args, file); | |
1128 | ||
1129 | out_put: | |
1130 | i915_gem_object_put_pages(obj); | |
1131 | } | |
673a394b | 1132 | |
35b62a89 | 1133 | out: |
fbd5a26d | 1134 | drm_gem_object_unreference(obj); |
1d7cfea1 | 1135 | unlock: |
fbd5a26d | 1136 | mutex_unlock(&dev->struct_mutex); |
673a394b EA |
1137 | return ret; |
1138 | } | |
1139 | ||
1140 | /** | |
2ef7eeaa EA |
1141 | * Called when user space prepares to use an object with the CPU, either |
1142 | * through the mmap ioctl's mapping or a GTT mapping. | |
673a394b EA |
1143 | */ |
1144 | int | |
1145 | i915_gem_set_domain_ioctl(struct drm_device *dev, void *data, | |
1146 | struct drm_file *file_priv) | |
1147 | { | |
a09ba7fa | 1148 | struct drm_i915_private *dev_priv = dev->dev_private; |
673a394b EA |
1149 | struct drm_i915_gem_set_domain *args = data; |
1150 | struct drm_gem_object *obj; | |
652c393a | 1151 | struct drm_i915_gem_object *obj_priv; |
2ef7eeaa EA |
1152 | uint32_t read_domains = args->read_domains; |
1153 | uint32_t write_domain = args->write_domain; | |
673a394b EA |
1154 | int ret; |
1155 | ||
1156 | if (!(dev->driver->driver_features & DRIVER_GEM)) | |
1157 | return -ENODEV; | |
1158 | ||
2ef7eeaa | 1159 | /* Only handle setting domains to types used by the CPU. */ |
21d509e3 | 1160 | if (write_domain & I915_GEM_GPU_DOMAINS) |
2ef7eeaa EA |
1161 | return -EINVAL; |
1162 | ||
21d509e3 | 1163 | if (read_domains & I915_GEM_GPU_DOMAINS) |
2ef7eeaa EA |
1164 | return -EINVAL; |
1165 | ||
1166 | /* Having something in the write domain implies it's in the read | |
1167 | * domain, and only that read domain. Enforce that in the request. | |
1168 | */ | |
1169 | if (write_domain != 0 && read_domains != write_domain) | |
1170 | return -EINVAL; | |
1171 | ||
76c1dec1 | 1172 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 1173 | if (ret) |
76c1dec1 | 1174 | return ret; |
1d7cfea1 | 1175 | |
673a394b | 1176 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); |
1d7cfea1 CW |
1177 | if (obj == NULL) { |
1178 | ret = -ENOENT; | |
1179 | goto unlock; | |
76c1dec1 | 1180 | } |
23010e43 | 1181 | obj_priv = to_intel_bo(obj); |
673a394b | 1182 | |
652c393a JB |
1183 | intel_mark_busy(dev, obj); |
1184 | ||
2ef7eeaa EA |
1185 | if (read_domains & I915_GEM_DOMAIN_GTT) { |
1186 | ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0); | |
02354392 | 1187 | |
a09ba7fa EA |
1188 | /* Update the LRU on the fence for the CPU access that's |
1189 | * about to occur. | |
1190 | */ | |
1191 | if (obj_priv->fence_reg != I915_FENCE_REG_NONE) { | |
007cc8ac DV |
1192 | struct drm_i915_fence_reg *reg = |
1193 | &dev_priv->fence_regs[obj_priv->fence_reg]; | |
1194 | list_move_tail(®->lru_list, | |
a09ba7fa EA |
1195 | &dev_priv->mm.fence_list); |
1196 | } | |
1197 | ||
02354392 EA |
1198 | /* Silently promote "you're not bound, there was nothing to do" |
1199 | * to success, since the client was just asking us to | |
1200 | * make sure everything was done. | |
1201 | */ | |
1202 | if (ret == -EINVAL) | |
1203 | ret = 0; | |
2ef7eeaa | 1204 | } else { |
e47c68e9 | 1205 | ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0); |
2ef7eeaa EA |
1206 | } |
1207 | ||
7d1c4804 CW |
1208 | /* Maintain LRU order of "inactive" objects */ |
1209 | if (ret == 0 && i915_gem_object_is_inactive(obj_priv)) | |
69dc4987 | 1210 | list_move_tail(&obj_priv->mm_list, &dev_priv->mm.inactive_list); |
7d1c4804 | 1211 | |
673a394b | 1212 | drm_gem_object_unreference(obj); |
1d7cfea1 | 1213 | unlock: |
673a394b EA |
1214 | mutex_unlock(&dev->struct_mutex); |
1215 | return ret; | |
1216 | } | |
1217 | ||
1218 | /** | |
1219 | * Called when user space has done writes to this buffer | |
1220 | */ | |
1221 | int | |
1222 | i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data, | |
1223 | struct drm_file *file_priv) | |
1224 | { | |
1225 | struct drm_i915_gem_sw_finish *args = data; | |
1226 | struct drm_gem_object *obj; | |
673a394b EA |
1227 | int ret = 0; |
1228 | ||
1229 | if (!(dev->driver->driver_features & DRIVER_GEM)) | |
1230 | return -ENODEV; | |
1231 | ||
76c1dec1 | 1232 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 1233 | if (ret) |
76c1dec1 | 1234 | return ret; |
1d7cfea1 | 1235 | |
673a394b EA |
1236 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); |
1237 | if (obj == NULL) { | |
1d7cfea1 CW |
1238 | ret = -ENOENT; |
1239 | goto unlock; | |
673a394b EA |
1240 | } |
1241 | ||
673a394b | 1242 | /* Pinned buffers may be scanout, so flush the cache */ |
3d2a812a | 1243 | if (to_intel_bo(obj)->pin_count) |
e47c68e9 EA |
1244 | i915_gem_object_flush_cpu_write_domain(obj); |
1245 | ||
673a394b | 1246 | drm_gem_object_unreference(obj); |
1d7cfea1 | 1247 | unlock: |
673a394b EA |
1248 | mutex_unlock(&dev->struct_mutex); |
1249 | return ret; | |
1250 | } | |
1251 | ||
1252 | /** | |
1253 | * Maps the contents of an object, returning the address it is mapped | |
1254 | * into. | |
1255 | * | |
1256 | * While the mapping holds a reference on the contents of the object, it doesn't | |
1257 | * imply a ref on the object itself. | |
1258 | */ | |
1259 | int | |
1260 | i915_gem_mmap_ioctl(struct drm_device *dev, void *data, | |
1261 | struct drm_file *file_priv) | |
1262 | { | |
da761a6e | 1263 | struct drm_i915_private *dev_priv = dev->dev_private; |
673a394b EA |
1264 | struct drm_i915_gem_mmap *args = data; |
1265 | struct drm_gem_object *obj; | |
1266 | loff_t offset; | |
1267 | unsigned long addr; | |
1268 | ||
1269 | if (!(dev->driver->driver_features & DRIVER_GEM)) | |
1270 | return -ENODEV; | |
1271 | ||
1272 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); | |
1273 | if (obj == NULL) | |
bf79cb91 | 1274 | return -ENOENT; |
673a394b | 1275 | |
da761a6e CW |
1276 | if (obj->size > dev_priv->mm.gtt_mappable_end) { |
1277 | drm_gem_object_unreference_unlocked(obj); | |
1278 | return -E2BIG; | |
1279 | } | |
1280 | ||
673a394b EA |
1281 | offset = args->offset; |
1282 | ||
1283 | down_write(¤t->mm->mmap_sem); | |
1284 | addr = do_mmap(obj->filp, 0, args->size, | |
1285 | PROT_READ | PROT_WRITE, MAP_SHARED, | |
1286 | args->offset); | |
1287 | up_write(¤t->mm->mmap_sem); | |
bc9025bd | 1288 | drm_gem_object_unreference_unlocked(obj); |
673a394b EA |
1289 | if (IS_ERR((void *)addr)) |
1290 | return addr; | |
1291 | ||
1292 | args->addr_ptr = (uint64_t) addr; | |
1293 | ||
1294 | return 0; | |
1295 | } | |
1296 | ||
de151cf6 JB |
1297 | /** |
1298 | * i915_gem_fault - fault a page into the GTT | |
1299 | * vma: VMA in question | |
1300 | * vmf: fault info | |
1301 | * | |
1302 | * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped | |
1303 | * from userspace. The fault handler takes care of binding the object to | |
1304 | * the GTT (if needed), allocating and programming a fence register (again, | |
1305 | * only if needed based on whether the old reg is still valid or the object | |
1306 | * is tiled) and inserting a new PTE into the faulting process. | |
1307 | * | |
1308 | * Note that the faulting process may involve evicting existing objects | |
1309 | * from the GTT and/or fence registers to make room. So performance may | |
1310 | * suffer if the GTT working set is large or there are few fence registers | |
1311 | * left. | |
1312 | */ | |
1313 | int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf) | |
1314 | { | |
1315 | struct drm_gem_object *obj = vma->vm_private_data; | |
1316 | struct drm_device *dev = obj->dev; | |
7d1c4804 | 1317 | drm_i915_private_t *dev_priv = dev->dev_private; |
23010e43 | 1318 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
de151cf6 JB |
1319 | pgoff_t page_offset; |
1320 | unsigned long pfn; | |
1321 | int ret = 0; | |
0f973f27 | 1322 | bool write = !!(vmf->flags & FAULT_FLAG_WRITE); |
de151cf6 JB |
1323 | |
1324 | /* We don't use vmf->pgoff since that has the fake offset */ | |
1325 | page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >> | |
1326 | PAGE_SHIFT; | |
1327 | ||
1328 | /* Now bind it into the GTT if needed */ | |
1329 | mutex_lock(&dev->struct_mutex); | |
fb7d516a | 1330 | BUG_ON(obj_priv->pin_count && !obj_priv->pin_mappable); |
16e809ac DV |
1331 | if (!i915_gem_object_cpu_accessible(obj_priv)) |
1332 | i915_gem_object_unbind(obj); | |
1333 | ||
de151cf6 | 1334 | if (!obj_priv->gtt_space) { |
920afa77 | 1335 | ret = i915_gem_object_bind_to_gtt(obj, 0, true); |
c715089f CW |
1336 | if (ret) |
1337 | goto unlock; | |
07f4f3e8 | 1338 | |
07f4f3e8 | 1339 | ret = i915_gem_object_set_to_gtt_domain(obj, write); |
c715089f CW |
1340 | if (ret) |
1341 | goto unlock; | |
de151cf6 JB |
1342 | } |
1343 | ||
fb7d516a DV |
1344 | if (!obj_priv->fault_mappable) { |
1345 | obj_priv->fault_mappable = true; | |
1346 | i915_gem_info_update_mappable(dev_priv, obj, true); | |
1347 | } | |
1348 | ||
de151cf6 | 1349 | /* Need a new fence register? */ |
a09ba7fa | 1350 | if (obj_priv->tiling_mode != I915_TILING_NONE) { |
2cf34d7b | 1351 | ret = i915_gem_object_get_fence_reg(obj, true); |
c715089f CW |
1352 | if (ret) |
1353 | goto unlock; | |
d9ddcb96 | 1354 | } |
de151cf6 | 1355 | |
7d1c4804 | 1356 | if (i915_gem_object_is_inactive(obj_priv)) |
69dc4987 | 1357 | list_move_tail(&obj_priv->mm_list, &dev_priv->mm.inactive_list); |
7d1c4804 | 1358 | |
de151cf6 JB |
1359 | pfn = ((dev->agp->base + obj_priv->gtt_offset) >> PAGE_SHIFT) + |
1360 | page_offset; | |
1361 | ||
1362 | /* Finally, remap it using the new GTT offset */ | |
1363 | ret = vm_insert_pfn(vma, (unsigned long)vmf->virtual_address, pfn); | |
c715089f | 1364 | unlock: |
de151cf6 JB |
1365 | mutex_unlock(&dev->struct_mutex); |
1366 | ||
1367 | switch (ret) { | |
c715089f CW |
1368 | case 0: |
1369 | case -ERESTARTSYS: | |
1370 | return VM_FAULT_NOPAGE; | |
de151cf6 JB |
1371 | case -ENOMEM: |
1372 | case -EAGAIN: | |
1373 | return VM_FAULT_OOM; | |
de151cf6 | 1374 | default: |
c715089f | 1375 | return VM_FAULT_SIGBUS; |
de151cf6 JB |
1376 | } |
1377 | } | |
1378 | ||
1379 | /** | |
1380 | * i915_gem_create_mmap_offset - create a fake mmap offset for an object | |
1381 | * @obj: obj in question | |
1382 | * | |
1383 | * GEM memory mapping works by handing back to userspace a fake mmap offset | |
1384 | * it can use in a subsequent mmap(2) call. The DRM core code then looks | |
1385 | * up the object based on the offset and sets up the various memory mapping | |
1386 | * structures. | |
1387 | * | |
1388 | * This routine allocates and attaches a fake offset for @obj. | |
1389 | */ | |
1390 | static int | |
1391 | i915_gem_create_mmap_offset(struct drm_gem_object *obj) | |
1392 | { | |
1393 | struct drm_device *dev = obj->dev; | |
1394 | struct drm_gem_mm *mm = dev->mm_private; | |
de151cf6 | 1395 | struct drm_map_list *list; |
f77d390c | 1396 | struct drm_local_map *map; |
de151cf6 JB |
1397 | int ret = 0; |
1398 | ||
1399 | /* Set the object up for mmap'ing */ | |
1400 | list = &obj->map_list; | |
9a298b2a | 1401 | list->map = kzalloc(sizeof(struct drm_map_list), GFP_KERNEL); |
de151cf6 JB |
1402 | if (!list->map) |
1403 | return -ENOMEM; | |
1404 | ||
1405 | map = list->map; | |
1406 | map->type = _DRM_GEM; | |
1407 | map->size = obj->size; | |
1408 | map->handle = obj; | |
1409 | ||
1410 | /* Get a DRM GEM mmap offset allocated... */ | |
1411 | list->file_offset_node = drm_mm_search_free(&mm->offset_manager, | |
1412 | obj->size / PAGE_SIZE, 0, 0); | |
1413 | if (!list->file_offset_node) { | |
1414 | DRM_ERROR("failed to allocate offset for bo %d\n", obj->name); | |
9e0ae534 | 1415 | ret = -ENOSPC; |
de151cf6 JB |
1416 | goto out_free_list; |
1417 | } | |
1418 | ||
1419 | list->file_offset_node = drm_mm_get_block(list->file_offset_node, | |
1420 | obj->size / PAGE_SIZE, 0); | |
1421 | if (!list->file_offset_node) { | |
1422 | ret = -ENOMEM; | |
1423 | goto out_free_list; | |
1424 | } | |
1425 | ||
1426 | list->hash.key = list->file_offset_node->start; | |
9e0ae534 CW |
1427 | ret = drm_ht_insert_item(&mm->offset_hash, &list->hash); |
1428 | if (ret) { | |
de151cf6 JB |
1429 | DRM_ERROR("failed to add to map hash\n"); |
1430 | goto out_free_mm; | |
1431 | } | |
1432 | ||
de151cf6 JB |
1433 | return 0; |
1434 | ||
1435 | out_free_mm: | |
1436 | drm_mm_put_block(list->file_offset_node); | |
1437 | out_free_list: | |
9a298b2a | 1438 | kfree(list->map); |
39a01d1f | 1439 | list->map = NULL; |
de151cf6 JB |
1440 | |
1441 | return ret; | |
1442 | } | |
1443 | ||
901782b2 CW |
1444 | /** |
1445 | * i915_gem_release_mmap - remove physical page mappings | |
1446 | * @obj: obj in question | |
1447 | * | |
af901ca1 | 1448 | * Preserve the reservation of the mmapping with the DRM core code, but |
901782b2 CW |
1449 | * relinquish ownership of the pages back to the system. |
1450 | * | |
1451 | * It is vital that we remove the page mapping if we have mapped a tiled | |
1452 | * object through the GTT and then lose the fence register due to | |
1453 | * resource pressure. Similarly if the object has been moved out of the | |
1454 | * aperture, than pages mapped into userspace must be revoked. Removing the | |
1455 | * mapping will then trigger a page fault on the next user access, allowing | |
1456 | * fixup by i915_gem_fault(). | |
1457 | */ | |
d05ca301 | 1458 | void |
901782b2 CW |
1459 | i915_gem_release_mmap(struct drm_gem_object *obj) |
1460 | { | |
1461 | struct drm_device *dev = obj->dev; | |
fb7d516a | 1462 | struct drm_i915_private *dev_priv = dev->dev_private; |
23010e43 | 1463 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
901782b2 | 1464 | |
39a01d1f | 1465 | if (unlikely(obj->map_list.map && dev->dev_mapping)) |
901782b2 | 1466 | unmap_mapping_range(dev->dev_mapping, |
39a01d1f CW |
1467 | (loff_t)obj->map_list.hash.key<<PAGE_SHIFT, |
1468 | obj->size, 1); | |
fb7d516a DV |
1469 | |
1470 | if (obj_priv->fault_mappable) { | |
1471 | obj_priv->fault_mappable = false; | |
1472 | i915_gem_info_update_mappable(dev_priv, obj, false); | |
1473 | } | |
901782b2 CW |
1474 | } |
1475 | ||
ab00b3e5 JB |
1476 | static void |
1477 | i915_gem_free_mmap_offset(struct drm_gem_object *obj) | |
1478 | { | |
1479 | struct drm_device *dev = obj->dev; | |
ab00b3e5 | 1480 | struct drm_gem_mm *mm = dev->mm_private; |
39a01d1f | 1481 | struct drm_map_list *list = &obj->map_list; |
ab00b3e5 | 1482 | |
ab00b3e5 | 1483 | drm_ht_remove_item(&mm->offset_hash, &list->hash); |
39a01d1f CW |
1484 | drm_mm_put_block(list->file_offset_node); |
1485 | kfree(list->map); | |
1486 | list->map = NULL; | |
ab00b3e5 JB |
1487 | } |
1488 | ||
de151cf6 JB |
1489 | /** |
1490 | * i915_gem_get_gtt_alignment - return required GTT alignment for an object | |
1491 | * @obj: object to check | |
1492 | * | |
1493 | * Return the required GTT alignment for an object, taking into account | |
1494 | * potential fence register mapping if needed. | |
1495 | */ | |
1496 | static uint32_t | |
1497 | i915_gem_get_gtt_alignment(struct drm_gem_object *obj) | |
1498 | { | |
1499 | struct drm_device *dev = obj->dev; | |
23010e43 | 1500 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
de151cf6 JB |
1501 | int start, i; |
1502 | ||
1503 | /* | |
1504 | * Minimum alignment is 4k (GTT page size), but might be greater | |
1505 | * if a fence register is needed for the object. | |
1506 | */ | |
a6c45cf0 | 1507 | if (INTEL_INFO(dev)->gen >= 4 || obj_priv->tiling_mode == I915_TILING_NONE) |
de151cf6 JB |
1508 | return 4096; |
1509 | ||
1510 | /* | |
1511 | * Previous chips need to be aligned to the size of the smallest | |
1512 | * fence register that can contain the object. | |
1513 | */ | |
a6c45cf0 | 1514 | if (INTEL_INFO(dev)->gen == 3) |
de151cf6 JB |
1515 | start = 1024*1024; |
1516 | else | |
1517 | start = 512*1024; | |
1518 | ||
1519 | for (i = start; i < obj->size; i <<= 1) | |
1520 | ; | |
1521 | ||
1522 | return i; | |
1523 | } | |
1524 | ||
1525 | /** | |
1526 | * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing | |
1527 | * @dev: DRM device | |
1528 | * @data: GTT mapping ioctl data | |
1529 | * @file_priv: GEM object info | |
1530 | * | |
1531 | * Simply returns the fake offset to userspace so it can mmap it. | |
1532 | * The mmap call will end up in drm_gem_mmap(), which will set things | |
1533 | * up so we can get faults in the handler above. | |
1534 | * | |
1535 | * The fault handler will take care of binding the object into the GTT | |
1536 | * (since it may have been evicted to make room for something), allocating | |
1537 | * a fence register, and mapping the appropriate aperture address into | |
1538 | * userspace. | |
1539 | */ | |
1540 | int | |
1541 | i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data, | |
1542 | struct drm_file *file_priv) | |
1543 | { | |
da761a6e | 1544 | struct drm_i915_private *dev_priv = dev->dev_private; |
de151cf6 | 1545 | struct drm_i915_gem_mmap_gtt *args = data; |
de151cf6 JB |
1546 | struct drm_gem_object *obj; |
1547 | struct drm_i915_gem_object *obj_priv; | |
1548 | int ret; | |
1549 | ||
1550 | if (!(dev->driver->driver_features & DRIVER_GEM)) | |
1551 | return -ENODEV; | |
1552 | ||
76c1dec1 | 1553 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 1554 | if (ret) |
76c1dec1 | 1555 | return ret; |
de151cf6 | 1556 | |
1d7cfea1 CW |
1557 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); |
1558 | if (obj == NULL) { | |
1559 | ret = -ENOENT; | |
1560 | goto unlock; | |
1561 | } | |
23010e43 | 1562 | obj_priv = to_intel_bo(obj); |
de151cf6 | 1563 | |
da761a6e CW |
1564 | if (obj->size > dev_priv->mm.gtt_mappable_end) { |
1565 | ret = -E2BIG; | |
1566 | goto unlock; | |
1567 | } | |
1568 | ||
ab18282d CW |
1569 | if (obj_priv->madv != I915_MADV_WILLNEED) { |
1570 | DRM_ERROR("Attempting to mmap a purgeable buffer\n"); | |
1d7cfea1 CW |
1571 | ret = -EINVAL; |
1572 | goto out; | |
ab18282d CW |
1573 | } |
1574 | ||
39a01d1f | 1575 | if (!obj->map_list.map) { |
de151cf6 | 1576 | ret = i915_gem_create_mmap_offset(obj); |
1d7cfea1 CW |
1577 | if (ret) |
1578 | goto out; | |
de151cf6 JB |
1579 | } |
1580 | ||
39a01d1f | 1581 | args->offset = (u64)obj->map_list.hash.key << PAGE_SHIFT; |
de151cf6 | 1582 | |
1d7cfea1 | 1583 | out: |
de151cf6 | 1584 | drm_gem_object_unreference(obj); |
1d7cfea1 | 1585 | unlock: |
de151cf6 | 1586 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 1587 | return ret; |
de151cf6 JB |
1588 | } |
1589 | ||
5cdf5881 | 1590 | static void |
856fa198 | 1591 | i915_gem_object_put_pages(struct drm_gem_object *obj) |
673a394b | 1592 | { |
23010e43 | 1593 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
673a394b EA |
1594 | int page_count = obj->size / PAGE_SIZE; |
1595 | int i; | |
1596 | ||
856fa198 | 1597 | BUG_ON(obj_priv->pages_refcount == 0); |
bb6baf76 | 1598 | BUG_ON(obj_priv->madv == __I915_MADV_PURGED); |
673a394b | 1599 | |
856fa198 EA |
1600 | if (--obj_priv->pages_refcount != 0) |
1601 | return; | |
673a394b | 1602 | |
280b713b EA |
1603 | if (obj_priv->tiling_mode != I915_TILING_NONE) |
1604 | i915_gem_object_save_bit_17_swizzle(obj); | |
1605 | ||
3ef94daa | 1606 | if (obj_priv->madv == I915_MADV_DONTNEED) |
13a05fd9 | 1607 | obj_priv->dirty = 0; |
3ef94daa CW |
1608 | |
1609 | for (i = 0; i < page_count; i++) { | |
3ef94daa CW |
1610 | if (obj_priv->dirty) |
1611 | set_page_dirty(obj_priv->pages[i]); | |
1612 | ||
1613 | if (obj_priv->madv == I915_MADV_WILLNEED) | |
856fa198 | 1614 | mark_page_accessed(obj_priv->pages[i]); |
3ef94daa CW |
1615 | |
1616 | page_cache_release(obj_priv->pages[i]); | |
1617 | } | |
673a394b EA |
1618 | obj_priv->dirty = 0; |
1619 | ||
8e7d2b2c | 1620 | drm_free_large(obj_priv->pages); |
856fa198 | 1621 | obj_priv->pages = NULL; |
673a394b EA |
1622 | } |
1623 | ||
a56ba56c CW |
1624 | static uint32_t |
1625 | i915_gem_next_request_seqno(struct drm_device *dev, | |
1626 | struct intel_ring_buffer *ring) | |
1627 | { | |
1628 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1629 | ||
1630 | ring->outstanding_lazy_request = true; | |
1631 | return dev_priv->next_seqno; | |
1632 | } | |
1633 | ||
673a394b | 1634 | static void |
617dbe27 | 1635 | i915_gem_object_move_to_active(struct drm_gem_object *obj, |
852835f3 | 1636 | struct intel_ring_buffer *ring) |
673a394b EA |
1637 | { |
1638 | struct drm_device *dev = obj->dev; | |
69dc4987 | 1639 | struct drm_i915_private *dev_priv = dev->dev_private; |
23010e43 | 1640 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
a56ba56c | 1641 | uint32_t seqno = i915_gem_next_request_seqno(dev, ring); |
617dbe27 | 1642 | |
852835f3 ZN |
1643 | BUG_ON(ring == NULL); |
1644 | obj_priv->ring = ring; | |
673a394b EA |
1645 | |
1646 | /* Add a reference if we're newly entering the active list. */ | |
1647 | if (!obj_priv->active) { | |
1648 | drm_gem_object_reference(obj); | |
1649 | obj_priv->active = 1; | |
1650 | } | |
e35a41de | 1651 | |
673a394b | 1652 | /* Move from whatever list we were on to the tail of execution. */ |
69dc4987 CW |
1653 | list_move_tail(&obj_priv->mm_list, &dev_priv->mm.active_list); |
1654 | list_move_tail(&obj_priv->ring_list, &ring->active_list); | |
ce44b0ea | 1655 | obj_priv->last_rendering_seqno = seqno; |
673a394b EA |
1656 | } |
1657 | ||
ce44b0ea EA |
1658 | static void |
1659 | i915_gem_object_move_to_flushing(struct drm_gem_object *obj) | |
1660 | { | |
1661 | struct drm_device *dev = obj->dev; | |
1662 | drm_i915_private_t *dev_priv = dev->dev_private; | |
23010e43 | 1663 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
ce44b0ea EA |
1664 | |
1665 | BUG_ON(!obj_priv->active); | |
69dc4987 CW |
1666 | list_move_tail(&obj_priv->mm_list, &dev_priv->mm.flushing_list); |
1667 | list_del_init(&obj_priv->ring_list); | |
ce44b0ea EA |
1668 | obj_priv->last_rendering_seqno = 0; |
1669 | } | |
673a394b | 1670 | |
963b4836 CW |
1671 | /* Immediately discard the backing storage */ |
1672 | static void | |
1673 | i915_gem_object_truncate(struct drm_gem_object *obj) | |
1674 | { | |
23010e43 | 1675 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
bb6baf76 | 1676 | struct inode *inode; |
963b4836 | 1677 | |
ae9fed6b CW |
1678 | /* Our goal here is to return as much of the memory as |
1679 | * is possible back to the system as we are called from OOM. | |
1680 | * To do this we must instruct the shmfs to drop all of its | |
1681 | * backing pages, *now*. Here we mirror the actions taken | |
1682 | * when by shmem_delete_inode() to release the backing store. | |
1683 | */ | |
bb6baf76 | 1684 | inode = obj->filp->f_path.dentry->d_inode; |
ae9fed6b CW |
1685 | truncate_inode_pages(inode->i_mapping, 0); |
1686 | if (inode->i_op->truncate_range) | |
1687 | inode->i_op->truncate_range(inode, 0, (loff_t)-1); | |
bb6baf76 CW |
1688 | |
1689 | obj_priv->madv = __I915_MADV_PURGED; | |
963b4836 CW |
1690 | } |
1691 | ||
1692 | static inline int | |
1693 | i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj_priv) | |
1694 | { | |
1695 | return obj_priv->madv == I915_MADV_DONTNEED; | |
1696 | } | |
1697 | ||
673a394b EA |
1698 | static void |
1699 | i915_gem_object_move_to_inactive(struct drm_gem_object *obj) | |
1700 | { | |
1701 | struct drm_device *dev = obj->dev; | |
1702 | drm_i915_private_t *dev_priv = dev->dev_private; | |
23010e43 | 1703 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
673a394b | 1704 | |
673a394b | 1705 | if (obj_priv->pin_count != 0) |
69dc4987 | 1706 | list_move_tail(&obj_priv->mm_list, &dev_priv->mm.pinned_list); |
673a394b | 1707 | else |
69dc4987 CW |
1708 | list_move_tail(&obj_priv->mm_list, &dev_priv->mm.inactive_list); |
1709 | list_del_init(&obj_priv->ring_list); | |
673a394b | 1710 | |
99fcb766 DV |
1711 | BUG_ON(!list_empty(&obj_priv->gpu_write_list)); |
1712 | ||
ce44b0ea | 1713 | obj_priv->last_rendering_seqno = 0; |
852835f3 | 1714 | obj_priv->ring = NULL; |
673a394b EA |
1715 | if (obj_priv->active) { |
1716 | obj_priv->active = 0; | |
1717 | drm_gem_object_unreference(obj); | |
1718 | } | |
23bc5982 | 1719 | WARN_ON(i915_verify_lists(dev)); |
673a394b EA |
1720 | } |
1721 | ||
63560396 DV |
1722 | static void |
1723 | i915_gem_process_flushing_list(struct drm_device *dev, | |
8a1a49f9 | 1724 | uint32_t flush_domains, |
852835f3 | 1725 | struct intel_ring_buffer *ring) |
63560396 DV |
1726 | { |
1727 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1728 | struct drm_i915_gem_object *obj_priv, *next; | |
1729 | ||
1730 | list_for_each_entry_safe(obj_priv, next, | |
64193406 | 1731 | &ring->gpu_write_list, |
63560396 | 1732 | gpu_write_list) { |
a8089e84 | 1733 | struct drm_gem_object *obj = &obj_priv->base; |
63560396 | 1734 | |
64193406 | 1735 | if (obj->write_domain & flush_domains) { |
63560396 DV |
1736 | uint32_t old_write_domain = obj->write_domain; |
1737 | ||
1738 | obj->write_domain = 0; | |
1739 | list_del_init(&obj_priv->gpu_write_list); | |
617dbe27 | 1740 | i915_gem_object_move_to_active(obj, ring); |
63560396 DV |
1741 | |
1742 | /* update the fence lru list */ | |
007cc8ac DV |
1743 | if (obj_priv->fence_reg != I915_FENCE_REG_NONE) { |
1744 | struct drm_i915_fence_reg *reg = | |
1745 | &dev_priv->fence_regs[obj_priv->fence_reg]; | |
1746 | list_move_tail(®->lru_list, | |
63560396 | 1747 | &dev_priv->mm.fence_list); |
007cc8ac | 1748 | } |
63560396 DV |
1749 | |
1750 | trace_i915_gem_object_change_domain(obj, | |
1751 | obj->read_domains, | |
1752 | old_write_domain); | |
1753 | } | |
1754 | } | |
1755 | } | |
8187a2b7 | 1756 | |
3cce469c | 1757 | int |
8a1a49f9 | 1758 | i915_add_request(struct drm_device *dev, |
f787a5f5 | 1759 | struct drm_file *file, |
8dc5d147 | 1760 | struct drm_i915_gem_request *request, |
8a1a49f9 | 1761 | struct intel_ring_buffer *ring) |
673a394b EA |
1762 | { |
1763 | drm_i915_private_t *dev_priv = dev->dev_private; | |
f787a5f5 | 1764 | struct drm_i915_file_private *file_priv = NULL; |
673a394b EA |
1765 | uint32_t seqno; |
1766 | int was_empty; | |
3cce469c CW |
1767 | int ret; |
1768 | ||
1769 | BUG_ON(request == NULL); | |
673a394b | 1770 | |
f787a5f5 CW |
1771 | if (file != NULL) |
1772 | file_priv = file->driver_priv; | |
b962442e | 1773 | |
3cce469c CW |
1774 | ret = ring->add_request(ring, &seqno); |
1775 | if (ret) | |
1776 | return ret; | |
673a394b | 1777 | |
a56ba56c | 1778 | ring->outstanding_lazy_request = false; |
673a394b EA |
1779 | |
1780 | request->seqno = seqno; | |
852835f3 | 1781 | request->ring = ring; |
673a394b | 1782 | request->emitted_jiffies = jiffies; |
852835f3 ZN |
1783 | was_empty = list_empty(&ring->request_list); |
1784 | list_add_tail(&request->list, &ring->request_list); | |
1785 | ||
f787a5f5 | 1786 | if (file_priv) { |
1c25595f | 1787 | spin_lock(&file_priv->mm.lock); |
f787a5f5 | 1788 | request->file_priv = file_priv; |
b962442e | 1789 | list_add_tail(&request->client_list, |
f787a5f5 | 1790 | &file_priv->mm.request_list); |
1c25595f | 1791 | spin_unlock(&file_priv->mm.lock); |
b962442e | 1792 | } |
673a394b | 1793 | |
f65d9421 | 1794 | if (!dev_priv->mm.suspended) { |
b3b079db CW |
1795 | mod_timer(&dev_priv->hangcheck_timer, |
1796 | jiffies + msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)); | |
f65d9421 | 1797 | if (was_empty) |
b3b079db CW |
1798 | queue_delayed_work(dev_priv->wq, |
1799 | &dev_priv->mm.retire_work, HZ); | |
f65d9421 | 1800 | } |
3cce469c | 1801 | return 0; |
673a394b EA |
1802 | } |
1803 | ||
1804 | /** | |
1805 | * Command execution barrier | |
1806 | * | |
1807 | * Ensures that all commands in the ring are finished | |
1808 | * before signalling the CPU | |
1809 | */ | |
8a1a49f9 | 1810 | static void |
852835f3 | 1811 | i915_retire_commands(struct drm_device *dev, struct intel_ring_buffer *ring) |
673a394b | 1812 | { |
673a394b | 1813 | uint32_t flush_domains = 0; |
673a394b EA |
1814 | |
1815 | /* The sampler always gets flushed on i965 (sigh) */ | |
a6c45cf0 | 1816 | if (INTEL_INFO(dev)->gen >= 4) |
673a394b | 1817 | flush_domains |= I915_GEM_DOMAIN_SAMPLER; |
852835f3 | 1818 | |
78501eac | 1819 | ring->flush(ring, I915_GEM_DOMAIN_COMMAND, flush_domains); |
673a394b EA |
1820 | } |
1821 | ||
f787a5f5 CW |
1822 | static inline void |
1823 | i915_gem_request_remove_from_client(struct drm_i915_gem_request *request) | |
673a394b | 1824 | { |
1c25595f | 1825 | struct drm_i915_file_private *file_priv = request->file_priv; |
673a394b | 1826 | |
1c25595f CW |
1827 | if (!file_priv) |
1828 | return; | |
1c5d22f7 | 1829 | |
1c25595f CW |
1830 | spin_lock(&file_priv->mm.lock); |
1831 | list_del(&request->client_list); | |
1832 | request->file_priv = NULL; | |
1833 | spin_unlock(&file_priv->mm.lock); | |
673a394b | 1834 | } |
673a394b | 1835 | |
dfaae392 CW |
1836 | static void i915_gem_reset_ring_lists(struct drm_i915_private *dev_priv, |
1837 | struct intel_ring_buffer *ring) | |
9375e446 | 1838 | { |
dfaae392 CW |
1839 | while (!list_empty(&ring->request_list)) { |
1840 | struct drm_i915_gem_request *request; | |
673a394b | 1841 | |
dfaae392 CW |
1842 | request = list_first_entry(&ring->request_list, |
1843 | struct drm_i915_gem_request, | |
1844 | list); | |
de151cf6 | 1845 | |
dfaae392 | 1846 | list_del(&request->list); |
f787a5f5 | 1847 | i915_gem_request_remove_from_client(request); |
dfaae392 CW |
1848 | kfree(request); |
1849 | } | |
673a394b | 1850 | |
dfaae392 | 1851 | while (!list_empty(&ring->active_list)) { |
9375e446 CW |
1852 | struct drm_i915_gem_object *obj_priv; |
1853 | ||
dfaae392 | 1854 | obj_priv = list_first_entry(&ring->active_list, |
9375e446 | 1855 | struct drm_i915_gem_object, |
69dc4987 | 1856 | ring_list); |
9375e446 CW |
1857 | |
1858 | obj_priv->base.write_domain = 0; | |
dfaae392 | 1859 | list_del_init(&obj_priv->gpu_write_list); |
9375e446 | 1860 | i915_gem_object_move_to_inactive(&obj_priv->base); |
673a394b EA |
1861 | } |
1862 | } | |
1863 | ||
069efc1d | 1864 | void i915_gem_reset(struct drm_device *dev) |
673a394b | 1865 | { |
77f01230 CW |
1866 | struct drm_i915_private *dev_priv = dev->dev_private; |
1867 | struct drm_i915_gem_object *obj_priv; | |
069efc1d | 1868 | int i; |
673a394b | 1869 | |
dfaae392 | 1870 | i915_gem_reset_ring_lists(dev_priv, &dev_priv->render_ring); |
87acb0a5 | 1871 | i915_gem_reset_ring_lists(dev_priv, &dev_priv->bsd_ring); |
549f7365 | 1872 | i915_gem_reset_ring_lists(dev_priv, &dev_priv->blt_ring); |
dfaae392 CW |
1873 | |
1874 | /* Remove anything from the flushing lists. The GPU cache is likely | |
1875 | * to be lost on reset along with the data, so simply move the | |
1876 | * lost bo to the inactive list. | |
1877 | */ | |
1878 | while (!list_empty(&dev_priv->mm.flushing_list)) { | |
1879 | obj_priv = list_first_entry(&dev_priv->mm.flushing_list, | |
1880 | struct drm_i915_gem_object, | |
69dc4987 | 1881 | mm_list); |
dfaae392 CW |
1882 | |
1883 | obj_priv->base.write_domain = 0; | |
1884 | list_del_init(&obj_priv->gpu_write_list); | |
1885 | i915_gem_object_move_to_inactive(&obj_priv->base); | |
1886 | } | |
1887 | ||
1888 | /* Move everything out of the GPU domains to ensure we do any | |
1889 | * necessary invalidation upon reuse. | |
1890 | */ | |
77f01230 CW |
1891 | list_for_each_entry(obj_priv, |
1892 | &dev_priv->mm.inactive_list, | |
69dc4987 | 1893 | mm_list) |
77f01230 CW |
1894 | { |
1895 | obj_priv->base.read_domains &= ~I915_GEM_GPU_DOMAINS; | |
1896 | } | |
069efc1d CW |
1897 | |
1898 | /* The fence registers are invalidated so clear them out */ | |
1899 | for (i = 0; i < 16; i++) { | |
1900 | struct drm_i915_fence_reg *reg; | |
1901 | ||
1902 | reg = &dev_priv->fence_regs[i]; | |
1903 | if (!reg->obj) | |
1904 | continue; | |
1905 | ||
1906 | i915_gem_clear_fence_reg(reg->obj); | |
1907 | } | |
673a394b EA |
1908 | } |
1909 | ||
1910 | /** | |
1911 | * This function clears the request list as sequence numbers are passed. | |
1912 | */ | |
b09a1fec CW |
1913 | static void |
1914 | i915_gem_retire_requests_ring(struct drm_device *dev, | |
1915 | struct intel_ring_buffer *ring) | |
673a394b EA |
1916 | { |
1917 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1918 | uint32_t seqno; | |
1919 | ||
b84d5f0c CW |
1920 | if (!ring->status_page.page_addr || |
1921 | list_empty(&ring->request_list)) | |
6c0594a3 KW |
1922 | return; |
1923 | ||
23bc5982 | 1924 | WARN_ON(i915_verify_lists(dev)); |
673a394b | 1925 | |
78501eac | 1926 | seqno = ring->get_seqno(ring); |
852835f3 | 1927 | while (!list_empty(&ring->request_list)) { |
673a394b | 1928 | struct drm_i915_gem_request *request; |
673a394b | 1929 | |
852835f3 | 1930 | request = list_first_entry(&ring->request_list, |
673a394b EA |
1931 | struct drm_i915_gem_request, |
1932 | list); | |
673a394b | 1933 | |
dfaae392 | 1934 | if (!i915_seqno_passed(seqno, request->seqno)) |
b84d5f0c CW |
1935 | break; |
1936 | ||
1937 | trace_i915_gem_request_retire(dev, request->seqno); | |
1938 | ||
1939 | list_del(&request->list); | |
f787a5f5 | 1940 | i915_gem_request_remove_from_client(request); |
b84d5f0c CW |
1941 | kfree(request); |
1942 | } | |
673a394b | 1943 | |
b84d5f0c CW |
1944 | /* Move any buffers on the active list that are no longer referenced |
1945 | * by the ringbuffer to the flushing/inactive lists as appropriate. | |
1946 | */ | |
1947 | while (!list_empty(&ring->active_list)) { | |
1948 | struct drm_gem_object *obj; | |
1949 | struct drm_i915_gem_object *obj_priv; | |
1950 | ||
1951 | obj_priv = list_first_entry(&ring->active_list, | |
1952 | struct drm_i915_gem_object, | |
69dc4987 | 1953 | ring_list); |
673a394b | 1954 | |
dfaae392 | 1955 | if (!i915_seqno_passed(seqno, obj_priv->last_rendering_seqno)) |
673a394b | 1956 | break; |
b84d5f0c CW |
1957 | |
1958 | obj = &obj_priv->base; | |
b84d5f0c CW |
1959 | if (obj->write_domain != 0) |
1960 | i915_gem_object_move_to_flushing(obj); | |
1961 | else | |
1962 | i915_gem_object_move_to_inactive(obj); | |
673a394b | 1963 | } |
9d34e5db CW |
1964 | |
1965 | if (unlikely (dev_priv->trace_irq_seqno && | |
1966 | i915_seqno_passed(dev_priv->trace_irq_seqno, seqno))) { | |
78501eac | 1967 | ring->user_irq_put(ring); |
9d34e5db CW |
1968 | dev_priv->trace_irq_seqno = 0; |
1969 | } | |
23bc5982 CW |
1970 | |
1971 | WARN_ON(i915_verify_lists(dev)); | |
673a394b EA |
1972 | } |
1973 | ||
b09a1fec CW |
1974 | void |
1975 | i915_gem_retire_requests(struct drm_device *dev) | |
1976 | { | |
1977 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1978 | ||
be72615b CW |
1979 | if (!list_empty(&dev_priv->mm.deferred_free_list)) { |
1980 | struct drm_i915_gem_object *obj_priv, *tmp; | |
1981 | ||
1982 | /* We must be careful that during unbind() we do not | |
1983 | * accidentally infinitely recurse into retire requests. | |
1984 | * Currently: | |
1985 | * retire -> free -> unbind -> wait -> retire_ring | |
1986 | */ | |
1987 | list_for_each_entry_safe(obj_priv, tmp, | |
1988 | &dev_priv->mm.deferred_free_list, | |
69dc4987 | 1989 | mm_list) |
be72615b CW |
1990 | i915_gem_free_object_tail(&obj_priv->base); |
1991 | } | |
1992 | ||
b09a1fec | 1993 | i915_gem_retire_requests_ring(dev, &dev_priv->render_ring); |
87acb0a5 | 1994 | i915_gem_retire_requests_ring(dev, &dev_priv->bsd_ring); |
549f7365 | 1995 | i915_gem_retire_requests_ring(dev, &dev_priv->blt_ring); |
b09a1fec CW |
1996 | } |
1997 | ||
75ef9da2 | 1998 | static void |
673a394b EA |
1999 | i915_gem_retire_work_handler(struct work_struct *work) |
2000 | { | |
2001 | drm_i915_private_t *dev_priv; | |
2002 | struct drm_device *dev; | |
2003 | ||
2004 | dev_priv = container_of(work, drm_i915_private_t, | |
2005 | mm.retire_work.work); | |
2006 | dev = dev_priv->dev; | |
2007 | ||
891b48cf CW |
2008 | /* Come back later if the device is busy... */ |
2009 | if (!mutex_trylock(&dev->struct_mutex)) { | |
2010 | queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ); | |
2011 | return; | |
2012 | } | |
2013 | ||
b09a1fec | 2014 | i915_gem_retire_requests(dev); |
d1b851fc | 2015 | |
6dbe2772 | 2016 | if (!dev_priv->mm.suspended && |
d1b851fc | 2017 | (!list_empty(&dev_priv->render_ring.request_list) || |
549f7365 CW |
2018 | !list_empty(&dev_priv->bsd_ring.request_list) || |
2019 | !list_empty(&dev_priv->blt_ring.request_list))) | |
9c9fe1f8 | 2020 | queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ); |
673a394b EA |
2021 | mutex_unlock(&dev->struct_mutex); |
2022 | } | |
2023 | ||
5a5a0c64 | 2024 | int |
852835f3 | 2025 | i915_do_wait_request(struct drm_device *dev, uint32_t seqno, |
8a1a49f9 | 2026 | bool interruptible, struct intel_ring_buffer *ring) |
673a394b EA |
2027 | { |
2028 | drm_i915_private_t *dev_priv = dev->dev_private; | |
802c7eb6 | 2029 | u32 ier; |
673a394b EA |
2030 | int ret = 0; |
2031 | ||
2032 | BUG_ON(seqno == 0); | |
2033 | ||
ba1234d1 | 2034 | if (atomic_read(&dev_priv->mm.wedged)) |
30dbf0c0 CW |
2035 | return -EAGAIN; |
2036 | ||
a56ba56c | 2037 | if (ring->outstanding_lazy_request) { |
3cce469c CW |
2038 | struct drm_i915_gem_request *request; |
2039 | ||
2040 | request = kzalloc(sizeof(*request), GFP_KERNEL); | |
2041 | if (request == NULL) | |
e35a41de | 2042 | return -ENOMEM; |
3cce469c CW |
2043 | |
2044 | ret = i915_add_request(dev, NULL, request, ring); | |
2045 | if (ret) { | |
2046 | kfree(request); | |
2047 | return ret; | |
2048 | } | |
2049 | ||
2050 | seqno = request->seqno; | |
e35a41de | 2051 | } |
a56ba56c | 2052 | BUG_ON(seqno == dev_priv->next_seqno); |
ffed1d09 | 2053 | |
78501eac | 2054 | if (!i915_seqno_passed(ring->get_seqno(ring), seqno)) { |
bad720ff | 2055 | if (HAS_PCH_SPLIT(dev)) |
036a4a7d ZW |
2056 | ier = I915_READ(DEIER) | I915_READ(GTIER); |
2057 | else | |
2058 | ier = I915_READ(IER); | |
802c7eb6 JB |
2059 | if (!ier) { |
2060 | DRM_ERROR("something (likely vbetool) disabled " | |
2061 | "interrupts, re-enabling\n"); | |
2062 | i915_driver_irq_preinstall(dev); | |
2063 | i915_driver_irq_postinstall(dev); | |
2064 | } | |
2065 | ||
1c5d22f7 CW |
2066 | trace_i915_gem_request_wait_begin(dev, seqno); |
2067 | ||
b2223497 | 2068 | ring->waiting_seqno = seqno; |
78501eac | 2069 | ring->user_irq_get(ring); |
48764bf4 | 2070 | if (interruptible) |
852835f3 | 2071 | ret = wait_event_interruptible(ring->irq_queue, |
78501eac | 2072 | i915_seqno_passed(ring->get_seqno(ring), seqno) |
852835f3 | 2073 | || atomic_read(&dev_priv->mm.wedged)); |
48764bf4 | 2074 | else |
852835f3 | 2075 | wait_event(ring->irq_queue, |
78501eac | 2076 | i915_seqno_passed(ring->get_seqno(ring), seqno) |
852835f3 | 2077 | || atomic_read(&dev_priv->mm.wedged)); |
48764bf4 | 2078 | |
78501eac | 2079 | ring->user_irq_put(ring); |
b2223497 | 2080 | ring->waiting_seqno = 0; |
1c5d22f7 CW |
2081 | |
2082 | trace_i915_gem_request_wait_end(dev, seqno); | |
673a394b | 2083 | } |
ba1234d1 | 2084 | if (atomic_read(&dev_priv->mm.wedged)) |
30dbf0c0 | 2085 | ret = -EAGAIN; |
673a394b EA |
2086 | |
2087 | if (ret && ret != -ERESTARTSYS) | |
8bff917c | 2088 | DRM_ERROR("%s returns %d (awaiting %d at %d, next %d)\n", |
78501eac | 2089 | __func__, ret, seqno, ring->get_seqno(ring), |
8bff917c | 2090 | dev_priv->next_seqno); |
673a394b EA |
2091 | |
2092 | /* Directly dispatch request retiring. While we have the work queue | |
2093 | * to handle this, the waiter on a request often wants an associated | |
2094 | * buffer to have made it to the inactive list, and we would need | |
2095 | * a separate wait queue to handle that. | |
2096 | */ | |
2097 | if (ret == 0) | |
b09a1fec | 2098 | i915_gem_retire_requests_ring(dev, ring); |
673a394b EA |
2099 | |
2100 | return ret; | |
2101 | } | |
2102 | ||
48764bf4 DV |
2103 | /** |
2104 | * Waits for a sequence number to be signaled, and cleans up the | |
2105 | * request and object lists appropriately for that event. | |
2106 | */ | |
2107 | static int | |
852835f3 | 2108 | i915_wait_request(struct drm_device *dev, uint32_t seqno, |
a56ba56c | 2109 | struct intel_ring_buffer *ring) |
48764bf4 | 2110 | { |
852835f3 | 2111 | return i915_do_wait_request(dev, seqno, 1, ring); |
48764bf4 DV |
2112 | } |
2113 | ||
20f0cd55 | 2114 | static void |
9220434a | 2115 | i915_gem_flush_ring(struct drm_device *dev, |
c78ec30b | 2116 | struct drm_file *file_priv, |
9220434a CW |
2117 | struct intel_ring_buffer *ring, |
2118 | uint32_t invalidate_domains, | |
2119 | uint32_t flush_domains) | |
2120 | { | |
78501eac | 2121 | ring->flush(ring, invalidate_domains, flush_domains); |
9220434a CW |
2122 | i915_gem_process_flushing_list(dev, flush_domains, ring); |
2123 | } | |
2124 | ||
8187a2b7 ZN |
2125 | static void |
2126 | i915_gem_flush(struct drm_device *dev, | |
c78ec30b | 2127 | struct drm_file *file_priv, |
8187a2b7 | 2128 | uint32_t invalidate_domains, |
9220434a CW |
2129 | uint32_t flush_domains, |
2130 | uint32_t flush_rings) | |
8187a2b7 ZN |
2131 | { |
2132 | drm_i915_private_t *dev_priv = dev->dev_private; | |
8bff917c | 2133 | |
8187a2b7 ZN |
2134 | if (flush_domains & I915_GEM_DOMAIN_CPU) |
2135 | drm_agp_chipset_flush(dev); | |
8bff917c | 2136 | |
9220434a CW |
2137 | if ((flush_domains | invalidate_domains) & I915_GEM_GPU_DOMAINS) { |
2138 | if (flush_rings & RING_RENDER) | |
c78ec30b | 2139 | i915_gem_flush_ring(dev, file_priv, |
9220434a CW |
2140 | &dev_priv->render_ring, |
2141 | invalidate_domains, flush_domains); | |
2142 | if (flush_rings & RING_BSD) | |
c78ec30b | 2143 | i915_gem_flush_ring(dev, file_priv, |
9220434a CW |
2144 | &dev_priv->bsd_ring, |
2145 | invalidate_domains, flush_domains); | |
549f7365 CW |
2146 | if (flush_rings & RING_BLT) |
2147 | i915_gem_flush_ring(dev, file_priv, | |
2148 | &dev_priv->blt_ring, | |
2149 | invalidate_domains, flush_domains); | |
9220434a | 2150 | } |
8187a2b7 ZN |
2151 | } |
2152 | ||
673a394b EA |
2153 | /** |
2154 | * Ensures that all rendering to the object has completed and the object is | |
2155 | * safe to unbind from the GTT or access from the CPU. | |
2156 | */ | |
2157 | static int | |
2cf34d7b CW |
2158 | i915_gem_object_wait_rendering(struct drm_gem_object *obj, |
2159 | bool interruptible) | |
673a394b EA |
2160 | { |
2161 | struct drm_device *dev = obj->dev; | |
23010e43 | 2162 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
673a394b EA |
2163 | int ret; |
2164 | ||
e47c68e9 EA |
2165 | /* This function only exists to support waiting for existing rendering, |
2166 | * not for emitting required flushes. | |
673a394b | 2167 | */ |
e47c68e9 | 2168 | BUG_ON((obj->write_domain & I915_GEM_GPU_DOMAINS) != 0); |
673a394b EA |
2169 | |
2170 | /* If there is rendering queued on the buffer being evicted, wait for | |
2171 | * it. | |
2172 | */ | |
2173 | if (obj_priv->active) { | |
2cf34d7b CW |
2174 | ret = i915_do_wait_request(dev, |
2175 | obj_priv->last_rendering_seqno, | |
2176 | interruptible, | |
2177 | obj_priv->ring); | |
2178 | if (ret) | |
673a394b EA |
2179 | return ret; |
2180 | } | |
2181 | ||
2182 | return 0; | |
2183 | } | |
2184 | ||
2185 | /** | |
2186 | * Unbinds an object from the GTT aperture. | |
2187 | */ | |
0f973f27 | 2188 | int |
673a394b EA |
2189 | i915_gem_object_unbind(struct drm_gem_object *obj) |
2190 | { | |
2191 | struct drm_device *dev = obj->dev; | |
73aa808f | 2192 | struct drm_i915_private *dev_priv = dev->dev_private; |
23010e43 | 2193 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
673a394b EA |
2194 | int ret = 0; |
2195 | ||
673a394b EA |
2196 | if (obj_priv->gtt_space == NULL) |
2197 | return 0; | |
2198 | ||
2199 | if (obj_priv->pin_count != 0) { | |
2200 | DRM_ERROR("Attempting to unbind pinned buffer\n"); | |
2201 | return -EINVAL; | |
2202 | } | |
2203 | ||
5323fd04 EA |
2204 | /* blow away mappings if mapped through GTT */ |
2205 | i915_gem_release_mmap(obj); | |
2206 | ||
673a394b EA |
2207 | /* Move the object to the CPU domain to ensure that |
2208 | * any possible CPU writes while it's not in the GTT | |
2209 | * are flushed when we go to remap it. This will | |
2210 | * also ensure that all pending GPU writes are finished | |
2211 | * before we unbind. | |
2212 | */ | |
e47c68e9 | 2213 | ret = i915_gem_object_set_to_cpu_domain(obj, 1); |
8dc1775d | 2214 | if (ret == -ERESTARTSYS) |
673a394b | 2215 | return ret; |
8dc1775d CW |
2216 | /* Continue on if we fail due to EIO, the GPU is hung so we |
2217 | * should be safe and we need to cleanup or else we might | |
2218 | * cause memory corruption through use-after-free. | |
2219 | */ | |
812ed492 CW |
2220 | if (ret) { |
2221 | i915_gem_clflush_object(obj); | |
2222 | obj->read_domains = obj->write_domain = I915_GEM_DOMAIN_CPU; | |
2223 | } | |
673a394b | 2224 | |
96b47b65 DV |
2225 | /* release the fence reg _after_ flushing */ |
2226 | if (obj_priv->fence_reg != I915_FENCE_REG_NONE) | |
2227 | i915_gem_clear_fence_reg(obj); | |
2228 | ||
73aa808f CW |
2229 | drm_unbind_agp(obj_priv->agp_mem); |
2230 | drm_free_agp(obj_priv->agp_mem, obj->size / PAGE_SIZE); | |
673a394b | 2231 | |
856fa198 | 2232 | i915_gem_object_put_pages(obj); |
a32808c0 | 2233 | BUG_ON(obj_priv->pages_refcount); |
673a394b | 2234 | |
fb7d516a | 2235 | i915_gem_info_remove_gtt(dev_priv, obj); |
69dc4987 | 2236 | list_del_init(&obj_priv->mm_list); |
673a394b | 2237 | |
73aa808f CW |
2238 | drm_mm_put_block(obj_priv->gtt_space); |
2239 | obj_priv->gtt_space = NULL; | |
9af90d19 | 2240 | obj_priv->gtt_offset = 0; |
673a394b | 2241 | |
963b4836 CW |
2242 | if (i915_gem_object_is_purgeable(obj_priv)) |
2243 | i915_gem_object_truncate(obj); | |
2244 | ||
1c5d22f7 CW |
2245 | trace_i915_gem_object_unbind(obj); |
2246 | ||
8dc1775d | 2247 | return ret; |
673a394b EA |
2248 | } |
2249 | ||
a56ba56c CW |
2250 | static int i915_ring_idle(struct drm_device *dev, |
2251 | struct intel_ring_buffer *ring) | |
2252 | { | |
64193406 CW |
2253 | if (list_empty(&ring->gpu_write_list)) |
2254 | return 0; | |
2255 | ||
a56ba56c CW |
2256 | i915_gem_flush_ring(dev, NULL, ring, |
2257 | I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS); | |
2258 | return i915_wait_request(dev, | |
2259 | i915_gem_next_request_seqno(dev, ring), | |
2260 | ring); | |
2261 | } | |
2262 | ||
b47eb4a2 | 2263 | int |
4df2faf4 DV |
2264 | i915_gpu_idle(struct drm_device *dev) |
2265 | { | |
2266 | drm_i915_private_t *dev_priv = dev->dev_private; | |
2267 | bool lists_empty; | |
852835f3 | 2268 | int ret; |
4df2faf4 | 2269 | |
d1b851fc ZN |
2270 | lists_empty = (list_empty(&dev_priv->mm.flushing_list) && |
2271 | list_empty(&dev_priv->render_ring.active_list) && | |
549f7365 CW |
2272 | list_empty(&dev_priv->bsd_ring.active_list) && |
2273 | list_empty(&dev_priv->blt_ring.active_list)); | |
4df2faf4 DV |
2274 | if (lists_empty) |
2275 | return 0; | |
2276 | ||
2277 | /* Flush everything onto the inactive list. */ | |
a56ba56c | 2278 | ret = i915_ring_idle(dev, &dev_priv->render_ring); |
8a1a49f9 DV |
2279 | if (ret) |
2280 | return ret; | |
d1b851fc | 2281 | |
87acb0a5 CW |
2282 | ret = i915_ring_idle(dev, &dev_priv->bsd_ring); |
2283 | if (ret) | |
2284 | return ret; | |
d1b851fc | 2285 | |
549f7365 CW |
2286 | ret = i915_ring_idle(dev, &dev_priv->blt_ring); |
2287 | if (ret) | |
2288 | return ret; | |
4df2faf4 | 2289 | |
8a1a49f9 | 2290 | return 0; |
4df2faf4 DV |
2291 | } |
2292 | ||
5cdf5881 | 2293 | static int |
4bdadb97 CW |
2294 | i915_gem_object_get_pages(struct drm_gem_object *obj, |
2295 | gfp_t gfpmask) | |
673a394b | 2296 | { |
23010e43 | 2297 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
673a394b EA |
2298 | int page_count, i; |
2299 | struct address_space *mapping; | |
2300 | struct inode *inode; | |
2301 | struct page *page; | |
673a394b | 2302 | |
778c3544 DV |
2303 | BUG_ON(obj_priv->pages_refcount |
2304 | == DRM_I915_GEM_OBJECT_MAX_PAGES_REFCOUNT); | |
2305 | ||
856fa198 | 2306 | if (obj_priv->pages_refcount++ != 0) |
673a394b EA |
2307 | return 0; |
2308 | ||
2309 | /* Get the list of pages out of our struct file. They'll be pinned | |
2310 | * at this point until we release them. | |
2311 | */ | |
2312 | page_count = obj->size / PAGE_SIZE; | |
856fa198 | 2313 | BUG_ON(obj_priv->pages != NULL); |
8e7d2b2c | 2314 | obj_priv->pages = drm_calloc_large(page_count, sizeof(struct page *)); |
856fa198 | 2315 | if (obj_priv->pages == NULL) { |
856fa198 | 2316 | obj_priv->pages_refcount--; |
673a394b EA |
2317 | return -ENOMEM; |
2318 | } | |
2319 | ||
2320 | inode = obj->filp->f_path.dentry->d_inode; | |
2321 | mapping = inode->i_mapping; | |
2322 | for (i = 0; i < page_count; i++) { | |
4bdadb97 | 2323 | page = read_cache_page_gfp(mapping, i, |
985b823b | 2324 | GFP_HIGHUSER | |
4bdadb97 | 2325 | __GFP_COLD | |
cd9f040d | 2326 | __GFP_RECLAIMABLE | |
4bdadb97 | 2327 | gfpmask); |
1f2b1013 CW |
2328 | if (IS_ERR(page)) |
2329 | goto err_pages; | |
2330 | ||
856fa198 | 2331 | obj_priv->pages[i] = page; |
673a394b | 2332 | } |
280b713b EA |
2333 | |
2334 | if (obj_priv->tiling_mode != I915_TILING_NONE) | |
2335 | i915_gem_object_do_bit_17_swizzle(obj); | |
2336 | ||
673a394b | 2337 | return 0; |
1f2b1013 CW |
2338 | |
2339 | err_pages: | |
2340 | while (i--) | |
2341 | page_cache_release(obj_priv->pages[i]); | |
2342 | ||
2343 | drm_free_large(obj_priv->pages); | |
2344 | obj_priv->pages = NULL; | |
2345 | obj_priv->pages_refcount--; | |
2346 | return PTR_ERR(page); | |
673a394b EA |
2347 | } |
2348 | ||
4e901fdc EA |
2349 | static void sandybridge_write_fence_reg(struct drm_i915_fence_reg *reg) |
2350 | { | |
2351 | struct drm_gem_object *obj = reg->obj; | |
2352 | struct drm_device *dev = obj->dev; | |
2353 | drm_i915_private_t *dev_priv = dev->dev_private; | |
23010e43 | 2354 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
4e901fdc EA |
2355 | int regnum = obj_priv->fence_reg; |
2356 | uint64_t val; | |
2357 | ||
2358 | val = (uint64_t)((obj_priv->gtt_offset + obj->size - 4096) & | |
2359 | 0xfffff000) << 32; | |
2360 | val |= obj_priv->gtt_offset & 0xfffff000; | |
2361 | val |= (uint64_t)((obj_priv->stride / 128) - 1) << | |
2362 | SANDYBRIDGE_FENCE_PITCH_SHIFT; | |
2363 | ||
2364 | if (obj_priv->tiling_mode == I915_TILING_Y) | |
2365 | val |= 1 << I965_FENCE_TILING_Y_SHIFT; | |
2366 | val |= I965_FENCE_REG_VALID; | |
2367 | ||
2368 | I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + (regnum * 8), val); | |
2369 | } | |
2370 | ||
de151cf6 JB |
2371 | static void i965_write_fence_reg(struct drm_i915_fence_reg *reg) |
2372 | { | |
2373 | struct drm_gem_object *obj = reg->obj; | |
2374 | struct drm_device *dev = obj->dev; | |
2375 | drm_i915_private_t *dev_priv = dev->dev_private; | |
23010e43 | 2376 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
de151cf6 JB |
2377 | int regnum = obj_priv->fence_reg; |
2378 | uint64_t val; | |
2379 | ||
2380 | val = (uint64_t)((obj_priv->gtt_offset + obj->size - 4096) & | |
2381 | 0xfffff000) << 32; | |
2382 | val |= obj_priv->gtt_offset & 0xfffff000; | |
2383 | val |= ((obj_priv->stride / 128) - 1) << I965_FENCE_PITCH_SHIFT; | |
2384 | if (obj_priv->tiling_mode == I915_TILING_Y) | |
2385 | val |= 1 << I965_FENCE_TILING_Y_SHIFT; | |
2386 | val |= I965_FENCE_REG_VALID; | |
2387 | ||
2388 | I915_WRITE64(FENCE_REG_965_0 + (regnum * 8), val); | |
2389 | } | |
2390 | ||
2391 | static void i915_write_fence_reg(struct drm_i915_fence_reg *reg) | |
2392 | { | |
2393 | struct drm_gem_object *obj = reg->obj; | |
2394 | struct drm_device *dev = obj->dev; | |
2395 | drm_i915_private_t *dev_priv = dev->dev_private; | |
23010e43 | 2396 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
de151cf6 | 2397 | int regnum = obj_priv->fence_reg; |
0f973f27 | 2398 | int tile_width; |
dc529a4f | 2399 | uint32_t fence_reg, val; |
de151cf6 JB |
2400 | uint32_t pitch_val; |
2401 | ||
2402 | if ((obj_priv->gtt_offset & ~I915_FENCE_START_MASK) || | |
2403 | (obj_priv->gtt_offset & (obj->size - 1))) { | |
f06da264 | 2404 | WARN(1, "%s: object 0x%08x not 1M or size (0x%zx) aligned\n", |
0f973f27 | 2405 | __func__, obj_priv->gtt_offset, obj->size); |
de151cf6 JB |
2406 | return; |
2407 | } | |
2408 | ||
0f973f27 JB |
2409 | if (obj_priv->tiling_mode == I915_TILING_Y && |
2410 | HAS_128_BYTE_Y_TILING(dev)) | |
2411 | tile_width = 128; | |
de151cf6 | 2412 | else |
0f973f27 JB |
2413 | tile_width = 512; |
2414 | ||
2415 | /* Note: pitch better be a power of two tile widths */ | |
2416 | pitch_val = obj_priv->stride / tile_width; | |
2417 | pitch_val = ffs(pitch_val) - 1; | |
de151cf6 | 2418 | |
c36a2a6d DV |
2419 | if (obj_priv->tiling_mode == I915_TILING_Y && |
2420 | HAS_128_BYTE_Y_TILING(dev)) | |
2421 | WARN_ON(pitch_val > I830_FENCE_MAX_PITCH_VAL); | |
2422 | else | |
2423 | WARN_ON(pitch_val > I915_FENCE_MAX_PITCH_VAL); | |
2424 | ||
de151cf6 JB |
2425 | val = obj_priv->gtt_offset; |
2426 | if (obj_priv->tiling_mode == I915_TILING_Y) | |
2427 | val |= 1 << I830_FENCE_TILING_Y_SHIFT; | |
2428 | val |= I915_FENCE_SIZE_BITS(obj->size); | |
2429 | val |= pitch_val << I830_FENCE_PITCH_SHIFT; | |
2430 | val |= I830_FENCE_REG_VALID; | |
2431 | ||
dc529a4f EA |
2432 | if (regnum < 8) |
2433 | fence_reg = FENCE_REG_830_0 + (regnum * 4); | |
2434 | else | |
2435 | fence_reg = FENCE_REG_945_8 + ((regnum - 8) * 4); | |
2436 | I915_WRITE(fence_reg, val); | |
de151cf6 JB |
2437 | } |
2438 | ||
2439 | static void i830_write_fence_reg(struct drm_i915_fence_reg *reg) | |
2440 | { | |
2441 | struct drm_gem_object *obj = reg->obj; | |
2442 | struct drm_device *dev = obj->dev; | |
2443 | drm_i915_private_t *dev_priv = dev->dev_private; | |
23010e43 | 2444 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
de151cf6 JB |
2445 | int regnum = obj_priv->fence_reg; |
2446 | uint32_t val; | |
2447 | uint32_t pitch_val; | |
8d7773a3 | 2448 | uint32_t fence_size_bits; |
de151cf6 | 2449 | |
8d7773a3 | 2450 | if ((obj_priv->gtt_offset & ~I830_FENCE_START_MASK) || |
de151cf6 | 2451 | (obj_priv->gtt_offset & (obj->size - 1))) { |
8d7773a3 | 2452 | WARN(1, "%s: object 0x%08x not 512K or size aligned\n", |
0f973f27 | 2453 | __func__, obj_priv->gtt_offset); |
de151cf6 JB |
2454 | return; |
2455 | } | |
2456 | ||
e76a16de EA |
2457 | pitch_val = obj_priv->stride / 128; |
2458 | pitch_val = ffs(pitch_val) - 1; | |
2459 | WARN_ON(pitch_val > I830_FENCE_MAX_PITCH_VAL); | |
2460 | ||
de151cf6 JB |
2461 | val = obj_priv->gtt_offset; |
2462 | if (obj_priv->tiling_mode == I915_TILING_Y) | |
2463 | val |= 1 << I830_FENCE_TILING_Y_SHIFT; | |
8d7773a3 DV |
2464 | fence_size_bits = I830_FENCE_SIZE_BITS(obj->size); |
2465 | WARN_ON(fence_size_bits & ~0x00000f00); | |
2466 | val |= fence_size_bits; | |
de151cf6 JB |
2467 | val |= pitch_val << I830_FENCE_PITCH_SHIFT; |
2468 | val |= I830_FENCE_REG_VALID; | |
2469 | ||
2470 | I915_WRITE(FENCE_REG_830_0 + (regnum * 4), val); | |
de151cf6 JB |
2471 | } |
2472 | ||
2cf34d7b CW |
2473 | static int i915_find_fence_reg(struct drm_device *dev, |
2474 | bool interruptible) | |
ae3db24a DV |
2475 | { |
2476 | struct drm_i915_fence_reg *reg = NULL; | |
2477 | struct drm_i915_gem_object *obj_priv = NULL; | |
2478 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2479 | struct drm_gem_object *obj = NULL; | |
2480 | int i, avail, ret; | |
2481 | ||
2482 | /* First try to find a free reg */ | |
2483 | avail = 0; | |
2484 | for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) { | |
2485 | reg = &dev_priv->fence_regs[i]; | |
2486 | if (!reg->obj) | |
2487 | return i; | |
2488 | ||
23010e43 | 2489 | obj_priv = to_intel_bo(reg->obj); |
ae3db24a DV |
2490 | if (!obj_priv->pin_count) |
2491 | avail++; | |
2492 | } | |
2493 | ||
2494 | if (avail == 0) | |
2495 | return -ENOSPC; | |
2496 | ||
2497 | /* None available, try to steal one or wait for a user to finish */ | |
2498 | i = I915_FENCE_REG_NONE; | |
007cc8ac DV |
2499 | list_for_each_entry(reg, &dev_priv->mm.fence_list, |
2500 | lru_list) { | |
2501 | obj = reg->obj; | |
2502 | obj_priv = to_intel_bo(obj); | |
ae3db24a DV |
2503 | |
2504 | if (obj_priv->pin_count) | |
2505 | continue; | |
2506 | ||
2507 | /* found one! */ | |
2508 | i = obj_priv->fence_reg; | |
2509 | break; | |
2510 | } | |
2511 | ||
2512 | BUG_ON(i == I915_FENCE_REG_NONE); | |
2513 | ||
2514 | /* We only have a reference on obj from the active list. put_fence_reg | |
2515 | * might drop that one, causing a use-after-free in it. So hold a | |
2516 | * private reference to obj like the other callers of put_fence_reg | |
2517 | * (set_tiling ioctl) do. */ | |
2518 | drm_gem_object_reference(obj); | |
2cf34d7b | 2519 | ret = i915_gem_object_put_fence_reg(obj, interruptible); |
ae3db24a DV |
2520 | drm_gem_object_unreference(obj); |
2521 | if (ret != 0) | |
2522 | return ret; | |
2523 | ||
2524 | return i; | |
2525 | } | |
2526 | ||
de151cf6 JB |
2527 | /** |
2528 | * i915_gem_object_get_fence_reg - set up a fence reg for an object | |
2529 | * @obj: object to map through a fence reg | |
2530 | * | |
2531 | * When mapping objects through the GTT, userspace wants to be able to write | |
2532 | * to them without having to worry about swizzling if the object is tiled. | |
2533 | * | |
2534 | * This function walks the fence regs looking for a free one for @obj, | |
2535 | * stealing one if it can't find any. | |
2536 | * | |
2537 | * It then sets up the reg based on the object's properties: address, pitch | |
2538 | * and tiling format. | |
2539 | */ | |
8c4b8c3f | 2540 | int |
2cf34d7b CW |
2541 | i915_gem_object_get_fence_reg(struct drm_gem_object *obj, |
2542 | bool interruptible) | |
de151cf6 JB |
2543 | { |
2544 | struct drm_device *dev = obj->dev; | |
79e53945 | 2545 | struct drm_i915_private *dev_priv = dev->dev_private; |
23010e43 | 2546 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
de151cf6 | 2547 | struct drm_i915_fence_reg *reg = NULL; |
ae3db24a | 2548 | int ret; |
de151cf6 | 2549 | |
a09ba7fa EA |
2550 | /* Just update our place in the LRU if our fence is getting used. */ |
2551 | if (obj_priv->fence_reg != I915_FENCE_REG_NONE) { | |
007cc8ac DV |
2552 | reg = &dev_priv->fence_regs[obj_priv->fence_reg]; |
2553 | list_move_tail(®->lru_list, &dev_priv->mm.fence_list); | |
a09ba7fa EA |
2554 | return 0; |
2555 | } | |
2556 | ||
de151cf6 JB |
2557 | switch (obj_priv->tiling_mode) { |
2558 | case I915_TILING_NONE: | |
2559 | WARN(1, "allocating a fence for non-tiled object?\n"); | |
2560 | break; | |
2561 | case I915_TILING_X: | |
0f973f27 JB |
2562 | if (!obj_priv->stride) |
2563 | return -EINVAL; | |
2564 | WARN((obj_priv->stride & (512 - 1)), | |
2565 | "object 0x%08x is X tiled but has non-512B pitch\n", | |
2566 | obj_priv->gtt_offset); | |
de151cf6 JB |
2567 | break; |
2568 | case I915_TILING_Y: | |
0f973f27 JB |
2569 | if (!obj_priv->stride) |
2570 | return -EINVAL; | |
2571 | WARN((obj_priv->stride & (128 - 1)), | |
2572 | "object 0x%08x is Y tiled but has non-128B pitch\n", | |
2573 | obj_priv->gtt_offset); | |
de151cf6 JB |
2574 | break; |
2575 | } | |
2576 | ||
2cf34d7b | 2577 | ret = i915_find_fence_reg(dev, interruptible); |
ae3db24a DV |
2578 | if (ret < 0) |
2579 | return ret; | |
de151cf6 | 2580 | |
ae3db24a DV |
2581 | obj_priv->fence_reg = ret; |
2582 | reg = &dev_priv->fence_regs[obj_priv->fence_reg]; | |
007cc8ac | 2583 | list_add_tail(®->lru_list, &dev_priv->mm.fence_list); |
a09ba7fa | 2584 | |
de151cf6 JB |
2585 | reg->obj = obj; |
2586 | ||
e259befd CW |
2587 | switch (INTEL_INFO(dev)->gen) { |
2588 | case 6: | |
4e901fdc | 2589 | sandybridge_write_fence_reg(reg); |
e259befd CW |
2590 | break; |
2591 | case 5: | |
2592 | case 4: | |
de151cf6 | 2593 | i965_write_fence_reg(reg); |
e259befd CW |
2594 | break; |
2595 | case 3: | |
de151cf6 | 2596 | i915_write_fence_reg(reg); |
e259befd CW |
2597 | break; |
2598 | case 2: | |
de151cf6 | 2599 | i830_write_fence_reg(reg); |
e259befd CW |
2600 | break; |
2601 | } | |
d9ddcb96 | 2602 | |
ae3db24a DV |
2603 | trace_i915_gem_object_get_fence(obj, obj_priv->fence_reg, |
2604 | obj_priv->tiling_mode); | |
1c5d22f7 | 2605 | |
d9ddcb96 | 2606 | return 0; |
de151cf6 JB |
2607 | } |
2608 | ||
2609 | /** | |
2610 | * i915_gem_clear_fence_reg - clear out fence register info | |
2611 | * @obj: object to clear | |
2612 | * | |
2613 | * Zeroes out the fence register itself and clears out the associated | |
2614 | * data structures in dev_priv and obj_priv. | |
2615 | */ | |
2616 | static void | |
2617 | i915_gem_clear_fence_reg(struct drm_gem_object *obj) | |
2618 | { | |
2619 | struct drm_device *dev = obj->dev; | |
79e53945 | 2620 | drm_i915_private_t *dev_priv = dev->dev_private; |
23010e43 | 2621 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
007cc8ac DV |
2622 | struct drm_i915_fence_reg *reg = |
2623 | &dev_priv->fence_regs[obj_priv->fence_reg]; | |
e259befd | 2624 | uint32_t fence_reg; |
de151cf6 | 2625 | |
e259befd CW |
2626 | switch (INTEL_INFO(dev)->gen) { |
2627 | case 6: | |
4e901fdc EA |
2628 | I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + |
2629 | (obj_priv->fence_reg * 8), 0); | |
e259befd CW |
2630 | break; |
2631 | case 5: | |
2632 | case 4: | |
de151cf6 | 2633 | I915_WRITE64(FENCE_REG_965_0 + (obj_priv->fence_reg * 8), 0); |
e259befd CW |
2634 | break; |
2635 | case 3: | |
9b74f734 | 2636 | if (obj_priv->fence_reg >= 8) |
e259befd | 2637 | fence_reg = FENCE_REG_945_8 + (obj_priv->fence_reg - 8) * 4; |
dc529a4f | 2638 | else |
e259befd CW |
2639 | case 2: |
2640 | fence_reg = FENCE_REG_830_0 + obj_priv->fence_reg * 4; | |
dc529a4f EA |
2641 | |
2642 | I915_WRITE(fence_reg, 0); | |
e259befd | 2643 | break; |
dc529a4f | 2644 | } |
de151cf6 | 2645 | |
007cc8ac | 2646 | reg->obj = NULL; |
de151cf6 | 2647 | obj_priv->fence_reg = I915_FENCE_REG_NONE; |
007cc8ac | 2648 | list_del_init(®->lru_list); |
de151cf6 JB |
2649 | } |
2650 | ||
52dc7d32 CW |
2651 | /** |
2652 | * i915_gem_object_put_fence_reg - waits on outstanding fenced access | |
2653 | * to the buffer to finish, and then resets the fence register. | |
2654 | * @obj: tiled object holding a fence register. | |
2cf34d7b | 2655 | * @bool: whether the wait upon the fence is interruptible |
52dc7d32 CW |
2656 | * |
2657 | * Zeroes out the fence register itself and clears out the associated | |
2658 | * data structures in dev_priv and obj_priv. | |
2659 | */ | |
2660 | int | |
2cf34d7b CW |
2661 | i915_gem_object_put_fence_reg(struct drm_gem_object *obj, |
2662 | bool interruptible) | |
52dc7d32 CW |
2663 | { |
2664 | struct drm_device *dev = obj->dev; | |
53640e1d | 2665 | struct drm_i915_private *dev_priv = dev->dev_private; |
23010e43 | 2666 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
53640e1d | 2667 | struct drm_i915_fence_reg *reg; |
52dc7d32 CW |
2668 | |
2669 | if (obj_priv->fence_reg == I915_FENCE_REG_NONE) | |
2670 | return 0; | |
2671 | ||
10ae9bd2 DV |
2672 | /* If we've changed tiling, GTT-mappings of the object |
2673 | * need to re-fault to ensure that the correct fence register | |
2674 | * setup is in place. | |
2675 | */ | |
2676 | i915_gem_release_mmap(obj); | |
2677 | ||
52dc7d32 CW |
2678 | /* On the i915, GPU access to tiled buffers is via a fence, |
2679 | * therefore we must wait for any outstanding access to complete | |
2680 | * before clearing the fence. | |
2681 | */ | |
53640e1d CW |
2682 | reg = &dev_priv->fence_regs[obj_priv->fence_reg]; |
2683 | if (reg->gpu) { | |
52dc7d32 CW |
2684 | int ret; |
2685 | ||
2cf34d7b | 2686 | ret = i915_gem_object_flush_gpu_write_domain(obj, true); |
0bc23aad | 2687 | if (ret) |
2dafb1e0 CW |
2688 | return ret; |
2689 | ||
2cf34d7b | 2690 | ret = i915_gem_object_wait_rendering(obj, interruptible); |
0bc23aad | 2691 | if (ret) |
52dc7d32 | 2692 | return ret; |
53640e1d CW |
2693 | |
2694 | reg->gpu = false; | |
52dc7d32 CW |
2695 | } |
2696 | ||
4a726612 | 2697 | i915_gem_object_flush_gtt_write_domain(obj); |
0bc23aad | 2698 | i915_gem_clear_fence_reg(obj); |
52dc7d32 CW |
2699 | |
2700 | return 0; | |
2701 | } | |
2702 | ||
673a394b EA |
2703 | /** |
2704 | * Finds free space in the GTT aperture and binds the object there. | |
2705 | */ | |
2706 | static int | |
920afa77 DV |
2707 | i915_gem_object_bind_to_gtt(struct drm_gem_object *obj, |
2708 | unsigned alignment, | |
2709 | bool mappable) | |
673a394b EA |
2710 | { |
2711 | struct drm_device *dev = obj->dev; | |
2712 | drm_i915_private_t *dev_priv = dev->dev_private; | |
23010e43 | 2713 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
673a394b | 2714 | struct drm_mm_node *free_space; |
4bdadb97 | 2715 | gfp_t gfpmask = __GFP_NORETRY | __GFP_NOWARN; |
07f73f69 | 2716 | int ret; |
673a394b | 2717 | |
bb6baf76 | 2718 | if (obj_priv->madv != I915_MADV_WILLNEED) { |
3ef94daa CW |
2719 | DRM_ERROR("Attempting to bind a purgeable object\n"); |
2720 | return -EINVAL; | |
2721 | } | |
2722 | ||
673a394b | 2723 | if (alignment == 0) |
0f973f27 | 2724 | alignment = i915_gem_get_gtt_alignment(obj); |
8d7773a3 | 2725 | if (alignment & (i915_gem_get_gtt_alignment(obj) - 1)) { |
673a394b EA |
2726 | DRM_ERROR("Invalid object alignment requested %u\n", alignment); |
2727 | return -EINVAL; | |
2728 | } | |
2729 | ||
654fc607 CW |
2730 | /* If the object is bigger than the entire aperture, reject it early |
2731 | * before evicting everything in a vain attempt to find space. | |
2732 | */ | |
920afa77 DV |
2733 | if (obj->size > |
2734 | (mappable ? dev_priv->mm.gtt_mappable_end : dev_priv->mm.gtt_total)) { | |
654fc607 CW |
2735 | DRM_ERROR("Attempting to bind an object larger than the aperture\n"); |
2736 | return -E2BIG; | |
2737 | } | |
2738 | ||
673a394b | 2739 | search_free: |
920afa77 DV |
2740 | if (mappable) |
2741 | free_space = | |
2742 | drm_mm_search_free_in_range(&dev_priv->mm.gtt_space, | |
2743 | obj->size, alignment, 0, | |
2744 | dev_priv->mm.gtt_mappable_end, | |
2745 | 0); | |
2746 | else | |
2747 | free_space = drm_mm_search_free(&dev_priv->mm.gtt_space, | |
2748 | obj->size, alignment, 0); | |
2749 | ||
2750 | if (free_space != NULL) { | |
2751 | if (mappable) | |
2752 | obj_priv->gtt_space = | |
2753 | drm_mm_get_block_range_generic(free_space, | |
2754 | obj->size, | |
2755 | alignment, 0, | |
2756 | dev_priv->mm.gtt_mappable_end, | |
2757 | 0); | |
2758 | else | |
2759 | obj_priv->gtt_space = | |
2760 | drm_mm_get_block(free_space, obj->size, | |
2761 | alignment); | |
2762 | } | |
673a394b EA |
2763 | if (obj_priv->gtt_space == NULL) { |
2764 | /* If the gtt is empty and we're still having trouble | |
2765 | * fitting our object in, we're out of memory. | |
2766 | */ | |
920afa77 DV |
2767 | ret = i915_gem_evict_something(dev, obj->size, alignment, |
2768 | mappable); | |
9731129c | 2769 | if (ret) |
673a394b | 2770 | return ret; |
9731129c | 2771 | |
673a394b EA |
2772 | goto search_free; |
2773 | } | |
2774 | ||
4bdadb97 | 2775 | ret = i915_gem_object_get_pages(obj, gfpmask); |
673a394b EA |
2776 | if (ret) { |
2777 | drm_mm_put_block(obj_priv->gtt_space); | |
2778 | obj_priv->gtt_space = NULL; | |
07f73f69 CW |
2779 | |
2780 | if (ret == -ENOMEM) { | |
2781 | /* first try to clear up some space from the GTT */ | |
0108a3ed | 2782 | ret = i915_gem_evict_something(dev, obj->size, |
920afa77 | 2783 | alignment, mappable); |
07f73f69 | 2784 | if (ret) { |
07f73f69 | 2785 | /* now try to shrink everyone else */ |
4bdadb97 CW |
2786 | if (gfpmask) { |
2787 | gfpmask = 0; | |
2788 | goto search_free; | |
07f73f69 CW |
2789 | } |
2790 | ||
2791 | return ret; | |
2792 | } | |
2793 | ||
2794 | goto search_free; | |
2795 | } | |
2796 | ||
673a394b EA |
2797 | return ret; |
2798 | } | |
2799 | ||
673a394b EA |
2800 | /* Create an AGP memory structure pointing at our pages, and bind it |
2801 | * into the GTT. | |
2802 | */ | |
2803 | obj_priv->agp_mem = drm_agp_bind_pages(dev, | |
856fa198 | 2804 | obj_priv->pages, |
07f73f69 | 2805 | obj->size >> PAGE_SHIFT, |
9af90d19 | 2806 | obj_priv->gtt_space->start, |
ba1eb1d8 | 2807 | obj_priv->agp_type); |
673a394b | 2808 | if (obj_priv->agp_mem == NULL) { |
856fa198 | 2809 | i915_gem_object_put_pages(obj); |
673a394b EA |
2810 | drm_mm_put_block(obj_priv->gtt_space); |
2811 | obj_priv->gtt_space = NULL; | |
07f73f69 | 2812 | |
920afa77 DV |
2813 | ret = i915_gem_evict_something(dev, obj->size, alignment, |
2814 | mappable); | |
9731129c | 2815 | if (ret) |
07f73f69 | 2816 | return ret; |
07f73f69 CW |
2817 | |
2818 | goto search_free; | |
673a394b | 2819 | } |
673a394b | 2820 | |
fb7d516a DV |
2821 | obj_priv->gtt_offset = obj_priv->gtt_space->start; |
2822 | ||
bf1a1092 | 2823 | /* keep track of bounds object by adding it to the inactive list */ |
69dc4987 | 2824 | list_add_tail(&obj_priv->mm_list, &dev_priv->mm.inactive_list); |
fb7d516a | 2825 | i915_gem_info_add_gtt(dev_priv, obj); |
bf1a1092 | 2826 | |
673a394b EA |
2827 | /* Assert that the object is not currently in any GPU domain. As it |
2828 | * wasn't in the GTT, there shouldn't be any way it could have been in | |
2829 | * a GPU cache | |
2830 | */ | |
21d509e3 CW |
2831 | BUG_ON(obj->read_domains & I915_GEM_GPU_DOMAINS); |
2832 | BUG_ON(obj->write_domain & I915_GEM_GPU_DOMAINS); | |
673a394b | 2833 | |
ec57d260 | 2834 | trace_i915_gem_object_bind(obj, obj_priv->gtt_offset, mappable); |
1c5d22f7 | 2835 | |
673a394b EA |
2836 | return 0; |
2837 | } | |
2838 | ||
2839 | void | |
2840 | i915_gem_clflush_object(struct drm_gem_object *obj) | |
2841 | { | |
23010e43 | 2842 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
673a394b EA |
2843 | |
2844 | /* If we don't have a page list set up, then we're not pinned | |
2845 | * to GPU, and we can ignore the cache flush because it'll happen | |
2846 | * again at bind time. | |
2847 | */ | |
856fa198 | 2848 | if (obj_priv->pages == NULL) |
673a394b EA |
2849 | return; |
2850 | ||
1c5d22f7 | 2851 | trace_i915_gem_object_clflush(obj); |
cfa16a0d | 2852 | |
856fa198 | 2853 | drm_clflush_pages(obj_priv->pages, obj->size / PAGE_SIZE); |
673a394b EA |
2854 | } |
2855 | ||
e47c68e9 | 2856 | /** Flushes any GPU write domain for the object if it's dirty. */ |
2dafb1e0 | 2857 | static int |
ba3d8d74 DV |
2858 | i915_gem_object_flush_gpu_write_domain(struct drm_gem_object *obj, |
2859 | bool pipelined) | |
e47c68e9 EA |
2860 | { |
2861 | struct drm_device *dev = obj->dev; | |
1c5d22f7 | 2862 | uint32_t old_write_domain; |
e47c68e9 EA |
2863 | |
2864 | if ((obj->write_domain & I915_GEM_GPU_DOMAINS) == 0) | |
2dafb1e0 | 2865 | return 0; |
e47c68e9 EA |
2866 | |
2867 | /* Queue the GPU write cache flushing we need. */ | |
1c5d22f7 | 2868 | old_write_domain = obj->write_domain; |
c78ec30b | 2869 | i915_gem_flush_ring(dev, NULL, |
9220434a CW |
2870 | to_intel_bo(obj)->ring, |
2871 | 0, obj->write_domain); | |
48b956c5 | 2872 | BUG_ON(obj->write_domain); |
1c5d22f7 CW |
2873 | |
2874 | trace_i915_gem_object_change_domain(obj, | |
2875 | obj->read_domains, | |
2876 | old_write_domain); | |
ba3d8d74 DV |
2877 | |
2878 | if (pipelined) | |
2879 | return 0; | |
2880 | ||
2cf34d7b | 2881 | return i915_gem_object_wait_rendering(obj, true); |
e47c68e9 EA |
2882 | } |
2883 | ||
2884 | /** Flushes the GTT write domain for the object if it's dirty. */ | |
2885 | static void | |
2886 | i915_gem_object_flush_gtt_write_domain(struct drm_gem_object *obj) | |
2887 | { | |
1c5d22f7 CW |
2888 | uint32_t old_write_domain; |
2889 | ||
e47c68e9 EA |
2890 | if (obj->write_domain != I915_GEM_DOMAIN_GTT) |
2891 | return; | |
2892 | ||
2893 | /* No actual flushing is required for the GTT write domain. Writes | |
2894 | * to it immediately go to main memory as far as we know, so there's | |
2895 | * no chipset flush. It also doesn't land in render cache. | |
2896 | */ | |
1c5d22f7 | 2897 | old_write_domain = obj->write_domain; |
e47c68e9 | 2898 | obj->write_domain = 0; |
1c5d22f7 CW |
2899 | |
2900 | trace_i915_gem_object_change_domain(obj, | |
2901 | obj->read_domains, | |
2902 | old_write_domain); | |
e47c68e9 EA |
2903 | } |
2904 | ||
2905 | /** Flushes the CPU write domain for the object if it's dirty. */ | |
2906 | static void | |
2907 | i915_gem_object_flush_cpu_write_domain(struct drm_gem_object *obj) | |
2908 | { | |
2909 | struct drm_device *dev = obj->dev; | |
1c5d22f7 | 2910 | uint32_t old_write_domain; |
e47c68e9 EA |
2911 | |
2912 | if (obj->write_domain != I915_GEM_DOMAIN_CPU) | |
2913 | return; | |
2914 | ||
2915 | i915_gem_clflush_object(obj); | |
2916 | drm_agp_chipset_flush(dev); | |
1c5d22f7 | 2917 | old_write_domain = obj->write_domain; |
e47c68e9 | 2918 | obj->write_domain = 0; |
1c5d22f7 CW |
2919 | |
2920 | trace_i915_gem_object_change_domain(obj, | |
2921 | obj->read_domains, | |
2922 | old_write_domain); | |
e47c68e9 EA |
2923 | } |
2924 | ||
2ef7eeaa EA |
2925 | /** |
2926 | * Moves a single object to the GTT read, and possibly write domain. | |
2927 | * | |
2928 | * This function returns when the move is complete, including waiting on | |
2929 | * flushes to occur. | |
2930 | */ | |
79e53945 | 2931 | int |
2ef7eeaa EA |
2932 | i915_gem_object_set_to_gtt_domain(struct drm_gem_object *obj, int write) |
2933 | { | |
23010e43 | 2934 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
1c5d22f7 | 2935 | uint32_t old_write_domain, old_read_domains; |
e47c68e9 | 2936 | int ret; |
2ef7eeaa | 2937 | |
02354392 EA |
2938 | /* Not valid to be called on unbound objects. */ |
2939 | if (obj_priv->gtt_space == NULL) | |
2940 | return -EINVAL; | |
2941 | ||
ba3d8d74 | 2942 | ret = i915_gem_object_flush_gpu_write_domain(obj, false); |
2dafb1e0 CW |
2943 | if (ret != 0) |
2944 | return ret; | |
2945 | ||
7213342d | 2946 | i915_gem_object_flush_cpu_write_domain(obj); |
1c5d22f7 | 2947 | |
ba3d8d74 | 2948 | if (write) { |
2cf34d7b | 2949 | ret = i915_gem_object_wait_rendering(obj, true); |
ba3d8d74 DV |
2950 | if (ret) |
2951 | return ret; | |
ba3d8d74 | 2952 | } |
e47c68e9 | 2953 | |
1c5d22f7 CW |
2954 | old_write_domain = obj->write_domain; |
2955 | old_read_domains = obj->read_domains; | |
2956 | ||
e47c68e9 EA |
2957 | /* It should now be out of any other write domains, and we can update |
2958 | * the domain values for our changes. | |
2959 | */ | |
2960 | BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_GTT) != 0); | |
2961 | obj->read_domains |= I915_GEM_DOMAIN_GTT; | |
2962 | if (write) { | |
7213342d | 2963 | obj->read_domains = I915_GEM_DOMAIN_GTT; |
e47c68e9 EA |
2964 | obj->write_domain = I915_GEM_DOMAIN_GTT; |
2965 | obj_priv->dirty = 1; | |
2ef7eeaa EA |
2966 | } |
2967 | ||
1c5d22f7 CW |
2968 | trace_i915_gem_object_change_domain(obj, |
2969 | old_read_domains, | |
2970 | old_write_domain); | |
2971 | ||
e47c68e9 EA |
2972 | return 0; |
2973 | } | |
2974 | ||
b9241ea3 ZW |
2975 | /* |
2976 | * Prepare buffer for display plane. Use uninterruptible for possible flush | |
2977 | * wait, as in modesetting process we're not supposed to be interrupted. | |
2978 | */ | |
2979 | int | |
48b956c5 CW |
2980 | i915_gem_object_set_to_display_plane(struct drm_gem_object *obj, |
2981 | bool pipelined) | |
b9241ea3 | 2982 | { |
23010e43 | 2983 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
ba3d8d74 | 2984 | uint32_t old_read_domains; |
b9241ea3 ZW |
2985 | int ret; |
2986 | ||
2987 | /* Not valid to be called on unbound objects. */ | |
2988 | if (obj_priv->gtt_space == NULL) | |
2989 | return -EINVAL; | |
2990 | ||
ced270fa | 2991 | ret = i915_gem_object_flush_gpu_write_domain(obj, true); |
2dafb1e0 CW |
2992 | if (ret) |
2993 | return ret; | |
b9241ea3 | 2994 | |
ced270fa CW |
2995 | /* Currently, we are always called from an non-interruptible context. */ |
2996 | if (!pipelined) { | |
2997 | ret = i915_gem_object_wait_rendering(obj, false); | |
2998 | if (ret) | |
b9241ea3 ZW |
2999 | return ret; |
3000 | } | |
3001 | ||
b118c1e3 CW |
3002 | i915_gem_object_flush_cpu_write_domain(obj); |
3003 | ||
b9241ea3 | 3004 | old_read_domains = obj->read_domains; |
c78ec30b | 3005 | obj->read_domains |= I915_GEM_DOMAIN_GTT; |
b9241ea3 ZW |
3006 | |
3007 | trace_i915_gem_object_change_domain(obj, | |
3008 | old_read_domains, | |
ba3d8d74 | 3009 | obj->write_domain); |
b9241ea3 ZW |
3010 | |
3011 | return 0; | |
3012 | } | |
3013 | ||
e47c68e9 EA |
3014 | /** |
3015 | * Moves a single object to the CPU read, and possibly write domain. | |
3016 | * | |
3017 | * This function returns when the move is complete, including waiting on | |
3018 | * flushes to occur. | |
3019 | */ | |
3020 | static int | |
3021 | i915_gem_object_set_to_cpu_domain(struct drm_gem_object *obj, int write) | |
3022 | { | |
1c5d22f7 | 3023 | uint32_t old_write_domain, old_read_domains; |
e47c68e9 EA |
3024 | int ret; |
3025 | ||
ba3d8d74 | 3026 | ret = i915_gem_object_flush_gpu_write_domain(obj, false); |
e47c68e9 EA |
3027 | if (ret != 0) |
3028 | return ret; | |
2ef7eeaa | 3029 | |
e47c68e9 | 3030 | i915_gem_object_flush_gtt_write_domain(obj); |
2ef7eeaa | 3031 | |
e47c68e9 EA |
3032 | /* If we have a partially-valid cache of the object in the CPU, |
3033 | * finish invalidating it and free the per-page flags. | |
2ef7eeaa | 3034 | */ |
e47c68e9 | 3035 | i915_gem_object_set_to_full_cpu_read_domain(obj); |
2ef7eeaa | 3036 | |
7213342d | 3037 | if (write) { |
2cf34d7b | 3038 | ret = i915_gem_object_wait_rendering(obj, true); |
7213342d CW |
3039 | if (ret) |
3040 | return ret; | |
3041 | } | |
3042 | ||
1c5d22f7 CW |
3043 | old_write_domain = obj->write_domain; |
3044 | old_read_domains = obj->read_domains; | |
3045 | ||
e47c68e9 EA |
3046 | /* Flush the CPU cache if it's still invalid. */ |
3047 | if ((obj->read_domains & I915_GEM_DOMAIN_CPU) == 0) { | |
2ef7eeaa | 3048 | i915_gem_clflush_object(obj); |
2ef7eeaa | 3049 | |
e47c68e9 | 3050 | obj->read_domains |= I915_GEM_DOMAIN_CPU; |
2ef7eeaa EA |
3051 | } |
3052 | ||
3053 | /* It should now be out of any other write domains, and we can update | |
3054 | * the domain values for our changes. | |
3055 | */ | |
e47c68e9 EA |
3056 | BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_CPU) != 0); |
3057 | ||
3058 | /* If we're writing through the CPU, then the GPU read domains will | |
3059 | * need to be invalidated at next use. | |
3060 | */ | |
3061 | if (write) { | |
c78ec30b | 3062 | obj->read_domains = I915_GEM_DOMAIN_CPU; |
e47c68e9 EA |
3063 | obj->write_domain = I915_GEM_DOMAIN_CPU; |
3064 | } | |
2ef7eeaa | 3065 | |
1c5d22f7 CW |
3066 | trace_i915_gem_object_change_domain(obj, |
3067 | old_read_domains, | |
3068 | old_write_domain); | |
3069 | ||
2ef7eeaa EA |
3070 | return 0; |
3071 | } | |
3072 | ||
673a394b EA |
3073 | /* |
3074 | * Set the next domain for the specified object. This | |
3075 | * may not actually perform the necessary flushing/invaliding though, | |
3076 | * as that may want to be batched with other set_domain operations | |
3077 | * | |
3078 | * This is (we hope) the only really tricky part of gem. The goal | |
3079 | * is fairly simple -- track which caches hold bits of the object | |
3080 | * and make sure they remain coherent. A few concrete examples may | |
3081 | * help to explain how it works. For shorthand, we use the notation | |
3082 | * (read_domains, write_domain), e.g. (CPU, CPU) to indicate the | |
3083 | * a pair of read and write domain masks. | |
3084 | * | |
3085 | * Case 1: the batch buffer | |
3086 | * | |
3087 | * 1. Allocated | |
3088 | * 2. Written by CPU | |
3089 | * 3. Mapped to GTT | |
3090 | * 4. Read by GPU | |
3091 | * 5. Unmapped from GTT | |
3092 | * 6. Freed | |
3093 | * | |
3094 | * Let's take these a step at a time | |
3095 | * | |
3096 | * 1. Allocated | |
3097 | * Pages allocated from the kernel may still have | |
3098 | * cache contents, so we set them to (CPU, CPU) always. | |
3099 | * 2. Written by CPU (using pwrite) | |
3100 | * The pwrite function calls set_domain (CPU, CPU) and | |
3101 | * this function does nothing (as nothing changes) | |
3102 | * 3. Mapped by GTT | |
3103 | * This function asserts that the object is not | |
3104 | * currently in any GPU-based read or write domains | |
3105 | * 4. Read by GPU | |
3106 | * i915_gem_execbuffer calls set_domain (COMMAND, 0). | |
3107 | * As write_domain is zero, this function adds in the | |
3108 | * current read domains (CPU+COMMAND, 0). | |
3109 | * flush_domains is set to CPU. | |
3110 | * invalidate_domains is set to COMMAND | |
3111 | * clflush is run to get data out of the CPU caches | |
3112 | * then i915_dev_set_domain calls i915_gem_flush to | |
3113 | * emit an MI_FLUSH and drm_agp_chipset_flush | |
3114 | * 5. Unmapped from GTT | |
3115 | * i915_gem_object_unbind calls set_domain (CPU, CPU) | |
3116 | * flush_domains and invalidate_domains end up both zero | |
3117 | * so no flushing/invalidating happens | |
3118 | * 6. Freed | |
3119 | * yay, done | |
3120 | * | |
3121 | * Case 2: The shared render buffer | |
3122 | * | |
3123 | * 1. Allocated | |
3124 | * 2. Mapped to GTT | |
3125 | * 3. Read/written by GPU | |
3126 | * 4. set_domain to (CPU,CPU) | |
3127 | * 5. Read/written by CPU | |
3128 | * 6. Read/written by GPU | |
3129 | * | |
3130 | * 1. Allocated | |
3131 | * Same as last example, (CPU, CPU) | |
3132 | * 2. Mapped to GTT | |
3133 | * Nothing changes (assertions find that it is not in the GPU) | |
3134 | * 3. Read/written by GPU | |
3135 | * execbuffer calls set_domain (RENDER, RENDER) | |
3136 | * flush_domains gets CPU | |
3137 | * invalidate_domains gets GPU | |
3138 | * clflush (obj) | |
3139 | * MI_FLUSH and drm_agp_chipset_flush | |
3140 | * 4. set_domain (CPU, CPU) | |
3141 | * flush_domains gets GPU | |
3142 | * invalidate_domains gets CPU | |
3143 | * wait_rendering (obj) to make sure all drawing is complete. | |
3144 | * This will include an MI_FLUSH to get the data from GPU | |
3145 | * to memory | |
3146 | * clflush (obj) to invalidate the CPU cache | |
3147 | * Another MI_FLUSH in i915_gem_flush (eliminate this somehow?) | |
3148 | * 5. Read/written by CPU | |
3149 | * cache lines are loaded and dirtied | |
3150 | * 6. Read written by GPU | |
3151 | * Same as last GPU access | |
3152 | * | |
3153 | * Case 3: The constant buffer | |
3154 | * | |
3155 | * 1. Allocated | |
3156 | * 2. Written by CPU | |
3157 | * 3. Read by GPU | |
3158 | * 4. Updated (written) by CPU again | |
3159 | * 5. Read by GPU | |
3160 | * | |
3161 | * 1. Allocated | |
3162 | * (CPU, CPU) | |
3163 | * 2. Written by CPU | |
3164 | * (CPU, CPU) | |
3165 | * 3. Read by GPU | |
3166 | * (CPU+RENDER, 0) | |
3167 | * flush_domains = CPU | |
3168 | * invalidate_domains = RENDER | |
3169 | * clflush (obj) | |
3170 | * MI_FLUSH | |
3171 | * drm_agp_chipset_flush | |
3172 | * 4. Updated (written) by CPU again | |
3173 | * (CPU, CPU) | |
3174 | * flush_domains = 0 (no previous write domain) | |
3175 | * invalidate_domains = 0 (no new read domains) | |
3176 | * 5. Read by GPU | |
3177 | * (CPU+RENDER, 0) | |
3178 | * flush_domains = CPU | |
3179 | * invalidate_domains = RENDER | |
3180 | * clflush (obj) | |
3181 | * MI_FLUSH | |
3182 | * drm_agp_chipset_flush | |
3183 | */ | |
c0d90829 | 3184 | static void |
b6651458 CW |
3185 | i915_gem_object_set_to_gpu_domain(struct drm_gem_object *obj, |
3186 | struct intel_ring_buffer *ring) | |
673a394b EA |
3187 | { |
3188 | struct drm_device *dev = obj->dev; | |
9220434a | 3189 | struct drm_i915_private *dev_priv = dev->dev_private; |
23010e43 | 3190 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
673a394b EA |
3191 | uint32_t invalidate_domains = 0; |
3192 | uint32_t flush_domains = 0; | |
652c393a | 3193 | |
673a394b EA |
3194 | /* |
3195 | * If the object isn't moving to a new write domain, | |
3196 | * let the object stay in multiple read domains | |
3197 | */ | |
8b0e378a EA |
3198 | if (obj->pending_write_domain == 0) |
3199 | obj->pending_read_domains |= obj->read_domains; | |
673a394b EA |
3200 | |
3201 | /* | |
3202 | * Flush the current write domain if | |
3203 | * the new read domains don't match. Invalidate | |
3204 | * any read domains which differ from the old | |
3205 | * write domain | |
3206 | */ | |
8b0e378a EA |
3207 | if (obj->write_domain && |
3208 | obj->write_domain != obj->pending_read_domains) { | |
673a394b | 3209 | flush_domains |= obj->write_domain; |
8b0e378a EA |
3210 | invalidate_domains |= |
3211 | obj->pending_read_domains & ~obj->write_domain; | |
673a394b EA |
3212 | } |
3213 | /* | |
3214 | * Invalidate any read caches which may have | |
3215 | * stale data. That is, any new read domains. | |
3216 | */ | |
8b0e378a | 3217 | invalidate_domains |= obj->pending_read_domains & ~obj->read_domains; |
3d2a812a | 3218 | if ((flush_domains | invalidate_domains) & I915_GEM_DOMAIN_CPU) |
673a394b | 3219 | i915_gem_clflush_object(obj); |
673a394b | 3220 | |
efbeed96 EA |
3221 | /* The actual obj->write_domain will be updated with |
3222 | * pending_write_domain after we emit the accumulated flush for all | |
3223 | * of our domain changes in execbuffers (which clears objects' | |
3224 | * write_domains). So if we have a current write domain that we | |
3225 | * aren't changing, set pending_write_domain to that. | |
3226 | */ | |
3227 | if (flush_domains == 0 && obj->pending_write_domain == 0) | |
3228 | obj->pending_write_domain = obj->write_domain; | |
673a394b EA |
3229 | |
3230 | dev->invalidate_domains |= invalidate_domains; | |
3231 | dev->flush_domains |= flush_domains; | |
b6651458 | 3232 | if (flush_domains & I915_GEM_GPU_DOMAINS) |
9220434a | 3233 | dev_priv->mm.flush_rings |= obj_priv->ring->id; |
b6651458 CW |
3234 | if (invalidate_domains & I915_GEM_GPU_DOMAINS) |
3235 | dev_priv->mm.flush_rings |= ring->id; | |
673a394b EA |
3236 | } |
3237 | ||
3238 | /** | |
e47c68e9 | 3239 | * Moves the object from a partially CPU read to a full one. |
673a394b | 3240 | * |
e47c68e9 EA |
3241 | * Note that this only resolves i915_gem_object_set_cpu_read_domain_range(), |
3242 | * and doesn't handle transitioning from !(read_domains & I915_GEM_DOMAIN_CPU). | |
673a394b | 3243 | */ |
e47c68e9 EA |
3244 | static void |
3245 | i915_gem_object_set_to_full_cpu_read_domain(struct drm_gem_object *obj) | |
673a394b | 3246 | { |
23010e43 | 3247 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
673a394b | 3248 | |
e47c68e9 EA |
3249 | if (!obj_priv->page_cpu_valid) |
3250 | return; | |
3251 | ||
3252 | /* If we're partially in the CPU read domain, finish moving it in. | |
3253 | */ | |
3254 | if (obj->read_domains & I915_GEM_DOMAIN_CPU) { | |
3255 | int i; | |
3256 | ||
3257 | for (i = 0; i <= (obj->size - 1) / PAGE_SIZE; i++) { | |
3258 | if (obj_priv->page_cpu_valid[i]) | |
3259 | continue; | |
856fa198 | 3260 | drm_clflush_pages(obj_priv->pages + i, 1); |
e47c68e9 | 3261 | } |
e47c68e9 EA |
3262 | } |
3263 | ||
3264 | /* Free the page_cpu_valid mappings which are now stale, whether | |
3265 | * or not we've got I915_GEM_DOMAIN_CPU. | |
3266 | */ | |
9a298b2a | 3267 | kfree(obj_priv->page_cpu_valid); |
e47c68e9 EA |
3268 | obj_priv->page_cpu_valid = NULL; |
3269 | } | |
3270 | ||
3271 | /** | |
3272 | * Set the CPU read domain on a range of the object. | |
3273 | * | |
3274 | * The object ends up with I915_GEM_DOMAIN_CPU in its read flags although it's | |
3275 | * not entirely valid. The page_cpu_valid member of the object flags which | |
3276 | * pages have been flushed, and will be respected by | |
3277 | * i915_gem_object_set_to_cpu_domain() if it's called on to get a valid mapping | |
3278 | * of the whole object. | |
3279 | * | |
3280 | * This function returns when the move is complete, including waiting on | |
3281 | * flushes to occur. | |
3282 | */ | |
3283 | static int | |
3284 | i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object *obj, | |
3285 | uint64_t offset, uint64_t size) | |
3286 | { | |
23010e43 | 3287 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
1c5d22f7 | 3288 | uint32_t old_read_domains; |
e47c68e9 | 3289 | int i, ret; |
673a394b | 3290 | |
e47c68e9 EA |
3291 | if (offset == 0 && size == obj->size) |
3292 | return i915_gem_object_set_to_cpu_domain(obj, 0); | |
673a394b | 3293 | |
ba3d8d74 | 3294 | ret = i915_gem_object_flush_gpu_write_domain(obj, false); |
e47c68e9 | 3295 | if (ret != 0) |
6a47baa6 | 3296 | return ret; |
e47c68e9 EA |
3297 | i915_gem_object_flush_gtt_write_domain(obj); |
3298 | ||
3299 | /* If we're already fully in the CPU read domain, we're done. */ | |
3300 | if (obj_priv->page_cpu_valid == NULL && | |
3301 | (obj->read_domains & I915_GEM_DOMAIN_CPU) != 0) | |
3302 | return 0; | |
673a394b | 3303 | |
e47c68e9 EA |
3304 | /* Otherwise, create/clear the per-page CPU read domain flag if we're |
3305 | * newly adding I915_GEM_DOMAIN_CPU | |
3306 | */ | |
673a394b | 3307 | if (obj_priv->page_cpu_valid == NULL) { |
9a298b2a EA |
3308 | obj_priv->page_cpu_valid = kzalloc(obj->size / PAGE_SIZE, |
3309 | GFP_KERNEL); | |
e47c68e9 EA |
3310 | if (obj_priv->page_cpu_valid == NULL) |
3311 | return -ENOMEM; | |
3312 | } else if ((obj->read_domains & I915_GEM_DOMAIN_CPU) == 0) | |
3313 | memset(obj_priv->page_cpu_valid, 0, obj->size / PAGE_SIZE); | |
673a394b EA |
3314 | |
3315 | /* Flush the cache on any pages that are still invalid from the CPU's | |
3316 | * perspective. | |
3317 | */ | |
e47c68e9 EA |
3318 | for (i = offset / PAGE_SIZE; i <= (offset + size - 1) / PAGE_SIZE; |
3319 | i++) { | |
673a394b EA |
3320 | if (obj_priv->page_cpu_valid[i]) |
3321 | continue; | |
3322 | ||
856fa198 | 3323 | drm_clflush_pages(obj_priv->pages + i, 1); |
673a394b EA |
3324 | |
3325 | obj_priv->page_cpu_valid[i] = 1; | |
3326 | } | |
3327 | ||
e47c68e9 EA |
3328 | /* It should now be out of any other write domains, and we can update |
3329 | * the domain values for our changes. | |
3330 | */ | |
3331 | BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_CPU) != 0); | |
3332 | ||
1c5d22f7 | 3333 | old_read_domains = obj->read_domains; |
e47c68e9 EA |
3334 | obj->read_domains |= I915_GEM_DOMAIN_CPU; |
3335 | ||
1c5d22f7 CW |
3336 | trace_i915_gem_object_change_domain(obj, |
3337 | old_read_domains, | |
3338 | obj->write_domain); | |
3339 | ||
673a394b EA |
3340 | return 0; |
3341 | } | |
3342 | ||
673a394b EA |
3343 | /** |
3344 | * Pin an object to the GTT and evaluate the relocations landing in it. | |
3345 | */ | |
3346 | static int | |
9af90d19 CW |
3347 | i915_gem_execbuffer_relocate(struct drm_i915_gem_object *obj, |
3348 | struct drm_file *file_priv, | |
3349 | struct drm_i915_gem_exec_object2 *entry) | |
673a394b | 3350 | { |
9af90d19 | 3351 | struct drm_device *dev = obj->base.dev; |
0839ccb8 | 3352 | drm_i915_private_t *dev_priv = dev->dev_private; |
2549d6c2 | 3353 | struct drm_i915_gem_relocation_entry __user *user_relocs; |
9af90d19 CW |
3354 | struct drm_gem_object *target_obj = NULL; |
3355 | uint32_t target_handle = 0; | |
3356 | int i, ret = 0; | |
673a394b | 3357 | |
2549d6c2 | 3358 | user_relocs = (void __user *)(uintptr_t)entry->relocs_ptr; |
673a394b | 3359 | for (i = 0; i < entry->relocation_count; i++) { |
2549d6c2 | 3360 | struct drm_i915_gem_relocation_entry reloc; |
9af90d19 | 3361 | uint32_t target_offset; |
673a394b | 3362 | |
9af90d19 CW |
3363 | if (__copy_from_user_inatomic(&reloc, |
3364 | user_relocs+i, | |
3365 | sizeof(reloc))) { | |
3366 | ret = -EFAULT; | |
3367 | break; | |
76446cac | 3368 | } |
76446cac | 3369 | |
9af90d19 CW |
3370 | if (reloc.target_handle != target_handle) { |
3371 | drm_gem_object_unreference(target_obj); | |
673a394b | 3372 | |
9af90d19 CW |
3373 | target_obj = drm_gem_object_lookup(dev, file_priv, |
3374 | reloc.target_handle); | |
3375 | if (target_obj == NULL) { | |
3376 | ret = -ENOENT; | |
3377 | break; | |
3378 | } | |
3379 | ||
3380 | target_handle = reloc.target_handle; | |
673a394b | 3381 | } |
9af90d19 | 3382 | target_offset = to_intel_bo(target_obj)->gtt_offset; |
673a394b | 3383 | |
8542a0bb CW |
3384 | #if WATCH_RELOC |
3385 | DRM_INFO("%s: obj %p offset %08x target %d " | |
3386 | "read %08x write %08x gtt %08x " | |
3387 | "presumed %08x delta %08x\n", | |
3388 | __func__, | |
3389 | obj, | |
2549d6c2 CW |
3390 | (int) reloc.offset, |
3391 | (int) reloc.target_handle, | |
3392 | (int) reloc.read_domains, | |
3393 | (int) reloc.write_domain, | |
9af90d19 | 3394 | (int) target_offset, |
2549d6c2 CW |
3395 | (int) reloc.presumed_offset, |
3396 | reloc.delta); | |
8542a0bb CW |
3397 | #endif |
3398 | ||
673a394b EA |
3399 | /* The target buffer should have appeared before us in the |
3400 | * exec_object list, so it should have a GTT space bound by now. | |
3401 | */ | |
9af90d19 | 3402 | if (target_offset == 0) { |
673a394b | 3403 | DRM_ERROR("No GTT space found for object %d\n", |
2549d6c2 | 3404 | reloc.target_handle); |
9af90d19 CW |
3405 | ret = -EINVAL; |
3406 | break; | |
673a394b EA |
3407 | } |
3408 | ||
8542a0bb | 3409 | /* Validate that the target is in a valid r/w GPU domain */ |
2549d6c2 | 3410 | if (reloc.write_domain & (reloc.write_domain - 1)) { |
16edd550 DV |
3411 | DRM_ERROR("reloc with multiple write domains: " |
3412 | "obj %p target %d offset %d " | |
3413 | "read %08x write %08x", | |
2549d6c2 CW |
3414 | obj, reloc.target_handle, |
3415 | (int) reloc.offset, | |
3416 | reloc.read_domains, | |
3417 | reloc.write_domain); | |
9af90d19 CW |
3418 | ret = -EINVAL; |
3419 | break; | |
16edd550 | 3420 | } |
2549d6c2 CW |
3421 | if (reloc.write_domain & I915_GEM_DOMAIN_CPU || |
3422 | reloc.read_domains & I915_GEM_DOMAIN_CPU) { | |
e47c68e9 EA |
3423 | DRM_ERROR("reloc with read/write CPU domains: " |
3424 | "obj %p target %d offset %d " | |
3425 | "read %08x write %08x", | |
2549d6c2 CW |
3426 | obj, reloc.target_handle, |
3427 | (int) reloc.offset, | |
3428 | reloc.read_domains, | |
3429 | reloc.write_domain); | |
9af90d19 CW |
3430 | ret = -EINVAL; |
3431 | break; | |
e47c68e9 | 3432 | } |
2549d6c2 CW |
3433 | if (reloc.write_domain && target_obj->pending_write_domain && |
3434 | reloc.write_domain != target_obj->pending_write_domain) { | |
673a394b EA |
3435 | DRM_ERROR("Write domain conflict: " |
3436 | "obj %p target %d offset %d " | |
3437 | "new %08x old %08x\n", | |
2549d6c2 CW |
3438 | obj, reloc.target_handle, |
3439 | (int) reloc.offset, | |
3440 | reloc.write_domain, | |
673a394b | 3441 | target_obj->pending_write_domain); |
9af90d19 CW |
3442 | ret = -EINVAL; |
3443 | break; | |
673a394b EA |
3444 | } |
3445 | ||
2549d6c2 | 3446 | target_obj->pending_read_domains |= reloc.read_domains; |
878a3c37 | 3447 | target_obj->pending_write_domain |= reloc.write_domain; |
673a394b EA |
3448 | |
3449 | /* If the relocation already has the right value in it, no | |
3450 | * more work needs to be done. | |
3451 | */ | |
9af90d19 | 3452 | if (target_offset == reloc.presumed_offset) |
673a394b | 3453 | continue; |
673a394b | 3454 | |
8542a0bb | 3455 | /* Check that the relocation address is valid... */ |
9af90d19 | 3456 | if (reloc.offset > obj->base.size - 4) { |
8542a0bb CW |
3457 | DRM_ERROR("Relocation beyond object bounds: " |
3458 | "obj %p target %d offset %d size %d.\n", | |
2549d6c2 | 3459 | obj, reloc.target_handle, |
9af90d19 CW |
3460 | (int) reloc.offset, (int) obj->base.size); |
3461 | ret = -EINVAL; | |
3462 | break; | |
8542a0bb | 3463 | } |
2549d6c2 | 3464 | if (reloc.offset & 3) { |
8542a0bb CW |
3465 | DRM_ERROR("Relocation not 4-byte aligned: " |
3466 | "obj %p target %d offset %d.\n", | |
2549d6c2 CW |
3467 | obj, reloc.target_handle, |
3468 | (int) reloc.offset); | |
9af90d19 CW |
3469 | ret = -EINVAL; |
3470 | break; | |
8542a0bb CW |
3471 | } |
3472 | ||
3473 | /* and points to somewhere within the target object. */ | |
2549d6c2 | 3474 | if (reloc.delta >= target_obj->size) { |
8542a0bb CW |
3475 | DRM_ERROR("Relocation beyond target object bounds: " |
3476 | "obj %p target %d delta %d size %d.\n", | |
2549d6c2 CW |
3477 | obj, reloc.target_handle, |
3478 | (int) reloc.delta, (int) target_obj->size); | |
9af90d19 CW |
3479 | ret = -EINVAL; |
3480 | break; | |
673a394b EA |
3481 | } |
3482 | ||
9af90d19 CW |
3483 | reloc.delta += target_offset; |
3484 | if (obj->base.write_domain == I915_GEM_DOMAIN_CPU) { | |
f0c43d9b CW |
3485 | uint32_t page_offset = reloc.offset & ~PAGE_MASK; |
3486 | char *vaddr; | |
673a394b | 3487 | |
c48c43e4 | 3488 | vaddr = kmap_atomic(obj->pages[reloc.offset >> PAGE_SHIFT]); |
f0c43d9b | 3489 | *(uint32_t *)(vaddr + page_offset) = reloc.delta; |
c48c43e4 | 3490 | kunmap_atomic(vaddr); |
f0c43d9b CW |
3491 | } else { |
3492 | uint32_t __iomem *reloc_entry; | |
3493 | void __iomem *reloc_page; | |
b962442e | 3494 | |
9af90d19 CW |
3495 | ret = i915_gem_object_set_to_gtt_domain(&obj->base, 1); |
3496 | if (ret) | |
3497 | break; | |
b962442e | 3498 | |
f0c43d9b | 3499 | /* Map the page containing the relocation we're going to perform. */ |
9af90d19 | 3500 | reloc.offset += obj->gtt_offset; |
f0c43d9b | 3501 | reloc_page = io_mapping_map_atomic_wc(dev_priv->mm.gtt_mapping, |
c48c43e4 | 3502 | reloc.offset & PAGE_MASK); |
f0c43d9b CW |
3503 | reloc_entry = (uint32_t __iomem *) |
3504 | (reloc_page + (reloc.offset & ~PAGE_MASK)); | |
3505 | iowrite32(reloc.delta, reloc_entry); | |
c48c43e4 | 3506 | io_mapping_unmap_atomic(reloc_page); |
f0c43d9b | 3507 | } |
b962442e | 3508 | |
b5dc608c CW |
3509 | /* and update the user's relocation entry */ |
3510 | reloc.presumed_offset = target_offset; | |
3511 | if (__copy_to_user_inatomic(&user_relocs[i].presumed_offset, | |
3512 | &reloc.presumed_offset, | |
3513 | sizeof(reloc.presumed_offset))) { | |
3514 | ret = -EFAULT; | |
3515 | break; | |
3516 | } | |
b962442e | 3517 | } |
b962442e | 3518 | |
9af90d19 | 3519 | drm_gem_object_unreference(target_obj); |
673a394b EA |
3520 | return ret; |
3521 | } | |
3522 | ||
40a5f0de | 3523 | static int |
9af90d19 CW |
3524 | i915_gem_execbuffer_pin(struct drm_device *dev, |
3525 | struct drm_file *file, | |
3526 | struct drm_gem_object **object_list, | |
3527 | struct drm_i915_gem_exec_object2 *exec_list, | |
3528 | int count) | |
40a5f0de | 3529 | { |
9af90d19 CW |
3530 | struct drm_i915_private *dev_priv = dev->dev_private; |
3531 | int ret, i, retry; | |
40a5f0de | 3532 | |
9af90d19 CW |
3533 | /* attempt to pin all of the buffers into the GTT */ |
3534 | for (retry = 0; retry < 2; retry++) { | |
3535 | ret = 0; | |
3536 | for (i = 0; i < count; i++) { | |
3537 | struct drm_i915_gem_exec_object2 *entry = &exec_list[i]; | |
16e809ac | 3538 | struct drm_i915_gem_object *obj = to_intel_bo(object_list[i]); |
9af90d19 CW |
3539 | bool need_fence = |
3540 | entry->flags & EXEC_OBJECT_NEEDS_FENCE && | |
3541 | obj->tiling_mode != I915_TILING_NONE; | |
3542 | ||
16e809ac DV |
3543 | /* g33/pnv can't fence buffers in the unmappable part */ |
3544 | bool need_mappable = | |
3545 | entry->relocation_count ? true : need_fence; | |
3546 | ||
9af90d19 CW |
3547 | /* Check fence reg constraints and rebind if necessary */ |
3548 | if (need_fence && | |
3549 | !i915_gem_object_fence_offset_ok(&obj->base, | |
3550 | obj->tiling_mode)) { | |
3551 | ret = i915_gem_object_unbind(&obj->base); | |
3552 | if (ret) | |
3553 | break; | |
3554 | } | |
40a5f0de | 3555 | |
920afa77 | 3556 | ret = i915_gem_object_pin(&obj->base, |
16e809ac DV |
3557 | entry->alignment, |
3558 | need_mappable); | |
9af90d19 CW |
3559 | if (ret) |
3560 | break; | |
40a5f0de | 3561 | |
9af90d19 CW |
3562 | /* |
3563 | * Pre-965 chips need a fence register set up in order | |
3564 | * to properly handle blits to/from tiled surfaces. | |
3565 | */ | |
3566 | if (need_fence) { | |
3567 | ret = i915_gem_object_get_fence_reg(&obj->base, true); | |
3568 | if (ret) { | |
3569 | i915_gem_object_unpin(&obj->base); | |
3570 | break; | |
3571 | } | |
40a5f0de | 3572 | |
9af90d19 CW |
3573 | dev_priv->fence_regs[obj->fence_reg].gpu = true; |
3574 | } | |
40a5f0de | 3575 | |
9af90d19 | 3576 | entry->offset = obj->gtt_offset; |
40a5f0de EA |
3577 | } |
3578 | ||
9af90d19 CW |
3579 | while (i--) |
3580 | i915_gem_object_unpin(object_list[i]); | |
3581 | ||
3582 | if (ret == 0) | |
3583 | break; | |
673a394b | 3584 | |
9af90d19 CW |
3585 | if (ret != -ENOSPC || retry) |
3586 | return ret; | |
3587 | ||
3588 | ret = i915_gem_evict_everything(dev); | |
3589 | if (ret) | |
3590 | return ret; | |
40a5f0de EA |
3591 | } |
3592 | ||
2bc43b5c | 3593 | return 0; |
40a5f0de EA |
3594 | } |
3595 | ||
673a394b EA |
3596 | /* Throttle our rendering by waiting until the ring has completed our requests |
3597 | * emitted over 20 msec ago. | |
3598 | * | |
b962442e EA |
3599 | * Note that if we were to use the current jiffies each time around the loop, |
3600 | * we wouldn't escape the function with any frames outstanding if the time to | |
3601 | * render a frame was over 20ms. | |
3602 | * | |
673a394b EA |
3603 | * This should get us reasonable parallelism between CPU and GPU but also |
3604 | * relatively low latency when blocking on a particular request to finish. | |
3605 | */ | |
40a5f0de | 3606 | static int |
f787a5f5 | 3607 | i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file) |
40a5f0de | 3608 | { |
f787a5f5 CW |
3609 | struct drm_i915_private *dev_priv = dev->dev_private; |
3610 | struct drm_i915_file_private *file_priv = file->driver_priv; | |
b962442e | 3611 | unsigned long recent_enough = jiffies - msecs_to_jiffies(20); |
f787a5f5 CW |
3612 | struct drm_i915_gem_request *request; |
3613 | struct intel_ring_buffer *ring = NULL; | |
3614 | u32 seqno = 0; | |
3615 | int ret; | |
93533c29 | 3616 | |
1c25595f | 3617 | spin_lock(&file_priv->mm.lock); |
f787a5f5 | 3618 | list_for_each_entry(request, &file_priv->mm.request_list, client_list) { |
b962442e EA |
3619 | if (time_after_eq(request->emitted_jiffies, recent_enough)) |
3620 | break; | |
40a5f0de | 3621 | |
f787a5f5 CW |
3622 | ring = request->ring; |
3623 | seqno = request->seqno; | |
b962442e | 3624 | } |
1c25595f | 3625 | spin_unlock(&file_priv->mm.lock); |
40a5f0de | 3626 | |
f787a5f5 CW |
3627 | if (seqno == 0) |
3628 | return 0; | |
2bc43b5c | 3629 | |
f787a5f5 | 3630 | ret = 0; |
78501eac | 3631 | if (!i915_seqno_passed(ring->get_seqno(ring), seqno)) { |
f787a5f5 CW |
3632 | /* And wait for the seqno passing without holding any locks and |
3633 | * causing extra latency for others. This is safe as the irq | |
3634 | * generation is designed to be run atomically and so is | |
3635 | * lockless. | |
3636 | */ | |
78501eac | 3637 | ring->user_irq_get(ring); |
f787a5f5 | 3638 | ret = wait_event_interruptible(ring->irq_queue, |
78501eac | 3639 | i915_seqno_passed(ring->get_seqno(ring), seqno) |
f787a5f5 | 3640 | || atomic_read(&dev_priv->mm.wedged)); |
78501eac | 3641 | ring->user_irq_put(ring); |
40a5f0de | 3642 | |
f787a5f5 CW |
3643 | if (ret == 0 && atomic_read(&dev_priv->mm.wedged)) |
3644 | ret = -EIO; | |
40a5f0de EA |
3645 | } |
3646 | ||
f787a5f5 CW |
3647 | if (ret == 0) |
3648 | queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, 0); | |
40a5f0de EA |
3649 | |
3650 | return ret; | |
3651 | } | |
3652 | ||
83d60795 | 3653 | static int |
2549d6c2 CW |
3654 | i915_gem_check_execbuffer(struct drm_i915_gem_execbuffer2 *exec, |
3655 | uint64_t exec_offset) | |
83d60795 CW |
3656 | { |
3657 | uint32_t exec_start, exec_len; | |
3658 | ||
3659 | exec_start = (uint32_t) exec_offset + exec->batch_start_offset; | |
3660 | exec_len = (uint32_t) exec->batch_len; | |
3661 | ||
3662 | if ((exec_start | exec_len) & 0x7) | |
3663 | return -EINVAL; | |
3664 | ||
3665 | if (!exec_start) | |
3666 | return -EINVAL; | |
3667 | ||
3668 | return 0; | |
3669 | } | |
3670 | ||
6b95a207 | 3671 | static int |
2549d6c2 CW |
3672 | validate_exec_list(struct drm_i915_gem_exec_object2 *exec, |
3673 | int count) | |
6b95a207 | 3674 | { |
2549d6c2 | 3675 | int i; |
6b95a207 | 3676 | |
2549d6c2 CW |
3677 | for (i = 0; i < count; i++) { |
3678 | char __user *ptr = (char __user *)(uintptr_t)exec[i].relocs_ptr; | |
3679 | size_t length = exec[i].relocation_count * sizeof(struct drm_i915_gem_relocation_entry); | |
6b95a207 | 3680 | |
2549d6c2 CW |
3681 | if (!access_ok(VERIFY_READ, ptr, length)) |
3682 | return -EFAULT; | |
40a5f0de | 3683 | |
b5dc608c CW |
3684 | /* we may also need to update the presumed offsets */ |
3685 | if (!access_ok(VERIFY_WRITE, ptr, length)) | |
3686 | return -EFAULT; | |
3687 | ||
2549d6c2 CW |
3688 | if (fault_in_pages_readable(ptr, length)) |
3689 | return -EFAULT; | |
6b95a207 | 3690 | } |
6b95a207 | 3691 | |
83d60795 | 3692 | return 0; |
6b95a207 KH |
3693 | } |
3694 | ||
8dc5d147 | 3695 | static int |
76446cac | 3696 | i915_gem_do_execbuffer(struct drm_device *dev, void *data, |
9af90d19 | 3697 | struct drm_file *file, |
76446cac JB |
3698 | struct drm_i915_gem_execbuffer2 *args, |
3699 | struct drm_i915_gem_exec_object2 *exec_list) | |
673a394b EA |
3700 | { |
3701 | drm_i915_private_t *dev_priv = dev->dev_private; | |
673a394b EA |
3702 | struct drm_gem_object **object_list = NULL; |
3703 | struct drm_gem_object *batch_obj; | |
201361a5 | 3704 | struct drm_clip_rect *cliprects = NULL; |
8dc5d147 | 3705 | struct drm_i915_gem_request *request = NULL; |
9af90d19 | 3706 | int ret, i, flips; |
673a394b | 3707 | uint64_t exec_offset; |
673a394b | 3708 | |
852835f3 ZN |
3709 | struct intel_ring_buffer *ring = NULL; |
3710 | ||
30dbf0c0 CW |
3711 | ret = i915_gem_check_is_wedged(dev); |
3712 | if (ret) | |
3713 | return ret; | |
3714 | ||
2549d6c2 CW |
3715 | ret = validate_exec_list(exec_list, args->buffer_count); |
3716 | if (ret) | |
3717 | return ret; | |
3718 | ||
673a394b EA |
3719 | #if WATCH_EXEC |
3720 | DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n", | |
3721 | (int) args->buffers_ptr, args->buffer_count, args->batch_len); | |
3722 | #endif | |
549f7365 CW |
3723 | switch (args->flags & I915_EXEC_RING_MASK) { |
3724 | case I915_EXEC_DEFAULT: | |
3725 | case I915_EXEC_RENDER: | |
3726 | ring = &dev_priv->render_ring; | |
3727 | break; | |
3728 | case I915_EXEC_BSD: | |
d1b851fc | 3729 | if (!HAS_BSD(dev)) { |
549f7365 | 3730 | DRM_ERROR("execbuf with invalid ring (BSD)\n"); |
d1b851fc ZN |
3731 | return -EINVAL; |
3732 | } | |
3733 | ring = &dev_priv->bsd_ring; | |
549f7365 CW |
3734 | break; |
3735 | case I915_EXEC_BLT: | |
3736 | if (!HAS_BLT(dev)) { | |
3737 | DRM_ERROR("execbuf with invalid ring (BLT)\n"); | |
3738 | return -EINVAL; | |
3739 | } | |
3740 | ring = &dev_priv->blt_ring; | |
3741 | break; | |
3742 | default: | |
3743 | DRM_ERROR("execbuf with unknown ring: %d\n", | |
3744 | (int)(args->flags & I915_EXEC_RING_MASK)); | |
3745 | return -EINVAL; | |
d1b851fc ZN |
3746 | } |
3747 | ||
4f481ed2 EA |
3748 | if (args->buffer_count < 1) { |
3749 | DRM_ERROR("execbuf with %d buffers\n", args->buffer_count); | |
3750 | return -EINVAL; | |
3751 | } | |
c8e0f93a | 3752 | object_list = drm_malloc_ab(sizeof(*object_list), args->buffer_count); |
76446cac JB |
3753 | if (object_list == NULL) { |
3754 | DRM_ERROR("Failed to allocate object list for %d buffers\n", | |
673a394b EA |
3755 | args->buffer_count); |
3756 | ret = -ENOMEM; | |
3757 | goto pre_mutex_err; | |
3758 | } | |
673a394b | 3759 | |
201361a5 | 3760 | if (args->num_cliprects != 0) { |
9a298b2a EA |
3761 | cliprects = kcalloc(args->num_cliprects, sizeof(*cliprects), |
3762 | GFP_KERNEL); | |
a40e8d31 OA |
3763 | if (cliprects == NULL) { |
3764 | ret = -ENOMEM; | |
201361a5 | 3765 | goto pre_mutex_err; |
a40e8d31 | 3766 | } |
201361a5 EA |
3767 | |
3768 | ret = copy_from_user(cliprects, | |
3769 | (struct drm_clip_rect __user *) | |
3770 | (uintptr_t) args->cliprects_ptr, | |
3771 | sizeof(*cliprects) * args->num_cliprects); | |
3772 | if (ret != 0) { | |
3773 | DRM_ERROR("copy %d cliprects failed: %d\n", | |
3774 | args->num_cliprects, ret); | |
c877cdce | 3775 | ret = -EFAULT; |
201361a5 EA |
3776 | goto pre_mutex_err; |
3777 | } | |
3778 | } | |
3779 | ||
8dc5d147 CW |
3780 | request = kzalloc(sizeof(*request), GFP_KERNEL); |
3781 | if (request == NULL) { | |
3782 | ret = -ENOMEM; | |
40a5f0de | 3783 | goto pre_mutex_err; |
8dc5d147 | 3784 | } |
40a5f0de | 3785 | |
76c1dec1 CW |
3786 | ret = i915_mutex_lock_interruptible(dev); |
3787 | if (ret) | |
a198bc80 | 3788 | goto pre_mutex_err; |
673a394b EA |
3789 | |
3790 | if (dev_priv->mm.suspended) { | |
673a394b | 3791 | mutex_unlock(&dev->struct_mutex); |
a198bc80 CW |
3792 | ret = -EBUSY; |
3793 | goto pre_mutex_err; | |
673a394b EA |
3794 | } |
3795 | ||
ac94a962 | 3796 | /* Look up object handles */ |
673a394b | 3797 | for (i = 0; i < args->buffer_count; i++) { |
7e318e18 CW |
3798 | struct drm_i915_gem_object *obj_priv; |
3799 | ||
9af90d19 | 3800 | object_list[i] = drm_gem_object_lookup(dev, file, |
673a394b EA |
3801 | exec_list[i].handle); |
3802 | if (object_list[i] == NULL) { | |
3803 | DRM_ERROR("Invalid object handle %d at index %d\n", | |
3804 | exec_list[i].handle, i); | |
0ce907f8 CW |
3805 | /* prevent error path from reading uninitialized data */ |
3806 | args->buffer_count = i + 1; | |
bf79cb91 | 3807 | ret = -ENOENT; |
673a394b EA |
3808 | goto err; |
3809 | } | |
b70d11da | 3810 | |
23010e43 | 3811 | obj_priv = to_intel_bo(object_list[i]); |
b70d11da KH |
3812 | if (obj_priv->in_execbuffer) { |
3813 | DRM_ERROR("Object %p appears more than once in object list\n", | |
3814 | object_list[i]); | |
0ce907f8 CW |
3815 | /* prevent error path from reading uninitialized data */ |
3816 | args->buffer_count = i + 1; | |
bf79cb91 | 3817 | ret = -EINVAL; |
b70d11da KH |
3818 | goto err; |
3819 | } | |
3820 | obj_priv->in_execbuffer = true; | |
ac94a962 | 3821 | } |
673a394b | 3822 | |
9af90d19 CW |
3823 | /* Move the objects en-masse into the GTT, evicting if necessary. */ |
3824 | ret = i915_gem_execbuffer_pin(dev, file, | |
3825 | object_list, exec_list, | |
3826 | args->buffer_count); | |
3827 | if (ret) | |
3828 | goto err; | |
ac94a962 | 3829 | |
9af90d19 CW |
3830 | /* The objects are in their final locations, apply the relocations. */ |
3831 | for (i = 0; i < args->buffer_count; i++) { | |
3832 | struct drm_i915_gem_object *obj = to_intel_bo(object_list[i]); | |
3833 | obj->base.pending_read_domains = 0; | |
3834 | obj->base.pending_write_domain = 0; | |
3835 | ret = i915_gem_execbuffer_relocate(obj, file, &exec_list[i]); | |
3836 | if (ret) | |
ac94a962 | 3837 | goto err; |
673a394b EA |
3838 | } |
3839 | ||
3840 | /* Set the pending read domains for the batch buffer to COMMAND */ | |
3841 | batch_obj = object_list[args->buffer_count-1]; | |
5f26a2c7 CW |
3842 | if (batch_obj->pending_write_domain) { |
3843 | DRM_ERROR("Attempting to use self-modifying batch buffer\n"); | |
3844 | ret = -EINVAL; | |
3845 | goto err; | |
3846 | } | |
3847 | batch_obj->pending_read_domains |= I915_GEM_DOMAIN_COMMAND; | |
673a394b | 3848 | |
9af90d19 CW |
3849 | /* Sanity check the batch buffer */ |
3850 | exec_offset = to_intel_bo(batch_obj)->gtt_offset; | |
3851 | ret = i915_gem_check_execbuffer(args, exec_offset); | |
83d60795 CW |
3852 | if (ret != 0) { |
3853 | DRM_ERROR("execbuf with invalid offset/length\n"); | |
3854 | goto err; | |
3855 | } | |
3856 | ||
646f0f6e KP |
3857 | /* Zero the global flush/invalidate flags. These |
3858 | * will be modified as new domains are computed | |
3859 | * for each object | |
3860 | */ | |
3861 | dev->invalidate_domains = 0; | |
3862 | dev->flush_domains = 0; | |
9220434a | 3863 | dev_priv->mm.flush_rings = 0; |
7e318e18 CW |
3864 | for (i = 0; i < args->buffer_count; i++) |
3865 | i915_gem_object_set_to_gpu_domain(object_list[i], ring); | |
673a394b | 3866 | |
646f0f6e KP |
3867 | if (dev->invalidate_domains | dev->flush_domains) { |
3868 | #if WATCH_EXEC | |
3869 | DRM_INFO("%s: invalidate_domains %08x flush_domains %08x\n", | |
3870 | __func__, | |
3871 | dev->invalidate_domains, | |
3872 | dev->flush_domains); | |
3873 | #endif | |
9af90d19 | 3874 | i915_gem_flush(dev, file, |
646f0f6e | 3875 | dev->invalidate_domains, |
9220434a CW |
3876 | dev->flush_domains, |
3877 | dev_priv->mm.flush_rings); | |
646f0f6e | 3878 | } |
673a394b | 3879 | |
673a394b EA |
3880 | #if WATCH_COHERENCY |
3881 | for (i = 0; i < args->buffer_count; i++) { | |
3882 | i915_gem_object_check_coherency(object_list[i], | |
3883 | exec_list[i].handle); | |
3884 | } | |
3885 | #endif | |
3886 | ||
673a394b | 3887 | #if WATCH_EXEC |
6911a9b8 | 3888 | i915_gem_dump_object(batch_obj, |
673a394b EA |
3889 | args->batch_len, |
3890 | __func__, | |
3891 | ~0); | |
3892 | #endif | |
3893 | ||
e59f2bac CW |
3894 | /* Check for any pending flips. As we only maintain a flip queue depth |
3895 | * of 1, we can simply insert a WAIT for the next display flip prior | |
3896 | * to executing the batch and avoid stalling the CPU. | |
3897 | */ | |
3898 | flips = 0; | |
3899 | for (i = 0; i < args->buffer_count; i++) { | |
3900 | if (object_list[i]->write_domain) | |
3901 | flips |= atomic_read(&to_intel_bo(object_list[i])->pending_flip); | |
3902 | } | |
3903 | if (flips) { | |
3904 | int plane, flip_mask; | |
3905 | ||
3906 | for (plane = 0; flips >> plane; plane++) { | |
3907 | if (((flips >> plane) & 1) == 0) | |
3908 | continue; | |
3909 | ||
3910 | if (plane) | |
3911 | flip_mask = MI_WAIT_FOR_PLANE_B_FLIP; | |
3912 | else | |
3913 | flip_mask = MI_WAIT_FOR_PLANE_A_FLIP; | |
3914 | ||
e1f99ce6 CW |
3915 | ret = intel_ring_begin(ring, 2); |
3916 | if (ret) | |
3917 | goto err; | |
3918 | ||
78501eac CW |
3919 | intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask); |
3920 | intel_ring_emit(ring, MI_NOOP); | |
3921 | intel_ring_advance(ring); | |
e59f2bac CW |
3922 | } |
3923 | } | |
3924 | ||
673a394b | 3925 | /* Exec the batchbuffer */ |
78501eac | 3926 | ret = ring->dispatch_execbuffer(ring, args, cliprects, exec_offset); |
673a394b EA |
3927 | if (ret) { |
3928 | DRM_ERROR("dispatch failed %d\n", ret); | |
3929 | goto err; | |
3930 | } | |
3931 | ||
673a394b EA |
3932 | for (i = 0; i < args->buffer_count; i++) { |
3933 | struct drm_gem_object *obj = object_list[i]; | |
673a394b | 3934 | |
7e318e18 CW |
3935 | obj->read_domains = obj->pending_read_domains; |
3936 | obj->write_domain = obj->pending_write_domain; | |
3937 | ||
617dbe27 | 3938 | i915_gem_object_move_to_active(obj, ring); |
7e318e18 CW |
3939 | if (obj->write_domain) { |
3940 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); | |
3941 | obj_priv->dirty = 1; | |
3942 | list_move_tail(&obj_priv->gpu_write_list, | |
64193406 | 3943 | &ring->gpu_write_list); |
7e318e18 CW |
3944 | intel_mark_busy(dev, obj); |
3945 | } | |
3946 | ||
3947 | trace_i915_gem_object_change_domain(obj, | |
3948 | obj->read_domains, | |
3949 | obj->write_domain); | |
673a394b | 3950 | } |
673a394b | 3951 | |
7e318e18 CW |
3952 | /* |
3953 | * Ensure that the commands in the batch buffer are | |
3954 | * finished before the interrupt fires | |
3955 | */ | |
3956 | i915_retire_commands(dev, ring); | |
3957 | ||
3cce469c CW |
3958 | if (i915_add_request(dev, file, request, ring)) |
3959 | ring->outstanding_lazy_request = true; | |
3960 | else | |
3961 | request = NULL; | |
673a394b | 3962 | |
673a394b | 3963 | err: |
b70d11da | 3964 | for (i = 0; i < args->buffer_count; i++) { |
7e318e18 CW |
3965 | if (object_list[i] == NULL) |
3966 | break; | |
3967 | ||
3968 | to_intel_bo(object_list[i])->in_execbuffer = false; | |
aad87dff | 3969 | drm_gem_object_unreference(object_list[i]); |
b70d11da | 3970 | } |
673a394b | 3971 | |
673a394b EA |
3972 | mutex_unlock(&dev->struct_mutex); |
3973 | ||
93533c29 | 3974 | pre_mutex_err: |
8e7d2b2c | 3975 | drm_free_large(object_list); |
9a298b2a | 3976 | kfree(cliprects); |
8dc5d147 | 3977 | kfree(request); |
673a394b EA |
3978 | |
3979 | return ret; | |
3980 | } | |
3981 | ||
76446cac JB |
3982 | /* |
3983 | * Legacy execbuffer just creates an exec2 list from the original exec object | |
3984 | * list array and passes it to the real function. | |
3985 | */ | |
3986 | int | |
3987 | i915_gem_execbuffer(struct drm_device *dev, void *data, | |
3988 | struct drm_file *file_priv) | |
3989 | { | |
3990 | struct drm_i915_gem_execbuffer *args = data; | |
3991 | struct drm_i915_gem_execbuffer2 exec2; | |
3992 | struct drm_i915_gem_exec_object *exec_list = NULL; | |
3993 | struct drm_i915_gem_exec_object2 *exec2_list = NULL; | |
3994 | int ret, i; | |
3995 | ||
3996 | #if WATCH_EXEC | |
3997 | DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n", | |
3998 | (int) args->buffers_ptr, args->buffer_count, args->batch_len); | |
3999 | #endif | |
4000 | ||
4001 | if (args->buffer_count < 1) { | |
4002 | DRM_ERROR("execbuf with %d buffers\n", args->buffer_count); | |
4003 | return -EINVAL; | |
4004 | } | |
4005 | ||
4006 | /* Copy in the exec list from userland */ | |
4007 | exec_list = drm_malloc_ab(sizeof(*exec_list), args->buffer_count); | |
4008 | exec2_list = drm_malloc_ab(sizeof(*exec2_list), args->buffer_count); | |
4009 | if (exec_list == NULL || exec2_list == NULL) { | |
4010 | DRM_ERROR("Failed to allocate exec list for %d buffers\n", | |
4011 | args->buffer_count); | |
4012 | drm_free_large(exec_list); | |
4013 | drm_free_large(exec2_list); | |
4014 | return -ENOMEM; | |
4015 | } | |
4016 | ret = copy_from_user(exec_list, | |
4017 | (struct drm_i915_relocation_entry __user *) | |
4018 | (uintptr_t) args->buffers_ptr, | |
4019 | sizeof(*exec_list) * args->buffer_count); | |
4020 | if (ret != 0) { | |
4021 | DRM_ERROR("copy %d exec entries failed %d\n", | |
4022 | args->buffer_count, ret); | |
4023 | drm_free_large(exec_list); | |
4024 | drm_free_large(exec2_list); | |
4025 | return -EFAULT; | |
4026 | } | |
4027 | ||
4028 | for (i = 0; i < args->buffer_count; i++) { | |
4029 | exec2_list[i].handle = exec_list[i].handle; | |
4030 | exec2_list[i].relocation_count = exec_list[i].relocation_count; | |
4031 | exec2_list[i].relocs_ptr = exec_list[i].relocs_ptr; | |
4032 | exec2_list[i].alignment = exec_list[i].alignment; | |
4033 | exec2_list[i].offset = exec_list[i].offset; | |
a6c45cf0 | 4034 | if (INTEL_INFO(dev)->gen < 4) |
76446cac JB |
4035 | exec2_list[i].flags = EXEC_OBJECT_NEEDS_FENCE; |
4036 | else | |
4037 | exec2_list[i].flags = 0; | |
4038 | } | |
4039 | ||
4040 | exec2.buffers_ptr = args->buffers_ptr; | |
4041 | exec2.buffer_count = args->buffer_count; | |
4042 | exec2.batch_start_offset = args->batch_start_offset; | |
4043 | exec2.batch_len = args->batch_len; | |
4044 | exec2.DR1 = args->DR1; | |
4045 | exec2.DR4 = args->DR4; | |
4046 | exec2.num_cliprects = args->num_cliprects; | |
4047 | exec2.cliprects_ptr = args->cliprects_ptr; | |
852835f3 | 4048 | exec2.flags = I915_EXEC_RENDER; |
76446cac JB |
4049 | |
4050 | ret = i915_gem_do_execbuffer(dev, data, file_priv, &exec2, exec2_list); | |
4051 | if (!ret) { | |
4052 | /* Copy the new buffer offsets back to the user's exec list. */ | |
4053 | for (i = 0; i < args->buffer_count; i++) | |
4054 | exec_list[i].offset = exec2_list[i].offset; | |
4055 | /* ... and back out to userspace */ | |
4056 | ret = copy_to_user((struct drm_i915_relocation_entry __user *) | |
4057 | (uintptr_t) args->buffers_ptr, | |
4058 | exec_list, | |
4059 | sizeof(*exec_list) * args->buffer_count); | |
4060 | if (ret) { | |
4061 | ret = -EFAULT; | |
4062 | DRM_ERROR("failed to copy %d exec entries " | |
4063 | "back to user (%d)\n", | |
4064 | args->buffer_count, ret); | |
4065 | } | |
76446cac JB |
4066 | } |
4067 | ||
4068 | drm_free_large(exec_list); | |
4069 | drm_free_large(exec2_list); | |
4070 | return ret; | |
4071 | } | |
4072 | ||
4073 | int | |
4074 | i915_gem_execbuffer2(struct drm_device *dev, void *data, | |
4075 | struct drm_file *file_priv) | |
4076 | { | |
4077 | struct drm_i915_gem_execbuffer2 *args = data; | |
4078 | struct drm_i915_gem_exec_object2 *exec2_list = NULL; | |
4079 | int ret; | |
4080 | ||
4081 | #if WATCH_EXEC | |
4082 | DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n", | |
4083 | (int) args->buffers_ptr, args->buffer_count, args->batch_len); | |
4084 | #endif | |
4085 | ||
4086 | if (args->buffer_count < 1) { | |
4087 | DRM_ERROR("execbuf2 with %d buffers\n", args->buffer_count); | |
4088 | return -EINVAL; | |
4089 | } | |
4090 | ||
4091 | exec2_list = drm_malloc_ab(sizeof(*exec2_list), args->buffer_count); | |
4092 | if (exec2_list == NULL) { | |
4093 | DRM_ERROR("Failed to allocate exec list for %d buffers\n", | |
4094 | args->buffer_count); | |
4095 | return -ENOMEM; | |
4096 | } | |
4097 | ret = copy_from_user(exec2_list, | |
4098 | (struct drm_i915_relocation_entry __user *) | |
4099 | (uintptr_t) args->buffers_ptr, | |
4100 | sizeof(*exec2_list) * args->buffer_count); | |
4101 | if (ret != 0) { | |
4102 | DRM_ERROR("copy %d exec entries failed %d\n", | |
4103 | args->buffer_count, ret); | |
4104 | drm_free_large(exec2_list); | |
4105 | return -EFAULT; | |
4106 | } | |
4107 | ||
4108 | ret = i915_gem_do_execbuffer(dev, data, file_priv, args, exec2_list); | |
4109 | if (!ret) { | |
4110 | /* Copy the new buffer offsets back to the user's exec list. */ | |
4111 | ret = copy_to_user((struct drm_i915_relocation_entry __user *) | |
4112 | (uintptr_t) args->buffers_ptr, | |
4113 | exec2_list, | |
4114 | sizeof(*exec2_list) * args->buffer_count); | |
4115 | if (ret) { | |
4116 | ret = -EFAULT; | |
4117 | DRM_ERROR("failed to copy %d exec entries " | |
4118 | "back to user (%d)\n", | |
4119 | args->buffer_count, ret); | |
4120 | } | |
4121 | } | |
4122 | ||
4123 | drm_free_large(exec2_list); | |
4124 | return ret; | |
4125 | } | |
4126 | ||
673a394b | 4127 | int |
920afa77 DV |
4128 | i915_gem_object_pin(struct drm_gem_object *obj, uint32_t alignment, |
4129 | bool mappable) | |
673a394b EA |
4130 | { |
4131 | struct drm_device *dev = obj->dev; | |
f13d3f73 | 4132 | struct drm_i915_private *dev_priv = dev->dev_private; |
23010e43 | 4133 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
673a394b EA |
4134 | int ret; |
4135 | ||
778c3544 | 4136 | BUG_ON(obj_priv->pin_count == DRM_I915_GEM_OBJECT_MAX_PIN_COUNT); |
23bc5982 | 4137 | WARN_ON(i915_verify_lists(dev)); |
ac0c6b5a CW |
4138 | |
4139 | if (obj_priv->gtt_space != NULL) { | |
4140 | if (alignment == 0) | |
4141 | alignment = i915_gem_get_gtt_alignment(obj); | |
16e809ac DV |
4142 | if (obj_priv->gtt_offset & (alignment - 1) || |
4143 | (mappable && !i915_gem_object_cpu_accessible(obj_priv))) { | |
ae7d49d8 CW |
4144 | WARN(obj_priv->pin_count, |
4145 | "bo is already pinned with incorrect alignment:" | |
4146 | " offset=%x, req.alignment=%x\n", | |
4147 | obj_priv->gtt_offset, alignment); | |
ac0c6b5a CW |
4148 | ret = i915_gem_object_unbind(obj); |
4149 | if (ret) | |
4150 | return ret; | |
4151 | } | |
4152 | } | |
4153 | ||
673a394b | 4154 | if (obj_priv->gtt_space == NULL) { |
920afa77 | 4155 | ret = i915_gem_object_bind_to_gtt(obj, alignment, mappable); |
9731129c | 4156 | if (ret) |
673a394b | 4157 | return ret; |
22c344e9 | 4158 | } |
76446cac | 4159 | |
673a394b EA |
4160 | obj_priv->pin_count++; |
4161 | ||
4162 | /* If the object is not active and not pending a flush, | |
4163 | * remove it from the inactive list | |
4164 | */ | |
4165 | if (obj_priv->pin_count == 1) { | |
fb7d516a | 4166 | i915_gem_info_add_pin(dev_priv, obj, mappable); |
f13d3f73 | 4167 | if (!obj_priv->active) |
69dc4987 | 4168 | list_move_tail(&obj_priv->mm_list, |
f13d3f73 | 4169 | &dev_priv->mm.pinned_list); |
673a394b | 4170 | } |
fb7d516a | 4171 | BUG_ON(!obj_priv->pin_mappable && mappable); |
673a394b | 4172 | |
23bc5982 | 4173 | WARN_ON(i915_verify_lists(dev)); |
673a394b EA |
4174 | return 0; |
4175 | } | |
4176 | ||
4177 | void | |
4178 | i915_gem_object_unpin(struct drm_gem_object *obj) | |
4179 | { | |
4180 | struct drm_device *dev = obj->dev; | |
4181 | drm_i915_private_t *dev_priv = dev->dev_private; | |
23010e43 | 4182 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
673a394b | 4183 | |
23bc5982 | 4184 | WARN_ON(i915_verify_lists(dev)); |
673a394b EA |
4185 | obj_priv->pin_count--; |
4186 | BUG_ON(obj_priv->pin_count < 0); | |
4187 | BUG_ON(obj_priv->gtt_space == NULL); | |
4188 | ||
4189 | /* If the object is no longer pinned, and is | |
4190 | * neither active nor being flushed, then stick it on | |
4191 | * the inactive list | |
4192 | */ | |
4193 | if (obj_priv->pin_count == 0) { | |
f13d3f73 | 4194 | if (!obj_priv->active) |
69dc4987 | 4195 | list_move_tail(&obj_priv->mm_list, |
673a394b | 4196 | &dev_priv->mm.inactive_list); |
fb7d516a | 4197 | i915_gem_info_remove_pin(dev_priv, obj); |
673a394b | 4198 | } |
23bc5982 | 4199 | WARN_ON(i915_verify_lists(dev)); |
673a394b EA |
4200 | } |
4201 | ||
4202 | int | |
4203 | i915_gem_pin_ioctl(struct drm_device *dev, void *data, | |
4204 | struct drm_file *file_priv) | |
4205 | { | |
4206 | struct drm_i915_gem_pin *args = data; | |
4207 | struct drm_gem_object *obj; | |
4208 | struct drm_i915_gem_object *obj_priv; | |
4209 | int ret; | |
4210 | ||
1d7cfea1 CW |
4211 | ret = i915_mutex_lock_interruptible(dev); |
4212 | if (ret) | |
4213 | return ret; | |
673a394b EA |
4214 | |
4215 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); | |
4216 | if (obj == NULL) { | |
1d7cfea1 CW |
4217 | ret = -ENOENT; |
4218 | goto unlock; | |
673a394b | 4219 | } |
23010e43 | 4220 | obj_priv = to_intel_bo(obj); |
673a394b | 4221 | |
bb6baf76 CW |
4222 | if (obj_priv->madv != I915_MADV_WILLNEED) { |
4223 | DRM_ERROR("Attempting to pin a purgeable buffer\n"); | |
1d7cfea1 CW |
4224 | ret = -EINVAL; |
4225 | goto out; | |
3ef94daa CW |
4226 | } |
4227 | ||
79e53945 JB |
4228 | if (obj_priv->pin_filp != NULL && obj_priv->pin_filp != file_priv) { |
4229 | DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n", | |
4230 | args->handle); | |
1d7cfea1 CW |
4231 | ret = -EINVAL; |
4232 | goto out; | |
79e53945 JB |
4233 | } |
4234 | ||
4235 | obj_priv->user_pin_count++; | |
4236 | obj_priv->pin_filp = file_priv; | |
4237 | if (obj_priv->user_pin_count == 1) { | |
920afa77 | 4238 | ret = i915_gem_object_pin(obj, args->alignment, true); |
1d7cfea1 CW |
4239 | if (ret) |
4240 | goto out; | |
673a394b EA |
4241 | } |
4242 | ||
4243 | /* XXX - flush the CPU caches for pinned objects | |
4244 | * as the X server doesn't manage domains yet | |
4245 | */ | |
e47c68e9 | 4246 | i915_gem_object_flush_cpu_write_domain(obj); |
673a394b | 4247 | args->offset = obj_priv->gtt_offset; |
1d7cfea1 | 4248 | out: |
673a394b | 4249 | drm_gem_object_unreference(obj); |
1d7cfea1 | 4250 | unlock: |
673a394b | 4251 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 4252 | return ret; |
673a394b EA |
4253 | } |
4254 | ||
4255 | int | |
4256 | i915_gem_unpin_ioctl(struct drm_device *dev, void *data, | |
4257 | struct drm_file *file_priv) | |
4258 | { | |
4259 | struct drm_i915_gem_pin *args = data; | |
4260 | struct drm_gem_object *obj; | |
79e53945 | 4261 | struct drm_i915_gem_object *obj_priv; |
76c1dec1 | 4262 | int ret; |
673a394b | 4263 | |
1d7cfea1 CW |
4264 | ret = i915_mutex_lock_interruptible(dev); |
4265 | if (ret) | |
4266 | return ret; | |
673a394b EA |
4267 | |
4268 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); | |
4269 | if (obj == NULL) { | |
1d7cfea1 CW |
4270 | ret = -ENOENT; |
4271 | goto unlock; | |
673a394b | 4272 | } |
23010e43 | 4273 | obj_priv = to_intel_bo(obj); |
76c1dec1 | 4274 | |
79e53945 JB |
4275 | if (obj_priv->pin_filp != file_priv) { |
4276 | DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n", | |
4277 | args->handle); | |
1d7cfea1 CW |
4278 | ret = -EINVAL; |
4279 | goto out; | |
79e53945 JB |
4280 | } |
4281 | obj_priv->user_pin_count--; | |
4282 | if (obj_priv->user_pin_count == 0) { | |
4283 | obj_priv->pin_filp = NULL; | |
4284 | i915_gem_object_unpin(obj); | |
4285 | } | |
673a394b | 4286 | |
1d7cfea1 | 4287 | out: |
673a394b | 4288 | drm_gem_object_unreference(obj); |
1d7cfea1 | 4289 | unlock: |
673a394b | 4290 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 4291 | return ret; |
673a394b EA |
4292 | } |
4293 | ||
4294 | int | |
4295 | i915_gem_busy_ioctl(struct drm_device *dev, void *data, | |
4296 | struct drm_file *file_priv) | |
4297 | { | |
4298 | struct drm_i915_gem_busy *args = data; | |
4299 | struct drm_gem_object *obj; | |
4300 | struct drm_i915_gem_object *obj_priv; | |
30dbf0c0 CW |
4301 | int ret; |
4302 | ||
76c1dec1 | 4303 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 4304 | if (ret) |
76c1dec1 | 4305 | return ret; |
673a394b | 4306 | |
673a394b EA |
4307 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); |
4308 | if (obj == NULL) { | |
1d7cfea1 CW |
4309 | ret = -ENOENT; |
4310 | goto unlock; | |
673a394b | 4311 | } |
1d7cfea1 | 4312 | obj_priv = to_intel_bo(obj); |
d1b851fc | 4313 | |
0be555b6 CW |
4314 | /* Count all active objects as busy, even if they are currently not used |
4315 | * by the gpu. Users of this interface expect objects to eventually | |
4316 | * become non-busy without any further actions, therefore emit any | |
4317 | * necessary flushes here. | |
c4de0a5d | 4318 | */ |
0be555b6 CW |
4319 | args->busy = obj_priv->active; |
4320 | if (args->busy) { | |
4321 | /* Unconditionally flush objects, even when the gpu still uses this | |
4322 | * object. Userspace calling this function indicates that it wants to | |
4323 | * use this buffer rather sooner than later, so issuing the required | |
4324 | * flush earlier is beneficial. | |
4325 | */ | |
c78ec30b CW |
4326 | if (obj->write_domain & I915_GEM_GPU_DOMAINS) |
4327 | i915_gem_flush_ring(dev, file_priv, | |
9220434a CW |
4328 | obj_priv->ring, |
4329 | 0, obj->write_domain); | |
0be555b6 CW |
4330 | |
4331 | /* Update the active list for the hardware's current position. | |
4332 | * Otherwise this only updates on a delayed timer or when irqs | |
4333 | * are actually unmasked, and our working set ends up being | |
4334 | * larger than required. | |
4335 | */ | |
4336 | i915_gem_retire_requests_ring(dev, obj_priv->ring); | |
4337 | ||
4338 | args->busy = obj_priv->active; | |
4339 | } | |
673a394b EA |
4340 | |
4341 | drm_gem_object_unreference(obj); | |
1d7cfea1 | 4342 | unlock: |
673a394b | 4343 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 4344 | return ret; |
673a394b EA |
4345 | } |
4346 | ||
4347 | int | |
4348 | i915_gem_throttle_ioctl(struct drm_device *dev, void *data, | |
4349 | struct drm_file *file_priv) | |
4350 | { | |
4351 | return i915_gem_ring_throttle(dev, file_priv); | |
4352 | } | |
4353 | ||
3ef94daa CW |
4354 | int |
4355 | i915_gem_madvise_ioctl(struct drm_device *dev, void *data, | |
4356 | struct drm_file *file_priv) | |
4357 | { | |
4358 | struct drm_i915_gem_madvise *args = data; | |
4359 | struct drm_gem_object *obj; | |
4360 | struct drm_i915_gem_object *obj_priv; | |
76c1dec1 | 4361 | int ret; |
3ef94daa CW |
4362 | |
4363 | switch (args->madv) { | |
4364 | case I915_MADV_DONTNEED: | |
4365 | case I915_MADV_WILLNEED: | |
4366 | break; | |
4367 | default: | |
4368 | return -EINVAL; | |
4369 | } | |
4370 | ||
1d7cfea1 CW |
4371 | ret = i915_mutex_lock_interruptible(dev); |
4372 | if (ret) | |
4373 | return ret; | |
4374 | ||
3ef94daa CW |
4375 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); |
4376 | if (obj == NULL) { | |
1d7cfea1 CW |
4377 | ret = -ENOENT; |
4378 | goto unlock; | |
3ef94daa | 4379 | } |
23010e43 | 4380 | obj_priv = to_intel_bo(obj); |
3ef94daa CW |
4381 | |
4382 | if (obj_priv->pin_count) { | |
1d7cfea1 CW |
4383 | ret = -EINVAL; |
4384 | goto out; | |
3ef94daa CW |
4385 | } |
4386 | ||
bb6baf76 CW |
4387 | if (obj_priv->madv != __I915_MADV_PURGED) |
4388 | obj_priv->madv = args->madv; | |
3ef94daa | 4389 | |
2d7ef395 CW |
4390 | /* if the object is no longer bound, discard its backing storage */ |
4391 | if (i915_gem_object_is_purgeable(obj_priv) && | |
4392 | obj_priv->gtt_space == NULL) | |
4393 | i915_gem_object_truncate(obj); | |
4394 | ||
bb6baf76 CW |
4395 | args->retained = obj_priv->madv != __I915_MADV_PURGED; |
4396 | ||
1d7cfea1 | 4397 | out: |
3ef94daa | 4398 | drm_gem_object_unreference(obj); |
1d7cfea1 | 4399 | unlock: |
3ef94daa | 4400 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 4401 | return ret; |
3ef94daa CW |
4402 | } |
4403 | ||
ac52bc56 DV |
4404 | struct drm_gem_object * i915_gem_alloc_object(struct drm_device *dev, |
4405 | size_t size) | |
4406 | { | |
73aa808f | 4407 | struct drm_i915_private *dev_priv = dev->dev_private; |
c397b908 | 4408 | struct drm_i915_gem_object *obj; |
ac52bc56 | 4409 | |
c397b908 DV |
4410 | obj = kzalloc(sizeof(*obj), GFP_KERNEL); |
4411 | if (obj == NULL) | |
4412 | return NULL; | |
673a394b | 4413 | |
c397b908 DV |
4414 | if (drm_gem_object_init(dev, &obj->base, size) != 0) { |
4415 | kfree(obj); | |
4416 | return NULL; | |
4417 | } | |
673a394b | 4418 | |
73aa808f CW |
4419 | i915_gem_info_add_obj(dev_priv, size); |
4420 | ||
c397b908 DV |
4421 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; |
4422 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; | |
673a394b | 4423 | |
c397b908 | 4424 | obj->agp_type = AGP_USER_MEMORY; |
62b8b215 | 4425 | obj->base.driver_private = NULL; |
c397b908 | 4426 | obj->fence_reg = I915_FENCE_REG_NONE; |
69dc4987 CW |
4427 | INIT_LIST_HEAD(&obj->mm_list); |
4428 | INIT_LIST_HEAD(&obj->ring_list); | |
c397b908 | 4429 | INIT_LIST_HEAD(&obj->gpu_write_list); |
c397b908 | 4430 | obj->madv = I915_MADV_WILLNEED; |
de151cf6 | 4431 | |
c397b908 DV |
4432 | return &obj->base; |
4433 | } | |
4434 | ||
4435 | int i915_gem_init_object(struct drm_gem_object *obj) | |
4436 | { | |
4437 | BUG(); | |
de151cf6 | 4438 | |
673a394b EA |
4439 | return 0; |
4440 | } | |
4441 | ||
be72615b | 4442 | static void i915_gem_free_object_tail(struct drm_gem_object *obj) |
673a394b | 4443 | { |
de151cf6 | 4444 | struct drm_device *dev = obj->dev; |
be72615b | 4445 | drm_i915_private_t *dev_priv = dev->dev_private; |
23010e43 | 4446 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
be72615b | 4447 | int ret; |
673a394b | 4448 | |
be72615b CW |
4449 | ret = i915_gem_object_unbind(obj); |
4450 | if (ret == -ERESTARTSYS) { | |
69dc4987 | 4451 | list_move(&obj_priv->mm_list, |
be72615b CW |
4452 | &dev_priv->mm.deferred_free_list); |
4453 | return; | |
4454 | } | |
673a394b | 4455 | |
39a01d1f | 4456 | if (obj->map_list.map) |
7e616158 | 4457 | i915_gem_free_mmap_offset(obj); |
de151cf6 | 4458 | |
c397b908 | 4459 | drm_gem_object_release(obj); |
73aa808f | 4460 | i915_gem_info_remove_obj(dev_priv, obj->size); |
c397b908 | 4461 | |
9a298b2a | 4462 | kfree(obj_priv->page_cpu_valid); |
280b713b | 4463 | kfree(obj_priv->bit_17); |
c397b908 | 4464 | kfree(obj_priv); |
673a394b EA |
4465 | } |
4466 | ||
be72615b CW |
4467 | void i915_gem_free_object(struct drm_gem_object *obj) |
4468 | { | |
4469 | struct drm_device *dev = obj->dev; | |
4470 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); | |
4471 | ||
4472 | trace_i915_gem_object_destroy(obj); | |
4473 | ||
4474 | while (obj_priv->pin_count > 0) | |
4475 | i915_gem_object_unpin(obj); | |
4476 | ||
4477 | if (obj_priv->phys_obj) | |
4478 | i915_gem_detach_phys_object(dev, obj); | |
4479 | ||
4480 | i915_gem_free_object_tail(obj); | |
4481 | } | |
4482 | ||
29105ccc CW |
4483 | int |
4484 | i915_gem_idle(struct drm_device *dev) | |
4485 | { | |
4486 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4487 | int ret; | |
28dfe52a | 4488 | |
29105ccc | 4489 | mutex_lock(&dev->struct_mutex); |
1c5d22f7 | 4490 | |
87acb0a5 | 4491 | if (dev_priv->mm.suspended) { |
29105ccc CW |
4492 | mutex_unlock(&dev->struct_mutex); |
4493 | return 0; | |
28dfe52a EA |
4494 | } |
4495 | ||
29105ccc | 4496 | ret = i915_gpu_idle(dev); |
6dbe2772 KP |
4497 | if (ret) { |
4498 | mutex_unlock(&dev->struct_mutex); | |
673a394b | 4499 | return ret; |
6dbe2772 | 4500 | } |
673a394b | 4501 | |
29105ccc CW |
4502 | /* Under UMS, be paranoid and evict. */ |
4503 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) { | |
b47eb4a2 | 4504 | ret = i915_gem_evict_inactive(dev); |
29105ccc CW |
4505 | if (ret) { |
4506 | mutex_unlock(&dev->struct_mutex); | |
4507 | return ret; | |
4508 | } | |
4509 | } | |
4510 | ||
4511 | /* Hack! Don't let anybody do execbuf while we don't control the chip. | |
4512 | * We need to replace this with a semaphore, or something. | |
4513 | * And not confound mm.suspended! | |
4514 | */ | |
4515 | dev_priv->mm.suspended = 1; | |
bc0c7f14 | 4516 | del_timer_sync(&dev_priv->hangcheck_timer); |
29105ccc CW |
4517 | |
4518 | i915_kernel_lost_context(dev); | |
6dbe2772 | 4519 | i915_gem_cleanup_ringbuffer(dev); |
29105ccc | 4520 | |
6dbe2772 KP |
4521 | mutex_unlock(&dev->struct_mutex); |
4522 | ||
29105ccc CW |
4523 | /* Cancel the retire work handler, which should be idle now. */ |
4524 | cancel_delayed_work_sync(&dev_priv->mm.retire_work); | |
4525 | ||
673a394b EA |
4526 | return 0; |
4527 | } | |
4528 | ||
e552eb70 JB |
4529 | /* |
4530 | * 965+ support PIPE_CONTROL commands, which provide finer grained control | |
4531 | * over cache flushing. | |
4532 | */ | |
8187a2b7 | 4533 | static int |
e552eb70 JB |
4534 | i915_gem_init_pipe_control(struct drm_device *dev) |
4535 | { | |
4536 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4537 | struct drm_gem_object *obj; | |
4538 | struct drm_i915_gem_object *obj_priv; | |
4539 | int ret; | |
4540 | ||
34dc4d44 | 4541 | obj = i915_gem_alloc_object(dev, 4096); |
e552eb70 JB |
4542 | if (obj == NULL) { |
4543 | DRM_ERROR("Failed to allocate seqno page\n"); | |
4544 | ret = -ENOMEM; | |
4545 | goto err; | |
4546 | } | |
4547 | obj_priv = to_intel_bo(obj); | |
4548 | obj_priv->agp_type = AGP_USER_CACHED_MEMORY; | |
4549 | ||
920afa77 | 4550 | ret = i915_gem_object_pin(obj, 4096, true); |
e552eb70 JB |
4551 | if (ret) |
4552 | goto err_unref; | |
4553 | ||
4554 | dev_priv->seqno_gfx_addr = obj_priv->gtt_offset; | |
4555 | dev_priv->seqno_page = kmap(obj_priv->pages[0]); | |
4556 | if (dev_priv->seqno_page == NULL) | |
4557 | goto err_unpin; | |
4558 | ||
4559 | dev_priv->seqno_obj = obj; | |
4560 | memset(dev_priv->seqno_page, 0, PAGE_SIZE); | |
4561 | ||
4562 | return 0; | |
4563 | ||
4564 | err_unpin: | |
4565 | i915_gem_object_unpin(obj); | |
4566 | err_unref: | |
4567 | drm_gem_object_unreference(obj); | |
4568 | err: | |
4569 | return ret; | |
4570 | } | |
4571 | ||
8187a2b7 ZN |
4572 | |
4573 | static void | |
e552eb70 JB |
4574 | i915_gem_cleanup_pipe_control(struct drm_device *dev) |
4575 | { | |
4576 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4577 | struct drm_gem_object *obj; | |
4578 | struct drm_i915_gem_object *obj_priv; | |
4579 | ||
4580 | obj = dev_priv->seqno_obj; | |
4581 | obj_priv = to_intel_bo(obj); | |
4582 | kunmap(obj_priv->pages[0]); | |
4583 | i915_gem_object_unpin(obj); | |
4584 | drm_gem_object_unreference(obj); | |
4585 | dev_priv->seqno_obj = NULL; | |
4586 | ||
4587 | dev_priv->seqno_page = NULL; | |
673a394b EA |
4588 | } |
4589 | ||
8187a2b7 ZN |
4590 | int |
4591 | i915_gem_init_ringbuffer(struct drm_device *dev) | |
4592 | { | |
4593 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4594 | int ret; | |
68f95ba9 | 4595 | |
8187a2b7 ZN |
4596 | if (HAS_PIPE_CONTROL(dev)) { |
4597 | ret = i915_gem_init_pipe_control(dev); | |
4598 | if (ret) | |
4599 | return ret; | |
4600 | } | |
68f95ba9 | 4601 | |
5c1143bb | 4602 | ret = intel_init_render_ring_buffer(dev); |
68f95ba9 CW |
4603 | if (ret) |
4604 | goto cleanup_pipe_control; | |
4605 | ||
4606 | if (HAS_BSD(dev)) { | |
5c1143bb | 4607 | ret = intel_init_bsd_ring_buffer(dev); |
68f95ba9 CW |
4608 | if (ret) |
4609 | goto cleanup_render_ring; | |
d1b851fc | 4610 | } |
68f95ba9 | 4611 | |
549f7365 CW |
4612 | if (HAS_BLT(dev)) { |
4613 | ret = intel_init_blt_ring_buffer(dev); | |
4614 | if (ret) | |
4615 | goto cleanup_bsd_ring; | |
4616 | } | |
4617 | ||
6f392d54 CW |
4618 | dev_priv->next_seqno = 1; |
4619 | ||
68f95ba9 CW |
4620 | return 0; |
4621 | ||
549f7365 | 4622 | cleanup_bsd_ring: |
78501eac | 4623 | intel_cleanup_ring_buffer(&dev_priv->bsd_ring); |
68f95ba9 | 4624 | cleanup_render_ring: |
78501eac | 4625 | intel_cleanup_ring_buffer(&dev_priv->render_ring); |
68f95ba9 CW |
4626 | cleanup_pipe_control: |
4627 | if (HAS_PIPE_CONTROL(dev)) | |
4628 | i915_gem_cleanup_pipe_control(dev); | |
8187a2b7 ZN |
4629 | return ret; |
4630 | } | |
4631 | ||
4632 | void | |
4633 | i915_gem_cleanup_ringbuffer(struct drm_device *dev) | |
4634 | { | |
4635 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4636 | ||
78501eac CW |
4637 | intel_cleanup_ring_buffer(&dev_priv->render_ring); |
4638 | intel_cleanup_ring_buffer(&dev_priv->bsd_ring); | |
4639 | intel_cleanup_ring_buffer(&dev_priv->blt_ring); | |
8187a2b7 ZN |
4640 | if (HAS_PIPE_CONTROL(dev)) |
4641 | i915_gem_cleanup_pipe_control(dev); | |
4642 | } | |
4643 | ||
673a394b EA |
4644 | int |
4645 | i915_gem_entervt_ioctl(struct drm_device *dev, void *data, | |
4646 | struct drm_file *file_priv) | |
4647 | { | |
4648 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4649 | int ret; | |
4650 | ||
79e53945 JB |
4651 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
4652 | return 0; | |
4653 | ||
ba1234d1 | 4654 | if (atomic_read(&dev_priv->mm.wedged)) { |
673a394b | 4655 | DRM_ERROR("Reenabling wedged hardware, good luck\n"); |
ba1234d1 | 4656 | atomic_set(&dev_priv->mm.wedged, 0); |
673a394b EA |
4657 | } |
4658 | ||
673a394b | 4659 | mutex_lock(&dev->struct_mutex); |
9bb2d6f9 EA |
4660 | dev_priv->mm.suspended = 0; |
4661 | ||
4662 | ret = i915_gem_init_ringbuffer(dev); | |
d816f6ac WF |
4663 | if (ret != 0) { |
4664 | mutex_unlock(&dev->struct_mutex); | |
9bb2d6f9 | 4665 | return ret; |
d816f6ac | 4666 | } |
9bb2d6f9 | 4667 | |
69dc4987 | 4668 | BUG_ON(!list_empty(&dev_priv->mm.active_list)); |
852835f3 | 4669 | BUG_ON(!list_empty(&dev_priv->render_ring.active_list)); |
87acb0a5 | 4670 | BUG_ON(!list_empty(&dev_priv->bsd_ring.active_list)); |
549f7365 | 4671 | BUG_ON(!list_empty(&dev_priv->blt_ring.active_list)); |
673a394b EA |
4672 | BUG_ON(!list_empty(&dev_priv->mm.flushing_list)); |
4673 | BUG_ON(!list_empty(&dev_priv->mm.inactive_list)); | |
852835f3 | 4674 | BUG_ON(!list_empty(&dev_priv->render_ring.request_list)); |
87acb0a5 | 4675 | BUG_ON(!list_empty(&dev_priv->bsd_ring.request_list)); |
549f7365 | 4676 | BUG_ON(!list_empty(&dev_priv->blt_ring.request_list)); |
673a394b | 4677 | mutex_unlock(&dev->struct_mutex); |
dbb19d30 | 4678 | |
5f35308b CW |
4679 | ret = drm_irq_install(dev); |
4680 | if (ret) | |
4681 | goto cleanup_ringbuffer; | |
dbb19d30 | 4682 | |
673a394b | 4683 | return 0; |
5f35308b CW |
4684 | |
4685 | cleanup_ringbuffer: | |
4686 | mutex_lock(&dev->struct_mutex); | |
4687 | i915_gem_cleanup_ringbuffer(dev); | |
4688 | dev_priv->mm.suspended = 1; | |
4689 | mutex_unlock(&dev->struct_mutex); | |
4690 | ||
4691 | return ret; | |
673a394b EA |
4692 | } |
4693 | ||
4694 | int | |
4695 | i915_gem_leavevt_ioctl(struct drm_device *dev, void *data, | |
4696 | struct drm_file *file_priv) | |
4697 | { | |
79e53945 JB |
4698 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
4699 | return 0; | |
4700 | ||
dbb19d30 | 4701 | drm_irq_uninstall(dev); |
e6890f6f | 4702 | return i915_gem_idle(dev); |
673a394b EA |
4703 | } |
4704 | ||
4705 | void | |
4706 | i915_gem_lastclose(struct drm_device *dev) | |
4707 | { | |
4708 | int ret; | |
673a394b | 4709 | |
e806b495 EA |
4710 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
4711 | return; | |
4712 | ||
6dbe2772 KP |
4713 | ret = i915_gem_idle(dev); |
4714 | if (ret) | |
4715 | DRM_ERROR("failed to idle hardware: %d\n", ret); | |
673a394b EA |
4716 | } |
4717 | ||
64193406 CW |
4718 | static void |
4719 | init_ring_lists(struct intel_ring_buffer *ring) | |
4720 | { | |
4721 | INIT_LIST_HEAD(&ring->active_list); | |
4722 | INIT_LIST_HEAD(&ring->request_list); | |
4723 | INIT_LIST_HEAD(&ring->gpu_write_list); | |
4724 | } | |
4725 | ||
673a394b EA |
4726 | void |
4727 | i915_gem_load(struct drm_device *dev) | |
4728 | { | |
b5aa8a0f | 4729 | int i; |
673a394b EA |
4730 | drm_i915_private_t *dev_priv = dev->dev_private; |
4731 | ||
69dc4987 | 4732 | INIT_LIST_HEAD(&dev_priv->mm.active_list); |
673a394b EA |
4733 | INIT_LIST_HEAD(&dev_priv->mm.flushing_list); |
4734 | INIT_LIST_HEAD(&dev_priv->mm.inactive_list); | |
f13d3f73 | 4735 | INIT_LIST_HEAD(&dev_priv->mm.pinned_list); |
a09ba7fa | 4736 | INIT_LIST_HEAD(&dev_priv->mm.fence_list); |
be72615b | 4737 | INIT_LIST_HEAD(&dev_priv->mm.deferred_free_list); |
64193406 CW |
4738 | init_ring_lists(&dev_priv->render_ring); |
4739 | init_ring_lists(&dev_priv->bsd_ring); | |
4740 | init_ring_lists(&dev_priv->blt_ring); | |
007cc8ac DV |
4741 | for (i = 0; i < 16; i++) |
4742 | INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list); | |
673a394b EA |
4743 | INIT_DELAYED_WORK(&dev_priv->mm.retire_work, |
4744 | i915_gem_retire_work_handler); | |
30dbf0c0 | 4745 | init_completion(&dev_priv->error_completion); |
31169714 | 4746 | |
94400120 DA |
4747 | /* On GEN3 we really need to make sure the ARB C3 LP bit is set */ |
4748 | if (IS_GEN3(dev)) { | |
4749 | u32 tmp = I915_READ(MI_ARB_STATE); | |
4750 | if (!(tmp & MI_ARB_C3_LP_WRITE_ENABLE)) { | |
4751 | /* arb state is a masked write, so set bit + bit in mask */ | |
4752 | tmp = MI_ARB_C3_LP_WRITE_ENABLE | (MI_ARB_C3_LP_WRITE_ENABLE << MI_ARB_MASK_SHIFT); | |
4753 | I915_WRITE(MI_ARB_STATE, tmp); | |
4754 | } | |
4755 | } | |
4756 | ||
de151cf6 | 4757 | /* Old X drivers will take 0-2 for front, back, depth buffers */ |
b397c836 EA |
4758 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) |
4759 | dev_priv->fence_reg_start = 3; | |
de151cf6 | 4760 | |
a6c45cf0 | 4761 | if (INTEL_INFO(dev)->gen >= 4 || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) |
de151cf6 JB |
4762 | dev_priv->num_fence_regs = 16; |
4763 | else | |
4764 | dev_priv->num_fence_regs = 8; | |
4765 | ||
b5aa8a0f | 4766 | /* Initialize fence registers to zero */ |
a6c45cf0 CW |
4767 | switch (INTEL_INFO(dev)->gen) { |
4768 | case 6: | |
4769 | for (i = 0; i < 16; i++) | |
4770 | I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + (i * 8), 0); | |
4771 | break; | |
4772 | case 5: | |
4773 | case 4: | |
b5aa8a0f GH |
4774 | for (i = 0; i < 16; i++) |
4775 | I915_WRITE64(FENCE_REG_965_0 + (i * 8), 0); | |
a6c45cf0 CW |
4776 | break; |
4777 | case 3: | |
b5aa8a0f GH |
4778 | if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) |
4779 | for (i = 0; i < 8; i++) | |
4780 | I915_WRITE(FENCE_REG_945_8 + (i * 4), 0); | |
a6c45cf0 CW |
4781 | case 2: |
4782 | for (i = 0; i < 8; i++) | |
4783 | I915_WRITE(FENCE_REG_830_0 + (i * 4), 0); | |
4784 | break; | |
b5aa8a0f | 4785 | } |
673a394b | 4786 | i915_gem_detect_bit_6_swizzle(dev); |
6b95a207 | 4787 | init_waitqueue_head(&dev_priv->pending_flip_queue); |
17250b71 CW |
4788 | |
4789 | dev_priv->mm.inactive_shrinker.shrink = i915_gem_inactive_shrink; | |
4790 | dev_priv->mm.inactive_shrinker.seeks = DEFAULT_SEEKS; | |
4791 | register_shrinker(&dev_priv->mm.inactive_shrinker); | |
673a394b | 4792 | } |
71acb5eb DA |
4793 | |
4794 | /* | |
4795 | * Create a physically contiguous memory object for this object | |
4796 | * e.g. for cursor + overlay regs | |
4797 | */ | |
995b6762 CW |
4798 | static int i915_gem_init_phys_object(struct drm_device *dev, |
4799 | int id, int size, int align) | |
71acb5eb DA |
4800 | { |
4801 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4802 | struct drm_i915_gem_phys_object *phys_obj; | |
4803 | int ret; | |
4804 | ||
4805 | if (dev_priv->mm.phys_objs[id - 1] || !size) | |
4806 | return 0; | |
4807 | ||
9a298b2a | 4808 | phys_obj = kzalloc(sizeof(struct drm_i915_gem_phys_object), GFP_KERNEL); |
71acb5eb DA |
4809 | if (!phys_obj) |
4810 | return -ENOMEM; | |
4811 | ||
4812 | phys_obj->id = id; | |
4813 | ||
6eeefaf3 | 4814 | phys_obj->handle = drm_pci_alloc(dev, size, align); |
71acb5eb DA |
4815 | if (!phys_obj->handle) { |
4816 | ret = -ENOMEM; | |
4817 | goto kfree_obj; | |
4818 | } | |
4819 | #ifdef CONFIG_X86 | |
4820 | set_memory_wc((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE); | |
4821 | #endif | |
4822 | ||
4823 | dev_priv->mm.phys_objs[id - 1] = phys_obj; | |
4824 | ||
4825 | return 0; | |
4826 | kfree_obj: | |
9a298b2a | 4827 | kfree(phys_obj); |
71acb5eb DA |
4828 | return ret; |
4829 | } | |
4830 | ||
995b6762 | 4831 | static void i915_gem_free_phys_object(struct drm_device *dev, int id) |
71acb5eb DA |
4832 | { |
4833 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4834 | struct drm_i915_gem_phys_object *phys_obj; | |
4835 | ||
4836 | if (!dev_priv->mm.phys_objs[id - 1]) | |
4837 | return; | |
4838 | ||
4839 | phys_obj = dev_priv->mm.phys_objs[id - 1]; | |
4840 | if (phys_obj->cur_obj) { | |
4841 | i915_gem_detach_phys_object(dev, phys_obj->cur_obj); | |
4842 | } | |
4843 | ||
4844 | #ifdef CONFIG_X86 | |
4845 | set_memory_wb((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE); | |
4846 | #endif | |
4847 | drm_pci_free(dev, phys_obj->handle); | |
4848 | kfree(phys_obj); | |
4849 | dev_priv->mm.phys_objs[id - 1] = NULL; | |
4850 | } | |
4851 | ||
4852 | void i915_gem_free_all_phys_object(struct drm_device *dev) | |
4853 | { | |
4854 | int i; | |
4855 | ||
260883c8 | 4856 | for (i = I915_GEM_PHYS_CURSOR_0; i <= I915_MAX_PHYS_OBJECT; i++) |
71acb5eb DA |
4857 | i915_gem_free_phys_object(dev, i); |
4858 | } | |
4859 | ||
4860 | void i915_gem_detach_phys_object(struct drm_device *dev, | |
4861 | struct drm_gem_object *obj) | |
4862 | { | |
4863 | struct drm_i915_gem_object *obj_priv; | |
4864 | int i; | |
4865 | int ret; | |
4866 | int page_count; | |
4867 | ||
23010e43 | 4868 | obj_priv = to_intel_bo(obj); |
71acb5eb DA |
4869 | if (!obj_priv->phys_obj) |
4870 | return; | |
4871 | ||
4bdadb97 | 4872 | ret = i915_gem_object_get_pages(obj, 0); |
71acb5eb DA |
4873 | if (ret) |
4874 | goto out; | |
4875 | ||
4876 | page_count = obj->size / PAGE_SIZE; | |
4877 | ||
4878 | for (i = 0; i < page_count; i++) { | |
3e4d3af5 | 4879 | char *dst = kmap_atomic(obj_priv->pages[i]); |
71acb5eb DA |
4880 | char *src = obj_priv->phys_obj->handle->vaddr + (i * PAGE_SIZE); |
4881 | ||
4882 | memcpy(dst, src, PAGE_SIZE); | |
3e4d3af5 | 4883 | kunmap_atomic(dst); |
71acb5eb | 4884 | } |
856fa198 | 4885 | drm_clflush_pages(obj_priv->pages, page_count); |
71acb5eb | 4886 | drm_agp_chipset_flush(dev); |
d78b47b9 CW |
4887 | |
4888 | i915_gem_object_put_pages(obj); | |
71acb5eb DA |
4889 | out: |
4890 | obj_priv->phys_obj->cur_obj = NULL; | |
4891 | obj_priv->phys_obj = NULL; | |
4892 | } | |
4893 | ||
4894 | int | |
4895 | i915_gem_attach_phys_object(struct drm_device *dev, | |
6eeefaf3 CW |
4896 | struct drm_gem_object *obj, |
4897 | int id, | |
4898 | int align) | |
71acb5eb DA |
4899 | { |
4900 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4901 | struct drm_i915_gem_object *obj_priv; | |
4902 | int ret = 0; | |
4903 | int page_count; | |
4904 | int i; | |
4905 | ||
4906 | if (id > I915_MAX_PHYS_OBJECT) | |
4907 | return -EINVAL; | |
4908 | ||
23010e43 | 4909 | obj_priv = to_intel_bo(obj); |
71acb5eb DA |
4910 | |
4911 | if (obj_priv->phys_obj) { | |
4912 | if (obj_priv->phys_obj->id == id) | |
4913 | return 0; | |
4914 | i915_gem_detach_phys_object(dev, obj); | |
4915 | } | |
4916 | ||
71acb5eb DA |
4917 | /* create a new object */ |
4918 | if (!dev_priv->mm.phys_objs[id - 1]) { | |
4919 | ret = i915_gem_init_phys_object(dev, id, | |
6eeefaf3 | 4920 | obj->size, align); |
71acb5eb | 4921 | if (ret) { |
aeb565df | 4922 | DRM_ERROR("failed to init phys object %d size: %zu\n", id, obj->size); |
71acb5eb DA |
4923 | goto out; |
4924 | } | |
4925 | } | |
4926 | ||
4927 | /* bind to the object */ | |
4928 | obj_priv->phys_obj = dev_priv->mm.phys_objs[id - 1]; | |
4929 | obj_priv->phys_obj->cur_obj = obj; | |
4930 | ||
4bdadb97 | 4931 | ret = i915_gem_object_get_pages(obj, 0); |
71acb5eb DA |
4932 | if (ret) { |
4933 | DRM_ERROR("failed to get page list\n"); | |
4934 | goto out; | |
4935 | } | |
4936 | ||
4937 | page_count = obj->size / PAGE_SIZE; | |
4938 | ||
4939 | for (i = 0; i < page_count; i++) { | |
3e4d3af5 | 4940 | char *src = kmap_atomic(obj_priv->pages[i]); |
71acb5eb DA |
4941 | char *dst = obj_priv->phys_obj->handle->vaddr + (i * PAGE_SIZE); |
4942 | ||
4943 | memcpy(dst, src, PAGE_SIZE); | |
3e4d3af5 | 4944 | kunmap_atomic(src); |
71acb5eb DA |
4945 | } |
4946 | ||
d78b47b9 CW |
4947 | i915_gem_object_put_pages(obj); |
4948 | ||
71acb5eb DA |
4949 | return 0; |
4950 | out: | |
4951 | return ret; | |
4952 | } | |
4953 | ||
4954 | static int | |
4955 | i915_gem_phys_pwrite(struct drm_device *dev, struct drm_gem_object *obj, | |
4956 | struct drm_i915_gem_pwrite *args, | |
4957 | struct drm_file *file_priv) | |
4958 | { | |
23010e43 | 4959 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
71acb5eb DA |
4960 | void *obj_addr; |
4961 | int ret; | |
4962 | char __user *user_data; | |
4963 | ||
4964 | user_data = (char __user *) (uintptr_t) args->data_ptr; | |
4965 | obj_addr = obj_priv->phys_obj->handle->vaddr + args->offset; | |
4966 | ||
44d98a61 | 4967 | DRM_DEBUG_DRIVER("obj_addr %p, %lld\n", obj_addr, args->size); |
71acb5eb DA |
4968 | ret = copy_from_user(obj_addr, user_data, args->size); |
4969 | if (ret) | |
4970 | return -EFAULT; | |
4971 | ||
4972 | drm_agp_chipset_flush(dev); | |
4973 | return 0; | |
4974 | } | |
b962442e | 4975 | |
f787a5f5 | 4976 | void i915_gem_release(struct drm_device *dev, struct drm_file *file) |
b962442e | 4977 | { |
f787a5f5 | 4978 | struct drm_i915_file_private *file_priv = file->driver_priv; |
b962442e EA |
4979 | |
4980 | /* Clean up our request list when the client is going away, so that | |
4981 | * later retire_requests won't dereference our soon-to-be-gone | |
4982 | * file_priv. | |
4983 | */ | |
1c25595f | 4984 | spin_lock(&file_priv->mm.lock); |
f787a5f5 CW |
4985 | while (!list_empty(&file_priv->mm.request_list)) { |
4986 | struct drm_i915_gem_request *request; | |
4987 | ||
4988 | request = list_first_entry(&file_priv->mm.request_list, | |
4989 | struct drm_i915_gem_request, | |
4990 | client_list); | |
4991 | list_del(&request->client_list); | |
4992 | request->file_priv = NULL; | |
4993 | } | |
1c25595f | 4994 | spin_unlock(&file_priv->mm.lock); |
b962442e | 4995 | } |
31169714 | 4996 | |
1637ef41 CW |
4997 | static int |
4998 | i915_gpu_is_active(struct drm_device *dev) | |
4999 | { | |
5000 | drm_i915_private_t *dev_priv = dev->dev_private; | |
5001 | int lists_empty; | |
5002 | ||
1637ef41 | 5003 | lists_empty = list_empty(&dev_priv->mm.flushing_list) && |
17250b71 | 5004 | list_empty(&dev_priv->mm.active_list); |
1637ef41 CW |
5005 | |
5006 | return !lists_empty; | |
5007 | } | |
5008 | ||
31169714 | 5009 | static int |
17250b71 CW |
5010 | i915_gem_inactive_shrink(struct shrinker *shrinker, |
5011 | int nr_to_scan, | |
5012 | gfp_t gfp_mask) | |
31169714 | 5013 | { |
17250b71 CW |
5014 | struct drm_i915_private *dev_priv = |
5015 | container_of(shrinker, | |
5016 | struct drm_i915_private, | |
5017 | mm.inactive_shrinker); | |
5018 | struct drm_device *dev = dev_priv->dev; | |
5019 | struct drm_i915_gem_object *obj, *next; | |
5020 | int cnt; | |
5021 | ||
5022 | if (!mutex_trylock(&dev->struct_mutex)) | |
5023 | return nr_to_scan ? 0 : -1; | |
31169714 CW |
5024 | |
5025 | /* "fast-path" to count number of available objects */ | |
5026 | if (nr_to_scan == 0) { | |
17250b71 CW |
5027 | cnt = 0; |
5028 | list_for_each_entry(obj, | |
5029 | &dev_priv->mm.inactive_list, | |
5030 | mm_list) | |
5031 | cnt++; | |
5032 | mutex_unlock(&dev->struct_mutex); | |
5033 | return cnt / 100 * sysctl_vfs_cache_pressure; | |
31169714 CW |
5034 | } |
5035 | ||
1637ef41 | 5036 | rescan: |
31169714 | 5037 | /* first scan for clean buffers */ |
17250b71 | 5038 | i915_gem_retire_requests(dev); |
31169714 | 5039 | |
17250b71 CW |
5040 | list_for_each_entry_safe(obj, next, |
5041 | &dev_priv->mm.inactive_list, | |
5042 | mm_list) { | |
5043 | if (i915_gem_object_is_purgeable(obj)) { | |
5044 | i915_gem_object_unbind(&obj->base); | |
5045 | if (--nr_to_scan == 0) | |
5046 | break; | |
31169714 | 5047 | } |
31169714 CW |
5048 | } |
5049 | ||
5050 | /* second pass, evict/count anything still on the inactive list */ | |
17250b71 CW |
5051 | cnt = 0; |
5052 | list_for_each_entry_safe(obj, next, | |
5053 | &dev_priv->mm.inactive_list, | |
5054 | mm_list) { | |
5055 | if (nr_to_scan) { | |
5056 | i915_gem_object_unbind(&obj->base); | |
5057 | nr_to_scan--; | |
5058 | } else | |
5059 | cnt++; | |
5060 | } | |
5061 | ||
5062 | if (nr_to_scan && i915_gpu_is_active(dev)) { | |
1637ef41 CW |
5063 | /* |
5064 | * We are desperate for pages, so as a last resort, wait | |
5065 | * for the GPU to finish and discard whatever we can. | |
5066 | * This has a dramatic impact to reduce the number of | |
5067 | * OOM-killer events whilst running the GPU aggressively. | |
5068 | */ | |
17250b71 | 5069 | if (i915_gpu_idle(dev) == 0) |
1637ef41 CW |
5070 | goto rescan; |
5071 | } | |
17250b71 CW |
5072 | mutex_unlock(&dev->struct_mutex); |
5073 | return cnt / 100 * sysctl_vfs_cache_pressure; | |
31169714 | 5074 | } |