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673a394b | 1 | /* |
be6a0376 | 2 | * Copyright © 2008-2015 Intel Corporation |
673a394b EA |
3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | * | |
26 | */ | |
27 | ||
760285e7 | 28 | #include <drm/drmP.h> |
0de23977 | 29 | #include <drm/drm_vma_manager.h> |
760285e7 | 30 | #include <drm/i915_drm.h> |
673a394b | 31 | #include "i915_drv.h" |
c13d87ea | 32 | #include "i915_gem_dmabuf.h" |
eb82289a | 33 | #include "i915_vgpu.h" |
1c5d22f7 | 34 | #include "i915_trace.h" |
652c393a | 35 | #include "intel_drv.h" |
5d723d7a | 36 | #include "intel_frontbuffer.h" |
0ccdacf6 | 37 | #include "intel_mocs.h" |
c13d87ea | 38 | #include <linux/reservation.h> |
5949eac4 | 39 | #include <linux/shmem_fs.h> |
5a0e3ad6 | 40 | #include <linux/slab.h> |
673a394b | 41 | #include <linux/swap.h> |
79e53945 | 42 | #include <linux/pci.h> |
1286ff73 | 43 | #include <linux/dma-buf.h> |
673a394b | 44 | |
05394f39 | 45 | static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj); |
e62b59e4 | 46 | static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj); |
61050808 | 47 | |
c76ce038 CW |
48 | static bool cpu_cache_is_coherent(struct drm_device *dev, |
49 | enum i915_cache_level level) | |
50 | { | |
51 | return HAS_LLC(dev) || level != I915_CACHE_NONE; | |
52 | } | |
53 | ||
2c22569b CW |
54 | static bool cpu_write_needs_clflush(struct drm_i915_gem_object *obj) |
55 | { | |
b50a5371 AS |
56 | if (obj->base.write_domain == I915_GEM_DOMAIN_CPU) |
57 | return false; | |
58 | ||
2c22569b CW |
59 | if (!cpu_cache_is_coherent(obj->base.dev, obj->cache_level)) |
60 | return true; | |
61 | ||
62 | return obj->pin_display; | |
63 | } | |
64 | ||
4f1959ee AS |
65 | static int |
66 | insert_mappable_node(struct drm_i915_private *i915, | |
67 | struct drm_mm_node *node, u32 size) | |
68 | { | |
69 | memset(node, 0, sizeof(*node)); | |
70 | return drm_mm_insert_node_in_range_generic(&i915->ggtt.base.mm, node, | |
71 | size, 0, 0, 0, | |
72 | i915->ggtt.mappable_end, | |
73 | DRM_MM_SEARCH_DEFAULT, | |
74 | DRM_MM_CREATE_DEFAULT); | |
75 | } | |
76 | ||
77 | static void | |
78 | remove_mappable_node(struct drm_mm_node *node) | |
79 | { | |
80 | drm_mm_remove_node(node); | |
81 | } | |
82 | ||
73aa808f CW |
83 | /* some bookkeeping */ |
84 | static void i915_gem_info_add_obj(struct drm_i915_private *dev_priv, | |
85 | size_t size) | |
86 | { | |
c20e8355 | 87 | spin_lock(&dev_priv->mm.object_stat_lock); |
73aa808f CW |
88 | dev_priv->mm.object_count++; |
89 | dev_priv->mm.object_memory += size; | |
c20e8355 | 90 | spin_unlock(&dev_priv->mm.object_stat_lock); |
73aa808f CW |
91 | } |
92 | ||
93 | static void i915_gem_info_remove_obj(struct drm_i915_private *dev_priv, | |
94 | size_t size) | |
95 | { | |
c20e8355 | 96 | spin_lock(&dev_priv->mm.object_stat_lock); |
73aa808f CW |
97 | dev_priv->mm.object_count--; |
98 | dev_priv->mm.object_memory -= size; | |
c20e8355 | 99 | spin_unlock(&dev_priv->mm.object_stat_lock); |
73aa808f CW |
100 | } |
101 | ||
21dd3734 | 102 | static int |
33196ded | 103 | i915_gem_wait_for_error(struct i915_gpu_error *error) |
30dbf0c0 | 104 | { |
30dbf0c0 CW |
105 | int ret; |
106 | ||
d98c52cf | 107 | if (!i915_reset_in_progress(error)) |
30dbf0c0 CW |
108 | return 0; |
109 | ||
0a6759c6 DV |
110 | /* |
111 | * Only wait 10 seconds for the gpu reset to complete to avoid hanging | |
112 | * userspace. If it takes that long something really bad is going on and | |
113 | * we should simply try to bail out and fail as gracefully as possible. | |
114 | */ | |
1f83fee0 | 115 | ret = wait_event_interruptible_timeout(error->reset_queue, |
d98c52cf | 116 | !i915_reset_in_progress(error), |
1f83fee0 | 117 | 10*HZ); |
0a6759c6 DV |
118 | if (ret == 0) { |
119 | DRM_ERROR("Timed out waiting for the gpu reset to complete\n"); | |
120 | return -EIO; | |
121 | } else if (ret < 0) { | |
30dbf0c0 | 122 | return ret; |
d98c52cf CW |
123 | } else { |
124 | return 0; | |
0a6759c6 | 125 | } |
30dbf0c0 CW |
126 | } |
127 | ||
54cf91dc | 128 | int i915_mutex_lock_interruptible(struct drm_device *dev) |
76c1dec1 | 129 | { |
fac5e23e | 130 | struct drm_i915_private *dev_priv = to_i915(dev); |
76c1dec1 CW |
131 | int ret; |
132 | ||
33196ded | 133 | ret = i915_gem_wait_for_error(&dev_priv->gpu_error); |
76c1dec1 CW |
134 | if (ret) |
135 | return ret; | |
136 | ||
137 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
138 | if (ret) | |
139 | return ret; | |
140 | ||
76c1dec1 CW |
141 | return 0; |
142 | } | |
30dbf0c0 | 143 | |
5a125c3c EA |
144 | int |
145 | i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 146 | struct drm_file *file) |
5a125c3c | 147 | { |
72e96d64 | 148 | struct drm_i915_private *dev_priv = to_i915(dev); |
62106b4f | 149 | struct i915_ggtt *ggtt = &dev_priv->ggtt; |
72e96d64 | 150 | struct drm_i915_gem_get_aperture *args = data; |
ca1543be | 151 | struct i915_vma *vma; |
6299f992 | 152 | size_t pinned; |
5a125c3c | 153 | |
6299f992 | 154 | pinned = 0; |
73aa808f | 155 | mutex_lock(&dev->struct_mutex); |
1c7f4bca | 156 | list_for_each_entry(vma, &ggtt->base.active_list, vm_link) |
20dfbde4 | 157 | if (i915_vma_is_pinned(vma)) |
ca1543be | 158 | pinned += vma->node.size; |
1c7f4bca | 159 | list_for_each_entry(vma, &ggtt->base.inactive_list, vm_link) |
20dfbde4 | 160 | if (i915_vma_is_pinned(vma)) |
ca1543be | 161 | pinned += vma->node.size; |
73aa808f | 162 | mutex_unlock(&dev->struct_mutex); |
5a125c3c | 163 | |
72e96d64 | 164 | args->aper_size = ggtt->base.total; |
0206e353 | 165 | args->aper_available_size = args->aper_size - pinned; |
6299f992 | 166 | |
5a125c3c EA |
167 | return 0; |
168 | } | |
169 | ||
6a2c4232 CW |
170 | static int |
171 | i915_gem_object_get_pages_phys(struct drm_i915_gem_object *obj) | |
00731155 | 172 | { |
6a2c4232 CW |
173 | struct address_space *mapping = file_inode(obj->base.filp)->i_mapping; |
174 | char *vaddr = obj->phys_handle->vaddr; | |
175 | struct sg_table *st; | |
176 | struct scatterlist *sg; | |
177 | int i; | |
00731155 | 178 | |
6a2c4232 CW |
179 | if (WARN_ON(i915_gem_object_needs_bit17_swizzle(obj))) |
180 | return -EINVAL; | |
181 | ||
182 | for (i = 0; i < obj->base.size / PAGE_SIZE; i++) { | |
183 | struct page *page; | |
184 | char *src; | |
185 | ||
186 | page = shmem_read_mapping_page(mapping, i); | |
187 | if (IS_ERR(page)) | |
188 | return PTR_ERR(page); | |
189 | ||
190 | src = kmap_atomic(page); | |
191 | memcpy(vaddr, src, PAGE_SIZE); | |
192 | drm_clflush_virt_range(vaddr, PAGE_SIZE); | |
193 | kunmap_atomic(src); | |
194 | ||
09cbfeaf | 195 | put_page(page); |
6a2c4232 CW |
196 | vaddr += PAGE_SIZE; |
197 | } | |
198 | ||
c033666a | 199 | i915_gem_chipset_flush(to_i915(obj->base.dev)); |
6a2c4232 CW |
200 | |
201 | st = kmalloc(sizeof(*st), GFP_KERNEL); | |
202 | if (st == NULL) | |
203 | return -ENOMEM; | |
204 | ||
205 | if (sg_alloc_table(st, 1, GFP_KERNEL)) { | |
206 | kfree(st); | |
207 | return -ENOMEM; | |
208 | } | |
209 | ||
210 | sg = st->sgl; | |
211 | sg->offset = 0; | |
212 | sg->length = obj->base.size; | |
00731155 | 213 | |
6a2c4232 CW |
214 | sg_dma_address(sg) = obj->phys_handle->busaddr; |
215 | sg_dma_len(sg) = obj->base.size; | |
216 | ||
217 | obj->pages = st; | |
6a2c4232 CW |
218 | return 0; |
219 | } | |
220 | ||
221 | static void | |
222 | i915_gem_object_put_pages_phys(struct drm_i915_gem_object *obj) | |
223 | { | |
224 | int ret; | |
225 | ||
226 | BUG_ON(obj->madv == __I915_MADV_PURGED); | |
00731155 | 227 | |
6a2c4232 | 228 | ret = i915_gem_object_set_to_cpu_domain(obj, true); |
f4457ae7 | 229 | if (WARN_ON(ret)) { |
6a2c4232 CW |
230 | /* In the event of a disaster, abandon all caches and |
231 | * hope for the best. | |
232 | */ | |
6a2c4232 CW |
233 | obj->base.read_domains = obj->base.write_domain = I915_GEM_DOMAIN_CPU; |
234 | } | |
235 | ||
236 | if (obj->madv == I915_MADV_DONTNEED) | |
237 | obj->dirty = 0; | |
238 | ||
239 | if (obj->dirty) { | |
00731155 | 240 | struct address_space *mapping = file_inode(obj->base.filp)->i_mapping; |
6a2c4232 | 241 | char *vaddr = obj->phys_handle->vaddr; |
00731155 CW |
242 | int i; |
243 | ||
244 | for (i = 0; i < obj->base.size / PAGE_SIZE; i++) { | |
6a2c4232 CW |
245 | struct page *page; |
246 | char *dst; | |
247 | ||
248 | page = shmem_read_mapping_page(mapping, i); | |
249 | if (IS_ERR(page)) | |
250 | continue; | |
251 | ||
252 | dst = kmap_atomic(page); | |
253 | drm_clflush_virt_range(vaddr, PAGE_SIZE); | |
254 | memcpy(dst, vaddr, PAGE_SIZE); | |
255 | kunmap_atomic(dst); | |
256 | ||
257 | set_page_dirty(page); | |
258 | if (obj->madv == I915_MADV_WILLNEED) | |
00731155 | 259 | mark_page_accessed(page); |
09cbfeaf | 260 | put_page(page); |
00731155 CW |
261 | vaddr += PAGE_SIZE; |
262 | } | |
6a2c4232 | 263 | obj->dirty = 0; |
00731155 CW |
264 | } |
265 | ||
6a2c4232 CW |
266 | sg_free_table(obj->pages); |
267 | kfree(obj->pages); | |
6a2c4232 CW |
268 | } |
269 | ||
270 | static void | |
271 | i915_gem_object_release_phys(struct drm_i915_gem_object *obj) | |
272 | { | |
273 | drm_pci_free(obj->base.dev, obj->phys_handle); | |
274 | } | |
275 | ||
276 | static const struct drm_i915_gem_object_ops i915_gem_phys_ops = { | |
277 | .get_pages = i915_gem_object_get_pages_phys, | |
278 | .put_pages = i915_gem_object_put_pages_phys, | |
279 | .release = i915_gem_object_release_phys, | |
280 | }; | |
281 | ||
aa653a68 CW |
282 | int |
283 | i915_gem_object_unbind(struct drm_i915_gem_object *obj) | |
284 | { | |
285 | struct i915_vma *vma; | |
286 | LIST_HEAD(still_in_list); | |
287 | int ret; | |
288 | ||
289 | /* The vma will only be freed if it is marked as closed, and if we wait | |
290 | * upon rendering to the vma, we may unbind anything in the list. | |
291 | */ | |
292 | while ((vma = list_first_entry_or_null(&obj->vma_list, | |
293 | struct i915_vma, | |
294 | obj_link))) { | |
295 | list_move_tail(&vma->obj_link, &still_in_list); | |
296 | ret = i915_vma_unbind(vma); | |
297 | if (ret) | |
298 | break; | |
299 | } | |
300 | list_splice(&still_in_list, &obj->vma_list); | |
301 | ||
302 | return ret; | |
303 | } | |
304 | ||
00e60f26 CW |
305 | /** |
306 | * Ensures that all rendering to the object has completed and the object is | |
307 | * safe to unbind from the GTT or access from the CPU. | |
308 | * @obj: i915 gem object | |
309 | * @readonly: waiting for just read access or read-write access | |
310 | */ | |
311 | int | |
312 | i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj, | |
313 | bool readonly) | |
314 | { | |
315 | struct reservation_object *resv; | |
316 | struct i915_gem_active *active; | |
317 | unsigned long active_mask; | |
318 | int idx; | |
319 | ||
320 | lockdep_assert_held(&obj->base.dev->struct_mutex); | |
321 | ||
322 | if (!readonly) { | |
323 | active = obj->last_read; | |
324 | active_mask = i915_gem_object_get_active(obj); | |
325 | } else { | |
326 | active_mask = 1; | |
327 | active = &obj->last_write; | |
328 | } | |
329 | ||
330 | for_each_active(active_mask, idx) { | |
331 | int ret; | |
332 | ||
333 | ret = i915_gem_active_wait(&active[idx], | |
334 | &obj->base.dev->struct_mutex); | |
335 | if (ret) | |
336 | return ret; | |
337 | } | |
338 | ||
339 | resv = i915_gem_object_get_dmabuf_resv(obj); | |
340 | if (resv) { | |
341 | long err; | |
342 | ||
343 | err = reservation_object_wait_timeout_rcu(resv, !readonly, true, | |
344 | MAX_SCHEDULE_TIMEOUT); | |
345 | if (err < 0) | |
346 | return err; | |
347 | } | |
348 | ||
349 | return 0; | |
350 | } | |
351 | ||
b8f9096d CW |
352 | /* A nonblocking variant of the above wait. Must be called prior to |
353 | * acquiring the mutex for the object, as the object state may change | |
354 | * during this call. A reference must be held by the caller for the object. | |
00e60f26 CW |
355 | */ |
356 | static __must_check int | |
b8f9096d CW |
357 | __unsafe_wait_rendering(struct drm_i915_gem_object *obj, |
358 | struct intel_rps_client *rps, | |
359 | bool readonly) | |
00e60f26 | 360 | { |
00e60f26 CW |
361 | struct i915_gem_active *active; |
362 | unsigned long active_mask; | |
b8f9096d | 363 | int idx; |
00e60f26 | 364 | |
b8f9096d | 365 | active_mask = __I915_BO_ACTIVE(obj); |
00e60f26 CW |
366 | if (!active_mask) |
367 | return 0; | |
368 | ||
369 | if (!readonly) { | |
370 | active = obj->last_read; | |
371 | } else { | |
372 | active_mask = 1; | |
373 | active = &obj->last_write; | |
374 | } | |
375 | ||
b8f9096d CW |
376 | for_each_active(active_mask, idx) { |
377 | int ret; | |
00e60f26 | 378 | |
b8f9096d CW |
379 | ret = i915_gem_active_wait_unlocked(&active[idx], |
380 | true, NULL, rps); | |
381 | if (ret) | |
382 | return ret; | |
00e60f26 CW |
383 | } |
384 | ||
b8f9096d | 385 | return 0; |
00e60f26 CW |
386 | } |
387 | ||
388 | static struct intel_rps_client *to_rps_client(struct drm_file *file) | |
389 | { | |
390 | struct drm_i915_file_private *fpriv = file->driver_priv; | |
391 | ||
392 | return &fpriv->rps; | |
393 | } | |
394 | ||
00731155 CW |
395 | int |
396 | i915_gem_object_attach_phys(struct drm_i915_gem_object *obj, | |
397 | int align) | |
398 | { | |
399 | drm_dma_handle_t *phys; | |
6a2c4232 | 400 | int ret; |
00731155 CW |
401 | |
402 | if (obj->phys_handle) { | |
403 | if ((unsigned long)obj->phys_handle->vaddr & (align -1)) | |
404 | return -EBUSY; | |
405 | ||
406 | return 0; | |
407 | } | |
408 | ||
409 | if (obj->madv != I915_MADV_WILLNEED) | |
410 | return -EFAULT; | |
411 | ||
412 | if (obj->base.filp == NULL) | |
413 | return -EINVAL; | |
414 | ||
4717ca9e CW |
415 | ret = i915_gem_object_unbind(obj); |
416 | if (ret) | |
417 | return ret; | |
418 | ||
419 | ret = i915_gem_object_put_pages(obj); | |
6a2c4232 CW |
420 | if (ret) |
421 | return ret; | |
422 | ||
00731155 CW |
423 | /* create a new object */ |
424 | phys = drm_pci_alloc(obj->base.dev, obj->base.size, align); | |
425 | if (!phys) | |
426 | return -ENOMEM; | |
427 | ||
00731155 | 428 | obj->phys_handle = phys; |
6a2c4232 CW |
429 | obj->ops = &i915_gem_phys_ops; |
430 | ||
431 | return i915_gem_object_get_pages(obj); | |
00731155 CW |
432 | } |
433 | ||
434 | static int | |
435 | i915_gem_phys_pwrite(struct drm_i915_gem_object *obj, | |
436 | struct drm_i915_gem_pwrite *args, | |
437 | struct drm_file *file_priv) | |
438 | { | |
439 | struct drm_device *dev = obj->base.dev; | |
440 | void *vaddr = obj->phys_handle->vaddr + args->offset; | |
3ed605bc | 441 | char __user *user_data = u64_to_user_ptr(args->data_ptr); |
063e4e6b | 442 | int ret = 0; |
6a2c4232 CW |
443 | |
444 | /* We manually control the domain here and pretend that it | |
445 | * remains coherent i.e. in the GTT domain, like shmem_pwrite. | |
446 | */ | |
447 | ret = i915_gem_object_wait_rendering(obj, false); | |
448 | if (ret) | |
449 | return ret; | |
00731155 | 450 | |
77a0d1ca | 451 | intel_fb_obj_invalidate(obj, ORIGIN_CPU); |
00731155 CW |
452 | if (__copy_from_user_inatomic_nocache(vaddr, user_data, args->size)) { |
453 | unsigned long unwritten; | |
454 | ||
455 | /* The physical object once assigned is fixed for the lifetime | |
456 | * of the obj, so we can safely drop the lock and continue | |
457 | * to access vaddr. | |
458 | */ | |
459 | mutex_unlock(&dev->struct_mutex); | |
460 | unwritten = copy_from_user(vaddr, user_data, args->size); | |
461 | mutex_lock(&dev->struct_mutex); | |
063e4e6b PZ |
462 | if (unwritten) { |
463 | ret = -EFAULT; | |
464 | goto out; | |
465 | } | |
00731155 CW |
466 | } |
467 | ||
6a2c4232 | 468 | drm_clflush_virt_range(vaddr, args->size); |
c033666a | 469 | i915_gem_chipset_flush(to_i915(dev)); |
063e4e6b PZ |
470 | |
471 | out: | |
de152b62 | 472 | intel_fb_obj_flush(obj, false, ORIGIN_CPU); |
063e4e6b | 473 | return ret; |
00731155 CW |
474 | } |
475 | ||
42dcedd4 CW |
476 | void *i915_gem_object_alloc(struct drm_device *dev) |
477 | { | |
fac5e23e | 478 | struct drm_i915_private *dev_priv = to_i915(dev); |
efab6d8d | 479 | return kmem_cache_zalloc(dev_priv->objects, GFP_KERNEL); |
42dcedd4 CW |
480 | } |
481 | ||
482 | void i915_gem_object_free(struct drm_i915_gem_object *obj) | |
483 | { | |
fac5e23e | 484 | struct drm_i915_private *dev_priv = to_i915(obj->base.dev); |
efab6d8d | 485 | kmem_cache_free(dev_priv->objects, obj); |
42dcedd4 CW |
486 | } |
487 | ||
ff72145b DA |
488 | static int |
489 | i915_gem_create(struct drm_file *file, | |
490 | struct drm_device *dev, | |
491 | uint64_t size, | |
492 | uint32_t *handle_p) | |
673a394b | 493 | { |
05394f39 | 494 | struct drm_i915_gem_object *obj; |
a1a2d1d3 PP |
495 | int ret; |
496 | u32 handle; | |
673a394b | 497 | |
ff72145b | 498 | size = roundup(size, PAGE_SIZE); |
8ffc0246 CW |
499 | if (size == 0) |
500 | return -EINVAL; | |
673a394b EA |
501 | |
502 | /* Allocate the new object */ | |
d37cd8a8 | 503 | obj = i915_gem_object_create(dev, size); |
fe3db79b CW |
504 | if (IS_ERR(obj)) |
505 | return PTR_ERR(obj); | |
673a394b | 506 | |
05394f39 | 507 | ret = drm_gem_handle_create(file, &obj->base, &handle); |
202f2fef | 508 | /* drop reference from allocate - handle holds it now */ |
34911fd3 | 509 | i915_gem_object_put_unlocked(obj); |
d861e338 DV |
510 | if (ret) |
511 | return ret; | |
202f2fef | 512 | |
ff72145b | 513 | *handle_p = handle; |
673a394b EA |
514 | return 0; |
515 | } | |
516 | ||
ff72145b DA |
517 | int |
518 | i915_gem_dumb_create(struct drm_file *file, | |
519 | struct drm_device *dev, | |
520 | struct drm_mode_create_dumb *args) | |
521 | { | |
522 | /* have to work out size/pitch and return them */ | |
de45eaf7 | 523 | args->pitch = ALIGN(args->width * DIV_ROUND_UP(args->bpp, 8), 64); |
ff72145b DA |
524 | args->size = args->pitch * args->height; |
525 | return i915_gem_create(file, dev, | |
da6b51d0 | 526 | args->size, &args->handle); |
ff72145b DA |
527 | } |
528 | ||
ff72145b DA |
529 | /** |
530 | * Creates a new mm object and returns a handle to it. | |
14bb2c11 TU |
531 | * @dev: drm device pointer |
532 | * @data: ioctl data blob | |
533 | * @file: drm file pointer | |
ff72145b DA |
534 | */ |
535 | int | |
536 | i915_gem_create_ioctl(struct drm_device *dev, void *data, | |
537 | struct drm_file *file) | |
538 | { | |
539 | struct drm_i915_gem_create *args = data; | |
63ed2cb2 | 540 | |
ff72145b | 541 | return i915_gem_create(file, dev, |
da6b51d0 | 542 | args->size, &args->handle); |
ff72145b DA |
543 | } |
544 | ||
8461d226 DV |
545 | static inline int |
546 | __copy_to_user_swizzled(char __user *cpu_vaddr, | |
547 | const char *gpu_vaddr, int gpu_offset, | |
548 | int length) | |
549 | { | |
550 | int ret, cpu_offset = 0; | |
551 | ||
552 | while (length > 0) { | |
553 | int cacheline_end = ALIGN(gpu_offset + 1, 64); | |
554 | int this_length = min(cacheline_end - gpu_offset, length); | |
555 | int swizzled_gpu_offset = gpu_offset ^ 64; | |
556 | ||
557 | ret = __copy_to_user(cpu_vaddr + cpu_offset, | |
558 | gpu_vaddr + swizzled_gpu_offset, | |
559 | this_length); | |
560 | if (ret) | |
561 | return ret + length; | |
562 | ||
563 | cpu_offset += this_length; | |
564 | gpu_offset += this_length; | |
565 | length -= this_length; | |
566 | } | |
567 | ||
568 | return 0; | |
569 | } | |
570 | ||
8c59967c | 571 | static inline int |
4f0c7cfb BW |
572 | __copy_from_user_swizzled(char *gpu_vaddr, int gpu_offset, |
573 | const char __user *cpu_vaddr, | |
8c59967c DV |
574 | int length) |
575 | { | |
576 | int ret, cpu_offset = 0; | |
577 | ||
578 | while (length > 0) { | |
579 | int cacheline_end = ALIGN(gpu_offset + 1, 64); | |
580 | int this_length = min(cacheline_end - gpu_offset, length); | |
581 | int swizzled_gpu_offset = gpu_offset ^ 64; | |
582 | ||
583 | ret = __copy_from_user(gpu_vaddr + swizzled_gpu_offset, | |
584 | cpu_vaddr + cpu_offset, | |
585 | this_length); | |
586 | if (ret) | |
587 | return ret + length; | |
588 | ||
589 | cpu_offset += this_length; | |
590 | gpu_offset += this_length; | |
591 | length -= this_length; | |
592 | } | |
593 | ||
594 | return 0; | |
595 | } | |
596 | ||
4c914c0c BV |
597 | /* |
598 | * Pins the specified object's pages and synchronizes the object with | |
599 | * GPU accesses. Sets needs_clflush to non-zero if the caller should | |
600 | * flush the object from the CPU cache. | |
601 | */ | |
602 | int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj, | |
603 | int *needs_clflush) | |
604 | { | |
605 | int ret; | |
606 | ||
607 | *needs_clflush = 0; | |
608 | ||
b9bcd14a | 609 | if (WARN_ON(!i915_gem_object_has_struct_page(obj))) |
4c914c0c BV |
610 | return -EINVAL; |
611 | ||
c13d87ea CW |
612 | ret = i915_gem_object_wait_rendering(obj, true); |
613 | if (ret) | |
614 | return ret; | |
615 | ||
4c914c0c BV |
616 | if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU)) { |
617 | /* If we're not in the cpu read domain, set ourself into the gtt | |
618 | * read domain and manually flush cachelines (if required). This | |
619 | * optimizes for the case when the gpu will dirty the data | |
620 | * anyway again before the next pread happens. */ | |
621 | *needs_clflush = !cpu_cache_is_coherent(obj->base.dev, | |
622 | obj->cache_level); | |
4c914c0c BV |
623 | } |
624 | ||
625 | ret = i915_gem_object_get_pages(obj); | |
626 | if (ret) | |
627 | return ret; | |
628 | ||
629 | i915_gem_object_pin_pages(obj); | |
630 | ||
631 | return ret; | |
632 | } | |
633 | ||
d174bd64 DV |
634 | /* Per-page copy function for the shmem pread fastpath. |
635 | * Flushes invalid cachelines before reading the target if | |
636 | * needs_clflush is set. */ | |
eb01459f | 637 | static int |
d174bd64 DV |
638 | shmem_pread_fast(struct page *page, int shmem_page_offset, int page_length, |
639 | char __user *user_data, | |
640 | bool page_do_bit17_swizzling, bool needs_clflush) | |
641 | { | |
642 | char *vaddr; | |
643 | int ret; | |
644 | ||
e7e58eb5 | 645 | if (unlikely(page_do_bit17_swizzling)) |
d174bd64 DV |
646 | return -EINVAL; |
647 | ||
648 | vaddr = kmap_atomic(page); | |
649 | if (needs_clflush) | |
650 | drm_clflush_virt_range(vaddr + shmem_page_offset, | |
651 | page_length); | |
652 | ret = __copy_to_user_inatomic(user_data, | |
653 | vaddr + shmem_page_offset, | |
654 | page_length); | |
655 | kunmap_atomic(vaddr); | |
656 | ||
f60d7f0c | 657 | return ret ? -EFAULT : 0; |
d174bd64 DV |
658 | } |
659 | ||
23c18c71 DV |
660 | static void |
661 | shmem_clflush_swizzled_range(char *addr, unsigned long length, | |
662 | bool swizzled) | |
663 | { | |
e7e58eb5 | 664 | if (unlikely(swizzled)) { |
23c18c71 DV |
665 | unsigned long start = (unsigned long) addr; |
666 | unsigned long end = (unsigned long) addr + length; | |
667 | ||
668 | /* For swizzling simply ensure that we always flush both | |
669 | * channels. Lame, but simple and it works. Swizzled | |
670 | * pwrite/pread is far from a hotpath - current userspace | |
671 | * doesn't use it at all. */ | |
672 | start = round_down(start, 128); | |
673 | end = round_up(end, 128); | |
674 | ||
675 | drm_clflush_virt_range((void *)start, end - start); | |
676 | } else { | |
677 | drm_clflush_virt_range(addr, length); | |
678 | } | |
679 | ||
680 | } | |
681 | ||
d174bd64 DV |
682 | /* Only difference to the fast-path function is that this can handle bit17 |
683 | * and uses non-atomic copy and kmap functions. */ | |
684 | static int | |
685 | shmem_pread_slow(struct page *page, int shmem_page_offset, int page_length, | |
686 | char __user *user_data, | |
687 | bool page_do_bit17_swizzling, bool needs_clflush) | |
688 | { | |
689 | char *vaddr; | |
690 | int ret; | |
691 | ||
692 | vaddr = kmap(page); | |
693 | if (needs_clflush) | |
23c18c71 DV |
694 | shmem_clflush_swizzled_range(vaddr + shmem_page_offset, |
695 | page_length, | |
696 | page_do_bit17_swizzling); | |
d174bd64 DV |
697 | |
698 | if (page_do_bit17_swizzling) | |
699 | ret = __copy_to_user_swizzled(user_data, | |
700 | vaddr, shmem_page_offset, | |
701 | page_length); | |
702 | else | |
703 | ret = __copy_to_user(user_data, | |
704 | vaddr + shmem_page_offset, | |
705 | page_length); | |
706 | kunmap(page); | |
707 | ||
f60d7f0c | 708 | return ret ? - EFAULT : 0; |
d174bd64 DV |
709 | } |
710 | ||
b50a5371 AS |
711 | static inline unsigned long |
712 | slow_user_access(struct io_mapping *mapping, | |
713 | uint64_t page_base, int page_offset, | |
714 | char __user *user_data, | |
715 | unsigned long length, bool pwrite) | |
716 | { | |
717 | void __iomem *ioaddr; | |
718 | void *vaddr; | |
719 | uint64_t unwritten; | |
720 | ||
721 | ioaddr = io_mapping_map_wc(mapping, page_base, PAGE_SIZE); | |
722 | /* We can use the cpu mem copy function because this is X86. */ | |
723 | vaddr = (void __force *)ioaddr + page_offset; | |
724 | if (pwrite) | |
725 | unwritten = __copy_from_user(vaddr, user_data, length); | |
726 | else | |
727 | unwritten = __copy_to_user(user_data, vaddr, length); | |
728 | ||
729 | io_mapping_unmap(ioaddr); | |
730 | return unwritten; | |
731 | } | |
732 | ||
733 | static int | |
734 | i915_gem_gtt_pread(struct drm_device *dev, | |
735 | struct drm_i915_gem_object *obj, uint64_t size, | |
736 | uint64_t data_offset, uint64_t data_ptr) | |
737 | { | |
fac5e23e | 738 | struct drm_i915_private *dev_priv = to_i915(dev); |
b50a5371 AS |
739 | struct i915_ggtt *ggtt = &dev_priv->ggtt; |
740 | struct drm_mm_node node; | |
741 | char __user *user_data; | |
742 | uint64_t remain; | |
743 | uint64_t offset; | |
744 | int ret; | |
745 | ||
de895082 | 746 | ret = i915_gem_object_ggtt_pin(obj, NULL, 0, 0, PIN_MAPPABLE); |
b50a5371 AS |
747 | if (ret) { |
748 | ret = insert_mappable_node(dev_priv, &node, PAGE_SIZE); | |
749 | if (ret) | |
750 | goto out; | |
751 | ||
752 | ret = i915_gem_object_get_pages(obj); | |
753 | if (ret) { | |
754 | remove_mappable_node(&node); | |
755 | goto out; | |
756 | } | |
757 | ||
758 | i915_gem_object_pin_pages(obj); | |
759 | } else { | |
760 | node.start = i915_gem_obj_ggtt_offset(obj); | |
761 | node.allocated = false; | |
762 | ret = i915_gem_object_put_fence(obj); | |
763 | if (ret) | |
764 | goto out_unpin; | |
765 | } | |
766 | ||
767 | ret = i915_gem_object_set_to_gtt_domain(obj, false); | |
768 | if (ret) | |
769 | goto out_unpin; | |
770 | ||
771 | user_data = u64_to_user_ptr(data_ptr); | |
772 | remain = size; | |
773 | offset = data_offset; | |
774 | ||
775 | mutex_unlock(&dev->struct_mutex); | |
776 | if (likely(!i915.prefault_disable)) { | |
777 | ret = fault_in_multipages_writeable(user_data, remain); | |
778 | if (ret) { | |
779 | mutex_lock(&dev->struct_mutex); | |
780 | goto out_unpin; | |
781 | } | |
782 | } | |
783 | ||
784 | while (remain > 0) { | |
785 | /* Operation in this page | |
786 | * | |
787 | * page_base = page offset within aperture | |
788 | * page_offset = offset within page | |
789 | * page_length = bytes to copy for this page | |
790 | */ | |
791 | u32 page_base = node.start; | |
792 | unsigned page_offset = offset_in_page(offset); | |
793 | unsigned page_length = PAGE_SIZE - page_offset; | |
794 | page_length = remain < page_length ? remain : page_length; | |
795 | if (node.allocated) { | |
796 | wmb(); | |
797 | ggtt->base.insert_page(&ggtt->base, | |
798 | i915_gem_object_get_dma_address(obj, offset >> PAGE_SHIFT), | |
799 | node.start, | |
800 | I915_CACHE_NONE, 0); | |
801 | wmb(); | |
802 | } else { | |
803 | page_base += offset & PAGE_MASK; | |
804 | } | |
805 | /* This is a slow read/write as it tries to read from | |
806 | * and write to user memory which may result into page | |
807 | * faults, and so we cannot perform this under struct_mutex. | |
808 | */ | |
809 | if (slow_user_access(ggtt->mappable, page_base, | |
810 | page_offset, user_data, | |
811 | page_length, false)) { | |
812 | ret = -EFAULT; | |
813 | break; | |
814 | } | |
815 | ||
816 | remain -= page_length; | |
817 | user_data += page_length; | |
818 | offset += page_length; | |
819 | } | |
820 | ||
821 | mutex_lock(&dev->struct_mutex); | |
822 | if (ret == 0 && (obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0) { | |
823 | /* The user has modified the object whilst we tried | |
824 | * reading from it, and we now have no idea what domain | |
825 | * the pages should be in. As we have just been touching | |
826 | * them directly, flush everything back to the GTT | |
827 | * domain. | |
828 | */ | |
829 | ret = i915_gem_object_set_to_gtt_domain(obj, false); | |
830 | } | |
831 | ||
832 | out_unpin: | |
833 | if (node.allocated) { | |
834 | wmb(); | |
835 | ggtt->base.clear_range(&ggtt->base, | |
836 | node.start, node.size, | |
837 | true); | |
838 | i915_gem_object_unpin_pages(obj); | |
839 | remove_mappable_node(&node); | |
840 | } else { | |
841 | i915_gem_object_ggtt_unpin(obj); | |
842 | } | |
843 | out: | |
844 | return ret; | |
845 | } | |
846 | ||
eb01459f | 847 | static int |
dbf7bff0 DV |
848 | i915_gem_shmem_pread(struct drm_device *dev, |
849 | struct drm_i915_gem_object *obj, | |
850 | struct drm_i915_gem_pread *args, | |
851 | struct drm_file *file) | |
eb01459f | 852 | { |
8461d226 | 853 | char __user *user_data; |
eb01459f | 854 | ssize_t remain; |
8461d226 | 855 | loff_t offset; |
eb2c0c81 | 856 | int shmem_page_offset, page_length, ret = 0; |
8461d226 | 857 | int obj_do_bit17_swizzling, page_do_bit17_swizzling; |
96d79b52 | 858 | int prefaulted = 0; |
8489731c | 859 | int needs_clflush = 0; |
67d5a50c | 860 | struct sg_page_iter sg_iter; |
eb01459f | 861 | |
6eae0059 | 862 | if (!i915_gem_object_has_struct_page(obj)) |
b50a5371 AS |
863 | return -ENODEV; |
864 | ||
3ed605bc | 865 | user_data = u64_to_user_ptr(args->data_ptr); |
eb01459f EA |
866 | remain = args->size; |
867 | ||
8461d226 | 868 | obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj); |
eb01459f | 869 | |
4c914c0c | 870 | ret = i915_gem_obj_prepare_shmem_read(obj, &needs_clflush); |
f60d7f0c CW |
871 | if (ret) |
872 | return ret; | |
873 | ||
8461d226 | 874 | offset = args->offset; |
eb01459f | 875 | |
67d5a50c ID |
876 | for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, |
877 | offset >> PAGE_SHIFT) { | |
2db76d7c | 878 | struct page *page = sg_page_iter_page(&sg_iter); |
9da3da66 CW |
879 | |
880 | if (remain <= 0) | |
881 | break; | |
882 | ||
eb01459f EA |
883 | /* Operation in this page |
884 | * | |
eb01459f | 885 | * shmem_page_offset = offset within page in shmem file |
eb01459f EA |
886 | * page_length = bytes to copy for this page |
887 | */ | |
c8cbbb8b | 888 | shmem_page_offset = offset_in_page(offset); |
eb01459f EA |
889 | page_length = remain; |
890 | if ((shmem_page_offset + page_length) > PAGE_SIZE) | |
891 | page_length = PAGE_SIZE - shmem_page_offset; | |
eb01459f | 892 | |
8461d226 DV |
893 | page_do_bit17_swizzling = obj_do_bit17_swizzling && |
894 | (page_to_phys(page) & (1 << 17)) != 0; | |
895 | ||
d174bd64 DV |
896 | ret = shmem_pread_fast(page, shmem_page_offset, page_length, |
897 | user_data, page_do_bit17_swizzling, | |
898 | needs_clflush); | |
899 | if (ret == 0) | |
900 | goto next_page; | |
dbf7bff0 | 901 | |
dbf7bff0 DV |
902 | mutex_unlock(&dev->struct_mutex); |
903 | ||
d330a953 | 904 | if (likely(!i915.prefault_disable) && !prefaulted) { |
f56f821f | 905 | ret = fault_in_multipages_writeable(user_data, remain); |
96d79b52 DV |
906 | /* Userspace is tricking us, but we've already clobbered |
907 | * its pages with the prefault and promised to write the | |
908 | * data up to the first fault. Hence ignore any errors | |
909 | * and just continue. */ | |
910 | (void)ret; | |
911 | prefaulted = 1; | |
912 | } | |
eb01459f | 913 | |
d174bd64 DV |
914 | ret = shmem_pread_slow(page, shmem_page_offset, page_length, |
915 | user_data, page_do_bit17_swizzling, | |
916 | needs_clflush); | |
eb01459f | 917 | |
dbf7bff0 | 918 | mutex_lock(&dev->struct_mutex); |
f60d7f0c | 919 | |
f60d7f0c | 920 | if (ret) |
8461d226 | 921 | goto out; |
8461d226 | 922 | |
17793c9a | 923 | next_page: |
eb01459f | 924 | remain -= page_length; |
8461d226 | 925 | user_data += page_length; |
eb01459f EA |
926 | offset += page_length; |
927 | } | |
928 | ||
4f27b75d | 929 | out: |
f60d7f0c CW |
930 | i915_gem_object_unpin_pages(obj); |
931 | ||
eb01459f EA |
932 | return ret; |
933 | } | |
934 | ||
673a394b EA |
935 | /** |
936 | * Reads data from the object referenced by handle. | |
14bb2c11 TU |
937 | * @dev: drm device pointer |
938 | * @data: ioctl data blob | |
939 | * @file: drm file pointer | |
673a394b EA |
940 | * |
941 | * On error, the contents of *data are undefined. | |
942 | */ | |
943 | int | |
944 | i915_gem_pread_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 945 | struct drm_file *file) |
673a394b EA |
946 | { |
947 | struct drm_i915_gem_pread *args = data; | |
05394f39 | 948 | struct drm_i915_gem_object *obj; |
35b62a89 | 949 | int ret = 0; |
673a394b | 950 | |
51311d0a CW |
951 | if (args->size == 0) |
952 | return 0; | |
953 | ||
954 | if (!access_ok(VERIFY_WRITE, | |
3ed605bc | 955 | u64_to_user_ptr(args->data_ptr), |
51311d0a CW |
956 | args->size)) |
957 | return -EFAULT; | |
958 | ||
4f27b75d | 959 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 960 | if (ret) |
4f27b75d | 961 | return ret; |
673a394b | 962 | |
03ac0642 CW |
963 | obj = i915_gem_object_lookup(file, args->handle); |
964 | if (!obj) { | |
1d7cfea1 CW |
965 | ret = -ENOENT; |
966 | goto unlock; | |
4f27b75d | 967 | } |
673a394b | 968 | |
7dcd2499 | 969 | /* Bounds check source. */ |
05394f39 CW |
970 | if (args->offset > obj->base.size || |
971 | args->size > obj->base.size - args->offset) { | |
ce9d419d | 972 | ret = -EINVAL; |
35b62a89 | 973 | goto out; |
ce9d419d CW |
974 | } |
975 | ||
db53a302 CW |
976 | trace_i915_gem_object_pread(obj, args->offset, args->size); |
977 | ||
dbf7bff0 | 978 | ret = i915_gem_shmem_pread(dev, obj, args, file); |
673a394b | 979 | |
b50a5371 | 980 | /* pread for non shmem backed objects */ |
1dd5b6f2 CW |
981 | if (ret == -EFAULT || ret == -ENODEV) { |
982 | intel_runtime_pm_get(to_i915(dev)); | |
b50a5371 AS |
983 | ret = i915_gem_gtt_pread(dev, obj, args->size, |
984 | args->offset, args->data_ptr); | |
1dd5b6f2 CW |
985 | intel_runtime_pm_put(to_i915(dev)); |
986 | } | |
b50a5371 | 987 | |
35b62a89 | 988 | out: |
f8c417cd | 989 | i915_gem_object_put(obj); |
1d7cfea1 | 990 | unlock: |
4f27b75d | 991 | mutex_unlock(&dev->struct_mutex); |
eb01459f | 992 | return ret; |
673a394b EA |
993 | } |
994 | ||
0839ccb8 KP |
995 | /* This is the fast write path which cannot handle |
996 | * page faults in the source data | |
9b7530cc | 997 | */ |
0839ccb8 KP |
998 | |
999 | static inline int | |
1000 | fast_user_write(struct io_mapping *mapping, | |
1001 | loff_t page_base, int page_offset, | |
1002 | char __user *user_data, | |
1003 | int length) | |
9b7530cc | 1004 | { |
4f0c7cfb BW |
1005 | void __iomem *vaddr_atomic; |
1006 | void *vaddr; | |
0839ccb8 | 1007 | unsigned long unwritten; |
9b7530cc | 1008 | |
3e4d3af5 | 1009 | vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base); |
4f0c7cfb BW |
1010 | /* We can use the cpu mem copy function because this is X86. */ |
1011 | vaddr = (void __force*)vaddr_atomic + page_offset; | |
1012 | unwritten = __copy_from_user_inatomic_nocache(vaddr, | |
0839ccb8 | 1013 | user_data, length); |
3e4d3af5 | 1014 | io_mapping_unmap_atomic(vaddr_atomic); |
fbd5a26d | 1015 | return unwritten; |
0839ccb8 KP |
1016 | } |
1017 | ||
3de09aa3 EA |
1018 | /** |
1019 | * This is the fast pwrite path, where we copy the data directly from the | |
1020 | * user into the GTT, uncached. | |
62f90b38 | 1021 | * @i915: i915 device private data |
14bb2c11 TU |
1022 | * @obj: i915 gem object |
1023 | * @args: pwrite arguments structure | |
1024 | * @file: drm file pointer | |
3de09aa3 | 1025 | */ |
673a394b | 1026 | static int |
4f1959ee | 1027 | i915_gem_gtt_pwrite_fast(struct drm_i915_private *i915, |
05394f39 | 1028 | struct drm_i915_gem_object *obj, |
3de09aa3 | 1029 | struct drm_i915_gem_pwrite *args, |
05394f39 | 1030 | struct drm_file *file) |
673a394b | 1031 | { |
4f1959ee | 1032 | struct i915_ggtt *ggtt = &i915->ggtt; |
b50a5371 | 1033 | struct drm_device *dev = obj->base.dev; |
4f1959ee AS |
1034 | struct drm_mm_node node; |
1035 | uint64_t remain, offset; | |
673a394b | 1036 | char __user *user_data; |
4f1959ee | 1037 | int ret; |
b50a5371 AS |
1038 | bool hit_slow_path = false; |
1039 | ||
1040 | if (obj->tiling_mode != I915_TILING_NONE) | |
1041 | return -EFAULT; | |
935aaa69 | 1042 | |
de895082 CW |
1043 | ret = i915_gem_object_ggtt_pin(obj, NULL, 0, 0, |
1044 | PIN_MAPPABLE | PIN_NONBLOCK); | |
4f1959ee AS |
1045 | if (ret) { |
1046 | ret = insert_mappable_node(i915, &node, PAGE_SIZE); | |
1047 | if (ret) | |
1048 | goto out; | |
1049 | ||
1050 | ret = i915_gem_object_get_pages(obj); | |
1051 | if (ret) { | |
1052 | remove_mappable_node(&node); | |
1053 | goto out; | |
1054 | } | |
1055 | ||
1056 | i915_gem_object_pin_pages(obj); | |
1057 | } else { | |
1058 | node.start = i915_gem_obj_ggtt_offset(obj); | |
1059 | node.allocated = false; | |
b50a5371 AS |
1060 | ret = i915_gem_object_put_fence(obj); |
1061 | if (ret) | |
1062 | goto out_unpin; | |
4f1959ee | 1063 | } |
935aaa69 DV |
1064 | |
1065 | ret = i915_gem_object_set_to_gtt_domain(obj, true); | |
1066 | if (ret) | |
1067 | goto out_unpin; | |
1068 | ||
77a0d1ca | 1069 | intel_fb_obj_invalidate(obj, ORIGIN_GTT); |
4f1959ee | 1070 | obj->dirty = true; |
063e4e6b | 1071 | |
4f1959ee AS |
1072 | user_data = u64_to_user_ptr(args->data_ptr); |
1073 | offset = args->offset; | |
1074 | remain = args->size; | |
1075 | while (remain) { | |
673a394b EA |
1076 | /* Operation in this page |
1077 | * | |
0839ccb8 KP |
1078 | * page_base = page offset within aperture |
1079 | * page_offset = offset within page | |
1080 | * page_length = bytes to copy for this page | |
673a394b | 1081 | */ |
4f1959ee AS |
1082 | u32 page_base = node.start; |
1083 | unsigned page_offset = offset_in_page(offset); | |
1084 | unsigned page_length = PAGE_SIZE - page_offset; | |
1085 | page_length = remain < page_length ? remain : page_length; | |
1086 | if (node.allocated) { | |
1087 | wmb(); /* flush the write before we modify the GGTT */ | |
1088 | ggtt->base.insert_page(&ggtt->base, | |
1089 | i915_gem_object_get_dma_address(obj, offset >> PAGE_SHIFT), | |
1090 | node.start, I915_CACHE_NONE, 0); | |
1091 | wmb(); /* flush modifications to the GGTT (insert_page) */ | |
1092 | } else { | |
1093 | page_base += offset & PAGE_MASK; | |
1094 | } | |
0839ccb8 | 1095 | /* If we get a fault while copying data, then (presumably) our |
3de09aa3 EA |
1096 | * source page isn't available. Return the error and we'll |
1097 | * retry in the slow path. | |
b50a5371 AS |
1098 | * If the object is non-shmem backed, we retry again with the |
1099 | * path that handles page fault. | |
0839ccb8 | 1100 | */ |
72e96d64 | 1101 | if (fast_user_write(ggtt->mappable, page_base, |
935aaa69 | 1102 | page_offset, user_data, page_length)) { |
b50a5371 AS |
1103 | hit_slow_path = true; |
1104 | mutex_unlock(&dev->struct_mutex); | |
1105 | if (slow_user_access(ggtt->mappable, | |
1106 | page_base, | |
1107 | page_offset, user_data, | |
1108 | page_length, true)) { | |
1109 | ret = -EFAULT; | |
1110 | mutex_lock(&dev->struct_mutex); | |
1111 | goto out_flush; | |
1112 | } | |
1113 | ||
1114 | mutex_lock(&dev->struct_mutex); | |
935aaa69 | 1115 | } |
673a394b | 1116 | |
0839ccb8 KP |
1117 | remain -= page_length; |
1118 | user_data += page_length; | |
1119 | offset += page_length; | |
673a394b | 1120 | } |
673a394b | 1121 | |
063e4e6b | 1122 | out_flush: |
b50a5371 AS |
1123 | if (hit_slow_path) { |
1124 | if (ret == 0 && | |
1125 | (obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0) { | |
1126 | /* The user has modified the object whilst we tried | |
1127 | * reading from it, and we now have no idea what domain | |
1128 | * the pages should be in. As we have just been touching | |
1129 | * them directly, flush everything back to the GTT | |
1130 | * domain. | |
1131 | */ | |
1132 | ret = i915_gem_object_set_to_gtt_domain(obj, false); | |
1133 | } | |
1134 | } | |
1135 | ||
de152b62 | 1136 | intel_fb_obj_flush(obj, false, ORIGIN_GTT); |
935aaa69 | 1137 | out_unpin: |
4f1959ee AS |
1138 | if (node.allocated) { |
1139 | wmb(); | |
1140 | ggtt->base.clear_range(&ggtt->base, | |
1141 | node.start, node.size, | |
1142 | true); | |
1143 | i915_gem_object_unpin_pages(obj); | |
1144 | remove_mappable_node(&node); | |
1145 | } else { | |
1146 | i915_gem_object_ggtt_unpin(obj); | |
1147 | } | |
935aaa69 | 1148 | out: |
3de09aa3 | 1149 | return ret; |
673a394b EA |
1150 | } |
1151 | ||
d174bd64 DV |
1152 | /* Per-page copy function for the shmem pwrite fastpath. |
1153 | * Flushes invalid cachelines before writing to the target if | |
1154 | * needs_clflush_before is set and flushes out any written cachelines after | |
1155 | * writing if needs_clflush is set. */ | |
3043c60c | 1156 | static int |
d174bd64 DV |
1157 | shmem_pwrite_fast(struct page *page, int shmem_page_offset, int page_length, |
1158 | char __user *user_data, | |
1159 | bool page_do_bit17_swizzling, | |
1160 | bool needs_clflush_before, | |
1161 | bool needs_clflush_after) | |
673a394b | 1162 | { |
d174bd64 | 1163 | char *vaddr; |
673a394b | 1164 | int ret; |
3de09aa3 | 1165 | |
e7e58eb5 | 1166 | if (unlikely(page_do_bit17_swizzling)) |
d174bd64 | 1167 | return -EINVAL; |
3de09aa3 | 1168 | |
d174bd64 DV |
1169 | vaddr = kmap_atomic(page); |
1170 | if (needs_clflush_before) | |
1171 | drm_clflush_virt_range(vaddr + shmem_page_offset, | |
1172 | page_length); | |
c2831a94 CW |
1173 | ret = __copy_from_user_inatomic(vaddr + shmem_page_offset, |
1174 | user_data, page_length); | |
d174bd64 DV |
1175 | if (needs_clflush_after) |
1176 | drm_clflush_virt_range(vaddr + shmem_page_offset, | |
1177 | page_length); | |
1178 | kunmap_atomic(vaddr); | |
3de09aa3 | 1179 | |
755d2218 | 1180 | return ret ? -EFAULT : 0; |
3de09aa3 EA |
1181 | } |
1182 | ||
d174bd64 DV |
1183 | /* Only difference to the fast-path function is that this can handle bit17 |
1184 | * and uses non-atomic copy and kmap functions. */ | |
3043c60c | 1185 | static int |
d174bd64 DV |
1186 | shmem_pwrite_slow(struct page *page, int shmem_page_offset, int page_length, |
1187 | char __user *user_data, | |
1188 | bool page_do_bit17_swizzling, | |
1189 | bool needs_clflush_before, | |
1190 | bool needs_clflush_after) | |
673a394b | 1191 | { |
d174bd64 DV |
1192 | char *vaddr; |
1193 | int ret; | |
e5281ccd | 1194 | |
d174bd64 | 1195 | vaddr = kmap(page); |
e7e58eb5 | 1196 | if (unlikely(needs_clflush_before || page_do_bit17_swizzling)) |
23c18c71 DV |
1197 | shmem_clflush_swizzled_range(vaddr + shmem_page_offset, |
1198 | page_length, | |
1199 | page_do_bit17_swizzling); | |
d174bd64 DV |
1200 | if (page_do_bit17_swizzling) |
1201 | ret = __copy_from_user_swizzled(vaddr, shmem_page_offset, | |
e5281ccd CW |
1202 | user_data, |
1203 | page_length); | |
d174bd64 DV |
1204 | else |
1205 | ret = __copy_from_user(vaddr + shmem_page_offset, | |
1206 | user_data, | |
1207 | page_length); | |
1208 | if (needs_clflush_after) | |
23c18c71 DV |
1209 | shmem_clflush_swizzled_range(vaddr + shmem_page_offset, |
1210 | page_length, | |
1211 | page_do_bit17_swizzling); | |
d174bd64 | 1212 | kunmap(page); |
40123c1f | 1213 | |
755d2218 | 1214 | return ret ? -EFAULT : 0; |
40123c1f EA |
1215 | } |
1216 | ||
40123c1f | 1217 | static int |
e244a443 DV |
1218 | i915_gem_shmem_pwrite(struct drm_device *dev, |
1219 | struct drm_i915_gem_object *obj, | |
1220 | struct drm_i915_gem_pwrite *args, | |
1221 | struct drm_file *file) | |
40123c1f | 1222 | { |
40123c1f | 1223 | ssize_t remain; |
8c59967c DV |
1224 | loff_t offset; |
1225 | char __user *user_data; | |
eb2c0c81 | 1226 | int shmem_page_offset, page_length, ret = 0; |
8c59967c | 1227 | int obj_do_bit17_swizzling, page_do_bit17_swizzling; |
e244a443 | 1228 | int hit_slowpath = 0; |
58642885 DV |
1229 | int needs_clflush_after = 0; |
1230 | int needs_clflush_before = 0; | |
67d5a50c | 1231 | struct sg_page_iter sg_iter; |
40123c1f | 1232 | |
3ed605bc | 1233 | user_data = u64_to_user_ptr(args->data_ptr); |
40123c1f EA |
1234 | remain = args->size; |
1235 | ||
8c59967c | 1236 | obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj); |
40123c1f | 1237 | |
c13d87ea CW |
1238 | ret = i915_gem_object_wait_rendering(obj, false); |
1239 | if (ret) | |
1240 | return ret; | |
1241 | ||
58642885 DV |
1242 | if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) { |
1243 | /* If we're not in the cpu write domain, set ourself into the gtt | |
1244 | * write domain and manually flush cachelines (if required). This | |
1245 | * optimizes for the case when the gpu will use the data | |
1246 | * right away and we therefore have to clflush anyway. */ | |
2c22569b | 1247 | needs_clflush_after = cpu_write_needs_clflush(obj); |
58642885 | 1248 | } |
c76ce038 CW |
1249 | /* Same trick applies to invalidate partially written cachelines read |
1250 | * before writing. */ | |
1251 | if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) | |
1252 | needs_clflush_before = | |
1253 | !cpu_cache_is_coherent(dev, obj->cache_level); | |
58642885 | 1254 | |
755d2218 CW |
1255 | ret = i915_gem_object_get_pages(obj); |
1256 | if (ret) | |
1257 | return ret; | |
1258 | ||
77a0d1ca | 1259 | intel_fb_obj_invalidate(obj, ORIGIN_CPU); |
063e4e6b | 1260 | |
755d2218 CW |
1261 | i915_gem_object_pin_pages(obj); |
1262 | ||
673a394b | 1263 | offset = args->offset; |
05394f39 | 1264 | obj->dirty = 1; |
673a394b | 1265 | |
67d5a50c ID |
1266 | for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, |
1267 | offset >> PAGE_SHIFT) { | |
2db76d7c | 1268 | struct page *page = sg_page_iter_page(&sg_iter); |
58642885 | 1269 | int partial_cacheline_write; |
e5281ccd | 1270 | |
9da3da66 CW |
1271 | if (remain <= 0) |
1272 | break; | |
1273 | ||
40123c1f EA |
1274 | /* Operation in this page |
1275 | * | |
40123c1f | 1276 | * shmem_page_offset = offset within page in shmem file |
40123c1f EA |
1277 | * page_length = bytes to copy for this page |
1278 | */ | |
c8cbbb8b | 1279 | shmem_page_offset = offset_in_page(offset); |
40123c1f EA |
1280 | |
1281 | page_length = remain; | |
1282 | if ((shmem_page_offset + page_length) > PAGE_SIZE) | |
1283 | page_length = PAGE_SIZE - shmem_page_offset; | |
40123c1f | 1284 | |
58642885 DV |
1285 | /* If we don't overwrite a cacheline completely we need to be |
1286 | * careful to have up-to-date data by first clflushing. Don't | |
1287 | * overcomplicate things and flush the entire patch. */ | |
1288 | partial_cacheline_write = needs_clflush_before && | |
1289 | ((shmem_page_offset | page_length) | |
1290 | & (boot_cpu_data.x86_clflush_size - 1)); | |
1291 | ||
8c59967c DV |
1292 | page_do_bit17_swizzling = obj_do_bit17_swizzling && |
1293 | (page_to_phys(page) & (1 << 17)) != 0; | |
1294 | ||
d174bd64 DV |
1295 | ret = shmem_pwrite_fast(page, shmem_page_offset, page_length, |
1296 | user_data, page_do_bit17_swizzling, | |
1297 | partial_cacheline_write, | |
1298 | needs_clflush_after); | |
1299 | if (ret == 0) | |
1300 | goto next_page; | |
e244a443 DV |
1301 | |
1302 | hit_slowpath = 1; | |
e244a443 | 1303 | mutex_unlock(&dev->struct_mutex); |
d174bd64 DV |
1304 | ret = shmem_pwrite_slow(page, shmem_page_offset, page_length, |
1305 | user_data, page_do_bit17_swizzling, | |
1306 | partial_cacheline_write, | |
1307 | needs_clflush_after); | |
40123c1f | 1308 | |
e244a443 | 1309 | mutex_lock(&dev->struct_mutex); |
755d2218 | 1310 | |
755d2218 | 1311 | if (ret) |
8c59967c | 1312 | goto out; |
8c59967c | 1313 | |
17793c9a | 1314 | next_page: |
40123c1f | 1315 | remain -= page_length; |
8c59967c | 1316 | user_data += page_length; |
40123c1f | 1317 | offset += page_length; |
673a394b EA |
1318 | } |
1319 | ||
fbd5a26d | 1320 | out: |
755d2218 CW |
1321 | i915_gem_object_unpin_pages(obj); |
1322 | ||
e244a443 | 1323 | if (hit_slowpath) { |
8dcf015e DV |
1324 | /* |
1325 | * Fixup: Flush cpu caches in case we didn't flush the dirty | |
1326 | * cachelines in-line while writing and the object moved | |
1327 | * out of the cpu write domain while we've dropped the lock. | |
1328 | */ | |
1329 | if (!needs_clflush_after && | |
1330 | obj->base.write_domain != I915_GEM_DOMAIN_CPU) { | |
000433b6 | 1331 | if (i915_gem_clflush_object(obj, obj->pin_display)) |
ed75a55b | 1332 | needs_clflush_after = true; |
e244a443 | 1333 | } |
8c59967c | 1334 | } |
673a394b | 1335 | |
58642885 | 1336 | if (needs_clflush_after) |
c033666a | 1337 | i915_gem_chipset_flush(to_i915(dev)); |
ed75a55b VS |
1338 | else |
1339 | obj->cache_dirty = true; | |
58642885 | 1340 | |
de152b62 | 1341 | intel_fb_obj_flush(obj, false, ORIGIN_CPU); |
40123c1f | 1342 | return ret; |
673a394b EA |
1343 | } |
1344 | ||
1345 | /** | |
1346 | * Writes data to the object referenced by handle. | |
14bb2c11 TU |
1347 | * @dev: drm device |
1348 | * @data: ioctl data blob | |
1349 | * @file: drm file | |
673a394b EA |
1350 | * |
1351 | * On error, the contents of the buffer that were to be modified are undefined. | |
1352 | */ | |
1353 | int | |
1354 | i915_gem_pwrite_ioctl(struct drm_device *dev, void *data, | |
fbd5a26d | 1355 | struct drm_file *file) |
673a394b | 1356 | { |
fac5e23e | 1357 | struct drm_i915_private *dev_priv = to_i915(dev); |
673a394b | 1358 | struct drm_i915_gem_pwrite *args = data; |
05394f39 | 1359 | struct drm_i915_gem_object *obj; |
51311d0a CW |
1360 | int ret; |
1361 | ||
1362 | if (args->size == 0) | |
1363 | return 0; | |
1364 | ||
1365 | if (!access_ok(VERIFY_READ, | |
3ed605bc | 1366 | u64_to_user_ptr(args->data_ptr), |
51311d0a CW |
1367 | args->size)) |
1368 | return -EFAULT; | |
1369 | ||
d330a953 | 1370 | if (likely(!i915.prefault_disable)) { |
3ed605bc | 1371 | ret = fault_in_multipages_readable(u64_to_user_ptr(args->data_ptr), |
0b74b508 XZ |
1372 | args->size); |
1373 | if (ret) | |
1374 | return -EFAULT; | |
1375 | } | |
673a394b | 1376 | |
5d77d9c5 ID |
1377 | intel_runtime_pm_get(dev_priv); |
1378 | ||
fbd5a26d | 1379 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 1380 | if (ret) |
5d77d9c5 | 1381 | goto put_rpm; |
1d7cfea1 | 1382 | |
03ac0642 CW |
1383 | obj = i915_gem_object_lookup(file, args->handle); |
1384 | if (!obj) { | |
1d7cfea1 CW |
1385 | ret = -ENOENT; |
1386 | goto unlock; | |
fbd5a26d | 1387 | } |
673a394b | 1388 | |
7dcd2499 | 1389 | /* Bounds check destination. */ |
05394f39 CW |
1390 | if (args->offset > obj->base.size || |
1391 | args->size > obj->base.size - args->offset) { | |
ce9d419d | 1392 | ret = -EINVAL; |
35b62a89 | 1393 | goto out; |
ce9d419d CW |
1394 | } |
1395 | ||
db53a302 CW |
1396 | trace_i915_gem_object_pwrite(obj, args->offset, args->size); |
1397 | ||
935aaa69 | 1398 | ret = -EFAULT; |
673a394b EA |
1399 | /* We can only do the GTT pwrite on untiled buffers, as otherwise |
1400 | * it would end up going through the fenced access, and we'll get | |
1401 | * different detiling behavior between reading and writing. | |
1402 | * pread/pwrite currently are reading and writing from the CPU | |
1403 | * perspective, requiring manual detiling by the client. | |
1404 | */ | |
6eae0059 CW |
1405 | if (!i915_gem_object_has_struct_page(obj) || |
1406 | cpu_write_needs_clflush(obj)) { | |
4f1959ee | 1407 | ret = i915_gem_gtt_pwrite_fast(dev_priv, obj, args, file); |
935aaa69 DV |
1408 | /* Note that the gtt paths might fail with non-page-backed user |
1409 | * pointers (e.g. gtt mappings when moving data between | |
1410 | * textures). Fallback to the shmem path in that case. */ | |
fbd5a26d | 1411 | } |
673a394b | 1412 | |
d1054ee4 | 1413 | if (ret == -EFAULT || ret == -ENOSPC) { |
6a2c4232 CW |
1414 | if (obj->phys_handle) |
1415 | ret = i915_gem_phys_pwrite(obj, args, file); | |
6eae0059 | 1416 | else if (i915_gem_object_has_struct_page(obj)) |
6a2c4232 | 1417 | ret = i915_gem_shmem_pwrite(dev, obj, args, file); |
b50a5371 AS |
1418 | else |
1419 | ret = -ENODEV; | |
6a2c4232 | 1420 | } |
5c0480f2 | 1421 | |
35b62a89 | 1422 | out: |
f8c417cd | 1423 | i915_gem_object_put(obj); |
1d7cfea1 | 1424 | unlock: |
fbd5a26d | 1425 | mutex_unlock(&dev->struct_mutex); |
5d77d9c5 ID |
1426 | put_rpm: |
1427 | intel_runtime_pm_put(dev_priv); | |
1428 | ||
673a394b EA |
1429 | return ret; |
1430 | } | |
1431 | ||
aeecc969 CW |
1432 | static enum fb_op_origin |
1433 | write_origin(struct drm_i915_gem_object *obj, unsigned domain) | |
1434 | { | |
1435 | return domain == I915_GEM_DOMAIN_GTT && !obj->has_wc_mmap ? | |
1436 | ORIGIN_GTT : ORIGIN_CPU; | |
1437 | } | |
1438 | ||
673a394b | 1439 | /** |
2ef7eeaa EA |
1440 | * Called when user space prepares to use an object with the CPU, either |
1441 | * through the mmap ioctl's mapping or a GTT mapping. | |
14bb2c11 TU |
1442 | * @dev: drm device |
1443 | * @data: ioctl data blob | |
1444 | * @file: drm file | |
673a394b EA |
1445 | */ |
1446 | int | |
1447 | i915_gem_set_domain_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 1448 | struct drm_file *file) |
673a394b EA |
1449 | { |
1450 | struct drm_i915_gem_set_domain *args = data; | |
05394f39 | 1451 | struct drm_i915_gem_object *obj; |
2ef7eeaa EA |
1452 | uint32_t read_domains = args->read_domains; |
1453 | uint32_t write_domain = args->write_domain; | |
673a394b EA |
1454 | int ret; |
1455 | ||
2ef7eeaa | 1456 | /* Only handle setting domains to types used by the CPU. */ |
b8f9096d | 1457 | if ((write_domain | read_domains) & I915_GEM_GPU_DOMAINS) |
2ef7eeaa EA |
1458 | return -EINVAL; |
1459 | ||
1460 | /* Having something in the write domain implies it's in the read | |
1461 | * domain, and only that read domain. Enforce that in the request. | |
1462 | */ | |
1463 | if (write_domain != 0 && read_domains != write_domain) | |
1464 | return -EINVAL; | |
1465 | ||
03ac0642 | 1466 | obj = i915_gem_object_lookup(file, args->handle); |
b8f9096d CW |
1467 | if (!obj) |
1468 | return -ENOENT; | |
673a394b | 1469 | |
3236f57a CW |
1470 | /* Try to flush the object off the GPU without holding the lock. |
1471 | * We will repeat the flush holding the lock in the normal manner | |
1472 | * to catch cases where we are gazumped. | |
1473 | */ | |
b8f9096d CW |
1474 | ret = __unsafe_wait_rendering(obj, to_rps_client(file), !write_domain); |
1475 | if (ret) | |
1476 | goto err; | |
1477 | ||
1478 | ret = i915_mutex_lock_interruptible(dev); | |
3236f57a | 1479 | if (ret) |
b8f9096d | 1480 | goto err; |
3236f57a | 1481 | |
43566ded | 1482 | if (read_domains & I915_GEM_DOMAIN_GTT) |
2ef7eeaa | 1483 | ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0); |
43566ded | 1484 | else |
e47c68e9 | 1485 | ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0); |
2ef7eeaa | 1486 | |
031b698a | 1487 | if (write_domain != 0) |
aeecc969 | 1488 | intel_fb_obj_invalidate(obj, write_origin(obj, write_domain)); |
031b698a | 1489 | |
f8c417cd | 1490 | i915_gem_object_put(obj); |
673a394b EA |
1491 | mutex_unlock(&dev->struct_mutex); |
1492 | return ret; | |
b8f9096d CW |
1493 | |
1494 | err: | |
1495 | i915_gem_object_put_unlocked(obj); | |
1496 | return ret; | |
673a394b EA |
1497 | } |
1498 | ||
1499 | /** | |
1500 | * Called when user space has done writes to this buffer | |
14bb2c11 TU |
1501 | * @dev: drm device |
1502 | * @data: ioctl data blob | |
1503 | * @file: drm file | |
673a394b EA |
1504 | */ |
1505 | int | |
1506 | i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 1507 | struct drm_file *file) |
673a394b EA |
1508 | { |
1509 | struct drm_i915_gem_sw_finish *args = data; | |
05394f39 | 1510 | struct drm_i915_gem_object *obj; |
673a394b EA |
1511 | int ret = 0; |
1512 | ||
76c1dec1 | 1513 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 1514 | if (ret) |
76c1dec1 | 1515 | return ret; |
1d7cfea1 | 1516 | |
03ac0642 CW |
1517 | obj = i915_gem_object_lookup(file, args->handle); |
1518 | if (!obj) { | |
1d7cfea1 CW |
1519 | ret = -ENOENT; |
1520 | goto unlock; | |
673a394b EA |
1521 | } |
1522 | ||
673a394b | 1523 | /* Pinned buffers may be scanout, so flush the cache */ |
2c22569b | 1524 | if (obj->pin_display) |
e62b59e4 | 1525 | i915_gem_object_flush_cpu_write_domain(obj); |
e47c68e9 | 1526 | |
f8c417cd | 1527 | i915_gem_object_put(obj); |
1d7cfea1 | 1528 | unlock: |
673a394b EA |
1529 | mutex_unlock(&dev->struct_mutex); |
1530 | return ret; | |
1531 | } | |
1532 | ||
1533 | /** | |
14bb2c11 TU |
1534 | * i915_gem_mmap_ioctl - Maps the contents of an object, returning the address |
1535 | * it is mapped to. | |
1536 | * @dev: drm device | |
1537 | * @data: ioctl data blob | |
1538 | * @file: drm file | |
673a394b EA |
1539 | * |
1540 | * While the mapping holds a reference on the contents of the object, it doesn't | |
1541 | * imply a ref on the object itself. | |
34367381 DV |
1542 | * |
1543 | * IMPORTANT: | |
1544 | * | |
1545 | * DRM driver writers who look a this function as an example for how to do GEM | |
1546 | * mmap support, please don't implement mmap support like here. The modern way | |
1547 | * to implement DRM mmap support is with an mmap offset ioctl (like | |
1548 | * i915_gem_mmap_gtt) and then using the mmap syscall on the DRM fd directly. | |
1549 | * That way debug tooling like valgrind will understand what's going on, hiding | |
1550 | * the mmap call in a driver private ioctl will break that. The i915 driver only | |
1551 | * does cpu mmaps this way because we didn't know better. | |
673a394b EA |
1552 | */ |
1553 | int | |
1554 | i915_gem_mmap_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 1555 | struct drm_file *file) |
673a394b EA |
1556 | { |
1557 | struct drm_i915_gem_mmap *args = data; | |
03ac0642 | 1558 | struct drm_i915_gem_object *obj; |
673a394b EA |
1559 | unsigned long addr; |
1560 | ||
1816f923 AG |
1561 | if (args->flags & ~(I915_MMAP_WC)) |
1562 | return -EINVAL; | |
1563 | ||
568a58e5 | 1564 | if (args->flags & I915_MMAP_WC && !boot_cpu_has(X86_FEATURE_PAT)) |
1816f923 AG |
1565 | return -ENODEV; |
1566 | ||
03ac0642 CW |
1567 | obj = i915_gem_object_lookup(file, args->handle); |
1568 | if (!obj) | |
bf79cb91 | 1569 | return -ENOENT; |
673a394b | 1570 | |
1286ff73 DV |
1571 | /* prime objects have no backing filp to GEM mmap |
1572 | * pages from. | |
1573 | */ | |
03ac0642 | 1574 | if (!obj->base.filp) { |
34911fd3 | 1575 | i915_gem_object_put_unlocked(obj); |
1286ff73 DV |
1576 | return -EINVAL; |
1577 | } | |
1578 | ||
03ac0642 | 1579 | addr = vm_mmap(obj->base.filp, 0, args->size, |
673a394b EA |
1580 | PROT_READ | PROT_WRITE, MAP_SHARED, |
1581 | args->offset); | |
1816f923 AG |
1582 | if (args->flags & I915_MMAP_WC) { |
1583 | struct mm_struct *mm = current->mm; | |
1584 | struct vm_area_struct *vma; | |
1585 | ||
80a89a5e | 1586 | if (down_write_killable(&mm->mmap_sem)) { |
34911fd3 | 1587 | i915_gem_object_put_unlocked(obj); |
80a89a5e MH |
1588 | return -EINTR; |
1589 | } | |
1816f923 AG |
1590 | vma = find_vma(mm, addr); |
1591 | if (vma) | |
1592 | vma->vm_page_prot = | |
1593 | pgprot_writecombine(vm_get_page_prot(vma->vm_flags)); | |
1594 | else | |
1595 | addr = -ENOMEM; | |
1596 | up_write(&mm->mmap_sem); | |
aeecc969 CW |
1597 | |
1598 | /* This may race, but that's ok, it only gets set */ | |
03ac0642 | 1599 | WRITE_ONCE(obj->has_wc_mmap, true); |
1816f923 | 1600 | } |
34911fd3 | 1601 | i915_gem_object_put_unlocked(obj); |
673a394b EA |
1602 | if (IS_ERR((void *)addr)) |
1603 | return addr; | |
1604 | ||
1605 | args->addr_ptr = (uint64_t) addr; | |
1606 | ||
1607 | return 0; | |
1608 | } | |
1609 | ||
de151cf6 JB |
1610 | /** |
1611 | * i915_gem_fault - fault a page into the GTT | |
d9072a3e GT |
1612 | * @vma: VMA in question |
1613 | * @vmf: fault info | |
de151cf6 JB |
1614 | * |
1615 | * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped | |
1616 | * from userspace. The fault handler takes care of binding the object to | |
1617 | * the GTT (if needed), allocating and programming a fence register (again, | |
1618 | * only if needed based on whether the old reg is still valid or the object | |
1619 | * is tiled) and inserting a new PTE into the faulting process. | |
1620 | * | |
1621 | * Note that the faulting process may involve evicting existing objects | |
1622 | * from the GTT and/or fence registers to make room. So performance may | |
1623 | * suffer if the GTT working set is large or there are few fence registers | |
1624 | * left. | |
1625 | */ | |
1626 | int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf) | |
1627 | { | |
05394f39 CW |
1628 | struct drm_i915_gem_object *obj = to_intel_bo(vma->vm_private_data); |
1629 | struct drm_device *dev = obj->base.dev; | |
72e96d64 JL |
1630 | struct drm_i915_private *dev_priv = to_i915(dev); |
1631 | struct i915_ggtt *ggtt = &dev_priv->ggtt; | |
c5ad54cf | 1632 | struct i915_ggtt_view view = i915_ggtt_view_normal; |
b8f9096d | 1633 | bool write = !!(vmf->flags & FAULT_FLAG_WRITE); |
de151cf6 JB |
1634 | pgoff_t page_offset; |
1635 | unsigned long pfn; | |
b8f9096d | 1636 | int ret; |
f65c9168 | 1637 | |
de151cf6 JB |
1638 | /* We don't use vmf->pgoff since that has the fake offset */ |
1639 | page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >> | |
1640 | PAGE_SHIFT; | |
1641 | ||
db53a302 CW |
1642 | trace_i915_gem_object_fault(obj, page_offset, true, write); |
1643 | ||
6e4930f6 | 1644 | /* Try to flush the object off the GPU first without holding the lock. |
b8f9096d | 1645 | * Upon acquiring the lock, we will perform our sanity checks and then |
6e4930f6 CW |
1646 | * repeat the flush holding the lock in the normal manner to catch cases |
1647 | * where we are gazumped. | |
1648 | */ | |
b8f9096d | 1649 | ret = __unsafe_wait_rendering(obj, NULL, !write); |
6e4930f6 | 1650 | if (ret) |
b8f9096d CW |
1651 | goto err; |
1652 | ||
1653 | intel_runtime_pm_get(dev_priv); | |
1654 | ||
1655 | ret = i915_mutex_lock_interruptible(dev); | |
1656 | if (ret) | |
1657 | goto err_rpm; | |
6e4930f6 | 1658 | |
eb119bd6 CW |
1659 | /* Access to snoopable pages through the GTT is incoherent. */ |
1660 | if (obj->cache_level != I915_CACHE_NONE && !HAS_LLC(dev)) { | |
ddeff6ee | 1661 | ret = -EFAULT; |
b8f9096d | 1662 | goto err_unlock; |
eb119bd6 CW |
1663 | } |
1664 | ||
c5ad54cf | 1665 | /* Use a partial view if the object is bigger than the aperture. */ |
72e96d64 | 1666 | if (obj->base.size >= ggtt->mappable_end && |
e7ded2d7 | 1667 | obj->tiling_mode == I915_TILING_NONE) { |
c5ad54cf | 1668 | static const unsigned int chunk_size = 256; // 1 MiB |
e7ded2d7 | 1669 | |
c5ad54cf JL |
1670 | memset(&view, 0, sizeof(view)); |
1671 | view.type = I915_GGTT_VIEW_PARTIAL; | |
1672 | view.params.partial.offset = rounddown(page_offset, chunk_size); | |
1673 | view.params.partial.size = | |
1674 | min_t(unsigned int, | |
1675 | chunk_size, | |
1676 | (vma->vm_end - vma->vm_start)/PAGE_SIZE - | |
1677 | view.params.partial.offset); | |
1678 | } | |
1679 | ||
1680 | /* Now pin it into the GTT if needed */ | |
91b2db6f | 1681 | ret = i915_gem_object_ggtt_pin(obj, &view, 0, 0, PIN_MAPPABLE); |
c9839303 | 1682 | if (ret) |
b8f9096d | 1683 | goto err_unlock; |
4a684a41 | 1684 | |
c9839303 CW |
1685 | ret = i915_gem_object_set_to_gtt_domain(obj, write); |
1686 | if (ret) | |
b8f9096d | 1687 | goto err_unpin; |
74898d7e | 1688 | |
06d98131 | 1689 | ret = i915_gem_object_get_fence(obj); |
d9e86c0e | 1690 | if (ret) |
b8f9096d | 1691 | goto err_unpin; |
7d1c4804 | 1692 | |
b90b91d8 | 1693 | /* Finally, remap it using the new GTT offset */ |
72e96d64 | 1694 | pfn = ggtt->mappable_base + |
c5ad54cf | 1695 | i915_gem_obj_ggtt_offset_view(obj, &view); |
f343c5f6 | 1696 | pfn >>= PAGE_SHIFT; |
de151cf6 | 1697 | |
c5ad54cf JL |
1698 | if (unlikely(view.type == I915_GGTT_VIEW_PARTIAL)) { |
1699 | /* Overriding existing pages in partial view does not cause | |
1700 | * us any trouble as TLBs are still valid because the fault | |
1701 | * is due to userspace losing part of the mapping or never | |
1702 | * having accessed it before (at this partials' range). | |
1703 | */ | |
1704 | unsigned long base = vma->vm_start + | |
1705 | (view.params.partial.offset << PAGE_SHIFT); | |
1706 | unsigned int i; | |
b90b91d8 | 1707 | |
c5ad54cf JL |
1708 | for (i = 0; i < view.params.partial.size; i++) { |
1709 | ret = vm_insert_pfn(vma, base + i * PAGE_SIZE, pfn + i); | |
b90b91d8 CW |
1710 | if (ret) |
1711 | break; | |
1712 | } | |
1713 | ||
1714 | obj->fault_mappable = true; | |
c5ad54cf JL |
1715 | } else { |
1716 | if (!obj->fault_mappable) { | |
1717 | unsigned long size = min_t(unsigned long, | |
1718 | vma->vm_end - vma->vm_start, | |
1719 | obj->base.size); | |
1720 | int i; | |
1721 | ||
1722 | for (i = 0; i < size >> PAGE_SHIFT; i++) { | |
1723 | ret = vm_insert_pfn(vma, | |
1724 | (unsigned long)vma->vm_start + i * PAGE_SIZE, | |
1725 | pfn + i); | |
1726 | if (ret) | |
1727 | break; | |
1728 | } | |
1729 | ||
1730 | obj->fault_mappable = true; | |
1731 | } else | |
1732 | ret = vm_insert_pfn(vma, | |
1733 | (unsigned long)vmf->virtual_address, | |
1734 | pfn + page_offset); | |
1735 | } | |
b8f9096d | 1736 | err_unpin: |
c5ad54cf | 1737 | i915_gem_object_ggtt_unpin_view(obj, &view); |
b8f9096d | 1738 | err_unlock: |
de151cf6 | 1739 | mutex_unlock(&dev->struct_mutex); |
b8f9096d CW |
1740 | err_rpm: |
1741 | intel_runtime_pm_put(dev_priv); | |
1742 | err: | |
de151cf6 | 1743 | switch (ret) { |
d9bc7e9f | 1744 | case -EIO: |
2232f031 DV |
1745 | /* |
1746 | * We eat errors when the gpu is terminally wedged to avoid | |
1747 | * userspace unduly crashing (gl has no provisions for mmaps to | |
1748 | * fail). But any other -EIO isn't ours (e.g. swap in failure) | |
1749 | * and so needs to be reported. | |
1750 | */ | |
1751 | if (!i915_terminally_wedged(&dev_priv->gpu_error)) { | |
f65c9168 PZ |
1752 | ret = VM_FAULT_SIGBUS; |
1753 | break; | |
1754 | } | |
045e769a | 1755 | case -EAGAIN: |
571c608d DV |
1756 | /* |
1757 | * EAGAIN means the gpu is hung and we'll wait for the error | |
1758 | * handler to reset everything when re-faulting in | |
1759 | * i915_mutex_lock_interruptible. | |
d9bc7e9f | 1760 | */ |
c715089f CW |
1761 | case 0: |
1762 | case -ERESTARTSYS: | |
bed636ab | 1763 | case -EINTR: |
e79e0fe3 DR |
1764 | case -EBUSY: |
1765 | /* | |
1766 | * EBUSY is ok: this just means that another thread | |
1767 | * already did the job. | |
1768 | */ | |
f65c9168 PZ |
1769 | ret = VM_FAULT_NOPAGE; |
1770 | break; | |
de151cf6 | 1771 | case -ENOMEM: |
f65c9168 PZ |
1772 | ret = VM_FAULT_OOM; |
1773 | break; | |
a7c2e1aa | 1774 | case -ENOSPC: |
45d67817 | 1775 | case -EFAULT: |
f65c9168 PZ |
1776 | ret = VM_FAULT_SIGBUS; |
1777 | break; | |
de151cf6 | 1778 | default: |
a7c2e1aa | 1779 | WARN_ONCE(ret, "unhandled error in i915_gem_fault: %i\n", ret); |
f65c9168 PZ |
1780 | ret = VM_FAULT_SIGBUS; |
1781 | break; | |
de151cf6 | 1782 | } |
f65c9168 | 1783 | return ret; |
de151cf6 JB |
1784 | } |
1785 | ||
901782b2 CW |
1786 | /** |
1787 | * i915_gem_release_mmap - remove physical page mappings | |
1788 | * @obj: obj in question | |
1789 | * | |
af901ca1 | 1790 | * Preserve the reservation of the mmapping with the DRM core code, but |
901782b2 CW |
1791 | * relinquish ownership of the pages back to the system. |
1792 | * | |
1793 | * It is vital that we remove the page mapping if we have mapped a tiled | |
1794 | * object through the GTT and then lose the fence register due to | |
1795 | * resource pressure. Similarly if the object has been moved out of the | |
1796 | * aperture, than pages mapped into userspace must be revoked. Removing the | |
1797 | * mapping will then trigger a page fault on the next user access, allowing | |
1798 | * fixup by i915_gem_fault(). | |
1799 | */ | |
d05ca301 | 1800 | void |
05394f39 | 1801 | i915_gem_release_mmap(struct drm_i915_gem_object *obj) |
901782b2 | 1802 | { |
349f2ccf CW |
1803 | /* Serialisation between user GTT access and our code depends upon |
1804 | * revoking the CPU's PTE whilst the mutex is held. The next user | |
1805 | * pagefault then has to wait until we release the mutex. | |
1806 | */ | |
1807 | lockdep_assert_held(&obj->base.dev->struct_mutex); | |
1808 | ||
6299f992 CW |
1809 | if (!obj->fault_mappable) |
1810 | return; | |
901782b2 | 1811 | |
6796cb16 DH |
1812 | drm_vma_node_unmap(&obj->base.vma_node, |
1813 | obj->base.dev->anon_inode->i_mapping); | |
349f2ccf CW |
1814 | |
1815 | /* Ensure that the CPU's PTE are revoked and there are not outstanding | |
1816 | * memory transactions from userspace before we return. The TLB | |
1817 | * flushing implied above by changing the PTE above *should* be | |
1818 | * sufficient, an extra barrier here just provides us with a bit | |
1819 | * of paranoid documentation about our requirement to serialise | |
1820 | * memory writes before touching registers / GSM. | |
1821 | */ | |
1822 | wmb(); | |
1823 | ||
6299f992 | 1824 | obj->fault_mappable = false; |
901782b2 CW |
1825 | } |
1826 | ||
eedd10f4 CW |
1827 | void |
1828 | i915_gem_release_all_mmaps(struct drm_i915_private *dev_priv) | |
1829 | { | |
1830 | struct drm_i915_gem_object *obj; | |
1831 | ||
1832 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) | |
1833 | i915_gem_release_mmap(obj); | |
1834 | } | |
1835 | ||
ad1a7d20 CW |
1836 | /** |
1837 | * i915_gem_get_ggtt_size - return required global GTT size for an object | |
a9f1481f | 1838 | * @dev_priv: i915 device |
ad1a7d20 CW |
1839 | * @size: object size |
1840 | * @tiling_mode: tiling mode | |
1841 | * | |
1842 | * Return the required global GTT size for an object, taking into account | |
1843 | * potential fence register mapping. | |
1844 | */ | |
a9f1481f CW |
1845 | u64 i915_gem_get_ggtt_size(struct drm_i915_private *dev_priv, |
1846 | u64 size, int tiling_mode) | |
92b88aeb | 1847 | { |
ad1a7d20 | 1848 | u64 ggtt_size; |
92b88aeb | 1849 | |
ad1a7d20 CW |
1850 | GEM_BUG_ON(size == 0); |
1851 | ||
a9f1481f | 1852 | if (INTEL_GEN(dev_priv) >= 4 || |
e28f8711 CW |
1853 | tiling_mode == I915_TILING_NONE) |
1854 | return size; | |
92b88aeb CW |
1855 | |
1856 | /* Previous chips need a power-of-two fence region when tiling */ | |
a9f1481f | 1857 | if (IS_GEN3(dev_priv)) |
ad1a7d20 | 1858 | ggtt_size = 1024*1024; |
92b88aeb | 1859 | else |
ad1a7d20 | 1860 | ggtt_size = 512*1024; |
92b88aeb | 1861 | |
ad1a7d20 CW |
1862 | while (ggtt_size < size) |
1863 | ggtt_size <<= 1; | |
92b88aeb | 1864 | |
ad1a7d20 | 1865 | return ggtt_size; |
92b88aeb CW |
1866 | } |
1867 | ||
de151cf6 | 1868 | /** |
ad1a7d20 | 1869 | * i915_gem_get_ggtt_alignment - return required global GTT alignment |
a9f1481f | 1870 | * @dev_priv: i915 device |
14bb2c11 TU |
1871 | * @size: object size |
1872 | * @tiling_mode: tiling mode | |
ad1a7d20 | 1873 | * @fenced: is fenced alignment required or not |
de151cf6 | 1874 | * |
ad1a7d20 | 1875 | * Return the required global GTT alignment for an object, taking into account |
5e783301 | 1876 | * potential fence register mapping. |
de151cf6 | 1877 | */ |
a9f1481f | 1878 | u64 i915_gem_get_ggtt_alignment(struct drm_i915_private *dev_priv, u64 size, |
ad1a7d20 | 1879 | int tiling_mode, bool fenced) |
de151cf6 | 1880 | { |
ad1a7d20 CW |
1881 | GEM_BUG_ON(size == 0); |
1882 | ||
de151cf6 JB |
1883 | /* |
1884 | * Minimum alignment is 4k (GTT page size), but might be greater | |
1885 | * if a fence register is needed for the object. | |
1886 | */ | |
a9f1481f | 1887 | if (INTEL_GEN(dev_priv) >= 4 || (!fenced && IS_G33(dev_priv)) || |
e28f8711 | 1888 | tiling_mode == I915_TILING_NONE) |
de151cf6 JB |
1889 | return 4096; |
1890 | ||
a00b10c3 CW |
1891 | /* |
1892 | * Previous chips need to be aligned to the size of the smallest | |
1893 | * fence register that can contain the object. | |
1894 | */ | |
a9f1481f | 1895 | return i915_gem_get_ggtt_size(dev_priv, size, tiling_mode); |
a00b10c3 CW |
1896 | } |
1897 | ||
d8cb5086 CW |
1898 | static int i915_gem_object_create_mmap_offset(struct drm_i915_gem_object *obj) |
1899 | { | |
fac5e23e | 1900 | struct drm_i915_private *dev_priv = to_i915(obj->base.dev); |
f3f6184c | 1901 | int err; |
da494d7c | 1902 | |
f3f6184c CW |
1903 | err = drm_gem_create_mmap_offset(&obj->base); |
1904 | if (!err) | |
1905 | return 0; | |
d8cb5086 | 1906 | |
f3f6184c CW |
1907 | /* We can idle the GPU locklessly to flush stale objects, but in order |
1908 | * to claim that space for ourselves, we need to take the big | |
1909 | * struct_mutex to free the requests+objects and allocate our slot. | |
d8cb5086 | 1910 | */ |
f3f6184c CW |
1911 | err = i915_gem_wait_for_idle(dev_priv, true); |
1912 | if (err) | |
1913 | return err; | |
1914 | ||
1915 | err = i915_mutex_lock_interruptible(&dev_priv->drm); | |
1916 | if (!err) { | |
1917 | i915_gem_retire_requests(dev_priv); | |
1918 | err = drm_gem_create_mmap_offset(&obj->base); | |
1919 | mutex_unlock(&dev_priv->drm.struct_mutex); | |
1920 | } | |
da494d7c | 1921 | |
f3f6184c | 1922 | return err; |
d8cb5086 CW |
1923 | } |
1924 | ||
1925 | static void i915_gem_object_free_mmap_offset(struct drm_i915_gem_object *obj) | |
1926 | { | |
d8cb5086 CW |
1927 | drm_gem_free_mmap_offset(&obj->base); |
1928 | } | |
1929 | ||
da6b51d0 | 1930 | int |
ff72145b DA |
1931 | i915_gem_mmap_gtt(struct drm_file *file, |
1932 | struct drm_device *dev, | |
da6b51d0 | 1933 | uint32_t handle, |
ff72145b | 1934 | uint64_t *offset) |
de151cf6 | 1935 | { |
05394f39 | 1936 | struct drm_i915_gem_object *obj; |
de151cf6 JB |
1937 | int ret; |
1938 | ||
03ac0642 | 1939 | obj = i915_gem_object_lookup(file, handle); |
f3f6184c CW |
1940 | if (!obj) |
1941 | return -ENOENT; | |
ab18282d | 1942 | |
d8cb5086 | 1943 | ret = i915_gem_object_create_mmap_offset(obj); |
f3f6184c CW |
1944 | if (ret == 0) |
1945 | *offset = drm_vma_node_offset_addr(&obj->base.vma_node); | |
de151cf6 | 1946 | |
f3f6184c | 1947 | i915_gem_object_put_unlocked(obj); |
1d7cfea1 | 1948 | return ret; |
de151cf6 JB |
1949 | } |
1950 | ||
ff72145b DA |
1951 | /** |
1952 | * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing | |
1953 | * @dev: DRM device | |
1954 | * @data: GTT mapping ioctl data | |
1955 | * @file: GEM object info | |
1956 | * | |
1957 | * Simply returns the fake offset to userspace so it can mmap it. | |
1958 | * The mmap call will end up in drm_gem_mmap(), which will set things | |
1959 | * up so we can get faults in the handler above. | |
1960 | * | |
1961 | * The fault handler will take care of binding the object into the GTT | |
1962 | * (since it may have been evicted to make room for something), allocating | |
1963 | * a fence register, and mapping the appropriate aperture address into | |
1964 | * userspace. | |
1965 | */ | |
1966 | int | |
1967 | i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data, | |
1968 | struct drm_file *file) | |
1969 | { | |
1970 | struct drm_i915_gem_mmap_gtt *args = data; | |
1971 | ||
da6b51d0 | 1972 | return i915_gem_mmap_gtt(file, dev, args->handle, &args->offset); |
ff72145b DA |
1973 | } |
1974 | ||
225067ee DV |
1975 | /* Immediately discard the backing storage */ |
1976 | static void | |
1977 | i915_gem_object_truncate(struct drm_i915_gem_object *obj) | |
e5281ccd | 1978 | { |
4d6294bf | 1979 | i915_gem_object_free_mmap_offset(obj); |
1286ff73 | 1980 | |
4d6294bf CW |
1981 | if (obj->base.filp == NULL) |
1982 | return; | |
e5281ccd | 1983 | |
225067ee DV |
1984 | /* Our goal here is to return as much of the memory as |
1985 | * is possible back to the system as we are called from OOM. | |
1986 | * To do this we must instruct the shmfs to drop all of its | |
1987 | * backing pages, *now*. | |
1988 | */ | |
5537252b | 1989 | shmem_truncate_range(file_inode(obj->base.filp), 0, (loff_t)-1); |
225067ee DV |
1990 | obj->madv = __I915_MADV_PURGED; |
1991 | } | |
e5281ccd | 1992 | |
5537252b CW |
1993 | /* Try to discard unwanted pages */ |
1994 | static void | |
1995 | i915_gem_object_invalidate(struct drm_i915_gem_object *obj) | |
225067ee | 1996 | { |
5537252b CW |
1997 | struct address_space *mapping; |
1998 | ||
1999 | switch (obj->madv) { | |
2000 | case I915_MADV_DONTNEED: | |
2001 | i915_gem_object_truncate(obj); | |
2002 | case __I915_MADV_PURGED: | |
2003 | return; | |
2004 | } | |
2005 | ||
2006 | if (obj->base.filp == NULL) | |
2007 | return; | |
2008 | ||
2009 | mapping = file_inode(obj->base.filp)->i_mapping, | |
2010 | invalidate_mapping_pages(mapping, 0, (loff_t)-1); | |
e5281ccd CW |
2011 | } |
2012 | ||
5cdf5881 | 2013 | static void |
05394f39 | 2014 | i915_gem_object_put_pages_gtt(struct drm_i915_gem_object *obj) |
673a394b | 2015 | { |
85d1225e DG |
2016 | struct sgt_iter sgt_iter; |
2017 | struct page *page; | |
90797e6d | 2018 | int ret; |
1286ff73 | 2019 | |
05394f39 | 2020 | BUG_ON(obj->madv == __I915_MADV_PURGED); |
673a394b | 2021 | |
6c085a72 | 2022 | ret = i915_gem_object_set_to_cpu_domain(obj, true); |
f4457ae7 | 2023 | if (WARN_ON(ret)) { |
6c085a72 CW |
2024 | /* In the event of a disaster, abandon all caches and |
2025 | * hope for the best. | |
2026 | */ | |
2c22569b | 2027 | i915_gem_clflush_object(obj, true); |
6c085a72 CW |
2028 | obj->base.read_domains = obj->base.write_domain = I915_GEM_DOMAIN_CPU; |
2029 | } | |
2030 | ||
e2273302 ID |
2031 | i915_gem_gtt_finish_object(obj); |
2032 | ||
6dacfd2f | 2033 | if (i915_gem_object_needs_bit17_swizzle(obj)) |
280b713b EA |
2034 | i915_gem_object_save_bit_17_swizzle(obj); |
2035 | ||
05394f39 CW |
2036 | if (obj->madv == I915_MADV_DONTNEED) |
2037 | obj->dirty = 0; | |
3ef94daa | 2038 | |
85d1225e | 2039 | for_each_sgt_page(page, sgt_iter, obj->pages) { |
05394f39 | 2040 | if (obj->dirty) |
9da3da66 | 2041 | set_page_dirty(page); |
3ef94daa | 2042 | |
05394f39 | 2043 | if (obj->madv == I915_MADV_WILLNEED) |
9da3da66 | 2044 | mark_page_accessed(page); |
3ef94daa | 2045 | |
09cbfeaf | 2046 | put_page(page); |
3ef94daa | 2047 | } |
05394f39 | 2048 | obj->dirty = 0; |
673a394b | 2049 | |
9da3da66 CW |
2050 | sg_free_table(obj->pages); |
2051 | kfree(obj->pages); | |
37e680a1 | 2052 | } |
6c085a72 | 2053 | |
dd624afd | 2054 | int |
37e680a1 CW |
2055 | i915_gem_object_put_pages(struct drm_i915_gem_object *obj) |
2056 | { | |
2057 | const struct drm_i915_gem_object_ops *ops = obj->ops; | |
2058 | ||
2f745ad3 | 2059 | if (obj->pages == NULL) |
37e680a1 CW |
2060 | return 0; |
2061 | ||
a5570178 CW |
2062 | if (obj->pages_pin_count) |
2063 | return -EBUSY; | |
2064 | ||
15717de2 | 2065 | GEM_BUG_ON(obj->bind_count); |
3e123027 | 2066 | |
a2165e31 CW |
2067 | /* ->put_pages might need to allocate memory for the bit17 swizzle |
2068 | * array, hence protect them from being reaped by removing them from gtt | |
2069 | * lists early. */ | |
35c20a60 | 2070 | list_del(&obj->global_list); |
a2165e31 | 2071 | |
0a798eb9 | 2072 | if (obj->mapping) { |
fb8621d3 CW |
2073 | if (is_vmalloc_addr(obj->mapping)) |
2074 | vunmap(obj->mapping); | |
2075 | else | |
2076 | kunmap(kmap_to_page(obj->mapping)); | |
0a798eb9 CW |
2077 | obj->mapping = NULL; |
2078 | } | |
2079 | ||
37e680a1 | 2080 | ops->put_pages(obj); |
05394f39 | 2081 | obj->pages = NULL; |
37e680a1 | 2082 | |
5537252b | 2083 | i915_gem_object_invalidate(obj); |
6c085a72 CW |
2084 | |
2085 | return 0; | |
2086 | } | |
2087 | ||
37e680a1 | 2088 | static int |
6c085a72 | 2089 | i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj) |
e5281ccd | 2090 | { |
fac5e23e | 2091 | struct drm_i915_private *dev_priv = to_i915(obj->base.dev); |
e5281ccd CW |
2092 | int page_count, i; |
2093 | struct address_space *mapping; | |
9da3da66 CW |
2094 | struct sg_table *st; |
2095 | struct scatterlist *sg; | |
85d1225e | 2096 | struct sgt_iter sgt_iter; |
e5281ccd | 2097 | struct page *page; |
90797e6d | 2098 | unsigned long last_pfn = 0; /* suppress gcc warning */ |
e2273302 | 2099 | int ret; |
6c085a72 | 2100 | gfp_t gfp; |
e5281ccd | 2101 | |
6c085a72 CW |
2102 | /* Assert that the object is not currently in any GPU domain. As it |
2103 | * wasn't in the GTT, there shouldn't be any way it could have been in | |
2104 | * a GPU cache | |
2105 | */ | |
2106 | BUG_ON(obj->base.read_domains & I915_GEM_GPU_DOMAINS); | |
2107 | BUG_ON(obj->base.write_domain & I915_GEM_GPU_DOMAINS); | |
2108 | ||
9da3da66 CW |
2109 | st = kmalloc(sizeof(*st), GFP_KERNEL); |
2110 | if (st == NULL) | |
2111 | return -ENOMEM; | |
2112 | ||
05394f39 | 2113 | page_count = obj->base.size / PAGE_SIZE; |
9da3da66 | 2114 | if (sg_alloc_table(st, page_count, GFP_KERNEL)) { |
9da3da66 | 2115 | kfree(st); |
e5281ccd | 2116 | return -ENOMEM; |
9da3da66 | 2117 | } |
e5281ccd | 2118 | |
9da3da66 CW |
2119 | /* Get the list of pages out of our struct file. They'll be pinned |
2120 | * at this point until we release them. | |
2121 | * | |
2122 | * Fail silently without starting the shrinker | |
2123 | */ | |
496ad9aa | 2124 | mapping = file_inode(obj->base.filp)->i_mapping; |
c62d2555 | 2125 | gfp = mapping_gfp_constraint(mapping, ~(__GFP_IO | __GFP_RECLAIM)); |
d0164adc | 2126 | gfp |= __GFP_NORETRY | __GFP_NOWARN; |
90797e6d ID |
2127 | sg = st->sgl; |
2128 | st->nents = 0; | |
2129 | for (i = 0; i < page_count; i++) { | |
6c085a72 CW |
2130 | page = shmem_read_mapping_page_gfp(mapping, i, gfp); |
2131 | if (IS_ERR(page)) { | |
21ab4e74 CW |
2132 | i915_gem_shrink(dev_priv, |
2133 | page_count, | |
2134 | I915_SHRINK_BOUND | | |
2135 | I915_SHRINK_UNBOUND | | |
2136 | I915_SHRINK_PURGEABLE); | |
6c085a72 CW |
2137 | page = shmem_read_mapping_page_gfp(mapping, i, gfp); |
2138 | } | |
2139 | if (IS_ERR(page)) { | |
2140 | /* We've tried hard to allocate the memory by reaping | |
2141 | * our own buffer, now let the real VM do its job and | |
2142 | * go down in flames if truly OOM. | |
2143 | */ | |
6c085a72 | 2144 | i915_gem_shrink_all(dev_priv); |
f461d1be | 2145 | page = shmem_read_mapping_page(mapping, i); |
e2273302 ID |
2146 | if (IS_ERR(page)) { |
2147 | ret = PTR_ERR(page); | |
6c085a72 | 2148 | goto err_pages; |
e2273302 | 2149 | } |
6c085a72 | 2150 | } |
426729dc KRW |
2151 | #ifdef CONFIG_SWIOTLB |
2152 | if (swiotlb_nr_tbl()) { | |
2153 | st->nents++; | |
2154 | sg_set_page(sg, page, PAGE_SIZE, 0); | |
2155 | sg = sg_next(sg); | |
2156 | continue; | |
2157 | } | |
2158 | #endif | |
90797e6d ID |
2159 | if (!i || page_to_pfn(page) != last_pfn + 1) { |
2160 | if (i) | |
2161 | sg = sg_next(sg); | |
2162 | st->nents++; | |
2163 | sg_set_page(sg, page, PAGE_SIZE, 0); | |
2164 | } else { | |
2165 | sg->length += PAGE_SIZE; | |
2166 | } | |
2167 | last_pfn = page_to_pfn(page); | |
3bbbe706 DV |
2168 | |
2169 | /* Check that the i965g/gm workaround works. */ | |
2170 | WARN_ON((gfp & __GFP_DMA32) && (last_pfn >= 0x00100000UL)); | |
e5281ccd | 2171 | } |
426729dc KRW |
2172 | #ifdef CONFIG_SWIOTLB |
2173 | if (!swiotlb_nr_tbl()) | |
2174 | #endif | |
2175 | sg_mark_end(sg); | |
74ce6b6c CW |
2176 | obj->pages = st; |
2177 | ||
e2273302 ID |
2178 | ret = i915_gem_gtt_prepare_object(obj); |
2179 | if (ret) | |
2180 | goto err_pages; | |
2181 | ||
6dacfd2f | 2182 | if (i915_gem_object_needs_bit17_swizzle(obj)) |
e5281ccd CW |
2183 | i915_gem_object_do_bit_17_swizzle(obj); |
2184 | ||
656bfa3a DV |
2185 | if (obj->tiling_mode != I915_TILING_NONE && |
2186 | dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES) | |
2187 | i915_gem_object_pin_pages(obj); | |
2188 | ||
e5281ccd CW |
2189 | return 0; |
2190 | ||
2191 | err_pages: | |
90797e6d | 2192 | sg_mark_end(sg); |
85d1225e DG |
2193 | for_each_sgt_page(page, sgt_iter, st) |
2194 | put_page(page); | |
9da3da66 CW |
2195 | sg_free_table(st); |
2196 | kfree(st); | |
0820baf3 CW |
2197 | |
2198 | /* shmemfs first checks if there is enough memory to allocate the page | |
2199 | * and reports ENOSPC should there be insufficient, along with the usual | |
2200 | * ENOMEM for a genuine allocation failure. | |
2201 | * | |
2202 | * We use ENOSPC in our driver to mean that we have run out of aperture | |
2203 | * space and so want to translate the error from shmemfs back to our | |
2204 | * usual understanding of ENOMEM. | |
2205 | */ | |
e2273302 ID |
2206 | if (ret == -ENOSPC) |
2207 | ret = -ENOMEM; | |
2208 | ||
2209 | return ret; | |
673a394b EA |
2210 | } |
2211 | ||
37e680a1 CW |
2212 | /* Ensure that the associated pages are gathered from the backing storage |
2213 | * and pinned into our object. i915_gem_object_get_pages() may be called | |
2214 | * multiple times before they are released by a single call to | |
2215 | * i915_gem_object_put_pages() - once the pages are no longer referenced | |
2216 | * either as a result of memory pressure (reaping pages under the shrinker) | |
2217 | * or as the object is itself released. | |
2218 | */ | |
2219 | int | |
2220 | i915_gem_object_get_pages(struct drm_i915_gem_object *obj) | |
2221 | { | |
fac5e23e | 2222 | struct drm_i915_private *dev_priv = to_i915(obj->base.dev); |
37e680a1 CW |
2223 | const struct drm_i915_gem_object_ops *ops = obj->ops; |
2224 | int ret; | |
2225 | ||
2f745ad3 | 2226 | if (obj->pages) |
37e680a1 CW |
2227 | return 0; |
2228 | ||
43e28f09 | 2229 | if (obj->madv != I915_MADV_WILLNEED) { |
bd9b6a4e | 2230 | DRM_DEBUG("Attempting to obtain a purgeable object\n"); |
8c99e57d | 2231 | return -EFAULT; |
43e28f09 CW |
2232 | } |
2233 | ||
a5570178 CW |
2234 | BUG_ON(obj->pages_pin_count); |
2235 | ||
37e680a1 CW |
2236 | ret = ops->get_pages(obj); |
2237 | if (ret) | |
2238 | return ret; | |
2239 | ||
35c20a60 | 2240 | list_add_tail(&obj->global_list, &dev_priv->mm.unbound_list); |
ee286370 CW |
2241 | |
2242 | obj->get_page.sg = obj->pages->sgl; | |
2243 | obj->get_page.last = 0; | |
2244 | ||
37e680a1 | 2245 | return 0; |
673a394b EA |
2246 | } |
2247 | ||
dd6034c6 DG |
2248 | /* The 'mapping' part of i915_gem_object_pin_map() below */ |
2249 | static void *i915_gem_object_map(const struct drm_i915_gem_object *obj) | |
2250 | { | |
2251 | unsigned long n_pages = obj->base.size >> PAGE_SHIFT; | |
2252 | struct sg_table *sgt = obj->pages; | |
85d1225e DG |
2253 | struct sgt_iter sgt_iter; |
2254 | struct page *page; | |
b338fa47 DG |
2255 | struct page *stack_pages[32]; |
2256 | struct page **pages = stack_pages; | |
dd6034c6 DG |
2257 | unsigned long i = 0; |
2258 | void *addr; | |
2259 | ||
2260 | /* A single page can always be kmapped */ | |
2261 | if (n_pages == 1) | |
2262 | return kmap(sg_page(sgt->sgl)); | |
2263 | ||
b338fa47 DG |
2264 | if (n_pages > ARRAY_SIZE(stack_pages)) { |
2265 | /* Too big for stack -- allocate temporary array instead */ | |
2266 | pages = drm_malloc_gfp(n_pages, sizeof(*pages), GFP_TEMPORARY); | |
2267 | if (!pages) | |
2268 | return NULL; | |
2269 | } | |
dd6034c6 | 2270 | |
85d1225e DG |
2271 | for_each_sgt_page(page, sgt_iter, sgt) |
2272 | pages[i++] = page; | |
dd6034c6 DG |
2273 | |
2274 | /* Check that we have the expected number of pages */ | |
2275 | GEM_BUG_ON(i != n_pages); | |
2276 | ||
2277 | addr = vmap(pages, n_pages, 0, PAGE_KERNEL); | |
2278 | ||
b338fa47 DG |
2279 | if (pages != stack_pages) |
2280 | drm_free_large(pages); | |
dd6034c6 DG |
2281 | |
2282 | return addr; | |
2283 | } | |
2284 | ||
2285 | /* get, pin, and map the pages of the object into kernel space */ | |
0a798eb9 CW |
2286 | void *i915_gem_object_pin_map(struct drm_i915_gem_object *obj) |
2287 | { | |
2288 | int ret; | |
2289 | ||
2290 | lockdep_assert_held(&obj->base.dev->struct_mutex); | |
2291 | ||
2292 | ret = i915_gem_object_get_pages(obj); | |
2293 | if (ret) | |
2294 | return ERR_PTR(ret); | |
2295 | ||
2296 | i915_gem_object_pin_pages(obj); | |
2297 | ||
dd6034c6 DG |
2298 | if (!obj->mapping) { |
2299 | obj->mapping = i915_gem_object_map(obj); | |
2300 | if (!obj->mapping) { | |
0a798eb9 CW |
2301 | i915_gem_object_unpin_pages(obj); |
2302 | return ERR_PTR(-ENOMEM); | |
2303 | } | |
2304 | } | |
2305 | ||
2306 | return obj->mapping; | |
2307 | } | |
2308 | ||
b4716185 | 2309 | static void |
fa545cbf CW |
2310 | i915_gem_object_retire__write(struct i915_gem_active *active, |
2311 | struct drm_i915_gem_request *request) | |
e2d05a8b | 2312 | { |
fa545cbf CW |
2313 | struct drm_i915_gem_object *obj = |
2314 | container_of(active, struct drm_i915_gem_object, last_write); | |
b4716185 | 2315 | |
de152b62 | 2316 | intel_fb_obj_flush(obj, true, ORIGIN_CS); |
e2d05a8b BW |
2317 | } |
2318 | ||
caea7476 | 2319 | static void |
fa545cbf CW |
2320 | i915_gem_object_retire__read(struct i915_gem_active *active, |
2321 | struct drm_i915_gem_request *request) | |
ce44b0ea | 2322 | { |
fa545cbf CW |
2323 | int idx = request->engine->id; |
2324 | struct drm_i915_gem_object *obj = | |
2325 | container_of(active, struct drm_i915_gem_object, last_read[idx]); | |
ce44b0ea | 2326 | |
573adb39 | 2327 | GEM_BUG_ON(!i915_gem_object_has_active_engine(obj, idx)); |
b4716185 | 2328 | |
573adb39 CW |
2329 | i915_gem_object_clear_active(obj, idx); |
2330 | if (i915_gem_object_is_active(obj)) | |
b4716185 | 2331 | return; |
caea7476 | 2332 | |
6c246959 CW |
2333 | /* Bump our place on the bound list to keep it roughly in LRU order |
2334 | * so that we don't steal from recently used but inactive objects | |
2335 | * (unless we are forced to ofc!) | |
2336 | */ | |
b0decaf7 CW |
2337 | if (obj->bind_count) |
2338 | list_move_tail(&obj->global_list, | |
2339 | &request->i915->mm.bound_list); | |
caea7476 | 2340 | |
f8c417cd | 2341 | i915_gem_object_put(obj); |
c8725f3d CW |
2342 | } |
2343 | ||
7b4d3a16 | 2344 | static bool i915_context_is_banned(const struct i915_gem_context *ctx) |
be62acb4 | 2345 | { |
44e2c070 | 2346 | unsigned long elapsed; |
be62acb4 | 2347 | |
44e2c070 | 2348 | if (ctx->hang_stats.banned) |
be62acb4 MK |
2349 | return true; |
2350 | ||
7b4d3a16 | 2351 | elapsed = get_seconds() - ctx->hang_stats.guilty_ts; |
676fa572 CW |
2352 | if (ctx->hang_stats.ban_period_seconds && |
2353 | elapsed <= ctx->hang_stats.ban_period_seconds) { | |
7b4d3a16 CW |
2354 | DRM_DEBUG("context hanging too fast, banning!\n"); |
2355 | return true; | |
be62acb4 MK |
2356 | } |
2357 | ||
2358 | return false; | |
2359 | } | |
2360 | ||
7b4d3a16 | 2361 | static void i915_set_reset_status(struct i915_gem_context *ctx, |
b6b0fac0 | 2362 | const bool guilty) |
aa60c664 | 2363 | { |
7b4d3a16 | 2364 | struct i915_ctx_hang_stats *hs = &ctx->hang_stats; |
44e2c070 MK |
2365 | |
2366 | if (guilty) { | |
7b4d3a16 | 2367 | hs->banned = i915_context_is_banned(ctx); |
44e2c070 MK |
2368 | hs->batch_active++; |
2369 | hs->guilty_ts = get_seconds(); | |
2370 | } else { | |
2371 | hs->batch_pending++; | |
aa60c664 MK |
2372 | } |
2373 | } | |
2374 | ||
8d9fc7fd | 2375 | struct drm_i915_gem_request * |
0bc40be8 | 2376 | i915_gem_find_active_request(struct intel_engine_cs *engine) |
9375e446 | 2377 | { |
4db080f9 CW |
2378 | struct drm_i915_gem_request *request; |
2379 | ||
f69a02c9 CW |
2380 | /* We are called by the error capture and reset at a random |
2381 | * point in time. In particular, note that neither is crucially | |
2382 | * ordered with an interrupt. After a hang, the GPU is dead and we | |
2383 | * assume that no more writes can happen (we waited long enough for | |
2384 | * all writes that were in transaction to be flushed) - adding an | |
2385 | * extra delay for a recent interrupt is pointless. Hence, we do | |
2386 | * not need an engine->irq_seqno_barrier() before the seqno reads. | |
2387 | */ | |
efdf7c06 | 2388 | list_for_each_entry(request, &engine->request_list, link) { |
f69a02c9 | 2389 | if (i915_gem_request_completed(request)) |
4db080f9 | 2390 | continue; |
aa60c664 | 2391 | |
b6b0fac0 | 2392 | return request; |
4db080f9 | 2393 | } |
b6b0fac0 MK |
2394 | |
2395 | return NULL; | |
2396 | } | |
2397 | ||
7b4d3a16 | 2398 | static void i915_gem_reset_engine_status(struct intel_engine_cs *engine) |
b6b0fac0 MK |
2399 | { |
2400 | struct drm_i915_gem_request *request; | |
2401 | bool ring_hung; | |
2402 | ||
0bc40be8 | 2403 | request = i915_gem_find_active_request(engine); |
b6b0fac0 MK |
2404 | if (request == NULL) |
2405 | return; | |
2406 | ||
0bc40be8 | 2407 | ring_hung = engine->hangcheck.score >= HANGCHECK_SCORE_RING_HUNG; |
b6b0fac0 | 2408 | |
7b4d3a16 | 2409 | i915_set_reset_status(request->ctx, ring_hung); |
efdf7c06 | 2410 | list_for_each_entry_continue(request, &engine->request_list, link) |
7b4d3a16 | 2411 | i915_set_reset_status(request->ctx, false); |
4db080f9 | 2412 | } |
aa60c664 | 2413 | |
7b4d3a16 | 2414 | static void i915_gem_reset_engine_cleanup(struct intel_engine_cs *engine) |
4db080f9 | 2415 | { |
dcff85c8 | 2416 | struct drm_i915_gem_request *request; |
7e37f889 | 2417 | struct intel_ring *ring; |
608c1a52 | 2418 | |
dcff85c8 CW |
2419 | request = i915_gem_active_peek(&engine->last_request, |
2420 | &engine->i915->drm.struct_mutex); | |
2421 | ||
c4b0930b CW |
2422 | /* Mark all pending requests as complete so that any concurrent |
2423 | * (lockless) lookup doesn't try and wait upon the request as we | |
2424 | * reset it. | |
2425 | */ | |
dcff85c8 CW |
2426 | if (request) |
2427 | intel_engine_init_seqno(engine, request->fence.seqno); | |
c4b0930b | 2428 | |
dcb4c12a OM |
2429 | /* |
2430 | * Clear the execlists queue up before freeing the requests, as those | |
2431 | * are the ones that keep the context and ringbuffer backing objects | |
2432 | * pinned in place. | |
2433 | */ | |
dcb4c12a | 2434 | |
7de1691a | 2435 | if (i915.enable_execlists) { |
27af5eea TU |
2436 | /* Ensure irq handler finishes or is cancelled. */ |
2437 | tasklet_kill(&engine->irq_tasklet); | |
1197b4f2 | 2438 | |
e39d42fa | 2439 | intel_execlists_cancel_requests(engine); |
dcb4c12a OM |
2440 | } |
2441 | ||
1d62beea BW |
2442 | /* |
2443 | * We must free the requests after all the corresponding objects have | |
2444 | * been moved off active lists. Which is the same order as the normal | |
2445 | * retire_requests function does. This is important if object hold | |
2446 | * implicit references on things like e.g. ppgtt address spaces through | |
2447 | * the request. | |
2448 | */ | |
dcff85c8 | 2449 | if (request) |
05235c53 | 2450 | i915_gem_request_retire_upto(request); |
dcff85c8 | 2451 | GEM_BUG_ON(intel_engine_is_active(engine)); |
608c1a52 CW |
2452 | |
2453 | /* Having flushed all requests from all queues, we know that all | |
2454 | * ringbuffers must now be empty. However, since we do not reclaim | |
2455 | * all space when retiring the request (to prevent HEADs colliding | |
2456 | * with rapid ringbuffer wraparound) the amount of available space | |
2457 | * upon reset is less than when we start. Do one more pass over | |
2458 | * all the ringbuffers to reset last_retired_head. | |
2459 | */ | |
7e37f889 CW |
2460 | list_for_each_entry(ring, &engine->buffers, link) { |
2461 | ring->last_retired_head = ring->tail; | |
2462 | intel_ring_update_space(ring); | |
608c1a52 | 2463 | } |
2ed53a94 | 2464 | |
b913b33c | 2465 | engine->i915->gt.active_engines &= ~intel_engine_flag(engine); |
673a394b EA |
2466 | } |
2467 | ||
069efc1d | 2468 | void i915_gem_reset(struct drm_device *dev) |
673a394b | 2469 | { |
fac5e23e | 2470 | struct drm_i915_private *dev_priv = to_i915(dev); |
e2f80391 | 2471 | struct intel_engine_cs *engine; |
673a394b | 2472 | |
4db080f9 CW |
2473 | /* |
2474 | * Before we free the objects from the requests, we need to inspect | |
2475 | * them for finding the guilty party. As the requests only borrow | |
2476 | * their reference to the objects, the inspection must be done first. | |
2477 | */ | |
b4ac5afc | 2478 | for_each_engine(engine, dev_priv) |
7b4d3a16 | 2479 | i915_gem_reset_engine_status(engine); |
4db080f9 | 2480 | |
b4ac5afc | 2481 | for_each_engine(engine, dev_priv) |
7b4d3a16 | 2482 | i915_gem_reset_engine_cleanup(engine); |
b913b33c | 2483 | mod_delayed_work(dev_priv->wq, &dev_priv->gt.idle_work, 0); |
dfaae392 | 2484 | |
acce9ffa BW |
2485 | i915_gem_context_reset(dev); |
2486 | ||
19b2dbde | 2487 | i915_gem_restore_fences(dev); |
673a394b EA |
2488 | } |
2489 | ||
75ef9da2 | 2490 | static void |
673a394b EA |
2491 | i915_gem_retire_work_handler(struct work_struct *work) |
2492 | { | |
b29c19b6 | 2493 | struct drm_i915_private *dev_priv = |
67d97da3 | 2494 | container_of(work, typeof(*dev_priv), gt.retire_work.work); |
91c8a326 | 2495 | struct drm_device *dev = &dev_priv->drm; |
673a394b | 2496 | |
891b48cf | 2497 | /* Come back later if the device is busy... */ |
b29c19b6 | 2498 | if (mutex_trylock(&dev->struct_mutex)) { |
67d97da3 | 2499 | i915_gem_retire_requests(dev_priv); |
b29c19b6 | 2500 | mutex_unlock(&dev->struct_mutex); |
673a394b | 2501 | } |
67d97da3 CW |
2502 | |
2503 | /* Keep the retire handler running until we are finally idle. | |
2504 | * We do not need to do this test under locking as in the worst-case | |
2505 | * we queue the retire worker once too often. | |
2506 | */ | |
c9615613 CW |
2507 | if (READ_ONCE(dev_priv->gt.awake)) { |
2508 | i915_queue_hangcheck(dev_priv); | |
67d97da3 CW |
2509 | queue_delayed_work(dev_priv->wq, |
2510 | &dev_priv->gt.retire_work, | |
bcb45086 | 2511 | round_jiffies_up_relative(HZ)); |
c9615613 | 2512 | } |
b29c19b6 | 2513 | } |
0a58705b | 2514 | |
b29c19b6 CW |
2515 | static void |
2516 | i915_gem_idle_work_handler(struct work_struct *work) | |
2517 | { | |
2518 | struct drm_i915_private *dev_priv = | |
67d97da3 | 2519 | container_of(work, typeof(*dev_priv), gt.idle_work.work); |
91c8a326 | 2520 | struct drm_device *dev = &dev_priv->drm; |
b4ac5afc | 2521 | struct intel_engine_cs *engine; |
67d97da3 CW |
2522 | unsigned int stuck_engines; |
2523 | bool rearm_hangcheck; | |
2524 | ||
2525 | if (!READ_ONCE(dev_priv->gt.awake)) | |
2526 | return; | |
2527 | ||
2528 | if (READ_ONCE(dev_priv->gt.active_engines)) | |
2529 | return; | |
2530 | ||
2531 | rearm_hangcheck = | |
2532 | cancel_delayed_work_sync(&dev_priv->gpu_error.hangcheck_work); | |
2533 | ||
2534 | if (!mutex_trylock(&dev->struct_mutex)) { | |
2535 | /* Currently busy, come back later */ | |
2536 | mod_delayed_work(dev_priv->wq, | |
2537 | &dev_priv->gt.idle_work, | |
2538 | msecs_to_jiffies(50)); | |
2539 | goto out_rearm; | |
2540 | } | |
2541 | ||
2542 | if (dev_priv->gt.active_engines) | |
2543 | goto out_unlock; | |
b29c19b6 | 2544 | |
b4ac5afc | 2545 | for_each_engine(engine, dev_priv) |
67d97da3 | 2546 | i915_gem_batch_pool_fini(&engine->batch_pool); |
35c94185 | 2547 | |
67d97da3 CW |
2548 | GEM_BUG_ON(!dev_priv->gt.awake); |
2549 | dev_priv->gt.awake = false; | |
2550 | rearm_hangcheck = false; | |
30ecad77 | 2551 | |
2529d570 CW |
2552 | /* As we have disabled hangcheck, we need to unstick any waiters still |
2553 | * hanging around. However, as we may be racing against the interrupt | |
2554 | * handler or the waiters themselves, we skip enabling the fake-irq. | |
2555 | */ | |
67d97da3 | 2556 | stuck_engines = intel_kick_waiters(dev_priv); |
2529d570 CW |
2557 | if (unlikely(stuck_engines)) |
2558 | DRM_DEBUG_DRIVER("kicked stuck waiters (%x)...missed irq?\n", | |
2559 | stuck_engines); | |
35c94185 | 2560 | |
67d97da3 CW |
2561 | if (INTEL_GEN(dev_priv) >= 6) |
2562 | gen6_rps_idle(dev_priv); | |
2563 | intel_runtime_pm_put(dev_priv); | |
2564 | out_unlock: | |
2565 | mutex_unlock(&dev->struct_mutex); | |
b29c19b6 | 2566 | |
67d97da3 CW |
2567 | out_rearm: |
2568 | if (rearm_hangcheck) { | |
2569 | GEM_BUG_ON(!dev_priv->gt.awake); | |
2570 | i915_queue_hangcheck(dev_priv); | |
35c94185 | 2571 | } |
673a394b EA |
2572 | } |
2573 | ||
b1f788c6 CW |
2574 | void i915_gem_close_object(struct drm_gem_object *gem, struct drm_file *file) |
2575 | { | |
2576 | struct drm_i915_gem_object *obj = to_intel_bo(gem); | |
2577 | struct drm_i915_file_private *fpriv = file->driver_priv; | |
2578 | struct i915_vma *vma, *vn; | |
2579 | ||
2580 | mutex_lock(&obj->base.dev->struct_mutex); | |
2581 | list_for_each_entry_safe(vma, vn, &obj->vma_list, obj_link) | |
2582 | if (vma->vm->file == fpriv) | |
2583 | i915_vma_close(vma); | |
2584 | mutex_unlock(&obj->base.dev->struct_mutex); | |
2585 | } | |
2586 | ||
23ba4fd0 BW |
2587 | /** |
2588 | * i915_gem_wait_ioctl - implements DRM_IOCTL_I915_GEM_WAIT | |
14bb2c11 TU |
2589 | * @dev: drm device pointer |
2590 | * @data: ioctl data blob | |
2591 | * @file: drm file pointer | |
23ba4fd0 BW |
2592 | * |
2593 | * Returns 0 if successful, else an error is returned with the remaining time in | |
2594 | * the timeout parameter. | |
2595 | * -ETIME: object is still busy after timeout | |
2596 | * -ERESTARTSYS: signal interrupted the wait | |
2597 | * -ENONENT: object doesn't exist | |
2598 | * Also possible, but rare: | |
2599 | * -EAGAIN: GPU wedged | |
2600 | * -ENOMEM: damn | |
2601 | * -ENODEV: Internal IRQ fail | |
2602 | * -E?: The add request failed | |
2603 | * | |
2604 | * The wait ioctl with a timeout of 0 reimplements the busy ioctl. With any | |
2605 | * non-zero timeout parameter the wait ioctl will wait for the given number of | |
2606 | * nanoseconds on an object becoming unbusy. Since the wait itself does so | |
2607 | * without holding struct_mutex the object may become re-busied before this | |
2608 | * function completes. A similar but shorter * race condition exists in the busy | |
2609 | * ioctl | |
2610 | */ | |
2611 | int | |
2612 | i915_gem_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *file) | |
2613 | { | |
2614 | struct drm_i915_gem_wait *args = data; | |
2615 | struct drm_i915_gem_object *obj; | |
27c01aae | 2616 | struct drm_i915_gem_request *requests[I915_NUM_ENGINES]; |
b4716185 CW |
2617 | int i, n = 0; |
2618 | int ret; | |
23ba4fd0 | 2619 | |
11b5d511 DV |
2620 | if (args->flags != 0) |
2621 | return -EINVAL; | |
2622 | ||
23ba4fd0 BW |
2623 | ret = i915_mutex_lock_interruptible(dev); |
2624 | if (ret) | |
2625 | return ret; | |
2626 | ||
03ac0642 CW |
2627 | obj = i915_gem_object_lookup(file, args->bo_handle); |
2628 | if (!obj) { | |
23ba4fd0 BW |
2629 | mutex_unlock(&dev->struct_mutex); |
2630 | return -ENOENT; | |
2631 | } | |
2632 | ||
573adb39 | 2633 | if (!i915_gem_object_is_active(obj)) |
97b2a6a1 | 2634 | goto out; |
23ba4fd0 | 2635 | |
666796da | 2636 | for (i = 0; i < I915_NUM_ENGINES; i++) { |
27c01aae | 2637 | struct drm_i915_gem_request *req; |
b4716185 | 2638 | |
d72d908b CW |
2639 | req = i915_gem_active_get(&obj->last_read[i], |
2640 | &obj->base.dev->struct_mutex); | |
27c01aae CW |
2641 | if (req) |
2642 | requests[n++] = req; | |
b4716185 CW |
2643 | } |
2644 | ||
21c310f2 CW |
2645 | out: |
2646 | i915_gem_object_put(obj); | |
23ba4fd0 BW |
2647 | mutex_unlock(&dev->struct_mutex); |
2648 | ||
b4716185 CW |
2649 | for (i = 0; i < n; i++) { |
2650 | if (ret == 0) | |
776f3236 CW |
2651 | ret = i915_wait_request(requests[i], true, |
2652 | args->timeout_ns > 0 ? &args->timeout_ns : NULL, | |
2653 | to_rps_client(file)); | |
27c01aae | 2654 | i915_gem_request_put(requests[i]); |
b4716185 | 2655 | } |
ff865885 | 2656 | return ret; |
23ba4fd0 BW |
2657 | } |
2658 | ||
b4716185 | 2659 | static int |
fa545cbf | 2660 | __i915_gem_object_sync(struct drm_i915_gem_request *to, |
8e637178 | 2661 | struct drm_i915_gem_request *from) |
b4716185 | 2662 | { |
b4716185 CW |
2663 | int ret; |
2664 | ||
8e637178 | 2665 | if (to->engine == from->engine) |
b4716185 CW |
2666 | return 0; |
2667 | ||
39df9190 | 2668 | if (!i915.semaphores) { |
776f3236 CW |
2669 | ret = i915_wait_request(from, |
2670 | from->i915->mm.interruptible, | |
2671 | NULL, | |
2672 | NO_WAITBOOST); | |
b4716185 CW |
2673 | if (ret) |
2674 | return ret; | |
b4716185 | 2675 | } else { |
8e637178 | 2676 | int idx = intel_engine_sync_index(from->engine, to->engine); |
ddf07be7 | 2677 | if (from->fence.seqno <= from->engine->semaphore.sync_seqno[idx]) |
b4716185 CW |
2678 | return 0; |
2679 | ||
8e637178 | 2680 | trace_i915_gem_ring_sync_to(to, from); |
ddf07be7 | 2681 | ret = to->engine->semaphore.sync_to(to, from); |
b4716185 CW |
2682 | if (ret) |
2683 | return ret; | |
2684 | ||
ddf07be7 | 2685 | from->engine->semaphore.sync_seqno[idx] = from->fence.seqno; |
b4716185 CW |
2686 | } |
2687 | ||
2688 | return 0; | |
2689 | } | |
2690 | ||
5816d648 BW |
2691 | /** |
2692 | * i915_gem_object_sync - sync an object to a ring. | |
2693 | * | |
2694 | * @obj: object which may be in use on another ring. | |
8e637178 | 2695 | * @to: request we are wishing to use |
5816d648 BW |
2696 | * |
2697 | * This code is meant to abstract object synchronization with the GPU. | |
8e637178 CW |
2698 | * Conceptually we serialise writes between engines inside the GPU. |
2699 | * We only allow one engine to write into a buffer at any time, but | |
2700 | * multiple readers. To ensure each has a coherent view of memory, we must: | |
b4716185 CW |
2701 | * |
2702 | * - If there is an outstanding write request to the object, the new | |
2703 | * request must wait for it to complete (either CPU or in hw, requests | |
2704 | * on the same ring will be naturally ordered). | |
2705 | * | |
2706 | * - If we are a write request (pending_write_domain is set), the new | |
2707 | * request must wait for outstanding read requests to complete. | |
5816d648 BW |
2708 | * |
2709 | * Returns 0 if successful, else propagates up the lower layer error. | |
2710 | */ | |
2911a35b BW |
2711 | int |
2712 | i915_gem_object_sync(struct drm_i915_gem_object *obj, | |
8e637178 | 2713 | struct drm_i915_gem_request *to) |
2911a35b | 2714 | { |
8cac6f6c CW |
2715 | struct i915_gem_active *active; |
2716 | unsigned long active_mask; | |
2717 | int idx; | |
41c52415 | 2718 | |
8cac6f6c | 2719 | lockdep_assert_held(&obj->base.dev->struct_mutex); |
2911a35b | 2720 | |
573adb39 | 2721 | active_mask = i915_gem_object_get_active(obj); |
8cac6f6c CW |
2722 | if (!active_mask) |
2723 | return 0; | |
27c01aae | 2724 | |
8cac6f6c CW |
2725 | if (obj->base.pending_write_domain) { |
2726 | active = obj->last_read; | |
b4716185 | 2727 | } else { |
8cac6f6c CW |
2728 | active_mask = 1; |
2729 | active = &obj->last_write; | |
b4716185 | 2730 | } |
8cac6f6c CW |
2731 | |
2732 | for_each_active(active_mask, idx) { | |
2733 | struct drm_i915_gem_request *request; | |
2734 | int ret; | |
2735 | ||
2736 | request = i915_gem_active_peek(&active[idx], | |
2737 | &obj->base.dev->struct_mutex); | |
2738 | if (!request) | |
2739 | continue; | |
2740 | ||
fa545cbf | 2741 | ret = __i915_gem_object_sync(to, request); |
b4716185 CW |
2742 | if (ret) |
2743 | return ret; | |
2744 | } | |
2911a35b | 2745 | |
b4716185 | 2746 | return 0; |
2911a35b BW |
2747 | } |
2748 | ||
b5ffc9bc CW |
2749 | static void i915_gem_object_finish_gtt(struct drm_i915_gem_object *obj) |
2750 | { | |
2751 | u32 old_write_domain, old_read_domains; | |
2752 | ||
b5ffc9bc CW |
2753 | /* Force a pagefault for domain tracking on next user access */ |
2754 | i915_gem_release_mmap(obj); | |
2755 | ||
b97c3d9c KP |
2756 | if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0) |
2757 | return; | |
2758 | ||
b5ffc9bc CW |
2759 | old_read_domains = obj->base.read_domains; |
2760 | old_write_domain = obj->base.write_domain; | |
2761 | ||
2762 | obj->base.read_domains &= ~I915_GEM_DOMAIN_GTT; | |
2763 | obj->base.write_domain &= ~I915_GEM_DOMAIN_GTT; | |
2764 | ||
2765 | trace_i915_gem_object_change_domain(obj, | |
2766 | old_read_domains, | |
2767 | old_write_domain); | |
2768 | } | |
2769 | ||
8ef8561f CW |
2770 | static void __i915_vma_iounmap(struct i915_vma *vma) |
2771 | { | |
20dfbde4 | 2772 | GEM_BUG_ON(i915_vma_is_pinned(vma)); |
8ef8561f CW |
2773 | |
2774 | if (vma->iomap == NULL) | |
2775 | return; | |
2776 | ||
2777 | io_mapping_unmap(vma->iomap); | |
2778 | vma->iomap = NULL; | |
2779 | } | |
2780 | ||
df0e9a28 | 2781 | int i915_vma_unbind(struct i915_vma *vma) |
673a394b | 2782 | { |
07fe0b12 | 2783 | struct drm_i915_gem_object *obj = vma->obj; |
b0decaf7 | 2784 | unsigned long active; |
43e28f09 | 2785 | int ret; |
673a394b | 2786 | |
b0decaf7 CW |
2787 | /* First wait upon any activity as retiring the request may |
2788 | * have side-effects such as unpinning or even unbinding this vma. | |
2789 | */ | |
2790 | active = i915_vma_get_active(vma); | |
df0e9a28 | 2791 | if (active) { |
b0decaf7 CW |
2792 | int idx; |
2793 | ||
b1f788c6 CW |
2794 | /* When a closed VMA is retired, it is unbound - eek. |
2795 | * In order to prevent it from being recursively closed, | |
2796 | * take a pin on the vma so that the second unbind is | |
2797 | * aborted. | |
2798 | */ | |
20dfbde4 | 2799 | __i915_vma_pin(vma); |
b1f788c6 | 2800 | |
b0decaf7 CW |
2801 | for_each_active(active, idx) { |
2802 | ret = i915_gem_active_retire(&vma->last_read[idx], | |
2803 | &vma->vm->dev->struct_mutex); | |
2804 | if (ret) | |
b1f788c6 | 2805 | break; |
b0decaf7 CW |
2806 | } |
2807 | ||
20dfbde4 | 2808 | __i915_vma_unpin(vma); |
b1f788c6 CW |
2809 | if (ret) |
2810 | return ret; | |
2811 | ||
b0decaf7 CW |
2812 | GEM_BUG_ON(i915_vma_is_active(vma)); |
2813 | } | |
2814 | ||
20dfbde4 | 2815 | if (i915_vma_is_pinned(vma)) |
b0decaf7 CW |
2816 | return -EBUSY; |
2817 | ||
b1f788c6 CW |
2818 | if (!drm_mm_node_allocated(&vma->node)) |
2819 | goto destroy; | |
433544bd | 2820 | |
15717de2 CW |
2821 | GEM_BUG_ON(obj->bind_count == 0); |
2822 | GEM_BUG_ON(!obj->pages); | |
c4670ad0 | 2823 | |
3272db53 CW |
2824 | if (i915_vma_is_ggtt(vma) && |
2825 | vma->ggtt_view.type == I915_GGTT_VIEW_NORMAL) { | |
8b1bc9b4 | 2826 | i915_gem_object_finish_gtt(obj); |
5323fd04 | 2827 | |
8b1bc9b4 DV |
2828 | /* release the fence reg _after_ flushing */ |
2829 | ret = i915_gem_object_put_fence(obj); | |
2830 | if (ret) | |
2831 | return ret; | |
8ef8561f CW |
2832 | |
2833 | __i915_vma_iounmap(vma); | |
8b1bc9b4 | 2834 | } |
96b47b65 | 2835 | |
50e046b6 CW |
2836 | if (likely(!vma->vm->closed)) { |
2837 | trace_i915_vma_unbind(vma); | |
2838 | vma->vm->unbind_vma(vma); | |
2839 | } | |
3272db53 | 2840 | vma->flags &= ~(I915_VMA_GLOBAL_BIND | I915_VMA_LOCAL_BIND); |
6f65e29a | 2841 | |
50e046b6 CW |
2842 | drm_mm_remove_node(&vma->node); |
2843 | list_move_tail(&vma->vm_link, &vma->vm->unbound_list); | |
2844 | ||
3272db53 | 2845 | if (i915_vma_is_ggtt(vma)) { |
fe14d5f4 TU |
2846 | if (vma->ggtt_view.type == I915_GGTT_VIEW_NORMAL) { |
2847 | obj->map_and_fenceable = false; | |
2848 | } else if (vma->ggtt_view.pages) { | |
2849 | sg_free_table(vma->ggtt_view.pages); | |
2850 | kfree(vma->ggtt_view.pages); | |
fe14d5f4 | 2851 | } |
016a65a3 | 2852 | vma->ggtt_view.pages = NULL; |
fe14d5f4 | 2853 | } |
673a394b | 2854 | |
2f633156 | 2855 | /* Since the unbound list is global, only move to that list if |
b93dab6e | 2856 | * no more VMAs exist. */ |
15717de2 CW |
2857 | if (--obj->bind_count == 0) |
2858 | list_move_tail(&obj->global_list, | |
2859 | &to_i915(obj->base.dev)->mm.unbound_list); | |
673a394b | 2860 | |
70903c3b CW |
2861 | /* And finally now the object is completely decoupled from this vma, |
2862 | * we can drop its hold on the backing storage and allow it to be | |
2863 | * reaped by the shrinker. | |
2864 | */ | |
2865 | i915_gem_object_unpin_pages(obj); | |
2866 | ||
b1f788c6 | 2867 | destroy: |
3272db53 | 2868 | if (unlikely(i915_vma_is_closed(vma))) |
b1f788c6 CW |
2869 | i915_vma_destroy(vma); |
2870 | ||
88241785 | 2871 | return 0; |
54cf91dc CW |
2872 | } |
2873 | ||
dcff85c8 CW |
2874 | int i915_gem_wait_for_idle(struct drm_i915_private *dev_priv, |
2875 | bool interruptible) | |
4df2faf4 | 2876 | { |
e2f80391 | 2877 | struct intel_engine_cs *engine; |
b4ac5afc | 2878 | int ret; |
4df2faf4 | 2879 | |
b4ac5afc | 2880 | for_each_engine(engine, dev_priv) { |
62e63007 CW |
2881 | if (engine->last_context == NULL) |
2882 | continue; | |
2883 | ||
dcff85c8 | 2884 | ret = intel_engine_idle(engine, interruptible); |
1ec14ad3 CW |
2885 | if (ret) |
2886 | return ret; | |
2887 | } | |
4df2faf4 | 2888 | |
8a1a49f9 | 2889 | return 0; |
4df2faf4 DV |
2890 | } |
2891 | ||
4144f9b5 | 2892 | static bool i915_gem_valid_gtt_space(struct i915_vma *vma, |
42d6ab48 CW |
2893 | unsigned long cache_level) |
2894 | { | |
4144f9b5 | 2895 | struct drm_mm_node *gtt_space = &vma->node; |
42d6ab48 CW |
2896 | struct drm_mm_node *other; |
2897 | ||
4144f9b5 CW |
2898 | /* |
2899 | * On some machines we have to be careful when putting differing types | |
2900 | * of snoopable memory together to avoid the prefetcher crossing memory | |
2901 | * domains and dying. During vm initialisation, we decide whether or not | |
2902 | * these constraints apply and set the drm_mm.color_adjust | |
2903 | * appropriately. | |
42d6ab48 | 2904 | */ |
4144f9b5 | 2905 | if (vma->vm->mm.color_adjust == NULL) |
42d6ab48 CW |
2906 | return true; |
2907 | ||
c6cfb325 | 2908 | if (!drm_mm_node_allocated(gtt_space)) |
42d6ab48 CW |
2909 | return true; |
2910 | ||
2911 | if (list_empty(>t_space->node_list)) | |
2912 | return true; | |
2913 | ||
2914 | other = list_entry(gtt_space->node_list.prev, struct drm_mm_node, node_list); | |
2915 | if (other->allocated && !other->hole_follows && other->color != cache_level) | |
2916 | return false; | |
2917 | ||
2918 | other = list_entry(gtt_space->node_list.next, struct drm_mm_node, node_list); | |
2919 | if (other->allocated && !gtt_space->hole_follows && other->color != cache_level) | |
2920 | return false; | |
2921 | ||
2922 | return true; | |
2923 | } | |
2924 | ||
673a394b | 2925 | /** |
59bfa124 CW |
2926 | * i915_vma_insert - finds a slot for the vma in its address space |
2927 | * @vma: the vma | |
91b2db6f | 2928 | * @size: requested size in bytes (can be larger than the VMA) |
59bfa124 | 2929 | * @alignment: required alignment |
14bb2c11 | 2930 | * @flags: mask of PIN_* flags to use |
59bfa124 CW |
2931 | * |
2932 | * First we try to allocate some free space that meets the requirements for | |
2933 | * the VMA. Failiing that, if the flags permit, it will evict an old VMA, | |
2934 | * preferrably the oldest idle entry to make room for the new VMA. | |
2935 | * | |
2936 | * Returns: | |
2937 | * 0 on success, negative error code otherwise. | |
673a394b | 2938 | */ |
59bfa124 CW |
2939 | static int |
2940 | i915_vma_insert(struct i915_vma *vma, u64 size, u64 alignment, u64 flags) | |
673a394b | 2941 | { |
59bfa124 CW |
2942 | struct drm_i915_private *dev_priv = to_i915(vma->vm->dev); |
2943 | struct drm_i915_gem_object *obj = vma->obj; | |
de180033 CW |
2944 | u64 start, end; |
2945 | u64 min_alignment; | |
07f73f69 | 2946 | int ret; |
673a394b | 2947 | |
3272db53 | 2948 | GEM_BUG_ON(vma->flags & (I915_VMA_GLOBAL_BIND | I915_VMA_LOCAL_BIND)); |
59bfa124 | 2949 | GEM_BUG_ON(drm_mm_node_allocated(&vma->node)); |
de180033 CW |
2950 | |
2951 | size = max(size, vma->size); | |
2952 | if (flags & PIN_MAPPABLE) | |
2953 | size = i915_gem_get_ggtt_size(dev_priv, size, obj->tiling_mode); | |
2954 | ||
2955 | min_alignment = | |
2956 | i915_gem_get_ggtt_alignment(dev_priv, size, obj->tiling_mode, | |
2957 | flags & PIN_MAPPABLE); | |
2958 | if (alignment == 0) | |
2959 | alignment = min_alignment; | |
2960 | if (alignment & (min_alignment - 1)) { | |
2961 | DRM_DEBUG("Invalid object alignment requested %llu, minimum %llu\n", | |
2962 | alignment, min_alignment); | |
59bfa124 | 2963 | return -EINVAL; |
91e6711e | 2964 | } |
a00b10c3 | 2965 | |
101b506a | 2966 | start = flags & PIN_OFFSET_BIAS ? flags & PIN_OFFSET_MASK : 0; |
de180033 CW |
2967 | |
2968 | end = vma->vm->total; | |
101b506a | 2969 | if (flags & PIN_MAPPABLE) |
91b2db6f | 2970 | end = min_t(u64, end, dev_priv->ggtt.mappable_end); |
101b506a | 2971 | if (flags & PIN_ZONE_4G) |
48ea1e32 | 2972 | end = min_t(u64, end, (1ULL << 32) - PAGE_SIZE); |
101b506a | 2973 | |
91e6711e JL |
2974 | /* If binding the object/GGTT view requires more space than the entire |
2975 | * aperture has, reject it early before evicting everything in a vain | |
2976 | * attempt to find space. | |
654fc607 | 2977 | */ |
91e6711e | 2978 | if (size > end) { |
de180033 | 2979 | DRM_DEBUG("Attempting to bind an object larger than the aperture: request=%llu [object=%zd] > %s aperture=%llu\n", |
91b2db6f | 2980 | size, obj->base.size, |
1ec9e26d | 2981 | flags & PIN_MAPPABLE ? "mappable" : "total", |
d23db88c | 2982 | end); |
59bfa124 | 2983 | return -E2BIG; |
654fc607 CW |
2984 | } |
2985 | ||
37e680a1 | 2986 | ret = i915_gem_object_get_pages(obj); |
6c085a72 | 2987 | if (ret) |
59bfa124 | 2988 | return ret; |
6c085a72 | 2989 | |
fbdda6fb CW |
2990 | i915_gem_object_pin_pages(obj); |
2991 | ||
506a8e87 | 2992 | if (flags & PIN_OFFSET_FIXED) { |
59bfa124 | 2993 | u64 offset = flags & PIN_OFFSET_MASK; |
de180033 | 2994 | if (offset & (alignment - 1) || offset > end - size) { |
506a8e87 | 2995 | ret = -EINVAL; |
de180033 | 2996 | goto err_unpin; |
506a8e87 | 2997 | } |
de180033 | 2998 | |
506a8e87 CW |
2999 | vma->node.start = offset; |
3000 | vma->node.size = size; | |
3001 | vma->node.color = obj->cache_level; | |
de180033 | 3002 | ret = drm_mm_reserve_node(&vma->vm->mm, &vma->node); |
506a8e87 CW |
3003 | if (ret) { |
3004 | ret = i915_gem_evict_for_vma(vma); | |
3005 | if (ret == 0) | |
de180033 CW |
3006 | ret = drm_mm_reserve_node(&vma->vm->mm, &vma->node); |
3007 | if (ret) | |
3008 | goto err_unpin; | |
506a8e87 | 3009 | } |
101b506a | 3010 | } else { |
de180033 CW |
3011 | u32 search_flag, alloc_flag; |
3012 | ||
506a8e87 CW |
3013 | if (flags & PIN_HIGH) { |
3014 | search_flag = DRM_MM_SEARCH_BELOW; | |
3015 | alloc_flag = DRM_MM_CREATE_TOP; | |
3016 | } else { | |
3017 | search_flag = DRM_MM_SEARCH_DEFAULT; | |
3018 | alloc_flag = DRM_MM_CREATE_DEFAULT; | |
3019 | } | |
101b506a | 3020 | |
954c4691 CW |
3021 | /* We only allocate in PAGE_SIZE/GTT_PAGE_SIZE (4096) chunks, |
3022 | * so we know that we always have a minimum alignment of 4096. | |
3023 | * The drm_mm range manager is optimised to return results | |
3024 | * with zero alignment, so where possible use the optimal | |
3025 | * path. | |
3026 | */ | |
3027 | if (alignment <= 4096) | |
3028 | alignment = 0; | |
3029 | ||
0a9ae0d7 | 3030 | search_free: |
de180033 CW |
3031 | ret = drm_mm_insert_node_in_range_generic(&vma->vm->mm, |
3032 | &vma->node, | |
506a8e87 CW |
3033 | size, alignment, |
3034 | obj->cache_level, | |
3035 | start, end, | |
3036 | search_flag, | |
3037 | alloc_flag); | |
3038 | if (ret) { | |
de180033 | 3039 | ret = i915_gem_evict_something(vma->vm, size, alignment, |
506a8e87 CW |
3040 | obj->cache_level, |
3041 | start, end, | |
3042 | flags); | |
3043 | if (ret == 0) | |
3044 | goto search_free; | |
9731129c | 3045 | |
de180033 | 3046 | goto err_unpin; |
506a8e87 | 3047 | } |
673a394b | 3048 | } |
37508589 | 3049 | GEM_BUG_ON(!i915_gem_valid_gtt_space(vma, obj->cache_level)); |
673a394b | 3050 | |
35c20a60 | 3051 | list_move_tail(&obj->global_list, &dev_priv->mm.bound_list); |
de180033 | 3052 | list_move_tail(&vma->vm_link, &vma->vm->inactive_list); |
15717de2 | 3053 | obj->bind_count++; |
bf1a1092 | 3054 | |
59bfa124 | 3055 | return 0; |
2f633156 | 3056 | |
bc6bc15b | 3057 | err_unpin: |
2f633156 | 3058 | i915_gem_object_unpin_pages(obj); |
59bfa124 | 3059 | return ret; |
673a394b EA |
3060 | } |
3061 | ||
000433b6 | 3062 | bool |
2c22569b CW |
3063 | i915_gem_clflush_object(struct drm_i915_gem_object *obj, |
3064 | bool force) | |
673a394b | 3065 | { |
673a394b EA |
3066 | /* If we don't have a page list set up, then we're not pinned |
3067 | * to GPU, and we can ignore the cache flush because it'll happen | |
3068 | * again at bind time. | |
3069 | */ | |
05394f39 | 3070 | if (obj->pages == NULL) |
000433b6 | 3071 | return false; |
673a394b | 3072 | |
769ce464 ID |
3073 | /* |
3074 | * Stolen memory is always coherent with the GPU as it is explicitly | |
3075 | * marked as wc by the system, or the system is cache-coherent. | |
3076 | */ | |
6a2c4232 | 3077 | if (obj->stolen || obj->phys_handle) |
000433b6 | 3078 | return false; |
769ce464 | 3079 | |
9c23f7fc CW |
3080 | /* If the GPU is snooping the contents of the CPU cache, |
3081 | * we do not need to manually clear the CPU cache lines. However, | |
3082 | * the caches are only snooped when the render cache is | |
3083 | * flushed/invalidated. As we always have to emit invalidations | |
3084 | * and flushes when moving into and out of the RENDER domain, correct | |
3085 | * snooping behaviour occurs naturally as the result of our domain | |
3086 | * tracking. | |
3087 | */ | |
0f71979a CW |
3088 | if (!force && cpu_cache_is_coherent(obj->base.dev, obj->cache_level)) { |
3089 | obj->cache_dirty = true; | |
000433b6 | 3090 | return false; |
0f71979a | 3091 | } |
9c23f7fc | 3092 | |
1c5d22f7 | 3093 | trace_i915_gem_object_clflush(obj); |
9da3da66 | 3094 | drm_clflush_sg(obj->pages); |
0f71979a | 3095 | obj->cache_dirty = false; |
000433b6 CW |
3096 | |
3097 | return true; | |
e47c68e9 EA |
3098 | } |
3099 | ||
3100 | /** Flushes the GTT write domain for the object if it's dirty. */ | |
3101 | static void | |
05394f39 | 3102 | i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj) |
e47c68e9 | 3103 | { |
1c5d22f7 CW |
3104 | uint32_t old_write_domain; |
3105 | ||
05394f39 | 3106 | if (obj->base.write_domain != I915_GEM_DOMAIN_GTT) |
e47c68e9 EA |
3107 | return; |
3108 | ||
63256ec5 | 3109 | /* No actual flushing is required for the GTT write domain. Writes |
e47c68e9 EA |
3110 | * to it immediately go to main memory as far as we know, so there's |
3111 | * no chipset flush. It also doesn't land in render cache. | |
63256ec5 CW |
3112 | * |
3113 | * However, we do have to enforce the order so that all writes through | |
3114 | * the GTT land before any writes to the device, such as updates to | |
3115 | * the GATT itself. | |
e47c68e9 | 3116 | */ |
63256ec5 CW |
3117 | wmb(); |
3118 | ||
05394f39 CW |
3119 | old_write_domain = obj->base.write_domain; |
3120 | obj->base.write_domain = 0; | |
1c5d22f7 | 3121 | |
de152b62 | 3122 | intel_fb_obj_flush(obj, false, ORIGIN_GTT); |
f99d7069 | 3123 | |
1c5d22f7 | 3124 | trace_i915_gem_object_change_domain(obj, |
05394f39 | 3125 | obj->base.read_domains, |
1c5d22f7 | 3126 | old_write_domain); |
e47c68e9 EA |
3127 | } |
3128 | ||
3129 | /** Flushes the CPU write domain for the object if it's dirty. */ | |
3130 | static void | |
e62b59e4 | 3131 | i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj) |
e47c68e9 | 3132 | { |
1c5d22f7 | 3133 | uint32_t old_write_domain; |
e47c68e9 | 3134 | |
05394f39 | 3135 | if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) |
e47c68e9 EA |
3136 | return; |
3137 | ||
e62b59e4 | 3138 | if (i915_gem_clflush_object(obj, obj->pin_display)) |
c033666a | 3139 | i915_gem_chipset_flush(to_i915(obj->base.dev)); |
000433b6 | 3140 | |
05394f39 CW |
3141 | old_write_domain = obj->base.write_domain; |
3142 | obj->base.write_domain = 0; | |
1c5d22f7 | 3143 | |
de152b62 | 3144 | intel_fb_obj_flush(obj, false, ORIGIN_CPU); |
f99d7069 | 3145 | |
1c5d22f7 | 3146 | trace_i915_gem_object_change_domain(obj, |
05394f39 | 3147 | obj->base.read_domains, |
1c5d22f7 | 3148 | old_write_domain); |
e47c68e9 EA |
3149 | } |
3150 | ||
2ef7eeaa EA |
3151 | /** |
3152 | * Moves a single object to the GTT read, and possibly write domain. | |
14bb2c11 TU |
3153 | * @obj: object to act on |
3154 | * @write: ask for write access or read only | |
2ef7eeaa EA |
3155 | * |
3156 | * This function returns when the move is complete, including waiting on | |
3157 | * flushes to occur. | |
3158 | */ | |
79e53945 | 3159 | int |
2021746e | 3160 | i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write) |
2ef7eeaa | 3161 | { |
1c5d22f7 | 3162 | uint32_t old_write_domain, old_read_domains; |
43566ded | 3163 | struct i915_vma *vma; |
e47c68e9 | 3164 | int ret; |
2ef7eeaa | 3165 | |
0201f1ec | 3166 | ret = i915_gem_object_wait_rendering(obj, !write); |
88241785 CW |
3167 | if (ret) |
3168 | return ret; | |
3169 | ||
c13d87ea CW |
3170 | if (obj->base.write_domain == I915_GEM_DOMAIN_GTT) |
3171 | return 0; | |
3172 | ||
43566ded CW |
3173 | /* Flush and acquire obj->pages so that we are coherent through |
3174 | * direct access in memory with previous cached writes through | |
3175 | * shmemfs and that our cache domain tracking remains valid. | |
3176 | * For example, if the obj->filp was moved to swap without us | |
3177 | * being notified and releasing the pages, we would mistakenly | |
3178 | * continue to assume that the obj remained out of the CPU cached | |
3179 | * domain. | |
3180 | */ | |
3181 | ret = i915_gem_object_get_pages(obj); | |
3182 | if (ret) | |
3183 | return ret; | |
3184 | ||
e62b59e4 | 3185 | i915_gem_object_flush_cpu_write_domain(obj); |
1c5d22f7 | 3186 | |
d0a57789 CW |
3187 | /* Serialise direct access to this object with the barriers for |
3188 | * coherent writes from the GPU, by effectively invalidating the | |
3189 | * GTT domain upon first access. | |
3190 | */ | |
3191 | if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0) | |
3192 | mb(); | |
3193 | ||
05394f39 CW |
3194 | old_write_domain = obj->base.write_domain; |
3195 | old_read_domains = obj->base.read_domains; | |
1c5d22f7 | 3196 | |
e47c68e9 EA |
3197 | /* It should now be out of any other write domains, and we can update |
3198 | * the domain values for our changes. | |
3199 | */ | |
05394f39 CW |
3200 | BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) != 0); |
3201 | obj->base.read_domains |= I915_GEM_DOMAIN_GTT; | |
e47c68e9 | 3202 | if (write) { |
05394f39 CW |
3203 | obj->base.read_domains = I915_GEM_DOMAIN_GTT; |
3204 | obj->base.write_domain = I915_GEM_DOMAIN_GTT; | |
3205 | obj->dirty = 1; | |
2ef7eeaa EA |
3206 | } |
3207 | ||
1c5d22f7 CW |
3208 | trace_i915_gem_object_change_domain(obj, |
3209 | old_read_domains, | |
3210 | old_write_domain); | |
3211 | ||
8325a09d | 3212 | /* And bump the LRU for this access */ |
43566ded | 3213 | vma = i915_gem_obj_to_ggtt(obj); |
b0decaf7 CW |
3214 | if (vma && |
3215 | drm_mm_node_allocated(&vma->node) && | |
3216 | !i915_vma_is_active(vma)) | |
3217 | list_move_tail(&vma->vm_link, &vma->vm->inactive_list); | |
8325a09d | 3218 | |
e47c68e9 EA |
3219 | return 0; |
3220 | } | |
3221 | ||
ef55f92a CW |
3222 | /** |
3223 | * Changes the cache-level of an object across all VMA. | |
14bb2c11 TU |
3224 | * @obj: object to act on |
3225 | * @cache_level: new cache level to set for the object | |
ef55f92a CW |
3226 | * |
3227 | * After this function returns, the object will be in the new cache-level | |
3228 | * across all GTT and the contents of the backing storage will be coherent, | |
3229 | * with respect to the new cache-level. In order to keep the backing storage | |
3230 | * coherent for all users, we only allow a single cache level to be set | |
3231 | * globally on the object and prevent it from being changed whilst the | |
3232 | * hardware is reading from the object. That is if the object is currently | |
3233 | * on the scanout it will be set to uncached (or equivalent display | |
3234 | * cache coherency) and all non-MOCS GPU access will also be uncached so | |
3235 | * that all direct access to the scanout remains coherent. | |
3236 | */ | |
e4ffd173 CW |
3237 | int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj, |
3238 | enum i915_cache_level cache_level) | |
3239 | { | |
aa653a68 | 3240 | struct i915_vma *vma; |
ed75a55b | 3241 | int ret = 0; |
e4ffd173 CW |
3242 | |
3243 | if (obj->cache_level == cache_level) | |
ed75a55b | 3244 | goto out; |
e4ffd173 | 3245 | |
ef55f92a CW |
3246 | /* Inspect the list of currently bound VMA and unbind any that would |
3247 | * be invalid given the new cache-level. This is principally to | |
3248 | * catch the issue of the CS prefetch crossing page boundaries and | |
3249 | * reading an invalid PTE on older architectures. | |
3250 | */ | |
aa653a68 CW |
3251 | restart: |
3252 | list_for_each_entry(vma, &obj->vma_list, obj_link) { | |
ef55f92a CW |
3253 | if (!drm_mm_node_allocated(&vma->node)) |
3254 | continue; | |
3255 | ||
20dfbde4 | 3256 | if (i915_vma_is_pinned(vma)) { |
ef55f92a CW |
3257 | DRM_DEBUG("can not change the cache level of pinned objects\n"); |
3258 | return -EBUSY; | |
3259 | } | |
3260 | ||
aa653a68 CW |
3261 | if (i915_gem_valid_gtt_space(vma, cache_level)) |
3262 | continue; | |
3263 | ||
3264 | ret = i915_vma_unbind(vma); | |
3265 | if (ret) | |
3266 | return ret; | |
3267 | ||
3268 | /* As unbinding may affect other elements in the | |
3269 | * obj->vma_list (due to side-effects from retiring | |
3270 | * an active vma), play safe and restart the iterator. | |
3271 | */ | |
3272 | goto restart; | |
42d6ab48 CW |
3273 | } |
3274 | ||
ef55f92a CW |
3275 | /* We can reuse the existing drm_mm nodes but need to change the |
3276 | * cache-level on the PTE. We could simply unbind them all and | |
3277 | * rebind with the correct cache-level on next use. However since | |
3278 | * we already have a valid slot, dma mapping, pages etc, we may as | |
3279 | * rewrite the PTE in the belief that doing so tramples upon less | |
3280 | * state and so involves less work. | |
3281 | */ | |
15717de2 | 3282 | if (obj->bind_count) { |
ef55f92a CW |
3283 | /* Before we change the PTE, the GPU must not be accessing it. |
3284 | * If we wait upon the object, we know that all the bound | |
3285 | * VMA are no longer active. | |
3286 | */ | |
2e2f351d | 3287 | ret = i915_gem_object_wait_rendering(obj, false); |
e4ffd173 CW |
3288 | if (ret) |
3289 | return ret; | |
3290 | ||
aa653a68 | 3291 | if (!HAS_LLC(obj->base.dev) && cache_level != I915_CACHE_NONE) { |
ef55f92a CW |
3292 | /* Access to snoopable pages through the GTT is |
3293 | * incoherent and on some machines causes a hard | |
3294 | * lockup. Relinquish the CPU mmaping to force | |
3295 | * userspace to refault in the pages and we can | |
3296 | * then double check if the GTT mapping is still | |
3297 | * valid for that pointer access. | |
3298 | */ | |
3299 | i915_gem_release_mmap(obj); | |
3300 | ||
3301 | /* As we no longer need a fence for GTT access, | |
3302 | * we can relinquish it now (and so prevent having | |
3303 | * to steal a fence from someone else on the next | |
3304 | * fence request). Note GPU activity would have | |
3305 | * dropped the fence as all snoopable access is | |
3306 | * supposed to be linear. | |
3307 | */ | |
e4ffd173 CW |
3308 | ret = i915_gem_object_put_fence(obj); |
3309 | if (ret) | |
3310 | return ret; | |
ef55f92a CW |
3311 | } else { |
3312 | /* We either have incoherent backing store and | |
3313 | * so no GTT access or the architecture is fully | |
3314 | * coherent. In such cases, existing GTT mmaps | |
3315 | * ignore the cache bit in the PTE and we can | |
3316 | * rewrite it without confusing the GPU or having | |
3317 | * to force userspace to fault back in its mmaps. | |
3318 | */ | |
e4ffd173 CW |
3319 | } |
3320 | ||
1c7f4bca | 3321 | list_for_each_entry(vma, &obj->vma_list, obj_link) { |
ef55f92a CW |
3322 | if (!drm_mm_node_allocated(&vma->node)) |
3323 | continue; | |
3324 | ||
3325 | ret = i915_vma_bind(vma, cache_level, PIN_UPDATE); | |
3326 | if (ret) | |
3327 | return ret; | |
3328 | } | |
e4ffd173 CW |
3329 | } |
3330 | ||
1c7f4bca | 3331 | list_for_each_entry(vma, &obj->vma_list, obj_link) |
2c22569b CW |
3332 | vma->node.color = cache_level; |
3333 | obj->cache_level = cache_level; | |
3334 | ||
ed75a55b | 3335 | out: |
ef55f92a CW |
3336 | /* Flush the dirty CPU caches to the backing storage so that the |
3337 | * object is now coherent at its new cache level (with respect | |
3338 | * to the access domain). | |
3339 | */ | |
b50a5371 | 3340 | if (obj->cache_dirty && cpu_write_needs_clflush(obj)) { |
0f71979a | 3341 | if (i915_gem_clflush_object(obj, true)) |
c033666a | 3342 | i915_gem_chipset_flush(to_i915(obj->base.dev)); |
e4ffd173 CW |
3343 | } |
3344 | ||
e4ffd173 CW |
3345 | return 0; |
3346 | } | |
3347 | ||
199adf40 BW |
3348 | int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data, |
3349 | struct drm_file *file) | |
e6994aee | 3350 | { |
199adf40 | 3351 | struct drm_i915_gem_caching *args = data; |
e6994aee | 3352 | struct drm_i915_gem_object *obj; |
e6994aee | 3353 | |
03ac0642 CW |
3354 | obj = i915_gem_object_lookup(file, args->handle); |
3355 | if (!obj) | |
432be69d | 3356 | return -ENOENT; |
e6994aee | 3357 | |
651d794f CW |
3358 | switch (obj->cache_level) { |
3359 | case I915_CACHE_LLC: | |
3360 | case I915_CACHE_L3_LLC: | |
3361 | args->caching = I915_CACHING_CACHED; | |
3362 | break; | |
3363 | ||
4257d3ba CW |
3364 | case I915_CACHE_WT: |
3365 | args->caching = I915_CACHING_DISPLAY; | |
3366 | break; | |
3367 | ||
651d794f CW |
3368 | default: |
3369 | args->caching = I915_CACHING_NONE; | |
3370 | break; | |
3371 | } | |
e6994aee | 3372 | |
34911fd3 | 3373 | i915_gem_object_put_unlocked(obj); |
432be69d | 3374 | return 0; |
e6994aee CW |
3375 | } |
3376 | ||
199adf40 BW |
3377 | int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data, |
3378 | struct drm_file *file) | |
e6994aee | 3379 | { |
fac5e23e | 3380 | struct drm_i915_private *dev_priv = to_i915(dev); |
199adf40 | 3381 | struct drm_i915_gem_caching *args = data; |
e6994aee CW |
3382 | struct drm_i915_gem_object *obj; |
3383 | enum i915_cache_level level; | |
3384 | int ret; | |
3385 | ||
199adf40 BW |
3386 | switch (args->caching) { |
3387 | case I915_CACHING_NONE: | |
e6994aee CW |
3388 | level = I915_CACHE_NONE; |
3389 | break; | |
199adf40 | 3390 | case I915_CACHING_CACHED: |
e5756c10 ID |
3391 | /* |
3392 | * Due to a HW issue on BXT A stepping, GPU stores via a | |
3393 | * snooped mapping may leave stale data in a corresponding CPU | |
3394 | * cacheline, whereas normally such cachelines would get | |
3395 | * invalidated. | |
3396 | */ | |
ca377809 | 3397 | if (!HAS_LLC(dev) && !HAS_SNOOP(dev)) |
e5756c10 ID |
3398 | return -ENODEV; |
3399 | ||
e6994aee CW |
3400 | level = I915_CACHE_LLC; |
3401 | break; | |
4257d3ba CW |
3402 | case I915_CACHING_DISPLAY: |
3403 | level = HAS_WT(dev) ? I915_CACHE_WT : I915_CACHE_NONE; | |
3404 | break; | |
e6994aee CW |
3405 | default: |
3406 | return -EINVAL; | |
3407 | } | |
3408 | ||
fd0fe6ac ID |
3409 | intel_runtime_pm_get(dev_priv); |
3410 | ||
3bc2913e BW |
3411 | ret = i915_mutex_lock_interruptible(dev); |
3412 | if (ret) | |
fd0fe6ac | 3413 | goto rpm_put; |
3bc2913e | 3414 | |
03ac0642 CW |
3415 | obj = i915_gem_object_lookup(file, args->handle); |
3416 | if (!obj) { | |
e6994aee CW |
3417 | ret = -ENOENT; |
3418 | goto unlock; | |
3419 | } | |
3420 | ||
3421 | ret = i915_gem_object_set_cache_level(obj, level); | |
3422 | ||
f8c417cd | 3423 | i915_gem_object_put(obj); |
e6994aee CW |
3424 | unlock: |
3425 | mutex_unlock(&dev->struct_mutex); | |
fd0fe6ac ID |
3426 | rpm_put: |
3427 | intel_runtime_pm_put(dev_priv); | |
3428 | ||
e6994aee CW |
3429 | return ret; |
3430 | } | |
3431 | ||
b9241ea3 | 3432 | /* |
2da3b9b9 CW |
3433 | * Prepare buffer for display plane (scanout, cursors, etc). |
3434 | * Can be called from an uninterruptible phase (modesetting) and allows | |
3435 | * any flushes to be pipelined (for pageflips). | |
b9241ea3 ZW |
3436 | */ |
3437 | int | |
2da3b9b9 CW |
3438 | i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj, |
3439 | u32 alignment, | |
e6617330 | 3440 | const struct i915_ggtt_view *view) |
b9241ea3 | 3441 | { |
2da3b9b9 | 3442 | u32 old_read_domains, old_write_domain; |
b9241ea3 ZW |
3443 | int ret; |
3444 | ||
cc98b413 CW |
3445 | /* Mark the pin_display early so that we account for the |
3446 | * display coherency whilst setting up the cache domains. | |
3447 | */ | |
8a0c39b1 | 3448 | obj->pin_display++; |
cc98b413 | 3449 | |
a7ef0640 EA |
3450 | /* The display engine is not coherent with the LLC cache on gen6. As |
3451 | * a result, we make sure that the pinning that is about to occur is | |
3452 | * done with uncached PTEs. This is lowest common denominator for all | |
3453 | * chipsets. | |
3454 | * | |
3455 | * However for gen6+, we could do better by using the GFDT bit instead | |
3456 | * of uncaching, which would allow us to flush all the LLC-cached data | |
3457 | * with that bit in the PTE to main memory with just one PIPE_CONTROL. | |
3458 | */ | |
651d794f CW |
3459 | ret = i915_gem_object_set_cache_level(obj, |
3460 | HAS_WT(obj->base.dev) ? I915_CACHE_WT : I915_CACHE_NONE); | |
a7ef0640 | 3461 | if (ret) |
cc98b413 | 3462 | goto err_unpin_display; |
a7ef0640 | 3463 | |
2da3b9b9 CW |
3464 | /* As the user may map the buffer once pinned in the display plane |
3465 | * (e.g. libkms for the bootup splash), we have to ensure that we | |
3466 | * always use map_and_fenceable for all scanout buffers. | |
3467 | */ | |
91b2db6f | 3468 | ret = i915_gem_object_ggtt_pin(obj, view, 0, alignment, |
50470bb0 TU |
3469 | view->type == I915_GGTT_VIEW_NORMAL ? |
3470 | PIN_MAPPABLE : 0); | |
2da3b9b9 | 3471 | if (ret) |
cc98b413 | 3472 | goto err_unpin_display; |
2da3b9b9 | 3473 | |
e62b59e4 | 3474 | i915_gem_object_flush_cpu_write_domain(obj); |
b118c1e3 | 3475 | |
2da3b9b9 | 3476 | old_write_domain = obj->base.write_domain; |
05394f39 | 3477 | old_read_domains = obj->base.read_domains; |
2da3b9b9 CW |
3478 | |
3479 | /* It should now be out of any other write domains, and we can update | |
3480 | * the domain values for our changes. | |
3481 | */ | |
e5f1d962 | 3482 | obj->base.write_domain = 0; |
05394f39 | 3483 | obj->base.read_domains |= I915_GEM_DOMAIN_GTT; |
b9241ea3 ZW |
3484 | |
3485 | trace_i915_gem_object_change_domain(obj, | |
3486 | old_read_domains, | |
2da3b9b9 | 3487 | old_write_domain); |
b9241ea3 ZW |
3488 | |
3489 | return 0; | |
cc98b413 CW |
3490 | |
3491 | err_unpin_display: | |
8a0c39b1 | 3492 | obj->pin_display--; |
cc98b413 CW |
3493 | return ret; |
3494 | } | |
3495 | ||
3496 | void | |
e6617330 TU |
3497 | i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object *obj, |
3498 | const struct i915_ggtt_view *view) | |
cc98b413 | 3499 | { |
8a0c39b1 TU |
3500 | if (WARN_ON(obj->pin_display == 0)) |
3501 | return; | |
3502 | ||
e6617330 TU |
3503 | i915_gem_object_ggtt_unpin_view(obj, view); |
3504 | ||
8a0c39b1 | 3505 | obj->pin_display--; |
b9241ea3 ZW |
3506 | } |
3507 | ||
e47c68e9 EA |
3508 | /** |
3509 | * Moves a single object to the CPU read, and possibly write domain. | |
14bb2c11 TU |
3510 | * @obj: object to act on |
3511 | * @write: requesting write or read-only access | |
e47c68e9 EA |
3512 | * |
3513 | * This function returns when the move is complete, including waiting on | |
3514 | * flushes to occur. | |
3515 | */ | |
dabdfe02 | 3516 | int |
919926ae | 3517 | i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write) |
e47c68e9 | 3518 | { |
1c5d22f7 | 3519 | uint32_t old_write_domain, old_read_domains; |
e47c68e9 EA |
3520 | int ret; |
3521 | ||
0201f1ec | 3522 | ret = i915_gem_object_wait_rendering(obj, !write); |
88241785 CW |
3523 | if (ret) |
3524 | return ret; | |
3525 | ||
c13d87ea CW |
3526 | if (obj->base.write_domain == I915_GEM_DOMAIN_CPU) |
3527 | return 0; | |
3528 | ||
e47c68e9 | 3529 | i915_gem_object_flush_gtt_write_domain(obj); |
2ef7eeaa | 3530 | |
05394f39 CW |
3531 | old_write_domain = obj->base.write_domain; |
3532 | old_read_domains = obj->base.read_domains; | |
1c5d22f7 | 3533 | |
e47c68e9 | 3534 | /* Flush the CPU cache if it's still invalid. */ |
05394f39 | 3535 | if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) { |
2c22569b | 3536 | i915_gem_clflush_object(obj, false); |
2ef7eeaa | 3537 | |
05394f39 | 3538 | obj->base.read_domains |= I915_GEM_DOMAIN_CPU; |
2ef7eeaa EA |
3539 | } |
3540 | ||
3541 | /* It should now be out of any other write domains, and we can update | |
3542 | * the domain values for our changes. | |
3543 | */ | |
05394f39 | 3544 | BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) != 0); |
e47c68e9 EA |
3545 | |
3546 | /* If we're writing through the CPU, then the GPU read domains will | |
3547 | * need to be invalidated at next use. | |
3548 | */ | |
3549 | if (write) { | |
05394f39 CW |
3550 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; |
3551 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; | |
e47c68e9 | 3552 | } |
2ef7eeaa | 3553 | |
1c5d22f7 CW |
3554 | trace_i915_gem_object_change_domain(obj, |
3555 | old_read_domains, | |
3556 | old_write_domain); | |
3557 | ||
2ef7eeaa EA |
3558 | return 0; |
3559 | } | |
3560 | ||
673a394b EA |
3561 | /* Throttle our rendering by waiting until the ring has completed our requests |
3562 | * emitted over 20 msec ago. | |
3563 | * | |
b962442e EA |
3564 | * Note that if we were to use the current jiffies each time around the loop, |
3565 | * we wouldn't escape the function with any frames outstanding if the time to | |
3566 | * render a frame was over 20ms. | |
3567 | * | |
673a394b EA |
3568 | * This should get us reasonable parallelism between CPU and GPU but also |
3569 | * relatively low latency when blocking on a particular request to finish. | |
3570 | */ | |
40a5f0de | 3571 | static int |
f787a5f5 | 3572 | i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file) |
40a5f0de | 3573 | { |
fac5e23e | 3574 | struct drm_i915_private *dev_priv = to_i915(dev); |
f787a5f5 | 3575 | struct drm_i915_file_private *file_priv = file->driver_priv; |
d0bc54f2 | 3576 | unsigned long recent_enough = jiffies - DRM_I915_THROTTLE_JIFFIES; |
54fb2411 | 3577 | struct drm_i915_gem_request *request, *target = NULL; |
f787a5f5 | 3578 | int ret; |
93533c29 | 3579 | |
308887aa DV |
3580 | ret = i915_gem_wait_for_error(&dev_priv->gpu_error); |
3581 | if (ret) | |
3582 | return ret; | |
3583 | ||
f4457ae7 CW |
3584 | /* ABI: return -EIO if already wedged */ |
3585 | if (i915_terminally_wedged(&dev_priv->gpu_error)) | |
3586 | return -EIO; | |
e110e8d6 | 3587 | |
1c25595f | 3588 | spin_lock(&file_priv->mm.lock); |
f787a5f5 | 3589 | list_for_each_entry(request, &file_priv->mm.request_list, client_list) { |
b962442e EA |
3590 | if (time_after_eq(request->emitted_jiffies, recent_enough)) |
3591 | break; | |
40a5f0de | 3592 | |
fcfa423c JH |
3593 | /* |
3594 | * Note that the request might not have been submitted yet. | |
3595 | * In which case emitted_jiffies will be zero. | |
3596 | */ | |
3597 | if (!request->emitted_jiffies) | |
3598 | continue; | |
3599 | ||
54fb2411 | 3600 | target = request; |
b962442e | 3601 | } |
ff865885 | 3602 | if (target) |
e8a261ea | 3603 | i915_gem_request_get(target); |
1c25595f | 3604 | spin_unlock(&file_priv->mm.lock); |
40a5f0de | 3605 | |
54fb2411 | 3606 | if (target == NULL) |
f787a5f5 | 3607 | return 0; |
2bc43b5c | 3608 | |
776f3236 | 3609 | ret = i915_wait_request(target, true, NULL, NULL); |
e8a261ea | 3610 | i915_gem_request_put(target); |
ff865885 | 3611 | |
40a5f0de EA |
3612 | return ret; |
3613 | } | |
3614 | ||
d23db88c | 3615 | static bool |
91b2db6f | 3616 | i915_vma_misplaced(struct i915_vma *vma, u64 size, u64 alignment, u64 flags) |
d23db88c CW |
3617 | { |
3618 | struct drm_i915_gem_object *obj = vma->obj; | |
3619 | ||
59bfa124 CW |
3620 | if (!drm_mm_node_allocated(&vma->node)) |
3621 | return false; | |
3622 | ||
91b2db6f CW |
3623 | if (vma->node.size < size) |
3624 | return true; | |
3625 | ||
3626 | if (alignment && vma->node.start & (alignment - 1)) | |
d23db88c CW |
3627 | return true; |
3628 | ||
3629 | if (flags & PIN_MAPPABLE && !obj->map_and_fenceable) | |
3630 | return true; | |
3631 | ||
3632 | if (flags & PIN_OFFSET_BIAS && | |
3633 | vma->node.start < (flags & PIN_OFFSET_MASK)) | |
3634 | return true; | |
3635 | ||
506a8e87 CW |
3636 | if (flags & PIN_OFFSET_FIXED && |
3637 | vma->node.start != (flags & PIN_OFFSET_MASK)) | |
3638 | return true; | |
3639 | ||
d23db88c CW |
3640 | return false; |
3641 | } | |
3642 | ||
d0710abb CW |
3643 | void __i915_vma_set_map_and_fenceable(struct i915_vma *vma) |
3644 | { | |
3645 | struct drm_i915_gem_object *obj = vma->obj; | |
a9f1481f | 3646 | struct drm_i915_private *dev_priv = to_i915(obj->base.dev); |
d0710abb CW |
3647 | bool mappable, fenceable; |
3648 | u32 fence_size, fence_alignment; | |
3649 | ||
a9f1481f | 3650 | fence_size = i915_gem_get_ggtt_size(dev_priv, |
ad1a7d20 CW |
3651 | obj->base.size, |
3652 | obj->tiling_mode); | |
a9f1481f | 3653 | fence_alignment = i915_gem_get_ggtt_alignment(dev_priv, |
ad1a7d20 CW |
3654 | obj->base.size, |
3655 | obj->tiling_mode, | |
3656 | true); | |
d0710abb CW |
3657 | |
3658 | fenceable = (vma->node.size == fence_size && | |
3659 | (vma->node.start & (fence_alignment - 1)) == 0); | |
3660 | ||
3661 | mappable = (vma->node.start + fence_size <= | |
a9f1481f | 3662 | dev_priv->ggtt.mappable_end); |
d0710abb CW |
3663 | |
3664 | obj->map_and_fenceable = mappable && fenceable; | |
3665 | } | |
3666 | ||
305bc234 CW |
3667 | int __i915_vma_do_pin(struct i915_vma *vma, |
3668 | u64 size, u64 alignment, u64 flags) | |
673a394b | 3669 | { |
305bc234 | 3670 | unsigned int bound = vma->flags; |
673a394b EA |
3671 | int ret; |
3672 | ||
59bfa124 | 3673 | GEM_BUG_ON((flags & (PIN_GLOBAL | PIN_USER)) == 0); |
3272db53 | 3674 | GEM_BUG_ON((flags & PIN_GLOBAL) && !i915_vma_is_ggtt(vma)); |
d7f46fc4 | 3675 | |
305bc234 CW |
3676 | if (WARN_ON(bound & I915_VMA_PIN_OVERFLOW)) { |
3677 | ret = -EBUSY; | |
3678 | goto err; | |
3679 | } | |
ac0c6b5a | 3680 | |
de895082 | 3681 | if ((bound & I915_VMA_BIND_MASK) == 0) { |
59bfa124 CW |
3682 | ret = i915_vma_insert(vma, size, alignment, flags); |
3683 | if (ret) | |
3684 | goto err; | |
fe14d5f4 | 3685 | } |
74898d7e | 3686 | |
59bfa124 | 3687 | ret = i915_vma_bind(vma, vma->obj->cache_level, flags); |
3b16525c | 3688 | if (ret) |
59bfa124 | 3689 | goto err; |
3b16525c | 3690 | |
3272db53 | 3691 | if ((bound ^ vma->flags) & I915_VMA_GLOBAL_BIND) |
d0710abb | 3692 | __i915_vma_set_map_and_fenceable(vma); |
ef79e17c | 3693 | |
3b16525c | 3694 | GEM_BUG_ON(i915_vma_misplaced(vma, size, alignment, flags)); |
673a394b | 3695 | return 0; |
673a394b | 3696 | |
59bfa124 CW |
3697 | err: |
3698 | __i915_vma_unpin(vma); | |
3699 | return ret; | |
ec7adb6e JL |
3700 | } |
3701 | ||
3702 | int | |
3703 | i915_gem_object_ggtt_pin(struct drm_i915_gem_object *obj, | |
3704 | const struct i915_ggtt_view *view, | |
91b2db6f | 3705 | u64 size, |
2ffffd0f CW |
3706 | u64 alignment, |
3707 | u64 flags) | |
ec7adb6e | 3708 | { |
59bfa124 CW |
3709 | struct i915_vma *vma; |
3710 | int ret; | |
72e96d64 | 3711 | |
de895082 CW |
3712 | if (!view) |
3713 | view = &i915_ggtt_view_normal; | |
ec7adb6e | 3714 | |
59bfa124 CW |
3715 | vma = i915_gem_obj_lookup_or_create_ggtt_vma(obj, view); |
3716 | if (IS_ERR(vma)) | |
3717 | return PTR_ERR(vma); | |
3718 | ||
3719 | if (i915_vma_misplaced(vma, size, alignment, flags)) { | |
3720 | if (flags & PIN_NONBLOCK && | |
3721 | (i915_vma_is_pinned(vma) || i915_vma_is_active(vma))) | |
3722 | return -ENOSPC; | |
3723 | ||
3724 | WARN(i915_vma_is_pinned(vma), | |
3725 | "bo is already pinned in ggtt with incorrect alignment:" | |
3726 | " offset=%08x %08x, req.alignment=%llx, req.map_and_fenceable=%d," | |
3727 | " obj->map_and_fenceable=%d\n", | |
3728 | upper_32_bits(vma->node.start), | |
3729 | lower_32_bits(vma->node.start), | |
3730 | alignment, | |
3731 | !!(flags & PIN_MAPPABLE), | |
3732 | obj->map_and_fenceable); | |
3733 | ret = i915_vma_unbind(vma); | |
3734 | if (ret) | |
3735 | return ret; | |
3736 | } | |
3737 | ||
3738 | return i915_vma_pin(vma, size, alignment, flags | PIN_GLOBAL); | |
ec7adb6e JL |
3739 | } |
3740 | ||
673a394b | 3741 | void |
e6617330 TU |
3742 | i915_gem_object_ggtt_unpin_view(struct drm_i915_gem_object *obj, |
3743 | const struct i915_ggtt_view *view) | |
673a394b | 3744 | { |
de895082 | 3745 | i915_vma_unpin(i915_gem_obj_to_ggtt_view(obj, view)); |
673a394b EA |
3746 | } |
3747 | ||
673a394b EA |
3748 | int |
3749 | i915_gem_busy_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 3750 | struct drm_file *file) |
673a394b EA |
3751 | { |
3752 | struct drm_i915_gem_busy *args = data; | |
05394f39 | 3753 | struct drm_i915_gem_object *obj; |
30dbf0c0 CW |
3754 | int ret; |
3755 | ||
76c1dec1 | 3756 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 3757 | if (ret) |
76c1dec1 | 3758 | return ret; |
673a394b | 3759 | |
03ac0642 CW |
3760 | obj = i915_gem_object_lookup(file, args->handle); |
3761 | if (!obj) { | |
1d7cfea1 CW |
3762 | ret = -ENOENT; |
3763 | goto unlock; | |
673a394b | 3764 | } |
d1b851fc | 3765 | |
0be555b6 CW |
3766 | /* Count all active objects as busy, even if they are currently not used |
3767 | * by the gpu. Users of this interface expect objects to eventually | |
21c310f2 | 3768 | * become non-busy without any further actions. |
c4de0a5d | 3769 | */ |
426960be | 3770 | args->busy = 0; |
573adb39 | 3771 | if (i915_gem_object_is_active(obj)) { |
27c01aae | 3772 | struct drm_i915_gem_request *req; |
426960be CW |
3773 | int i; |
3774 | ||
666796da | 3775 | for (i = 0; i < I915_NUM_ENGINES; i++) { |
d72d908b CW |
3776 | req = i915_gem_active_peek(&obj->last_read[i], |
3777 | &obj->base.dev->struct_mutex); | |
426960be | 3778 | if (req) |
4a570db5 | 3779 | args->busy |= 1 << (16 + req->engine->exec_id); |
426960be | 3780 | } |
d72d908b CW |
3781 | req = i915_gem_active_peek(&obj->last_write, |
3782 | &obj->base.dev->struct_mutex); | |
27c01aae CW |
3783 | if (req) |
3784 | args->busy |= req->engine->exec_id; | |
426960be | 3785 | } |
673a394b | 3786 | |
f8c417cd | 3787 | i915_gem_object_put(obj); |
1d7cfea1 | 3788 | unlock: |
673a394b | 3789 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 3790 | return ret; |
673a394b EA |
3791 | } |
3792 | ||
3793 | int | |
3794 | i915_gem_throttle_ioctl(struct drm_device *dev, void *data, | |
3795 | struct drm_file *file_priv) | |
3796 | { | |
0206e353 | 3797 | return i915_gem_ring_throttle(dev, file_priv); |
673a394b EA |
3798 | } |
3799 | ||
3ef94daa CW |
3800 | int |
3801 | i915_gem_madvise_ioctl(struct drm_device *dev, void *data, | |
3802 | struct drm_file *file_priv) | |
3803 | { | |
fac5e23e | 3804 | struct drm_i915_private *dev_priv = to_i915(dev); |
3ef94daa | 3805 | struct drm_i915_gem_madvise *args = data; |
05394f39 | 3806 | struct drm_i915_gem_object *obj; |
76c1dec1 | 3807 | int ret; |
3ef94daa CW |
3808 | |
3809 | switch (args->madv) { | |
3810 | case I915_MADV_DONTNEED: | |
3811 | case I915_MADV_WILLNEED: | |
3812 | break; | |
3813 | default: | |
3814 | return -EINVAL; | |
3815 | } | |
3816 | ||
1d7cfea1 CW |
3817 | ret = i915_mutex_lock_interruptible(dev); |
3818 | if (ret) | |
3819 | return ret; | |
3820 | ||
03ac0642 CW |
3821 | obj = i915_gem_object_lookup(file_priv, args->handle); |
3822 | if (!obj) { | |
1d7cfea1 CW |
3823 | ret = -ENOENT; |
3824 | goto unlock; | |
3ef94daa | 3825 | } |
3ef94daa | 3826 | |
d7f46fc4 | 3827 | if (i915_gem_obj_is_pinned(obj)) { |
1d7cfea1 CW |
3828 | ret = -EINVAL; |
3829 | goto out; | |
3ef94daa CW |
3830 | } |
3831 | ||
656bfa3a DV |
3832 | if (obj->pages && |
3833 | obj->tiling_mode != I915_TILING_NONE && | |
3834 | dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES) { | |
3835 | if (obj->madv == I915_MADV_WILLNEED) | |
3836 | i915_gem_object_unpin_pages(obj); | |
3837 | if (args->madv == I915_MADV_WILLNEED) | |
3838 | i915_gem_object_pin_pages(obj); | |
3839 | } | |
3840 | ||
05394f39 CW |
3841 | if (obj->madv != __I915_MADV_PURGED) |
3842 | obj->madv = args->madv; | |
3ef94daa | 3843 | |
6c085a72 | 3844 | /* if the object is no longer attached, discard its backing storage */ |
be6a0376 | 3845 | if (obj->madv == I915_MADV_DONTNEED && obj->pages == NULL) |
2d7ef395 CW |
3846 | i915_gem_object_truncate(obj); |
3847 | ||
05394f39 | 3848 | args->retained = obj->madv != __I915_MADV_PURGED; |
bb6baf76 | 3849 | |
1d7cfea1 | 3850 | out: |
f8c417cd | 3851 | i915_gem_object_put(obj); |
1d7cfea1 | 3852 | unlock: |
3ef94daa | 3853 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 3854 | return ret; |
3ef94daa CW |
3855 | } |
3856 | ||
37e680a1 CW |
3857 | void i915_gem_object_init(struct drm_i915_gem_object *obj, |
3858 | const struct drm_i915_gem_object_ops *ops) | |
0327d6ba | 3859 | { |
b4716185 CW |
3860 | int i; |
3861 | ||
35c20a60 | 3862 | INIT_LIST_HEAD(&obj->global_list); |
666796da | 3863 | for (i = 0; i < I915_NUM_ENGINES; i++) |
fa545cbf CW |
3864 | init_request_active(&obj->last_read[i], |
3865 | i915_gem_object_retire__read); | |
3866 | init_request_active(&obj->last_write, | |
3867 | i915_gem_object_retire__write); | |
3868 | init_request_active(&obj->last_fence, NULL); | |
b25cb2f8 | 3869 | INIT_LIST_HEAD(&obj->obj_exec_link); |
2f633156 | 3870 | INIT_LIST_HEAD(&obj->vma_list); |
8d9d5744 | 3871 | INIT_LIST_HEAD(&obj->batch_pool_link); |
0327d6ba | 3872 | |
37e680a1 CW |
3873 | obj->ops = ops; |
3874 | ||
0327d6ba CW |
3875 | obj->fence_reg = I915_FENCE_REG_NONE; |
3876 | obj->madv = I915_MADV_WILLNEED; | |
0327d6ba | 3877 | |
f19ec8cb | 3878 | i915_gem_info_add_obj(to_i915(obj->base.dev), obj->base.size); |
0327d6ba CW |
3879 | } |
3880 | ||
37e680a1 | 3881 | static const struct drm_i915_gem_object_ops i915_gem_object_ops = { |
de472664 | 3882 | .flags = I915_GEM_OBJECT_HAS_STRUCT_PAGE, |
37e680a1 CW |
3883 | .get_pages = i915_gem_object_get_pages_gtt, |
3884 | .put_pages = i915_gem_object_put_pages_gtt, | |
3885 | }; | |
3886 | ||
d37cd8a8 | 3887 | struct drm_i915_gem_object *i915_gem_object_create(struct drm_device *dev, |
05394f39 | 3888 | size_t size) |
ac52bc56 | 3889 | { |
c397b908 | 3890 | struct drm_i915_gem_object *obj; |
5949eac4 | 3891 | struct address_space *mapping; |
1a240d4d | 3892 | gfp_t mask; |
fe3db79b | 3893 | int ret; |
ac52bc56 | 3894 | |
42dcedd4 | 3895 | obj = i915_gem_object_alloc(dev); |
c397b908 | 3896 | if (obj == NULL) |
fe3db79b | 3897 | return ERR_PTR(-ENOMEM); |
673a394b | 3898 | |
fe3db79b CW |
3899 | ret = drm_gem_object_init(dev, &obj->base, size); |
3900 | if (ret) | |
3901 | goto fail; | |
673a394b | 3902 | |
bed1ea95 CW |
3903 | mask = GFP_HIGHUSER | __GFP_RECLAIMABLE; |
3904 | if (IS_CRESTLINE(dev) || IS_BROADWATER(dev)) { | |
3905 | /* 965gm cannot relocate objects above 4GiB. */ | |
3906 | mask &= ~__GFP_HIGHMEM; | |
3907 | mask |= __GFP_DMA32; | |
3908 | } | |
3909 | ||
496ad9aa | 3910 | mapping = file_inode(obj->base.filp)->i_mapping; |
bed1ea95 | 3911 | mapping_set_gfp_mask(mapping, mask); |
5949eac4 | 3912 | |
37e680a1 | 3913 | i915_gem_object_init(obj, &i915_gem_object_ops); |
73aa808f | 3914 | |
c397b908 DV |
3915 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; |
3916 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; | |
673a394b | 3917 | |
3d29b842 ED |
3918 | if (HAS_LLC(dev)) { |
3919 | /* On some devices, we can have the GPU use the LLC (the CPU | |
a1871112 EA |
3920 | * cache) for about a 10% performance improvement |
3921 | * compared to uncached. Graphics requests other than | |
3922 | * display scanout are coherent with the CPU in | |
3923 | * accessing this cache. This means in this mode we | |
3924 | * don't need to clflush on the CPU side, and on the | |
3925 | * GPU side we only need to flush internal caches to | |
3926 | * get data visible to the CPU. | |
3927 | * | |
3928 | * However, we maintain the display planes as UC, and so | |
3929 | * need to rebind when first used as such. | |
3930 | */ | |
3931 | obj->cache_level = I915_CACHE_LLC; | |
3932 | } else | |
3933 | obj->cache_level = I915_CACHE_NONE; | |
3934 | ||
d861e338 DV |
3935 | trace_i915_gem_object_create(obj); |
3936 | ||
05394f39 | 3937 | return obj; |
fe3db79b CW |
3938 | |
3939 | fail: | |
3940 | i915_gem_object_free(obj); | |
3941 | ||
3942 | return ERR_PTR(ret); | |
c397b908 DV |
3943 | } |
3944 | ||
340fbd8c CW |
3945 | static bool discard_backing_storage(struct drm_i915_gem_object *obj) |
3946 | { | |
3947 | /* If we are the last user of the backing storage (be it shmemfs | |
3948 | * pages or stolen etc), we know that the pages are going to be | |
3949 | * immediately released. In this case, we can then skip copying | |
3950 | * back the contents from the GPU. | |
3951 | */ | |
3952 | ||
3953 | if (obj->madv != I915_MADV_WILLNEED) | |
3954 | return false; | |
3955 | ||
3956 | if (obj->base.filp == NULL) | |
3957 | return true; | |
3958 | ||
3959 | /* At first glance, this looks racy, but then again so would be | |
3960 | * userspace racing mmap against close. However, the first external | |
3961 | * reference to the filp can only be obtained through the | |
3962 | * i915_gem_mmap_ioctl() which safeguards us against the user | |
3963 | * acquiring such a reference whilst we are in the middle of | |
3964 | * freeing the object. | |
3965 | */ | |
3966 | return atomic_long_read(&obj->base.filp->f_count) == 1; | |
3967 | } | |
3968 | ||
1488fc08 | 3969 | void i915_gem_free_object(struct drm_gem_object *gem_obj) |
673a394b | 3970 | { |
1488fc08 | 3971 | struct drm_i915_gem_object *obj = to_intel_bo(gem_obj); |
05394f39 | 3972 | struct drm_device *dev = obj->base.dev; |
fac5e23e | 3973 | struct drm_i915_private *dev_priv = to_i915(dev); |
07fe0b12 | 3974 | struct i915_vma *vma, *next; |
673a394b | 3975 | |
f65c9168 PZ |
3976 | intel_runtime_pm_get(dev_priv); |
3977 | ||
26e12f89 CW |
3978 | trace_i915_gem_object_destroy(obj); |
3979 | ||
b1f788c6 CW |
3980 | /* All file-owned VMA should have been released by this point through |
3981 | * i915_gem_close_object(), or earlier by i915_gem_context_close(). | |
3982 | * However, the object may also be bound into the global GTT (e.g. | |
3983 | * older GPUs without per-process support, or for direct access through | |
3984 | * the GTT either for the user or for scanout). Those VMA still need to | |
3985 | * unbound now. | |
3986 | */ | |
1c7f4bca | 3987 | list_for_each_entry_safe(vma, next, &obj->vma_list, obj_link) { |
3272db53 | 3988 | GEM_BUG_ON(!i915_vma_is_ggtt(vma)); |
b1f788c6 | 3989 | GEM_BUG_ON(i915_vma_is_active(vma)); |
3272db53 | 3990 | vma->flags &= ~I915_VMA_PIN_MASK; |
b1f788c6 | 3991 | i915_vma_close(vma); |
1488fc08 | 3992 | } |
15717de2 | 3993 | GEM_BUG_ON(obj->bind_count); |
1488fc08 | 3994 | |
1d64ae71 BW |
3995 | /* Stolen objects don't hold a ref, but do hold pin count. Fix that up |
3996 | * before progressing. */ | |
3997 | if (obj->stolen) | |
3998 | i915_gem_object_unpin_pages(obj); | |
3999 | ||
faf5bf0a | 4000 | WARN_ON(atomic_read(&obj->frontbuffer_bits)); |
a071fa00 | 4001 | |
656bfa3a DV |
4002 | if (obj->pages && obj->madv == I915_MADV_WILLNEED && |
4003 | dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES && | |
4004 | obj->tiling_mode != I915_TILING_NONE) | |
4005 | i915_gem_object_unpin_pages(obj); | |
4006 | ||
401c29f6 BW |
4007 | if (WARN_ON(obj->pages_pin_count)) |
4008 | obj->pages_pin_count = 0; | |
340fbd8c | 4009 | if (discard_backing_storage(obj)) |
5537252b | 4010 | obj->madv = I915_MADV_DONTNEED; |
37e680a1 | 4011 | i915_gem_object_put_pages(obj); |
de151cf6 | 4012 | |
9da3da66 CW |
4013 | BUG_ON(obj->pages); |
4014 | ||
2f745ad3 CW |
4015 | if (obj->base.import_attach) |
4016 | drm_prime_gem_destroy(&obj->base, NULL); | |
de151cf6 | 4017 | |
5cc9ed4b CW |
4018 | if (obj->ops->release) |
4019 | obj->ops->release(obj); | |
4020 | ||
05394f39 CW |
4021 | drm_gem_object_release(&obj->base); |
4022 | i915_gem_info_remove_obj(dev_priv, obj->base.size); | |
c397b908 | 4023 | |
05394f39 | 4024 | kfree(obj->bit_17); |
42dcedd4 | 4025 | i915_gem_object_free(obj); |
f65c9168 PZ |
4026 | |
4027 | intel_runtime_pm_put(dev_priv); | |
673a394b EA |
4028 | } |
4029 | ||
ec7adb6e JL |
4030 | struct i915_vma *i915_gem_obj_to_vma(struct drm_i915_gem_object *obj, |
4031 | struct i915_address_space *vm) | |
e656a6cb DV |
4032 | { |
4033 | struct i915_vma *vma; | |
1c7f4bca | 4034 | list_for_each_entry(vma, &obj->vma_list, obj_link) { |
1b683729 TU |
4035 | if (vma->ggtt_view.type == I915_GGTT_VIEW_NORMAL && |
4036 | vma->vm == vm) | |
e656a6cb | 4037 | return vma; |
ec7adb6e JL |
4038 | } |
4039 | return NULL; | |
4040 | } | |
4041 | ||
4042 | struct i915_vma *i915_gem_obj_to_ggtt_view(struct drm_i915_gem_object *obj, | |
4043 | const struct i915_ggtt_view *view) | |
4044 | { | |
ec7adb6e | 4045 | struct i915_vma *vma; |
e656a6cb | 4046 | |
598b9ec8 | 4047 | GEM_BUG_ON(!view); |
ec7adb6e | 4048 | |
1c7f4bca | 4049 | list_for_each_entry(vma, &obj->vma_list, obj_link) |
3272db53 CW |
4050 | if (i915_vma_is_ggtt(vma) && |
4051 | i915_ggtt_view_equal(&vma->ggtt_view, view)) | |
ec7adb6e | 4052 | return vma; |
e656a6cb DV |
4053 | return NULL; |
4054 | } | |
4055 | ||
dcff85c8 | 4056 | int i915_gem_suspend(struct drm_device *dev) |
29105ccc | 4057 | { |
fac5e23e | 4058 | struct drm_i915_private *dev_priv = to_i915(dev); |
dcff85c8 | 4059 | int ret; |
28dfe52a | 4060 | |
54b4f68f CW |
4061 | intel_suspend_gt_powersave(dev_priv); |
4062 | ||
45c5f202 | 4063 | mutex_lock(&dev->struct_mutex); |
5ab57c70 CW |
4064 | |
4065 | /* We have to flush all the executing contexts to main memory so | |
4066 | * that they can saved in the hibernation image. To ensure the last | |
4067 | * context image is coherent, we have to switch away from it. That | |
4068 | * leaves the dev_priv->kernel_context still active when | |
4069 | * we actually suspend, and its image in memory may not match the GPU | |
4070 | * state. Fortunately, the kernel_context is disposable and we do | |
4071 | * not rely on its state. | |
4072 | */ | |
4073 | ret = i915_gem_switch_to_kernel_context(dev_priv); | |
4074 | if (ret) | |
4075 | goto err; | |
4076 | ||
dcff85c8 | 4077 | ret = i915_gem_wait_for_idle(dev_priv, true); |
f7403347 | 4078 | if (ret) |
45c5f202 | 4079 | goto err; |
f7403347 | 4080 | |
c033666a | 4081 | i915_gem_retire_requests(dev_priv); |
673a394b | 4082 | |
b2e862d0 | 4083 | i915_gem_context_lost(dev_priv); |
45c5f202 CW |
4084 | mutex_unlock(&dev->struct_mutex); |
4085 | ||
737b1506 | 4086 | cancel_delayed_work_sync(&dev_priv->gpu_error.hangcheck_work); |
67d97da3 CW |
4087 | cancel_delayed_work_sync(&dev_priv->gt.retire_work); |
4088 | flush_delayed_work(&dev_priv->gt.idle_work); | |
29105ccc | 4089 | |
bdcf120b CW |
4090 | /* Assert that we sucessfully flushed all the work and |
4091 | * reset the GPU back to its idle, low power state. | |
4092 | */ | |
67d97da3 | 4093 | WARN_ON(dev_priv->gt.awake); |
bdcf120b | 4094 | |
673a394b | 4095 | return 0; |
45c5f202 CW |
4096 | |
4097 | err: | |
4098 | mutex_unlock(&dev->struct_mutex); | |
4099 | return ret; | |
673a394b EA |
4100 | } |
4101 | ||
5ab57c70 CW |
4102 | void i915_gem_resume(struct drm_device *dev) |
4103 | { | |
4104 | struct drm_i915_private *dev_priv = to_i915(dev); | |
4105 | ||
4106 | mutex_lock(&dev->struct_mutex); | |
4107 | i915_gem_restore_gtt_mappings(dev); | |
4108 | ||
4109 | /* As we didn't flush the kernel context before suspend, we cannot | |
4110 | * guarantee that the context image is complete. So let's just reset | |
4111 | * it and start again. | |
4112 | */ | |
4113 | if (i915.enable_execlists) | |
4114 | intel_lr_context_reset(dev_priv, dev_priv->kernel_context); | |
4115 | ||
4116 | mutex_unlock(&dev->struct_mutex); | |
4117 | } | |
4118 | ||
f691e2f4 DV |
4119 | void i915_gem_init_swizzling(struct drm_device *dev) |
4120 | { | |
fac5e23e | 4121 | struct drm_i915_private *dev_priv = to_i915(dev); |
f691e2f4 | 4122 | |
11782b02 | 4123 | if (INTEL_INFO(dev)->gen < 5 || |
f691e2f4 DV |
4124 | dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE) |
4125 | return; | |
4126 | ||
4127 | I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) | | |
4128 | DISP_TILE_SURFACE_SWIZZLING); | |
4129 | ||
11782b02 DV |
4130 | if (IS_GEN5(dev)) |
4131 | return; | |
4132 | ||
f691e2f4 DV |
4133 | I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_SWZCTL); |
4134 | if (IS_GEN6(dev)) | |
6b26c86d | 4135 | I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB)); |
8782e26c | 4136 | else if (IS_GEN7(dev)) |
6b26c86d | 4137 | I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB)); |
31a5336e BW |
4138 | else if (IS_GEN8(dev)) |
4139 | I915_WRITE(GAMTARBMODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_BDW)); | |
8782e26c BW |
4140 | else |
4141 | BUG(); | |
f691e2f4 | 4142 | } |
e21af88d | 4143 | |
81e7f200 VS |
4144 | static void init_unused_ring(struct drm_device *dev, u32 base) |
4145 | { | |
fac5e23e | 4146 | struct drm_i915_private *dev_priv = to_i915(dev); |
81e7f200 VS |
4147 | |
4148 | I915_WRITE(RING_CTL(base), 0); | |
4149 | I915_WRITE(RING_HEAD(base), 0); | |
4150 | I915_WRITE(RING_TAIL(base), 0); | |
4151 | I915_WRITE(RING_START(base), 0); | |
4152 | } | |
4153 | ||
4154 | static void init_unused_rings(struct drm_device *dev) | |
4155 | { | |
4156 | if (IS_I830(dev)) { | |
4157 | init_unused_ring(dev, PRB1_BASE); | |
4158 | init_unused_ring(dev, SRB0_BASE); | |
4159 | init_unused_ring(dev, SRB1_BASE); | |
4160 | init_unused_ring(dev, SRB2_BASE); | |
4161 | init_unused_ring(dev, SRB3_BASE); | |
4162 | } else if (IS_GEN2(dev)) { | |
4163 | init_unused_ring(dev, SRB0_BASE); | |
4164 | init_unused_ring(dev, SRB1_BASE); | |
4165 | } else if (IS_GEN3(dev)) { | |
4166 | init_unused_ring(dev, PRB1_BASE); | |
4167 | init_unused_ring(dev, PRB2_BASE); | |
4168 | } | |
4169 | } | |
4170 | ||
4fc7c971 BW |
4171 | int |
4172 | i915_gem_init_hw(struct drm_device *dev) | |
4173 | { | |
fac5e23e | 4174 | struct drm_i915_private *dev_priv = to_i915(dev); |
e2f80391 | 4175 | struct intel_engine_cs *engine; |
d200cda6 | 4176 | int ret; |
4fc7c971 | 4177 | |
5e4f5189 CW |
4178 | /* Double layer security blanket, see i915_gem_init() */ |
4179 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); | |
4180 | ||
3accaf7e | 4181 | if (HAS_EDRAM(dev) && INTEL_GEN(dev_priv) < 9) |
05e21cc4 | 4182 | I915_WRITE(HSW_IDICR, I915_READ(HSW_IDICR) | IDIHASHMSK(0xf)); |
4fc7c971 | 4183 | |
0bf21347 VS |
4184 | if (IS_HASWELL(dev)) |
4185 | I915_WRITE(MI_PREDICATE_RESULT_2, IS_HSW_GT3(dev) ? | |
4186 | LOWER_SLICE_ENABLED : LOWER_SLICE_DISABLED); | |
9435373e | 4187 | |
88a2b2a3 | 4188 | if (HAS_PCH_NOP(dev)) { |
6ba844b0 DV |
4189 | if (IS_IVYBRIDGE(dev)) { |
4190 | u32 temp = I915_READ(GEN7_MSG_CTL); | |
4191 | temp &= ~(WAIT_FOR_PCH_FLR_ACK | WAIT_FOR_PCH_RESET_ACK); | |
4192 | I915_WRITE(GEN7_MSG_CTL, temp); | |
4193 | } else if (INTEL_INFO(dev)->gen >= 7) { | |
4194 | u32 temp = I915_READ(HSW_NDE_RSTWRN_OPT); | |
4195 | temp &= ~RESET_PCH_HANDSHAKE_ENABLE; | |
4196 | I915_WRITE(HSW_NDE_RSTWRN_OPT, temp); | |
4197 | } | |
88a2b2a3 BW |
4198 | } |
4199 | ||
4fc7c971 BW |
4200 | i915_gem_init_swizzling(dev); |
4201 | ||
d5abdfda DV |
4202 | /* |
4203 | * At least 830 can leave some of the unused rings | |
4204 | * "active" (ie. head != tail) after resume which | |
4205 | * will prevent c3 entry. Makes sure all unused rings | |
4206 | * are totally idle. | |
4207 | */ | |
4208 | init_unused_rings(dev); | |
4209 | ||
ed54c1a1 | 4210 | BUG_ON(!dev_priv->kernel_context); |
90638cc1 | 4211 | |
4ad2fd88 JH |
4212 | ret = i915_ppgtt_init_hw(dev); |
4213 | if (ret) { | |
4214 | DRM_ERROR("PPGTT enable HW failed %d\n", ret); | |
4215 | goto out; | |
4216 | } | |
4217 | ||
4218 | /* Need to do basic initialisation of all rings first: */ | |
b4ac5afc | 4219 | for_each_engine(engine, dev_priv) { |
e2f80391 | 4220 | ret = engine->init_hw(engine); |
35a57ffb | 4221 | if (ret) |
5e4f5189 | 4222 | goto out; |
35a57ffb | 4223 | } |
99433931 | 4224 | |
0ccdacf6 PA |
4225 | intel_mocs_init_l3cc_table(dev); |
4226 | ||
33a732f4 | 4227 | /* We can't enable contexts until all firmware is loaded */ |
e556f7c1 DG |
4228 | ret = intel_guc_setup(dev); |
4229 | if (ret) | |
4230 | goto out; | |
33a732f4 | 4231 | |
5e4f5189 CW |
4232 | out: |
4233 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); | |
2fa48d8d | 4234 | return ret; |
8187a2b7 ZN |
4235 | } |
4236 | ||
39df9190 CW |
4237 | bool intel_sanitize_semaphores(struct drm_i915_private *dev_priv, int value) |
4238 | { | |
4239 | if (INTEL_INFO(dev_priv)->gen < 6) | |
4240 | return false; | |
4241 | ||
4242 | /* TODO: make semaphores and Execlists play nicely together */ | |
4243 | if (i915.enable_execlists) | |
4244 | return false; | |
4245 | ||
4246 | if (value >= 0) | |
4247 | return value; | |
4248 | ||
4249 | #ifdef CONFIG_INTEL_IOMMU | |
4250 | /* Enable semaphores on SNB when IO remapping is off */ | |
4251 | if (INTEL_INFO(dev_priv)->gen == 6 && intel_iommu_gfx_mapped) | |
4252 | return false; | |
4253 | #endif | |
4254 | ||
4255 | return true; | |
4256 | } | |
4257 | ||
1070a42b CW |
4258 | int i915_gem_init(struct drm_device *dev) |
4259 | { | |
fac5e23e | 4260 | struct drm_i915_private *dev_priv = to_i915(dev); |
1070a42b CW |
4261 | int ret; |
4262 | ||
1070a42b | 4263 | mutex_lock(&dev->struct_mutex); |
d62b4892 | 4264 | |
a83014d3 | 4265 | if (!i915.enable_execlists) { |
7e37f889 | 4266 | dev_priv->gt.cleanup_engine = intel_engine_cleanup; |
454afebd | 4267 | } else { |
117897f4 | 4268 | dev_priv->gt.cleanup_engine = intel_logical_ring_cleanup; |
a83014d3 OM |
4269 | } |
4270 | ||
5e4f5189 CW |
4271 | /* This is just a security blanket to placate dragons. |
4272 | * On some systems, we very sporadically observe that the first TLBs | |
4273 | * used by the CS may be stale, despite us poking the TLB reset. If | |
4274 | * we hold the forcewake during initialisation these problems | |
4275 | * just magically go away. | |
4276 | */ | |
4277 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); | |
4278 | ||
72778cb2 | 4279 | i915_gem_init_userptr(dev_priv); |
f6b9d5ca CW |
4280 | |
4281 | ret = i915_gem_init_ggtt(dev_priv); | |
4282 | if (ret) | |
4283 | goto out_unlock; | |
d62b4892 | 4284 | |
2fa48d8d | 4285 | ret = i915_gem_context_init(dev); |
7bcc3777 JN |
4286 | if (ret) |
4287 | goto out_unlock; | |
2fa48d8d | 4288 | |
8b3e2d36 | 4289 | ret = intel_engines_init(dev); |
35a57ffb | 4290 | if (ret) |
7bcc3777 | 4291 | goto out_unlock; |
2fa48d8d | 4292 | |
1070a42b | 4293 | ret = i915_gem_init_hw(dev); |
60990320 | 4294 | if (ret == -EIO) { |
7e21d648 | 4295 | /* Allow engine initialisation to fail by marking the GPU as |
60990320 CW |
4296 | * wedged. But we only want to do this where the GPU is angry, |
4297 | * for all other failure, such as an allocation failure, bail. | |
4298 | */ | |
4299 | DRM_ERROR("Failed to initialize GPU, declaring it wedged\n"); | |
805de8f4 | 4300 | atomic_or(I915_WEDGED, &dev_priv->gpu_error.reset_counter); |
60990320 | 4301 | ret = 0; |
1070a42b | 4302 | } |
7bcc3777 JN |
4303 | |
4304 | out_unlock: | |
5e4f5189 | 4305 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); |
60990320 | 4306 | mutex_unlock(&dev->struct_mutex); |
1070a42b | 4307 | |
60990320 | 4308 | return ret; |
1070a42b CW |
4309 | } |
4310 | ||
8187a2b7 | 4311 | void |
117897f4 | 4312 | i915_gem_cleanup_engines(struct drm_device *dev) |
8187a2b7 | 4313 | { |
fac5e23e | 4314 | struct drm_i915_private *dev_priv = to_i915(dev); |
e2f80391 | 4315 | struct intel_engine_cs *engine; |
8187a2b7 | 4316 | |
b4ac5afc | 4317 | for_each_engine(engine, dev_priv) |
117897f4 | 4318 | dev_priv->gt.cleanup_engine(engine); |
8187a2b7 ZN |
4319 | } |
4320 | ||
64193406 | 4321 | static void |
666796da | 4322 | init_engine_lists(struct intel_engine_cs *engine) |
64193406 | 4323 | { |
0bc40be8 | 4324 | INIT_LIST_HEAD(&engine->request_list); |
64193406 CW |
4325 | } |
4326 | ||
40ae4e16 ID |
4327 | void |
4328 | i915_gem_load_init_fences(struct drm_i915_private *dev_priv) | |
4329 | { | |
91c8a326 | 4330 | struct drm_device *dev = &dev_priv->drm; |
40ae4e16 ID |
4331 | |
4332 | if (INTEL_INFO(dev_priv)->gen >= 7 && !IS_VALLEYVIEW(dev_priv) && | |
4333 | !IS_CHERRYVIEW(dev_priv)) | |
4334 | dev_priv->num_fence_regs = 32; | |
4335 | else if (INTEL_INFO(dev_priv)->gen >= 4 || IS_I945G(dev_priv) || | |
4336 | IS_I945GM(dev_priv) || IS_G33(dev_priv)) | |
4337 | dev_priv->num_fence_regs = 16; | |
4338 | else | |
4339 | dev_priv->num_fence_regs = 8; | |
4340 | ||
c033666a | 4341 | if (intel_vgpu_active(dev_priv)) |
40ae4e16 ID |
4342 | dev_priv->num_fence_regs = |
4343 | I915_READ(vgtif_reg(avail_rs.fence_num)); | |
4344 | ||
4345 | /* Initialize fence registers to zero */ | |
4346 | i915_gem_restore_fences(dev); | |
4347 | ||
4348 | i915_gem_detect_bit_6_swizzle(dev); | |
4349 | } | |
4350 | ||
673a394b | 4351 | void |
d64aa096 | 4352 | i915_gem_load_init(struct drm_device *dev) |
673a394b | 4353 | { |
fac5e23e | 4354 | struct drm_i915_private *dev_priv = to_i915(dev); |
42dcedd4 CW |
4355 | int i; |
4356 | ||
efab6d8d | 4357 | dev_priv->objects = |
42dcedd4 CW |
4358 | kmem_cache_create("i915_gem_object", |
4359 | sizeof(struct drm_i915_gem_object), 0, | |
4360 | SLAB_HWCACHE_ALIGN, | |
4361 | NULL); | |
e20d2ab7 CW |
4362 | dev_priv->vmas = |
4363 | kmem_cache_create("i915_gem_vma", | |
4364 | sizeof(struct i915_vma), 0, | |
4365 | SLAB_HWCACHE_ALIGN, | |
4366 | NULL); | |
efab6d8d CW |
4367 | dev_priv->requests = |
4368 | kmem_cache_create("i915_gem_request", | |
4369 | sizeof(struct drm_i915_gem_request), 0, | |
0eafec6d CW |
4370 | SLAB_HWCACHE_ALIGN | |
4371 | SLAB_RECLAIM_ACCOUNT | | |
4372 | SLAB_DESTROY_BY_RCU, | |
efab6d8d | 4373 | NULL); |
673a394b | 4374 | |
a33afea5 | 4375 | INIT_LIST_HEAD(&dev_priv->context_list); |
6c085a72 CW |
4376 | INIT_LIST_HEAD(&dev_priv->mm.unbound_list); |
4377 | INIT_LIST_HEAD(&dev_priv->mm.bound_list); | |
a09ba7fa | 4378 | INIT_LIST_HEAD(&dev_priv->mm.fence_list); |
666796da TU |
4379 | for (i = 0; i < I915_NUM_ENGINES; i++) |
4380 | init_engine_lists(&dev_priv->engine[i]); | |
4b9de737 | 4381 | for (i = 0; i < I915_MAX_NUM_FENCES; i++) |
007cc8ac | 4382 | INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list); |
67d97da3 | 4383 | INIT_DELAYED_WORK(&dev_priv->gt.retire_work, |
673a394b | 4384 | i915_gem_retire_work_handler); |
67d97da3 | 4385 | INIT_DELAYED_WORK(&dev_priv->gt.idle_work, |
b29c19b6 | 4386 | i915_gem_idle_work_handler); |
1f15b76f | 4387 | init_waitqueue_head(&dev_priv->gpu_error.wait_queue); |
1f83fee0 | 4388 | init_waitqueue_head(&dev_priv->gpu_error.reset_queue); |
31169714 | 4389 | |
72bfa19c CW |
4390 | dev_priv->relative_constants_mode = I915_EXEC_CONSTANTS_REL_GENERAL; |
4391 | ||
19b2dbde | 4392 | INIT_LIST_HEAD(&dev_priv->mm.fence_list); |
10ed13e4 | 4393 | |
6b95a207 | 4394 | init_waitqueue_head(&dev_priv->pending_flip_queue); |
17250b71 | 4395 | |
ce453d81 CW |
4396 | dev_priv->mm.interruptible = true; |
4397 | ||
b5add959 | 4398 | spin_lock_init(&dev_priv->fb_tracking.lock); |
673a394b | 4399 | } |
71acb5eb | 4400 | |
d64aa096 ID |
4401 | void i915_gem_load_cleanup(struct drm_device *dev) |
4402 | { | |
4403 | struct drm_i915_private *dev_priv = to_i915(dev); | |
4404 | ||
4405 | kmem_cache_destroy(dev_priv->requests); | |
4406 | kmem_cache_destroy(dev_priv->vmas); | |
4407 | kmem_cache_destroy(dev_priv->objects); | |
0eafec6d CW |
4408 | |
4409 | /* And ensure that our DESTROY_BY_RCU slabs are truly destroyed */ | |
4410 | rcu_barrier(); | |
d64aa096 ID |
4411 | } |
4412 | ||
461fb99c CW |
4413 | int i915_gem_freeze_late(struct drm_i915_private *dev_priv) |
4414 | { | |
4415 | struct drm_i915_gem_object *obj; | |
4416 | ||
4417 | /* Called just before we write the hibernation image. | |
4418 | * | |
4419 | * We need to update the domain tracking to reflect that the CPU | |
4420 | * will be accessing all the pages to create and restore from the | |
4421 | * hibernation, and so upon restoration those pages will be in the | |
4422 | * CPU domain. | |
4423 | * | |
4424 | * To make sure the hibernation image contains the latest state, | |
4425 | * we update that state just before writing out the image. | |
4426 | */ | |
4427 | ||
4428 | list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) { | |
4429 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; | |
4430 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; | |
4431 | } | |
4432 | ||
4433 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) { | |
4434 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; | |
4435 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; | |
4436 | } | |
4437 | ||
4438 | return 0; | |
4439 | } | |
4440 | ||
f787a5f5 | 4441 | void i915_gem_release(struct drm_device *dev, struct drm_file *file) |
b962442e | 4442 | { |
f787a5f5 | 4443 | struct drm_i915_file_private *file_priv = file->driver_priv; |
15f7bbc7 | 4444 | struct drm_i915_gem_request *request; |
b962442e EA |
4445 | |
4446 | /* Clean up our request list when the client is going away, so that | |
4447 | * later retire_requests won't dereference our soon-to-be-gone | |
4448 | * file_priv. | |
4449 | */ | |
1c25595f | 4450 | spin_lock(&file_priv->mm.lock); |
15f7bbc7 | 4451 | list_for_each_entry(request, &file_priv->mm.request_list, client_list) |
f787a5f5 | 4452 | request->file_priv = NULL; |
1c25595f | 4453 | spin_unlock(&file_priv->mm.lock); |
b29c19b6 | 4454 | |
2e1b8730 | 4455 | if (!list_empty(&file_priv->rps.link)) { |
8d3afd7d | 4456 | spin_lock(&to_i915(dev)->rps.client_lock); |
2e1b8730 | 4457 | list_del(&file_priv->rps.link); |
8d3afd7d | 4458 | spin_unlock(&to_i915(dev)->rps.client_lock); |
1854d5ca | 4459 | } |
b29c19b6 CW |
4460 | } |
4461 | ||
4462 | int i915_gem_open(struct drm_device *dev, struct drm_file *file) | |
4463 | { | |
4464 | struct drm_i915_file_private *file_priv; | |
e422b888 | 4465 | int ret; |
b29c19b6 CW |
4466 | |
4467 | DRM_DEBUG_DRIVER("\n"); | |
4468 | ||
4469 | file_priv = kzalloc(sizeof(*file_priv), GFP_KERNEL); | |
4470 | if (!file_priv) | |
4471 | return -ENOMEM; | |
4472 | ||
4473 | file->driver_priv = file_priv; | |
f19ec8cb | 4474 | file_priv->dev_priv = to_i915(dev); |
ab0e7ff9 | 4475 | file_priv->file = file; |
2e1b8730 | 4476 | INIT_LIST_HEAD(&file_priv->rps.link); |
b29c19b6 CW |
4477 | |
4478 | spin_lock_init(&file_priv->mm.lock); | |
4479 | INIT_LIST_HEAD(&file_priv->mm.request_list); | |
b29c19b6 | 4480 | |
c80ff16e | 4481 | file_priv->bsd_engine = -1; |
de1add36 | 4482 | |
e422b888 BW |
4483 | ret = i915_gem_context_open(dev, file); |
4484 | if (ret) | |
4485 | kfree(file_priv); | |
b29c19b6 | 4486 | |
e422b888 | 4487 | return ret; |
b29c19b6 CW |
4488 | } |
4489 | ||
b680c37a DV |
4490 | /** |
4491 | * i915_gem_track_fb - update frontbuffer tracking | |
d9072a3e GT |
4492 | * @old: current GEM buffer for the frontbuffer slots |
4493 | * @new: new GEM buffer for the frontbuffer slots | |
4494 | * @frontbuffer_bits: bitmask of frontbuffer slots | |
b680c37a DV |
4495 | * |
4496 | * This updates the frontbuffer tracking bits @frontbuffer_bits by clearing them | |
4497 | * from @old and setting them in @new. Both @old and @new can be NULL. | |
4498 | */ | |
a071fa00 DV |
4499 | void i915_gem_track_fb(struct drm_i915_gem_object *old, |
4500 | struct drm_i915_gem_object *new, | |
4501 | unsigned frontbuffer_bits) | |
4502 | { | |
faf5bf0a CW |
4503 | /* Control of individual bits within the mask are guarded by |
4504 | * the owning plane->mutex, i.e. we can never see concurrent | |
4505 | * manipulation of individual bits. But since the bitfield as a whole | |
4506 | * is updated using RMW, we need to use atomics in order to update | |
4507 | * the bits. | |
4508 | */ | |
4509 | BUILD_BUG_ON(INTEL_FRONTBUFFER_BITS_PER_PIPE * I915_MAX_PIPES > | |
4510 | sizeof(atomic_t) * BITS_PER_BYTE); | |
4511 | ||
a071fa00 | 4512 | if (old) { |
faf5bf0a CW |
4513 | WARN_ON(!(atomic_read(&old->frontbuffer_bits) & frontbuffer_bits)); |
4514 | atomic_andnot(frontbuffer_bits, &old->frontbuffer_bits); | |
a071fa00 DV |
4515 | } |
4516 | ||
4517 | if (new) { | |
faf5bf0a CW |
4518 | WARN_ON(atomic_read(&new->frontbuffer_bits) & frontbuffer_bits); |
4519 | atomic_or(frontbuffer_bits, &new->frontbuffer_bits); | |
a071fa00 DV |
4520 | } |
4521 | } | |
4522 | ||
a70a3148 | 4523 | /* All the new VM stuff */ |
088e0df4 MT |
4524 | u64 i915_gem_obj_offset(struct drm_i915_gem_object *o, |
4525 | struct i915_address_space *vm) | |
a70a3148 | 4526 | { |
fac5e23e | 4527 | struct drm_i915_private *dev_priv = to_i915(o->base.dev); |
a70a3148 BW |
4528 | struct i915_vma *vma; |
4529 | ||
896ab1a5 | 4530 | WARN_ON(vm == &dev_priv->mm.aliasing_ppgtt->base); |
a70a3148 | 4531 | |
1c7f4bca | 4532 | list_for_each_entry(vma, &o->vma_list, obj_link) { |
3272db53 | 4533 | if (i915_vma_is_ggtt(vma) && |
ec7adb6e JL |
4534 | vma->ggtt_view.type != I915_GGTT_VIEW_NORMAL) |
4535 | continue; | |
4536 | if (vma->vm == vm) | |
a70a3148 | 4537 | return vma->node.start; |
a70a3148 | 4538 | } |
ec7adb6e | 4539 | |
f25748ea DV |
4540 | WARN(1, "%s vma for this object not found.\n", |
4541 | i915_is_ggtt(vm) ? "global" : "ppgtt"); | |
a70a3148 BW |
4542 | return -1; |
4543 | } | |
4544 | ||
088e0df4 MT |
4545 | u64 i915_gem_obj_ggtt_offset_view(struct drm_i915_gem_object *o, |
4546 | const struct i915_ggtt_view *view) | |
a70a3148 BW |
4547 | { |
4548 | struct i915_vma *vma; | |
4549 | ||
1c7f4bca | 4550 | list_for_each_entry(vma, &o->vma_list, obj_link) |
3272db53 CW |
4551 | if (i915_vma_is_ggtt(vma) && |
4552 | i915_ggtt_view_equal(&vma->ggtt_view, view)) | |
ec7adb6e JL |
4553 | return vma->node.start; |
4554 | ||
5678ad73 | 4555 | WARN(1, "global vma for this object not found. (view=%u)\n", view->type); |
ec7adb6e JL |
4556 | return -1; |
4557 | } | |
4558 | ||
4559 | bool i915_gem_obj_bound(struct drm_i915_gem_object *o, | |
4560 | struct i915_address_space *vm) | |
4561 | { | |
4562 | struct i915_vma *vma; | |
4563 | ||
1c7f4bca | 4564 | list_for_each_entry(vma, &o->vma_list, obj_link) { |
3272db53 | 4565 | if (i915_vma_is_ggtt(vma) && |
ec7adb6e JL |
4566 | vma->ggtt_view.type != I915_GGTT_VIEW_NORMAL) |
4567 | continue; | |
4568 | if (vma->vm == vm && drm_mm_node_allocated(&vma->node)) | |
4569 | return true; | |
4570 | } | |
4571 | ||
4572 | return false; | |
4573 | } | |
4574 | ||
4575 | bool i915_gem_obj_ggtt_bound_view(struct drm_i915_gem_object *o, | |
9abc4648 | 4576 | const struct i915_ggtt_view *view) |
ec7adb6e | 4577 | { |
ec7adb6e JL |
4578 | struct i915_vma *vma; |
4579 | ||
1c7f4bca | 4580 | list_for_each_entry(vma, &o->vma_list, obj_link) |
3272db53 | 4581 | if (i915_vma_is_ggtt(vma) && |
9abc4648 | 4582 | i915_ggtt_view_equal(&vma->ggtt_view, view) && |
fe14d5f4 | 4583 | drm_mm_node_allocated(&vma->node)) |
a70a3148 BW |
4584 | return true; |
4585 | ||
4586 | return false; | |
4587 | } | |
4588 | ||
8da32727 | 4589 | unsigned long i915_gem_obj_ggtt_size(struct drm_i915_gem_object *o) |
a70a3148 | 4590 | { |
a70a3148 BW |
4591 | struct i915_vma *vma; |
4592 | ||
8da32727 | 4593 | GEM_BUG_ON(list_empty(&o->vma_list)); |
a70a3148 | 4594 | |
1c7f4bca | 4595 | list_for_each_entry(vma, &o->vma_list, obj_link) { |
3272db53 | 4596 | if (i915_vma_is_ggtt(vma) && |
8da32727 | 4597 | vma->ggtt_view.type == I915_GGTT_VIEW_NORMAL) |
a70a3148 | 4598 | return vma->node.size; |
ec7adb6e | 4599 | } |
8da32727 | 4600 | |
a70a3148 BW |
4601 | return 0; |
4602 | } | |
4603 | ||
ec7adb6e | 4604 | bool i915_gem_obj_is_pinned(struct drm_i915_gem_object *obj) |
5c2abbea BW |
4605 | { |
4606 | struct i915_vma *vma; | |
1c7f4bca | 4607 | list_for_each_entry(vma, &obj->vma_list, obj_link) |
20dfbde4 | 4608 | if (i915_vma_is_pinned(vma)) |
ec7adb6e | 4609 | return true; |
a6631ae1 | 4610 | |
ec7adb6e | 4611 | return false; |
5c2abbea | 4612 | } |
ea70299d | 4613 | |
033908ae DG |
4614 | /* Like i915_gem_object_get_page(), but mark the returned page dirty */ |
4615 | struct page * | |
4616 | i915_gem_object_get_dirty_page(struct drm_i915_gem_object *obj, int n) | |
4617 | { | |
4618 | struct page *page; | |
4619 | ||
4620 | /* Only default objects have per-page dirty tracking */ | |
b9bcd14a | 4621 | if (WARN_ON(!i915_gem_object_has_struct_page(obj))) |
033908ae DG |
4622 | return NULL; |
4623 | ||
4624 | page = i915_gem_object_get_page(obj, n); | |
4625 | set_page_dirty(page); | |
4626 | return page; | |
4627 | } | |
4628 | ||
ea70299d DG |
4629 | /* Allocate a new GEM object and fill it with the supplied data */ |
4630 | struct drm_i915_gem_object * | |
4631 | i915_gem_object_create_from_data(struct drm_device *dev, | |
4632 | const void *data, size_t size) | |
4633 | { | |
4634 | struct drm_i915_gem_object *obj; | |
4635 | struct sg_table *sg; | |
4636 | size_t bytes; | |
4637 | int ret; | |
4638 | ||
d37cd8a8 | 4639 | obj = i915_gem_object_create(dev, round_up(size, PAGE_SIZE)); |
fe3db79b | 4640 | if (IS_ERR(obj)) |
ea70299d DG |
4641 | return obj; |
4642 | ||
4643 | ret = i915_gem_object_set_to_cpu_domain(obj, true); | |
4644 | if (ret) | |
4645 | goto fail; | |
4646 | ||
4647 | ret = i915_gem_object_get_pages(obj); | |
4648 | if (ret) | |
4649 | goto fail; | |
4650 | ||
4651 | i915_gem_object_pin_pages(obj); | |
4652 | sg = obj->pages; | |
4653 | bytes = sg_copy_from_buffer(sg->sgl, sg->nents, (void *)data, size); | |
9e7d18c0 | 4654 | obj->dirty = 1; /* Backing store is now out of date */ |
ea70299d DG |
4655 | i915_gem_object_unpin_pages(obj); |
4656 | ||
4657 | if (WARN_ON(bytes != size)) { | |
4658 | DRM_ERROR("Incomplete copy, wrote %zu of %zu", bytes, size); | |
4659 | ret = -EFAULT; | |
4660 | goto fail; | |
4661 | } | |
4662 | ||
4663 | return obj; | |
4664 | ||
4665 | fail: | |
f8c417cd | 4666 | i915_gem_object_put(obj); |
ea70299d DG |
4667 | return ERR_PTR(ret); |
4668 | } |