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Commit | Line | Data |
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673a394b EA |
1 | /* |
2 | * Copyright © 2008 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | * | |
26 | */ | |
27 | ||
28 | #include "drmP.h" | |
29 | #include "drm.h" | |
30 | #include "i915_drm.h" | |
31 | #include "i915_drv.h" | |
1c5d22f7 | 32 | #include "i915_trace.h" |
652c393a | 33 | #include "intel_drv.h" |
5949eac4 | 34 | #include <linux/shmem_fs.h> |
5a0e3ad6 | 35 | #include <linux/slab.h> |
673a394b | 36 | #include <linux/swap.h> |
79e53945 | 37 | #include <linux/pci.h> |
673a394b | 38 | |
88241785 | 39 | static __must_check int i915_gem_object_flush_gpu_write_domain(struct drm_i915_gem_object *obj); |
05394f39 CW |
40 | static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj); |
41 | static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj); | |
88241785 CW |
42 | static __must_check int i915_gem_object_bind_to_gtt(struct drm_i915_gem_object *obj, |
43 | unsigned alignment, | |
44 | bool map_and_fenceable); | |
d9e86c0e CW |
45 | static void i915_gem_clear_fence_reg(struct drm_device *dev, |
46 | struct drm_i915_fence_reg *reg); | |
05394f39 CW |
47 | static int i915_gem_phys_pwrite(struct drm_device *dev, |
48 | struct drm_i915_gem_object *obj, | |
71acb5eb | 49 | struct drm_i915_gem_pwrite *args, |
05394f39 CW |
50 | struct drm_file *file); |
51 | static void i915_gem_free_object_tail(struct drm_i915_gem_object *obj); | |
673a394b | 52 | |
17250b71 | 53 | static int i915_gem_inactive_shrink(struct shrinker *shrinker, |
1495f230 | 54 | struct shrink_control *sc); |
8c59967c | 55 | static void i915_gem_object_truncate(struct drm_i915_gem_object *obj); |
31169714 | 56 | |
73aa808f CW |
57 | /* some bookkeeping */ |
58 | static void i915_gem_info_add_obj(struct drm_i915_private *dev_priv, | |
59 | size_t size) | |
60 | { | |
61 | dev_priv->mm.object_count++; | |
62 | dev_priv->mm.object_memory += size; | |
63 | } | |
64 | ||
65 | static void i915_gem_info_remove_obj(struct drm_i915_private *dev_priv, | |
66 | size_t size) | |
67 | { | |
68 | dev_priv->mm.object_count--; | |
69 | dev_priv->mm.object_memory -= size; | |
70 | } | |
71 | ||
21dd3734 CW |
72 | static int |
73 | i915_gem_wait_for_error(struct drm_device *dev) | |
30dbf0c0 CW |
74 | { |
75 | struct drm_i915_private *dev_priv = dev->dev_private; | |
76 | struct completion *x = &dev_priv->error_completion; | |
77 | unsigned long flags; | |
78 | int ret; | |
79 | ||
80 | if (!atomic_read(&dev_priv->mm.wedged)) | |
81 | return 0; | |
82 | ||
83 | ret = wait_for_completion_interruptible(x); | |
84 | if (ret) | |
85 | return ret; | |
86 | ||
21dd3734 CW |
87 | if (atomic_read(&dev_priv->mm.wedged)) { |
88 | /* GPU is hung, bump the completion count to account for | |
89 | * the token we just consumed so that we never hit zero and | |
90 | * end up waiting upon a subsequent completion event that | |
91 | * will never happen. | |
92 | */ | |
93 | spin_lock_irqsave(&x->wait.lock, flags); | |
94 | x->done++; | |
95 | spin_unlock_irqrestore(&x->wait.lock, flags); | |
96 | } | |
97 | return 0; | |
30dbf0c0 CW |
98 | } |
99 | ||
54cf91dc | 100 | int i915_mutex_lock_interruptible(struct drm_device *dev) |
76c1dec1 | 101 | { |
76c1dec1 CW |
102 | int ret; |
103 | ||
21dd3734 | 104 | ret = i915_gem_wait_for_error(dev); |
76c1dec1 CW |
105 | if (ret) |
106 | return ret; | |
107 | ||
108 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
109 | if (ret) | |
110 | return ret; | |
111 | ||
23bc5982 | 112 | WARN_ON(i915_verify_lists(dev)); |
76c1dec1 CW |
113 | return 0; |
114 | } | |
30dbf0c0 | 115 | |
7d1c4804 | 116 | static inline bool |
05394f39 | 117 | i915_gem_object_is_inactive(struct drm_i915_gem_object *obj) |
7d1c4804 | 118 | { |
05394f39 | 119 | return obj->gtt_space && !obj->active && obj->pin_count == 0; |
7d1c4804 CW |
120 | } |
121 | ||
79e53945 JB |
122 | int |
123 | i915_gem_init_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 124 | struct drm_file *file) |
79e53945 JB |
125 | { |
126 | struct drm_i915_gem_init *args = data; | |
2021746e CW |
127 | |
128 | if (args->gtt_start >= args->gtt_end || | |
129 | (args->gtt_end | args->gtt_start) & (PAGE_SIZE - 1)) | |
130 | return -EINVAL; | |
79e53945 JB |
131 | |
132 | mutex_lock(&dev->struct_mutex); | |
644ec02b DV |
133 | i915_gem_init_global_gtt(dev, args->gtt_start, |
134 | args->gtt_end, args->gtt_end); | |
673a394b EA |
135 | mutex_unlock(&dev->struct_mutex); |
136 | ||
2021746e | 137 | return 0; |
673a394b EA |
138 | } |
139 | ||
5a125c3c EA |
140 | int |
141 | i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 142 | struct drm_file *file) |
5a125c3c | 143 | { |
73aa808f | 144 | struct drm_i915_private *dev_priv = dev->dev_private; |
5a125c3c | 145 | struct drm_i915_gem_get_aperture *args = data; |
6299f992 CW |
146 | struct drm_i915_gem_object *obj; |
147 | size_t pinned; | |
5a125c3c EA |
148 | |
149 | if (!(dev->driver->driver_features & DRIVER_GEM)) | |
150 | return -ENODEV; | |
151 | ||
6299f992 | 152 | pinned = 0; |
73aa808f | 153 | mutex_lock(&dev->struct_mutex); |
6299f992 CW |
154 | list_for_each_entry(obj, &dev_priv->mm.pinned_list, mm_list) |
155 | pinned += obj->gtt_space->size; | |
73aa808f | 156 | mutex_unlock(&dev->struct_mutex); |
5a125c3c | 157 | |
6299f992 | 158 | args->aper_size = dev_priv->mm.gtt_total; |
0206e353 | 159 | args->aper_available_size = args->aper_size - pinned; |
6299f992 | 160 | |
5a125c3c EA |
161 | return 0; |
162 | } | |
163 | ||
ff72145b DA |
164 | static int |
165 | i915_gem_create(struct drm_file *file, | |
166 | struct drm_device *dev, | |
167 | uint64_t size, | |
168 | uint32_t *handle_p) | |
673a394b | 169 | { |
05394f39 | 170 | struct drm_i915_gem_object *obj; |
a1a2d1d3 PP |
171 | int ret; |
172 | u32 handle; | |
673a394b | 173 | |
ff72145b | 174 | size = roundup(size, PAGE_SIZE); |
8ffc0246 CW |
175 | if (size == 0) |
176 | return -EINVAL; | |
673a394b EA |
177 | |
178 | /* Allocate the new object */ | |
ff72145b | 179 | obj = i915_gem_alloc_object(dev, size); |
673a394b EA |
180 | if (obj == NULL) |
181 | return -ENOMEM; | |
182 | ||
05394f39 | 183 | ret = drm_gem_handle_create(file, &obj->base, &handle); |
1dfd9754 | 184 | if (ret) { |
05394f39 CW |
185 | drm_gem_object_release(&obj->base); |
186 | i915_gem_info_remove_obj(dev->dev_private, obj->base.size); | |
202f2fef | 187 | kfree(obj); |
673a394b | 188 | return ret; |
1dfd9754 | 189 | } |
673a394b | 190 | |
202f2fef | 191 | /* drop reference from allocate - handle holds it now */ |
05394f39 | 192 | drm_gem_object_unreference(&obj->base); |
202f2fef CW |
193 | trace_i915_gem_object_create(obj); |
194 | ||
ff72145b | 195 | *handle_p = handle; |
673a394b EA |
196 | return 0; |
197 | } | |
198 | ||
ff72145b DA |
199 | int |
200 | i915_gem_dumb_create(struct drm_file *file, | |
201 | struct drm_device *dev, | |
202 | struct drm_mode_create_dumb *args) | |
203 | { | |
204 | /* have to work out size/pitch and return them */ | |
ed0291fd | 205 | args->pitch = ALIGN(args->width * ((args->bpp + 7) / 8), 64); |
ff72145b DA |
206 | args->size = args->pitch * args->height; |
207 | return i915_gem_create(file, dev, | |
208 | args->size, &args->handle); | |
209 | } | |
210 | ||
211 | int i915_gem_dumb_destroy(struct drm_file *file, | |
212 | struct drm_device *dev, | |
213 | uint32_t handle) | |
214 | { | |
215 | return drm_gem_handle_delete(file, handle); | |
216 | } | |
217 | ||
218 | /** | |
219 | * Creates a new mm object and returns a handle to it. | |
220 | */ | |
221 | int | |
222 | i915_gem_create_ioctl(struct drm_device *dev, void *data, | |
223 | struct drm_file *file) | |
224 | { | |
225 | struct drm_i915_gem_create *args = data; | |
226 | return i915_gem_create(file, dev, | |
227 | args->size, &args->handle); | |
228 | } | |
229 | ||
05394f39 | 230 | static int i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj) |
280b713b | 231 | { |
05394f39 | 232 | drm_i915_private_t *dev_priv = obj->base.dev->dev_private; |
280b713b EA |
233 | |
234 | return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 && | |
05394f39 | 235 | obj->tiling_mode != I915_TILING_NONE; |
280b713b EA |
236 | } |
237 | ||
8461d226 DV |
238 | static inline int |
239 | __copy_to_user_swizzled(char __user *cpu_vaddr, | |
240 | const char *gpu_vaddr, int gpu_offset, | |
241 | int length) | |
242 | { | |
243 | int ret, cpu_offset = 0; | |
244 | ||
245 | while (length > 0) { | |
246 | int cacheline_end = ALIGN(gpu_offset + 1, 64); | |
247 | int this_length = min(cacheline_end - gpu_offset, length); | |
248 | int swizzled_gpu_offset = gpu_offset ^ 64; | |
249 | ||
250 | ret = __copy_to_user(cpu_vaddr + cpu_offset, | |
251 | gpu_vaddr + swizzled_gpu_offset, | |
252 | this_length); | |
253 | if (ret) | |
254 | return ret + length; | |
255 | ||
256 | cpu_offset += this_length; | |
257 | gpu_offset += this_length; | |
258 | length -= this_length; | |
259 | } | |
260 | ||
261 | return 0; | |
262 | } | |
263 | ||
8c59967c DV |
264 | static inline int |
265 | __copy_from_user_swizzled(char __user *gpu_vaddr, int gpu_offset, | |
266 | const char *cpu_vaddr, | |
267 | int length) | |
268 | { | |
269 | int ret, cpu_offset = 0; | |
270 | ||
271 | while (length > 0) { | |
272 | int cacheline_end = ALIGN(gpu_offset + 1, 64); | |
273 | int this_length = min(cacheline_end - gpu_offset, length); | |
274 | int swizzled_gpu_offset = gpu_offset ^ 64; | |
275 | ||
276 | ret = __copy_from_user(gpu_vaddr + swizzled_gpu_offset, | |
277 | cpu_vaddr + cpu_offset, | |
278 | this_length); | |
279 | if (ret) | |
280 | return ret + length; | |
281 | ||
282 | cpu_offset += this_length; | |
283 | gpu_offset += this_length; | |
284 | length -= this_length; | |
285 | } | |
286 | ||
287 | return 0; | |
288 | } | |
289 | ||
d174bd64 DV |
290 | /* Per-page copy function for the shmem pread fastpath. |
291 | * Flushes invalid cachelines before reading the target if | |
292 | * needs_clflush is set. */ | |
293 | static int | |
294 | shmem_pread_fast(struct page *page, int shmem_page_offset, int page_length, | |
295 | char __user *user_data, | |
296 | bool page_do_bit17_swizzling, bool needs_clflush) | |
297 | { | |
298 | char *vaddr; | |
299 | int ret; | |
300 | ||
e7e58eb5 | 301 | if (unlikely(page_do_bit17_swizzling)) |
d174bd64 DV |
302 | return -EINVAL; |
303 | ||
304 | vaddr = kmap_atomic(page); | |
305 | if (needs_clflush) | |
306 | drm_clflush_virt_range(vaddr + shmem_page_offset, | |
307 | page_length); | |
308 | ret = __copy_to_user_inatomic(user_data, | |
309 | vaddr + shmem_page_offset, | |
310 | page_length); | |
311 | kunmap_atomic(vaddr); | |
312 | ||
313 | return ret; | |
314 | } | |
315 | ||
23c18c71 DV |
316 | static void |
317 | shmem_clflush_swizzled_range(char *addr, unsigned long length, | |
318 | bool swizzled) | |
319 | { | |
e7e58eb5 | 320 | if (unlikely(swizzled)) { |
23c18c71 DV |
321 | unsigned long start = (unsigned long) addr; |
322 | unsigned long end = (unsigned long) addr + length; | |
323 | ||
324 | /* For swizzling simply ensure that we always flush both | |
325 | * channels. Lame, but simple and it works. Swizzled | |
326 | * pwrite/pread is far from a hotpath - current userspace | |
327 | * doesn't use it at all. */ | |
328 | start = round_down(start, 128); | |
329 | end = round_up(end, 128); | |
330 | ||
331 | drm_clflush_virt_range((void *)start, end - start); | |
332 | } else { | |
333 | drm_clflush_virt_range(addr, length); | |
334 | } | |
335 | ||
336 | } | |
337 | ||
d174bd64 DV |
338 | /* Only difference to the fast-path function is that this can handle bit17 |
339 | * and uses non-atomic copy and kmap functions. */ | |
340 | static int | |
341 | shmem_pread_slow(struct page *page, int shmem_page_offset, int page_length, | |
342 | char __user *user_data, | |
343 | bool page_do_bit17_swizzling, bool needs_clflush) | |
344 | { | |
345 | char *vaddr; | |
346 | int ret; | |
347 | ||
348 | vaddr = kmap(page); | |
349 | if (needs_clflush) | |
23c18c71 DV |
350 | shmem_clflush_swizzled_range(vaddr + shmem_page_offset, |
351 | page_length, | |
352 | page_do_bit17_swizzling); | |
d174bd64 DV |
353 | |
354 | if (page_do_bit17_swizzling) | |
355 | ret = __copy_to_user_swizzled(user_data, | |
356 | vaddr, shmem_page_offset, | |
357 | page_length); | |
358 | else | |
359 | ret = __copy_to_user(user_data, | |
360 | vaddr + shmem_page_offset, | |
361 | page_length); | |
362 | kunmap(page); | |
363 | ||
364 | return ret; | |
365 | } | |
366 | ||
eb01459f | 367 | static int |
dbf7bff0 DV |
368 | i915_gem_shmem_pread(struct drm_device *dev, |
369 | struct drm_i915_gem_object *obj, | |
370 | struct drm_i915_gem_pread *args, | |
371 | struct drm_file *file) | |
eb01459f | 372 | { |
05394f39 | 373 | struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping; |
8461d226 | 374 | char __user *user_data; |
eb01459f | 375 | ssize_t remain; |
8461d226 | 376 | loff_t offset; |
eb2c0c81 | 377 | int shmem_page_offset, page_length, ret = 0; |
8461d226 | 378 | int obj_do_bit17_swizzling, page_do_bit17_swizzling; |
dbf7bff0 | 379 | int hit_slowpath = 0; |
96d79b52 | 380 | int prefaulted = 0; |
8489731c | 381 | int needs_clflush = 0; |
692a576b | 382 | int release_page; |
eb01459f | 383 | |
8461d226 | 384 | user_data = (char __user *) (uintptr_t) args->data_ptr; |
eb01459f EA |
385 | remain = args->size; |
386 | ||
8461d226 | 387 | obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj); |
eb01459f | 388 | |
8489731c DV |
389 | if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU)) { |
390 | /* If we're not in the cpu read domain, set ourself into the gtt | |
391 | * read domain and manually flush cachelines (if required). This | |
392 | * optimizes for the case when the gpu will dirty the data | |
393 | * anyway again before the next pread happens. */ | |
394 | if (obj->cache_level == I915_CACHE_NONE) | |
395 | needs_clflush = 1; | |
396 | ret = i915_gem_object_set_to_gtt_domain(obj, false); | |
397 | if (ret) | |
398 | return ret; | |
399 | } | |
400 | ||
8461d226 | 401 | offset = args->offset; |
eb01459f | 402 | |
eb01459f | 403 | while (remain > 0) { |
e5281ccd CW |
404 | struct page *page; |
405 | ||
eb01459f EA |
406 | /* Operation in this page |
407 | * | |
eb01459f | 408 | * shmem_page_offset = offset within page in shmem file |
eb01459f EA |
409 | * page_length = bytes to copy for this page |
410 | */ | |
c8cbbb8b | 411 | shmem_page_offset = offset_in_page(offset); |
eb01459f EA |
412 | page_length = remain; |
413 | if ((shmem_page_offset + page_length) > PAGE_SIZE) | |
414 | page_length = PAGE_SIZE - shmem_page_offset; | |
eb01459f | 415 | |
692a576b DV |
416 | if (obj->pages) { |
417 | page = obj->pages[offset >> PAGE_SHIFT]; | |
418 | release_page = 0; | |
419 | } else { | |
420 | page = shmem_read_mapping_page(mapping, offset >> PAGE_SHIFT); | |
421 | if (IS_ERR(page)) { | |
422 | ret = PTR_ERR(page); | |
423 | goto out; | |
424 | } | |
425 | release_page = 1; | |
b65552f0 | 426 | } |
e5281ccd | 427 | |
8461d226 DV |
428 | page_do_bit17_swizzling = obj_do_bit17_swizzling && |
429 | (page_to_phys(page) & (1 << 17)) != 0; | |
430 | ||
d174bd64 DV |
431 | ret = shmem_pread_fast(page, shmem_page_offset, page_length, |
432 | user_data, page_do_bit17_swizzling, | |
433 | needs_clflush); | |
434 | if (ret == 0) | |
435 | goto next_page; | |
dbf7bff0 DV |
436 | |
437 | hit_slowpath = 1; | |
692a576b | 438 | page_cache_get(page); |
dbf7bff0 DV |
439 | mutex_unlock(&dev->struct_mutex); |
440 | ||
96d79b52 | 441 | if (!prefaulted) { |
f56f821f | 442 | ret = fault_in_multipages_writeable(user_data, remain); |
96d79b52 DV |
443 | /* Userspace is tricking us, but we've already clobbered |
444 | * its pages with the prefault and promised to write the | |
445 | * data up to the first fault. Hence ignore any errors | |
446 | * and just continue. */ | |
447 | (void)ret; | |
448 | prefaulted = 1; | |
449 | } | |
450 | ||
d174bd64 DV |
451 | ret = shmem_pread_slow(page, shmem_page_offset, page_length, |
452 | user_data, page_do_bit17_swizzling, | |
453 | needs_clflush); | |
eb01459f | 454 | |
dbf7bff0 | 455 | mutex_lock(&dev->struct_mutex); |
692a576b | 456 | page_cache_release(page); |
dbf7bff0 | 457 | next_page: |
e5281ccd | 458 | mark_page_accessed(page); |
692a576b DV |
459 | if (release_page) |
460 | page_cache_release(page); | |
e5281ccd | 461 | |
8461d226 DV |
462 | if (ret) { |
463 | ret = -EFAULT; | |
464 | goto out; | |
465 | } | |
466 | ||
eb01459f | 467 | remain -= page_length; |
8461d226 | 468 | user_data += page_length; |
eb01459f EA |
469 | offset += page_length; |
470 | } | |
471 | ||
4f27b75d | 472 | out: |
dbf7bff0 DV |
473 | if (hit_slowpath) { |
474 | /* Fixup: Kill any reinstated backing storage pages */ | |
475 | if (obj->madv == __I915_MADV_PURGED) | |
476 | i915_gem_object_truncate(obj); | |
477 | } | |
eb01459f EA |
478 | |
479 | return ret; | |
480 | } | |
481 | ||
673a394b EA |
482 | /** |
483 | * Reads data from the object referenced by handle. | |
484 | * | |
485 | * On error, the contents of *data are undefined. | |
486 | */ | |
487 | int | |
488 | i915_gem_pread_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 489 | struct drm_file *file) |
673a394b EA |
490 | { |
491 | struct drm_i915_gem_pread *args = data; | |
05394f39 | 492 | struct drm_i915_gem_object *obj; |
35b62a89 | 493 | int ret = 0; |
673a394b | 494 | |
51311d0a CW |
495 | if (args->size == 0) |
496 | return 0; | |
497 | ||
498 | if (!access_ok(VERIFY_WRITE, | |
499 | (char __user *)(uintptr_t)args->data_ptr, | |
500 | args->size)) | |
501 | return -EFAULT; | |
502 | ||
4f27b75d | 503 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 504 | if (ret) |
4f27b75d | 505 | return ret; |
673a394b | 506 | |
05394f39 | 507 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 508 | if (&obj->base == NULL) { |
1d7cfea1 CW |
509 | ret = -ENOENT; |
510 | goto unlock; | |
4f27b75d | 511 | } |
673a394b | 512 | |
7dcd2499 | 513 | /* Bounds check source. */ |
05394f39 CW |
514 | if (args->offset > obj->base.size || |
515 | args->size > obj->base.size - args->offset) { | |
ce9d419d | 516 | ret = -EINVAL; |
35b62a89 | 517 | goto out; |
ce9d419d CW |
518 | } |
519 | ||
db53a302 CW |
520 | trace_i915_gem_object_pread(obj, args->offset, args->size); |
521 | ||
dbf7bff0 | 522 | ret = i915_gem_shmem_pread(dev, obj, args, file); |
673a394b | 523 | |
35b62a89 | 524 | out: |
05394f39 | 525 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 526 | unlock: |
4f27b75d | 527 | mutex_unlock(&dev->struct_mutex); |
eb01459f | 528 | return ret; |
673a394b EA |
529 | } |
530 | ||
0839ccb8 KP |
531 | /* This is the fast write path which cannot handle |
532 | * page faults in the source data | |
9b7530cc | 533 | */ |
0839ccb8 KP |
534 | |
535 | static inline int | |
536 | fast_user_write(struct io_mapping *mapping, | |
537 | loff_t page_base, int page_offset, | |
538 | char __user *user_data, | |
539 | int length) | |
9b7530cc | 540 | { |
9b7530cc | 541 | char *vaddr_atomic; |
0839ccb8 | 542 | unsigned long unwritten; |
9b7530cc | 543 | |
3e4d3af5 | 544 | vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base); |
0839ccb8 KP |
545 | unwritten = __copy_from_user_inatomic_nocache(vaddr_atomic + page_offset, |
546 | user_data, length); | |
3e4d3af5 | 547 | io_mapping_unmap_atomic(vaddr_atomic); |
fbd5a26d | 548 | return unwritten; |
0839ccb8 KP |
549 | } |
550 | ||
3de09aa3 EA |
551 | /** |
552 | * This is the fast pwrite path, where we copy the data directly from the | |
553 | * user into the GTT, uncached. | |
554 | */ | |
673a394b | 555 | static int |
05394f39 CW |
556 | i915_gem_gtt_pwrite_fast(struct drm_device *dev, |
557 | struct drm_i915_gem_object *obj, | |
3de09aa3 | 558 | struct drm_i915_gem_pwrite *args, |
05394f39 | 559 | struct drm_file *file) |
673a394b | 560 | { |
0839ccb8 | 561 | drm_i915_private_t *dev_priv = dev->dev_private; |
673a394b | 562 | ssize_t remain; |
0839ccb8 | 563 | loff_t offset, page_base; |
673a394b | 564 | char __user *user_data; |
935aaa69 DV |
565 | int page_offset, page_length, ret; |
566 | ||
567 | ret = i915_gem_object_pin(obj, 0, true); | |
568 | if (ret) | |
569 | goto out; | |
570 | ||
571 | ret = i915_gem_object_set_to_gtt_domain(obj, true); | |
572 | if (ret) | |
573 | goto out_unpin; | |
574 | ||
575 | ret = i915_gem_object_put_fence(obj); | |
576 | if (ret) | |
577 | goto out_unpin; | |
673a394b EA |
578 | |
579 | user_data = (char __user *) (uintptr_t) args->data_ptr; | |
580 | remain = args->size; | |
673a394b | 581 | |
05394f39 | 582 | offset = obj->gtt_offset + args->offset; |
673a394b EA |
583 | |
584 | while (remain > 0) { | |
585 | /* Operation in this page | |
586 | * | |
0839ccb8 KP |
587 | * page_base = page offset within aperture |
588 | * page_offset = offset within page | |
589 | * page_length = bytes to copy for this page | |
673a394b | 590 | */ |
c8cbbb8b CW |
591 | page_base = offset & PAGE_MASK; |
592 | page_offset = offset_in_page(offset); | |
0839ccb8 KP |
593 | page_length = remain; |
594 | if ((page_offset + remain) > PAGE_SIZE) | |
595 | page_length = PAGE_SIZE - page_offset; | |
596 | ||
0839ccb8 | 597 | /* If we get a fault while copying data, then (presumably) our |
3de09aa3 EA |
598 | * source page isn't available. Return the error and we'll |
599 | * retry in the slow path. | |
0839ccb8 | 600 | */ |
fbd5a26d | 601 | if (fast_user_write(dev_priv->mm.gtt_mapping, page_base, |
935aaa69 DV |
602 | page_offset, user_data, page_length)) { |
603 | ret = -EFAULT; | |
604 | goto out_unpin; | |
605 | } | |
673a394b | 606 | |
0839ccb8 KP |
607 | remain -= page_length; |
608 | user_data += page_length; | |
609 | offset += page_length; | |
673a394b | 610 | } |
673a394b | 611 | |
935aaa69 DV |
612 | out_unpin: |
613 | i915_gem_object_unpin(obj); | |
614 | out: | |
3de09aa3 EA |
615 | return ret; |
616 | } | |
617 | ||
d174bd64 DV |
618 | /* Per-page copy function for the shmem pwrite fastpath. |
619 | * Flushes invalid cachelines before writing to the target if | |
620 | * needs_clflush_before is set and flushes out any written cachelines after | |
621 | * writing if needs_clflush is set. */ | |
622 | static int | |
623 | shmem_pwrite_fast(struct page *page, int shmem_page_offset, int page_length, | |
624 | char __user *user_data, | |
625 | bool page_do_bit17_swizzling, | |
626 | bool needs_clflush_before, | |
627 | bool needs_clflush_after) | |
628 | { | |
629 | char *vaddr; | |
630 | int ret; | |
631 | ||
e7e58eb5 | 632 | if (unlikely(page_do_bit17_swizzling)) |
d174bd64 DV |
633 | return -EINVAL; |
634 | ||
635 | vaddr = kmap_atomic(page); | |
636 | if (needs_clflush_before) | |
637 | drm_clflush_virt_range(vaddr + shmem_page_offset, | |
638 | page_length); | |
639 | ret = __copy_from_user_inatomic_nocache(vaddr + shmem_page_offset, | |
640 | user_data, | |
641 | page_length); | |
642 | if (needs_clflush_after) | |
643 | drm_clflush_virt_range(vaddr + shmem_page_offset, | |
644 | page_length); | |
645 | kunmap_atomic(vaddr); | |
646 | ||
647 | return ret; | |
648 | } | |
649 | ||
650 | /* Only difference to the fast-path function is that this can handle bit17 | |
651 | * and uses non-atomic copy and kmap functions. */ | |
652 | static int | |
653 | shmem_pwrite_slow(struct page *page, int shmem_page_offset, int page_length, | |
654 | char __user *user_data, | |
655 | bool page_do_bit17_swizzling, | |
656 | bool needs_clflush_before, | |
657 | bool needs_clflush_after) | |
658 | { | |
659 | char *vaddr; | |
660 | int ret; | |
661 | ||
662 | vaddr = kmap(page); | |
e7e58eb5 | 663 | if (unlikely(needs_clflush_before || page_do_bit17_swizzling)) |
23c18c71 DV |
664 | shmem_clflush_swizzled_range(vaddr + shmem_page_offset, |
665 | page_length, | |
666 | page_do_bit17_swizzling); | |
d174bd64 DV |
667 | if (page_do_bit17_swizzling) |
668 | ret = __copy_from_user_swizzled(vaddr, shmem_page_offset, | |
669 | user_data, | |
670 | page_length); | |
671 | else | |
672 | ret = __copy_from_user(vaddr + shmem_page_offset, | |
673 | user_data, | |
674 | page_length); | |
675 | if (needs_clflush_after) | |
23c18c71 DV |
676 | shmem_clflush_swizzled_range(vaddr + shmem_page_offset, |
677 | page_length, | |
678 | page_do_bit17_swizzling); | |
d174bd64 DV |
679 | kunmap(page); |
680 | ||
681 | return ret; | |
682 | } | |
683 | ||
3043c60c | 684 | static int |
e244a443 DV |
685 | i915_gem_shmem_pwrite(struct drm_device *dev, |
686 | struct drm_i915_gem_object *obj, | |
687 | struct drm_i915_gem_pwrite *args, | |
688 | struct drm_file *file) | |
40123c1f | 689 | { |
05394f39 | 690 | struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping; |
40123c1f | 691 | ssize_t remain; |
8c59967c DV |
692 | loff_t offset; |
693 | char __user *user_data; | |
eb2c0c81 | 694 | int shmem_page_offset, page_length, ret = 0; |
8c59967c | 695 | int obj_do_bit17_swizzling, page_do_bit17_swizzling; |
e244a443 | 696 | int hit_slowpath = 0; |
58642885 DV |
697 | int needs_clflush_after = 0; |
698 | int needs_clflush_before = 0; | |
692a576b | 699 | int release_page; |
40123c1f | 700 | |
8c59967c | 701 | user_data = (char __user *) (uintptr_t) args->data_ptr; |
40123c1f EA |
702 | remain = args->size; |
703 | ||
8c59967c | 704 | obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj); |
40123c1f | 705 | |
58642885 DV |
706 | if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) { |
707 | /* If we're not in the cpu write domain, set ourself into the gtt | |
708 | * write domain and manually flush cachelines (if required). This | |
709 | * optimizes for the case when the gpu will use the data | |
710 | * right away and we therefore have to clflush anyway. */ | |
711 | if (obj->cache_level == I915_CACHE_NONE) | |
712 | needs_clflush_after = 1; | |
713 | ret = i915_gem_object_set_to_gtt_domain(obj, true); | |
714 | if (ret) | |
715 | return ret; | |
716 | } | |
717 | /* Same trick applies for invalidate partially written cachelines before | |
718 | * writing. */ | |
719 | if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU) | |
720 | && obj->cache_level == I915_CACHE_NONE) | |
721 | needs_clflush_before = 1; | |
722 | ||
673a394b | 723 | offset = args->offset; |
05394f39 | 724 | obj->dirty = 1; |
673a394b | 725 | |
40123c1f | 726 | while (remain > 0) { |
e5281ccd | 727 | struct page *page; |
58642885 | 728 | int partial_cacheline_write; |
e5281ccd | 729 | |
40123c1f EA |
730 | /* Operation in this page |
731 | * | |
40123c1f | 732 | * shmem_page_offset = offset within page in shmem file |
40123c1f EA |
733 | * page_length = bytes to copy for this page |
734 | */ | |
c8cbbb8b | 735 | shmem_page_offset = offset_in_page(offset); |
40123c1f EA |
736 | |
737 | page_length = remain; | |
738 | if ((shmem_page_offset + page_length) > PAGE_SIZE) | |
739 | page_length = PAGE_SIZE - shmem_page_offset; | |
40123c1f | 740 | |
58642885 DV |
741 | /* If we don't overwrite a cacheline completely we need to be |
742 | * careful to have up-to-date data by first clflushing. Don't | |
743 | * overcomplicate things and flush the entire patch. */ | |
744 | partial_cacheline_write = needs_clflush_before && | |
745 | ((shmem_page_offset | page_length) | |
746 | & (boot_cpu_data.x86_clflush_size - 1)); | |
747 | ||
692a576b DV |
748 | if (obj->pages) { |
749 | page = obj->pages[offset >> PAGE_SHIFT]; | |
750 | release_page = 0; | |
751 | } else { | |
752 | page = shmem_read_mapping_page(mapping, offset >> PAGE_SHIFT); | |
753 | if (IS_ERR(page)) { | |
754 | ret = PTR_ERR(page); | |
755 | goto out; | |
756 | } | |
757 | release_page = 1; | |
e5281ccd CW |
758 | } |
759 | ||
8c59967c DV |
760 | page_do_bit17_swizzling = obj_do_bit17_swizzling && |
761 | (page_to_phys(page) & (1 << 17)) != 0; | |
762 | ||
d174bd64 DV |
763 | ret = shmem_pwrite_fast(page, shmem_page_offset, page_length, |
764 | user_data, page_do_bit17_swizzling, | |
765 | partial_cacheline_write, | |
766 | needs_clflush_after); | |
767 | if (ret == 0) | |
768 | goto next_page; | |
e244a443 DV |
769 | |
770 | hit_slowpath = 1; | |
692a576b | 771 | page_cache_get(page); |
e244a443 DV |
772 | mutex_unlock(&dev->struct_mutex); |
773 | ||
d174bd64 DV |
774 | ret = shmem_pwrite_slow(page, shmem_page_offset, page_length, |
775 | user_data, page_do_bit17_swizzling, | |
776 | partial_cacheline_write, | |
777 | needs_clflush_after); | |
40123c1f | 778 | |
e244a443 | 779 | mutex_lock(&dev->struct_mutex); |
692a576b | 780 | page_cache_release(page); |
e244a443 | 781 | next_page: |
e5281ccd CW |
782 | set_page_dirty(page); |
783 | mark_page_accessed(page); | |
692a576b DV |
784 | if (release_page) |
785 | page_cache_release(page); | |
e5281ccd | 786 | |
8c59967c DV |
787 | if (ret) { |
788 | ret = -EFAULT; | |
789 | goto out; | |
790 | } | |
791 | ||
40123c1f | 792 | remain -= page_length; |
8c59967c | 793 | user_data += page_length; |
40123c1f | 794 | offset += page_length; |
673a394b EA |
795 | } |
796 | ||
fbd5a26d | 797 | out: |
e244a443 DV |
798 | if (hit_slowpath) { |
799 | /* Fixup: Kill any reinstated backing storage pages */ | |
800 | if (obj->madv == __I915_MADV_PURGED) | |
801 | i915_gem_object_truncate(obj); | |
802 | /* and flush dirty cachelines in case the object isn't in the cpu write | |
803 | * domain anymore. */ | |
804 | if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) { | |
805 | i915_gem_clflush_object(obj); | |
806 | intel_gtt_chipset_flush(); | |
807 | } | |
8c59967c | 808 | } |
673a394b | 809 | |
58642885 DV |
810 | if (needs_clflush_after) |
811 | intel_gtt_chipset_flush(); | |
812 | ||
40123c1f | 813 | return ret; |
673a394b EA |
814 | } |
815 | ||
816 | /** | |
817 | * Writes data to the object referenced by handle. | |
818 | * | |
819 | * On error, the contents of the buffer that were to be modified are undefined. | |
820 | */ | |
821 | int | |
822 | i915_gem_pwrite_ioctl(struct drm_device *dev, void *data, | |
fbd5a26d | 823 | struct drm_file *file) |
673a394b EA |
824 | { |
825 | struct drm_i915_gem_pwrite *args = data; | |
05394f39 | 826 | struct drm_i915_gem_object *obj; |
51311d0a CW |
827 | int ret; |
828 | ||
829 | if (args->size == 0) | |
830 | return 0; | |
831 | ||
832 | if (!access_ok(VERIFY_READ, | |
833 | (char __user *)(uintptr_t)args->data_ptr, | |
834 | args->size)) | |
835 | return -EFAULT; | |
836 | ||
f56f821f DV |
837 | ret = fault_in_multipages_readable((char __user *)(uintptr_t)args->data_ptr, |
838 | args->size); | |
51311d0a CW |
839 | if (ret) |
840 | return -EFAULT; | |
673a394b | 841 | |
fbd5a26d | 842 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 843 | if (ret) |
fbd5a26d | 844 | return ret; |
1d7cfea1 | 845 | |
05394f39 | 846 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 847 | if (&obj->base == NULL) { |
1d7cfea1 CW |
848 | ret = -ENOENT; |
849 | goto unlock; | |
fbd5a26d | 850 | } |
673a394b | 851 | |
7dcd2499 | 852 | /* Bounds check destination. */ |
05394f39 CW |
853 | if (args->offset > obj->base.size || |
854 | args->size > obj->base.size - args->offset) { | |
ce9d419d | 855 | ret = -EINVAL; |
35b62a89 | 856 | goto out; |
ce9d419d CW |
857 | } |
858 | ||
db53a302 CW |
859 | trace_i915_gem_object_pwrite(obj, args->offset, args->size); |
860 | ||
935aaa69 | 861 | ret = -EFAULT; |
673a394b EA |
862 | /* We can only do the GTT pwrite on untiled buffers, as otherwise |
863 | * it would end up going through the fenced access, and we'll get | |
864 | * different detiling behavior between reading and writing. | |
865 | * pread/pwrite currently are reading and writing from the CPU | |
866 | * perspective, requiring manual detiling by the client. | |
867 | */ | |
5c0480f2 | 868 | if (obj->phys_obj) { |
fbd5a26d | 869 | ret = i915_gem_phys_pwrite(dev, obj, args, file); |
5c0480f2 DV |
870 | goto out; |
871 | } | |
872 | ||
873 | if (obj->gtt_space && | |
3ae53783 | 874 | obj->cache_level == I915_CACHE_NONE && |
ffc62976 | 875 | obj->map_and_fenceable && |
5c0480f2 | 876 | obj->base.write_domain != I915_GEM_DOMAIN_CPU) { |
fbd5a26d | 877 | ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file); |
935aaa69 DV |
878 | /* Note that the gtt paths might fail with non-page-backed user |
879 | * pointers (e.g. gtt mappings when moving data between | |
880 | * textures). Fallback to the shmem path in that case. */ | |
fbd5a26d | 881 | } |
673a394b | 882 | |
935aaa69 DV |
883 | if (ret == -EFAULT) |
884 | ret = i915_gem_shmem_pwrite(dev, obj, args, file); | |
5c0480f2 | 885 | |
35b62a89 | 886 | out: |
05394f39 | 887 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 888 | unlock: |
fbd5a26d | 889 | mutex_unlock(&dev->struct_mutex); |
673a394b EA |
890 | return ret; |
891 | } | |
892 | ||
893 | /** | |
2ef7eeaa EA |
894 | * Called when user space prepares to use an object with the CPU, either |
895 | * through the mmap ioctl's mapping or a GTT mapping. | |
673a394b EA |
896 | */ |
897 | int | |
898 | i915_gem_set_domain_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 899 | struct drm_file *file) |
673a394b EA |
900 | { |
901 | struct drm_i915_gem_set_domain *args = data; | |
05394f39 | 902 | struct drm_i915_gem_object *obj; |
2ef7eeaa EA |
903 | uint32_t read_domains = args->read_domains; |
904 | uint32_t write_domain = args->write_domain; | |
673a394b EA |
905 | int ret; |
906 | ||
907 | if (!(dev->driver->driver_features & DRIVER_GEM)) | |
908 | return -ENODEV; | |
909 | ||
2ef7eeaa | 910 | /* Only handle setting domains to types used by the CPU. */ |
21d509e3 | 911 | if (write_domain & I915_GEM_GPU_DOMAINS) |
2ef7eeaa EA |
912 | return -EINVAL; |
913 | ||
21d509e3 | 914 | if (read_domains & I915_GEM_GPU_DOMAINS) |
2ef7eeaa EA |
915 | return -EINVAL; |
916 | ||
917 | /* Having something in the write domain implies it's in the read | |
918 | * domain, and only that read domain. Enforce that in the request. | |
919 | */ | |
920 | if (write_domain != 0 && read_domains != write_domain) | |
921 | return -EINVAL; | |
922 | ||
76c1dec1 | 923 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 924 | if (ret) |
76c1dec1 | 925 | return ret; |
1d7cfea1 | 926 | |
05394f39 | 927 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 928 | if (&obj->base == NULL) { |
1d7cfea1 CW |
929 | ret = -ENOENT; |
930 | goto unlock; | |
76c1dec1 | 931 | } |
673a394b | 932 | |
2ef7eeaa EA |
933 | if (read_domains & I915_GEM_DOMAIN_GTT) { |
934 | ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0); | |
02354392 EA |
935 | |
936 | /* Silently promote "you're not bound, there was nothing to do" | |
937 | * to success, since the client was just asking us to | |
938 | * make sure everything was done. | |
939 | */ | |
940 | if (ret == -EINVAL) | |
941 | ret = 0; | |
2ef7eeaa | 942 | } else { |
e47c68e9 | 943 | ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0); |
2ef7eeaa EA |
944 | } |
945 | ||
05394f39 | 946 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 947 | unlock: |
673a394b EA |
948 | mutex_unlock(&dev->struct_mutex); |
949 | return ret; | |
950 | } | |
951 | ||
952 | /** | |
953 | * Called when user space has done writes to this buffer | |
954 | */ | |
955 | int | |
956 | i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 957 | struct drm_file *file) |
673a394b EA |
958 | { |
959 | struct drm_i915_gem_sw_finish *args = data; | |
05394f39 | 960 | struct drm_i915_gem_object *obj; |
673a394b EA |
961 | int ret = 0; |
962 | ||
963 | if (!(dev->driver->driver_features & DRIVER_GEM)) | |
964 | return -ENODEV; | |
965 | ||
76c1dec1 | 966 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 967 | if (ret) |
76c1dec1 | 968 | return ret; |
1d7cfea1 | 969 | |
05394f39 | 970 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 971 | if (&obj->base == NULL) { |
1d7cfea1 CW |
972 | ret = -ENOENT; |
973 | goto unlock; | |
673a394b EA |
974 | } |
975 | ||
673a394b | 976 | /* Pinned buffers may be scanout, so flush the cache */ |
05394f39 | 977 | if (obj->pin_count) |
e47c68e9 EA |
978 | i915_gem_object_flush_cpu_write_domain(obj); |
979 | ||
05394f39 | 980 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 981 | unlock: |
673a394b EA |
982 | mutex_unlock(&dev->struct_mutex); |
983 | return ret; | |
984 | } | |
985 | ||
986 | /** | |
987 | * Maps the contents of an object, returning the address it is mapped | |
988 | * into. | |
989 | * | |
990 | * While the mapping holds a reference on the contents of the object, it doesn't | |
991 | * imply a ref on the object itself. | |
992 | */ | |
993 | int | |
994 | i915_gem_mmap_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 995 | struct drm_file *file) |
673a394b EA |
996 | { |
997 | struct drm_i915_gem_mmap *args = data; | |
998 | struct drm_gem_object *obj; | |
673a394b EA |
999 | unsigned long addr; |
1000 | ||
1001 | if (!(dev->driver->driver_features & DRIVER_GEM)) | |
1002 | return -ENODEV; | |
1003 | ||
05394f39 | 1004 | obj = drm_gem_object_lookup(dev, file, args->handle); |
673a394b | 1005 | if (obj == NULL) |
bf79cb91 | 1006 | return -ENOENT; |
673a394b | 1007 | |
673a394b EA |
1008 | down_write(¤t->mm->mmap_sem); |
1009 | addr = do_mmap(obj->filp, 0, args->size, | |
1010 | PROT_READ | PROT_WRITE, MAP_SHARED, | |
1011 | args->offset); | |
1012 | up_write(¤t->mm->mmap_sem); | |
bc9025bd | 1013 | drm_gem_object_unreference_unlocked(obj); |
673a394b EA |
1014 | if (IS_ERR((void *)addr)) |
1015 | return addr; | |
1016 | ||
1017 | args->addr_ptr = (uint64_t) addr; | |
1018 | ||
1019 | return 0; | |
1020 | } | |
1021 | ||
de151cf6 JB |
1022 | /** |
1023 | * i915_gem_fault - fault a page into the GTT | |
1024 | * vma: VMA in question | |
1025 | * vmf: fault info | |
1026 | * | |
1027 | * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped | |
1028 | * from userspace. The fault handler takes care of binding the object to | |
1029 | * the GTT (if needed), allocating and programming a fence register (again, | |
1030 | * only if needed based on whether the old reg is still valid or the object | |
1031 | * is tiled) and inserting a new PTE into the faulting process. | |
1032 | * | |
1033 | * Note that the faulting process may involve evicting existing objects | |
1034 | * from the GTT and/or fence registers to make room. So performance may | |
1035 | * suffer if the GTT working set is large or there are few fence registers | |
1036 | * left. | |
1037 | */ | |
1038 | int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf) | |
1039 | { | |
05394f39 CW |
1040 | struct drm_i915_gem_object *obj = to_intel_bo(vma->vm_private_data); |
1041 | struct drm_device *dev = obj->base.dev; | |
7d1c4804 | 1042 | drm_i915_private_t *dev_priv = dev->dev_private; |
de151cf6 JB |
1043 | pgoff_t page_offset; |
1044 | unsigned long pfn; | |
1045 | int ret = 0; | |
0f973f27 | 1046 | bool write = !!(vmf->flags & FAULT_FLAG_WRITE); |
de151cf6 JB |
1047 | |
1048 | /* We don't use vmf->pgoff since that has the fake offset */ | |
1049 | page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >> | |
1050 | PAGE_SHIFT; | |
1051 | ||
d9bc7e9f CW |
1052 | ret = i915_mutex_lock_interruptible(dev); |
1053 | if (ret) | |
1054 | goto out; | |
a00b10c3 | 1055 | |
db53a302 CW |
1056 | trace_i915_gem_object_fault(obj, page_offset, true, write); |
1057 | ||
d9bc7e9f | 1058 | /* Now bind it into the GTT if needed */ |
919926ae CW |
1059 | if (!obj->map_and_fenceable) { |
1060 | ret = i915_gem_object_unbind(obj); | |
1061 | if (ret) | |
1062 | goto unlock; | |
a00b10c3 | 1063 | } |
05394f39 | 1064 | if (!obj->gtt_space) { |
75e9e915 | 1065 | ret = i915_gem_object_bind_to_gtt(obj, 0, true); |
c715089f CW |
1066 | if (ret) |
1067 | goto unlock; | |
de151cf6 | 1068 | |
e92d03bf EA |
1069 | ret = i915_gem_object_set_to_gtt_domain(obj, write); |
1070 | if (ret) | |
1071 | goto unlock; | |
1072 | } | |
4a684a41 | 1073 | |
74898d7e DV |
1074 | if (!obj->has_global_gtt_mapping) |
1075 | i915_gem_gtt_bind_object(obj, obj->cache_level); | |
1076 | ||
d9e86c0e CW |
1077 | if (obj->tiling_mode == I915_TILING_NONE) |
1078 | ret = i915_gem_object_put_fence(obj); | |
1079 | else | |
ce453d81 | 1080 | ret = i915_gem_object_get_fence(obj, NULL); |
d9e86c0e CW |
1081 | if (ret) |
1082 | goto unlock; | |
de151cf6 | 1083 | |
05394f39 CW |
1084 | if (i915_gem_object_is_inactive(obj)) |
1085 | list_move_tail(&obj->mm_list, &dev_priv->mm.inactive_list); | |
7d1c4804 | 1086 | |
6299f992 CW |
1087 | obj->fault_mappable = true; |
1088 | ||
05394f39 | 1089 | pfn = ((dev->agp->base + obj->gtt_offset) >> PAGE_SHIFT) + |
de151cf6 JB |
1090 | page_offset; |
1091 | ||
1092 | /* Finally, remap it using the new GTT offset */ | |
1093 | ret = vm_insert_pfn(vma, (unsigned long)vmf->virtual_address, pfn); | |
c715089f | 1094 | unlock: |
de151cf6 | 1095 | mutex_unlock(&dev->struct_mutex); |
d9bc7e9f | 1096 | out: |
de151cf6 | 1097 | switch (ret) { |
d9bc7e9f | 1098 | case -EIO: |
045e769a | 1099 | case -EAGAIN: |
d9bc7e9f CW |
1100 | /* Give the error handler a chance to run and move the |
1101 | * objects off the GPU active list. Next time we service the | |
1102 | * fault, we should be able to transition the page into the | |
1103 | * GTT without touching the GPU (and so avoid further | |
1104 | * EIO/EGAIN). If the GPU is wedged, then there is no issue | |
1105 | * with coherency, just lost writes. | |
1106 | */ | |
045e769a | 1107 | set_need_resched(); |
c715089f CW |
1108 | case 0: |
1109 | case -ERESTARTSYS: | |
bed636ab | 1110 | case -EINTR: |
c715089f | 1111 | return VM_FAULT_NOPAGE; |
de151cf6 | 1112 | case -ENOMEM: |
de151cf6 | 1113 | return VM_FAULT_OOM; |
de151cf6 | 1114 | default: |
c715089f | 1115 | return VM_FAULT_SIGBUS; |
de151cf6 JB |
1116 | } |
1117 | } | |
1118 | ||
901782b2 CW |
1119 | /** |
1120 | * i915_gem_release_mmap - remove physical page mappings | |
1121 | * @obj: obj in question | |
1122 | * | |
af901ca1 | 1123 | * Preserve the reservation of the mmapping with the DRM core code, but |
901782b2 CW |
1124 | * relinquish ownership of the pages back to the system. |
1125 | * | |
1126 | * It is vital that we remove the page mapping if we have mapped a tiled | |
1127 | * object through the GTT and then lose the fence register due to | |
1128 | * resource pressure. Similarly if the object has been moved out of the | |
1129 | * aperture, than pages mapped into userspace must be revoked. Removing the | |
1130 | * mapping will then trigger a page fault on the next user access, allowing | |
1131 | * fixup by i915_gem_fault(). | |
1132 | */ | |
d05ca301 | 1133 | void |
05394f39 | 1134 | i915_gem_release_mmap(struct drm_i915_gem_object *obj) |
901782b2 | 1135 | { |
6299f992 CW |
1136 | if (!obj->fault_mappable) |
1137 | return; | |
901782b2 | 1138 | |
f6e47884 CW |
1139 | if (obj->base.dev->dev_mapping) |
1140 | unmap_mapping_range(obj->base.dev->dev_mapping, | |
1141 | (loff_t)obj->base.map_list.hash.key<<PAGE_SHIFT, | |
1142 | obj->base.size, 1); | |
fb7d516a | 1143 | |
6299f992 | 1144 | obj->fault_mappable = false; |
901782b2 CW |
1145 | } |
1146 | ||
92b88aeb | 1147 | static uint32_t |
e28f8711 | 1148 | i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode) |
92b88aeb | 1149 | { |
e28f8711 | 1150 | uint32_t gtt_size; |
92b88aeb CW |
1151 | |
1152 | if (INTEL_INFO(dev)->gen >= 4 || | |
e28f8711 CW |
1153 | tiling_mode == I915_TILING_NONE) |
1154 | return size; | |
92b88aeb CW |
1155 | |
1156 | /* Previous chips need a power-of-two fence region when tiling */ | |
1157 | if (INTEL_INFO(dev)->gen == 3) | |
e28f8711 | 1158 | gtt_size = 1024*1024; |
92b88aeb | 1159 | else |
e28f8711 | 1160 | gtt_size = 512*1024; |
92b88aeb | 1161 | |
e28f8711 CW |
1162 | while (gtt_size < size) |
1163 | gtt_size <<= 1; | |
92b88aeb | 1164 | |
e28f8711 | 1165 | return gtt_size; |
92b88aeb CW |
1166 | } |
1167 | ||
de151cf6 JB |
1168 | /** |
1169 | * i915_gem_get_gtt_alignment - return required GTT alignment for an object | |
1170 | * @obj: object to check | |
1171 | * | |
1172 | * Return the required GTT alignment for an object, taking into account | |
5e783301 | 1173 | * potential fence register mapping. |
de151cf6 JB |
1174 | */ |
1175 | static uint32_t | |
e28f8711 CW |
1176 | i915_gem_get_gtt_alignment(struct drm_device *dev, |
1177 | uint32_t size, | |
1178 | int tiling_mode) | |
de151cf6 | 1179 | { |
de151cf6 JB |
1180 | /* |
1181 | * Minimum alignment is 4k (GTT page size), but might be greater | |
1182 | * if a fence register is needed for the object. | |
1183 | */ | |
a00b10c3 | 1184 | if (INTEL_INFO(dev)->gen >= 4 || |
e28f8711 | 1185 | tiling_mode == I915_TILING_NONE) |
de151cf6 JB |
1186 | return 4096; |
1187 | ||
a00b10c3 CW |
1188 | /* |
1189 | * Previous chips need to be aligned to the size of the smallest | |
1190 | * fence register that can contain the object. | |
1191 | */ | |
e28f8711 | 1192 | return i915_gem_get_gtt_size(dev, size, tiling_mode); |
a00b10c3 CW |
1193 | } |
1194 | ||
5e783301 DV |
1195 | /** |
1196 | * i915_gem_get_unfenced_gtt_alignment - return required GTT alignment for an | |
1197 | * unfenced object | |
e28f8711 CW |
1198 | * @dev: the device |
1199 | * @size: size of the object | |
1200 | * @tiling_mode: tiling mode of the object | |
5e783301 DV |
1201 | * |
1202 | * Return the required GTT alignment for an object, only taking into account | |
1203 | * unfenced tiled surface requirements. | |
1204 | */ | |
467cffba | 1205 | uint32_t |
e28f8711 CW |
1206 | i915_gem_get_unfenced_gtt_alignment(struct drm_device *dev, |
1207 | uint32_t size, | |
1208 | int tiling_mode) | |
5e783301 | 1209 | { |
5e783301 DV |
1210 | /* |
1211 | * Minimum alignment is 4k (GTT page size) for sane hw. | |
1212 | */ | |
1213 | if (INTEL_INFO(dev)->gen >= 4 || IS_G33(dev) || | |
e28f8711 | 1214 | tiling_mode == I915_TILING_NONE) |
5e783301 DV |
1215 | return 4096; |
1216 | ||
e28f8711 CW |
1217 | /* Previous hardware however needs to be aligned to a power-of-two |
1218 | * tile height. The simplest method for determining this is to reuse | |
1219 | * the power-of-tile object size. | |
5e783301 | 1220 | */ |
e28f8711 | 1221 | return i915_gem_get_gtt_size(dev, size, tiling_mode); |
5e783301 DV |
1222 | } |
1223 | ||
de151cf6 | 1224 | int |
ff72145b DA |
1225 | i915_gem_mmap_gtt(struct drm_file *file, |
1226 | struct drm_device *dev, | |
1227 | uint32_t handle, | |
1228 | uint64_t *offset) | |
de151cf6 | 1229 | { |
da761a6e | 1230 | struct drm_i915_private *dev_priv = dev->dev_private; |
05394f39 | 1231 | struct drm_i915_gem_object *obj; |
de151cf6 JB |
1232 | int ret; |
1233 | ||
1234 | if (!(dev->driver->driver_features & DRIVER_GEM)) | |
1235 | return -ENODEV; | |
1236 | ||
76c1dec1 | 1237 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 1238 | if (ret) |
76c1dec1 | 1239 | return ret; |
de151cf6 | 1240 | |
ff72145b | 1241 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle)); |
c8725226 | 1242 | if (&obj->base == NULL) { |
1d7cfea1 CW |
1243 | ret = -ENOENT; |
1244 | goto unlock; | |
1245 | } | |
de151cf6 | 1246 | |
05394f39 | 1247 | if (obj->base.size > dev_priv->mm.gtt_mappable_end) { |
da761a6e | 1248 | ret = -E2BIG; |
ff56b0bc | 1249 | goto out; |
da761a6e CW |
1250 | } |
1251 | ||
05394f39 | 1252 | if (obj->madv != I915_MADV_WILLNEED) { |
ab18282d | 1253 | DRM_ERROR("Attempting to mmap a purgeable buffer\n"); |
1d7cfea1 CW |
1254 | ret = -EINVAL; |
1255 | goto out; | |
ab18282d CW |
1256 | } |
1257 | ||
05394f39 | 1258 | if (!obj->base.map_list.map) { |
b464e9a2 | 1259 | ret = drm_gem_create_mmap_offset(&obj->base); |
1d7cfea1 CW |
1260 | if (ret) |
1261 | goto out; | |
de151cf6 JB |
1262 | } |
1263 | ||
ff72145b | 1264 | *offset = (u64)obj->base.map_list.hash.key << PAGE_SHIFT; |
de151cf6 | 1265 | |
1d7cfea1 | 1266 | out: |
05394f39 | 1267 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 1268 | unlock: |
de151cf6 | 1269 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 1270 | return ret; |
de151cf6 JB |
1271 | } |
1272 | ||
ff72145b DA |
1273 | /** |
1274 | * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing | |
1275 | * @dev: DRM device | |
1276 | * @data: GTT mapping ioctl data | |
1277 | * @file: GEM object info | |
1278 | * | |
1279 | * Simply returns the fake offset to userspace so it can mmap it. | |
1280 | * The mmap call will end up in drm_gem_mmap(), which will set things | |
1281 | * up so we can get faults in the handler above. | |
1282 | * | |
1283 | * The fault handler will take care of binding the object into the GTT | |
1284 | * (since it may have been evicted to make room for something), allocating | |
1285 | * a fence register, and mapping the appropriate aperture address into | |
1286 | * userspace. | |
1287 | */ | |
1288 | int | |
1289 | i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data, | |
1290 | struct drm_file *file) | |
1291 | { | |
1292 | struct drm_i915_gem_mmap_gtt *args = data; | |
1293 | ||
1294 | if (!(dev->driver->driver_features & DRIVER_GEM)) | |
1295 | return -ENODEV; | |
1296 | ||
1297 | return i915_gem_mmap_gtt(file, dev, args->handle, &args->offset); | |
1298 | } | |
1299 | ||
1300 | ||
e5281ccd | 1301 | static int |
05394f39 | 1302 | i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj, |
e5281ccd CW |
1303 | gfp_t gfpmask) |
1304 | { | |
e5281ccd CW |
1305 | int page_count, i; |
1306 | struct address_space *mapping; | |
1307 | struct inode *inode; | |
1308 | struct page *page; | |
1309 | ||
1310 | /* Get the list of pages out of our struct file. They'll be pinned | |
1311 | * at this point until we release them. | |
1312 | */ | |
05394f39 CW |
1313 | page_count = obj->base.size / PAGE_SIZE; |
1314 | BUG_ON(obj->pages != NULL); | |
1315 | obj->pages = drm_malloc_ab(page_count, sizeof(struct page *)); | |
1316 | if (obj->pages == NULL) | |
e5281ccd CW |
1317 | return -ENOMEM; |
1318 | ||
05394f39 | 1319 | inode = obj->base.filp->f_path.dentry->d_inode; |
e5281ccd | 1320 | mapping = inode->i_mapping; |
5949eac4 HD |
1321 | gfpmask |= mapping_gfp_mask(mapping); |
1322 | ||
e5281ccd | 1323 | for (i = 0; i < page_count; i++) { |
5949eac4 | 1324 | page = shmem_read_mapping_page_gfp(mapping, i, gfpmask); |
e5281ccd CW |
1325 | if (IS_ERR(page)) |
1326 | goto err_pages; | |
1327 | ||
05394f39 | 1328 | obj->pages[i] = page; |
e5281ccd CW |
1329 | } |
1330 | ||
6dacfd2f | 1331 | if (i915_gem_object_needs_bit17_swizzle(obj)) |
e5281ccd CW |
1332 | i915_gem_object_do_bit_17_swizzle(obj); |
1333 | ||
1334 | return 0; | |
1335 | ||
1336 | err_pages: | |
1337 | while (i--) | |
05394f39 | 1338 | page_cache_release(obj->pages[i]); |
e5281ccd | 1339 | |
05394f39 CW |
1340 | drm_free_large(obj->pages); |
1341 | obj->pages = NULL; | |
e5281ccd CW |
1342 | return PTR_ERR(page); |
1343 | } | |
1344 | ||
5cdf5881 | 1345 | static void |
05394f39 | 1346 | i915_gem_object_put_pages_gtt(struct drm_i915_gem_object *obj) |
673a394b | 1347 | { |
05394f39 | 1348 | int page_count = obj->base.size / PAGE_SIZE; |
673a394b EA |
1349 | int i; |
1350 | ||
05394f39 | 1351 | BUG_ON(obj->madv == __I915_MADV_PURGED); |
673a394b | 1352 | |
6dacfd2f | 1353 | if (i915_gem_object_needs_bit17_swizzle(obj)) |
280b713b EA |
1354 | i915_gem_object_save_bit_17_swizzle(obj); |
1355 | ||
05394f39 CW |
1356 | if (obj->madv == I915_MADV_DONTNEED) |
1357 | obj->dirty = 0; | |
3ef94daa CW |
1358 | |
1359 | for (i = 0; i < page_count; i++) { | |
05394f39 CW |
1360 | if (obj->dirty) |
1361 | set_page_dirty(obj->pages[i]); | |
3ef94daa | 1362 | |
05394f39 CW |
1363 | if (obj->madv == I915_MADV_WILLNEED) |
1364 | mark_page_accessed(obj->pages[i]); | |
3ef94daa | 1365 | |
05394f39 | 1366 | page_cache_release(obj->pages[i]); |
3ef94daa | 1367 | } |
05394f39 | 1368 | obj->dirty = 0; |
673a394b | 1369 | |
05394f39 CW |
1370 | drm_free_large(obj->pages); |
1371 | obj->pages = NULL; | |
673a394b EA |
1372 | } |
1373 | ||
54cf91dc | 1374 | void |
05394f39 | 1375 | i915_gem_object_move_to_active(struct drm_i915_gem_object *obj, |
1ec14ad3 CW |
1376 | struct intel_ring_buffer *ring, |
1377 | u32 seqno) | |
673a394b | 1378 | { |
05394f39 | 1379 | struct drm_device *dev = obj->base.dev; |
69dc4987 | 1380 | struct drm_i915_private *dev_priv = dev->dev_private; |
617dbe27 | 1381 | |
852835f3 | 1382 | BUG_ON(ring == NULL); |
05394f39 | 1383 | obj->ring = ring; |
673a394b EA |
1384 | |
1385 | /* Add a reference if we're newly entering the active list. */ | |
05394f39 CW |
1386 | if (!obj->active) { |
1387 | drm_gem_object_reference(&obj->base); | |
1388 | obj->active = 1; | |
673a394b | 1389 | } |
e35a41de | 1390 | |
673a394b | 1391 | /* Move from whatever list we were on to the tail of execution. */ |
05394f39 CW |
1392 | list_move_tail(&obj->mm_list, &dev_priv->mm.active_list); |
1393 | list_move_tail(&obj->ring_list, &ring->active_list); | |
caea7476 | 1394 | |
05394f39 | 1395 | obj->last_rendering_seqno = seqno; |
caea7476 CW |
1396 | if (obj->fenced_gpu_access) { |
1397 | struct drm_i915_fence_reg *reg; | |
1398 | ||
1399 | BUG_ON(obj->fence_reg == I915_FENCE_REG_NONE); | |
1400 | ||
1401 | obj->last_fenced_seqno = seqno; | |
1402 | obj->last_fenced_ring = ring; | |
1403 | ||
1404 | reg = &dev_priv->fence_regs[obj->fence_reg]; | |
1405 | list_move_tail(®->lru_list, &dev_priv->mm.fence_list); | |
1406 | } | |
1407 | } | |
1408 | ||
1409 | static void | |
1410 | i915_gem_object_move_off_active(struct drm_i915_gem_object *obj) | |
1411 | { | |
1412 | list_del_init(&obj->ring_list); | |
1413 | obj->last_rendering_seqno = 0; | |
673a394b EA |
1414 | } |
1415 | ||
ce44b0ea | 1416 | static void |
05394f39 | 1417 | i915_gem_object_move_to_flushing(struct drm_i915_gem_object *obj) |
ce44b0ea | 1418 | { |
05394f39 | 1419 | struct drm_device *dev = obj->base.dev; |
ce44b0ea | 1420 | drm_i915_private_t *dev_priv = dev->dev_private; |
ce44b0ea | 1421 | |
05394f39 CW |
1422 | BUG_ON(!obj->active); |
1423 | list_move_tail(&obj->mm_list, &dev_priv->mm.flushing_list); | |
caea7476 CW |
1424 | |
1425 | i915_gem_object_move_off_active(obj); | |
1426 | } | |
1427 | ||
1428 | static void | |
1429 | i915_gem_object_move_to_inactive(struct drm_i915_gem_object *obj) | |
1430 | { | |
1431 | struct drm_device *dev = obj->base.dev; | |
1432 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1433 | ||
1434 | if (obj->pin_count != 0) | |
1435 | list_move_tail(&obj->mm_list, &dev_priv->mm.pinned_list); | |
1436 | else | |
1437 | list_move_tail(&obj->mm_list, &dev_priv->mm.inactive_list); | |
1438 | ||
1439 | BUG_ON(!list_empty(&obj->gpu_write_list)); | |
1440 | BUG_ON(!obj->active); | |
1441 | obj->ring = NULL; | |
1442 | ||
1443 | i915_gem_object_move_off_active(obj); | |
1444 | obj->fenced_gpu_access = false; | |
caea7476 CW |
1445 | |
1446 | obj->active = 0; | |
87ca9c8a | 1447 | obj->pending_gpu_write = false; |
caea7476 CW |
1448 | drm_gem_object_unreference(&obj->base); |
1449 | ||
1450 | WARN_ON(i915_verify_lists(dev)); | |
ce44b0ea | 1451 | } |
673a394b | 1452 | |
963b4836 CW |
1453 | /* Immediately discard the backing storage */ |
1454 | static void | |
05394f39 | 1455 | i915_gem_object_truncate(struct drm_i915_gem_object *obj) |
963b4836 | 1456 | { |
bb6baf76 | 1457 | struct inode *inode; |
963b4836 | 1458 | |
ae9fed6b CW |
1459 | /* Our goal here is to return as much of the memory as |
1460 | * is possible back to the system as we are called from OOM. | |
1461 | * To do this we must instruct the shmfs to drop all of its | |
e2377fe0 | 1462 | * backing pages, *now*. |
ae9fed6b | 1463 | */ |
05394f39 | 1464 | inode = obj->base.filp->f_path.dentry->d_inode; |
e2377fe0 | 1465 | shmem_truncate_range(inode, 0, (loff_t)-1); |
bb6baf76 | 1466 | |
a14917ee CW |
1467 | if (obj->base.map_list.map) |
1468 | drm_gem_free_mmap_offset(&obj->base); | |
1469 | ||
05394f39 | 1470 | obj->madv = __I915_MADV_PURGED; |
963b4836 CW |
1471 | } |
1472 | ||
1473 | static inline int | |
05394f39 | 1474 | i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj) |
963b4836 | 1475 | { |
05394f39 | 1476 | return obj->madv == I915_MADV_DONTNEED; |
963b4836 CW |
1477 | } |
1478 | ||
63560396 | 1479 | static void |
db53a302 CW |
1480 | i915_gem_process_flushing_list(struct intel_ring_buffer *ring, |
1481 | uint32_t flush_domains) | |
63560396 | 1482 | { |
05394f39 | 1483 | struct drm_i915_gem_object *obj, *next; |
63560396 | 1484 | |
05394f39 | 1485 | list_for_each_entry_safe(obj, next, |
64193406 | 1486 | &ring->gpu_write_list, |
63560396 | 1487 | gpu_write_list) { |
05394f39 CW |
1488 | if (obj->base.write_domain & flush_domains) { |
1489 | uint32_t old_write_domain = obj->base.write_domain; | |
63560396 | 1490 | |
05394f39 CW |
1491 | obj->base.write_domain = 0; |
1492 | list_del_init(&obj->gpu_write_list); | |
1ec14ad3 | 1493 | i915_gem_object_move_to_active(obj, ring, |
db53a302 | 1494 | i915_gem_next_request_seqno(ring)); |
63560396 | 1495 | |
63560396 | 1496 | trace_i915_gem_object_change_domain(obj, |
05394f39 | 1497 | obj->base.read_domains, |
63560396 DV |
1498 | old_write_domain); |
1499 | } | |
1500 | } | |
1501 | } | |
8187a2b7 | 1502 | |
53d227f2 DV |
1503 | static u32 |
1504 | i915_gem_get_seqno(struct drm_device *dev) | |
1505 | { | |
1506 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1507 | u32 seqno = dev_priv->next_seqno; | |
1508 | ||
1509 | /* reserve 0 for non-seqno */ | |
1510 | if (++dev_priv->next_seqno == 0) | |
1511 | dev_priv->next_seqno = 1; | |
1512 | ||
1513 | return seqno; | |
1514 | } | |
1515 | ||
1516 | u32 | |
1517 | i915_gem_next_request_seqno(struct intel_ring_buffer *ring) | |
1518 | { | |
1519 | if (ring->outstanding_lazy_request == 0) | |
1520 | ring->outstanding_lazy_request = i915_gem_get_seqno(ring->dev); | |
1521 | ||
1522 | return ring->outstanding_lazy_request; | |
1523 | } | |
1524 | ||
3cce469c | 1525 | int |
db53a302 | 1526 | i915_add_request(struct intel_ring_buffer *ring, |
f787a5f5 | 1527 | struct drm_file *file, |
db53a302 | 1528 | struct drm_i915_gem_request *request) |
673a394b | 1529 | { |
db53a302 | 1530 | drm_i915_private_t *dev_priv = ring->dev->dev_private; |
673a394b | 1531 | uint32_t seqno; |
a71d8d94 | 1532 | u32 request_ring_position; |
673a394b | 1533 | int was_empty; |
3cce469c CW |
1534 | int ret; |
1535 | ||
1536 | BUG_ON(request == NULL); | |
53d227f2 | 1537 | seqno = i915_gem_next_request_seqno(ring); |
673a394b | 1538 | |
a71d8d94 CW |
1539 | /* Record the position of the start of the request so that |
1540 | * should we detect the updated seqno part-way through the | |
1541 | * GPU processing the request, we never over-estimate the | |
1542 | * position of the head. | |
1543 | */ | |
1544 | request_ring_position = intel_ring_get_tail(ring); | |
1545 | ||
3cce469c CW |
1546 | ret = ring->add_request(ring, &seqno); |
1547 | if (ret) | |
1548 | return ret; | |
673a394b | 1549 | |
db53a302 | 1550 | trace_i915_gem_request_add(ring, seqno); |
673a394b EA |
1551 | |
1552 | request->seqno = seqno; | |
852835f3 | 1553 | request->ring = ring; |
a71d8d94 | 1554 | request->tail = request_ring_position; |
673a394b | 1555 | request->emitted_jiffies = jiffies; |
852835f3 ZN |
1556 | was_empty = list_empty(&ring->request_list); |
1557 | list_add_tail(&request->list, &ring->request_list); | |
1558 | ||
db53a302 CW |
1559 | if (file) { |
1560 | struct drm_i915_file_private *file_priv = file->driver_priv; | |
1561 | ||
1c25595f | 1562 | spin_lock(&file_priv->mm.lock); |
f787a5f5 | 1563 | request->file_priv = file_priv; |
b962442e | 1564 | list_add_tail(&request->client_list, |
f787a5f5 | 1565 | &file_priv->mm.request_list); |
1c25595f | 1566 | spin_unlock(&file_priv->mm.lock); |
b962442e | 1567 | } |
673a394b | 1568 | |
5391d0cf | 1569 | ring->outstanding_lazy_request = 0; |
db53a302 | 1570 | |
f65d9421 | 1571 | if (!dev_priv->mm.suspended) { |
3e0dc6b0 BW |
1572 | if (i915_enable_hangcheck) { |
1573 | mod_timer(&dev_priv->hangcheck_timer, | |
1574 | jiffies + | |
1575 | msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)); | |
1576 | } | |
f65d9421 | 1577 | if (was_empty) |
b3b079db CW |
1578 | queue_delayed_work(dev_priv->wq, |
1579 | &dev_priv->mm.retire_work, HZ); | |
f65d9421 | 1580 | } |
3cce469c | 1581 | return 0; |
673a394b EA |
1582 | } |
1583 | ||
f787a5f5 CW |
1584 | static inline void |
1585 | i915_gem_request_remove_from_client(struct drm_i915_gem_request *request) | |
673a394b | 1586 | { |
1c25595f | 1587 | struct drm_i915_file_private *file_priv = request->file_priv; |
673a394b | 1588 | |
1c25595f CW |
1589 | if (!file_priv) |
1590 | return; | |
1c5d22f7 | 1591 | |
1c25595f | 1592 | spin_lock(&file_priv->mm.lock); |
09bfa517 HRK |
1593 | if (request->file_priv) { |
1594 | list_del(&request->client_list); | |
1595 | request->file_priv = NULL; | |
1596 | } | |
1c25595f | 1597 | spin_unlock(&file_priv->mm.lock); |
673a394b | 1598 | } |
673a394b | 1599 | |
dfaae392 CW |
1600 | static void i915_gem_reset_ring_lists(struct drm_i915_private *dev_priv, |
1601 | struct intel_ring_buffer *ring) | |
9375e446 | 1602 | { |
dfaae392 CW |
1603 | while (!list_empty(&ring->request_list)) { |
1604 | struct drm_i915_gem_request *request; | |
673a394b | 1605 | |
dfaae392 CW |
1606 | request = list_first_entry(&ring->request_list, |
1607 | struct drm_i915_gem_request, | |
1608 | list); | |
de151cf6 | 1609 | |
dfaae392 | 1610 | list_del(&request->list); |
f787a5f5 | 1611 | i915_gem_request_remove_from_client(request); |
dfaae392 CW |
1612 | kfree(request); |
1613 | } | |
673a394b | 1614 | |
dfaae392 | 1615 | while (!list_empty(&ring->active_list)) { |
05394f39 | 1616 | struct drm_i915_gem_object *obj; |
9375e446 | 1617 | |
05394f39 CW |
1618 | obj = list_first_entry(&ring->active_list, |
1619 | struct drm_i915_gem_object, | |
1620 | ring_list); | |
9375e446 | 1621 | |
05394f39 CW |
1622 | obj->base.write_domain = 0; |
1623 | list_del_init(&obj->gpu_write_list); | |
1624 | i915_gem_object_move_to_inactive(obj); | |
673a394b EA |
1625 | } |
1626 | } | |
1627 | ||
312817a3 CW |
1628 | static void i915_gem_reset_fences(struct drm_device *dev) |
1629 | { | |
1630 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1631 | int i; | |
1632 | ||
4b9de737 | 1633 | for (i = 0; i < dev_priv->num_fence_regs; i++) { |
312817a3 | 1634 | struct drm_i915_fence_reg *reg = &dev_priv->fence_regs[i]; |
7d2cb39c CW |
1635 | struct drm_i915_gem_object *obj = reg->obj; |
1636 | ||
1637 | if (!obj) | |
1638 | continue; | |
1639 | ||
1640 | if (obj->tiling_mode) | |
1641 | i915_gem_release_mmap(obj); | |
1642 | ||
d9e86c0e CW |
1643 | reg->obj->fence_reg = I915_FENCE_REG_NONE; |
1644 | reg->obj->fenced_gpu_access = false; | |
1645 | reg->obj->last_fenced_seqno = 0; | |
1646 | reg->obj->last_fenced_ring = NULL; | |
1647 | i915_gem_clear_fence_reg(dev, reg); | |
312817a3 CW |
1648 | } |
1649 | } | |
1650 | ||
069efc1d | 1651 | void i915_gem_reset(struct drm_device *dev) |
673a394b | 1652 | { |
77f01230 | 1653 | struct drm_i915_private *dev_priv = dev->dev_private; |
05394f39 | 1654 | struct drm_i915_gem_object *obj; |
1ec14ad3 | 1655 | int i; |
673a394b | 1656 | |
1ec14ad3 CW |
1657 | for (i = 0; i < I915_NUM_RINGS; i++) |
1658 | i915_gem_reset_ring_lists(dev_priv, &dev_priv->ring[i]); | |
dfaae392 CW |
1659 | |
1660 | /* Remove anything from the flushing lists. The GPU cache is likely | |
1661 | * to be lost on reset along with the data, so simply move the | |
1662 | * lost bo to the inactive list. | |
1663 | */ | |
1664 | while (!list_empty(&dev_priv->mm.flushing_list)) { | |
0206e353 | 1665 | obj = list_first_entry(&dev_priv->mm.flushing_list, |
05394f39 CW |
1666 | struct drm_i915_gem_object, |
1667 | mm_list); | |
dfaae392 | 1668 | |
05394f39 CW |
1669 | obj->base.write_domain = 0; |
1670 | list_del_init(&obj->gpu_write_list); | |
1671 | i915_gem_object_move_to_inactive(obj); | |
dfaae392 CW |
1672 | } |
1673 | ||
1674 | /* Move everything out of the GPU domains to ensure we do any | |
1675 | * necessary invalidation upon reuse. | |
1676 | */ | |
05394f39 | 1677 | list_for_each_entry(obj, |
77f01230 | 1678 | &dev_priv->mm.inactive_list, |
69dc4987 | 1679 | mm_list) |
77f01230 | 1680 | { |
05394f39 | 1681 | obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS; |
77f01230 | 1682 | } |
069efc1d CW |
1683 | |
1684 | /* The fence registers are invalidated so clear them out */ | |
312817a3 | 1685 | i915_gem_reset_fences(dev); |
673a394b EA |
1686 | } |
1687 | ||
1688 | /** | |
1689 | * This function clears the request list as sequence numbers are passed. | |
1690 | */ | |
a71d8d94 | 1691 | void |
db53a302 | 1692 | i915_gem_retire_requests_ring(struct intel_ring_buffer *ring) |
673a394b | 1693 | { |
673a394b | 1694 | uint32_t seqno; |
1ec14ad3 | 1695 | int i; |
673a394b | 1696 | |
db53a302 | 1697 | if (list_empty(&ring->request_list)) |
6c0594a3 KW |
1698 | return; |
1699 | ||
db53a302 | 1700 | WARN_ON(i915_verify_lists(ring->dev)); |
673a394b | 1701 | |
78501eac | 1702 | seqno = ring->get_seqno(ring); |
1ec14ad3 | 1703 | |
076e2c0e | 1704 | for (i = 0; i < ARRAY_SIZE(ring->sync_seqno); i++) |
1ec14ad3 CW |
1705 | if (seqno >= ring->sync_seqno[i]) |
1706 | ring->sync_seqno[i] = 0; | |
1707 | ||
852835f3 | 1708 | while (!list_empty(&ring->request_list)) { |
673a394b | 1709 | struct drm_i915_gem_request *request; |
673a394b | 1710 | |
852835f3 | 1711 | request = list_first_entry(&ring->request_list, |
673a394b EA |
1712 | struct drm_i915_gem_request, |
1713 | list); | |
673a394b | 1714 | |
dfaae392 | 1715 | if (!i915_seqno_passed(seqno, request->seqno)) |
b84d5f0c CW |
1716 | break; |
1717 | ||
db53a302 | 1718 | trace_i915_gem_request_retire(ring, request->seqno); |
a71d8d94 CW |
1719 | /* We know the GPU must have read the request to have |
1720 | * sent us the seqno + interrupt, so use the position | |
1721 | * of tail of the request to update the last known position | |
1722 | * of the GPU head. | |
1723 | */ | |
1724 | ring->last_retired_head = request->tail; | |
b84d5f0c CW |
1725 | |
1726 | list_del(&request->list); | |
f787a5f5 | 1727 | i915_gem_request_remove_from_client(request); |
b84d5f0c CW |
1728 | kfree(request); |
1729 | } | |
673a394b | 1730 | |
b84d5f0c CW |
1731 | /* Move any buffers on the active list that are no longer referenced |
1732 | * by the ringbuffer to the flushing/inactive lists as appropriate. | |
1733 | */ | |
1734 | while (!list_empty(&ring->active_list)) { | |
05394f39 | 1735 | struct drm_i915_gem_object *obj; |
b84d5f0c | 1736 | |
0206e353 | 1737 | obj = list_first_entry(&ring->active_list, |
05394f39 CW |
1738 | struct drm_i915_gem_object, |
1739 | ring_list); | |
673a394b | 1740 | |
05394f39 | 1741 | if (!i915_seqno_passed(seqno, obj->last_rendering_seqno)) |
673a394b | 1742 | break; |
b84d5f0c | 1743 | |
05394f39 | 1744 | if (obj->base.write_domain != 0) |
b84d5f0c CW |
1745 | i915_gem_object_move_to_flushing(obj); |
1746 | else | |
1747 | i915_gem_object_move_to_inactive(obj); | |
673a394b | 1748 | } |
9d34e5db | 1749 | |
db53a302 CW |
1750 | if (unlikely(ring->trace_irq_seqno && |
1751 | i915_seqno_passed(seqno, ring->trace_irq_seqno))) { | |
1ec14ad3 | 1752 | ring->irq_put(ring); |
db53a302 | 1753 | ring->trace_irq_seqno = 0; |
9d34e5db | 1754 | } |
23bc5982 | 1755 | |
db53a302 | 1756 | WARN_ON(i915_verify_lists(ring->dev)); |
673a394b EA |
1757 | } |
1758 | ||
b09a1fec CW |
1759 | void |
1760 | i915_gem_retire_requests(struct drm_device *dev) | |
1761 | { | |
1762 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1ec14ad3 | 1763 | int i; |
b09a1fec | 1764 | |
be72615b | 1765 | if (!list_empty(&dev_priv->mm.deferred_free_list)) { |
05394f39 | 1766 | struct drm_i915_gem_object *obj, *next; |
be72615b CW |
1767 | |
1768 | /* We must be careful that during unbind() we do not | |
1769 | * accidentally infinitely recurse into retire requests. | |
1770 | * Currently: | |
1771 | * retire -> free -> unbind -> wait -> retire_ring | |
1772 | */ | |
05394f39 | 1773 | list_for_each_entry_safe(obj, next, |
be72615b | 1774 | &dev_priv->mm.deferred_free_list, |
69dc4987 | 1775 | mm_list) |
05394f39 | 1776 | i915_gem_free_object_tail(obj); |
be72615b CW |
1777 | } |
1778 | ||
1ec14ad3 | 1779 | for (i = 0; i < I915_NUM_RINGS; i++) |
db53a302 | 1780 | i915_gem_retire_requests_ring(&dev_priv->ring[i]); |
b09a1fec CW |
1781 | } |
1782 | ||
75ef9da2 | 1783 | static void |
673a394b EA |
1784 | i915_gem_retire_work_handler(struct work_struct *work) |
1785 | { | |
1786 | drm_i915_private_t *dev_priv; | |
1787 | struct drm_device *dev; | |
0a58705b CW |
1788 | bool idle; |
1789 | int i; | |
673a394b EA |
1790 | |
1791 | dev_priv = container_of(work, drm_i915_private_t, | |
1792 | mm.retire_work.work); | |
1793 | dev = dev_priv->dev; | |
1794 | ||
891b48cf CW |
1795 | /* Come back later if the device is busy... */ |
1796 | if (!mutex_trylock(&dev->struct_mutex)) { | |
1797 | queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ); | |
1798 | return; | |
1799 | } | |
1800 | ||
b09a1fec | 1801 | i915_gem_retire_requests(dev); |
d1b851fc | 1802 | |
0a58705b CW |
1803 | /* Send a periodic flush down the ring so we don't hold onto GEM |
1804 | * objects indefinitely. | |
1805 | */ | |
1806 | idle = true; | |
1807 | for (i = 0; i < I915_NUM_RINGS; i++) { | |
1808 | struct intel_ring_buffer *ring = &dev_priv->ring[i]; | |
1809 | ||
1810 | if (!list_empty(&ring->gpu_write_list)) { | |
1811 | struct drm_i915_gem_request *request; | |
1812 | int ret; | |
1813 | ||
db53a302 CW |
1814 | ret = i915_gem_flush_ring(ring, |
1815 | 0, I915_GEM_GPU_DOMAINS); | |
0a58705b CW |
1816 | request = kzalloc(sizeof(*request), GFP_KERNEL); |
1817 | if (ret || request == NULL || | |
db53a302 | 1818 | i915_add_request(ring, NULL, request)) |
0a58705b CW |
1819 | kfree(request); |
1820 | } | |
1821 | ||
1822 | idle &= list_empty(&ring->request_list); | |
1823 | } | |
1824 | ||
1825 | if (!dev_priv->mm.suspended && !idle) | |
9c9fe1f8 | 1826 | queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ); |
0a58705b | 1827 | |
673a394b EA |
1828 | mutex_unlock(&dev->struct_mutex); |
1829 | } | |
1830 | ||
db53a302 CW |
1831 | /** |
1832 | * Waits for a sequence number to be signaled, and cleans up the | |
1833 | * request and object lists appropriately for that event. | |
1834 | */ | |
5a5a0c64 | 1835 | int |
db53a302 | 1836 | i915_wait_request(struct intel_ring_buffer *ring, |
b93f9cf1 BW |
1837 | uint32_t seqno, |
1838 | bool do_retire) | |
673a394b | 1839 | { |
db53a302 | 1840 | drm_i915_private_t *dev_priv = ring->dev->dev_private; |
802c7eb6 | 1841 | u32 ier; |
673a394b EA |
1842 | int ret = 0; |
1843 | ||
1844 | BUG_ON(seqno == 0); | |
1845 | ||
d9bc7e9f CW |
1846 | if (atomic_read(&dev_priv->mm.wedged)) { |
1847 | struct completion *x = &dev_priv->error_completion; | |
1848 | bool recovery_complete; | |
1849 | unsigned long flags; | |
1850 | ||
1851 | /* Give the error handler a chance to run. */ | |
1852 | spin_lock_irqsave(&x->wait.lock, flags); | |
1853 | recovery_complete = x->done > 0; | |
1854 | spin_unlock_irqrestore(&x->wait.lock, flags); | |
1855 | ||
1856 | return recovery_complete ? -EIO : -EAGAIN; | |
1857 | } | |
30dbf0c0 | 1858 | |
5d97eb69 | 1859 | if (seqno == ring->outstanding_lazy_request) { |
3cce469c CW |
1860 | struct drm_i915_gem_request *request; |
1861 | ||
1862 | request = kzalloc(sizeof(*request), GFP_KERNEL); | |
1863 | if (request == NULL) | |
e35a41de | 1864 | return -ENOMEM; |
3cce469c | 1865 | |
db53a302 | 1866 | ret = i915_add_request(ring, NULL, request); |
3cce469c CW |
1867 | if (ret) { |
1868 | kfree(request); | |
1869 | return ret; | |
1870 | } | |
1871 | ||
1872 | seqno = request->seqno; | |
e35a41de | 1873 | } |
ffed1d09 | 1874 | |
78501eac | 1875 | if (!i915_seqno_passed(ring->get_seqno(ring), seqno)) { |
db53a302 | 1876 | if (HAS_PCH_SPLIT(ring->dev)) |
036a4a7d ZW |
1877 | ier = I915_READ(DEIER) | I915_READ(GTIER); |
1878 | else | |
1879 | ier = I915_READ(IER); | |
802c7eb6 JB |
1880 | if (!ier) { |
1881 | DRM_ERROR("something (likely vbetool) disabled " | |
1882 | "interrupts, re-enabling\n"); | |
f01c22fd CW |
1883 | ring->dev->driver->irq_preinstall(ring->dev); |
1884 | ring->dev->driver->irq_postinstall(ring->dev); | |
802c7eb6 JB |
1885 | } |
1886 | ||
db53a302 | 1887 | trace_i915_gem_request_wait_begin(ring, seqno); |
1c5d22f7 | 1888 | |
b2223497 | 1889 | ring->waiting_seqno = seqno; |
b13c2b96 | 1890 | if (ring->irq_get(ring)) { |
ce453d81 | 1891 | if (dev_priv->mm.interruptible) |
b13c2b96 CW |
1892 | ret = wait_event_interruptible(ring->irq_queue, |
1893 | i915_seqno_passed(ring->get_seqno(ring), seqno) | |
1894 | || atomic_read(&dev_priv->mm.wedged)); | |
1895 | else | |
1896 | wait_event(ring->irq_queue, | |
1897 | i915_seqno_passed(ring->get_seqno(ring), seqno) | |
1898 | || atomic_read(&dev_priv->mm.wedged)); | |
1899 | ||
1900 | ring->irq_put(ring); | |
e959b5db EA |
1901 | } else if (wait_for_atomic(i915_seqno_passed(ring->get_seqno(ring), |
1902 | seqno) || | |
1903 | atomic_read(&dev_priv->mm.wedged), 3000)) | |
b5ba177d | 1904 | ret = -EBUSY; |
b2223497 | 1905 | ring->waiting_seqno = 0; |
1c5d22f7 | 1906 | |
db53a302 | 1907 | trace_i915_gem_request_wait_end(ring, seqno); |
673a394b | 1908 | } |
ba1234d1 | 1909 | if (atomic_read(&dev_priv->mm.wedged)) |
30dbf0c0 | 1910 | ret = -EAGAIN; |
673a394b | 1911 | |
673a394b EA |
1912 | /* Directly dispatch request retiring. While we have the work queue |
1913 | * to handle this, the waiter on a request often wants an associated | |
1914 | * buffer to have made it to the inactive list, and we would need | |
1915 | * a separate wait queue to handle that. | |
1916 | */ | |
b93f9cf1 | 1917 | if (ret == 0 && do_retire) |
db53a302 | 1918 | i915_gem_retire_requests_ring(ring); |
673a394b EA |
1919 | |
1920 | return ret; | |
1921 | } | |
1922 | ||
673a394b EA |
1923 | /** |
1924 | * Ensures that all rendering to the object has completed and the object is | |
1925 | * safe to unbind from the GTT or access from the CPU. | |
1926 | */ | |
54cf91dc | 1927 | int |
ce453d81 | 1928 | i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj) |
673a394b | 1929 | { |
673a394b EA |
1930 | int ret; |
1931 | ||
e47c68e9 EA |
1932 | /* This function only exists to support waiting for existing rendering, |
1933 | * not for emitting required flushes. | |
673a394b | 1934 | */ |
05394f39 | 1935 | BUG_ON((obj->base.write_domain & I915_GEM_GPU_DOMAINS) != 0); |
673a394b EA |
1936 | |
1937 | /* If there is rendering queued on the buffer being evicted, wait for | |
1938 | * it. | |
1939 | */ | |
05394f39 | 1940 | if (obj->active) { |
b93f9cf1 BW |
1941 | ret = i915_wait_request(obj->ring, obj->last_rendering_seqno, |
1942 | true); | |
2cf34d7b | 1943 | if (ret) |
673a394b EA |
1944 | return ret; |
1945 | } | |
1946 | ||
1947 | return 0; | |
1948 | } | |
1949 | ||
b5ffc9bc CW |
1950 | static void i915_gem_object_finish_gtt(struct drm_i915_gem_object *obj) |
1951 | { | |
1952 | u32 old_write_domain, old_read_domains; | |
1953 | ||
b5ffc9bc CW |
1954 | /* Act a barrier for all accesses through the GTT */ |
1955 | mb(); | |
1956 | ||
1957 | /* Force a pagefault for domain tracking on next user access */ | |
1958 | i915_gem_release_mmap(obj); | |
1959 | ||
b97c3d9c KP |
1960 | if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0) |
1961 | return; | |
1962 | ||
b5ffc9bc CW |
1963 | old_read_domains = obj->base.read_domains; |
1964 | old_write_domain = obj->base.write_domain; | |
1965 | ||
1966 | obj->base.read_domains &= ~I915_GEM_DOMAIN_GTT; | |
1967 | obj->base.write_domain &= ~I915_GEM_DOMAIN_GTT; | |
1968 | ||
1969 | trace_i915_gem_object_change_domain(obj, | |
1970 | old_read_domains, | |
1971 | old_write_domain); | |
1972 | } | |
1973 | ||
673a394b EA |
1974 | /** |
1975 | * Unbinds an object from the GTT aperture. | |
1976 | */ | |
0f973f27 | 1977 | int |
05394f39 | 1978 | i915_gem_object_unbind(struct drm_i915_gem_object *obj) |
673a394b | 1979 | { |
7bddb01f | 1980 | drm_i915_private_t *dev_priv = obj->base.dev->dev_private; |
673a394b EA |
1981 | int ret = 0; |
1982 | ||
05394f39 | 1983 | if (obj->gtt_space == NULL) |
673a394b EA |
1984 | return 0; |
1985 | ||
05394f39 | 1986 | if (obj->pin_count != 0) { |
673a394b EA |
1987 | DRM_ERROR("Attempting to unbind pinned buffer\n"); |
1988 | return -EINVAL; | |
1989 | } | |
1990 | ||
a8198eea CW |
1991 | ret = i915_gem_object_finish_gpu(obj); |
1992 | if (ret == -ERESTARTSYS) | |
1993 | return ret; | |
1994 | /* Continue on if we fail due to EIO, the GPU is hung so we | |
1995 | * should be safe and we need to cleanup or else we might | |
1996 | * cause memory corruption through use-after-free. | |
1997 | */ | |
1998 | ||
b5ffc9bc | 1999 | i915_gem_object_finish_gtt(obj); |
5323fd04 | 2000 | |
673a394b EA |
2001 | /* Move the object to the CPU domain to ensure that |
2002 | * any possible CPU writes while it's not in the GTT | |
a8198eea | 2003 | * are flushed when we go to remap it. |
673a394b | 2004 | */ |
a8198eea CW |
2005 | if (ret == 0) |
2006 | ret = i915_gem_object_set_to_cpu_domain(obj, 1); | |
8dc1775d | 2007 | if (ret == -ERESTARTSYS) |
673a394b | 2008 | return ret; |
812ed492 | 2009 | if (ret) { |
a8198eea CW |
2010 | /* In the event of a disaster, abandon all caches and |
2011 | * hope for the best. | |
2012 | */ | |
812ed492 | 2013 | i915_gem_clflush_object(obj); |
05394f39 | 2014 | obj->base.read_domains = obj->base.write_domain = I915_GEM_DOMAIN_CPU; |
812ed492 | 2015 | } |
673a394b | 2016 | |
96b47b65 | 2017 | /* release the fence reg _after_ flushing */ |
d9e86c0e CW |
2018 | ret = i915_gem_object_put_fence(obj); |
2019 | if (ret == -ERESTARTSYS) | |
2020 | return ret; | |
96b47b65 | 2021 | |
db53a302 CW |
2022 | trace_i915_gem_object_unbind(obj); |
2023 | ||
74898d7e DV |
2024 | if (obj->has_global_gtt_mapping) |
2025 | i915_gem_gtt_unbind_object(obj); | |
7bddb01f DV |
2026 | if (obj->has_aliasing_ppgtt_mapping) { |
2027 | i915_ppgtt_unbind_object(dev_priv->mm.aliasing_ppgtt, obj); | |
2028 | obj->has_aliasing_ppgtt_mapping = 0; | |
2029 | } | |
74163907 | 2030 | i915_gem_gtt_finish_object(obj); |
7bddb01f | 2031 | |
e5281ccd | 2032 | i915_gem_object_put_pages_gtt(obj); |
673a394b | 2033 | |
6299f992 | 2034 | list_del_init(&obj->gtt_list); |
05394f39 | 2035 | list_del_init(&obj->mm_list); |
75e9e915 | 2036 | /* Avoid an unnecessary call to unbind on rebind. */ |
05394f39 | 2037 | obj->map_and_fenceable = true; |
673a394b | 2038 | |
05394f39 CW |
2039 | drm_mm_put_block(obj->gtt_space); |
2040 | obj->gtt_space = NULL; | |
2041 | obj->gtt_offset = 0; | |
673a394b | 2042 | |
05394f39 | 2043 | if (i915_gem_object_is_purgeable(obj)) |
963b4836 CW |
2044 | i915_gem_object_truncate(obj); |
2045 | ||
8dc1775d | 2046 | return ret; |
673a394b EA |
2047 | } |
2048 | ||
88241785 | 2049 | int |
db53a302 | 2050 | i915_gem_flush_ring(struct intel_ring_buffer *ring, |
54cf91dc CW |
2051 | uint32_t invalidate_domains, |
2052 | uint32_t flush_domains) | |
2053 | { | |
88241785 CW |
2054 | int ret; |
2055 | ||
36d527de CW |
2056 | if (((invalidate_domains | flush_domains) & I915_GEM_GPU_DOMAINS) == 0) |
2057 | return 0; | |
2058 | ||
db53a302 CW |
2059 | trace_i915_gem_ring_flush(ring, invalidate_domains, flush_domains); |
2060 | ||
88241785 CW |
2061 | ret = ring->flush(ring, invalidate_domains, flush_domains); |
2062 | if (ret) | |
2063 | return ret; | |
2064 | ||
36d527de CW |
2065 | if (flush_domains & I915_GEM_GPU_DOMAINS) |
2066 | i915_gem_process_flushing_list(ring, flush_domains); | |
2067 | ||
88241785 | 2068 | return 0; |
54cf91dc CW |
2069 | } |
2070 | ||
b93f9cf1 | 2071 | static int i915_ring_idle(struct intel_ring_buffer *ring, bool do_retire) |
a56ba56c | 2072 | { |
88241785 CW |
2073 | int ret; |
2074 | ||
395b70be | 2075 | if (list_empty(&ring->gpu_write_list) && list_empty(&ring->active_list)) |
64193406 CW |
2076 | return 0; |
2077 | ||
88241785 | 2078 | if (!list_empty(&ring->gpu_write_list)) { |
db53a302 | 2079 | ret = i915_gem_flush_ring(ring, |
0ac74c6b | 2080 | I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS); |
88241785 CW |
2081 | if (ret) |
2082 | return ret; | |
2083 | } | |
2084 | ||
b93f9cf1 BW |
2085 | return i915_wait_request(ring, i915_gem_next_request_seqno(ring), |
2086 | do_retire); | |
a56ba56c CW |
2087 | } |
2088 | ||
b93f9cf1 | 2089 | int i915_gpu_idle(struct drm_device *dev, bool do_retire) |
4df2faf4 DV |
2090 | { |
2091 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1ec14ad3 | 2092 | int ret, i; |
4df2faf4 | 2093 | |
4df2faf4 | 2094 | /* Flush everything onto the inactive list. */ |
1ec14ad3 | 2095 | for (i = 0; i < I915_NUM_RINGS; i++) { |
b93f9cf1 | 2096 | ret = i915_ring_idle(&dev_priv->ring[i], do_retire); |
1ec14ad3 CW |
2097 | if (ret) |
2098 | return ret; | |
2099 | } | |
4df2faf4 | 2100 | |
8a1a49f9 | 2101 | return 0; |
4df2faf4 DV |
2102 | } |
2103 | ||
c6642782 DV |
2104 | static int sandybridge_write_fence_reg(struct drm_i915_gem_object *obj, |
2105 | struct intel_ring_buffer *pipelined) | |
4e901fdc | 2106 | { |
05394f39 | 2107 | struct drm_device *dev = obj->base.dev; |
4e901fdc | 2108 | drm_i915_private_t *dev_priv = dev->dev_private; |
05394f39 CW |
2109 | u32 size = obj->gtt_space->size; |
2110 | int regnum = obj->fence_reg; | |
4e901fdc EA |
2111 | uint64_t val; |
2112 | ||
05394f39 | 2113 | val = (uint64_t)((obj->gtt_offset + size - 4096) & |
c6642782 | 2114 | 0xfffff000) << 32; |
05394f39 CW |
2115 | val |= obj->gtt_offset & 0xfffff000; |
2116 | val |= (uint64_t)((obj->stride / 128) - 1) << | |
4e901fdc EA |
2117 | SANDYBRIDGE_FENCE_PITCH_SHIFT; |
2118 | ||
05394f39 | 2119 | if (obj->tiling_mode == I915_TILING_Y) |
4e901fdc EA |
2120 | val |= 1 << I965_FENCE_TILING_Y_SHIFT; |
2121 | val |= I965_FENCE_REG_VALID; | |
2122 | ||
c6642782 DV |
2123 | if (pipelined) { |
2124 | int ret = intel_ring_begin(pipelined, 6); | |
2125 | if (ret) | |
2126 | return ret; | |
2127 | ||
2128 | intel_ring_emit(pipelined, MI_NOOP); | |
2129 | intel_ring_emit(pipelined, MI_LOAD_REGISTER_IMM(2)); | |
2130 | intel_ring_emit(pipelined, FENCE_REG_SANDYBRIDGE_0 + regnum*8); | |
2131 | intel_ring_emit(pipelined, (u32)val); | |
2132 | intel_ring_emit(pipelined, FENCE_REG_SANDYBRIDGE_0 + regnum*8 + 4); | |
2133 | intel_ring_emit(pipelined, (u32)(val >> 32)); | |
2134 | intel_ring_advance(pipelined); | |
2135 | } else | |
2136 | I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + regnum * 8, val); | |
2137 | ||
2138 | return 0; | |
4e901fdc EA |
2139 | } |
2140 | ||
c6642782 DV |
2141 | static int i965_write_fence_reg(struct drm_i915_gem_object *obj, |
2142 | struct intel_ring_buffer *pipelined) | |
de151cf6 | 2143 | { |
05394f39 | 2144 | struct drm_device *dev = obj->base.dev; |
de151cf6 | 2145 | drm_i915_private_t *dev_priv = dev->dev_private; |
05394f39 CW |
2146 | u32 size = obj->gtt_space->size; |
2147 | int regnum = obj->fence_reg; | |
de151cf6 JB |
2148 | uint64_t val; |
2149 | ||
05394f39 | 2150 | val = (uint64_t)((obj->gtt_offset + size - 4096) & |
de151cf6 | 2151 | 0xfffff000) << 32; |
05394f39 CW |
2152 | val |= obj->gtt_offset & 0xfffff000; |
2153 | val |= ((obj->stride / 128) - 1) << I965_FENCE_PITCH_SHIFT; | |
2154 | if (obj->tiling_mode == I915_TILING_Y) | |
de151cf6 JB |
2155 | val |= 1 << I965_FENCE_TILING_Y_SHIFT; |
2156 | val |= I965_FENCE_REG_VALID; | |
2157 | ||
c6642782 DV |
2158 | if (pipelined) { |
2159 | int ret = intel_ring_begin(pipelined, 6); | |
2160 | if (ret) | |
2161 | return ret; | |
2162 | ||
2163 | intel_ring_emit(pipelined, MI_NOOP); | |
2164 | intel_ring_emit(pipelined, MI_LOAD_REGISTER_IMM(2)); | |
2165 | intel_ring_emit(pipelined, FENCE_REG_965_0 + regnum*8); | |
2166 | intel_ring_emit(pipelined, (u32)val); | |
2167 | intel_ring_emit(pipelined, FENCE_REG_965_0 + regnum*8 + 4); | |
2168 | intel_ring_emit(pipelined, (u32)(val >> 32)); | |
2169 | intel_ring_advance(pipelined); | |
2170 | } else | |
2171 | I915_WRITE64(FENCE_REG_965_0 + regnum * 8, val); | |
2172 | ||
2173 | return 0; | |
de151cf6 JB |
2174 | } |
2175 | ||
c6642782 DV |
2176 | static int i915_write_fence_reg(struct drm_i915_gem_object *obj, |
2177 | struct intel_ring_buffer *pipelined) | |
de151cf6 | 2178 | { |
05394f39 | 2179 | struct drm_device *dev = obj->base.dev; |
de151cf6 | 2180 | drm_i915_private_t *dev_priv = dev->dev_private; |
05394f39 | 2181 | u32 size = obj->gtt_space->size; |
c6642782 | 2182 | u32 fence_reg, val, pitch_val; |
0f973f27 | 2183 | int tile_width; |
de151cf6 | 2184 | |
c6642782 DV |
2185 | if (WARN((obj->gtt_offset & ~I915_FENCE_START_MASK) || |
2186 | (size & -size) != size || | |
2187 | (obj->gtt_offset & (size - 1)), | |
2188 | "object 0x%08x [fenceable? %d] not 1M or pot-size (0x%08x) aligned\n", | |
2189 | obj->gtt_offset, obj->map_and_fenceable, size)) | |
2190 | return -EINVAL; | |
de151cf6 | 2191 | |
c6642782 | 2192 | if (obj->tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev)) |
0f973f27 | 2193 | tile_width = 128; |
de151cf6 | 2194 | else |
0f973f27 JB |
2195 | tile_width = 512; |
2196 | ||
2197 | /* Note: pitch better be a power of two tile widths */ | |
05394f39 | 2198 | pitch_val = obj->stride / tile_width; |
0f973f27 | 2199 | pitch_val = ffs(pitch_val) - 1; |
de151cf6 | 2200 | |
05394f39 CW |
2201 | val = obj->gtt_offset; |
2202 | if (obj->tiling_mode == I915_TILING_Y) | |
de151cf6 | 2203 | val |= 1 << I830_FENCE_TILING_Y_SHIFT; |
a00b10c3 | 2204 | val |= I915_FENCE_SIZE_BITS(size); |
de151cf6 JB |
2205 | val |= pitch_val << I830_FENCE_PITCH_SHIFT; |
2206 | val |= I830_FENCE_REG_VALID; | |
2207 | ||
05394f39 | 2208 | fence_reg = obj->fence_reg; |
a00b10c3 CW |
2209 | if (fence_reg < 8) |
2210 | fence_reg = FENCE_REG_830_0 + fence_reg * 4; | |
dc529a4f | 2211 | else |
a00b10c3 | 2212 | fence_reg = FENCE_REG_945_8 + (fence_reg - 8) * 4; |
c6642782 DV |
2213 | |
2214 | if (pipelined) { | |
2215 | int ret = intel_ring_begin(pipelined, 4); | |
2216 | if (ret) | |
2217 | return ret; | |
2218 | ||
2219 | intel_ring_emit(pipelined, MI_NOOP); | |
2220 | intel_ring_emit(pipelined, MI_LOAD_REGISTER_IMM(1)); | |
2221 | intel_ring_emit(pipelined, fence_reg); | |
2222 | intel_ring_emit(pipelined, val); | |
2223 | intel_ring_advance(pipelined); | |
2224 | } else | |
2225 | I915_WRITE(fence_reg, val); | |
2226 | ||
2227 | return 0; | |
de151cf6 JB |
2228 | } |
2229 | ||
c6642782 DV |
2230 | static int i830_write_fence_reg(struct drm_i915_gem_object *obj, |
2231 | struct intel_ring_buffer *pipelined) | |
de151cf6 | 2232 | { |
05394f39 | 2233 | struct drm_device *dev = obj->base.dev; |
de151cf6 | 2234 | drm_i915_private_t *dev_priv = dev->dev_private; |
05394f39 CW |
2235 | u32 size = obj->gtt_space->size; |
2236 | int regnum = obj->fence_reg; | |
de151cf6 JB |
2237 | uint32_t val; |
2238 | uint32_t pitch_val; | |
2239 | ||
c6642782 DV |
2240 | if (WARN((obj->gtt_offset & ~I830_FENCE_START_MASK) || |
2241 | (size & -size) != size || | |
2242 | (obj->gtt_offset & (size - 1)), | |
2243 | "object 0x%08x not 512K or pot-size 0x%08x aligned\n", | |
2244 | obj->gtt_offset, size)) | |
2245 | return -EINVAL; | |
de151cf6 | 2246 | |
05394f39 | 2247 | pitch_val = obj->stride / 128; |
e76a16de | 2248 | pitch_val = ffs(pitch_val) - 1; |
e76a16de | 2249 | |
05394f39 CW |
2250 | val = obj->gtt_offset; |
2251 | if (obj->tiling_mode == I915_TILING_Y) | |
de151cf6 | 2252 | val |= 1 << I830_FENCE_TILING_Y_SHIFT; |
c6642782 | 2253 | val |= I830_FENCE_SIZE_BITS(size); |
de151cf6 JB |
2254 | val |= pitch_val << I830_FENCE_PITCH_SHIFT; |
2255 | val |= I830_FENCE_REG_VALID; | |
2256 | ||
c6642782 DV |
2257 | if (pipelined) { |
2258 | int ret = intel_ring_begin(pipelined, 4); | |
2259 | if (ret) | |
2260 | return ret; | |
2261 | ||
2262 | intel_ring_emit(pipelined, MI_NOOP); | |
2263 | intel_ring_emit(pipelined, MI_LOAD_REGISTER_IMM(1)); | |
2264 | intel_ring_emit(pipelined, FENCE_REG_830_0 + regnum*4); | |
2265 | intel_ring_emit(pipelined, val); | |
2266 | intel_ring_advance(pipelined); | |
2267 | } else | |
2268 | I915_WRITE(FENCE_REG_830_0 + regnum * 4, val); | |
2269 | ||
2270 | return 0; | |
de151cf6 JB |
2271 | } |
2272 | ||
d9e86c0e CW |
2273 | static bool ring_passed_seqno(struct intel_ring_buffer *ring, u32 seqno) |
2274 | { | |
2275 | return i915_seqno_passed(ring->get_seqno(ring), seqno); | |
2276 | } | |
2277 | ||
2278 | static int | |
2279 | i915_gem_object_flush_fence(struct drm_i915_gem_object *obj, | |
ce453d81 | 2280 | struct intel_ring_buffer *pipelined) |
d9e86c0e CW |
2281 | { |
2282 | int ret; | |
2283 | ||
2284 | if (obj->fenced_gpu_access) { | |
88241785 | 2285 | if (obj->base.write_domain & I915_GEM_GPU_DOMAINS) { |
db53a302 | 2286 | ret = i915_gem_flush_ring(obj->last_fenced_ring, |
88241785 CW |
2287 | 0, obj->base.write_domain); |
2288 | if (ret) | |
2289 | return ret; | |
2290 | } | |
d9e86c0e CW |
2291 | |
2292 | obj->fenced_gpu_access = false; | |
2293 | } | |
2294 | ||
2295 | if (obj->last_fenced_seqno && pipelined != obj->last_fenced_ring) { | |
2296 | if (!ring_passed_seqno(obj->last_fenced_ring, | |
2297 | obj->last_fenced_seqno)) { | |
db53a302 | 2298 | ret = i915_wait_request(obj->last_fenced_ring, |
b93f9cf1 BW |
2299 | obj->last_fenced_seqno, |
2300 | true); | |
d9e86c0e CW |
2301 | if (ret) |
2302 | return ret; | |
2303 | } | |
2304 | ||
2305 | obj->last_fenced_seqno = 0; | |
2306 | obj->last_fenced_ring = NULL; | |
2307 | } | |
2308 | ||
63256ec5 CW |
2309 | /* Ensure that all CPU reads are completed before installing a fence |
2310 | * and all writes before removing the fence. | |
2311 | */ | |
2312 | if (obj->base.read_domains & I915_GEM_DOMAIN_GTT) | |
2313 | mb(); | |
2314 | ||
d9e86c0e CW |
2315 | return 0; |
2316 | } | |
2317 | ||
2318 | int | |
2319 | i915_gem_object_put_fence(struct drm_i915_gem_object *obj) | |
2320 | { | |
2321 | int ret; | |
2322 | ||
2323 | if (obj->tiling_mode) | |
2324 | i915_gem_release_mmap(obj); | |
2325 | ||
ce453d81 | 2326 | ret = i915_gem_object_flush_fence(obj, NULL); |
d9e86c0e CW |
2327 | if (ret) |
2328 | return ret; | |
2329 | ||
2330 | if (obj->fence_reg != I915_FENCE_REG_NONE) { | |
2331 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; | |
1690e1eb CW |
2332 | |
2333 | WARN_ON(dev_priv->fence_regs[obj->fence_reg].pin_count); | |
d9e86c0e CW |
2334 | i915_gem_clear_fence_reg(obj->base.dev, |
2335 | &dev_priv->fence_regs[obj->fence_reg]); | |
2336 | ||
2337 | obj->fence_reg = I915_FENCE_REG_NONE; | |
2338 | } | |
2339 | ||
2340 | return 0; | |
2341 | } | |
2342 | ||
2343 | static struct drm_i915_fence_reg * | |
2344 | i915_find_fence_reg(struct drm_device *dev, | |
2345 | struct intel_ring_buffer *pipelined) | |
ae3db24a | 2346 | { |
ae3db24a | 2347 | struct drm_i915_private *dev_priv = dev->dev_private; |
d9e86c0e CW |
2348 | struct drm_i915_fence_reg *reg, *first, *avail; |
2349 | int i; | |
ae3db24a DV |
2350 | |
2351 | /* First try to find a free reg */ | |
d9e86c0e | 2352 | avail = NULL; |
ae3db24a DV |
2353 | for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) { |
2354 | reg = &dev_priv->fence_regs[i]; | |
2355 | if (!reg->obj) | |
d9e86c0e | 2356 | return reg; |
ae3db24a | 2357 | |
1690e1eb | 2358 | if (!reg->pin_count) |
d9e86c0e | 2359 | avail = reg; |
ae3db24a DV |
2360 | } |
2361 | ||
d9e86c0e CW |
2362 | if (avail == NULL) |
2363 | return NULL; | |
ae3db24a DV |
2364 | |
2365 | /* None available, try to steal one or wait for a user to finish */ | |
d9e86c0e CW |
2366 | avail = first = NULL; |
2367 | list_for_each_entry(reg, &dev_priv->mm.fence_list, lru_list) { | |
1690e1eb | 2368 | if (reg->pin_count) |
ae3db24a DV |
2369 | continue; |
2370 | ||
d9e86c0e CW |
2371 | if (first == NULL) |
2372 | first = reg; | |
2373 | ||
2374 | if (!pipelined || | |
2375 | !reg->obj->last_fenced_ring || | |
2376 | reg->obj->last_fenced_ring == pipelined) { | |
2377 | avail = reg; | |
2378 | break; | |
2379 | } | |
ae3db24a DV |
2380 | } |
2381 | ||
d9e86c0e CW |
2382 | if (avail == NULL) |
2383 | avail = first; | |
ae3db24a | 2384 | |
a00b10c3 | 2385 | return avail; |
ae3db24a DV |
2386 | } |
2387 | ||
de151cf6 | 2388 | /** |
d9e86c0e | 2389 | * i915_gem_object_get_fence - set up a fence reg for an object |
de151cf6 | 2390 | * @obj: object to map through a fence reg |
d9e86c0e CW |
2391 | * @pipelined: ring on which to queue the change, or NULL for CPU access |
2392 | * @interruptible: must we wait uninterruptibly for the register to retire? | |
de151cf6 JB |
2393 | * |
2394 | * When mapping objects through the GTT, userspace wants to be able to write | |
2395 | * to them without having to worry about swizzling if the object is tiled. | |
2396 | * | |
2397 | * This function walks the fence regs looking for a free one for @obj, | |
2398 | * stealing one if it can't find any. | |
2399 | * | |
2400 | * It then sets up the reg based on the object's properties: address, pitch | |
2401 | * and tiling format. | |
2402 | */ | |
8c4b8c3f | 2403 | int |
d9e86c0e | 2404 | i915_gem_object_get_fence(struct drm_i915_gem_object *obj, |
ce453d81 | 2405 | struct intel_ring_buffer *pipelined) |
de151cf6 | 2406 | { |
05394f39 | 2407 | struct drm_device *dev = obj->base.dev; |
79e53945 | 2408 | struct drm_i915_private *dev_priv = dev->dev_private; |
d9e86c0e | 2409 | struct drm_i915_fence_reg *reg; |
ae3db24a | 2410 | int ret; |
de151cf6 | 2411 | |
6bda10d1 CW |
2412 | /* XXX disable pipelining. There are bugs. Shocking. */ |
2413 | pipelined = NULL; | |
2414 | ||
d9e86c0e | 2415 | /* Just update our place in the LRU if our fence is getting reused. */ |
05394f39 CW |
2416 | if (obj->fence_reg != I915_FENCE_REG_NONE) { |
2417 | reg = &dev_priv->fence_regs[obj->fence_reg]; | |
007cc8ac | 2418 | list_move_tail(®->lru_list, &dev_priv->mm.fence_list); |
d9e86c0e | 2419 | |
29c5a587 CW |
2420 | if (obj->tiling_changed) { |
2421 | ret = i915_gem_object_flush_fence(obj, pipelined); | |
2422 | if (ret) | |
2423 | return ret; | |
2424 | ||
2425 | if (!obj->fenced_gpu_access && !obj->last_fenced_seqno) | |
2426 | pipelined = NULL; | |
2427 | ||
2428 | if (pipelined) { | |
2429 | reg->setup_seqno = | |
2430 | i915_gem_next_request_seqno(pipelined); | |
2431 | obj->last_fenced_seqno = reg->setup_seqno; | |
2432 | obj->last_fenced_ring = pipelined; | |
2433 | } | |
2434 | ||
2435 | goto update; | |
2436 | } | |
d9e86c0e CW |
2437 | |
2438 | if (!pipelined) { | |
2439 | if (reg->setup_seqno) { | |
2440 | if (!ring_passed_seqno(obj->last_fenced_ring, | |
2441 | reg->setup_seqno)) { | |
db53a302 | 2442 | ret = i915_wait_request(obj->last_fenced_ring, |
b93f9cf1 BW |
2443 | reg->setup_seqno, |
2444 | true); | |
d9e86c0e CW |
2445 | if (ret) |
2446 | return ret; | |
2447 | } | |
2448 | ||
2449 | reg->setup_seqno = 0; | |
2450 | } | |
2451 | } else if (obj->last_fenced_ring && | |
2452 | obj->last_fenced_ring != pipelined) { | |
ce453d81 | 2453 | ret = i915_gem_object_flush_fence(obj, pipelined); |
d9e86c0e CW |
2454 | if (ret) |
2455 | return ret; | |
d9e86c0e CW |
2456 | } |
2457 | ||
a09ba7fa EA |
2458 | return 0; |
2459 | } | |
2460 | ||
d9e86c0e CW |
2461 | reg = i915_find_fence_reg(dev, pipelined); |
2462 | if (reg == NULL) | |
39965b37 | 2463 | return -EDEADLK; |
de151cf6 | 2464 | |
ce453d81 | 2465 | ret = i915_gem_object_flush_fence(obj, pipelined); |
d9e86c0e | 2466 | if (ret) |
ae3db24a | 2467 | return ret; |
de151cf6 | 2468 | |
d9e86c0e CW |
2469 | if (reg->obj) { |
2470 | struct drm_i915_gem_object *old = reg->obj; | |
2471 | ||
2472 | drm_gem_object_reference(&old->base); | |
2473 | ||
2474 | if (old->tiling_mode) | |
2475 | i915_gem_release_mmap(old); | |
2476 | ||
ce453d81 | 2477 | ret = i915_gem_object_flush_fence(old, pipelined); |
d9e86c0e CW |
2478 | if (ret) { |
2479 | drm_gem_object_unreference(&old->base); | |
2480 | return ret; | |
2481 | } | |
2482 | ||
2483 | if (old->last_fenced_seqno == 0 && obj->last_fenced_seqno == 0) | |
2484 | pipelined = NULL; | |
2485 | ||
2486 | old->fence_reg = I915_FENCE_REG_NONE; | |
2487 | old->last_fenced_ring = pipelined; | |
2488 | old->last_fenced_seqno = | |
db53a302 | 2489 | pipelined ? i915_gem_next_request_seqno(pipelined) : 0; |
d9e86c0e CW |
2490 | |
2491 | drm_gem_object_unreference(&old->base); | |
2492 | } else if (obj->last_fenced_seqno == 0) | |
2493 | pipelined = NULL; | |
a09ba7fa | 2494 | |
de151cf6 | 2495 | reg->obj = obj; |
d9e86c0e CW |
2496 | list_move_tail(®->lru_list, &dev_priv->mm.fence_list); |
2497 | obj->fence_reg = reg - dev_priv->fence_regs; | |
2498 | obj->last_fenced_ring = pipelined; | |
de151cf6 | 2499 | |
d9e86c0e | 2500 | reg->setup_seqno = |
db53a302 | 2501 | pipelined ? i915_gem_next_request_seqno(pipelined) : 0; |
d9e86c0e CW |
2502 | obj->last_fenced_seqno = reg->setup_seqno; |
2503 | ||
2504 | update: | |
2505 | obj->tiling_changed = false; | |
e259befd | 2506 | switch (INTEL_INFO(dev)->gen) { |
25aebfc3 | 2507 | case 7: |
e259befd | 2508 | case 6: |
c6642782 | 2509 | ret = sandybridge_write_fence_reg(obj, pipelined); |
e259befd CW |
2510 | break; |
2511 | case 5: | |
2512 | case 4: | |
c6642782 | 2513 | ret = i965_write_fence_reg(obj, pipelined); |
e259befd CW |
2514 | break; |
2515 | case 3: | |
c6642782 | 2516 | ret = i915_write_fence_reg(obj, pipelined); |
e259befd CW |
2517 | break; |
2518 | case 2: | |
c6642782 | 2519 | ret = i830_write_fence_reg(obj, pipelined); |
e259befd CW |
2520 | break; |
2521 | } | |
d9ddcb96 | 2522 | |
c6642782 | 2523 | return ret; |
de151cf6 JB |
2524 | } |
2525 | ||
2526 | /** | |
2527 | * i915_gem_clear_fence_reg - clear out fence register info | |
2528 | * @obj: object to clear | |
2529 | * | |
2530 | * Zeroes out the fence register itself and clears out the associated | |
05394f39 | 2531 | * data structures in dev_priv and obj. |
de151cf6 JB |
2532 | */ |
2533 | static void | |
d9e86c0e CW |
2534 | i915_gem_clear_fence_reg(struct drm_device *dev, |
2535 | struct drm_i915_fence_reg *reg) | |
de151cf6 | 2536 | { |
79e53945 | 2537 | drm_i915_private_t *dev_priv = dev->dev_private; |
d9e86c0e | 2538 | uint32_t fence_reg = reg - dev_priv->fence_regs; |
de151cf6 | 2539 | |
e259befd | 2540 | switch (INTEL_INFO(dev)->gen) { |
25aebfc3 | 2541 | case 7: |
e259befd | 2542 | case 6: |
d9e86c0e | 2543 | I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + fence_reg*8, 0); |
e259befd CW |
2544 | break; |
2545 | case 5: | |
2546 | case 4: | |
d9e86c0e | 2547 | I915_WRITE64(FENCE_REG_965_0 + fence_reg*8, 0); |
e259befd CW |
2548 | break; |
2549 | case 3: | |
d9e86c0e CW |
2550 | if (fence_reg >= 8) |
2551 | fence_reg = FENCE_REG_945_8 + (fence_reg - 8) * 4; | |
dc529a4f | 2552 | else |
e259befd | 2553 | case 2: |
d9e86c0e | 2554 | fence_reg = FENCE_REG_830_0 + fence_reg * 4; |
dc529a4f EA |
2555 | |
2556 | I915_WRITE(fence_reg, 0); | |
e259befd | 2557 | break; |
dc529a4f | 2558 | } |
de151cf6 | 2559 | |
007cc8ac | 2560 | list_del_init(®->lru_list); |
d9e86c0e CW |
2561 | reg->obj = NULL; |
2562 | reg->setup_seqno = 0; | |
1690e1eb | 2563 | reg->pin_count = 0; |
52dc7d32 CW |
2564 | } |
2565 | ||
673a394b EA |
2566 | /** |
2567 | * Finds free space in the GTT aperture and binds the object there. | |
2568 | */ | |
2569 | static int | |
05394f39 | 2570 | i915_gem_object_bind_to_gtt(struct drm_i915_gem_object *obj, |
920afa77 | 2571 | unsigned alignment, |
75e9e915 | 2572 | bool map_and_fenceable) |
673a394b | 2573 | { |
05394f39 | 2574 | struct drm_device *dev = obj->base.dev; |
673a394b | 2575 | drm_i915_private_t *dev_priv = dev->dev_private; |
673a394b | 2576 | struct drm_mm_node *free_space; |
a00b10c3 | 2577 | gfp_t gfpmask = __GFP_NORETRY | __GFP_NOWARN; |
5e783301 | 2578 | u32 size, fence_size, fence_alignment, unfenced_alignment; |
75e9e915 | 2579 | bool mappable, fenceable; |
07f73f69 | 2580 | int ret; |
673a394b | 2581 | |
05394f39 | 2582 | if (obj->madv != I915_MADV_WILLNEED) { |
3ef94daa CW |
2583 | DRM_ERROR("Attempting to bind a purgeable object\n"); |
2584 | return -EINVAL; | |
2585 | } | |
2586 | ||
e28f8711 CW |
2587 | fence_size = i915_gem_get_gtt_size(dev, |
2588 | obj->base.size, | |
2589 | obj->tiling_mode); | |
2590 | fence_alignment = i915_gem_get_gtt_alignment(dev, | |
2591 | obj->base.size, | |
2592 | obj->tiling_mode); | |
2593 | unfenced_alignment = | |
2594 | i915_gem_get_unfenced_gtt_alignment(dev, | |
2595 | obj->base.size, | |
2596 | obj->tiling_mode); | |
a00b10c3 | 2597 | |
673a394b | 2598 | if (alignment == 0) |
5e783301 DV |
2599 | alignment = map_and_fenceable ? fence_alignment : |
2600 | unfenced_alignment; | |
75e9e915 | 2601 | if (map_and_fenceable && alignment & (fence_alignment - 1)) { |
673a394b EA |
2602 | DRM_ERROR("Invalid object alignment requested %u\n", alignment); |
2603 | return -EINVAL; | |
2604 | } | |
2605 | ||
05394f39 | 2606 | size = map_and_fenceable ? fence_size : obj->base.size; |
a00b10c3 | 2607 | |
654fc607 CW |
2608 | /* If the object is bigger than the entire aperture, reject it early |
2609 | * before evicting everything in a vain attempt to find space. | |
2610 | */ | |
05394f39 | 2611 | if (obj->base.size > |
75e9e915 | 2612 | (map_and_fenceable ? dev_priv->mm.gtt_mappable_end : dev_priv->mm.gtt_total)) { |
654fc607 CW |
2613 | DRM_ERROR("Attempting to bind an object larger than the aperture\n"); |
2614 | return -E2BIG; | |
2615 | } | |
2616 | ||
673a394b | 2617 | search_free: |
75e9e915 | 2618 | if (map_and_fenceable) |
920afa77 DV |
2619 | free_space = |
2620 | drm_mm_search_free_in_range(&dev_priv->mm.gtt_space, | |
a00b10c3 | 2621 | size, alignment, 0, |
920afa77 DV |
2622 | dev_priv->mm.gtt_mappable_end, |
2623 | 0); | |
2624 | else | |
2625 | free_space = drm_mm_search_free(&dev_priv->mm.gtt_space, | |
a00b10c3 | 2626 | size, alignment, 0); |
920afa77 DV |
2627 | |
2628 | if (free_space != NULL) { | |
75e9e915 | 2629 | if (map_and_fenceable) |
05394f39 | 2630 | obj->gtt_space = |
920afa77 | 2631 | drm_mm_get_block_range_generic(free_space, |
a00b10c3 | 2632 | size, alignment, 0, |
920afa77 DV |
2633 | dev_priv->mm.gtt_mappable_end, |
2634 | 0); | |
2635 | else | |
05394f39 | 2636 | obj->gtt_space = |
a00b10c3 | 2637 | drm_mm_get_block(free_space, size, alignment); |
920afa77 | 2638 | } |
05394f39 | 2639 | if (obj->gtt_space == NULL) { |
673a394b EA |
2640 | /* If the gtt is empty and we're still having trouble |
2641 | * fitting our object in, we're out of memory. | |
2642 | */ | |
75e9e915 DV |
2643 | ret = i915_gem_evict_something(dev, size, alignment, |
2644 | map_and_fenceable); | |
9731129c | 2645 | if (ret) |
673a394b | 2646 | return ret; |
9731129c | 2647 | |
673a394b EA |
2648 | goto search_free; |
2649 | } | |
2650 | ||
e5281ccd | 2651 | ret = i915_gem_object_get_pages_gtt(obj, gfpmask); |
673a394b | 2652 | if (ret) { |
05394f39 CW |
2653 | drm_mm_put_block(obj->gtt_space); |
2654 | obj->gtt_space = NULL; | |
07f73f69 CW |
2655 | |
2656 | if (ret == -ENOMEM) { | |
809b6334 CW |
2657 | /* first try to reclaim some memory by clearing the GTT */ |
2658 | ret = i915_gem_evict_everything(dev, false); | |
07f73f69 | 2659 | if (ret) { |
07f73f69 | 2660 | /* now try to shrink everyone else */ |
4bdadb97 CW |
2661 | if (gfpmask) { |
2662 | gfpmask = 0; | |
2663 | goto search_free; | |
07f73f69 CW |
2664 | } |
2665 | ||
809b6334 | 2666 | return -ENOMEM; |
07f73f69 CW |
2667 | } |
2668 | ||
2669 | goto search_free; | |
2670 | } | |
2671 | ||
673a394b EA |
2672 | return ret; |
2673 | } | |
2674 | ||
74163907 | 2675 | ret = i915_gem_gtt_prepare_object(obj); |
7c2e6fdf | 2676 | if (ret) { |
e5281ccd | 2677 | i915_gem_object_put_pages_gtt(obj); |
05394f39 CW |
2678 | drm_mm_put_block(obj->gtt_space); |
2679 | obj->gtt_space = NULL; | |
07f73f69 | 2680 | |
809b6334 | 2681 | if (i915_gem_evict_everything(dev, false)) |
07f73f69 | 2682 | return ret; |
07f73f69 CW |
2683 | |
2684 | goto search_free; | |
673a394b | 2685 | } |
0ebb9829 DV |
2686 | |
2687 | if (!dev_priv->mm.aliasing_ppgtt) | |
2688 | i915_gem_gtt_bind_object(obj, obj->cache_level); | |
673a394b | 2689 | |
6299f992 | 2690 | list_add_tail(&obj->gtt_list, &dev_priv->mm.gtt_list); |
05394f39 | 2691 | list_add_tail(&obj->mm_list, &dev_priv->mm.inactive_list); |
bf1a1092 | 2692 | |
673a394b EA |
2693 | /* Assert that the object is not currently in any GPU domain. As it |
2694 | * wasn't in the GTT, there shouldn't be any way it could have been in | |
2695 | * a GPU cache | |
2696 | */ | |
05394f39 CW |
2697 | BUG_ON(obj->base.read_domains & I915_GEM_GPU_DOMAINS); |
2698 | BUG_ON(obj->base.write_domain & I915_GEM_GPU_DOMAINS); | |
673a394b | 2699 | |
6299f992 | 2700 | obj->gtt_offset = obj->gtt_space->start; |
1c5d22f7 | 2701 | |
75e9e915 | 2702 | fenceable = |
05394f39 | 2703 | obj->gtt_space->size == fence_size && |
0206e353 | 2704 | (obj->gtt_space->start & (fence_alignment - 1)) == 0; |
a00b10c3 | 2705 | |
75e9e915 | 2706 | mappable = |
05394f39 | 2707 | obj->gtt_offset + obj->base.size <= dev_priv->mm.gtt_mappable_end; |
a00b10c3 | 2708 | |
05394f39 | 2709 | obj->map_and_fenceable = mappable && fenceable; |
75e9e915 | 2710 | |
db53a302 | 2711 | trace_i915_gem_object_bind(obj, map_and_fenceable); |
673a394b EA |
2712 | return 0; |
2713 | } | |
2714 | ||
2715 | void | |
05394f39 | 2716 | i915_gem_clflush_object(struct drm_i915_gem_object *obj) |
673a394b | 2717 | { |
673a394b EA |
2718 | /* If we don't have a page list set up, then we're not pinned |
2719 | * to GPU, and we can ignore the cache flush because it'll happen | |
2720 | * again at bind time. | |
2721 | */ | |
05394f39 | 2722 | if (obj->pages == NULL) |
673a394b EA |
2723 | return; |
2724 | ||
9c23f7fc CW |
2725 | /* If the GPU is snooping the contents of the CPU cache, |
2726 | * we do not need to manually clear the CPU cache lines. However, | |
2727 | * the caches are only snooped when the render cache is | |
2728 | * flushed/invalidated. As we always have to emit invalidations | |
2729 | * and flushes when moving into and out of the RENDER domain, correct | |
2730 | * snooping behaviour occurs naturally as the result of our domain | |
2731 | * tracking. | |
2732 | */ | |
2733 | if (obj->cache_level != I915_CACHE_NONE) | |
2734 | return; | |
2735 | ||
1c5d22f7 | 2736 | trace_i915_gem_object_clflush(obj); |
cfa16a0d | 2737 | |
05394f39 | 2738 | drm_clflush_pages(obj->pages, obj->base.size / PAGE_SIZE); |
673a394b EA |
2739 | } |
2740 | ||
e47c68e9 | 2741 | /** Flushes any GPU write domain for the object if it's dirty. */ |
88241785 | 2742 | static int |
3619df03 | 2743 | i915_gem_object_flush_gpu_write_domain(struct drm_i915_gem_object *obj) |
e47c68e9 | 2744 | { |
05394f39 | 2745 | if ((obj->base.write_domain & I915_GEM_GPU_DOMAINS) == 0) |
88241785 | 2746 | return 0; |
e47c68e9 EA |
2747 | |
2748 | /* Queue the GPU write cache flushing we need. */ | |
db53a302 | 2749 | return i915_gem_flush_ring(obj->ring, 0, obj->base.write_domain); |
e47c68e9 EA |
2750 | } |
2751 | ||
2752 | /** Flushes the GTT write domain for the object if it's dirty. */ | |
2753 | static void | |
05394f39 | 2754 | i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj) |
e47c68e9 | 2755 | { |
1c5d22f7 CW |
2756 | uint32_t old_write_domain; |
2757 | ||
05394f39 | 2758 | if (obj->base.write_domain != I915_GEM_DOMAIN_GTT) |
e47c68e9 EA |
2759 | return; |
2760 | ||
63256ec5 | 2761 | /* No actual flushing is required for the GTT write domain. Writes |
e47c68e9 EA |
2762 | * to it immediately go to main memory as far as we know, so there's |
2763 | * no chipset flush. It also doesn't land in render cache. | |
63256ec5 CW |
2764 | * |
2765 | * However, we do have to enforce the order so that all writes through | |
2766 | * the GTT land before any writes to the device, such as updates to | |
2767 | * the GATT itself. | |
e47c68e9 | 2768 | */ |
63256ec5 CW |
2769 | wmb(); |
2770 | ||
05394f39 CW |
2771 | old_write_domain = obj->base.write_domain; |
2772 | obj->base.write_domain = 0; | |
1c5d22f7 CW |
2773 | |
2774 | trace_i915_gem_object_change_domain(obj, | |
05394f39 | 2775 | obj->base.read_domains, |
1c5d22f7 | 2776 | old_write_domain); |
e47c68e9 EA |
2777 | } |
2778 | ||
2779 | /** Flushes the CPU write domain for the object if it's dirty. */ | |
2780 | static void | |
05394f39 | 2781 | i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj) |
e47c68e9 | 2782 | { |
1c5d22f7 | 2783 | uint32_t old_write_domain; |
e47c68e9 | 2784 | |
05394f39 | 2785 | if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) |
e47c68e9 EA |
2786 | return; |
2787 | ||
2788 | i915_gem_clflush_object(obj); | |
40ce6575 | 2789 | intel_gtt_chipset_flush(); |
05394f39 CW |
2790 | old_write_domain = obj->base.write_domain; |
2791 | obj->base.write_domain = 0; | |
1c5d22f7 CW |
2792 | |
2793 | trace_i915_gem_object_change_domain(obj, | |
05394f39 | 2794 | obj->base.read_domains, |
1c5d22f7 | 2795 | old_write_domain); |
e47c68e9 EA |
2796 | } |
2797 | ||
2ef7eeaa EA |
2798 | /** |
2799 | * Moves a single object to the GTT read, and possibly write domain. | |
2800 | * | |
2801 | * This function returns when the move is complete, including waiting on | |
2802 | * flushes to occur. | |
2803 | */ | |
79e53945 | 2804 | int |
2021746e | 2805 | i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write) |
2ef7eeaa | 2806 | { |
1c5d22f7 | 2807 | uint32_t old_write_domain, old_read_domains; |
e47c68e9 | 2808 | int ret; |
2ef7eeaa | 2809 | |
02354392 | 2810 | /* Not valid to be called on unbound objects. */ |
05394f39 | 2811 | if (obj->gtt_space == NULL) |
02354392 EA |
2812 | return -EINVAL; |
2813 | ||
8d7e3de1 CW |
2814 | if (obj->base.write_domain == I915_GEM_DOMAIN_GTT) |
2815 | return 0; | |
2816 | ||
88241785 CW |
2817 | ret = i915_gem_object_flush_gpu_write_domain(obj); |
2818 | if (ret) | |
2819 | return ret; | |
2820 | ||
87ca9c8a | 2821 | if (obj->pending_gpu_write || write) { |
ce453d81 | 2822 | ret = i915_gem_object_wait_rendering(obj); |
87ca9c8a CW |
2823 | if (ret) |
2824 | return ret; | |
2825 | } | |
2dafb1e0 | 2826 | |
7213342d | 2827 | i915_gem_object_flush_cpu_write_domain(obj); |
1c5d22f7 | 2828 | |
05394f39 CW |
2829 | old_write_domain = obj->base.write_domain; |
2830 | old_read_domains = obj->base.read_domains; | |
1c5d22f7 | 2831 | |
e47c68e9 EA |
2832 | /* It should now be out of any other write domains, and we can update |
2833 | * the domain values for our changes. | |
2834 | */ | |
05394f39 CW |
2835 | BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) != 0); |
2836 | obj->base.read_domains |= I915_GEM_DOMAIN_GTT; | |
e47c68e9 | 2837 | if (write) { |
05394f39 CW |
2838 | obj->base.read_domains = I915_GEM_DOMAIN_GTT; |
2839 | obj->base.write_domain = I915_GEM_DOMAIN_GTT; | |
2840 | obj->dirty = 1; | |
2ef7eeaa EA |
2841 | } |
2842 | ||
1c5d22f7 CW |
2843 | trace_i915_gem_object_change_domain(obj, |
2844 | old_read_domains, | |
2845 | old_write_domain); | |
2846 | ||
e47c68e9 EA |
2847 | return 0; |
2848 | } | |
2849 | ||
e4ffd173 CW |
2850 | int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj, |
2851 | enum i915_cache_level cache_level) | |
2852 | { | |
7bddb01f DV |
2853 | struct drm_device *dev = obj->base.dev; |
2854 | drm_i915_private_t *dev_priv = dev->dev_private; | |
e4ffd173 CW |
2855 | int ret; |
2856 | ||
2857 | if (obj->cache_level == cache_level) | |
2858 | return 0; | |
2859 | ||
2860 | if (obj->pin_count) { | |
2861 | DRM_DEBUG("can not change the cache level of pinned objects\n"); | |
2862 | return -EBUSY; | |
2863 | } | |
2864 | ||
2865 | if (obj->gtt_space) { | |
2866 | ret = i915_gem_object_finish_gpu(obj); | |
2867 | if (ret) | |
2868 | return ret; | |
2869 | ||
2870 | i915_gem_object_finish_gtt(obj); | |
2871 | ||
2872 | /* Before SandyBridge, you could not use tiling or fence | |
2873 | * registers with snooped memory, so relinquish any fences | |
2874 | * currently pointing to our region in the aperture. | |
2875 | */ | |
2876 | if (INTEL_INFO(obj->base.dev)->gen < 6) { | |
2877 | ret = i915_gem_object_put_fence(obj); | |
2878 | if (ret) | |
2879 | return ret; | |
2880 | } | |
2881 | ||
74898d7e DV |
2882 | if (obj->has_global_gtt_mapping) |
2883 | i915_gem_gtt_bind_object(obj, cache_level); | |
7bddb01f DV |
2884 | if (obj->has_aliasing_ppgtt_mapping) |
2885 | i915_ppgtt_bind_object(dev_priv->mm.aliasing_ppgtt, | |
2886 | obj, cache_level); | |
e4ffd173 CW |
2887 | } |
2888 | ||
2889 | if (cache_level == I915_CACHE_NONE) { | |
2890 | u32 old_read_domains, old_write_domain; | |
2891 | ||
2892 | /* If we're coming from LLC cached, then we haven't | |
2893 | * actually been tracking whether the data is in the | |
2894 | * CPU cache or not, since we only allow one bit set | |
2895 | * in obj->write_domain and have been skipping the clflushes. | |
2896 | * Just set it to the CPU cache for now. | |
2897 | */ | |
2898 | WARN_ON(obj->base.write_domain & ~I915_GEM_DOMAIN_CPU); | |
2899 | WARN_ON(obj->base.read_domains & ~I915_GEM_DOMAIN_CPU); | |
2900 | ||
2901 | old_read_domains = obj->base.read_domains; | |
2902 | old_write_domain = obj->base.write_domain; | |
2903 | ||
2904 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; | |
2905 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; | |
2906 | ||
2907 | trace_i915_gem_object_change_domain(obj, | |
2908 | old_read_domains, | |
2909 | old_write_domain); | |
2910 | } | |
2911 | ||
2912 | obj->cache_level = cache_level; | |
2913 | return 0; | |
2914 | } | |
2915 | ||
b9241ea3 | 2916 | /* |
2da3b9b9 CW |
2917 | * Prepare buffer for display plane (scanout, cursors, etc). |
2918 | * Can be called from an uninterruptible phase (modesetting) and allows | |
2919 | * any flushes to be pipelined (for pageflips). | |
2920 | * | |
2921 | * For the display plane, we want to be in the GTT but out of any write | |
2922 | * domains. So in many ways this looks like set_to_gtt_domain() apart from the | |
2923 | * ability to pipeline the waits, pinning and any additional subtleties | |
2924 | * that may differentiate the display plane from ordinary buffers. | |
b9241ea3 ZW |
2925 | */ |
2926 | int | |
2da3b9b9 CW |
2927 | i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj, |
2928 | u32 alignment, | |
919926ae | 2929 | struct intel_ring_buffer *pipelined) |
b9241ea3 | 2930 | { |
2da3b9b9 | 2931 | u32 old_read_domains, old_write_domain; |
b9241ea3 ZW |
2932 | int ret; |
2933 | ||
88241785 CW |
2934 | ret = i915_gem_object_flush_gpu_write_domain(obj); |
2935 | if (ret) | |
2936 | return ret; | |
2937 | ||
0be73284 | 2938 | if (pipelined != obj->ring) { |
ce453d81 | 2939 | ret = i915_gem_object_wait_rendering(obj); |
f0b69efc | 2940 | if (ret == -ERESTARTSYS) |
b9241ea3 ZW |
2941 | return ret; |
2942 | } | |
2943 | ||
a7ef0640 EA |
2944 | /* The display engine is not coherent with the LLC cache on gen6. As |
2945 | * a result, we make sure that the pinning that is about to occur is | |
2946 | * done with uncached PTEs. This is lowest common denominator for all | |
2947 | * chipsets. | |
2948 | * | |
2949 | * However for gen6+, we could do better by using the GFDT bit instead | |
2950 | * of uncaching, which would allow us to flush all the LLC-cached data | |
2951 | * with that bit in the PTE to main memory with just one PIPE_CONTROL. | |
2952 | */ | |
2953 | ret = i915_gem_object_set_cache_level(obj, I915_CACHE_NONE); | |
2954 | if (ret) | |
2955 | return ret; | |
2956 | ||
2da3b9b9 CW |
2957 | /* As the user may map the buffer once pinned in the display plane |
2958 | * (e.g. libkms for the bootup splash), we have to ensure that we | |
2959 | * always use map_and_fenceable for all scanout buffers. | |
2960 | */ | |
2961 | ret = i915_gem_object_pin(obj, alignment, true); | |
2962 | if (ret) | |
2963 | return ret; | |
2964 | ||
b118c1e3 CW |
2965 | i915_gem_object_flush_cpu_write_domain(obj); |
2966 | ||
2da3b9b9 | 2967 | old_write_domain = obj->base.write_domain; |
05394f39 | 2968 | old_read_domains = obj->base.read_domains; |
2da3b9b9 CW |
2969 | |
2970 | /* It should now be out of any other write domains, and we can update | |
2971 | * the domain values for our changes. | |
2972 | */ | |
2973 | BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) != 0); | |
05394f39 | 2974 | obj->base.read_domains |= I915_GEM_DOMAIN_GTT; |
b9241ea3 ZW |
2975 | |
2976 | trace_i915_gem_object_change_domain(obj, | |
2977 | old_read_domains, | |
2da3b9b9 | 2978 | old_write_domain); |
b9241ea3 ZW |
2979 | |
2980 | return 0; | |
2981 | } | |
2982 | ||
85345517 | 2983 | int |
a8198eea | 2984 | i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj) |
85345517 | 2985 | { |
88241785 CW |
2986 | int ret; |
2987 | ||
a8198eea | 2988 | if ((obj->base.read_domains & I915_GEM_GPU_DOMAINS) == 0) |
85345517 CW |
2989 | return 0; |
2990 | ||
88241785 | 2991 | if (obj->base.write_domain & I915_GEM_GPU_DOMAINS) { |
db53a302 | 2992 | ret = i915_gem_flush_ring(obj->ring, 0, obj->base.write_domain); |
88241785 CW |
2993 | if (ret) |
2994 | return ret; | |
2995 | } | |
85345517 | 2996 | |
c501ae7f CW |
2997 | ret = i915_gem_object_wait_rendering(obj); |
2998 | if (ret) | |
2999 | return ret; | |
3000 | ||
a8198eea CW |
3001 | /* Ensure that we invalidate the GPU's caches and TLBs. */ |
3002 | obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS; | |
c501ae7f | 3003 | return 0; |
85345517 CW |
3004 | } |
3005 | ||
e47c68e9 EA |
3006 | /** |
3007 | * Moves a single object to the CPU read, and possibly write domain. | |
3008 | * | |
3009 | * This function returns when the move is complete, including waiting on | |
3010 | * flushes to occur. | |
3011 | */ | |
dabdfe02 | 3012 | int |
919926ae | 3013 | i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write) |
e47c68e9 | 3014 | { |
1c5d22f7 | 3015 | uint32_t old_write_domain, old_read_domains; |
e47c68e9 EA |
3016 | int ret; |
3017 | ||
8d7e3de1 CW |
3018 | if (obj->base.write_domain == I915_GEM_DOMAIN_CPU) |
3019 | return 0; | |
3020 | ||
88241785 CW |
3021 | ret = i915_gem_object_flush_gpu_write_domain(obj); |
3022 | if (ret) | |
3023 | return ret; | |
3024 | ||
ce453d81 | 3025 | ret = i915_gem_object_wait_rendering(obj); |
de18a29e | 3026 | if (ret) |
e47c68e9 | 3027 | return ret; |
2ef7eeaa | 3028 | |
e47c68e9 | 3029 | i915_gem_object_flush_gtt_write_domain(obj); |
2ef7eeaa | 3030 | |
05394f39 CW |
3031 | old_write_domain = obj->base.write_domain; |
3032 | old_read_domains = obj->base.read_domains; | |
1c5d22f7 | 3033 | |
e47c68e9 | 3034 | /* Flush the CPU cache if it's still invalid. */ |
05394f39 | 3035 | if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) { |
2ef7eeaa | 3036 | i915_gem_clflush_object(obj); |
2ef7eeaa | 3037 | |
05394f39 | 3038 | obj->base.read_domains |= I915_GEM_DOMAIN_CPU; |
2ef7eeaa EA |
3039 | } |
3040 | ||
3041 | /* It should now be out of any other write domains, and we can update | |
3042 | * the domain values for our changes. | |
3043 | */ | |
05394f39 | 3044 | BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) != 0); |
e47c68e9 EA |
3045 | |
3046 | /* If we're writing through the CPU, then the GPU read domains will | |
3047 | * need to be invalidated at next use. | |
3048 | */ | |
3049 | if (write) { | |
05394f39 CW |
3050 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; |
3051 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; | |
e47c68e9 | 3052 | } |
2ef7eeaa | 3053 | |
1c5d22f7 CW |
3054 | trace_i915_gem_object_change_domain(obj, |
3055 | old_read_domains, | |
3056 | old_write_domain); | |
3057 | ||
2ef7eeaa EA |
3058 | return 0; |
3059 | } | |
3060 | ||
673a394b EA |
3061 | /* Throttle our rendering by waiting until the ring has completed our requests |
3062 | * emitted over 20 msec ago. | |
3063 | * | |
b962442e EA |
3064 | * Note that if we were to use the current jiffies each time around the loop, |
3065 | * we wouldn't escape the function with any frames outstanding if the time to | |
3066 | * render a frame was over 20ms. | |
3067 | * | |
673a394b EA |
3068 | * This should get us reasonable parallelism between CPU and GPU but also |
3069 | * relatively low latency when blocking on a particular request to finish. | |
3070 | */ | |
40a5f0de | 3071 | static int |
f787a5f5 | 3072 | i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file) |
40a5f0de | 3073 | { |
f787a5f5 CW |
3074 | struct drm_i915_private *dev_priv = dev->dev_private; |
3075 | struct drm_i915_file_private *file_priv = file->driver_priv; | |
b962442e | 3076 | unsigned long recent_enough = jiffies - msecs_to_jiffies(20); |
f787a5f5 CW |
3077 | struct drm_i915_gem_request *request; |
3078 | struct intel_ring_buffer *ring = NULL; | |
3079 | u32 seqno = 0; | |
3080 | int ret; | |
93533c29 | 3081 | |
e110e8d6 CW |
3082 | if (atomic_read(&dev_priv->mm.wedged)) |
3083 | return -EIO; | |
3084 | ||
1c25595f | 3085 | spin_lock(&file_priv->mm.lock); |
f787a5f5 | 3086 | list_for_each_entry(request, &file_priv->mm.request_list, client_list) { |
b962442e EA |
3087 | if (time_after_eq(request->emitted_jiffies, recent_enough)) |
3088 | break; | |
40a5f0de | 3089 | |
f787a5f5 CW |
3090 | ring = request->ring; |
3091 | seqno = request->seqno; | |
b962442e | 3092 | } |
1c25595f | 3093 | spin_unlock(&file_priv->mm.lock); |
40a5f0de | 3094 | |
f787a5f5 CW |
3095 | if (seqno == 0) |
3096 | return 0; | |
2bc43b5c | 3097 | |
f787a5f5 | 3098 | ret = 0; |
78501eac | 3099 | if (!i915_seqno_passed(ring->get_seqno(ring), seqno)) { |
f787a5f5 CW |
3100 | /* And wait for the seqno passing without holding any locks and |
3101 | * causing extra latency for others. This is safe as the irq | |
3102 | * generation is designed to be run atomically and so is | |
3103 | * lockless. | |
3104 | */ | |
b13c2b96 CW |
3105 | if (ring->irq_get(ring)) { |
3106 | ret = wait_event_interruptible(ring->irq_queue, | |
3107 | i915_seqno_passed(ring->get_seqno(ring), seqno) | |
3108 | || atomic_read(&dev_priv->mm.wedged)); | |
3109 | ring->irq_put(ring); | |
40a5f0de | 3110 | |
b13c2b96 CW |
3111 | if (ret == 0 && atomic_read(&dev_priv->mm.wedged)) |
3112 | ret = -EIO; | |
e959b5db EA |
3113 | } else if (wait_for_atomic(i915_seqno_passed(ring->get_seqno(ring), |
3114 | seqno) || | |
7ea29b13 EA |
3115 | atomic_read(&dev_priv->mm.wedged), 3000)) { |
3116 | ret = -EBUSY; | |
b13c2b96 | 3117 | } |
40a5f0de EA |
3118 | } |
3119 | ||
f787a5f5 CW |
3120 | if (ret == 0) |
3121 | queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, 0); | |
40a5f0de EA |
3122 | |
3123 | return ret; | |
3124 | } | |
3125 | ||
673a394b | 3126 | int |
05394f39 CW |
3127 | i915_gem_object_pin(struct drm_i915_gem_object *obj, |
3128 | uint32_t alignment, | |
75e9e915 | 3129 | bool map_and_fenceable) |
673a394b | 3130 | { |
05394f39 | 3131 | struct drm_device *dev = obj->base.dev; |
f13d3f73 | 3132 | struct drm_i915_private *dev_priv = dev->dev_private; |
673a394b EA |
3133 | int ret; |
3134 | ||
05394f39 | 3135 | BUG_ON(obj->pin_count == DRM_I915_GEM_OBJECT_MAX_PIN_COUNT); |
23bc5982 | 3136 | WARN_ON(i915_verify_lists(dev)); |
ac0c6b5a | 3137 | |
05394f39 CW |
3138 | if (obj->gtt_space != NULL) { |
3139 | if ((alignment && obj->gtt_offset & (alignment - 1)) || | |
3140 | (map_and_fenceable && !obj->map_and_fenceable)) { | |
3141 | WARN(obj->pin_count, | |
ae7d49d8 | 3142 | "bo is already pinned with incorrect alignment:" |
75e9e915 DV |
3143 | " offset=%x, req.alignment=%x, req.map_and_fenceable=%d," |
3144 | " obj->map_and_fenceable=%d\n", | |
05394f39 | 3145 | obj->gtt_offset, alignment, |
75e9e915 | 3146 | map_and_fenceable, |
05394f39 | 3147 | obj->map_and_fenceable); |
ac0c6b5a CW |
3148 | ret = i915_gem_object_unbind(obj); |
3149 | if (ret) | |
3150 | return ret; | |
3151 | } | |
3152 | } | |
3153 | ||
05394f39 | 3154 | if (obj->gtt_space == NULL) { |
a00b10c3 | 3155 | ret = i915_gem_object_bind_to_gtt(obj, alignment, |
75e9e915 | 3156 | map_and_fenceable); |
9731129c | 3157 | if (ret) |
673a394b | 3158 | return ret; |
22c344e9 | 3159 | } |
76446cac | 3160 | |
74898d7e DV |
3161 | if (!obj->has_global_gtt_mapping && map_and_fenceable) |
3162 | i915_gem_gtt_bind_object(obj, obj->cache_level); | |
3163 | ||
05394f39 | 3164 | if (obj->pin_count++ == 0) { |
05394f39 CW |
3165 | if (!obj->active) |
3166 | list_move_tail(&obj->mm_list, | |
f13d3f73 | 3167 | &dev_priv->mm.pinned_list); |
673a394b | 3168 | } |
6299f992 | 3169 | obj->pin_mappable |= map_and_fenceable; |
673a394b | 3170 | |
23bc5982 | 3171 | WARN_ON(i915_verify_lists(dev)); |
673a394b EA |
3172 | return 0; |
3173 | } | |
3174 | ||
3175 | void | |
05394f39 | 3176 | i915_gem_object_unpin(struct drm_i915_gem_object *obj) |
673a394b | 3177 | { |
05394f39 | 3178 | struct drm_device *dev = obj->base.dev; |
673a394b | 3179 | drm_i915_private_t *dev_priv = dev->dev_private; |
673a394b | 3180 | |
23bc5982 | 3181 | WARN_ON(i915_verify_lists(dev)); |
05394f39 CW |
3182 | BUG_ON(obj->pin_count == 0); |
3183 | BUG_ON(obj->gtt_space == NULL); | |
673a394b | 3184 | |
05394f39 CW |
3185 | if (--obj->pin_count == 0) { |
3186 | if (!obj->active) | |
3187 | list_move_tail(&obj->mm_list, | |
673a394b | 3188 | &dev_priv->mm.inactive_list); |
6299f992 | 3189 | obj->pin_mappable = false; |
673a394b | 3190 | } |
23bc5982 | 3191 | WARN_ON(i915_verify_lists(dev)); |
673a394b EA |
3192 | } |
3193 | ||
3194 | int | |
3195 | i915_gem_pin_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 3196 | struct drm_file *file) |
673a394b EA |
3197 | { |
3198 | struct drm_i915_gem_pin *args = data; | |
05394f39 | 3199 | struct drm_i915_gem_object *obj; |
673a394b EA |
3200 | int ret; |
3201 | ||
1d7cfea1 CW |
3202 | ret = i915_mutex_lock_interruptible(dev); |
3203 | if (ret) | |
3204 | return ret; | |
673a394b | 3205 | |
05394f39 | 3206 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 3207 | if (&obj->base == NULL) { |
1d7cfea1 CW |
3208 | ret = -ENOENT; |
3209 | goto unlock; | |
673a394b | 3210 | } |
673a394b | 3211 | |
05394f39 | 3212 | if (obj->madv != I915_MADV_WILLNEED) { |
bb6baf76 | 3213 | DRM_ERROR("Attempting to pin a purgeable buffer\n"); |
1d7cfea1 CW |
3214 | ret = -EINVAL; |
3215 | goto out; | |
3ef94daa CW |
3216 | } |
3217 | ||
05394f39 | 3218 | if (obj->pin_filp != NULL && obj->pin_filp != file) { |
79e53945 JB |
3219 | DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n", |
3220 | args->handle); | |
1d7cfea1 CW |
3221 | ret = -EINVAL; |
3222 | goto out; | |
79e53945 JB |
3223 | } |
3224 | ||
05394f39 CW |
3225 | obj->user_pin_count++; |
3226 | obj->pin_filp = file; | |
3227 | if (obj->user_pin_count == 1) { | |
75e9e915 | 3228 | ret = i915_gem_object_pin(obj, args->alignment, true); |
1d7cfea1 CW |
3229 | if (ret) |
3230 | goto out; | |
673a394b EA |
3231 | } |
3232 | ||
3233 | /* XXX - flush the CPU caches for pinned objects | |
3234 | * as the X server doesn't manage domains yet | |
3235 | */ | |
e47c68e9 | 3236 | i915_gem_object_flush_cpu_write_domain(obj); |
05394f39 | 3237 | args->offset = obj->gtt_offset; |
1d7cfea1 | 3238 | out: |
05394f39 | 3239 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 3240 | unlock: |
673a394b | 3241 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 3242 | return ret; |
673a394b EA |
3243 | } |
3244 | ||
3245 | int | |
3246 | i915_gem_unpin_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 3247 | struct drm_file *file) |
673a394b EA |
3248 | { |
3249 | struct drm_i915_gem_pin *args = data; | |
05394f39 | 3250 | struct drm_i915_gem_object *obj; |
76c1dec1 | 3251 | int ret; |
673a394b | 3252 | |
1d7cfea1 CW |
3253 | ret = i915_mutex_lock_interruptible(dev); |
3254 | if (ret) | |
3255 | return ret; | |
673a394b | 3256 | |
05394f39 | 3257 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 3258 | if (&obj->base == NULL) { |
1d7cfea1 CW |
3259 | ret = -ENOENT; |
3260 | goto unlock; | |
673a394b | 3261 | } |
76c1dec1 | 3262 | |
05394f39 | 3263 | if (obj->pin_filp != file) { |
79e53945 JB |
3264 | DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n", |
3265 | args->handle); | |
1d7cfea1 CW |
3266 | ret = -EINVAL; |
3267 | goto out; | |
79e53945 | 3268 | } |
05394f39 CW |
3269 | obj->user_pin_count--; |
3270 | if (obj->user_pin_count == 0) { | |
3271 | obj->pin_filp = NULL; | |
79e53945 JB |
3272 | i915_gem_object_unpin(obj); |
3273 | } | |
673a394b | 3274 | |
1d7cfea1 | 3275 | out: |
05394f39 | 3276 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 3277 | unlock: |
673a394b | 3278 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 3279 | return ret; |
673a394b EA |
3280 | } |
3281 | ||
3282 | int | |
3283 | i915_gem_busy_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 3284 | struct drm_file *file) |
673a394b EA |
3285 | { |
3286 | struct drm_i915_gem_busy *args = data; | |
05394f39 | 3287 | struct drm_i915_gem_object *obj; |
30dbf0c0 CW |
3288 | int ret; |
3289 | ||
76c1dec1 | 3290 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 3291 | if (ret) |
76c1dec1 | 3292 | return ret; |
673a394b | 3293 | |
05394f39 | 3294 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 3295 | if (&obj->base == NULL) { |
1d7cfea1 CW |
3296 | ret = -ENOENT; |
3297 | goto unlock; | |
673a394b | 3298 | } |
d1b851fc | 3299 | |
0be555b6 CW |
3300 | /* Count all active objects as busy, even if they are currently not used |
3301 | * by the gpu. Users of this interface expect objects to eventually | |
3302 | * become non-busy without any further actions, therefore emit any | |
3303 | * necessary flushes here. | |
c4de0a5d | 3304 | */ |
05394f39 | 3305 | args->busy = obj->active; |
0be555b6 CW |
3306 | if (args->busy) { |
3307 | /* Unconditionally flush objects, even when the gpu still uses this | |
3308 | * object. Userspace calling this function indicates that it wants to | |
3309 | * use this buffer rather sooner than later, so issuing the required | |
3310 | * flush earlier is beneficial. | |
3311 | */ | |
1a1c6976 | 3312 | if (obj->base.write_domain & I915_GEM_GPU_DOMAINS) { |
db53a302 | 3313 | ret = i915_gem_flush_ring(obj->ring, |
88241785 | 3314 | 0, obj->base.write_domain); |
1a1c6976 CW |
3315 | } else if (obj->ring->outstanding_lazy_request == |
3316 | obj->last_rendering_seqno) { | |
3317 | struct drm_i915_gem_request *request; | |
3318 | ||
7a194876 CW |
3319 | /* This ring is not being cleared by active usage, |
3320 | * so emit a request to do so. | |
3321 | */ | |
1a1c6976 | 3322 | request = kzalloc(sizeof(*request), GFP_KERNEL); |
457eafce | 3323 | if (request) { |
0206e353 | 3324 | ret = i915_add_request(obj->ring, NULL, request); |
457eafce RM |
3325 | if (ret) |
3326 | kfree(request); | |
3327 | } else | |
7a194876 CW |
3328 | ret = -ENOMEM; |
3329 | } | |
0be555b6 CW |
3330 | |
3331 | /* Update the active list for the hardware's current position. | |
3332 | * Otherwise this only updates on a delayed timer or when irqs | |
3333 | * are actually unmasked, and our working set ends up being | |
3334 | * larger than required. | |
3335 | */ | |
db53a302 | 3336 | i915_gem_retire_requests_ring(obj->ring); |
0be555b6 | 3337 | |
05394f39 | 3338 | args->busy = obj->active; |
0be555b6 | 3339 | } |
673a394b | 3340 | |
05394f39 | 3341 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 3342 | unlock: |
673a394b | 3343 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 3344 | return ret; |
673a394b EA |
3345 | } |
3346 | ||
3347 | int | |
3348 | i915_gem_throttle_ioctl(struct drm_device *dev, void *data, | |
3349 | struct drm_file *file_priv) | |
3350 | { | |
0206e353 | 3351 | return i915_gem_ring_throttle(dev, file_priv); |
673a394b EA |
3352 | } |
3353 | ||
3ef94daa CW |
3354 | int |
3355 | i915_gem_madvise_ioctl(struct drm_device *dev, void *data, | |
3356 | struct drm_file *file_priv) | |
3357 | { | |
3358 | struct drm_i915_gem_madvise *args = data; | |
05394f39 | 3359 | struct drm_i915_gem_object *obj; |
76c1dec1 | 3360 | int ret; |
3ef94daa CW |
3361 | |
3362 | switch (args->madv) { | |
3363 | case I915_MADV_DONTNEED: | |
3364 | case I915_MADV_WILLNEED: | |
3365 | break; | |
3366 | default: | |
3367 | return -EINVAL; | |
3368 | } | |
3369 | ||
1d7cfea1 CW |
3370 | ret = i915_mutex_lock_interruptible(dev); |
3371 | if (ret) | |
3372 | return ret; | |
3373 | ||
05394f39 | 3374 | obj = to_intel_bo(drm_gem_object_lookup(dev, file_priv, args->handle)); |
c8725226 | 3375 | if (&obj->base == NULL) { |
1d7cfea1 CW |
3376 | ret = -ENOENT; |
3377 | goto unlock; | |
3ef94daa | 3378 | } |
3ef94daa | 3379 | |
05394f39 | 3380 | if (obj->pin_count) { |
1d7cfea1 CW |
3381 | ret = -EINVAL; |
3382 | goto out; | |
3ef94daa CW |
3383 | } |
3384 | ||
05394f39 CW |
3385 | if (obj->madv != __I915_MADV_PURGED) |
3386 | obj->madv = args->madv; | |
3ef94daa | 3387 | |
2d7ef395 | 3388 | /* if the object is no longer bound, discard its backing storage */ |
05394f39 CW |
3389 | if (i915_gem_object_is_purgeable(obj) && |
3390 | obj->gtt_space == NULL) | |
2d7ef395 CW |
3391 | i915_gem_object_truncate(obj); |
3392 | ||
05394f39 | 3393 | args->retained = obj->madv != __I915_MADV_PURGED; |
bb6baf76 | 3394 | |
1d7cfea1 | 3395 | out: |
05394f39 | 3396 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 3397 | unlock: |
3ef94daa | 3398 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 3399 | return ret; |
3ef94daa CW |
3400 | } |
3401 | ||
05394f39 CW |
3402 | struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev, |
3403 | size_t size) | |
ac52bc56 | 3404 | { |
73aa808f | 3405 | struct drm_i915_private *dev_priv = dev->dev_private; |
c397b908 | 3406 | struct drm_i915_gem_object *obj; |
5949eac4 | 3407 | struct address_space *mapping; |
ac52bc56 | 3408 | |
c397b908 DV |
3409 | obj = kzalloc(sizeof(*obj), GFP_KERNEL); |
3410 | if (obj == NULL) | |
3411 | return NULL; | |
673a394b | 3412 | |
c397b908 DV |
3413 | if (drm_gem_object_init(dev, &obj->base, size) != 0) { |
3414 | kfree(obj); | |
3415 | return NULL; | |
3416 | } | |
673a394b | 3417 | |
5949eac4 HD |
3418 | mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping; |
3419 | mapping_set_gfp_mask(mapping, GFP_HIGHUSER | __GFP_RECLAIMABLE); | |
3420 | ||
73aa808f CW |
3421 | i915_gem_info_add_obj(dev_priv, size); |
3422 | ||
c397b908 DV |
3423 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; |
3424 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; | |
673a394b | 3425 | |
3d29b842 ED |
3426 | if (HAS_LLC(dev)) { |
3427 | /* On some devices, we can have the GPU use the LLC (the CPU | |
a1871112 EA |
3428 | * cache) for about a 10% performance improvement |
3429 | * compared to uncached. Graphics requests other than | |
3430 | * display scanout are coherent with the CPU in | |
3431 | * accessing this cache. This means in this mode we | |
3432 | * don't need to clflush on the CPU side, and on the | |
3433 | * GPU side we only need to flush internal caches to | |
3434 | * get data visible to the CPU. | |
3435 | * | |
3436 | * However, we maintain the display planes as UC, and so | |
3437 | * need to rebind when first used as such. | |
3438 | */ | |
3439 | obj->cache_level = I915_CACHE_LLC; | |
3440 | } else | |
3441 | obj->cache_level = I915_CACHE_NONE; | |
3442 | ||
62b8b215 | 3443 | obj->base.driver_private = NULL; |
c397b908 | 3444 | obj->fence_reg = I915_FENCE_REG_NONE; |
69dc4987 | 3445 | INIT_LIST_HEAD(&obj->mm_list); |
93a37f20 | 3446 | INIT_LIST_HEAD(&obj->gtt_list); |
69dc4987 | 3447 | INIT_LIST_HEAD(&obj->ring_list); |
432e58ed | 3448 | INIT_LIST_HEAD(&obj->exec_list); |
c397b908 | 3449 | INIT_LIST_HEAD(&obj->gpu_write_list); |
c397b908 | 3450 | obj->madv = I915_MADV_WILLNEED; |
75e9e915 DV |
3451 | /* Avoid an unnecessary call to unbind on the first bind. */ |
3452 | obj->map_and_fenceable = true; | |
de151cf6 | 3453 | |
05394f39 | 3454 | return obj; |
c397b908 DV |
3455 | } |
3456 | ||
3457 | int i915_gem_init_object(struct drm_gem_object *obj) | |
3458 | { | |
3459 | BUG(); | |
de151cf6 | 3460 | |
673a394b EA |
3461 | return 0; |
3462 | } | |
3463 | ||
05394f39 | 3464 | static void i915_gem_free_object_tail(struct drm_i915_gem_object *obj) |
673a394b | 3465 | { |
05394f39 | 3466 | struct drm_device *dev = obj->base.dev; |
be72615b | 3467 | drm_i915_private_t *dev_priv = dev->dev_private; |
be72615b | 3468 | int ret; |
673a394b | 3469 | |
be72615b CW |
3470 | ret = i915_gem_object_unbind(obj); |
3471 | if (ret == -ERESTARTSYS) { | |
05394f39 | 3472 | list_move(&obj->mm_list, |
be72615b CW |
3473 | &dev_priv->mm.deferred_free_list); |
3474 | return; | |
3475 | } | |
673a394b | 3476 | |
26e12f89 CW |
3477 | trace_i915_gem_object_destroy(obj); |
3478 | ||
05394f39 | 3479 | if (obj->base.map_list.map) |
b464e9a2 | 3480 | drm_gem_free_mmap_offset(&obj->base); |
de151cf6 | 3481 | |
05394f39 CW |
3482 | drm_gem_object_release(&obj->base); |
3483 | i915_gem_info_remove_obj(dev_priv, obj->base.size); | |
c397b908 | 3484 | |
05394f39 CW |
3485 | kfree(obj->bit_17); |
3486 | kfree(obj); | |
673a394b EA |
3487 | } |
3488 | ||
05394f39 | 3489 | void i915_gem_free_object(struct drm_gem_object *gem_obj) |
be72615b | 3490 | { |
05394f39 CW |
3491 | struct drm_i915_gem_object *obj = to_intel_bo(gem_obj); |
3492 | struct drm_device *dev = obj->base.dev; | |
be72615b | 3493 | |
05394f39 | 3494 | while (obj->pin_count > 0) |
be72615b CW |
3495 | i915_gem_object_unpin(obj); |
3496 | ||
05394f39 | 3497 | if (obj->phys_obj) |
be72615b CW |
3498 | i915_gem_detach_phys_object(dev, obj); |
3499 | ||
3500 | i915_gem_free_object_tail(obj); | |
3501 | } | |
3502 | ||
29105ccc CW |
3503 | int |
3504 | i915_gem_idle(struct drm_device *dev) | |
3505 | { | |
3506 | drm_i915_private_t *dev_priv = dev->dev_private; | |
3507 | int ret; | |
28dfe52a | 3508 | |
29105ccc | 3509 | mutex_lock(&dev->struct_mutex); |
1c5d22f7 | 3510 | |
87acb0a5 | 3511 | if (dev_priv->mm.suspended) { |
29105ccc CW |
3512 | mutex_unlock(&dev->struct_mutex); |
3513 | return 0; | |
28dfe52a EA |
3514 | } |
3515 | ||
b93f9cf1 | 3516 | ret = i915_gpu_idle(dev, true); |
6dbe2772 KP |
3517 | if (ret) { |
3518 | mutex_unlock(&dev->struct_mutex); | |
673a394b | 3519 | return ret; |
6dbe2772 | 3520 | } |
673a394b | 3521 | |
29105ccc CW |
3522 | /* Under UMS, be paranoid and evict. */ |
3523 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) { | |
5eac3ab4 | 3524 | ret = i915_gem_evict_inactive(dev, false); |
29105ccc CW |
3525 | if (ret) { |
3526 | mutex_unlock(&dev->struct_mutex); | |
3527 | return ret; | |
3528 | } | |
3529 | } | |
3530 | ||
312817a3 CW |
3531 | i915_gem_reset_fences(dev); |
3532 | ||
29105ccc CW |
3533 | /* Hack! Don't let anybody do execbuf while we don't control the chip. |
3534 | * We need to replace this with a semaphore, or something. | |
3535 | * And not confound mm.suspended! | |
3536 | */ | |
3537 | dev_priv->mm.suspended = 1; | |
bc0c7f14 | 3538 | del_timer_sync(&dev_priv->hangcheck_timer); |
29105ccc CW |
3539 | |
3540 | i915_kernel_lost_context(dev); | |
6dbe2772 | 3541 | i915_gem_cleanup_ringbuffer(dev); |
29105ccc | 3542 | |
6dbe2772 KP |
3543 | mutex_unlock(&dev->struct_mutex); |
3544 | ||
29105ccc CW |
3545 | /* Cancel the retire work handler, which should be idle now. */ |
3546 | cancel_delayed_work_sync(&dev_priv->mm.retire_work); | |
3547 | ||
673a394b EA |
3548 | return 0; |
3549 | } | |
3550 | ||
f691e2f4 DV |
3551 | void i915_gem_init_swizzling(struct drm_device *dev) |
3552 | { | |
3553 | drm_i915_private_t *dev_priv = dev->dev_private; | |
3554 | ||
11782b02 | 3555 | if (INTEL_INFO(dev)->gen < 5 || |
f691e2f4 DV |
3556 | dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE) |
3557 | return; | |
3558 | ||
3559 | I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) | | |
3560 | DISP_TILE_SURFACE_SWIZZLING); | |
3561 | ||
11782b02 DV |
3562 | if (IS_GEN5(dev)) |
3563 | return; | |
3564 | ||
f691e2f4 DV |
3565 | I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_SWZCTL); |
3566 | if (IS_GEN6(dev)) | |
3567 | I915_WRITE(ARB_MODE, ARB_MODE_ENABLE(ARB_MODE_SWIZZLE_SNB)); | |
3568 | else | |
3569 | I915_WRITE(ARB_MODE, ARB_MODE_ENABLE(ARB_MODE_SWIZZLE_IVB)); | |
3570 | } | |
e21af88d DV |
3571 | |
3572 | void i915_gem_init_ppgtt(struct drm_device *dev) | |
3573 | { | |
3574 | drm_i915_private_t *dev_priv = dev->dev_private; | |
3575 | uint32_t pd_offset; | |
3576 | struct intel_ring_buffer *ring; | |
3577 | int i; | |
3578 | ||
3579 | if (!dev_priv->mm.aliasing_ppgtt) | |
3580 | return; | |
3581 | ||
3582 | pd_offset = dev_priv->mm.aliasing_ppgtt->pd_offset; | |
3583 | pd_offset /= 64; /* in cachelines, */ | |
3584 | pd_offset <<= 16; | |
3585 | ||
3586 | if (INTEL_INFO(dev)->gen == 6) { | |
3587 | uint32_t ecochk = I915_READ(GAM_ECOCHK); | |
3588 | I915_WRITE(GAM_ECOCHK, ecochk | ECOCHK_SNB_BIT | | |
3589 | ECOCHK_PPGTT_CACHE64B); | |
3590 | I915_WRITE(GFX_MODE, GFX_MODE_ENABLE(GFX_PPGTT_ENABLE)); | |
3591 | } else if (INTEL_INFO(dev)->gen >= 7) { | |
3592 | I915_WRITE(GAM_ECOCHK, ECOCHK_PPGTT_CACHE64B); | |
3593 | /* GFX_MODE is per-ring on gen7+ */ | |
3594 | } | |
3595 | ||
3596 | for (i = 0; i < I915_NUM_RINGS; i++) { | |
3597 | ring = &dev_priv->ring[i]; | |
3598 | ||
3599 | if (INTEL_INFO(dev)->gen >= 7) | |
3600 | I915_WRITE(RING_MODE_GEN7(ring), | |
3601 | GFX_MODE_ENABLE(GFX_PPGTT_ENABLE)); | |
3602 | ||
3603 | I915_WRITE(RING_PP_DIR_DCLV(ring), PP_DIR_DCLV_2G); | |
3604 | I915_WRITE(RING_PP_DIR_BASE(ring), pd_offset); | |
3605 | } | |
3606 | } | |
3607 | ||
8187a2b7 | 3608 | int |
f691e2f4 | 3609 | i915_gem_init_hw(struct drm_device *dev) |
8187a2b7 ZN |
3610 | { |
3611 | drm_i915_private_t *dev_priv = dev->dev_private; | |
3612 | int ret; | |
68f95ba9 | 3613 | |
f691e2f4 DV |
3614 | i915_gem_init_swizzling(dev); |
3615 | ||
5c1143bb | 3616 | ret = intel_init_render_ring_buffer(dev); |
68f95ba9 | 3617 | if (ret) |
b6913e4b | 3618 | return ret; |
68f95ba9 CW |
3619 | |
3620 | if (HAS_BSD(dev)) { | |
5c1143bb | 3621 | ret = intel_init_bsd_ring_buffer(dev); |
68f95ba9 CW |
3622 | if (ret) |
3623 | goto cleanup_render_ring; | |
d1b851fc | 3624 | } |
68f95ba9 | 3625 | |
549f7365 CW |
3626 | if (HAS_BLT(dev)) { |
3627 | ret = intel_init_blt_ring_buffer(dev); | |
3628 | if (ret) | |
3629 | goto cleanup_bsd_ring; | |
3630 | } | |
3631 | ||
6f392d54 CW |
3632 | dev_priv->next_seqno = 1; |
3633 | ||
e21af88d DV |
3634 | i915_gem_init_ppgtt(dev); |
3635 | ||
68f95ba9 CW |
3636 | return 0; |
3637 | ||
549f7365 | 3638 | cleanup_bsd_ring: |
1ec14ad3 | 3639 | intel_cleanup_ring_buffer(&dev_priv->ring[VCS]); |
68f95ba9 | 3640 | cleanup_render_ring: |
1ec14ad3 | 3641 | intel_cleanup_ring_buffer(&dev_priv->ring[RCS]); |
8187a2b7 ZN |
3642 | return ret; |
3643 | } | |
3644 | ||
3645 | void | |
3646 | i915_gem_cleanup_ringbuffer(struct drm_device *dev) | |
3647 | { | |
3648 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1ec14ad3 | 3649 | int i; |
8187a2b7 | 3650 | |
1ec14ad3 CW |
3651 | for (i = 0; i < I915_NUM_RINGS; i++) |
3652 | intel_cleanup_ring_buffer(&dev_priv->ring[i]); | |
8187a2b7 ZN |
3653 | } |
3654 | ||
673a394b EA |
3655 | int |
3656 | i915_gem_entervt_ioctl(struct drm_device *dev, void *data, | |
3657 | struct drm_file *file_priv) | |
3658 | { | |
3659 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1ec14ad3 | 3660 | int ret, i; |
673a394b | 3661 | |
79e53945 JB |
3662 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
3663 | return 0; | |
3664 | ||
ba1234d1 | 3665 | if (atomic_read(&dev_priv->mm.wedged)) { |
673a394b | 3666 | DRM_ERROR("Reenabling wedged hardware, good luck\n"); |
ba1234d1 | 3667 | atomic_set(&dev_priv->mm.wedged, 0); |
673a394b EA |
3668 | } |
3669 | ||
673a394b | 3670 | mutex_lock(&dev->struct_mutex); |
9bb2d6f9 EA |
3671 | dev_priv->mm.suspended = 0; |
3672 | ||
f691e2f4 | 3673 | ret = i915_gem_init_hw(dev); |
d816f6ac WF |
3674 | if (ret != 0) { |
3675 | mutex_unlock(&dev->struct_mutex); | |
9bb2d6f9 | 3676 | return ret; |
d816f6ac | 3677 | } |
9bb2d6f9 | 3678 | |
69dc4987 | 3679 | BUG_ON(!list_empty(&dev_priv->mm.active_list)); |
673a394b EA |
3680 | BUG_ON(!list_empty(&dev_priv->mm.flushing_list)); |
3681 | BUG_ON(!list_empty(&dev_priv->mm.inactive_list)); | |
1ec14ad3 CW |
3682 | for (i = 0; i < I915_NUM_RINGS; i++) { |
3683 | BUG_ON(!list_empty(&dev_priv->ring[i].active_list)); | |
3684 | BUG_ON(!list_empty(&dev_priv->ring[i].request_list)); | |
3685 | } | |
673a394b | 3686 | mutex_unlock(&dev->struct_mutex); |
dbb19d30 | 3687 | |
5f35308b CW |
3688 | ret = drm_irq_install(dev); |
3689 | if (ret) | |
3690 | goto cleanup_ringbuffer; | |
dbb19d30 | 3691 | |
673a394b | 3692 | return 0; |
5f35308b CW |
3693 | |
3694 | cleanup_ringbuffer: | |
3695 | mutex_lock(&dev->struct_mutex); | |
3696 | i915_gem_cleanup_ringbuffer(dev); | |
3697 | dev_priv->mm.suspended = 1; | |
3698 | mutex_unlock(&dev->struct_mutex); | |
3699 | ||
3700 | return ret; | |
673a394b EA |
3701 | } |
3702 | ||
3703 | int | |
3704 | i915_gem_leavevt_ioctl(struct drm_device *dev, void *data, | |
3705 | struct drm_file *file_priv) | |
3706 | { | |
79e53945 JB |
3707 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
3708 | return 0; | |
3709 | ||
dbb19d30 | 3710 | drm_irq_uninstall(dev); |
e6890f6f | 3711 | return i915_gem_idle(dev); |
673a394b EA |
3712 | } |
3713 | ||
3714 | void | |
3715 | i915_gem_lastclose(struct drm_device *dev) | |
3716 | { | |
3717 | int ret; | |
673a394b | 3718 | |
e806b495 EA |
3719 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
3720 | return; | |
3721 | ||
6dbe2772 KP |
3722 | ret = i915_gem_idle(dev); |
3723 | if (ret) | |
3724 | DRM_ERROR("failed to idle hardware: %d\n", ret); | |
673a394b EA |
3725 | } |
3726 | ||
64193406 CW |
3727 | static void |
3728 | init_ring_lists(struct intel_ring_buffer *ring) | |
3729 | { | |
3730 | INIT_LIST_HEAD(&ring->active_list); | |
3731 | INIT_LIST_HEAD(&ring->request_list); | |
3732 | INIT_LIST_HEAD(&ring->gpu_write_list); | |
3733 | } | |
3734 | ||
673a394b EA |
3735 | void |
3736 | i915_gem_load(struct drm_device *dev) | |
3737 | { | |
b5aa8a0f | 3738 | int i; |
673a394b EA |
3739 | drm_i915_private_t *dev_priv = dev->dev_private; |
3740 | ||
69dc4987 | 3741 | INIT_LIST_HEAD(&dev_priv->mm.active_list); |
673a394b EA |
3742 | INIT_LIST_HEAD(&dev_priv->mm.flushing_list); |
3743 | INIT_LIST_HEAD(&dev_priv->mm.inactive_list); | |
f13d3f73 | 3744 | INIT_LIST_HEAD(&dev_priv->mm.pinned_list); |
a09ba7fa | 3745 | INIT_LIST_HEAD(&dev_priv->mm.fence_list); |
be72615b | 3746 | INIT_LIST_HEAD(&dev_priv->mm.deferred_free_list); |
93a37f20 | 3747 | INIT_LIST_HEAD(&dev_priv->mm.gtt_list); |
1ec14ad3 CW |
3748 | for (i = 0; i < I915_NUM_RINGS; i++) |
3749 | init_ring_lists(&dev_priv->ring[i]); | |
4b9de737 | 3750 | for (i = 0; i < I915_MAX_NUM_FENCES; i++) |
007cc8ac | 3751 | INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list); |
673a394b EA |
3752 | INIT_DELAYED_WORK(&dev_priv->mm.retire_work, |
3753 | i915_gem_retire_work_handler); | |
30dbf0c0 | 3754 | init_completion(&dev_priv->error_completion); |
31169714 | 3755 | |
94400120 DA |
3756 | /* On GEN3 we really need to make sure the ARB C3 LP bit is set */ |
3757 | if (IS_GEN3(dev)) { | |
3758 | u32 tmp = I915_READ(MI_ARB_STATE); | |
3759 | if (!(tmp & MI_ARB_C3_LP_WRITE_ENABLE)) { | |
3760 | /* arb state is a masked write, so set bit + bit in mask */ | |
3761 | tmp = MI_ARB_C3_LP_WRITE_ENABLE | (MI_ARB_C3_LP_WRITE_ENABLE << MI_ARB_MASK_SHIFT); | |
3762 | I915_WRITE(MI_ARB_STATE, tmp); | |
3763 | } | |
3764 | } | |
3765 | ||
72bfa19c CW |
3766 | dev_priv->relative_constants_mode = I915_EXEC_CONSTANTS_REL_GENERAL; |
3767 | ||
de151cf6 | 3768 | /* Old X drivers will take 0-2 for front, back, depth buffers */ |
b397c836 EA |
3769 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) |
3770 | dev_priv->fence_reg_start = 3; | |
de151cf6 | 3771 | |
a6c45cf0 | 3772 | if (INTEL_INFO(dev)->gen >= 4 || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) |
de151cf6 JB |
3773 | dev_priv->num_fence_regs = 16; |
3774 | else | |
3775 | dev_priv->num_fence_regs = 8; | |
3776 | ||
b5aa8a0f | 3777 | /* Initialize fence registers to zero */ |
10ed13e4 EA |
3778 | for (i = 0; i < dev_priv->num_fence_regs; i++) { |
3779 | i915_gem_clear_fence_reg(dev, &dev_priv->fence_regs[i]); | |
b5aa8a0f | 3780 | } |
10ed13e4 | 3781 | |
673a394b | 3782 | i915_gem_detect_bit_6_swizzle(dev); |
6b95a207 | 3783 | init_waitqueue_head(&dev_priv->pending_flip_queue); |
17250b71 | 3784 | |
ce453d81 CW |
3785 | dev_priv->mm.interruptible = true; |
3786 | ||
17250b71 CW |
3787 | dev_priv->mm.inactive_shrinker.shrink = i915_gem_inactive_shrink; |
3788 | dev_priv->mm.inactive_shrinker.seeks = DEFAULT_SEEKS; | |
3789 | register_shrinker(&dev_priv->mm.inactive_shrinker); | |
673a394b | 3790 | } |
71acb5eb DA |
3791 | |
3792 | /* | |
3793 | * Create a physically contiguous memory object for this object | |
3794 | * e.g. for cursor + overlay regs | |
3795 | */ | |
995b6762 CW |
3796 | static int i915_gem_init_phys_object(struct drm_device *dev, |
3797 | int id, int size, int align) | |
71acb5eb DA |
3798 | { |
3799 | drm_i915_private_t *dev_priv = dev->dev_private; | |
3800 | struct drm_i915_gem_phys_object *phys_obj; | |
3801 | int ret; | |
3802 | ||
3803 | if (dev_priv->mm.phys_objs[id - 1] || !size) | |
3804 | return 0; | |
3805 | ||
9a298b2a | 3806 | phys_obj = kzalloc(sizeof(struct drm_i915_gem_phys_object), GFP_KERNEL); |
71acb5eb DA |
3807 | if (!phys_obj) |
3808 | return -ENOMEM; | |
3809 | ||
3810 | phys_obj->id = id; | |
3811 | ||
6eeefaf3 | 3812 | phys_obj->handle = drm_pci_alloc(dev, size, align); |
71acb5eb DA |
3813 | if (!phys_obj->handle) { |
3814 | ret = -ENOMEM; | |
3815 | goto kfree_obj; | |
3816 | } | |
3817 | #ifdef CONFIG_X86 | |
3818 | set_memory_wc((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE); | |
3819 | #endif | |
3820 | ||
3821 | dev_priv->mm.phys_objs[id - 1] = phys_obj; | |
3822 | ||
3823 | return 0; | |
3824 | kfree_obj: | |
9a298b2a | 3825 | kfree(phys_obj); |
71acb5eb DA |
3826 | return ret; |
3827 | } | |
3828 | ||
995b6762 | 3829 | static void i915_gem_free_phys_object(struct drm_device *dev, int id) |
71acb5eb DA |
3830 | { |
3831 | drm_i915_private_t *dev_priv = dev->dev_private; | |
3832 | struct drm_i915_gem_phys_object *phys_obj; | |
3833 | ||
3834 | if (!dev_priv->mm.phys_objs[id - 1]) | |
3835 | return; | |
3836 | ||
3837 | phys_obj = dev_priv->mm.phys_objs[id - 1]; | |
3838 | if (phys_obj->cur_obj) { | |
3839 | i915_gem_detach_phys_object(dev, phys_obj->cur_obj); | |
3840 | } | |
3841 | ||
3842 | #ifdef CONFIG_X86 | |
3843 | set_memory_wb((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE); | |
3844 | #endif | |
3845 | drm_pci_free(dev, phys_obj->handle); | |
3846 | kfree(phys_obj); | |
3847 | dev_priv->mm.phys_objs[id - 1] = NULL; | |
3848 | } | |
3849 | ||
3850 | void i915_gem_free_all_phys_object(struct drm_device *dev) | |
3851 | { | |
3852 | int i; | |
3853 | ||
260883c8 | 3854 | for (i = I915_GEM_PHYS_CURSOR_0; i <= I915_MAX_PHYS_OBJECT; i++) |
71acb5eb DA |
3855 | i915_gem_free_phys_object(dev, i); |
3856 | } | |
3857 | ||
3858 | void i915_gem_detach_phys_object(struct drm_device *dev, | |
05394f39 | 3859 | struct drm_i915_gem_object *obj) |
71acb5eb | 3860 | { |
05394f39 | 3861 | struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping; |
e5281ccd | 3862 | char *vaddr; |
71acb5eb | 3863 | int i; |
71acb5eb DA |
3864 | int page_count; |
3865 | ||
05394f39 | 3866 | if (!obj->phys_obj) |
71acb5eb | 3867 | return; |
05394f39 | 3868 | vaddr = obj->phys_obj->handle->vaddr; |
71acb5eb | 3869 | |
05394f39 | 3870 | page_count = obj->base.size / PAGE_SIZE; |
71acb5eb | 3871 | for (i = 0; i < page_count; i++) { |
5949eac4 | 3872 | struct page *page = shmem_read_mapping_page(mapping, i); |
e5281ccd CW |
3873 | if (!IS_ERR(page)) { |
3874 | char *dst = kmap_atomic(page); | |
3875 | memcpy(dst, vaddr + i*PAGE_SIZE, PAGE_SIZE); | |
3876 | kunmap_atomic(dst); | |
3877 | ||
3878 | drm_clflush_pages(&page, 1); | |
3879 | ||
3880 | set_page_dirty(page); | |
3881 | mark_page_accessed(page); | |
3882 | page_cache_release(page); | |
3883 | } | |
71acb5eb | 3884 | } |
40ce6575 | 3885 | intel_gtt_chipset_flush(); |
d78b47b9 | 3886 | |
05394f39 CW |
3887 | obj->phys_obj->cur_obj = NULL; |
3888 | obj->phys_obj = NULL; | |
71acb5eb DA |
3889 | } |
3890 | ||
3891 | int | |
3892 | i915_gem_attach_phys_object(struct drm_device *dev, | |
05394f39 | 3893 | struct drm_i915_gem_object *obj, |
6eeefaf3 CW |
3894 | int id, |
3895 | int align) | |
71acb5eb | 3896 | { |
05394f39 | 3897 | struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping; |
71acb5eb | 3898 | drm_i915_private_t *dev_priv = dev->dev_private; |
71acb5eb DA |
3899 | int ret = 0; |
3900 | int page_count; | |
3901 | int i; | |
3902 | ||
3903 | if (id > I915_MAX_PHYS_OBJECT) | |
3904 | return -EINVAL; | |
3905 | ||
05394f39 CW |
3906 | if (obj->phys_obj) { |
3907 | if (obj->phys_obj->id == id) | |
71acb5eb DA |
3908 | return 0; |
3909 | i915_gem_detach_phys_object(dev, obj); | |
3910 | } | |
3911 | ||
71acb5eb DA |
3912 | /* create a new object */ |
3913 | if (!dev_priv->mm.phys_objs[id - 1]) { | |
3914 | ret = i915_gem_init_phys_object(dev, id, | |
05394f39 | 3915 | obj->base.size, align); |
71acb5eb | 3916 | if (ret) { |
05394f39 CW |
3917 | DRM_ERROR("failed to init phys object %d size: %zu\n", |
3918 | id, obj->base.size); | |
e5281ccd | 3919 | return ret; |
71acb5eb DA |
3920 | } |
3921 | } | |
3922 | ||
3923 | /* bind to the object */ | |
05394f39 CW |
3924 | obj->phys_obj = dev_priv->mm.phys_objs[id - 1]; |
3925 | obj->phys_obj->cur_obj = obj; | |
71acb5eb | 3926 | |
05394f39 | 3927 | page_count = obj->base.size / PAGE_SIZE; |
71acb5eb DA |
3928 | |
3929 | for (i = 0; i < page_count; i++) { | |
e5281ccd CW |
3930 | struct page *page; |
3931 | char *dst, *src; | |
3932 | ||
5949eac4 | 3933 | page = shmem_read_mapping_page(mapping, i); |
e5281ccd CW |
3934 | if (IS_ERR(page)) |
3935 | return PTR_ERR(page); | |
71acb5eb | 3936 | |
ff75b9bc | 3937 | src = kmap_atomic(page); |
05394f39 | 3938 | dst = obj->phys_obj->handle->vaddr + (i * PAGE_SIZE); |
71acb5eb | 3939 | memcpy(dst, src, PAGE_SIZE); |
3e4d3af5 | 3940 | kunmap_atomic(src); |
71acb5eb | 3941 | |
e5281ccd CW |
3942 | mark_page_accessed(page); |
3943 | page_cache_release(page); | |
3944 | } | |
d78b47b9 | 3945 | |
71acb5eb | 3946 | return 0; |
71acb5eb DA |
3947 | } |
3948 | ||
3949 | static int | |
05394f39 CW |
3950 | i915_gem_phys_pwrite(struct drm_device *dev, |
3951 | struct drm_i915_gem_object *obj, | |
71acb5eb DA |
3952 | struct drm_i915_gem_pwrite *args, |
3953 | struct drm_file *file_priv) | |
3954 | { | |
05394f39 | 3955 | void *vaddr = obj->phys_obj->handle->vaddr + args->offset; |
b47b30cc | 3956 | char __user *user_data = (char __user *) (uintptr_t) args->data_ptr; |
71acb5eb | 3957 | |
b47b30cc CW |
3958 | if (__copy_from_user_inatomic_nocache(vaddr, user_data, args->size)) { |
3959 | unsigned long unwritten; | |
3960 | ||
3961 | /* The physical object once assigned is fixed for the lifetime | |
3962 | * of the obj, so we can safely drop the lock and continue | |
3963 | * to access vaddr. | |
3964 | */ | |
3965 | mutex_unlock(&dev->struct_mutex); | |
3966 | unwritten = copy_from_user(vaddr, user_data, args->size); | |
3967 | mutex_lock(&dev->struct_mutex); | |
3968 | if (unwritten) | |
3969 | return -EFAULT; | |
3970 | } | |
71acb5eb | 3971 | |
40ce6575 | 3972 | intel_gtt_chipset_flush(); |
71acb5eb DA |
3973 | return 0; |
3974 | } | |
b962442e | 3975 | |
f787a5f5 | 3976 | void i915_gem_release(struct drm_device *dev, struct drm_file *file) |
b962442e | 3977 | { |
f787a5f5 | 3978 | struct drm_i915_file_private *file_priv = file->driver_priv; |
b962442e EA |
3979 | |
3980 | /* Clean up our request list when the client is going away, so that | |
3981 | * later retire_requests won't dereference our soon-to-be-gone | |
3982 | * file_priv. | |
3983 | */ | |
1c25595f | 3984 | spin_lock(&file_priv->mm.lock); |
f787a5f5 CW |
3985 | while (!list_empty(&file_priv->mm.request_list)) { |
3986 | struct drm_i915_gem_request *request; | |
3987 | ||
3988 | request = list_first_entry(&file_priv->mm.request_list, | |
3989 | struct drm_i915_gem_request, | |
3990 | client_list); | |
3991 | list_del(&request->client_list); | |
3992 | request->file_priv = NULL; | |
3993 | } | |
1c25595f | 3994 | spin_unlock(&file_priv->mm.lock); |
b962442e | 3995 | } |
31169714 | 3996 | |
1637ef41 CW |
3997 | static int |
3998 | i915_gpu_is_active(struct drm_device *dev) | |
3999 | { | |
4000 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4001 | int lists_empty; | |
4002 | ||
1637ef41 | 4003 | lists_empty = list_empty(&dev_priv->mm.flushing_list) && |
17250b71 | 4004 | list_empty(&dev_priv->mm.active_list); |
1637ef41 CW |
4005 | |
4006 | return !lists_empty; | |
4007 | } | |
4008 | ||
31169714 | 4009 | static int |
1495f230 | 4010 | i915_gem_inactive_shrink(struct shrinker *shrinker, struct shrink_control *sc) |
31169714 | 4011 | { |
17250b71 CW |
4012 | struct drm_i915_private *dev_priv = |
4013 | container_of(shrinker, | |
4014 | struct drm_i915_private, | |
4015 | mm.inactive_shrinker); | |
4016 | struct drm_device *dev = dev_priv->dev; | |
4017 | struct drm_i915_gem_object *obj, *next; | |
1495f230 | 4018 | int nr_to_scan = sc->nr_to_scan; |
17250b71 CW |
4019 | int cnt; |
4020 | ||
4021 | if (!mutex_trylock(&dev->struct_mutex)) | |
bbe2e11a | 4022 | return 0; |
31169714 CW |
4023 | |
4024 | /* "fast-path" to count number of available objects */ | |
4025 | if (nr_to_scan == 0) { | |
17250b71 CW |
4026 | cnt = 0; |
4027 | list_for_each_entry(obj, | |
4028 | &dev_priv->mm.inactive_list, | |
4029 | mm_list) | |
4030 | cnt++; | |
4031 | mutex_unlock(&dev->struct_mutex); | |
4032 | return cnt / 100 * sysctl_vfs_cache_pressure; | |
31169714 CW |
4033 | } |
4034 | ||
1637ef41 | 4035 | rescan: |
31169714 | 4036 | /* first scan for clean buffers */ |
17250b71 | 4037 | i915_gem_retire_requests(dev); |
31169714 | 4038 | |
17250b71 CW |
4039 | list_for_each_entry_safe(obj, next, |
4040 | &dev_priv->mm.inactive_list, | |
4041 | mm_list) { | |
4042 | if (i915_gem_object_is_purgeable(obj)) { | |
2021746e CW |
4043 | if (i915_gem_object_unbind(obj) == 0 && |
4044 | --nr_to_scan == 0) | |
17250b71 | 4045 | break; |
31169714 | 4046 | } |
31169714 CW |
4047 | } |
4048 | ||
4049 | /* second pass, evict/count anything still on the inactive list */ | |
17250b71 CW |
4050 | cnt = 0; |
4051 | list_for_each_entry_safe(obj, next, | |
4052 | &dev_priv->mm.inactive_list, | |
4053 | mm_list) { | |
2021746e CW |
4054 | if (nr_to_scan && |
4055 | i915_gem_object_unbind(obj) == 0) | |
17250b71 | 4056 | nr_to_scan--; |
2021746e | 4057 | else |
17250b71 CW |
4058 | cnt++; |
4059 | } | |
4060 | ||
4061 | if (nr_to_scan && i915_gpu_is_active(dev)) { | |
1637ef41 CW |
4062 | /* |
4063 | * We are desperate for pages, so as a last resort, wait | |
4064 | * for the GPU to finish and discard whatever we can. | |
4065 | * This has a dramatic impact to reduce the number of | |
4066 | * OOM-killer events whilst running the GPU aggressively. | |
4067 | */ | |
b93f9cf1 | 4068 | if (i915_gpu_idle(dev, true) == 0) |
1637ef41 CW |
4069 | goto rescan; |
4070 | } | |
17250b71 CW |
4071 | mutex_unlock(&dev->struct_mutex); |
4072 | return cnt / 100 * sysctl_vfs_cache_pressure; | |
31169714 | 4073 | } |