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673a394b EA |
1 | /* |
2 | * Copyright © 2008 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | * | |
26 | */ | |
27 | ||
28 | #include "drmP.h" | |
29 | #include "drm.h" | |
30 | #include "i915_drm.h" | |
31 | #include "i915_drv.h" | |
1c5d22f7 | 32 | #include "i915_trace.h" |
652c393a | 33 | #include "intel_drv.h" |
5a0e3ad6 | 34 | #include <linux/slab.h> |
673a394b | 35 | #include <linux/swap.h> |
79e53945 | 36 | #include <linux/pci.h> |
f8f235e5 | 37 | #include <linux/intel-gtt.h> |
673a394b | 38 | |
0f8c6d7c CW |
39 | struct change_domains { |
40 | uint32_t invalidate_domains; | |
41 | uint32_t flush_domains; | |
42 | uint32_t flush_rings; | |
43 | }; | |
44 | ||
a00b10c3 CW |
45 | static uint32_t i915_gem_get_gtt_alignment(struct drm_i915_gem_object *obj_priv); |
46 | static uint32_t i915_gem_get_gtt_size(struct drm_i915_gem_object *obj_priv); | |
ba3d8d74 DV |
47 | |
48 | static int i915_gem_object_flush_gpu_write_domain(struct drm_gem_object *obj, | |
49 | bool pipelined); | |
e47c68e9 EA |
50 | static void i915_gem_object_flush_gtt_write_domain(struct drm_gem_object *obj); |
51 | static void i915_gem_object_flush_cpu_write_domain(struct drm_gem_object *obj); | |
e47c68e9 EA |
52 | static int i915_gem_object_set_to_cpu_domain(struct drm_gem_object *obj, |
53 | int write); | |
54 | static int i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object *obj, | |
55 | uint64_t offset, | |
56 | uint64_t size); | |
57 | static void i915_gem_object_set_to_full_cpu_read_domain(struct drm_gem_object *obj); | |
2cf34d7b CW |
58 | static int i915_gem_object_wait_rendering(struct drm_gem_object *obj, |
59 | bool interruptible); | |
de151cf6 | 60 | static int i915_gem_object_bind_to_gtt(struct drm_gem_object *obj, |
a00b10c3 CW |
61 | unsigned alignment, |
62 | bool mappable, | |
63 | bool need_fence); | |
de151cf6 | 64 | static void i915_gem_clear_fence_reg(struct drm_gem_object *obj); |
71acb5eb DA |
65 | static int i915_gem_phys_pwrite(struct drm_device *dev, struct drm_gem_object *obj, |
66 | struct drm_i915_gem_pwrite *args, | |
67 | struct drm_file *file_priv); | |
be72615b | 68 | static void i915_gem_free_object_tail(struct drm_gem_object *obj); |
673a394b | 69 | |
17250b71 CW |
70 | static int i915_gem_inactive_shrink(struct shrinker *shrinker, |
71 | int nr_to_scan, | |
72 | gfp_t gfp_mask); | |
73 | ||
31169714 | 74 | |
73aa808f CW |
75 | /* some bookkeeping */ |
76 | static void i915_gem_info_add_obj(struct drm_i915_private *dev_priv, | |
77 | size_t size) | |
78 | { | |
79 | dev_priv->mm.object_count++; | |
80 | dev_priv->mm.object_memory += size; | |
81 | } | |
82 | ||
83 | static void i915_gem_info_remove_obj(struct drm_i915_private *dev_priv, | |
84 | size_t size) | |
85 | { | |
86 | dev_priv->mm.object_count--; | |
87 | dev_priv->mm.object_memory -= size; | |
88 | } | |
89 | ||
90 | static void i915_gem_info_add_gtt(struct drm_i915_private *dev_priv, | |
a00b10c3 | 91 | struct drm_i915_gem_object *obj) |
73aa808f CW |
92 | { |
93 | dev_priv->mm.gtt_count++; | |
a00b10c3 CW |
94 | dev_priv->mm.gtt_memory += obj->gtt_space->size; |
95 | if (obj->gtt_offset < dev_priv->mm.gtt_mappable_end) { | |
fb7d516a | 96 | dev_priv->mm.mappable_gtt_used += |
a00b10c3 CW |
97 | min_t(size_t, obj->gtt_space->size, |
98 | dev_priv->mm.gtt_mappable_end - obj->gtt_offset); | |
fb7d516a | 99 | } |
73aa808f CW |
100 | } |
101 | ||
102 | static void i915_gem_info_remove_gtt(struct drm_i915_private *dev_priv, | |
a00b10c3 | 103 | struct drm_i915_gem_object *obj) |
73aa808f CW |
104 | { |
105 | dev_priv->mm.gtt_count--; | |
a00b10c3 CW |
106 | dev_priv->mm.gtt_memory -= obj->gtt_space->size; |
107 | if (obj->gtt_offset < dev_priv->mm.gtt_mappable_end) { | |
fb7d516a | 108 | dev_priv->mm.mappable_gtt_used -= |
a00b10c3 CW |
109 | min_t(size_t, obj->gtt_space->size, |
110 | dev_priv->mm.gtt_mappable_end - obj->gtt_offset); | |
fb7d516a DV |
111 | } |
112 | } | |
113 | ||
114 | /** | |
115 | * Update the mappable working set counters. Call _only_ when there is a change | |
116 | * in one of (pin|fault)_mappable and update *_mappable _before_ calling. | |
117 | * @mappable: new state the changed mappable flag (either pin_ or fault_). | |
118 | */ | |
119 | static void | |
120 | i915_gem_info_update_mappable(struct drm_i915_private *dev_priv, | |
a00b10c3 | 121 | struct drm_i915_gem_object *obj, |
fb7d516a DV |
122 | bool mappable) |
123 | { | |
fb7d516a | 124 | if (mappable) { |
a00b10c3 | 125 | if (obj->pin_mappable && obj->fault_mappable) |
fb7d516a DV |
126 | /* Combined state was already mappable. */ |
127 | return; | |
128 | dev_priv->mm.gtt_mappable_count++; | |
a00b10c3 | 129 | dev_priv->mm.gtt_mappable_memory += obj->gtt_space->size; |
fb7d516a | 130 | } else { |
a00b10c3 | 131 | if (obj->pin_mappable || obj->fault_mappable) |
fb7d516a DV |
132 | /* Combined state still mappable. */ |
133 | return; | |
134 | dev_priv->mm.gtt_mappable_count--; | |
a00b10c3 | 135 | dev_priv->mm.gtt_mappable_memory -= obj->gtt_space->size; |
fb7d516a | 136 | } |
73aa808f CW |
137 | } |
138 | ||
139 | static void i915_gem_info_add_pin(struct drm_i915_private *dev_priv, | |
a00b10c3 | 140 | struct drm_i915_gem_object *obj, |
fb7d516a | 141 | bool mappable) |
73aa808f CW |
142 | { |
143 | dev_priv->mm.pin_count++; | |
a00b10c3 | 144 | dev_priv->mm.pin_memory += obj->gtt_space->size; |
fb7d516a | 145 | if (mappable) { |
a00b10c3 | 146 | obj->pin_mappable = true; |
fb7d516a DV |
147 | i915_gem_info_update_mappable(dev_priv, obj, true); |
148 | } | |
73aa808f CW |
149 | } |
150 | ||
151 | static void i915_gem_info_remove_pin(struct drm_i915_private *dev_priv, | |
a00b10c3 | 152 | struct drm_i915_gem_object *obj) |
73aa808f CW |
153 | { |
154 | dev_priv->mm.pin_count--; | |
a00b10c3 CW |
155 | dev_priv->mm.pin_memory -= obj->gtt_space->size; |
156 | if (obj->pin_mappable) { | |
157 | obj->pin_mappable = false; | |
fb7d516a DV |
158 | i915_gem_info_update_mappable(dev_priv, obj, false); |
159 | } | |
73aa808f CW |
160 | } |
161 | ||
30dbf0c0 CW |
162 | int |
163 | i915_gem_check_is_wedged(struct drm_device *dev) | |
164 | { | |
165 | struct drm_i915_private *dev_priv = dev->dev_private; | |
166 | struct completion *x = &dev_priv->error_completion; | |
167 | unsigned long flags; | |
168 | int ret; | |
169 | ||
170 | if (!atomic_read(&dev_priv->mm.wedged)) | |
171 | return 0; | |
172 | ||
173 | ret = wait_for_completion_interruptible(x); | |
174 | if (ret) | |
175 | return ret; | |
176 | ||
177 | /* Success, we reset the GPU! */ | |
178 | if (!atomic_read(&dev_priv->mm.wedged)) | |
179 | return 0; | |
180 | ||
181 | /* GPU is hung, bump the completion count to account for | |
182 | * the token we just consumed so that we never hit zero and | |
183 | * end up waiting upon a subsequent completion event that | |
184 | * will never happen. | |
185 | */ | |
186 | spin_lock_irqsave(&x->wait.lock, flags); | |
187 | x->done++; | |
188 | spin_unlock_irqrestore(&x->wait.lock, flags); | |
189 | return -EIO; | |
190 | } | |
191 | ||
76c1dec1 CW |
192 | static int i915_mutex_lock_interruptible(struct drm_device *dev) |
193 | { | |
194 | struct drm_i915_private *dev_priv = dev->dev_private; | |
195 | int ret; | |
196 | ||
197 | ret = i915_gem_check_is_wedged(dev); | |
198 | if (ret) | |
199 | return ret; | |
200 | ||
201 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
202 | if (ret) | |
203 | return ret; | |
204 | ||
205 | if (atomic_read(&dev_priv->mm.wedged)) { | |
206 | mutex_unlock(&dev->struct_mutex); | |
207 | return -EAGAIN; | |
208 | } | |
209 | ||
23bc5982 | 210 | WARN_ON(i915_verify_lists(dev)); |
76c1dec1 CW |
211 | return 0; |
212 | } | |
30dbf0c0 | 213 | |
7d1c4804 CW |
214 | static inline bool |
215 | i915_gem_object_is_inactive(struct drm_i915_gem_object *obj_priv) | |
216 | { | |
217 | return obj_priv->gtt_space && | |
218 | !obj_priv->active && | |
219 | obj_priv->pin_count == 0; | |
220 | } | |
221 | ||
73aa808f CW |
222 | int i915_gem_do_init(struct drm_device *dev, |
223 | unsigned long start, | |
53984635 | 224 | unsigned long mappable_end, |
79e53945 | 225 | unsigned long end) |
673a394b EA |
226 | { |
227 | drm_i915_private_t *dev_priv = dev->dev_private; | |
673a394b | 228 | |
79e53945 JB |
229 | if (start >= end || |
230 | (start & (PAGE_SIZE - 1)) != 0 || | |
231 | (end & (PAGE_SIZE - 1)) != 0) { | |
673a394b EA |
232 | return -EINVAL; |
233 | } | |
234 | ||
79e53945 JB |
235 | drm_mm_init(&dev_priv->mm.gtt_space, start, |
236 | end - start); | |
673a394b | 237 | |
73aa808f | 238 | dev_priv->mm.gtt_total = end - start; |
fb7d516a | 239 | dev_priv->mm.mappable_gtt_total = min(end, mappable_end) - start; |
53984635 | 240 | dev_priv->mm.gtt_mappable_end = mappable_end; |
79e53945 JB |
241 | |
242 | return 0; | |
243 | } | |
673a394b | 244 | |
79e53945 JB |
245 | int |
246 | i915_gem_init_ioctl(struct drm_device *dev, void *data, | |
247 | struct drm_file *file_priv) | |
248 | { | |
249 | struct drm_i915_gem_init *args = data; | |
250 | int ret; | |
251 | ||
252 | mutex_lock(&dev->struct_mutex); | |
53984635 | 253 | ret = i915_gem_do_init(dev, args->gtt_start, args->gtt_end, args->gtt_end); |
673a394b EA |
254 | mutex_unlock(&dev->struct_mutex); |
255 | ||
79e53945 | 256 | return ret; |
673a394b EA |
257 | } |
258 | ||
5a125c3c EA |
259 | int |
260 | i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data, | |
261 | struct drm_file *file_priv) | |
262 | { | |
73aa808f | 263 | struct drm_i915_private *dev_priv = dev->dev_private; |
5a125c3c | 264 | struct drm_i915_gem_get_aperture *args = data; |
5a125c3c EA |
265 | |
266 | if (!(dev->driver->driver_features & DRIVER_GEM)) | |
267 | return -ENODEV; | |
268 | ||
73aa808f CW |
269 | mutex_lock(&dev->struct_mutex); |
270 | args->aper_size = dev_priv->mm.gtt_total; | |
271 | args->aper_available_size = args->aper_size - dev_priv->mm.pin_memory; | |
272 | mutex_unlock(&dev->struct_mutex); | |
5a125c3c EA |
273 | |
274 | return 0; | |
275 | } | |
276 | ||
673a394b EA |
277 | |
278 | /** | |
279 | * Creates a new mm object and returns a handle to it. | |
280 | */ | |
281 | int | |
282 | i915_gem_create_ioctl(struct drm_device *dev, void *data, | |
283 | struct drm_file *file_priv) | |
284 | { | |
285 | struct drm_i915_gem_create *args = data; | |
286 | struct drm_gem_object *obj; | |
a1a2d1d3 PP |
287 | int ret; |
288 | u32 handle; | |
673a394b EA |
289 | |
290 | args->size = roundup(args->size, PAGE_SIZE); | |
291 | ||
292 | /* Allocate the new object */ | |
ac52bc56 | 293 | obj = i915_gem_alloc_object(dev, args->size); |
673a394b EA |
294 | if (obj == NULL) |
295 | return -ENOMEM; | |
296 | ||
297 | ret = drm_gem_handle_create(file_priv, obj, &handle); | |
1dfd9754 | 298 | if (ret) { |
202f2fef CW |
299 | drm_gem_object_release(obj); |
300 | i915_gem_info_remove_obj(dev->dev_private, obj->size); | |
301 | kfree(obj); | |
673a394b | 302 | return ret; |
1dfd9754 | 303 | } |
673a394b | 304 | |
202f2fef CW |
305 | /* drop reference from allocate - handle holds it now */ |
306 | drm_gem_object_unreference(obj); | |
307 | trace_i915_gem_object_create(obj); | |
308 | ||
1dfd9754 | 309 | args->handle = handle; |
673a394b EA |
310 | return 0; |
311 | } | |
312 | ||
280b713b EA |
313 | static int i915_gem_object_needs_bit17_swizzle(struct drm_gem_object *obj) |
314 | { | |
315 | drm_i915_private_t *dev_priv = obj->dev->dev_private; | |
23010e43 | 316 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
280b713b EA |
317 | |
318 | return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 && | |
319 | obj_priv->tiling_mode != I915_TILING_NONE; | |
320 | } | |
321 | ||
99a03df5 | 322 | static inline void |
40123c1f EA |
323 | slow_shmem_copy(struct page *dst_page, |
324 | int dst_offset, | |
325 | struct page *src_page, | |
326 | int src_offset, | |
327 | int length) | |
328 | { | |
329 | char *dst_vaddr, *src_vaddr; | |
330 | ||
99a03df5 CW |
331 | dst_vaddr = kmap(dst_page); |
332 | src_vaddr = kmap(src_page); | |
40123c1f EA |
333 | |
334 | memcpy(dst_vaddr + dst_offset, src_vaddr + src_offset, length); | |
335 | ||
99a03df5 CW |
336 | kunmap(src_page); |
337 | kunmap(dst_page); | |
40123c1f EA |
338 | } |
339 | ||
99a03df5 | 340 | static inline void |
280b713b EA |
341 | slow_shmem_bit17_copy(struct page *gpu_page, |
342 | int gpu_offset, | |
343 | struct page *cpu_page, | |
344 | int cpu_offset, | |
345 | int length, | |
346 | int is_read) | |
347 | { | |
348 | char *gpu_vaddr, *cpu_vaddr; | |
349 | ||
350 | /* Use the unswizzled path if this page isn't affected. */ | |
351 | if ((page_to_phys(gpu_page) & (1 << 17)) == 0) { | |
352 | if (is_read) | |
353 | return slow_shmem_copy(cpu_page, cpu_offset, | |
354 | gpu_page, gpu_offset, length); | |
355 | else | |
356 | return slow_shmem_copy(gpu_page, gpu_offset, | |
357 | cpu_page, cpu_offset, length); | |
358 | } | |
359 | ||
99a03df5 CW |
360 | gpu_vaddr = kmap(gpu_page); |
361 | cpu_vaddr = kmap(cpu_page); | |
280b713b EA |
362 | |
363 | /* Copy the data, XORing A6 with A17 (1). The user already knows he's | |
364 | * XORing with the other bits (A9 for Y, A9 and A10 for X) | |
365 | */ | |
366 | while (length > 0) { | |
367 | int cacheline_end = ALIGN(gpu_offset + 1, 64); | |
368 | int this_length = min(cacheline_end - gpu_offset, length); | |
369 | int swizzled_gpu_offset = gpu_offset ^ 64; | |
370 | ||
371 | if (is_read) { | |
372 | memcpy(cpu_vaddr + cpu_offset, | |
373 | gpu_vaddr + swizzled_gpu_offset, | |
374 | this_length); | |
375 | } else { | |
376 | memcpy(gpu_vaddr + swizzled_gpu_offset, | |
377 | cpu_vaddr + cpu_offset, | |
378 | this_length); | |
379 | } | |
380 | cpu_offset += this_length; | |
381 | gpu_offset += this_length; | |
382 | length -= this_length; | |
383 | } | |
384 | ||
99a03df5 CW |
385 | kunmap(cpu_page); |
386 | kunmap(gpu_page); | |
280b713b EA |
387 | } |
388 | ||
eb01459f EA |
389 | /** |
390 | * This is the fast shmem pread path, which attempts to copy_from_user directly | |
391 | * from the backing pages of the object to the user's address space. On a | |
392 | * fault, it fails so we can fall back to i915_gem_shmem_pwrite_slow(). | |
393 | */ | |
394 | static int | |
395 | i915_gem_shmem_pread_fast(struct drm_device *dev, struct drm_gem_object *obj, | |
396 | struct drm_i915_gem_pread *args, | |
397 | struct drm_file *file_priv) | |
398 | { | |
23010e43 | 399 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
e5281ccd | 400 | struct address_space *mapping = obj->filp->f_path.dentry->d_inode->i_mapping; |
eb01459f | 401 | ssize_t remain; |
e5281ccd | 402 | loff_t offset; |
eb01459f EA |
403 | char __user *user_data; |
404 | int page_offset, page_length; | |
eb01459f EA |
405 | |
406 | user_data = (char __user *) (uintptr_t) args->data_ptr; | |
407 | remain = args->size; | |
408 | ||
23010e43 | 409 | obj_priv = to_intel_bo(obj); |
eb01459f EA |
410 | offset = args->offset; |
411 | ||
412 | while (remain > 0) { | |
e5281ccd CW |
413 | struct page *page; |
414 | char *vaddr; | |
415 | int ret; | |
416 | ||
eb01459f EA |
417 | /* Operation in this page |
418 | * | |
eb01459f EA |
419 | * page_offset = offset within page |
420 | * page_length = bytes to copy for this page | |
421 | */ | |
eb01459f EA |
422 | page_offset = offset & (PAGE_SIZE-1); |
423 | page_length = remain; | |
424 | if ((page_offset + remain) > PAGE_SIZE) | |
425 | page_length = PAGE_SIZE - page_offset; | |
426 | ||
e5281ccd CW |
427 | page = read_cache_page_gfp(mapping, offset >> PAGE_SHIFT, |
428 | GFP_HIGHUSER | __GFP_RECLAIMABLE); | |
429 | if (IS_ERR(page)) | |
430 | return PTR_ERR(page); | |
431 | ||
432 | vaddr = kmap_atomic(page); | |
433 | ret = __copy_to_user_inatomic(user_data, | |
434 | vaddr + page_offset, | |
435 | page_length); | |
436 | kunmap_atomic(vaddr); | |
437 | ||
438 | mark_page_accessed(page); | |
439 | page_cache_release(page); | |
440 | if (ret) | |
4f27b75d | 441 | return -EFAULT; |
eb01459f EA |
442 | |
443 | remain -= page_length; | |
444 | user_data += page_length; | |
445 | offset += page_length; | |
446 | } | |
447 | ||
4f27b75d | 448 | return 0; |
eb01459f EA |
449 | } |
450 | ||
451 | /** | |
452 | * This is the fallback shmem pread path, which allocates temporary storage | |
453 | * in kernel space to copy_to_user into outside of the struct_mutex, so we | |
454 | * can copy out of the object's backing pages while holding the struct mutex | |
455 | * and not take page faults. | |
456 | */ | |
457 | static int | |
458 | i915_gem_shmem_pread_slow(struct drm_device *dev, struct drm_gem_object *obj, | |
459 | struct drm_i915_gem_pread *args, | |
460 | struct drm_file *file_priv) | |
461 | { | |
e5281ccd | 462 | struct address_space *mapping = obj->filp->f_path.dentry->d_inode->i_mapping; |
23010e43 | 463 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
eb01459f EA |
464 | struct mm_struct *mm = current->mm; |
465 | struct page **user_pages; | |
466 | ssize_t remain; | |
467 | loff_t offset, pinned_pages, i; | |
468 | loff_t first_data_page, last_data_page, num_pages; | |
e5281ccd CW |
469 | int shmem_page_offset; |
470 | int data_page_index, data_page_offset; | |
eb01459f EA |
471 | int page_length; |
472 | int ret; | |
473 | uint64_t data_ptr = args->data_ptr; | |
280b713b | 474 | int do_bit17_swizzling; |
eb01459f EA |
475 | |
476 | remain = args->size; | |
477 | ||
478 | /* Pin the user pages containing the data. We can't fault while | |
479 | * holding the struct mutex, yet we want to hold it while | |
480 | * dereferencing the user data. | |
481 | */ | |
482 | first_data_page = data_ptr / PAGE_SIZE; | |
483 | last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE; | |
484 | num_pages = last_data_page - first_data_page + 1; | |
485 | ||
4f27b75d | 486 | user_pages = drm_malloc_ab(num_pages, sizeof(struct page *)); |
eb01459f EA |
487 | if (user_pages == NULL) |
488 | return -ENOMEM; | |
489 | ||
4f27b75d | 490 | mutex_unlock(&dev->struct_mutex); |
eb01459f EA |
491 | down_read(&mm->mmap_sem); |
492 | pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr, | |
e5e9ecde | 493 | num_pages, 1, 0, user_pages, NULL); |
eb01459f | 494 | up_read(&mm->mmap_sem); |
4f27b75d | 495 | mutex_lock(&dev->struct_mutex); |
eb01459f EA |
496 | if (pinned_pages < num_pages) { |
497 | ret = -EFAULT; | |
4f27b75d | 498 | goto out; |
eb01459f EA |
499 | } |
500 | ||
4f27b75d CW |
501 | ret = i915_gem_object_set_cpu_read_domain_range(obj, |
502 | args->offset, | |
503 | args->size); | |
07f73f69 | 504 | if (ret) |
4f27b75d | 505 | goto out; |
eb01459f | 506 | |
4f27b75d | 507 | do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj); |
eb01459f | 508 | |
23010e43 | 509 | obj_priv = to_intel_bo(obj); |
eb01459f EA |
510 | offset = args->offset; |
511 | ||
512 | while (remain > 0) { | |
e5281ccd CW |
513 | struct page *page; |
514 | ||
eb01459f EA |
515 | /* Operation in this page |
516 | * | |
eb01459f EA |
517 | * shmem_page_offset = offset within page in shmem file |
518 | * data_page_index = page number in get_user_pages return | |
519 | * data_page_offset = offset with data_page_index page. | |
520 | * page_length = bytes to copy for this page | |
521 | */ | |
eb01459f EA |
522 | shmem_page_offset = offset & ~PAGE_MASK; |
523 | data_page_index = data_ptr / PAGE_SIZE - first_data_page; | |
524 | data_page_offset = data_ptr & ~PAGE_MASK; | |
525 | ||
526 | page_length = remain; | |
527 | if ((shmem_page_offset + page_length) > PAGE_SIZE) | |
528 | page_length = PAGE_SIZE - shmem_page_offset; | |
529 | if ((data_page_offset + page_length) > PAGE_SIZE) | |
530 | page_length = PAGE_SIZE - data_page_offset; | |
531 | ||
e5281ccd CW |
532 | page = read_cache_page_gfp(mapping, offset >> PAGE_SHIFT, |
533 | GFP_HIGHUSER | __GFP_RECLAIMABLE); | |
534 | if (IS_ERR(page)) | |
535 | return PTR_ERR(page); | |
536 | ||
280b713b | 537 | if (do_bit17_swizzling) { |
e5281ccd | 538 | slow_shmem_bit17_copy(page, |
280b713b | 539 | shmem_page_offset, |
99a03df5 CW |
540 | user_pages[data_page_index], |
541 | data_page_offset, | |
542 | page_length, | |
543 | 1); | |
544 | } else { | |
545 | slow_shmem_copy(user_pages[data_page_index], | |
546 | data_page_offset, | |
e5281ccd | 547 | page, |
99a03df5 CW |
548 | shmem_page_offset, |
549 | page_length); | |
280b713b | 550 | } |
eb01459f | 551 | |
e5281ccd CW |
552 | mark_page_accessed(page); |
553 | page_cache_release(page); | |
554 | ||
eb01459f EA |
555 | remain -= page_length; |
556 | data_ptr += page_length; | |
557 | offset += page_length; | |
558 | } | |
559 | ||
4f27b75d | 560 | out: |
eb01459f EA |
561 | for (i = 0; i < pinned_pages; i++) { |
562 | SetPageDirty(user_pages[i]); | |
e5281ccd | 563 | mark_page_accessed(user_pages[i]); |
eb01459f EA |
564 | page_cache_release(user_pages[i]); |
565 | } | |
8e7d2b2c | 566 | drm_free_large(user_pages); |
eb01459f EA |
567 | |
568 | return ret; | |
569 | } | |
570 | ||
673a394b EA |
571 | /** |
572 | * Reads data from the object referenced by handle. | |
573 | * | |
574 | * On error, the contents of *data are undefined. | |
575 | */ | |
576 | int | |
577 | i915_gem_pread_ioctl(struct drm_device *dev, void *data, | |
578 | struct drm_file *file_priv) | |
579 | { | |
580 | struct drm_i915_gem_pread *args = data; | |
581 | struct drm_gem_object *obj; | |
582 | struct drm_i915_gem_object *obj_priv; | |
35b62a89 | 583 | int ret = 0; |
673a394b | 584 | |
4f27b75d | 585 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 586 | if (ret) |
4f27b75d | 587 | return ret; |
673a394b EA |
588 | |
589 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); | |
1d7cfea1 CW |
590 | if (obj == NULL) { |
591 | ret = -ENOENT; | |
592 | goto unlock; | |
4f27b75d | 593 | } |
23010e43 | 594 | obj_priv = to_intel_bo(obj); |
673a394b | 595 | |
7dcd2499 CW |
596 | /* Bounds check source. */ |
597 | if (args->offset > obj->size || args->size > obj->size - args->offset) { | |
ce9d419d | 598 | ret = -EINVAL; |
35b62a89 | 599 | goto out; |
ce9d419d CW |
600 | } |
601 | ||
35b62a89 CW |
602 | if (args->size == 0) |
603 | goto out; | |
604 | ||
ce9d419d CW |
605 | if (!access_ok(VERIFY_WRITE, |
606 | (char __user *)(uintptr_t)args->data_ptr, | |
607 | args->size)) { | |
608 | ret = -EFAULT; | |
35b62a89 | 609 | goto out; |
673a394b EA |
610 | } |
611 | ||
b5e4feb6 CW |
612 | ret = fault_in_pages_writeable((char __user *)(uintptr_t)args->data_ptr, |
613 | args->size); | |
614 | if (ret) { | |
615 | ret = -EFAULT; | |
616 | goto out; | |
280b713b | 617 | } |
673a394b | 618 | |
4f27b75d CW |
619 | ret = i915_gem_object_set_cpu_read_domain_range(obj, |
620 | args->offset, | |
621 | args->size); | |
622 | if (ret) | |
e5281ccd | 623 | goto out; |
4f27b75d CW |
624 | |
625 | ret = -EFAULT; | |
626 | if (!i915_gem_object_needs_bit17_swizzle(obj)) | |
280b713b | 627 | ret = i915_gem_shmem_pread_fast(dev, obj, args, file_priv); |
4f27b75d CW |
628 | if (ret == -EFAULT) |
629 | ret = i915_gem_shmem_pread_slow(dev, obj, args, file_priv); | |
673a394b | 630 | |
35b62a89 | 631 | out: |
4f27b75d | 632 | drm_gem_object_unreference(obj); |
1d7cfea1 | 633 | unlock: |
4f27b75d | 634 | mutex_unlock(&dev->struct_mutex); |
eb01459f | 635 | return ret; |
673a394b EA |
636 | } |
637 | ||
0839ccb8 KP |
638 | /* This is the fast write path which cannot handle |
639 | * page faults in the source data | |
9b7530cc | 640 | */ |
0839ccb8 KP |
641 | |
642 | static inline int | |
643 | fast_user_write(struct io_mapping *mapping, | |
644 | loff_t page_base, int page_offset, | |
645 | char __user *user_data, | |
646 | int length) | |
9b7530cc | 647 | { |
9b7530cc | 648 | char *vaddr_atomic; |
0839ccb8 | 649 | unsigned long unwritten; |
9b7530cc | 650 | |
3e4d3af5 | 651 | vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base); |
0839ccb8 KP |
652 | unwritten = __copy_from_user_inatomic_nocache(vaddr_atomic + page_offset, |
653 | user_data, length); | |
3e4d3af5 | 654 | io_mapping_unmap_atomic(vaddr_atomic); |
fbd5a26d | 655 | return unwritten; |
0839ccb8 KP |
656 | } |
657 | ||
658 | /* Here's the write path which can sleep for | |
659 | * page faults | |
660 | */ | |
661 | ||
ab34c226 | 662 | static inline void |
3de09aa3 EA |
663 | slow_kernel_write(struct io_mapping *mapping, |
664 | loff_t gtt_base, int gtt_offset, | |
665 | struct page *user_page, int user_offset, | |
666 | int length) | |
0839ccb8 | 667 | { |
ab34c226 CW |
668 | char __iomem *dst_vaddr; |
669 | char *src_vaddr; | |
0839ccb8 | 670 | |
ab34c226 CW |
671 | dst_vaddr = io_mapping_map_wc(mapping, gtt_base); |
672 | src_vaddr = kmap(user_page); | |
673 | ||
674 | memcpy_toio(dst_vaddr + gtt_offset, | |
675 | src_vaddr + user_offset, | |
676 | length); | |
677 | ||
678 | kunmap(user_page); | |
679 | io_mapping_unmap(dst_vaddr); | |
9b7530cc LT |
680 | } |
681 | ||
3de09aa3 EA |
682 | /** |
683 | * This is the fast pwrite path, where we copy the data directly from the | |
684 | * user into the GTT, uncached. | |
685 | */ | |
673a394b | 686 | static int |
3de09aa3 EA |
687 | i915_gem_gtt_pwrite_fast(struct drm_device *dev, struct drm_gem_object *obj, |
688 | struct drm_i915_gem_pwrite *args, | |
689 | struct drm_file *file_priv) | |
673a394b | 690 | { |
23010e43 | 691 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
0839ccb8 | 692 | drm_i915_private_t *dev_priv = dev->dev_private; |
673a394b | 693 | ssize_t remain; |
0839ccb8 | 694 | loff_t offset, page_base; |
673a394b | 695 | char __user *user_data; |
0839ccb8 | 696 | int page_offset, page_length; |
673a394b EA |
697 | |
698 | user_data = (char __user *) (uintptr_t) args->data_ptr; | |
699 | remain = args->size; | |
673a394b | 700 | |
23010e43 | 701 | obj_priv = to_intel_bo(obj); |
673a394b | 702 | offset = obj_priv->gtt_offset + args->offset; |
673a394b EA |
703 | |
704 | while (remain > 0) { | |
705 | /* Operation in this page | |
706 | * | |
0839ccb8 KP |
707 | * page_base = page offset within aperture |
708 | * page_offset = offset within page | |
709 | * page_length = bytes to copy for this page | |
673a394b | 710 | */ |
0839ccb8 KP |
711 | page_base = (offset & ~(PAGE_SIZE-1)); |
712 | page_offset = offset & (PAGE_SIZE-1); | |
713 | page_length = remain; | |
714 | if ((page_offset + remain) > PAGE_SIZE) | |
715 | page_length = PAGE_SIZE - page_offset; | |
716 | ||
0839ccb8 | 717 | /* If we get a fault while copying data, then (presumably) our |
3de09aa3 EA |
718 | * source page isn't available. Return the error and we'll |
719 | * retry in the slow path. | |
0839ccb8 | 720 | */ |
fbd5a26d CW |
721 | if (fast_user_write(dev_priv->mm.gtt_mapping, page_base, |
722 | page_offset, user_data, page_length)) | |
723 | ||
724 | return -EFAULT; | |
673a394b | 725 | |
0839ccb8 KP |
726 | remain -= page_length; |
727 | user_data += page_length; | |
728 | offset += page_length; | |
673a394b | 729 | } |
673a394b | 730 | |
fbd5a26d | 731 | return 0; |
673a394b EA |
732 | } |
733 | ||
3de09aa3 EA |
734 | /** |
735 | * This is the fallback GTT pwrite path, which uses get_user_pages to pin | |
736 | * the memory and maps it using kmap_atomic for copying. | |
737 | * | |
738 | * This code resulted in x11perf -rgb10text consuming about 10% more CPU | |
739 | * than using i915_gem_gtt_pwrite_fast on a G45 (32-bit). | |
740 | */ | |
3043c60c | 741 | static int |
3de09aa3 EA |
742 | i915_gem_gtt_pwrite_slow(struct drm_device *dev, struct drm_gem_object *obj, |
743 | struct drm_i915_gem_pwrite *args, | |
744 | struct drm_file *file_priv) | |
673a394b | 745 | { |
23010e43 | 746 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
3de09aa3 EA |
747 | drm_i915_private_t *dev_priv = dev->dev_private; |
748 | ssize_t remain; | |
749 | loff_t gtt_page_base, offset; | |
750 | loff_t first_data_page, last_data_page, num_pages; | |
751 | loff_t pinned_pages, i; | |
752 | struct page **user_pages; | |
753 | struct mm_struct *mm = current->mm; | |
754 | int gtt_page_offset, data_page_offset, data_page_index, page_length; | |
673a394b | 755 | int ret; |
3de09aa3 EA |
756 | uint64_t data_ptr = args->data_ptr; |
757 | ||
758 | remain = args->size; | |
759 | ||
760 | /* Pin the user pages containing the data. We can't fault while | |
761 | * holding the struct mutex, and all of the pwrite implementations | |
762 | * want to hold it while dereferencing the user data. | |
763 | */ | |
764 | first_data_page = data_ptr / PAGE_SIZE; | |
765 | last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE; | |
766 | num_pages = last_data_page - first_data_page + 1; | |
767 | ||
fbd5a26d | 768 | user_pages = drm_malloc_ab(num_pages, sizeof(struct page *)); |
3de09aa3 EA |
769 | if (user_pages == NULL) |
770 | return -ENOMEM; | |
771 | ||
fbd5a26d | 772 | mutex_unlock(&dev->struct_mutex); |
3de09aa3 EA |
773 | down_read(&mm->mmap_sem); |
774 | pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr, | |
775 | num_pages, 0, 0, user_pages, NULL); | |
776 | up_read(&mm->mmap_sem); | |
fbd5a26d | 777 | mutex_lock(&dev->struct_mutex); |
3de09aa3 EA |
778 | if (pinned_pages < num_pages) { |
779 | ret = -EFAULT; | |
780 | goto out_unpin_pages; | |
781 | } | |
673a394b | 782 | |
3de09aa3 EA |
783 | ret = i915_gem_object_set_to_gtt_domain(obj, 1); |
784 | if (ret) | |
fbd5a26d | 785 | goto out_unpin_pages; |
3de09aa3 | 786 | |
23010e43 | 787 | obj_priv = to_intel_bo(obj); |
3de09aa3 EA |
788 | offset = obj_priv->gtt_offset + args->offset; |
789 | ||
790 | while (remain > 0) { | |
791 | /* Operation in this page | |
792 | * | |
793 | * gtt_page_base = page offset within aperture | |
794 | * gtt_page_offset = offset within page in aperture | |
795 | * data_page_index = page number in get_user_pages return | |
796 | * data_page_offset = offset with data_page_index page. | |
797 | * page_length = bytes to copy for this page | |
798 | */ | |
799 | gtt_page_base = offset & PAGE_MASK; | |
800 | gtt_page_offset = offset & ~PAGE_MASK; | |
801 | data_page_index = data_ptr / PAGE_SIZE - first_data_page; | |
802 | data_page_offset = data_ptr & ~PAGE_MASK; | |
803 | ||
804 | page_length = remain; | |
805 | if ((gtt_page_offset + page_length) > PAGE_SIZE) | |
806 | page_length = PAGE_SIZE - gtt_page_offset; | |
807 | if ((data_page_offset + page_length) > PAGE_SIZE) | |
808 | page_length = PAGE_SIZE - data_page_offset; | |
809 | ||
ab34c226 CW |
810 | slow_kernel_write(dev_priv->mm.gtt_mapping, |
811 | gtt_page_base, gtt_page_offset, | |
812 | user_pages[data_page_index], | |
813 | data_page_offset, | |
814 | page_length); | |
3de09aa3 EA |
815 | |
816 | remain -= page_length; | |
817 | offset += page_length; | |
818 | data_ptr += page_length; | |
819 | } | |
820 | ||
3de09aa3 EA |
821 | out_unpin_pages: |
822 | for (i = 0; i < pinned_pages; i++) | |
823 | page_cache_release(user_pages[i]); | |
8e7d2b2c | 824 | drm_free_large(user_pages); |
3de09aa3 EA |
825 | |
826 | return ret; | |
827 | } | |
828 | ||
40123c1f EA |
829 | /** |
830 | * This is the fast shmem pwrite path, which attempts to directly | |
831 | * copy_from_user into the kmapped pages backing the object. | |
832 | */ | |
3043c60c | 833 | static int |
40123c1f EA |
834 | i915_gem_shmem_pwrite_fast(struct drm_device *dev, struct drm_gem_object *obj, |
835 | struct drm_i915_gem_pwrite *args, | |
836 | struct drm_file *file_priv) | |
673a394b | 837 | { |
e5281ccd | 838 | struct address_space *mapping = obj->filp->f_path.dentry->d_inode->i_mapping; |
23010e43 | 839 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
40123c1f | 840 | ssize_t remain; |
e5281ccd | 841 | loff_t offset; |
40123c1f EA |
842 | char __user *user_data; |
843 | int page_offset, page_length; | |
40123c1f EA |
844 | |
845 | user_data = (char __user *) (uintptr_t) args->data_ptr; | |
846 | remain = args->size; | |
673a394b | 847 | |
23010e43 | 848 | obj_priv = to_intel_bo(obj); |
40123c1f EA |
849 | offset = args->offset; |
850 | obj_priv->dirty = 1; | |
851 | ||
852 | while (remain > 0) { | |
e5281ccd CW |
853 | struct page *page; |
854 | char *vaddr; | |
855 | int ret; | |
856 | ||
40123c1f EA |
857 | /* Operation in this page |
858 | * | |
40123c1f EA |
859 | * page_offset = offset within page |
860 | * page_length = bytes to copy for this page | |
861 | */ | |
40123c1f EA |
862 | page_offset = offset & (PAGE_SIZE-1); |
863 | page_length = remain; | |
864 | if ((page_offset + remain) > PAGE_SIZE) | |
865 | page_length = PAGE_SIZE - page_offset; | |
866 | ||
e5281ccd CW |
867 | page = read_cache_page_gfp(mapping, offset >> PAGE_SHIFT, |
868 | GFP_HIGHUSER | __GFP_RECLAIMABLE); | |
869 | if (IS_ERR(page)) | |
870 | return PTR_ERR(page); | |
871 | ||
872 | vaddr = kmap_atomic(page, KM_USER0); | |
873 | ret = __copy_from_user_inatomic(vaddr + page_offset, | |
874 | user_data, | |
875 | page_length); | |
876 | kunmap_atomic(vaddr, KM_USER0); | |
877 | ||
878 | set_page_dirty(page); | |
879 | mark_page_accessed(page); | |
880 | page_cache_release(page); | |
881 | ||
882 | /* If we get a fault while copying data, then (presumably) our | |
883 | * source page isn't available. Return the error and we'll | |
884 | * retry in the slow path. | |
885 | */ | |
886 | if (ret) | |
fbd5a26d | 887 | return -EFAULT; |
40123c1f EA |
888 | |
889 | remain -= page_length; | |
890 | user_data += page_length; | |
891 | offset += page_length; | |
892 | } | |
893 | ||
fbd5a26d | 894 | return 0; |
40123c1f EA |
895 | } |
896 | ||
897 | /** | |
898 | * This is the fallback shmem pwrite path, which uses get_user_pages to pin | |
899 | * the memory and maps it using kmap_atomic for copying. | |
900 | * | |
901 | * This avoids taking mmap_sem for faulting on the user's address while the | |
902 | * struct_mutex is held. | |
903 | */ | |
904 | static int | |
905 | i915_gem_shmem_pwrite_slow(struct drm_device *dev, struct drm_gem_object *obj, | |
906 | struct drm_i915_gem_pwrite *args, | |
907 | struct drm_file *file_priv) | |
908 | { | |
e5281ccd | 909 | struct address_space *mapping = obj->filp->f_path.dentry->d_inode->i_mapping; |
23010e43 | 910 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
40123c1f EA |
911 | struct mm_struct *mm = current->mm; |
912 | struct page **user_pages; | |
913 | ssize_t remain; | |
914 | loff_t offset, pinned_pages, i; | |
915 | loff_t first_data_page, last_data_page, num_pages; | |
e5281ccd | 916 | int shmem_page_offset; |
40123c1f EA |
917 | int data_page_index, data_page_offset; |
918 | int page_length; | |
919 | int ret; | |
920 | uint64_t data_ptr = args->data_ptr; | |
280b713b | 921 | int do_bit17_swizzling; |
40123c1f EA |
922 | |
923 | remain = args->size; | |
924 | ||
925 | /* Pin the user pages containing the data. We can't fault while | |
926 | * holding the struct mutex, and all of the pwrite implementations | |
927 | * want to hold it while dereferencing the user data. | |
928 | */ | |
929 | first_data_page = data_ptr / PAGE_SIZE; | |
930 | last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE; | |
931 | num_pages = last_data_page - first_data_page + 1; | |
932 | ||
4f27b75d | 933 | user_pages = drm_malloc_ab(num_pages, sizeof(struct page *)); |
40123c1f EA |
934 | if (user_pages == NULL) |
935 | return -ENOMEM; | |
936 | ||
fbd5a26d | 937 | mutex_unlock(&dev->struct_mutex); |
40123c1f EA |
938 | down_read(&mm->mmap_sem); |
939 | pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr, | |
940 | num_pages, 0, 0, user_pages, NULL); | |
941 | up_read(&mm->mmap_sem); | |
fbd5a26d | 942 | mutex_lock(&dev->struct_mutex); |
40123c1f EA |
943 | if (pinned_pages < num_pages) { |
944 | ret = -EFAULT; | |
fbd5a26d | 945 | goto out; |
673a394b EA |
946 | } |
947 | ||
fbd5a26d | 948 | ret = i915_gem_object_set_to_cpu_domain(obj, 1); |
07f73f69 | 949 | if (ret) |
fbd5a26d | 950 | goto out; |
40123c1f | 951 | |
fbd5a26d | 952 | do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj); |
40123c1f | 953 | |
23010e43 | 954 | obj_priv = to_intel_bo(obj); |
673a394b | 955 | offset = args->offset; |
40123c1f | 956 | obj_priv->dirty = 1; |
673a394b | 957 | |
40123c1f | 958 | while (remain > 0) { |
e5281ccd CW |
959 | struct page *page; |
960 | ||
40123c1f EA |
961 | /* Operation in this page |
962 | * | |
40123c1f EA |
963 | * shmem_page_offset = offset within page in shmem file |
964 | * data_page_index = page number in get_user_pages return | |
965 | * data_page_offset = offset with data_page_index page. | |
966 | * page_length = bytes to copy for this page | |
967 | */ | |
40123c1f EA |
968 | shmem_page_offset = offset & ~PAGE_MASK; |
969 | data_page_index = data_ptr / PAGE_SIZE - first_data_page; | |
970 | data_page_offset = data_ptr & ~PAGE_MASK; | |
971 | ||
972 | page_length = remain; | |
973 | if ((shmem_page_offset + page_length) > PAGE_SIZE) | |
974 | page_length = PAGE_SIZE - shmem_page_offset; | |
975 | if ((data_page_offset + page_length) > PAGE_SIZE) | |
976 | page_length = PAGE_SIZE - data_page_offset; | |
977 | ||
e5281ccd CW |
978 | page = read_cache_page_gfp(mapping, offset >> PAGE_SHIFT, |
979 | GFP_HIGHUSER | __GFP_RECLAIMABLE); | |
980 | if (IS_ERR(page)) { | |
981 | ret = PTR_ERR(page); | |
982 | goto out; | |
983 | } | |
984 | ||
280b713b | 985 | if (do_bit17_swizzling) { |
e5281ccd | 986 | slow_shmem_bit17_copy(page, |
280b713b EA |
987 | shmem_page_offset, |
988 | user_pages[data_page_index], | |
989 | data_page_offset, | |
99a03df5 CW |
990 | page_length, |
991 | 0); | |
992 | } else { | |
e5281ccd | 993 | slow_shmem_copy(page, |
99a03df5 CW |
994 | shmem_page_offset, |
995 | user_pages[data_page_index], | |
996 | data_page_offset, | |
997 | page_length); | |
280b713b | 998 | } |
40123c1f | 999 | |
e5281ccd CW |
1000 | set_page_dirty(page); |
1001 | mark_page_accessed(page); | |
1002 | page_cache_release(page); | |
1003 | ||
40123c1f EA |
1004 | remain -= page_length; |
1005 | data_ptr += page_length; | |
1006 | offset += page_length; | |
673a394b EA |
1007 | } |
1008 | ||
fbd5a26d | 1009 | out: |
40123c1f EA |
1010 | for (i = 0; i < pinned_pages; i++) |
1011 | page_cache_release(user_pages[i]); | |
8e7d2b2c | 1012 | drm_free_large(user_pages); |
673a394b | 1013 | |
40123c1f | 1014 | return ret; |
673a394b EA |
1015 | } |
1016 | ||
1017 | /** | |
1018 | * Writes data to the object referenced by handle. | |
1019 | * | |
1020 | * On error, the contents of the buffer that were to be modified are undefined. | |
1021 | */ | |
1022 | int | |
1023 | i915_gem_pwrite_ioctl(struct drm_device *dev, void *data, | |
fbd5a26d | 1024 | struct drm_file *file) |
673a394b EA |
1025 | { |
1026 | struct drm_i915_gem_pwrite *args = data; | |
1027 | struct drm_gem_object *obj; | |
1028 | struct drm_i915_gem_object *obj_priv; | |
1029 | int ret = 0; | |
1030 | ||
fbd5a26d | 1031 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 1032 | if (ret) |
fbd5a26d | 1033 | return ret; |
1d7cfea1 CW |
1034 | |
1035 | obj = drm_gem_object_lookup(dev, file, args->handle); | |
1036 | if (obj == NULL) { | |
1037 | ret = -ENOENT; | |
1038 | goto unlock; | |
fbd5a26d | 1039 | } |
23010e43 | 1040 | obj_priv = to_intel_bo(obj); |
673a394b | 1041 | |
fbd5a26d | 1042 | |
7dcd2499 CW |
1043 | /* Bounds check destination. */ |
1044 | if (args->offset > obj->size || args->size > obj->size - args->offset) { | |
ce9d419d | 1045 | ret = -EINVAL; |
35b62a89 | 1046 | goto out; |
ce9d419d CW |
1047 | } |
1048 | ||
35b62a89 CW |
1049 | if (args->size == 0) |
1050 | goto out; | |
1051 | ||
ce9d419d CW |
1052 | if (!access_ok(VERIFY_READ, |
1053 | (char __user *)(uintptr_t)args->data_ptr, | |
1054 | args->size)) { | |
1055 | ret = -EFAULT; | |
35b62a89 | 1056 | goto out; |
673a394b EA |
1057 | } |
1058 | ||
b5e4feb6 CW |
1059 | ret = fault_in_pages_readable((char __user *)(uintptr_t)args->data_ptr, |
1060 | args->size); | |
1061 | if (ret) { | |
1062 | ret = -EFAULT; | |
1063 | goto out; | |
673a394b EA |
1064 | } |
1065 | ||
1066 | /* We can only do the GTT pwrite on untiled buffers, as otherwise | |
1067 | * it would end up going through the fenced access, and we'll get | |
1068 | * different detiling behavior between reading and writing. | |
1069 | * pread/pwrite currently are reading and writing from the CPU | |
1070 | * perspective, requiring manual detiling by the client. | |
1071 | */ | |
71acb5eb | 1072 | if (obj_priv->phys_obj) |
fbd5a26d | 1073 | ret = i915_gem_phys_pwrite(dev, obj, args, file); |
71acb5eb | 1074 | else if (obj_priv->tiling_mode == I915_TILING_NONE && |
5cdf5881 | 1075 | obj_priv->gtt_space && |
9b8c4a0b | 1076 | obj->write_domain != I915_GEM_DOMAIN_CPU) { |
a00b10c3 | 1077 | ret = i915_gem_object_pin(obj, 0, true, false); |
fbd5a26d CW |
1078 | if (ret) |
1079 | goto out; | |
1080 | ||
1081 | ret = i915_gem_object_set_to_gtt_domain(obj, 1); | |
1082 | if (ret) | |
1083 | goto out_unpin; | |
1084 | ||
1085 | ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file); | |
1086 | if (ret == -EFAULT) | |
1087 | ret = i915_gem_gtt_pwrite_slow(dev, obj, args, file); | |
1088 | ||
1089 | out_unpin: | |
1090 | i915_gem_object_unpin(obj); | |
40123c1f | 1091 | } else { |
fbd5a26d CW |
1092 | ret = i915_gem_object_set_to_cpu_domain(obj, 1); |
1093 | if (ret) | |
e5281ccd | 1094 | goto out; |
673a394b | 1095 | |
fbd5a26d CW |
1096 | ret = -EFAULT; |
1097 | if (!i915_gem_object_needs_bit17_swizzle(obj)) | |
1098 | ret = i915_gem_shmem_pwrite_fast(dev, obj, args, file); | |
1099 | if (ret == -EFAULT) | |
1100 | ret = i915_gem_shmem_pwrite_slow(dev, obj, args, file); | |
fbd5a26d | 1101 | } |
673a394b | 1102 | |
35b62a89 | 1103 | out: |
fbd5a26d | 1104 | drm_gem_object_unreference(obj); |
1d7cfea1 | 1105 | unlock: |
fbd5a26d | 1106 | mutex_unlock(&dev->struct_mutex); |
673a394b EA |
1107 | return ret; |
1108 | } | |
1109 | ||
1110 | /** | |
2ef7eeaa EA |
1111 | * Called when user space prepares to use an object with the CPU, either |
1112 | * through the mmap ioctl's mapping or a GTT mapping. | |
673a394b EA |
1113 | */ |
1114 | int | |
1115 | i915_gem_set_domain_ioctl(struct drm_device *dev, void *data, | |
1116 | struct drm_file *file_priv) | |
1117 | { | |
a09ba7fa | 1118 | struct drm_i915_private *dev_priv = dev->dev_private; |
673a394b EA |
1119 | struct drm_i915_gem_set_domain *args = data; |
1120 | struct drm_gem_object *obj; | |
652c393a | 1121 | struct drm_i915_gem_object *obj_priv; |
2ef7eeaa EA |
1122 | uint32_t read_domains = args->read_domains; |
1123 | uint32_t write_domain = args->write_domain; | |
673a394b EA |
1124 | int ret; |
1125 | ||
1126 | if (!(dev->driver->driver_features & DRIVER_GEM)) | |
1127 | return -ENODEV; | |
1128 | ||
2ef7eeaa | 1129 | /* Only handle setting domains to types used by the CPU. */ |
21d509e3 | 1130 | if (write_domain & I915_GEM_GPU_DOMAINS) |
2ef7eeaa EA |
1131 | return -EINVAL; |
1132 | ||
21d509e3 | 1133 | if (read_domains & I915_GEM_GPU_DOMAINS) |
2ef7eeaa EA |
1134 | return -EINVAL; |
1135 | ||
1136 | /* Having something in the write domain implies it's in the read | |
1137 | * domain, and only that read domain. Enforce that in the request. | |
1138 | */ | |
1139 | if (write_domain != 0 && read_domains != write_domain) | |
1140 | return -EINVAL; | |
1141 | ||
76c1dec1 | 1142 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 1143 | if (ret) |
76c1dec1 | 1144 | return ret; |
1d7cfea1 | 1145 | |
673a394b | 1146 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); |
1d7cfea1 CW |
1147 | if (obj == NULL) { |
1148 | ret = -ENOENT; | |
1149 | goto unlock; | |
76c1dec1 | 1150 | } |
23010e43 | 1151 | obj_priv = to_intel_bo(obj); |
673a394b | 1152 | |
652c393a JB |
1153 | intel_mark_busy(dev, obj); |
1154 | ||
2ef7eeaa EA |
1155 | if (read_domains & I915_GEM_DOMAIN_GTT) { |
1156 | ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0); | |
02354392 | 1157 | |
a09ba7fa EA |
1158 | /* Update the LRU on the fence for the CPU access that's |
1159 | * about to occur. | |
1160 | */ | |
1161 | if (obj_priv->fence_reg != I915_FENCE_REG_NONE) { | |
007cc8ac DV |
1162 | struct drm_i915_fence_reg *reg = |
1163 | &dev_priv->fence_regs[obj_priv->fence_reg]; | |
1164 | list_move_tail(®->lru_list, | |
a09ba7fa EA |
1165 | &dev_priv->mm.fence_list); |
1166 | } | |
1167 | ||
02354392 EA |
1168 | /* Silently promote "you're not bound, there was nothing to do" |
1169 | * to success, since the client was just asking us to | |
1170 | * make sure everything was done. | |
1171 | */ | |
1172 | if (ret == -EINVAL) | |
1173 | ret = 0; | |
2ef7eeaa | 1174 | } else { |
e47c68e9 | 1175 | ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0); |
2ef7eeaa EA |
1176 | } |
1177 | ||
7d1c4804 CW |
1178 | /* Maintain LRU order of "inactive" objects */ |
1179 | if (ret == 0 && i915_gem_object_is_inactive(obj_priv)) | |
69dc4987 | 1180 | list_move_tail(&obj_priv->mm_list, &dev_priv->mm.inactive_list); |
7d1c4804 | 1181 | |
673a394b | 1182 | drm_gem_object_unreference(obj); |
1d7cfea1 | 1183 | unlock: |
673a394b EA |
1184 | mutex_unlock(&dev->struct_mutex); |
1185 | return ret; | |
1186 | } | |
1187 | ||
1188 | /** | |
1189 | * Called when user space has done writes to this buffer | |
1190 | */ | |
1191 | int | |
1192 | i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data, | |
1193 | struct drm_file *file_priv) | |
1194 | { | |
1195 | struct drm_i915_gem_sw_finish *args = data; | |
1196 | struct drm_gem_object *obj; | |
673a394b EA |
1197 | int ret = 0; |
1198 | ||
1199 | if (!(dev->driver->driver_features & DRIVER_GEM)) | |
1200 | return -ENODEV; | |
1201 | ||
76c1dec1 | 1202 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 1203 | if (ret) |
76c1dec1 | 1204 | return ret; |
1d7cfea1 | 1205 | |
673a394b EA |
1206 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); |
1207 | if (obj == NULL) { | |
1d7cfea1 CW |
1208 | ret = -ENOENT; |
1209 | goto unlock; | |
673a394b EA |
1210 | } |
1211 | ||
673a394b | 1212 | /* Pinned buffers may be scanout, so flush the cache */ |
3d2a812a | 1213 | if (to_intel_bo(obj)->pin_count) |
e47c68e9 EA |
1214 | i915_gem_object_flush_cpu_write_domain(obj); |
1215 | ||
673a394b | 1216 | drm_gem_object_unreference(obj); |
1d7cfea1 | 1217 | unlock: |
673a394b EA |
1218 | mutex_unlock(&dev->struct_mutex); |
1219 | return ret; | |
1220 | } | |
1221 | ||
1222 | /** | |
1223 | * Maps the contents of an object, returning the address it is mapped | |
1224 | * into. | |
1225 | * | |
1226 | * While the mapping holds a reference on the contents of the object, it doesn't | |
1227 | * imply a ref on the object itself. | |
1228 | */ | |
1229 | int | |
1230 | i915_gem_mmap_ioctl(struct drm_device *dev, void *data, | |
1231 | struct drm_file *file_priv) | |
1232 | { | |
da761a6e | 1233 | struct drm_i915_private *dev_priv = dev->dev_private; |
673a394b EA |
1234 | struct drm_i915_gem_mmap *args = data; |
1235 | struct drm_gem_object *obj; | |
1236 | loff_t offset; | |
1237 | unsigned long addr; | |
1238 | ||
1239 | if (!(dev->driver->driver_features & DRIVER_GEM)) | |
1240 | return -ENODEV; | |
1241 | ||
1242 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); | |
1243 | if (obj == NULL) | |
bf79cb91 | 1244 | return -ENOENT; |
673a394b | 1245 | |
da761a6e CW |
1246 | if (obj->size > dev_priv->mm.gtt_mappable_end) { |
1247 | drm_gem_object_unreference_unlocked(obj); | |
1248 | return -E2BIG; | |
1249 | } | |
1250 | ||
673a394b EA |
1251 | offset = args->offset; |
1252 | ||
1253 | down_write(¤t->mm->mmap_sem); | |
1254 | addr = do_mmap(obj->filp, 0, args->size, | |
1255 | PROT_READ | PROT_WRITE, MAP_SHARED, | |
1256 | args->offset); | |
1257 | up_write(¤t->mm->mmap_sem); | |
bc9025bd | 1258 | drm_gem_object_unreference_unlocked(obj); |
673a394b EA |
1259 | if (IS_ERR((void *)addr)) |
1260 | return addr; | |
1261 | ||
1262 | args->addr_ptr = (uint64_t) addr; | |
1263 | ||
1264 | return 0; | |
1265 | } | |
1266 | ||
de151cf6 JB |
1267 | /** |
1268 | * i915_gem_fault - fault a page into the GTT | |
1269 | * vma: VMA in question | |
1270 | * vmf: fault info | |
1271 | * | |
1272 | * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped | |
1273 | * from userspace. The fault handler takes care of binding the object to | |
1274 | * the GTT (if needed), allocating and programming a fence register (again, | |
1275 | * only if needed based on whether the old reg is still valid or the object | |
1276 | * is tiled) and inserting a new PTE into the faulting process. | |
1277 | * | |
1278 | * Note that the faulting process may involve evicting existing objects | |
1279 | * from the GTT and/or fence registers to make room. So performance may | |
1280 | * suffer if the GTT working set is large or there are few fence registers | |
1281 | * left. | |
1282 | */ | |
1283 | int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf) | |
1284 | { | |
1285 | struct drm_gem_object *obj = vma->vm_private_data; | |
1286 | struct drm_device *dev = obj->dev; | |
7d1c4804 | 1287 | drm_i915_private_t *dev_priv = dev->dev_private; |
23010e43 | 1288 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
de151cf6 JB |
1289 | pgoff_t page_offset; |
1290 | unsigned long pfn; | |
1291 | int ret = 0; | |
0f973f27 | 1292 | bool write = !!(vmf->flags & FAULT_FLAG_WRITE); |
de151cf6 JB |
1293 | |
1294 | /* We don't use vmf->pgoff since that has the fake offset */ | |
1295 | page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >> | |
1296 | PAGE_SHIFT; | |
1297 | ||
1298 | /* Now bind it into the GTT if needed */ | |
1299 | mutex_lock(&dev->struct_mutex); | |
fb7d516a | 1300 | BUG_ON(obj_priv->pin_count && !obj_priv->pin_mappable); |
a00b10c3 CW |
1301 | |
1302 | if (obj_priv->gtt_space) { | |
1303 | if (!obj_priv->mappable || | |
1304 | (obj_priv->tiling_mode && !obj_priv->fenceable)) { | |
1305 | ret = i915_gem_object_unbind(obj); | |
1306 | if (ret) | |
1307 | goto unlock; | |
1308 | } | |
1309 | } | |
16e809ac | 1310 | |
de151cf6 | 1311 | if (!obj_priv->gtt_space) { |
a00b10c3 CW |
1312 | ret = i915_gem_object_bind_to_gtt(obj, 0, |
1313 | true, obj_priv->tiling_mode); | |
c715089f CW |
1314 | if (ret) |
1315 | goto unlock; | |
de151cf6 JB |
1316 | } |
1317 | ||
4a684a41 CW |
1318 | ret = i915_gem_object_set_to_gtt_domain(obj, write); |
1319 | if (ret) | |
1320 | goto unlock; | |
1321 | ||
fb7d516a DV |
1322 | if (!obj_priv->fault_mappable) { |
1323 | obj_priv->fault_mappable = true; | |
a00b10c3 | 1324 | i915_gem_info_update_mappable(dev_priv, obj_priv, true); |
fb7d516a DV |
1325 | } |
1326 | ||
de151cf6 | 1327 | /* Need a new fence register? */ |
a09ba7fa | 1328 | if (obj_priv->tiling_mode != I915_TILING_NONE) { |
2cf34d7b | 1329 | ret = i915_gem_object_get_fence_reg(obj, true); |
c715089f CW |
1330 | if (ret) |
1331 | goto unlock; | |
d9ddcb96 | 1332 | } |
de151cf6 | 1333 | |
7d1c4804 | 1334 | if (i915_gem_object_is_inactive(obj_priv)) |
69dc4987 | 1335 | list_move_tail(&obj_priv->mm_list, &dev_priv->mm.inactive_list); |
7d1c4804 | 1336 | |
de151cf6 JB |
1337 | pfn = ((dev->agp->base + obj_priv->gtt_offset) >> PAGE_SHIFT) + |
1338 | page_offset; | |
1339 | ||
1340 | /* Finally, remap it using the new GTT offset */ | |
1341 | ret = vm_insert_pfn(vma, (unsigned long)vmf->virtual_address, pfn); | |
c715089f | 1342 | unlock: |
de151cf6 JB |
1343 | mutex_unlock(&dev->struct_mutex); |
1344 | ||
1345 | switch (ret) { | |
c715089f CW |
1346 | case 0: |
1347 | case -ERESTARTSYS: | |
1348 | return VM_FAULT_NOPAGE; | |
de151cf6 JB |
1349 | case -ENOMEM: |
1350 | case -EAGAIN: | |
1351 | return VM_FAULT_OOM; | |
de151cf6 | 1352 | default: |
c715089f | 1353 | return VM_FAULT_SIGBUS; |
de151cf6 JB |
1354 | } |
1355 | } | |
1356 | ||
1357 | /** | |
1358 | * i915_gem_create_mmap_offset - create a fake mmap offset for an object | |
1359 | * @obj: obj in question | |
1360 | * | |
1361 | * GEM memory mapping works by handing back to userspace a fake mmap offset | |
1362 | * it can use in a subsequent mmap(2) call. The DRM core code then looks | |
1363 | * up the object based on the offset and sets up the various memory mapping | |
1364 | * structures. | |
1365 | * | |
1366 | * This routine allocates and attaches a fake offset for @obj. | |
1367 | */ | |
1368 | static int | |
1369 | i915_gem_create_mmap_offset(struct drm_gem_object *obj) | |
1370 | { | |
1371 | struct drm_device *dev = obj->dev; | |
1372 | struct drm_gem_mm *mm = dev->mm_private; | |
de151cf6 | 1373 | struct drm_map_list *list; |
f77d390c | 1374 | struct drm_local_map *map; |
de151cf6 JB |
1375 | int ret = 0; |
1376 | ||
1377 | /* Set the object up for mmap'ing */ | |
1378 | list = &obj->map_list; | |
9a298b2a | 1379 | list->map = kzalloc(sizeof(struct drm_map_list), GFP_KERNEL); |
de151cf6 JB |
1380 | if (!list->map) |
1381 | return -ENOMEM; | |
1382 | ||
1383 | map = list->map; | |
1384 | map->type = _DRM_GEM; | |
1385 | map->size = obj->size; | |
1386 | map->handle = obj; | |
1387 | ||
1388 | /* Get a DRM GEM mmap offset allocated... */ | |
1389 | list->file_offset_node = drm_mm_search_free(&mm->offset_manager, | |
1390 | obj->size / PAGE_SIZE, 0, 0); | |
1391 | if (!list->file_offset_node) { | |
1392 | DRM_ERROR("failed to allocate offset for bo %d\n", obj->name); | |
9e0ae534 | 1393 | ret = -ENOSPC; |
de151cf6 JB |
1394 | goto out_free_list; |
1395 | } | |
1396 | ||
1397 | list->file_offset_node = drm_mm_get_block(list->file_offset_node, | |
1398 | obj->size / PAGE_SIZE, 0); | |
1399 | if (!list->file_offset_node) { | |
1400 | ret = -ENOMEM; | |
1401 | goto out_free_list; | |
1402 | } | |
1403 | ||
1404 | list->hash.key = list->file_offset_node->start; | |
9e0ae534 CW |
1405 | ret = drm_ht_insert_item(&mm->offset_hash, &list->hash); |
1406 | if (ret) { | |
de151cf6 JB |
1407 | DRM_ERROR("failed to add to map hash\n"); |
1408 | goto out_free_mm; | |
1409 | } | |
1410 | ||
de151cf6 JB |
1411 | return 0; |
1412 | ||
1413 | out_free_mm: | |
1414 | drm_mm_put_block(list->file_offset_node); | |
1415 | out_free_list: | |
9a298b2a | 1416 | kfree(list->map); |
39a01d1f | 1417 | list->map = NULL; |
de151cf6 JB |
1418 | |
1419 | return ret; | |
1420 | } | |
1421 | ||
901782b2 CW |
1422 | /** |
1423 | * i915_gem_release_mmap - remove physical page mappings | |
1424 | * @obj: obj in question | |
1425 | * | |
af901ca1 | 1426 | * Preserve the reservation of the mmapping with the DRM core code, but |
901782b2 CW |
1427 | * relinquish ownership of the pages back to the system. |
1428 | * | |
1429 | * It is vital that we remove the page mapping if we have mapped a tiled | |
1430 | * object through the GTT and then lose the fence register due to | |
1431 | * resource pressure. Similarly if the object has been moved out of the | |
1432 | * aperture, than pages mapped into userspace must be revoked. Removing the | |
1433 | * mapping will then trigger a page fault on the next user access, allowing | |
1434 | * fixup by i915_gem_fault(). | |
1435 | */ | |
d05ca301 | 1436 | void |
901782b2 CW |
1437 | i915_gem_release_mmap(struct drm_gem_object *obj) |
1438 | { | |
1439 | struct drm_device *dev = obj->dev; | |
fb7d516a | 1440 | struct drm_i915_private *dev_priv = dev->dev_private; |
23010e43 | 1441 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
901782b2 | 1442 | |
39a01d1f | 1443 | if (unlikely(obj->map_list.map && dev->dev_mapping)) |
901782b2 | 1444 | unmap_mapping_range(dev->dev_mapping, |
39a01d1f CW |
1445 | (loff_t)obj->map_list.hash.key<<PAGE_SHIFT, |
1446 | obj->size, 1); | |
fb7d516a DV |
1447 | |
1448 | if (obj_priv->fault_mappable) { | |
1449 | obj_priv->fault_mappable = false; | |
a00b10c3 | 1450 | i915_gem_info_update_mappable(dev_priv, obj_priv, false); |
fb7d516a | 1451 | } |
901782b2 CW |
1452 | } |
1453 | ||
ab00b3e5 JB |
1454 | static void |
1455 | i915_gem_free_mmap_offset(struct drm_gem_object *obj) | |
1456 | { | |
1457 | struct drm_device *dev = obj->dev; | |
ab00b3e5 | 1458 | struct drm_gem_mm *mm = dev->mm_private; |
39a01d1f | 1459 | struct drm_map_list *list = &obj->map_list; |
ab00b3e5 | 1460 | |
ab00b3e5 | 1461 | drm_ht_remove_item(&mm->offset_hash, &list->hash); |
39a01d1f CW |
1462 | drm_mm_put_block(list->file_offset_node); |
1463 | kfree(list->map); | |
1464 | list->map = NULL; | |
ab00b3e5 JB |
1465 | } |
1466 | ||
de151cf6 JB |
1467 | /** |
1468 | * i915_gem_get_gtt_alignment - return required GTT alignment for an object | |
1469 | * @obj: object to check | |
1470 | * | |
1471 | * Return the required GTT alignment for an object, taking into account | |
1472 | * potential fence register mapping if needed. | |
1473 | */ | |
1474 | static uint32_t | |
a00b10c3 | 1475 | i915_gem_get_gtt_alignment(struct drm_i915_gem_object *obj_priv) |
de151cf6 | 1476 | { |
a00b10c3 | 1477 | struct drm_device *dev = obj_priv->base.dev; |
de151cf6 JB |
1478 | |
1479 | /* | |
1480 | * Minimum alignment is 4k (GTT page size), but might be greater | |
1481 | * if a fence register is needed for the object. | |
1482 | */ | |
a00b10c3 CW |
1483 | if (INTEL_INFO(dev)->gen >= 4 || |
1484 | obj_priv->tiling_mode == I915_TILING_NONE) | |
de151cf6 JB |
1485 | return 4096; |
1486 | ||
a00b10c3 CW |
1487 | /* |
1488 | * Previous chips need to be aligned to the size of the smallest | |
1489 | * fence register that can contain the object. | |
1490 | */ | |
1491 | return i915_gem_get_gtt_size(obj_priv); | |
1492 | } | |
1493 | ||
1494 | static uint32_t | |
1495 | i915_gem_get_gtt_size(struct drm_i915_gem_object *obj_priv) | |
1496 | { | |
1497 | struct drm_device *dev = obj_priv->base.dev; | |
1498 | uint32_t size; | |
1499 | ||
1500 | /* | |
1501 | * Minimum alignment is 4k (GTT page size), but might be greater | |
1502 | * if a fence register is needed for the object. | |
1503 | */ | |
1504 | if (INTEL_INFO(dev)->gen >= 4) | |
1505 | return obj_priv->base.size; | |
1506 | ||
de151cf6 JB |
1507 | /* |
1508 | * Previous chips need to be aligned to the size of the smallest | |
1509 | * fence register that can contain the object. | |
1510 | */ | |
a6c45cf0 | 1511 | if (INTEL_INFO(dev)->gen == 3) |
a00b10c3 | 1512 | size = 1024*1024; |
de151cf6 | 1513 | else |
a00b10c3 | 1514 | size = 512*1024; |
de151cf6 | 1515 | |
a00b10c3 CW |
1516 | while (size < obj_priv->base.size) |
1517 | size <<= 1; | |
de151cf6 | 1518 | |
a00b10c3 | 1519 | return size; |
de151cf6 JB |
1520 | } |
1521 | ||
1522 | /** | |
1523 | * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing | |
1524 | * @dev: DRM device | |
1525 | * @data: GTT mapping ioctl data | |
1526 | * @file_priv: GEM object info | |
1527 | * | |
1528 | * Simply returns the fake offset to userspace so it can mmap it. | |
1529 | * The mmap call will end up in drm_gem_mmap(), which will set things | |
1530 | * up so we can get faults in the handler above. | |
1531 | * | |
1532 | * The fault handler will take care of binding the object into the GTT | |
1533 | * (since it may have been evicted to make room for something), allocating | |
1534 | * a fence register, and mapping the appropriate aperture address into | |
1535 | * userspace. | |
1536 | */ | |
1537 | int | |
1538 | i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data, | |
1539 | struct drm_file *file_priv) | |
1540 | { | |
da761a6e | 1541 | struct drm_i915_private *dev_priv = dev->dev_private; |
de151cf6 | 1542 | struct drm_i915_gem_mmap_gtt *args = data; |
de151cf6 JB |
1543 | struct drm_gem_object *obj; |
1544 | struct drm_i915_gem_object *obj_priv; | |
1545 | int ret; | |
1546 | ||
1547 | if (!(dev->driver->driver_features & DRIVER_GEM)) | |
1548 | return -ENODEV; | |
1549 | ||
76c1dec1 | 1550 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 1551 | if (ret) |
76c1dec1 | 1552 | return ret; |
de151cf6 | 1553 | |
1d7cfea1 CW |
1554 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); |
1555 | if (obj == NULL) { | |
1556 | ret = -ENOENT; | |
1557 | goto unlock; | |
1558 | } | |
23010e43 | 1559 | obj_priv = to_intel_bo(obj); |
de151cf6 | 1560 | |
da761a6e CW |
1561 | if (obj->size > dev_priv->mm.gtt_mappable_end) { |
1562 | ret = -E2BIG; | |
1563 | goto unlock; | |
1564 | } | |
1565 | ||
ab18282d CW |
1566 | if (obj_priv->madv != I915_MADV_WILLNEED) { |
1567 | DRM_ERROR("Attempting to mmap a purgeable buffer\n"); | |
1d7cfea1 CW |
1568 | ret = -EINVAL; |
1569 | goto out; | |
ab18282d CW |
1570 | } |
1571 | ||
39a01d1f | 1572 | if (!obj->map_list.map) { |
de151cf6 | 1573 | ret = i915_gem_create_mmap_offset(obj); |
1d7cfea1 CW |
1574 | if (ret) |
1575 | goto out; | |
de151cf6 JB |
1576 | } |
1577 | ||
39a01d1f | 1578 | args->offset = (u64)obj->map_list.hash.key << PAGE_SHIFT; |
de151cf6 | 1579 | |
1d7cfea1 | 1580 | out: |
de151cf6 | 1581 | drm_gem_object_unreference(obj); |
1d7cfea1 | 1582 | unlock: |
de151cf6 | 1583 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 1584 | return ret; |
de151cf6 JB |
1585 | } |
1586 | ||
e5281ccd CW |
1587 | static int |
1588 | i915_gem_object_get_pages_gtt(struct drm_gem_object *obj, | |
1589 | gfp_t gfpmask) | |
1590 | { | |
1591 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); | |
1592 | int page_count, i; | |
1593 | struct address_space *mapping; | |
1594 | struct inode *inode; | |
1595 | struct page *page; | |
1596 | ||
1597 | /* Get the list of pages out of our struct file. They'll be pinned | |
1598 | * at this point until we release them. | |
1599 | */ | |
1600 | page_count = obj->size / PAGE_SIZE; | |
1601 | BUG_ON(obj_priv->pages != NULL); | |
1602 | obj_priv->pages = drm_malloc_ab(page_count, sizeof(struct page *)); | |
1603 | if (obj_priv->pages == NULL) | |
1604 | return -ENOMEM; | |
1605 | ||
1606 | inode = obj->filp->f_path.dentry->d_inode; | |
1607 | mapping = inode->i_mapping; | |
1608 | for (i = 0; i < page_count; i++) { | |
1609 | page = read_cache_page_gfp(mapping, i, | |
1610 | GFP_HIGHUSER | | |
1611 | __GFP_COLD | | |
1612 | __GFP_RECLAIMABLE | | |
1613 | gfpmask); | |
1614 | if (IS_ERR(page)) | |
1615 | goto err_pages; | |
1616 | ||
1617 | obj_priv->pages[i] = page; | |
1618 | } | |
1619 | ||
1620 | if (obj_priv->tiling_mode != I915_TILING_NONE) | |
1621 | i915_gem_object_do_bit_17_swizzle(obj); | |
1622 | ||
1623 | return 0; | |
1624 | ||
1625 | err_pages: | |
1626 | while (i--) | |
1627 | page_cache_release(obj_priv->pages[i]); | |
1628 | ||
1629 | drm_free_large(obj_priv->pages); | |
1630 | obj_priv->pages = NULL; | |
1631 | return PTR_ERR(page); | |
1632 | } | |
1633 | ||
5cdf5881 | 1634 | static void |
e5281ccd | 1635 | i915_gem_object_put_pages_gtt(struct drm_gem_object *obj) |
673a394b | 1636 | { |
23010e43 | 1637 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
673a394b EA |
1638 | int page_count = obj->size / PAGE_SIZE; |
1639 | int i; | |
1640 | ||
bb6baf76 | 1641 | BUG_ON(obj_priv->madv == __I915_MADV_PURGED); |
673a394b | 1642 | |
280b713b EA |
1643 | if (obj_priv->tiling_mode != I915_TILING_NONE) |
1644 | i915_gem_object_save_bit_17_swizzle(obj); | |
1645 | ||
3ef94daa | 1646 | if (obj_priv->madv == I915_MADV_DONTNEED) |
13a05fd9 | 1647 | obj_priv->dirty = 0; |
3ef94daa CW |
1648 | |
1649 | for (i = 0; i < page_count; i++) { | |
3ef94daa CW |
1650 | if (obj_priv->dirty) |
1651 | set_page_dirty(obj_priv->pages[i]); | |
1652 | ||
1653 | if (obj_priv->madv == I915_MADV_WILLNEED) | |
856fa198 | 1654 | mark_page_accessed(obj_priv->pages[i]); |
3ef94daa CW |
1655 | |
1656 | page_cache_release(obj_priv->pages[i]); | |
1657 | } | |
673a394b EA |
1658 | obj_priv->dirty = 0; |
1659 | ||
8e7d2b2c | 1660 | drm_free_large(obj_priv->pages); |
856fa198 | 1661 | obj_priv->pages = NULL; |
673a394b EA |
1662 | } |
1663 | ||
a56ba56c CW |
1664 | static uint32_t |
1665 | i915_gem_next_request_seqno(struct drm_device *dev, | |
1666 | struct intel_ring_buffer *ring) | |
1667 | { | |
1668 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1669 | ||
1670 | ring->outstanding_lazy_request = true; | |
1671 | return dev_priv->next_seqno; | |
1672 | } | |
1673 | ||
673a394b | 1674 | static void |
617dbe27 | 1675 | i915_gem_object_move_to_active(struct drm_gem_object *obj, |
852835f3 | 1676 | struct intel_ring_buffer *ring) |
673a394b EA |
1677 | { |
1678 | struct drm_device *dev = obj->dev; | |
69dc4987 | 1679 | struct drm_i915_private *dev_priv = dev->dev_private; |
23010e43 | 1680 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
a56ba56c | 1681 | uint32_t seqno = i915_gem_next_request_seqno(dev, ring); |
617dbe27 | 1682 | |
852835f3 ZN |
1683 | BUG_ON(ring == NULL); |
1684 | obj_priv->ring = ring; | |
673a394b EA |
1685 | |
1686 | /* Add a reference if we're newly entering the active list. */ | |
1687 | if (!obj_priv->active) { | |
1688 | drm_gem_object_reference(obj); | |
1689 | obj_priv->active = 1; | |
1690 | } | |
e35a41de | 1691 | |
673a394b | 1692 | /* Move from whatever list we were on to the tail of execution. */ |
69dc4987 CW |
1693 | list_move_tail(&obj_priv->mm_list, &dev_priv->mm.active_list); |
1694 | list_move_tail(&obj_priv->ring_list, &ring->active_list); | |
ce44b0ea | 1695 | obj_priv->last_rendering_seqno = seqno; |
673a394b EA |
1696 | } |
1697 | ||
ce44b0ea EA |
1698 | static void |
1699 | i915_gem_object_move_to_flushing(struct drm_gem_object *obj) | |
1700 | { | |
1701 | struct drm_device *dev = obj->dev; | |
1702 | drm_i915_private_t *dev_priv = dev->dev_private; | |
23010e43 | 1703 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
ce44b0ea EA |
1704 | |
1705 | BUG_ON(!obj_priv->active); | |
69dc4987 CW |
1706 | list_move_tail(&obj_priv->mm_list, &dev_priv->mm.flushing_list); |
1707 | list_del_init(&obj_priv->ring_list); | |
ce44b0ea EA |
1708 | obj_priv->last_rendering_seqno = 0; |
1709 | } | |
673a394b | 1710 | |
963b4836 CW |
1711 | /* Immediately discard the backing storage */ |
1712 | static void | |
1713 | i915_gem_object_truncate(struct drm_gem_object *obj) | |
1714 | { | |
23010e43 | 1715 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
bb6baf76 | 1716 | struct inode *inode; |
963b4836 | 1717 | |
ae9fed6b CW |
1718 | /* Our goal here is to return as much of the memory as |
1719 | * is possible back to the system as we are called from OOM. | |
1720 | * To do this we must instruct the shmfs to drop all of its | |
1721 | * backing pages, *now*. Here we mirror the actions taken | |
1722 | * when by shmem_delete_inode() to release the backing store. | |
1723 | */ | |
bb6baf76 | 1724 | inode = obj->filp->f_path.dentry->d_inode; |
ae9fed6b CW |
1725 | truncate_inode_pages(inode->i_mapping, 0); |
1726 | if (inode->i_op->truncate_range) | |
1727 | inode->i_op->truncate_range(inode, 0, (loff_t)-1); | |
bb6baf76 CW |
1728 | |
1729 | obj_priv->madv = __I915_MADV_PURGED; | |
963b4836 CW |
1730 | } |
1731 | ||
1732 | static inline int | |
1733 | i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj_priv) | |
1734 | { | |
1735 | return obj_priv->madv == I915_MADV_DONTNEED; | |
1736 | } | |
1737 | ||
673a394b EA |
1738 | static void |
1739 | i915_gem_object_move_to_inactive(struct drm_gem_object *obj) | |
1740 | { | |
1741 | struct drm_device *dev = obj->dev; | |
1742 | drm_i915_private_t *dev_priv = dev->dev_private; | |
23010e43 | 1743 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
673a394b | 1744 | |
673a394b | 1745 | if (obj_priv->pin_count != 0) |
69dc4987 | 1746 | list_move_tail(&obj_priv->mm_list, &dev_priv->mm.pinned_list); |
673a394b | 1747 | else |
69dc4987 CW |
1748 | list_move_tail(&obj_priv->mm_list, &dev_priv->mm.inactive_list); |
1749 | list_del_init(&obj_priv->ring_list); | |
673a394b | 1750 | |
99fcb766 DV |
1751 | BUG_ON(!list_empty(&obj_priv->gpu_write_list)); |
1752 | ||
ce44b0ea | 1753 | obj_priv->last_rendering_seqno = 0; |
852835f3 | 1754 | obj_priv->ring = NULL; |
673a394b EA |
1755 | if (obj_priv->active) { |
1756 | obj_priv->active = 0; | |
1757 | drm_gem_object_unreference(obj); | |
1758 | } | |
23bc5982 | 1759 | WARN_ON(i915_verify_lists(dev)); |
673a394b EA |
1760 | } |
1761 | ||
63560396 DV |
1762 | static void |
1763 | i915_gem_process_flushing_list(struct drm_device *dev, | |
8a1a49f9 | 1764 | uint32_t flush_domains, |
852835f3 | 1765 | struct intel_ring_buffer *ring) |
63560396 DV |
1766 | { |
1767 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1768 | struct drm_i915_gem_object *obj_priv, *next; | |
1769 | ||
1770 | list_for_each_entry_safe(obj_priv, next, | |
64193406 | 1771 | &ring->gpu_write_list, |
63560396 | 1772 | gpu_write_list) { |
a8089e84 | 1773 | struct drm_gem_object *obj = &obj_priv->base; |
63560396 | 1774 | |
64193406 | 1775 | if (obj->write_domain & flush_domains) { |
63560396 DV |
1776 | uint32_t old_write_domain = obj->write_domain; |
1777 | ||
1778 | obj->write_domain = 0; | |
1779 | list_del_init(&obj_priv->gpu_write_list); | |
617dbe27 | 1780 | i915_gem_object_move_to_active(obj, ring); |
63560396 DV |
1781 | |
1782 | /* update the fence lru list */ | |
007cc8ac DV |
1783 | if (obj_priv->fence_reg != I915_FENCE_REG_NONE) { |
1784 | struct drm_i915_fence_reg *reg = | |
1785 | &dev_priv->fence_regs[obj_priv->fence_reg]; | |
1786 | list_move_tail(®->lru_list, | |
63560396 | 1787 | &dev_priv->mm.fence_list); |
007cc8ac | 1788 | } |
63560396 DV |
1789 | |
1790 | trace_i915_gem_object_change_domain(obj, | |
1791 | obj->read_domains, | |
1792 | old_write_domain); | |
1793 | } | |
1794 | } | |
1795 | } | |
8187a2b7 | 1796 | |
3cce469c | 1797 | int |
8a1a49f9 | 1798 | i915_add_request(struct drm_device *dev, |
f787a5f5 | 1799 | struct drm_file *file, |
8dc5d147 | 1800 | struct drm_i915_gem_request *request, |
8a1a49f9 | 1801 | struct intel_ring_buffer *ring) |
673a394b EA |
1802 | { |
1803 | drm_i915_private_t *dev_priv = dev->dev_private; | |
f787a5f5 | 1804 | struct drm_i915_file_private *file_priv = NULL; |
673a394b EA |
1805 | uint32_t seqno; |
1806 | int was_empty; | |
3cce469c CW |
1807 | int ret; |
1808 | ||
1809 | BUG_ON(request == NULL); | |
673a394b | 1810 | |
f787a5f5 CW |
1811 | if (file != NULL) |
1812 | file_priv = file->driver_priv; | |
b962442e | 1813 | |
3cce469c CW |
1814 | ret = ring->add_request(ring, &seqno); |
1815 | if (ret) | |
1816 | return ret; | |
673a394b | 1817 | |
a56ba56c | 1818 | ring->outstanding_lazy_request = false; |
673a394b EA |
1819 | |
1820 | request->seqno = seqno; | |
852835f3 | 1821 | request->ring = ring; |
673a394b | 1822 | request->emitted_jiffies = jiffies; |
852835f3 ZN |
1823 | was_empty = list_empty(&ring->request_list); |
1824 | list_add_tail(&request->list, &ring->request_list); | |
1825 | ||
f787a5f5 | 1826 | if (file_priv) { |
1c25595f | 1827 | spin_lock(&file_priv->mm.lock); |
f787a5f5 | 1828 | request->file_priv = file_priv; |
b962442e | 1829 | list_add_tail(&request->client_list, |
f787a5f5 | 1830 | &file_priv->mm.request_list); |
1c25595f | 1831 | spin_unlock(&file_priv->mm.lock); |
b962442e | 1832 | } |
673a394b | 1833 | |
f65d9421 | 1834 | if (!dev_priv->mm.suspended) { |
b3b079db CW |
1835 | mod_timer(&dev_priv->hangcheck_timer, |
1836 | jiffies + msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)); | |
f65d9421 | 1837 | if (was_empty) |
b3b079db CW |
1838 | queue_delayed_work(dev_priv->wq, |
1839 | &dev_priv->mm.retire_work, HZ); | |
f65d9421 | 1840 | } |
3cce469c | 1841 | return 0; |
673a394b EA |
1842 | } |
1843 | ||
1844 | /** | |
1845 | * Command execution barrier | |
1846 | * | |
1847 | * Ensures that all commands in the ring are finished | |
1848 | * before signalling the CPU | |
1849 | */ | |
8a1a49f9 | 1850 | static void |
852835f3 | 1851 | i915_retire_commands(struct drm_device *dev, struct intel_ring_buffer *ring) |
673a394b | 1852 | { |
673a394b | 1853 | uint32_t flush_domains = 0; |
673a394b EA |
1854 | |
1855 | /* The sampler always gets flushed on i965 (sigh) */ | |
a6c45cf0 | 1856 | if (INTEL_INFO(dev)->gen >= 4) |
673a394b | 1857 | flush_domains |= I915_GEM_DOMAIN_SAMPLER; |
852835f3 | 1858 | |
78501eac | 1859 | ring->flush(ring, I915_GEM_DOMAIN_COMMAND, flush_domains); |
673a394b EA |
1860 | } |
1861 | ||
f787a5f5 CW |
1862 | static inline void |
1863 | i915_gem_request_remove_from_client(struct drm_i915_gem_request *request) | |
673a394b | 1864 | { |
1c25595f | 1865 | struct drm_i915_file_private *file_priv = request->file_priv; |
673a394b | 1866 | |
1c25595f CW |
1867 | if (!file_priv) |
1868 | return; | |
1c5d22f7 | 1869 | |
1c25595f CW |
1870 | spin_lock(&file_priv->mm.lock); |
1871 | list_del(&request->client_list); | |
1872 | request->file_priv = NULL; | |
1873 | spin_unlock(&file_priv->mm.lock); | |
673a394b | 1874 | } |
673a394b | 1875 | |
dfaae392 CW |
1876 | static void i915_gem_reset_ring_lists(struct drm_i915_private *dev_priv, |
1877 | struct intel_ring_buffer *ring) | |
9375e446 | 1878 | { |
dfaae392 CW |
1879 | while (!list_empty(&ring->request_list)) { |
1880 | struct drm_i915_gem_request *request; | |
673a394b | 1881 | |
dfaae392 CW |
1882 | request = list_first_entry(&ring->request_list, |
1883 | struct drm_i915_gem_request, | |
1884 | list); | |
de151cf6 | 1885 | |
dfaae392 | 1886 | list_del(&request->list); |
f787a5f5 | 1887 | i915_gem_request_remove_from_client(request); |
dfaae392 CW |
1888 | kfree(request); |
1889 | } | |
673a394b | 1890 | |
dfaae392 | 1891 | while (!list_empty(&ring->active_list)) { |
9375e446 CW |
1892 | struct drm_i915_gem_object *obj_priv; |
1893 | ||
dfaae392 | 1894 | obj_priv = list_first_entry(&ring->active_list, |
9375e446 | 1895 | struct drm_i915_gem_object, |
69dc4987 | 1896 | ring_list); |
9375e446 CW |
1897 | |
1898 | obj_priv->base.write_domain = 0; | |
dfaae392 | 1899 | list_del_init(&obj_priv->gpu_write_list); |
9375e446 | 1900 | i915_gem_object_move_to_inactive(&obj_priv->base); |
673a394b EA |
1901 | } |
1902 | } | |
1903 | ||
069efc1d | 1904 | void i915_gem_reset(struct drm_device *dev) |
673a394b | 1905 | { |
77f01230 CW |
1906 | struct drm_i915_private *dev_priv = dev->dev_private; |
1907 | struct drm_i915_gem_object *obj_priv; | |
069efc1d | 1908 | int i; |
673a394b | 1909 | |
dfaae392 | 1910 | i915_gem_reset_ring_lists(dev_priv, &dev_priv->render_ring); |
87acb0a5 | 1911 | i915_gem_reset_ring_lists(dev_priv, &dev_priv->bsd_ring); |
549f7365 | 1912 | i915_gem_reset_ring_lists(dev_priv, &dev_priv->blt_ring); |
dfaae392 CW |
1913 | |
1914 | /* Remove anything from the flushing lists. The GPU cache is likely | |
1915 | * to be lost on reset along with the data, so simply move the | |
1916 | * lost bo to the inactive list. | |
1917 | */ | |
1918 | while (!list_empty(&dev_priv->mm.flushing_list)) { | |
1919 | obj_priv = list_first_entry(&dev_priv->mm.flushing_list, | |
1920 | struct drm_i915_gem_object, | |
69dc4987 | 1921 | mm_list); |
dfaae392 CW |
1922 | |
1923 | obj_priv->base.write_domain = 0; | |
1924 | list_del_init(&obj_priv->gpu_write_list); | |
1925 | i915_gem_object_move_to_inactive(&obj_priv->base); | |
1926 | } | |
1927 | ||
1928 | /* Move everything out of the GPU domains to ensure we do any | |
1929 | * necessary invalidation upon reuse. | |
1930 | */ | |
77f01230 CW |
1931 | list_for_each_entry(obj_priv, |
1932 | &dev_priv->mm.inactive_list, | |
69dc4987 | 1933 | mm_list) |
77f01230 CW |
1934 | { |
1935 | obj_priv->base.read_domains &= ~I915_GEM_GPU_DOMAINS; | |
1936 | } | |
069efc1d CW |
1937 | |
1938 | /* The fence registers are invalidated so clear them out */ | |
1939 | for (i = 0; i < 16; i++) { | |
1940 | struct drm_i915_fence_reg *reg; | |
1941 | ||
1942 | reg = &dev_priv->fence_regs[i]; | |
1943 | if (!reg->obj) | |
1944 | continue; | |
1945 | ||
1946 | i915_gem_clear_fence_reg(reg->obj); | |
1947 | } | |
673a394b EA |
1948 | } |
1949 | ||
1950 | /** | |
1951 | * This function clears the request list as sequence numbers are passed. | |
1952 | */ | |
b09a1fec CW |
1953 | static void |
1954 | i915_gem_retire_requests_ring(struct drm_device *dev, | |
1955 | struct intel_ring_buffer *ring) | |
673a394b EA |
1956 | { |
1957 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1958 | uint32_t seqno; | |
1959 | ||
b84d5f0c CW |
1960 | if (!ring->status_page.page_addr || |
1961 | list_empty(&ring->request_list)) | |
6c0594a3 KW |
1962 | return; |
1963 | ||
23bc5982 | 1964 | WARN_ON(i915_verify_lists(dev)); |
673a394b | 1965 | |
78501eac | 1966 | seqno = ring->get_seqno(ring); |
852835f3 | 1967 | while (!list_empty(&ring->request_list)) { |
673a394b | 1968 | struct drm_i915_gem_request *request; |
673a394b | 1969 | |
852835f3 | 1970 | request = list_first_entry(&ring->request_list, |
673a394b EA |
1971 | struct drm_i915_gem_request, |
1972 | list); | |
673a394b | 1973 | |
dfaae392 | 1974 | if (!i915_seqno_passed(seqno, request->seqno)) |
b84d5f0c CW |
1975 | break; |
1976 | ||
1977 | trace_i915_gem_request_retire(dev, request->seqno); | |
1978 | ||
1979 | list_del(&request->list); | |
f787a5f5 | 1980 | i915_gem_request_remove_from_client(request); |
b84d5f0c CW |
1981 | kfree(request); |
1982 | } | |
673a394b | 1983 | |
b84d5f0c CW |
1984 | /* Move any buffers on the active list that are no longer referenced |
1985 | * by the ringbuffer to the flushing/inactive lists as appropriate. | |
1986 | */ | |
1987 | while (!list_empty(&ring->active_list)) { | |
1988 | struct drm_gem_object *obj; | |
1989 | struct drm_i915_gem_object *obj_priv; | |
1990 | ||
1991 | obj_priv = list_first_entry(&ring->active_list, | |
1992 | struct drm_i915_gem_object, | |
69dc4987 | 1993 | ring_list); |
673a394b | 1994 | |
dfaae392 | 1995 | if (!i915_seqno_passed(seqno, obj_priv->last_rendering_seqno)) |
673a394b | 1996 | break; |
b84d5f0c CW |
1997 | |
1998 | obj = &obj_priv->base; | |
b84d5f0c CW |
1999 | if (obj->write_domain != 0) |
2000 | i915_gem_object_move_to_flushing(obj); | |
2001 | else | |
2002 | i915_gem_object_move_to_inactive(obj); | |
673a394b | 2003 | } |
9d34e5db CW |
2004 | |
2005 | if (unlikely (dev_priv->trace_irq_seqno && | |
2006 | i915_seqno_passed(dev_priv->trace_irq_seqno, seqno))) { | |
78501eac | 2007 | ring->user_irq_put(ring); |
9d34e5db CW |
2008 | dev_priv->trace_irq_seqno = 0; |
2009 | } | |
23bc5982 CW |
2010 | |
2011 | WARN_ON(i915_verify_lists(dev)); | |
673a394b EA |
2012 | } |
2013 | ||
b09a1fec CW |
2014 | void |
2015 | i915_gem_retire_requests(struct drm_device *dev) | |
2016 | { | |
2017 | drm_i915_private_t *dev_priv = dev->dev_private; | |
2018 | ||
be72615b CW |
2019 | if (!list_empty(&dev_priv->mm.deferred_free_list)) { |
2020 | struct drm_i915_gem_object *obj_priv, *tmp; | |
2021 | ||
2022 | /* We must be careful that during unbind() we do not | |
2023 | * accidentally infinitely recurse into retire requests. | |
2024 | * Currently: | |
2025 | * retire -> free -> unbind -> wait -> retire_ring | |
2026 | */ | |
2027 | list_for_each_entry_safe(obj_priv, tmp, | |
2028 | &dev_priv->mm.deferred_free_list, | |
69dc4987 | 2029 | mm_list) |
be72615b CW |
2030 | i915_gem_free_object_tail(&obj_priv->base); |
2031 | } | |
2032 | ||
b09a1fec | 2033 | i915_gem_retire_requests_ring(dev, &dev_priv->render_ring); |
87acb0a5 | 2034 | i915_gem_retire_requests_ring(dev, &dev_priv->bsd_ring); |
549f7365 | 2035 | i915_gem_retire_requests_ring(dev, &dev_priv->blt_ring); |
b09a1fec CW |
2036 | } |
2037 | ||
75ef9da2 | 2038 | static void |
673a394b EA |
2039 | i915_gem_retire_work_handler(struct work_struct *work) |
2040 | { | |
2041 | drm_i915_private_t *dev_priv; | |
2042 | struct drm_device *dev; | |
2043 | ||
2044 | dev_priv = container_of(work, drm_i915_private_t, | |
2045 | mm.retire_work.work); | |
2046 | dev = dev_priv->dev; | |
2047 | ||
891b48cf CW |
2048 | /* Come back later if the device is busy... */ |
2049 | if (!mutex_trylock(&dev->struct_mutex)) { | |
2050 | queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ); | |
2051 | return; | |
2052 | } | |
2053 | ||
b09a1fec | 2054 | i915_gem_retire_requests(dev); |
d1b851fc | 2055 | |
6dbe2772 | 2056 | if (!dev_priv->mm.suspended && |
d1b851fc | 2057 | (!list_empty(&dev_priv->render_ring.request_list) || |
549f7365 CW |
2058 | !list_empty(&dev_priv->bsd_ring.request_list) || |
2059 | !list_empty(&dev_priv->blt_ring.request_list))) | |
9c9fe1f8 | 2060 | queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ); |
673a394b EA |
2061 | mutex_unlock(&dev->struct_mutex); |
2062 | } | |
2063 | ||
5a5a0c64 | 2064 | int |
852835f3 | 2065 | i915_do_wait_request(struct drm_device *dev, uint32_t seqno, |
8a1a49f9 | 2066 | bool interruptible, struct intel_ring_buffer *ring) |
673a394b EA |
2067 | { |
2068 | drm_i915_private_t *dev_priv = dev->dev_private; | |
802c7eb6 | 2069 | u32 ier; |
673a394b EA |
2070 | int ret = 0; |
2071 | ||
2072 | BUG_ON(seqno == 0); | |
2073 | ||
ba1234d1 | 2074 | if (atomic_read(&dev_priv->mm.wedged)) |
30dbf0c0 CW |
2075 | return -EAGAIN; |
2076 | ||
a56ba56c | 2077 | if (ring->outstanding_lazy_request) { |
3cce469c CW |
2078 | struct drm_i915_gem_request *request; |
2079 | ||
2080 | request = kzalloc(sizeof(*request), GFP_KERNEL); | |
2081 | if (request == NULL) | |
e35a41de | 2082 | return -ENOMEM; |
3cce469c CW |
2083 | |
2084 | ret = i915_add_request(dev, NULL, request, ring); | |
2085 | if (ret) { | |
2086 | kfree(request); | |
2087 | return ret; | |
2088 | } | |
2089 | ||
2090 | seqno = request->seqno; | |
e35a41de | 2091 | } |
a56ba56c | 2092 | BUG_ON(seqno == dev_priv->next_seqno); |
ffed1d09 | 2093 | |
78501eac | 2094 | if (!i915_seqno_passed(ring->get_seqno(ring), seqno)) { |
bad720ff | 2095 | if (HAS_PCH_SPLIT(dev)) |
036a4a7d ZW |
2096 | ier = I915_READ(DEIER) | I915_READ(GTIER); |
2097 | else | |
2098 | ier = I915_READ(IER); | |
802c7eb6 JB |
2099 | if (!ier) { |
2100 | DRM_ERROR("something (likely vbetool) disabled " | |
2101 | "interrupts, re-enabling\n"); | |
2102 | i915_driver_irq_preinstall(dev); | |
2103 | i915_driver_irq_postinstall(dev); | |
2104 | } | |
2105 | ||
1c5d22f7 CW |
2106 | trace_i915_gem_request_wait_begin(dev, seqno); |
2107 | ||
b2223497 | 2108 | ring->waiting_seqno = seqno; |
78501eac | 2109 | ring->user_irq_get(ring); |
48764bf4 | 2110 | if (interruptible) |
852835f3 | 2111 | ret = wait_event_interruptible(ring->irq_queue, |
78501eac | 2112 | i915_seqno_passed(ring->get_seqno(ring), seqno) |
852835f3 | 2113 | || atomic_read(&dev_priv->mm.wedged)); |
48764bf4 | 2114 | else |
852835f3 | 2115 | wait_event(ring->irq_queue, |
78501eac | 2116 | i915_seqno_passed(ring->get_seqno(ring), seqno) |
852835f3 | 2117 | || atomic_read(&dev_priv->mm.wedged)); |
48764bf4 | 2118 | |
78501eac | 2119 | ring->user_irq_put(ring); |
b2223497 | 2120 | ring->waiting_seqno = 0; |
1c5d22f7 CW |
2121 | |
2122 | trace_i915_gem_request_wait_end(dev, seqno); | |
673a394b | 2123 | } |
ba1234d1 | 2124 | if (atomic_read(&dev_priv->mm.wedged)) |
30dbf0c0 | 2125 | ret = -EAGAIN; |
673a394b EA |
2126 | |
2127 | if (ret && ret != -ERESTARTSYS) | |
8bff917c | 2128 | DRM_ERROR("%s returns %d (awaiting %d at %d, next %d)\n", |
78501eac | 2129 | __func__, ret, seqno, ring->get_seqno(ring), |
8bff917c | 2130 | dev_priv->next_seqno); |
673a394b EA |
2131 | |
2132 | /* Directly dispatch request retiring. While we have the work queue | |
2133 | * to handle this, the waiter on a request often wants an associated | |
2134 | * buffer to have made it to the inactive list, and we would need | |
2135 | * a separate wait queue to handle that. | |
2136 | */ | |
2137 | if (ret == 0) | |
b09a1fec | 2138 | i915_gem_retire_requests_ring(dev, ring); |
673a394b EA |
2139 | |
2140 | return ret; | |
2141 | } | |
2142 | ||
48764bf4 DV |
2143 | /** |
2144 | * Waits for a sequence number to be signaled, and cleans up the | |
2145 | * request and object lists appropriately for that event. | |
2146 | */ | |
2147 | static int | |
852835f3 | 2148 | i915_wait_request(struct drm_device *dev, uint32_t seqno, |
a56ba56c | 2149 | struct intel_ring_buffer *ring) |
48764bf4 | 2150 | { |
852835f3 | 2151 | return i915_do_wait_request(dev, seqno, 1, ring); |
48764bf4 DV |
2152 | } |
2153 | ||
20f0cd55 | 2154 | static void |
9220434a | 2155 | i915_gem_flush_ring(struct drm_device *dev, |
c78ec30b | 2156 | struct drm_file *file_priv, |
9220434a CW |
2157 | struct intel_ring_buffer *ring, |
2158 | uint32_t invalidate_domains, | |
2159 | uint32_t flush_domains) | |
2160 | { | |
78501eac | 2161 | ring->flush(ring, invalidate_domains, flush_domains); |
9220434a CW |
2162 | i915_gem_process_flushing_list(dev, flush_domains, ring); |
2163 | } | |
2164 | ||
8187a2b7 ZN |
2165 | static void |
2166 | i915_gem_flush(struct drm_device *dev, | |
c78ec30b | 2167 | struct drm_file *file_priv, |
8187a2b7 | 2168 | uint32_t invalidate_domains, |
9220434a CW |
2169 | uint32_t flush_domains, |
2170 | uint32_t flush_rings) | |
8187a2b7 ZN |
2171 | { |
2172 | drm_i915_private_t *dev_priv = dev->dev_private; | |
8bff917c | 2173 | |
8187a2b7 ZN |
2174 | if (flush_domains & I915_GEM_DOMAIN_CPU) |
2175 | drm_agp_chipset_flush(dev); | |
8bff917c | 2176 | |
9220434a CW |
2177 | if ((flush_domains | invalidate_domains) & I915_GEM_GPU_DOMAINS) { |
2178 | if (flush_rings & RING_RENDER) | |
c78ec30b | 2179 | i915_gem_flush_ring(dev, file_priv, |
9220434a CW |
2180 | &dev_priv->render_ring, |
2181 | invalidate_domains, flush_domains); | |
2182 | if (flush_rings & RING_BSD) | |
c78ec30b | 2183 | i915_gem_flush_ring(dev, file_priv, |
9220434a CW |
2184 | &dev_priv->bsd_ring, |
2185 | invalidate_domains, flush_domains); | |
549f7365 CW |
2186 | if (flush_rings & RING_BLT) |
2187 | i915_gem_flush_ring(dev, file_priv, | |
2188 | &dev_priv->blt_ring, | |
2189 | invalidate_domains, flush_domains); | |
9220434a | 2190 | } |
8187a2b7 ZN |
2191 | } |
2192 | ||
673a394b EA |
2193 | /** |
2194 | * Ensures that all rendering to the object has completed and the object is | |
2195 | * safe to unbind from the GTT or access from the CPU. | |
2196 | */ | |
2197 | static int | |
2cf34d7b CW |
2198 | i915_gem_object_wait_rendering(struct drm_gem_object *obj, |
2199 | bool interruptible) | |
673a394b EA |
2200 | { |
2201 | struct drm_device *dev = obj->dev; | |
23010e43 | 2202 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
673a394b EA |
2203 | int ret; |
2204 | ||
e47c68e9 EA |
2205 | /* This function only exists to support waiting for existing rendering, |
2206 | * not for emitting required flushes. | |
673a394b | 2207 | */ |
e47c68e9 | 2208 | BUG_ON((obj->write_domain & I915_GEM_GPU_DOMAINS) != 0); |
673a394b EA |
2209 | |
2210 | /* If there is rendering queued on the buffer being evicted, wait for | |
2211 | * it. | |
2212 | */ | |
2213 | if (obj_priv->active) { | |
2cf34d7b CW |
2214 | ret = i915_do_wait_request(dev, |
2215 | obj_priv->last_rendering_seqno, | |
2216 | interruptible, | |
2217 | obj_priv->ring); | |
2218 | if (ret) | |
673a394b EA |
2219 | return ret; |
2220 | } | |
2221 | ||
2222 | return 0; | |
2223 | } | |
2224 | ||
2225 | /** | |
2226 | * Unbinds an object from the GTT aperture. | |
2227 | */ | |
0f973f27 | 2228 | int |
673a394b EA |
2229 | i915_gem_object_unbind(struct drm_gem_object *obj) |
2230 | { | |
2231 | struct drm_device *dev = obj->dev; | |
73aa808f | 2232 | struct drm_i915_private *dev_priv = dev->dev_private; |
23010e43 | 2233 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
673a394b EA |
2234 | int ret = 0; |
2235 | ||
673a394b EA |
2236 | if (obj_priv->gtt_space == NULL) |
2237 | return 0; | |
2238 | ||
2239 | if (obj_priv->pin_count != 0) { | |
2240 | DRM_ERROR("Attempting to unbind pinned buffer\n"); | |
2241 | return -EINVAL; | |
2242 | } | |
2243 | ||
5323fd04 EA |
2244 | /* blow away mappings if mapped through GTT */ |
2245 | i915_gem_release_mmap(obj); | |
2246 | ||
673a394b EA |
2247 | /* Move the object to the CPU domain to ensure that |
2248 | * any possible CPU writes while it's not in the GTT | |
2249 | * are flushed when we go to remap it. This will | |
2250 | * also ensure that all pending GPU writes are finished | |
2251 | * before we unbind. | |
2252 | */ | |
e47c68e9 | 2253 | ret = i915_gem_object_set_to_cpu_domain(obj, 1); |
8dc1775d | 2254 | if (ret == -ERESTARTSYS) |
673a394b | 2255 | return ret; |
8dc1775d CW |
2256 | /* Continue on if we fail due to EIO, the GPU is hung so we |
2257 | * should be safe and we need to cleanup or else we might | |
2258 | * cause memory corruption through use-after-free. | |
2259 | */ | |
812ed492 CW |
2260 | if (ret) { |
2261 | i915_gem_clflush_object(obj); | |
2262 | obj->read_domains = obj->write_domain = I915_GEM_DOMAIN_CPU; | |
2263 | } | |
673a394b | 2264 | |
96b47b65 DV |
2265 | /* release the fence reg _after_ flushing */ |
2266 | if (obj_priv->fence_reg != I915_FENCE_REG_NONE) | |
2267 | i915_gem_clear_fence_reg(obj); | |
2268 | ||
73aa808f CW |
2269 | drm_unbind_agp(obj_priv->agp_mem); |
2270 | drm_free_agp(obj_priv->agp_mem, obj->size / PAGE_SIZE); | |
673a394b | 2271 | |
e5281ccd | 2272 | i915_gem_object_put_pages_gtt(obj); |
673a394b | 2273 | |
a00b10c3 | 2274 | i915_gem_info_remove_gtt(dev_priv, obj_priv); |
69dc4987 | 2275 | list_del_init(&obj_priv->mm_list); |
a00b10c3 CW |
2276 | obj_priv->fenceable = true; |
2277 | obj_priv->mappable = true; | |
673a394b | 2278 | |
73aa808f CW |
2279 | drm_mm_put_block(obj_priv->gtt_space); |
2280 | obj_priv->gtt_space = NULL; | |
9af90d19 | 2281 | obj_priv->gtt_offset = 0; |
673a394b | 2282 | |
963b4836 CW |
2283 | if (i915_gem_object_is_purgeable(obj_priv)) |
2284 | i915_gem_object_truncate(obj); | |
2285 | ||
1c5d22f7 CW |
2286 | trace_i915_gem_object_unbind(obj); |
2287 | ||
8dc1775d | 2288 | return ret; |
673a394b EA |
2289 | } |
2290 | ||
a56ba56c CW |
2291 | static int i915_ring_idle(struct drm_device *dev, |
2292 | struct intel_ring_buffer *ring) | |
2293 | { | |
395b70be | 2294 | if (list_empty(&ring->gpu_write_list) && list_empty(&ring->active_list)) |
64193406 CW |
2295 | return 0; |
2296 | ||
a56ba56c CW |
2297 | i915_gem_flush_ring(dev, NULL, ring, |
2298 | I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS); | |
2299 | return i915_wait_request(dev, | |
2300 | i915_gem_next_request_seqno(dev, ring), | |
2301 | ring); | |
2302 | } | |
2303 | ||
b47eb4a2 | 2304 | int |
4df2faf4 DV |
2305 | i915_gpu_idle(struct drm_device *dev) |
2306 | { | |
2307 | drm_i915_private_t *dev_priv = dev->dev_private; | |
2308 | bool lists_empty; | |
852835f3 | 2309 | int ret; |
4df2faf4 | 2310 | |
d1b851fc | 2311 | lists_empty = (list_empty(&dev_priv->mm.flushing_list) && |
395b70be | 2312 | list_empty(&dev_priv->mm.active_list)); |
4df2faf4 DV |
2313 | if (lists_empty) |
2314 | return 0; | |
2315 | ||
2316 | /* Flush everything onto the inactive list. */ | |
a56ba56c | 2317 | ret = i915_ring_idle(dev, &dev_priv->render_ring); |
8a1a49f9 DV |
2318 | if (ret) |
2319 | return ret; | |
d1b851fc | 2320 | |
87acb0a5 CW |
2321 | ret = i915_ring_idle(dev, &dev_priv->bsd_ring); |
2322 | if (ret) | |
2323 | return ret; | |
d1b851fc | 2324 | |
549f7365 CW |
2325 | ret = i915_ring_idle(dev, &dev_priv->blt_ring); |
2326 | if (ret) | |
2327 | return ret; | |
4df2faf4 | 2328 | |
8a1a49f9 | 2329 | return 0; |
4df2faf4 DV |
2330 | } |
2331 | ||
a00b10c3 | 2332 | static void sandybridge_write_fence_reg(struct drm_gem_object *obj) |
4e901fdc | 2333 | { |
4e901fdc EA |
2334 | struct drm_device *dev = obj->dev; |
2335 | drm_i915_private_t *dev_priv = dev->dev_private; | |
23010e43 | 2336 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
a00b10c3 | 2337 | u32 size = i915_gem_get_gtt_size(obj_priv); |
4e901fdc EA |
2338 | int regnum = obj_priv->fence_reg; |
2339 | uint64_t val; | |
2340 | ||
a00b10c3 | 2341 | val = (uint64_t)((obj_priv->gtt_offset + size - 4096) & |
4e901fdc EA |
2342 | 0xfffff000) << 32; |
2343 | val |= obj_priv->gtt_offset & 0xfffff000; | |
2344 | val |= (uint64_t)((obj_priv->stride / 128) - 1) << | |
2345 | SANDYBRIDGE_FENCE_PITCH_SHIFT; | |
2346 | ||
2347 | if (obj_priv->tiling_mode == I915_TILING_Y) | |
2348 | val |= 1 << I965_FENCE_TILING_Y_SHIFT; | |
2349 | val |= I965_FENCE_REG_VALID; | |
2350 | ||
2351 | I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + (regnum * 8), val); | |
2352 | } | |
2353 | ||
a00b10c3 | 2354 | static void i965_write_fence_reg(struct drm_gem_object *obj) |
de151cf6 | 2355 | { |
de151cf6 JB |
2356 | struct drm_device *dev = obj->dev; |
2357 | drm_i915_private_t *dev_priv = dev->dev_private; | |
23010e43 | 2358 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
a00b10c3 | 2359 | u32 size = i915_gem_get_gtt_size(obj_priv); |
de151cf6 JB |
2360 | int regnum = obj_priv->fence_reg; |
2361 | uint64_t val; | |
2362 | ||
a00b10c3 | 2363 | val = (uint64_t)((obj_priv->gtt_offset + size - 4096) & |
de151cf6 JB |
2364 | 0xfffff000) << 32; |
2365 | val |= obj_priv->gtt_offset & 0xfffff000; | |
2366 | val |= ((obj_priv->stride / 128) - 1) << I965_FENCE_PITCH_SHIFT; | |
2367 | if (obj_priv->tiling_mode == I915_TILING_Y) | |
2368 | val |= 1 << I965_FENCE_TILING_Y_SHIFT; | |
2369 | val |= I965_FENCE_REG_VALID; | |
2370 | ||
2371 | I915_WRITE64(FENCE_REG_965_0 + (regnum * 8), val); | |
2372 | } | |
2373 | ||
a00b10c3 | 2374 | static void i915_write_fence_reg(struct drm_gem_object *obj) |
de151cf6 | 2375 | { |
de151cf6 JB |
2376 | struct drm_device *dev = obj->dev; |
2377 | drm_i915_private_t *dev_priv = dev->dev_private; | |
23010e43 | 2378 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
a00b10c3 CW |
2379 | u32 size = i915_gem_get_gtt_size(obj_priv); |
2380 | uint32_t fence_reg, val, pitch_val; | |
0f973f27 | 2381 | int tile_width; |
de151cf6 JB |
2382 | |
2383 | if ((obj_priv->gtt_offset & ~I915_FENCE_START_MASK) || | |
a00b10c3 CW |
2384 | (obj_priv->gtt_offset & (size - 1))) { |
2385 | WARN(1, "%s: object 0x%08x [fenceable? %d] not 1M or size (0x%08x) aligned [gtt_space offset=%lx, size=%lx]\n", | |
2386 | __func__, obj_priv->gtt_offset, obj_priv->fenceable, size, | |
2387 | obj_priv->gtt_space->start, obj_priv->gtt_space->size); | |
de151cf6 JB |
2388 | return; |
2389 | } | |
2390 | ||
0f973f27 JB |
2391 | if (obj_priv->tiling_mode == I915_TILING_Y && |
2392 | HAS_128_BYTE_Y_TILING(dev)) | |
2393 | tile_width = 128; | |
de151cf6 | 2394 | else |
0f973f27 JB |
2395 | tile_width = 512; |
2396 | ||
2397 | /* Note: pitch better be a power of two tile widths */ | |
2398 | pitch_val = obj_priv->stride / tile_width; | |
2399 | pitch_val = ffs(pitch_val) - 1; | |
de151cf6 | 2400 | |
c36a2a6d DV |
2401 | if (obj_priv->tiling_mode == I915_TILING_Y && |
2402 | HAS_128_BYTE_Y_TILING(dev)) | |
2403 | WARN_ON(pitch_val > I830_FENCE_MAX_PITCH_VAL); | |
2404 | else | |
2405 | WARN_ON(pitch_val > I915_FENCE_MAX_PITCH_VAL); | |
2406 | ||
de151cf6 JB |
2407 | val = obj_priv->gtt_offset; |
2408 | if (obj_priv->tiling_mode == I915_TILING_Y) | |
2409 | val |= 1 << I830_FENCE_TILING_Y_SHIFT; | |
a00b10c3 | 2410 | val |= I915_FENCE_SIZE_BITS(size); |
de151cf6 JB |
2411 | val |= pitch_val << I830_FENCE_PITCH_SHIFT; |
2412 | val |= I830_FENCE_REG_VALID; | |
2413 | ||
a00b10c3 CW |
2414 | fence_reg = obj_priv->fence_reg; |
2415 | if (fence_reg < 8) | |
2416 | fence_reg = FENCE_REG_830_0 + fence_reg * 4; | |
dc529a4f | 2417 | else |
a00b10c3 | 2418 | fence_reg = FENCE_REG_945_8 + (fence_reg - 8) * 4; |
dc529a4f | 2419 | I915_WRITE(fence_reg, val); |
de151cf6 JB |
2420 | } |
2421 | ||
a00b10c3 | 2422 | static void i830_write_fence_reg(struct drm_gem_object *obj) |
de151cf6 | 2423 | { |
de151cf6 JB |
2424 | struct drm_device *dev = obj->dev; |
2425 | drm_i915_private_t *dev_priv = dev->dev_private; | |
23010e43 | 2426 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
a00b10c3 | 2427 | u32 size = i915_gem_get_gtt_size(obj_priv); |
de151cf6 JB |
2428 | int regnum = obj_priv->fence_reg; |
2429 | uint32_t val; | |
2430 | uint32_t pitch_val; | |
8d7773a3 | 2431 | uint32_t fence_size_bits; |
de151cf6 | 2432 | |
8d7773a3 | 2433 | if ((obj_priv->gtt_offset & ~I830_FENCE_START_MASK) || |
de151cf6 | 2434 | (obj_priv->gtt_offset & (obj->size - 1))) { |
8d7773a3 | 2435 | WARN(1, "%s: object 0x%08x not 512K or size aligned\n", |
0f973f27 | 2436 | __func__, obj_priv->gtt_offset); |
de151cf6 JB |
2437 | return; |
2438 | } | |
2439 | ||
e76a16de EA |
2440 | pitch_val = obj_priv->stride / 128; |
2441 | pitch_val = ffs(pitch_val) - 1; | |
2442 | WARN_ON(pitch_val > I830_FENCE_MAX_PITCH_VAL); | |
2443 | ||
de151cf6 JB |
2444 | val = obj_priv->gtt_offset; |
2445 | if (obj_priv->tiling_mode == I915_TILING_Y) | |
2446 | val |= 1 << I830_FENCE_TILING_Y_SHIFT; | |
a00b10c3 | 2447 | fence_size_bits = I830_FENCE_SIZE_BITS(size); |
8d7773a3 DV |
2448 | WARN_ON(fence_size_bits & ~0x00000f00); |
2449 | val |= fence_size_bits; | |
de151cf6 JB |
2450 | val |= pitch_val << I830_FENCE_PITCH_SHIFT; |
2451 | val |= I830_FENCE_REG_VALID; | |
2452 | ||
2453 | I915_WRITE(FENCE_REG_830_0 + (regnum * 4), val); | |
de151cf6 JB |
2454 | } |
2455 | ||
2cf34d7b CW |
2456 | static int i915_find_fence_reg(struct drm_device *dev, |
2457 | bool interruptible) | |
ae3db24a | 2458 | { |
ae3db24a | 2459 | struct drm_i915_private *dev_priv = dev->dev_private; |
a00b10c3 CW |
2460 | struct drm_i915_fence_reg *reg; |
2461 | struct drm_i915_gem_object *obj_priv = NULL; | |
ae3db24a DV |
2462 | int i, avail, ret; |
2463 | ||
2464 | /* First try to find a free reg */ | |
2465 | avail = 0; | |
2466 | for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) { | |
2467 | reg = &dev_priv->fence_regs[i]; | |
2468 | if (!reg->obj) | |
2469 | return i; | |
2470 | ||
23010e43 | 2471 | obj_priv = to_intel_bo(reg->obj); |
ae3db24a DV |
2472 | if (!obj_priv->pin_count) |
2473 | avail++; | |
2474 | } | |
2475 | ||
2476 | if (avail == 0) | |
2477 | return -ENOSPC; | |
2478 | ||
2479 | /* None available, try to steal one or wait for a user to finish */ | |
a00b10c3 | 2480 | avail = I915_FENCE_REG_NONE; |
007cc8ac DV |
2481 | list_for_each_entry(reg, &dev_priv->mm.fence_list, |
2482 | lru_list) { | |
a00b10c3 | 2483 | obj_priv = to_intel_bo(reg->obj); |
ae3db24a DV |
2484 | if (obj_priv->pin_count) |
2485 | continue; | |
2486 | ||
2487 | /* found one! */ | |
a00b10c3 | 2488 | avail = obj_priv->fence_reg; |
ae3db24a DV |
2489 | break; |
2490 | } | |
2491 | ||
a00b10c3 | 2492 | BUG_ON(avail == I915_FENCE_REG_NONE); |
ae3db24a DV |
2493 | |
2494 | /* We only have a reference on obj from the active list. put_fence_reg | |
2495 | * might drop that one, causing a use-after-free in it. So hold a | |
2496 | * private reference to obj like the other callers of put_fence_reg | |
2497 | * (set_tiling ioctl) do. */ | |
a00b10c3 CW |
2498 | drm_gem_object_reference(&obj_priv->base); |
2499 | ret = i915_gem_object_put_fence_reg(&obj_priv->base, interruptible); | |
2500 | drm_gem_object_unreference(&obj_priv->base); | |
ae3db24a DV |
2501 | if (ret != 0) |
2502 | return ret; | |
2503 | ||
a00b10c3 | 2504 | return avail; |
ae3db24a DV |
2505 | } |
2506 | ||
de151cf6 JB |
2507 | /** |
2508 | * i915_gem_object_get_fence_reg - set up a fence reg for an object | |
2509 | * @obj: object to map through a fence reg | |
2510 | * | |
2511 | * When mapping objects through the GTT, userspace wants to be able to write | |
2512 | * to them without having to worry about swizzling if the object is tiled. | |
2513 | * | |
2514 | * This function walks the fence regs looking for a free one for @obj, | |
2515 | * stealing one if it can't find any. | |
2516 | * | |
2517 | * It then sets up the reg based on the object's properties: address, pitch | |
2518 | * and tiling format. | |
2519 | */ | |
8c4b8c3f | 2520 | int |
2cf34d7b CW |
2521 | i915_gem_object_get_fence_reg(struct drm_gem_object *obj, |
2522 | bool interruptible) | |
de151cf6 JB |
2523 | { |
2524 | struct drm_device *dev = obj->dev; | |
79e53945 | 2525 | struct drm_i915_private *dev_priv = dev->dev_private; |
23010e43 | 2526 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
de151cf6 | 2527 | struct drm_i915_fence_reg *reg = NULL; |
ae3db24a | 2528 | int ret; |
de151cf6 | 2529 | |
a09ba7fa EA |
2530 | /* Just update our place in the LRU if our fence is getting used. */ |
2531 | if (obj_priv->fence_reg != I915_FENCE_REG_NONE) { | |
007cc8ac DV |
2532 | reg = &dev_priv->fence_regs[obj_priv->fence_reg]; |
2533 | list_move_tail(®->lru_list, &dev_priv->mm.fence_list); | |
a09ba7fa EA |
2534 | return 0; |
2535 | } | |
2536 | ||
de151cf6 JB |
2537 | switch (obj_priv->tiling_mode) { |
2538 | case I915_TILING_NONE: | |
2539 | WARN(1, "allocating a fence for non-tiled object?\n"); | |
2540 | break; | |
2541 | case I915_TILING_X: | |
0f973f27 JB |
2542 | if (!obj_priv->stride) |
2543 | return -EINVAL; | |
2544 | WARN((obj_priv->stride & (512 - 1)), | |
2545 | "object 0x%08x is X tiled but has non-512B pitch\n", | |
2546 | obj_priv->gtt_offset); | |
de151cf6 JB |
2547 | break; |
2548 | case I915_TILING_Y: | |
0f973f27 JB |
2549 | if (!obj_priv->stride) |
2550 | return -EINVAL; | |
2551 | WARN((obj_priv->stride & (128 - 1)), | |
2552 | "object 0x%08x is Y tiled but has non-128B pitch\n", | |
2553 | obj_priv->gtt_offset); | |
de151cf6 JB |
2554 | break; |
2555 | } | |
2556 | ||
2cf34d7b | 2557 | ret = i915_find_fence_reg(dev, interruptible); |
ae3db24a DV |
2558 | if (ret < 0) |
2559 | return ret; | |
de151cf6 | 2560 | |
ae3db24a DV |
2561 | obj_priv->fence_reg = ret; |
2562 | reg = &dev_priv->fence_regs[obj_priv->fence_reg]; | |
007cc8ac | 2563 | list_add_tail(®->lru_list, &dev_priv->mm.fence_list); |
a09ba7fa | 2564 | |
de151cf6 JB |
2565 | reg->obj = obj; |
2566 | ||
e259befd CW |
2567 | switch (INTEL_INFO(dev)->gen) { |
2568 | case 6: | |
a00b10c3 | 2569 | sandybridge_write_fence_reg(obj); |
e259befd CW |
2570 | break; |
2571 | case 5: | |
2572 | case 4: | |
a00b10c3 | 2573 | i965_write_fence_reg(obj); |
e259befd CW |
2574 | break; |
2575 | case 3: | |
a00b10c3 | 2576 | i915_write_fence_reg(obj); |
e259befd CW |
2577 | break; |
2578 | case 2: | |
a00b10c3 | 2579 | i830_write_fence_reg(obj); |
e259befd CW |
2580 | break; |
2581 | } | |
d9ddcb96 | 2582 | |
a00b10c3 CW |
2583 | trace_i915_gem_object_get_fence(obj, |
2584 | obj_priv->fence_reg, | |
2585 | obj_priv->tiling_mode); | |
1c5d22f7 | 2586 | |
d9ddcb96 | 2587 | return 0; |
de151cf6 JB |
2588 | } |
2589 | ||
2590 | /** | |
2591 | * i915_gem_clear_fence_reg - clear out fence register info | |
2592 | * @obj: object to clear | |
2593 | * | |
2594 | * Zeroes out the fence register itself and clears out the associated | |
2595 | * data structures in dev_priv and obj_priv. | |
2596 | */ | |
2597 | static void | |
2598 | i915_gem_clear_fence_reg(struct drm_gem_object *obj) | |
2599 | { | |
2600 | struct drm_device *dev = obj->dev; | |
79e53945 | 2601 | drm_i915_private_t *dev_priv = dev->dev_private; |
23010e43 | 2602 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
007cc8ac DV |
2603 | struct drm_i915_fence_reg *reg = |
2604 | &dev_priv->fence_regs[obj_priv->fence_reg]; | |
e259befd | 2605 | uint32_t fence_reg; |
de151cf6 | 2606 | |
e259befd CW |
2607 | switch (INTEL_INFO(dev)->gen) { |
2608 | case 6: | |
4e901fdc EA |
2609 | I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + |
2610 | (obj_priv->fence_reg * 8), 0); | |
e259befd CW |
2611 | break; |
2612 | case 5: | |
2613 | case 4: | |
de151cf6 | 2614 | I915_WRITE64(FENCE_REG_965_0 + (obj_priv->fence_reg * 8), 0); |
e259befd CW |
2615 | break; |
2616 | case 3: | |
9b74f734 | 2617 | if (obj_priv->fence_reg >= 8) |
e259befd | 2618 | fence_reg = FENCE_REG_945_8 + (obj_priv->fence_reg - 8) * 4; |
dc529a4f | 2619 | else |
e259befd CW |
2620 | case 2: |
2621 | fence_reg = FENCE_REG_830_0 + obj_priv->fence_reg * 4; | |
dc529a4f EA |
2622 | |
2623 | I915_WRITE(fence_reg, 0); | |
e259befd | 2624 | break; |
dc529a4f | 2625 | } |
de151cf6 | 2626 | |
007cc8ac | 2627 | reg->obj = NULL; |
de151cf6 | 2628 | obj_priv->fence_reg = I915_FENCE_REG_NONE; |
007cc8ac | 2629 | list_del_init(®->lru_list); |
de151cf6 JB |
2630 | } |
2631 | ||
52dc7d32 CW |
2632 | /** |
2633 | * i915_gem_object_put_fence_reg - waits on outstanding fenced access | |
2634 | * to the buffer to finish, and then resets the fence register. | |
2635 | * @obj: tiled object holding a fence register. | |
2cf34d7b | 2636 | * @bool: whether the wait upon the fence is interruptible |
52dc7d32 CW |
2637 | * |
2638 | * Zeroes out the fence register itself and clears out the associated | |
2639 | * data structures in dev_priv and obj_priv. | |
2640 | */ | |
2641 | int | |
2cf34d7b CW |
2642 | i915_gem_object_put_fence_reg(struct drm_gem_object *obj, |
2643 | bool interruptible) | |
52dc7d32 CW |
2644 | { |
2645 | struct drm_device *dev = obj->dev; | |
53640e1d | 2646 | struct drm_i915_private *dev_priv = dev->dev_private; |
23010e43 | 2647 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
53640e1d | 2648 | struct drm_i915_fence_reg *reg; |
52dc7d32 CW |
2649 | |
2650 | if (obj_priv->fence_reg == I915_FENCE_REG_NONE) | |
2651 | return 0; | |
2652 | ||
10ae9bd2 DV |
2653 | /* If we've changed tiling, GTT-mappings of the object |
2654 | * need to re-fault to ensure that the correct fence register | |
2655 | * setup is in place. | |
2656 | */ | |
2657 | i915_gem_release_mmap(obj); | |
2658 | ||
52dc7d32 CW |
2659 | /* On the i915, GPU access to tiled buffers is via a fence, |
2660 | * therefore we must wait for any outstanding access to complete | |
2661 | * before clearing the fence. | |
2662 | */ | |
53640e1d CW |
2663 | reg = &dev_priv->fence_regs[obj_priv->fence_reg]; |
2664 | if (reg->gpu) { | |
52dc7d32 CW |
2665 | int ret; |
2666 | ||
2cf34d7b | 2667 | ret = i915_gem_object_flush_gpu_write_domain(obj, true); |
0bc23aad | 2668 | if (ret) |
2dafb1e0 CW |
2669 | return ret; |
2670 | ||
2cf34d7b | 2671 | ret = i915_gem_object_wait_rendering(obj, interruptible); |
0bc23aad | 2672 | if (ret) |
52dc7d32 | 2673 | return ret; |
53640e1d CW |
2674 | |
2675 | reg->gpu = false; | |
52dc7d32 CW |
2676 | } |
2677 | ||
4a726612 | 2678 | i915_gem_object_flush_gtt_write_domain(obj); |
0bc23aad | 2679 | i915_gem_clear_fence_reg(obj); |
52dc7d32 CW |
2680 | |
2681 | return 0; | |
2682 | } | |
2683 | ||
673a394b EA |
2684 | /** |
2685 | * Finds free space in the GTT aperture and binds the object there. | |
2686 | */ | |
2687 | static int | |
920afa77 DV |
2688 | i915_gem_object_bind_to_gtt(struct drm_gem_object *obj, |
2689 | unsigned alignment, | |
a00b10c3 CW |
2690 | bool mappable, |
2691 | bool need_fence) | |
673a394b EA |
2692 | { |
2693 | struct drm_device *dev = obj->dev; | |
2694 | drm_i915_private_t *dev_priv = dev->dev_private; | |
23010e43 | 2695 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
673a394b | 2696 | struct drm_mm_node *free_space; |
a00b10c3 CW |
2697 | gfp_t gfpmask = __GFP_NORETRY | __GFP_NOWARN; |
2698 | u32 size, fence_size, fence_alignment; | |
07f73f69 | 2699 | int ret; |
673a394b | 2700 | |
bb6baf76 | 2701 | if (obj_priv->madv != I915_MADV_WILLNEED) { |
3ef94daa CW |
2702 | DRM_ERROR("Attempting to bind a purgeable object\n"); |
2703 | return -EINVAL; | |
2704 | } | |
2705 | ||
a00b10c3 CW |
2706 | fence_size = i915_gem_get_gtt_size(obj_priv); |
2707 | fence_alignment = i915_gem_get_gtt_alignment(obj_priv); | |
2708 | ||
673a394b | 2709 | if (alignment == 0) |
a00b10c3 CW |
2710 | alignment = need_fence ? fence_alignment : 4096; |
2711 | if (need_fence && alignment & (fence_alignment - 1)) { | |
673a394b EA |
2712 | DRM_ERROR("Invalid object alignment requested %u\n", alignment); |
2713 | return -EINVAL; | |
2714 | } | |
2715 | ||
a00b10c3 CW |
2716 | size = need_fence ? fence_size : obj->size; |
2717 | ||
654fc607 CW |
2718 | /* If the object is bigger than the entire aperture, reject it early |
2719 | * before evicting everything in a vain attempt to find space. | |
2720 | */ | |
920afa77 DV |
2721 | if (obj->size > |
2722 | (mappable ? dev_priv->mm.gtt_mappable_end : dev_priv->mm.gtt_total)) { | |
654fc607 CW |
2723 | DRM_ERROR("Attempting to bind an object larger than the aperture\n"); |
2724 | return -E2BIG; | |
2725 | } | |
2726 | ||
673a394b | 2727 | search_free: |
920afa77 DV |
2728 | if (mappable) |
2729 | free_space = | |
2730 | drm_mm_search_free_in_range(&dev_priv->mm.gtt_space, | |
a00b10c3 | 2731 | size, alignment, 0, |
920afa77 DV |
2732 | dev_priv->mm.gtt_mappable_end, |
2733 | 0); | |
2734 | else | |
2735 | free_space = drm_mm_search_free(&dev_priv->mm.gtt_space, | |
a00b10c3 | 2736 | size, alignment, 0); |
920afa77 DV |
2737 | |
2738 | if (free_space != NULL) { | |
2739 | if (mappable) | |
2740 | obj_priv->gtt_space = | |
2741 | drm_mm_get_block_range_generic(free_space, | |
a00b10c3 | 2742 | size, alignment, 0, |
920afa77 DV |
2743 | dev_priv->mm.gtt_mappable_end, |
2744 | 0); | |
2745 | else | |
2746 | obj_priv->gtt_space = | |
a00b10c3 | 2747 | drm_mm_get_block(free_space, size, alignment); |
920afa77 | 2748 | } |
673a394b EA |
2749 | if (obj_priv->gtt_space == NULL) { |
2750 | /* If the gtt is empty and we're still having trouble | |
2751 | * fitting our object in, we're out of memory. | |
2752 | */ | |
a00b10c3 | 2753 | ret = i915_gem_evict_something(dev, size, alignment, mappable); |
9731129c | 2754 | if (ret) |
673a394b | 2755 | return ret; |
9731129c | 2756 | |
673a394b EA |
2757 | goto search_free; |
2758 | } | |
2759 | ||
e5281ccd | 2760 | ret = i915_gem_object_get_pages_gtt(obj, gfpmask); |
673a394b EA |
2761 | if (ret) { |
2762 | drm_mm_put_block(obj_priv->gtt_space); | |
2763 | obj_priv->gtt_space = NULL; | |
07f73f69 CW |
2764 | |
2765 | if (ret == -ENOMEM) { | |
2766 | /* first try to clear up some space from the GTT */ | |
a00b10c3 | 2767 | ret = i915_gem_evict_something(dev, size, |
920afa77 | 2768 | alignment, mappable); |
07f73f69 | 2769 | if (ret) { |
07f73f69 | 2770 | /* now try to shrink everyone else */ |
4bdadb97 CW |
2771 | if (gfpmask) { |
2772 | gfpmask = 0; | |
2773 | goto search_free; | |
07f73f69 CW |
2774 | } |
2775 | ||
2776 | return ret; | |
2777 | } | |
2778 | ||
2779 | goto search_free; | |
2780 | } | |
2781 | ||
673a394b EA |
2782 | return ret; |
2783 | } | |
2784 | ||
673a394b EA |
2785 | /* Create an AGP memory structure pointing at our pages, and bind it |
2786 | * into the GTT. | |
2787 | */ | |
2788 | obj_priv->agp_mem = drm_agp_bind_pages(dev, | |
856fa198 | 2789 | obj_priv->pages, |
07f73f69 | 2790 | obj->size >> PAGE_SHIFT, |
9af90d19 | 2791 | obj_priv->gtt_space->start, |
ba1eb1d8 | 2792 | obj_priv->agp_type); |
673a394b | 2793 | if (obj_priv->agp_mem == NULL) { |
e5281ccd | 2794 | i915_gem_object_put_pages_gtt(obj); |
673a394b EA |
2795 | drm_mm_put_block(obj_priv->gtt_space); |
2796 | obj_priv->gtt_space = NULL; | |
07f73f69 | 2797 | |
a00b10c3 CW |
2798 | ret = i915_gem_evict_something(dev, size, |
2799 | alignment, mappable); | |
9731129c | 2800 | if (ret) |
07f73f69 | 2801 | return ret; |
07f73f69 CW |
2802 | |
2803 | goto search_free; | |
673a394b | 2804 | } |
673a394b | 2805 | |
fb7d516a DV |
2806 | obj_priv->gtt_offset = obj_priv->gtt_space->start; |
2807 | ||
bf1a1092 | 2808 | /* keep track of bounds object by adding it to the inactive list */ |
69dc4987 | 2809 | list_add_tail(&obj_priv->mm_list, &dev_priv->mm.inactive_list); |
a00b10c3 | 2810 | i915_gem_info_add_gtt(dev_priv, obj_priv); |
bf1a1092 | 2811 | |
673a394b EA |
2812 | /* Assert that the object is not currently in any GPU domain. As it |
2813 | * wasn't in the GTT, there shouldn't be any way it could have been in | |
2814 | * a GPU cache | |
2815 | */ | |
21d509e3 CW |
2816 | BUG_ON(obj->read_domains & I915_GEM_GPU_DOMAINS); |
2817 | BUG_ON(obj->write_domain & I915_GEM_GPU_DOMAINS); | |
673a394b | 2818 | |
ec57d260 | 2819 | trace_i915_gem_object_bind(obj, obj_priv->gtt_offset, mappable); |
1c5d22f7 | 2820 | |
a00b10c3 CW |
2821 | obj_priv->fenceable = |
2822 | obj_priv->gtt_space->size == fence_size && | |
2823 | (obj_priv->gtt_space->start & (fence_alignment -1)) == 0; | |
2824 | ||
2825 | obj_priv->mappable = | |
2826 | obj_priv->gtt_offset + obj->size <= dev_priv->mm.gtt_mappable_end; | |
2827 | ||
673a394b EA |
2828 | return 0; |
2829 | } | |
2830 | ||
2831 | void | |
2832 | i915_gem_clflush_object(struct drm_gem_object *obj) | |
2833 | { | |
23010e43 | 2834 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
673a394b EA |
2835 | |
2836 | /* If we don't have a page list set up, then we're not pinned | |
2837 | * to GPU, and we can ignore the cache flush because it'll happen | |
2838 | * again at bind time. | |
2839 | */ | |
856fa198 | 2840 | if (obj_priv->pages == NULL) |
673a394b EA |
2841 | return; |
2842 | ||
1c5d22f7 | 2843 | trace_i915_gem_object_clflush(obj); |
cfa16a0d | 2844 | |
856fa198 | 2845 | drm_clflush_pages(obj_priv->pages, obj->size / PAGE_SIZE); |
673a394b EA |
2846 | } |
2847 | ||
e47c68e9 | 2848 | /** Flushes any GPU write domain for the object if it's dirty. */ |
2dafb1e0 | 2849 | static int |
ba3d8d74 DV |
2850 | i915_gem_object_flush_gpu_write_domain(struct drm_gem_object *obj, |
2851 | bool pipelined) | |
e47c68e9 EA |
2852 | { |
2853 | struct drm_device *dev = obj->dev; | |
e47c68e9 EA |
2854 | |
2855 | if ((obj->write_domain & I915_GEM_GPU_DOMAINS) == 0) | |
2dafb1e0 | 2856 | return 0; |
e47c68e9 EA |
2857 | |
2858 | /* Queue the GPU write cache flushing we need. */ | |
c78ec30b | 2859 | i915_gem_flush_ring(dev, NULL, |
9220434a CW |
2860 | to_intel_bo(obj)->ring, |
2861 | 0, obj->write_domain); | |
48b956c5 | 2862 | BUG_ON(obj->write_domain); |
1c5d22f7 | 2863 | |
ba3d8d74 DV |
2864 | if (pipelined) |
2865 | return 0; | |
2866 | ||
2cf34d7b | 2867 | return i915_gem_object_wait_rendering(obj, true); |
e47c68e9 EA |
2868 | } |
2869 | ||
2870 | /** Flushes the GTT write domain for the object if it's dirty. */ | |
2871 | static void | |
2872 | i915_gem_object_flush_gtt_write_domain(struct drm_gem_object *obj) | |
2873 | { | |
1c5d22f7 CW |
2874 | uint32_t old_write_domain; |
2875 | ||
e47c68e9 EA |
2876 | if (obj->write_domain != I915_GEM_DOMAIN_GTT) |
2877 | return; | |
2878 | ||
2879 | /* No actual flushing is required for the GTT write domain. Writes | |
2880 | * to it immediately go to main memory as far as we know, so there's | |
2881 | * no chipset flush. It also doesn't land in render cache. | |
2882 | */ | |
4a684a41 CW |
2883 | i915_gem_release_mmap(obj); |
2884 | ||
1c5d22f7 | 2885 | old_write_domain = obj->write_domain; |
e47c68e9 | 2886 | obj->write_domain = 0; |
1c5d22f7 CW |
2887 | |
2888 | trace_i915_gem_object_change_domain(obj, | |
2889 | obj->read_domains, | |
2890 | old_write_domain); | |
e47c68e9 EA |
2891 | } |
2892 | ||
2893 | /** Flushes the CPU write domain for the object if it's dirty. */ | |
2894 | static void | |
2895 | i915_gem_object_flush_cpu_write_domain(struct drm_gem_object *obj) | |
2896 | { | |
2897 | struct drm_device *dev = obj->dev; | |
1c5d22f7 | 2898 | uint32_t old_write_domain; |
e47c68e9 EA |
2899 | |
2900 | if (obj->write_domain != I915_GEM_DOMAIN_CPU) | |
2901 | return; | |
2902 | ||
2903 | i915_gem_clflush_object(obj); | |
2904 | drm_agp_chipset_flush(dev); | |
1c5d22f7 | 2905 | old_write_domain = obj->write_domain; |
e47c68e9 | 2906 | obj->write_domain = 0; |
1c5d22f7 CW |
2907 | |
2908 | trace_i915_gem_object_change_domain(obj, | |
2909 | obj->read_domains, | |
2910 | old_write_domain); | |
e47c68e9 EA |
2911 | } |
2912 | ||
2ef7eeaa EA |
2913 | /** |
2914 | * Moves a single object to the GTT read, and possibly write domain. | |
2915 | * | |
2916 | * This function returns when the move is complete, including waiting on | |
2917 | * flushes to occur. | |
2918 | */ | |
79e53945 | 2919 | int |
2ef7eeaa EA |
2920 | i915_gem_object_set_to_gtt_domain(struct drm_gem_object *obj, int write) |
2921 | { | |
23010e43 | 2922 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
1c5d22f7 | 2923 | uint32_t old_write_domain, old_read_domains; |
e47c68e9 | 2924 | int ret; |
2ef7eeaa | 2925 | |
02354392 EA |
2926 | /* Not valid to be called on unbound objects. */ |
2927 | if (obj_priv->gtt_space == NULL) | |
2928 | return -EINVAL; | |
2929 | ||
ba3d8d74 | 2930 | ret = i915_gem_object_flush_gpu_write_domain(obj, false); |
2dafb1e0 CW |
2931 | if (ret != 0) |
2932 | return ret; | |
2933 | ||
7213342d | 2934 | i915_gem_object_flush_cpu_write_domain(obj); |
1c5d22f7 | 2935 | |
ba3d8d74 | 2936 | if (write) { |
2cf34d7b | 2937 | ret = i915_gem_object_wait_rendering(obj, true); |
ba3d8d74 DV |
2938 | if (ret) |
2939 | return ret; | |
ba3d8d74 | 2940 | } |
e47c68e9 | 2941 | |
1c5d22f7 CW |
2942 | old_write_domain = obj->write_domain; |
2943 | old_read_domains = obj->read_domains; | |
2944 | ||
e47c68e9 EA |
2945 | /* It should now be out of any other write domains, and we can update |
2946 | * the domain values for our changes. | |
2947 | */ | |
2948 | BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_GTT) != 0); | |
2949 | obj->read_domains |= I915_GEM_DOMAIN_GTT; | |
2950 | if (write) { | |
7213342d | 2951 | obj->read_domains = I915_GEM_DOMAIN_GTT; |
e47c68e9 EA |
2952 | obj->write_domain = I915_GEM_DOMAIN_GTT; |
2953 | obj_priv->dirty = 1; | |
2ef7eeaa EA |
2954 | } |
2955 | ||
1c5d22f7 CW |
2956 | trace_i915_gem_object_change_domain(obj, |
2957 | old_read_domains, | |
2958 | old_write_domain); | |
2959 | ||
e47c68e9 EA |
2960 | return 0; |
2961 | } | |
2962 | ||
b9241ea3 ZW |
2963 | /* |
2964 | * Prepare buffer for display plane. Use uninterruptible for possible flush | |
2965 | * wait, as in modesetting process we're not supposed to be interrupted. | |
2966 | */ | |
2967 | int | |
48b956c5 CW |
2968 | i915_gem_object_set_to_display_plane(struct drm_gem_object *obj, |
2969 | bool pipelined) | |
b9241ea3 | 2970 | { |
23010e43 | 2971 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
ba3d8d74 | 2972 | uint32_t old_read_domains; |
b9241ea3 ZW |
2973 | int ret; |
2974 | ||
2975 | /* Not valid to be called on unbound objects. */ | |
2976 | if (obj_priv->gtt_space == NULL) | |
2977 | return -EINVAL; | |
2978 | ||
ced270fa | 2979 | ret = i915_gem_object_flush_gpu_write_domain(obj, true); |
2dafb1e0 CW |
2980 | if (ret) |
2981 | return ret; | |
b9241ea3 | 2982 | |
ced270fa CW |
2983 | /* Currently, we are always called from an non-interruptible context. */ |
2984 | if (!pipelined) { | |
2985 | ret = i915_gem_object_wait_rendering(obj, false); | |
2986 | if (ret) | |
b9241ea3 ZW |
2987 | return ret; |
2988 | } | |
2989 | ||
b118c1e3 CW |
2990 | i915_gem_object_flush_cpu_write_domain(obj); |
2991 | ||
b9241ea3 | 2992 | old_read_domains = obj->read_domains; |
c78ec30b | 2993 | obj->read_domains |= I915_GEM_DOMAIN_GTT; |
b9241ea3 ZW |
2994 | |
2995 | trace_i915_gem_object_change_domain(obj, | |
2996 | old_read_domains, | |
ba3d8d74 | 2997 | obj->write_domain); |
b9241ea3 ZW |
2998 | |
2999 | return 0; | |
3000 | } | |
3001 | ||
e47c68e9 EA |
3002 | /** |
3003 | * Moves a single object to the CPU read, and possibly write domain. | |
3004 | * | |
3005 | * This function returns when the move is complete, including waiting on | |
3006 | * flushes to occur. | |
3007 | */ | |
3008 | static int | |
3009 | i915_gem_object_set_to_cpu_domain(struct drm_gem_object *obj, int write) | |
3010 | { | |
1c5d22f7 | 3011 | uint32_t old_write_domain, old_read_domains; |
e47c68e9 EA |
3012 | int ret; |
3013 | ||
ba3d8d74 | 3014 | ret = i915_gem_object_flush_gpu_write_domain(obj, false); |
e47c68e9 EA |
3015 | if (ret != 0) |
3016 | return ret; | |
2ef7eeaa | 3017 | |
e47c68e9 | 3018 | i915_gem_object_flush_gtt_write_domain(obj); |
2ef7eeaa | 3019 | |
e47c68e9 EA |
3020 | /* If we have a partially-valid cache of the object in the CPU, |
3021 | * finish invalidating it and free the per-page flags. | |
2ef7eeaa | 3022 | */ |
e47c68e9 | 3023 | i915_gem_object_set_to_full_cpu_read_domain(obj); |
2ef7eeaa | 3024 | |
7213342d | 3025 | if (write) { |
2cf34d7b | 3026 | ret = i915_gem_object_wait_rendering(obj, true); |
7213342d CW |
3027 | if (ret) |
3028 | return ret; | |
3029 | } | |
3030 | ||
1c5d22f7 CW |
3031 | old_write_domain = obj->write_domain; |
3032 | old_read_domains = obj->read_domains; | |
3033 | ||
e47c68e9 EA |
3034 | /* Flush the CPU cache if it's still invalid. */ |
3035 | if ((obj->read_domains & I915_GEM_DOMAIN_CPU) == 0) { | |
2ef7eeaa | 3036 | i915_gem_clflush_object(obj); |
2ef7eeaa | 3037 | |
e47c68e9 | 3038 | obj->read_domains |= I915_GEM_DOMAIN_CPU; |
2ef7eeaa EA |
3039 | } |
3040 | ||
3041 | /* It should now be out of any other write domains, and we can update | |
3042 | * the domain values for our changes. | |
3043 | */ | |
e47c68e9 EA |
3044 | BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_CPU) != 0); |
3045 | ||
3046 | /* If we're writing through the CPU, then the GPU read domains will | |
3047 | * need to be invalidated at next use. | |
3048 | */ | |
3049 | if (write) { | |
c78ec30b | 3050 | obj->read_domains = I915_GEM_DOMAIN_CPU; |
e47c68e9 EA |
3051 | obj->write_domain = I915_GEM_DOMAIN_CPU; |
3052 | } | |
2ef7eeaa | 3053 | |
1c5d22f7 CW |
3054 | trace_i915_gem_object_change_domain(obj, |
3055 | old_read_domains, | |
3056 | old_write_domain); | |
3057 | ||
2ef7eeaa EA |
3058 | return 0; |
3059 | } | |
3060 | ||
673a394b EA |
3061 | /* |
3062 | * Set the next domain for the specified object. This | |
3063 | * may not actually perform the necessary flushing/invaliding though, | |
3064 | * as that may want to be batched with other set_domain operations | |
3065 | * | |
3066 | * This is (we hope) the only really tricky part of gem. The goal | |
3067 | * is fairly simple -- track which caches hold bits of the object | |
3068 | * and make sure they remain coherent. A few concrete examples may | |
3069 | * help to explain how it works. For shorthand, we use the notation | |
3070 | * (read_domains, write_domain), e.g. (CPU, CPU) to indicate the | |
3071 | * a pair of read and write domain masks. | |
3072 | * | |
3073 | * Case 1: the batch buffer | |
3074 | * | |
3075 | * 1. Allocated | |
3076 | * 2. Written by CPU | |
3077 | * 3. Mapped to GTT | |
3078 | * 4. Read by GPU | |
3079 | * 5. Unmapped from GTT | |
3080 | * 6. Freed | |
3081 | * | |
3082 | * Let's take these a step at a time | |
3083 | * | |
3084 | * 1. Allocated | |
3085 | * Pages allocated from the kernel may still have | |
3086 | * cache contents, so we set them to (CPU, CPU) always. | |
3087 | * 2. Written by CPU (using pwrite) | |
3088 | * The pwrite function calls set_domain (CPU, CPU) and | |
3089 | * this function does nothing (as nothing changes) | |
3090 | * 3. Mapped by GTT | |
3091 | * This function asserts that the object is not | |
3092 | * currently in any GPU-based read or write domains | |
3093 | * 4. Read by GPU | |
3094 | * i915_gem_execbuffer calls set_domain (COMMAND, 0). | |
3095 | * As write_domain is zero, this function adds in the | |
3096 | * current read domains (CPU+COMMAND, 0). | |
3097 | * flush_domains is set to CPU. | |
3098 | * invalidate_domains is set to COMMAND | |
3099 | * clflush is run to get data out of the CPU caches | |
3100 | * then i915_dev_set_domain calls i915_gem_flush to | |
3101 | * emit an MI_FLUSH and drm_agp_chipset_flush | |
3102 | * 5. Unmapped from GTT | |
3103 | * i915_gem_object_unbind calls set_domain (CPU, CPU) | |
3104 | * flush_domains and invalidate_domains end up both zero | |
3105 | * so no flushing/invalidating happens | |
3106 | * 6. Freed | |
3107 | * yay, done | |
3108 | * | |
3109 | * Case 2: The shared render buffer | |
3110 | * | |
3111 | * 1. Allocated | |
3112 | * 2. Mapped to GTT | |
3113 | * 3. Read/written by GPU | |
3114 | * 4. set_domain to (CPU,CPU) | |
3115 | * 5. Read/written by CPU | |
3116 | * 6. Read/written by GPU | |
3117 | * | |
3118 | * 1. Allocated | |
3119 | * Same as last example, (CPU, CPU) | |
3120 | * 2. Mapped to GTT | |
3121 | * Nothing changes (assertions find that it is not in the GPU) | |
3122 | * 3. Read/written by GPU | |
3123 | * execbuffer calls set_domain (RENDER, RENDER) | |
3124 | * flush_domains gets CPU | |
3125 | * invalidate_domains gets GPU | |
3126 | * clflush (obj) | |
3127 | * MI_FLUSH and drm_agp_chipset_flush | |
3128 | * 4. set_domain (CPU, CPU) | |
3129 | * flush_domains gets GPU | |
3130 | * invalidate_domains gets CPU | |
3131 | * wait_rendering (obj) to make sure all drawing is complete. | |
3132 | * This will include an MI_FLUSH to get the data from GPU | |
3133 | * to memory | |
3134 | * clflush (obj) to invalidate the CPU cache | |
3135 | * Another MI_FLUSH in i915_gem_flush (eliminate this somehow?) | |
3136 | * 5. Read/written by CPU | |
3137 | * cache lines are loaded and dirtied | |
3138 | * 6. Read written by GPU | |
3139 | * Same as last GPU access | |
3140 | * | |
3141 | * Case 3: The constant buffer | |
3142 | * | |
3143 | * 1. Allocated | |
3144 | * 2. Written by CPU | |
3145 | * 3. Read by GPU | |
3146 | * 4. Updated (written) by CPU again | |
3147 | * 5. Read by GPU | |
3148 | * | |
3149 | * 1. Allocated | |
3150 | * (CPU, CPU) | |
3151 | * 2. Written by CPU | |
3152 | * (CPU, CPU) | |
3153 | * 3. Read by GPU | |
3154 | * (CPU+RENDER, 0) | |
3155 | * flush_domains = CPU | |
3156 | * invalidate_domains = RENDER | |
3157 | * clflush (obj) | |
3158 | * MI_FLUSH | |
3159 | * drm_agp_chipset_flush | |
3160 | * 4. Updated (written) by CPU again | |
3161 | * (CPU, CPU) | |
3162 | * flush_domains = 0 (no previous write domain) | |
3163 | * invalidate_domains = 0 (no new read domains) | |
3164 | * 5. Read by GPU | |
3165 | * (CPU+RENDER, 0) | |
3166 | * flush_domains = CPU | |
3167 | * invalidate_domains = RENDER | |
3168 | * clflush (obj) | |
3169 | * MI_FLUSH | |
3170 | * drm_agp_chipset_flush | |
3171 | */ | |
c0d90829 | 3172 | static void |
b6651458 | 3173 | i915_gem_object_set_to_gpu_domain(struct drm_gem_object *obj, |
0f8c6d7c CW |
3174 | struct intel_ring_buffer *ring, |
3175 | struct change_domains *cd) | |
673a394b | 3176 | { |
23010e43 | 3177 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
673a394b EA |
3178 | uint32_t invalidate_domains = 0; |
3179 | uint32_t flush_domains = 0; | |
652c393a | 3180 | |
673a394b EA |
3181 | /* |
3182 | * If the object isn't moving to a new write domain, | |
3183 | * let the object stay in multiple read domains | |
3184 | */ | |
8b0e378a EA |
3185 | if (obj->pending_write_domain == 0) |
3186 | obj->pending_read_domains |= obj->read_domains; | |
673a394b EA |
3187 | |
3188 | /* | |
3189 | * Flush the current write domain if | |
3190 | * the new read domains don't match. Invalidate | |
3191 | * any read domains which differ from the old | |
3192 | * write domain | |
3193 | */ | |
8b0e378a | 3194 | if (obj->write_domain && |
13b29289 CW |
3195 | (obj->write_domain != obj->pending_read_domains || |
3196 | obj_priv->ring != ring)) { | |
673a394b | 3197 | flush_domains |= obj->write_domain; |
8b0e378a EA |
3198 | invalidate_domains |= |
3199 | obj->pending_read_domains & ~obj->write_domain; | |
673a394b EA |
3200 | } |
3201 | /* | |
3202 | * Invalidate any read caches which may have | |
3203 | * stale data. That is, any new read domains. | |
3204 | */ | |
8b0e378a | 3205 | invalidate_domains |= obj->pending_read_domains & ~obj->read_domains; |
3d2a812a | 3206 | if ((flush_domains | invalidate_domains) & I915_GEM_DOMAIN_CPU) |
673a394b | 3207 | i915_gem_clflush_object(obj); |
673a394b | 3208 | |
4a684a41 CW |
3209 | /* blow away mappings if mapped through GTT */ |
3210 | if ((flush_domains | invalidate_domains) & I915_GEM_DOMAIN_GTT) | |
3211 | i915_gem_release_mmap(obj); | |
3212 | ||
efbeed96 EA |
3213 | /* The actual obj->write_domain will be updated with |
3214 | * pending_write_domain after we emit the accumulated flush for all | |
3215 | * of our domain changes in execbuffers (which clears objects' | |
3216 | * write_domains). So if we have a current write domain that we | |
3217 | * aren't changing, set pending_write_domain to that. | |
3218 | */ | |
3219 | if (flush_domains == 0 && obj->pending_write_domain == 0) | |
3220 | obj->pending_write_domain = obj->write_domain; | |
673a394b | 3221 | |
0f8c6d7c CW |
3222 | cd->invalidate_domains |= invalidate_domains; |
3223 | cd->flush_domains |= flush_domains; | |
b6651458 | 3224 | if (flush_domains & I915_GEM_GPU_DOMAINS) |
0f8c6d7c | 3225 | cd->flush_rings |= obj_priv->ring->id; |
b6651458 | 3226 | if (invalidate_domains & I915_GEM_GPU_DOMAINS) |
0f8c6d7c | 3227 | cd->flush_rings |= ring->id; |
673a394b EA |
3228 | } |
3229 | ||
3230 | /** | |
e47c68e9 | 3231 | * Moves the object from a partially CPU read to a full one. |
673a394b | 3232 | * |
e47c68e9 EA |
3233 | * Note that this only resolves i915_gem_object_set_cpu_read_domain_range(), |
3234 | * and doesn't handle transitioning from !(read_domains & I915_GEM_DOMAIN_CPU). | |
673a394b | 3235 | */ |
e47c68e9 EA |
3236 | static void |
3237 | i915_gem_object_set_to_full_cpu_read_domain(struct drm_gem_object *obj) | |
673a394b | 3238 | { |
23010e43 | 3239 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
673a394b | 3240 | |
e47c68e9 EA |
3241 | if (!obj_priv->page_cpu_valid) |
3242 | return; | |
3243 | ||
3244 | /* If we're partially in the CPU read domain, finish moving it in. | |
3245 | */ | |
3246 | if (obj->read_domains & I915_GEM_DOMAIN_CPU) { | |
3247 | int i; | |
3248 | ||
3249 | for (i = 0; i <= (obj->size - 1) / PAGE_SIZE; i++) { | |
3250 | if (obj_priv->page_cpu_valid[i]) | |
3251 | continue; | |
856fa198 | 3252 | drm_clflush_pages(obj_priv->pages + i, 1); |
e47c68e9 | 3253 | } |
e47c68e9 EA |
3254 | } |
3255 | ||
3256 | /* Free the page_cpu_valid mappings which are now stale, whether | |
3257 | * or not we've got I915_GEM_DOMAIN_CPU. | |
3258 | */ | |
9a298b2a | 3259 | kfree(obj_priv->page_cpu_valid); |
e47c68e9 EA |
3260 | obj_priv->page_cpu_valid = NULL; |
3261 | } | |
3262 | ||
3263 | /** | |
3264 | * Set the CPU read domain on a range of the object. | |
3265 | * | |
3266 | * The object ends up with I915_GEM_DOMAIN_CPU in its read flags although it's | |
3267 | * not entirely valid. The page_cpu_valid member of the object flags which | |
3268 | * pages have been flushed, and will be respected by | |
3269 | * i915_gem_object_set_to_cpu_domain() if it's called on to get a valid mapping | |
3270 | * of the whole object. | |
3271 | * | |
3272 | * This function returns when the move is complete, including waiting on | |
3273 | * flushes to occur. | |
3274 | */ | |
3275 | static int | |
3276 | i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object *obj, | |
3277 | uint64_t offset, uint64_t size) | |
3278 | { | |
23010e43 | 3279 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
1c5d22f7 | 3280 | uint32_t old_read_domains; |
e47c68e9 | 3281 | int i, ret; |
673a394b | 3282 | |
e47c68e9 EA |
3283 | if (offset == 0 && size == obj->size) |
3284 | return i915_gem_object_set_to_cpu_domain(obj, 0); | |
673a394b | 3285 | |
ba3d8d74 | 3286 | ret = i915_gem_object_flush_gpu_write_domain(obj, false); |
e47c68e9 | 3287 | if (ret != 0) |
6a47baa6 | 3288 | return ret; |
e47c68e9 EA |
3289 | i915_gem_object_flush_gtt_write_domain(obj); |
3290 | ||
3291 | /* If we're already fully in the CPU read domain, we're done. */ | |
3292 | if (obj_priv->page_cpu_valid == NULL && | |
3293 | (obj->read_domains & I915_GEM_DOMAIN_CPU) != 0) | |
3294 | return 0; | |
673a394b | 3295 | |
e47c68e9 EA |
3296 | /* Otherwise, create/clear the per-page CPU read domain flag if we're |
3297 | * newly adding I915_GEM_DOMAIN_CPU | |
3298 | */ | |
673a394b | 3299 | if (obj_priv->page_cpu_valid == NULL) { |
9a298b2a EA |
3300 | obj_priv->page_cpu_valid = kzalloc(obj->size / PAGE_SIZE, |
3301 | GFP_KERNEL); | |
e47c68e9 EA |
3302 | if (obj_priv->page_cpu_valid == NULL) |
3303 | return -ENOMEM; | |
3304 | } else if ((obj->read_domains & I915_GEM_DOMAIN_CPU) == 0) | |
3305 | memset(obj_priv->page_cpu_valid, 0, obj->size / PAGE_SIZE); | |
673a394b EA |
3306 | |
3307 | /* Flush the cache on any pages that are still invalid from the CPU's | |
3308 | * perspective. | |
3309 | */ | |
e47c68e9 EA |
3310 | for (i = offset / PAGE_SIZE; i <= (offset + size - 1) / PAGE_SIZE; |
3311 | i++) { | |
673a394b EA |
3312 | if (obj_priv->page_cpu_valid[i]) |
3313 | continue; | |
3314 | ||
856fa198 | 3315 | drm_clflush_pages(obj_priv->pages + i, 1); |
673a394b EA |
3316 | |
3317 | obj_priv->page_cpu_valid[i] = 1; | |
3318 | } | |
3319 | ||
e47c68e9 EA |
3320 | /* It should now be out of any other write domains, and we can update |
3321 | * the domain values for our changes. | |
3322 | */ | |
3323 | BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_CPU) != 0); | |
3324 | ||
1c5d22f7 | 3325 | old_read_domains = obj->read_domains; |
e47c68e9 EA |
3326 | obj->read_domains |= I915_GEM_DOMAIN_CPU; |
3327 | ||
1c5d22f7 CW |
3328 | trace_i915_gem_object_change_domain(obj, |
3329 | old_read_domains, | |
3330 | obj->write_domain); | |
3331 | ||
673a394b EA |
3332 | return 0; |
3333 | } | |
3334 | ||
673a394b EA |
3335 | /** |
3336 | * Pin an object to the GTT and evaluate the relocations landing in it. | |
3337 | */ | |
3338 | static int | |
9af90d19 CW |
3339 | i915_gem_execbuffer_relocate(struct drm_i915_gem_object *obj, |
3340 | struct drm_file *file_priv, | |
3341 | struct drm_i915_gem_exec_object2 *entry) | |
673a394b | 3342 | { |
9af90d19 | 3343 | struct drm_device *dev = obj->base.dev; |
0839ccb8 | 3344 | drm_i915_private_t *dev_priv = dev->dev_private; |
2549d6c2 | 3345 | struct drm_i915_gem_relocation_entry __user *user_relocs; |
9af90d19 CW |
3346 | struct drm_gem_object *target_obj = NULL; |
3347 | uint32_t target_handle = 0; | |
3348 | int i, ret = 0; | |
673a394b | 3349 | |
2549d6c2 | 3350 | user_relocs = (void __user *)(uintptr_t)entry->relocs_ptr; |
673a394b | 3351 | for (i = 0; i < entry->relocation_count; i++) { |
2549d6c2 | 3352 | struct drm_i915_gem_relocation_entry reloc; |
9af90d19 | 3353 | uint32_t target_offset; |
673a394b | 3354 | |
9af90d19 CW |
3355 | if (__copy_from_user_inatomic(&reloc, |
3356 | user_relocs+i, | |
3357 | sizeof(reloc))) { | |
3358 | ret = -EFAULT; | |
3359 | break; | |
76446cac | 3360 | } |
76446cac | 3361 | |
9af90d19 CW |
3362 | if (reloc.target_handle != target_handle) { |
3363 | drm_gem_object_unreference(target_obj); | |
673a394b | 3364 | |
9af90d19 CW |
3365 | target_obj = drm_gem_object_lookup(dev, file_priv, |
3366 | reloc.target_handle); | |
3367 | if (target_obj == NULL) { | |
3368 | ret = -ENOENT; | |
3369 | break; | |
3370 | } | |
3371 | ||
3372 | target_handle = reloc.target_handle; | |
673a394b | 3373 | } |
9af90d19 | 3374 | target_offset = to_intel_bo(target_obj)->gtt_offset; |
673a394b | 3375 | |
8542a0bb CW |
3376 | #if WATCH_RELOC |
3377 | DRM_INFO("%s: obj %p offset %08x target %d " | |
3378 | "read %08x write %08x gtt %08x " | |
3379 | "presumed %08x delta %08x\n", | |
3380 | __func__, | |
3381 | obj, | |
2549d6c2 CW |
3382 | (int) reloc.offset, |
3383 | (int) reloc.target_handle, | |
3384 | (int) reloc.read_domains, | |
3385 | (int) reloc.write_domain, | |
9af90d19 | 3386 | (int) target_offset, |
2549d6c2 CW |
3387 | (int) reloc.presumed_offset, |
3388 | reloc.delta); | |
8542a0bb CW |
3389 | #endif |
3390 | ||
673a394b EA |
3391 | /* The target buffer should have appeared before us in the |
3392 | * exec_object list, so it should have a GTT space bound by now. | |
3393 | */ | |
9af90d19 | 3394 | if (target_offset == 0) { |
673a394b | 3395 | DRM_ERROR("No GTT space found for object %d\n", |
2549d6c2 | 3396 | reloc.target_handle); |
9af90d19 CW |
3397 | ret = -EINVAL; |
3398 | break; | |
673a394b EA |
3399 | } |
3400 | ||
8542a0bb | 3401 | /* Validate that the target is in a valid r/w GPU domain */ |
2549d6c2 | 3402 | if (reloc.write_domain & (reloc.write_domain - 1)) { |
16edd550 DV |
3403 | DRM_ERROR("reloc with multiple write domains: " |
3404 | "obj %p target %d offset %d " | |
3405 | "read %08x write %08x", | |
2549d6c2 CW |
3406 | obj, reloc.target_handle, |
3407 | (int) reloc.offset, | |
3408 | reloc.read_domains, | |
3409 | reloc.write_domain); | |
9af90d19 CW |
3410 | ret = -EINVAL; |
3411 | break; | |
16edd550 | 3412 | } |
2549d6c2 CW |
3413 | if (reloc.write_domain & I915_GEM_DOMAIN_CPU || |
3414 | reloc.read_domains & I915_GEM_DOMAIN_CPU) { | |
e47c68e9 EA |
3415 | DRM_ERROR("reloc with read/write CPU domains: " |
3416 | "obj %p target %d offset %d " | |
3417 | "read %08x write %08x", | |
2549d6c2 CW |
3418 | obj, reloc.target_handle, |
3419 | (int) reloc.offset, | |
3420 | reloc.read_domains, | |
3421 | reloc.write_domain); | |
9af90d19 CW |
3422 | ret = -EINVAL; |
3423 | break; | |
e47c68e9 | 3424 | } |
2549d6c2 CW |
3425 | if (reloc.write_domain && target_obj->pending_write_domain && |
3426 | reloc.write_domain != target_obj->pending_write_domain) { | |
673a394b EA |
3427 | DRM_ERROR("Write domain conflict: " |
3428 | "obj %p target %d offset %d " | |
3429 | "new %08x old %08x\n", | |
2549d6c2 CW |
3430 | obj, reloc.target_handle, |
3431 | (int) reloc.offset, | |
3432 | reloc.write_domain, | |
673a394b | 3433 | target_obj->pending_write_domain); |
9af90d19 CW |
3434 | ret = -EINVAL; |
3435 | break; | |
673a394b EA |
3436 | } |
3437 | ||
2549d6c2 | 3438 | target_obj->pending_read_domains |= reloc.read_domains; |
878a3c37 | 3439 | target_obj->pending_write_domain |= reloc.write_domain; |
673a394b EA |
3440 | |
3441 | /* If the relocation already has the right value in it, no | |
3442 | * more work needs to be done. | |
3443 | */ | |
9af90d19 | 3444 | if (target_offset == reloc.presumed_offset) |
673a394b | 3445 | continue; |
673a394b | 3446 | |
8542a0bb | 3447 | /* Check that the relocation address is valid... */ |
9af90d19 | 3448 | if (reloc.offset > obj->base.size - 4) { |
8542a0bb CW |
3449 | DRM_ERROR("Relocation beyond object bounds: " |
3450 | "obj %p target %d offset %d size %d.\n", | |
2549d6c2 | 3451 | obj, reloc.target_handle, |
9af90d19 CW |
3452 | (int) reloc.offset, (int) obj->base.size); |
3453 | ret = -EINVAL; | |
3454 | break; | |
8542a0bb | 3455 | } |
2549d6c2 | 3456 | if (reloc.offset & 3) { |
8542a0bb CW |
3457 | DRM_ERROR("Relocation not 4-byte aligned: " |
3458 | "obj %p target %d offset %d.\n", | |
2549d6c2 CW |
3459 | obj, reloc.target_handle, |
3460 | (int) reloc.offset); | |
9af90d19 CW |
3461 | ret = -EINVAL; |
3462 | break; | |
8542a0bb CW |
3463 | } |
3464 | ||
3465 | /* and points to somewhere within the target object. */ | |
2549d6c2 | 3466 | if (reloc.delta >= target_obj->size) { |
8542a0bb CW |
3467 | DRM_ERROR("Relocation beyond target object bounds: " |
3468 | "obj %p target %d delta %d size %d.\n", | |
2549d6c2 CW |
3469 | obj, reloc.target_handle, |
3470 | (int) reloc.delta, (int) target_obj->size); | |
9af90d19 CW |
3471 | ret = -EINVAL; |
3472 | break; | |
673a394b EA |
3473 | } |
3474 | ||
9af90d19 CW |
3475 | reloc.delta += target_offset; |
3476 | if (obj->base.write_domain == I915_GEM_DOMAIN_CPU) { | |
f0c43d9b CW |
3477 | uint32_t page_offset = reloc.offset & ~PAGE_MASK; |
3478 | char *vaddr; | |
673a394b | 3479 | |
c48c43e4 | 3480 | vaddr = kmap_atomic(obj->pages[reloc.offset >> PAGE_SHIFT]); |
f0c43d9b | 3481 | *(uint32_t *)(vaddr + page_offset) = reloc.delta; |
c48c43e4 | 3482 | kunmap_atomic(vaddr); |
f0c43d9b CW |
3483 | } else { |
3484 | uint32_t __iomem *reloc_entry; | |
3485 | void __iomem *reloc_page; | |
b962442e | 3486 | |
9af90d19 CW |
3487 | ret = i915_gem_object_set_to_gtt_domain(&obj->base, 1); |
3488 | if (ret) | |
3489 | break; | |
b962442e | 3490 | |
f0c43d9b | 3491 | /* Map the page containing the relocation we're going to perform. */ |
9af90d19 | 3492 | reloc.offset += obj->gtt_offset; |
f0c43d9b | 3493 | reloc_page = io_mapping_map_atomic_wc(dev_priv->mm.gtt_mapping, |
c48c43e4 | 3494 | reloc.offset & PAGE_MASK); |
f0c43d9b CW |
3495 | reloc_entry = (uint32_t __iomem *) |
3496 | (reloc_page + (reloc.offset & ~PAGE_MASK)); | |
3497 | iowrite32(reloc.delta, reloc_entry); | |
c48c43e4 | 3498 | io_mapping_unmap_atomic(reloc_page); |
f0c43d9b | 3499 | } |
b962442e | 3500 | |
b5dc608c CW |
3501 | /* and update the user's relocation entry */ |
3502 | reloc.presumed_offset = target_offset; | |
3503 | if (__copy_to_user_inatomic(&user_relocs[i].presumed_offset, | |
3504 | &reloc.presumed_offset, | |
3505 | sizeof(reloc.presumed_offset))) { | |
3506 | ret = -EFAULT; | |
3507 | break; | |
3508 | } | |
b962442e | 3509 | } |
b962442e | 3510 | |
9af90d19 | 3511 | drm_gem_object_unreference(target_obj); |
673a394b EA |
3512 | return ret; |
3513 | } | |
3514 | ||
40a5f0de | 3515 | static int |
9af90d19 CW |
3516 | i915_gem_execbuffer_pin(struct drm_device *dev, |
3517 | struct drm_file *file, | |
3518 | struct drm_gem_object **object_list, | |
3519 | struct drm_i915_gem_exec_object2 *exec_list, | |
3520 | int count) | |
40a5f0de | 3521 | { |
9af90d19 CW |
3522 | struct drm_i915_private *dev_priv = dev->dev_private; |
3523 | int ret, i, retry; | |
40a5f0de | 3524 | |
9af90d19 | 3525 | /* attempt to pin all of the buffers into the GTT */ |
5eac3ab4 CW |
3526 | retry = 0; |
3527 | do { | |
9af90d19 CW |
3528 | ret = 0; |
3529 | for (i = 0; i < count; i++) { | |
3530 | struct drm_i915_gem_exec_object2 *entry = &exec_list[i]; | |
16e809ac | 3531 | struct drm_i915_gem_object *obj = to_intel_bo(object_list[i]); |
9af90d19 CW |
3532 | bool need_fence = |
3533 | entry->flags & EXEC_OBJECT_NEEDS_FENCE && | |
3534 | obj->tiling_mode != I915_TILING_NONE; | |
3535 | ||
16e809ac DV |
3536 | /* g33/pnv can't fence buffers in the unmappable part */ |
3537 | bool need_mappable = | |
3538 | entry->relocation_count ? true : need_fence; | |
3539 | ||
9af90d19 | 3540 | /* Check fence reg constraints and rebind if necessary */ |
a00b10c3 CW |
3541 | if ((need_fence && !obj->fenceable) || |
3542 | (need_mappable && !obj->mappable)) { | |
9af90d19 CW |
3543 | ret = i915_gem_object_unbind(&obj->base); |
3544 | if (ret) | |
3545 | break; | |
3546 | } | |
40a5f0de | 3547 | |
920afa77 | 3548 | ret = i915_gem_object_pin(&obj->base, |
16e809ac | 3549 | entry->alignment, |
a00b10c3 CW |
3550 | need_mappable, |
3551 | need_fence); | |
9af90d19 CW |
3552 | if (ret) |
3553 | break; | |
40a5f0de | 3554 | |
9af90d19 CW |
3555 | /* |
3556 | * Pre-965 chips need a fence register set up in order | |
3557 | * to properly handle blits to/from tiled surfaces. | |
3558 | */ | |
3559 | if (need_fence) { | |
3560 | ret = i915_gem_object_get_fence_reg(&obj->base, true); | |
3561 | if (ret) { | |
3562 | i915_gem_object_unpin(&obj->base); | |
3563 | break; | |
3564 | } | |
40a5f0de | 3565 | |
9af90d19 CW |
3566 | dev_priv->fence_regs[obj->fence_reg].gpu = true; |
3567 | } | |
40a5f0de | 3568 | |
9af90d19 | 3569 | entry->offset = obj->gtt_offset; |
40a5f0de EA |
3570 | } |
3571 | ||
9af90d19 CW |
3572 | while (i--) |
3573 | i915_gem_object_unpin(object_list[i]); | |
3574 | ||
5eac3ab4 | 3575 | if (ret != -ENOSPC || retry > 1) |
9af90d19 CW |
3576 | return ret; |
3577 | ||
5eac3ab4 CW |
3578 | /* First attempt, just clear anything that is purgeable. |
3579 | * Second attempt, clear the entire GTT. | |
3580 | */ | |
3581 | ret = i915_gem_evict_everything(dev, retry == 0); | |
9af90d19 CW |
3582 | if (ret) |
3583 | return ret; | |
40a5f0de | 3584 | |
5eac3ab4 CW |
3585 | retry++; |
3586 | } while (1); | |
40a5f0de EA |
3587 | } |
3588 | ||
13b29289 CW |
3589 | static int |
3590 | i915_gem_execbuffer_move_to_gpu(struct drm_device *dev, | |
3591 | struct drm_file *file, | |
3592 | struct intel_ring_buffer *ring, | |
3593 | struct drm_gem_object **objects, | |
3594 | int count) | |
3595 | { | |
0f8c6d7c | 3596 | struct change_domains cd; |
13b29289 CW |
3597 | int ret, i; |
3598 | ||
0f8c6d7c CW |
3599 | cd.invalidate_domains = 0; |
3600 | cd.flush_domains = 0; | |
3601 | cd.flush_rings = 0; | |
13b29289 | 3602 | for (i = 0; i < count; i++) |
0f8c6d7c | 3603 | i915_gem_object_set_to_gpu_domain(objects[i], ring, &cd); |
13b29289 | 3604 | |
0f8c6d7c | 3605 | if (cd.invalidate_domains | cd.flush_domains) { |
13b29289 CW |
3606 | #if WATCH_EXEC |
3607 | DRM_INFO("%s: invalidate_domains %08x flush_domains %08x\n", | |
3608 | __func__, | |
0f8c6d7c CW |
3609 | cd.invalidate_domains, |
3610 | cd.flush_domains); | |
13b29289 CW |
3611 | #endif |
3612 | i915_gem_flush(dev, file, | |
0f8c6d7c CW |
3613 | cd.invalidate_domains, |
3614 | cd.flush_domains, | |
3615 | cd.flush_rings); | |
13b29289 CW |
3616 | } |
3617 | ||
3618 | for (i = 0; i < count; i++) { | |
3619 | struct drm_i915_gem_object *obj = to_intel_bo(objects[i]); | |
3620 | /* XXX replace with semaphores */ | |
3621 | if (obj->ring && ring != obj->ring) { | |
3622 | ret = i915_gem_object_wait_rendering(&obj->base, true); | |
3623 | if (ret) | |
3624 | return ret; | |
3625 | } | |
3626 | } | |
3627 | ||
3628 | return 0; | |
3629 | } | |
3630 | ||
673a394b EA |
3631 | /* Throttle our rendering by waiting until the ring has completed our requests |
3632 | * emitted over 20 msec ago. | |
3633 | * | |
b962442e EA |
3634 | * Note that if we were to use the current jiffies each time around the loop, |
3635 | * we wouldn't escape the function with any frames outstanding if the time to | |
3636 | * render a frame was over 20ms. | |
3637 | * | |
673a394b EA |
3638 | * This should get us reasonable parallelism between CPU and GPU but also |
3639 | * relatively low latency when blocking on a particular request to finish. | |
3640 | */ | |
40a5f0de | 3641 | static int |
f787a5f5 | 3642 | i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file) |
40a5f0de | 3643 | { |
f787a5f5 CW |
3644 | struct drm_i915_private *dev_priv = dev->dev_private; |
3645 | struct drm_i915_file_private *file_priv = file->driver_priv; | |
b962442e | 3646 | unsigned long recent_enough = jiffies - msecs_to_jiffies(20); |
f787a5f5 CW |
3647 | struct drm_i915_gem_request *request; |
3648 | struct intel_ring_buffer *ring = NULL; | |
3649 | u32 seqno = 0; | |
3650 | int ret; | |
93533c29 | 3651 | |
1c25595f | 3652 | spin_lock(&file_priv->mm.lock); |
f787a5f5 | 3653 | list_for_each_entry(request, &file_priv->mm.request_list, client_list) { |
b962442e EA |
3654 | if (time_after_eq(request->emitted_jiffies, recent_enough)) |
3655 | break; | |
40a5f0de | 3656 | |
f787a5f5 CW |
3657 | ring = request->ring; |
3658 | seqno = request->seqno; | |
b962442e | 3659 | } |
1c25595f | 3660 | spin_unlock(&file_priv->mm.lock); |
40a5f0de | 3661 | |
f787a5f5 CW |
3662 | if (seqno == 0) |
3663 | return 0; | |
2bc43b5c | 3664 | |
f787a5f5 | 3665 | ret = 0; |
78501eac | 3666 | if (!i915_seqno_passed(ring->get_seqno(ring), seqno)) { |
f787a5f5 CW |
3667 | /* And wait for the seqno passing without holding any locks and |
3668 | * causing extra latency for others. This is safe as the irq | |
3669 | * generation is designed to be run atomically and so is | |
3670 | * lockless. | |
3671 | */ | |
78501eac | 3672 | ring->user_irq_get(ring); |
f787a5f5 | 3673 | ret = wait_event_interruptible(ring->irq_queue, |
78501eac | 3674 | i915_seqno_passed(ring->get_seqno(ring), seqno) |
f787a5f5 | 3675 | || atomic_read(&dev_priv->mm.wedged)); |
78501eac | 3676 | ring->user_irq_put(ring); |
40a5f0de | 3677 | |
f787a5f5 CW |
3678 | if (ret == 0 && atomic_read(&dev_priv->mm.wedged)) |
3679 | ret = -EIO; | |
40a5f0de EA |
3680 | } |
3681 | ||
f787a5f5 CW |
3682 | if (ret == 0) |
3683 | queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, 0); | |
40a5f0de EA |
3684 | |
3685 | return ret; | |
3686 | } | |
3687 | ||
83d60795 | 3688 | static int |
2549d6c2 CW |
3689 | i915_gem_check_execbuffer(struct drm_i915_gem_execbuffer2 *exec, |
3690 | uint64_t exec_offset) | |
83d60795 CW |
3691 | { |
3692 | uint32_t exec_start, exec_len; | |
3693 | ||
3694 | exec_start = (uint32_t) exec_offset + exec->batch_start_offset; | |
3695 | exec_len = (uint32_t) exec->batch_len; | |
3696 | ||
3697 | if ((exec_start | exec_len) & 0x7) | |
3698 | return -EINVAL; | |
3699 | ||
3700 | if (!exec_start) | |
3701 | return -EINVAL; | |
3702 | ||
3703 | return 0; | |
3704 | } | |
3705 | ||
6b95a207 | 3706 | static int |
2549d6c2 CW |
3707 | validate_exec_list(struct drm_i915_gem_exec_object2 *exec, |
3708 | int count) | |
6b95a207 | 3709 | { |
2549d6c2 | 3710 | int i; |
6b95a207 | 3711 | |
2549d6c2 CW |
3712 | for (i = 0; i < count; i++) { |
3713 | char __user *ptr = (char __user *)(uintptr_t)exec[i].relocs_ptr; | |
3714 | size_t length = exec[i].relocation_count * sizeof(struct drm_i915_gem_relocation_entry); | |
6b95a207 | 3715 | |
2549d6c2 CW |
3716 | if (!access_ok(VERIFY_READ, ptr, length)) |
3717 | return -EFAULT; | |
40a5f0de | 3718 | |
b5dc608c CW |
3719 | /* we may also need to update the presumed offsets */ |
3720 | if (!access_ok(VERIFY_WRITE, ptr, length)) | |
3721 | return -EFAULT; | |
3722 | ||
2549d6c2 CW |
3723 | if (fault_in_pages_readable(ptr, length)) |
3724 | return -EFAULT; | |
6b95a207 | 3725 | } |
6b95a207 | 3726 | |
83d60795 | 3727 | return 0; |
6b95a207 KH |
3728 | } |
3729 | ||
8dc5d147 | 3730 | static int |
76446cac | 3731 | i915_gem_do_execbuffer(struct drm_device *dev, void *data, |
9af90d19 | 3732 | struct drm_file *file, |
76446cac JB |
3733 | struct drm_i915_gem_execbuffer2 *args, |
3734 | struct drm_i915_gem_exec_object2 *exec_list) | |
673a394b EA |
3735 | { |
3736 | drm_i915_private_t *dev_priv = dev->dev_private; | |
673a394b EA |
3737 | struct drm_gem_object **object_list = NULL; |
3738 | struct drm_gem_object *batch_obj; | |
201361a5 | 3739 | struct drm_clip_rect *cliprects = NULL; |
8dc5d147 | 3740 | struct drm_i915_gem_request *request = NULL; |
9af90d19 | 3741 | int ret, i, flips; |
673a394b | 3742 | uint64_t exec_offset; |
673a394b | 3743 | |
852835f3 ZN |
3744 | struct intel_ring_buffer *ring = NULL; |
3745 | ||
30dbf0c0 CW |
3746 | ret = i915_gem_check_is_wedged(dev); |
3747 | if (ret) | |
3748 | return ret; | |
3749 | ||
2549d6c2 CW |
3750 | ret = validate_exec_list(exec_list, args->buffer_count); |
3751 | if (ret) | |
3752 | return ret; | |
3753 | ||
673a394b EA |
3754 | #if WATCH_EXEC |
3755 | DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n", | |
3756 | (int) args->buffers_ptr, args->buffer_count, args->batch_len); | |
3757 | #endif | |
549f7365 CW |
3758 | switch (args->flags & I915_EXEC_RING_MASK) { |
3759 | case I915_EXEC_DEFAULT: | |
3760 | case I915_EXEC_RENDER: | |
3761 | ring = &dev_priv->render_ring; | |
3762 | break; | |
3763 | case I915_EXEC_BSD: | |
d1b851fc | 3764 | if (!HAS_BSD(dev)) { |
549f7365 | 3765 | DRM_ERROR("execbuf with invalid ring (BSD)\n"); |
d1b851fc ZN |
3766 | return -EINVAL; |
3767 | } | |
3768 | ring = &dev_priv->bsd_ring; | |
549f7365 CW |
3769 | break; |
3770 | case I915_EXEC_BLT: | |
3771 | if (!HAS_BLT(dev)) { | |
3772 | DRM_ERROR("execbuf with invalid ring (BLT)\n"); | |
3773 | return -EINVAL; | |
3774 | } | |
3775 | ring = &dev_priv->blt_ring; | |
3776 | break; | |
3777 | default: | |
3778 | DRM_ERROR("execbuf with unknown ring: %d\n", | |
3779 | (int)(args->flags & I915_EXEC_RING_MASK)); | |
3780 | return -EINVAL; | |
d1b851fc ZN |
3781 | } |
3782 | ||
4f481ed2 EA |
3783 | if (args->buffer_count < 1) { |
3784 | DRM_ERROR("execbuf with %d buffers\n", args->buffer_count); | |
3785 | return -EINVAL; | |
3786 | } | |
c8e0f93a | 3787 | object_list = drm_malloc_ab(sizeof(*object_list), args->buffer_count); |
76446cac JB |
3788 | if (object_list == NULL) { |
3789 | DRM_ERROR("Failed to allocate object list for %d buffers\n", | |
673a394b EA |
3790 | args->buffer_count); |
3791 | ret = -ENOMEM; | |
3792 | goto pre_mutex_err; | |
3793 | } | |
673a394b | 3794 | |
201361a5 | 3795 | if (args->num_cliprects != 0) { |
9a298b2a EA |
3796 | cliprects = kcalloc(args->num_cliprects, sizeof(*cliprects), |
3797 | GFP_KERNEL); | |
a40e8d31 OA |
3798 | if (cliprects == NULL) { |
3799 | ret = -ENOMEM; | |
201361a5 | 3800 | goto pre_mutex_err; |
a40e8d31 | 3801 | } |
201361a5 EA |
3802 | |
3803 | ret = copy_from_user(cliprects, | |
3804 | (struct drm_clip_rect __user *) | |
3805 | (uintptr_t) args->cliprects_ptr, | |
3806 | sizeof(*cliprects) * args->num_cliprects); | |
3807 | if (ret != 0) { | |
3808 | DRM_ERROR("copy %d cliprects failed: %d\n", | |
3809 | args->num_cliprects, ret); | |
c877cdce | 3810 | ret = -EFAULT; |
201361a5 EA |
3811 | goto pre_mutex_err; |
3812 | } | |
3813 | } | |
3814 | ||
8dc5d147 CW |
3815 | request = kzalloc(sizeof(*request), GFP_KERNEL); |
3816 | if (request == NULL) { | |
3817 | ret = -ENOMEM; | |
40a5f0de | 3818 | goto pre_mutex_err; |
8dc5d147 | 3819 | } |
40a5f0de | 3820 | |
76c1dec1 CW |
3821 | ret = i915_mutex_lock_interruptible(dev); |
3822 | if (ret) | |
a198bc80 | 3823 | goto pre_mutex_err; |
673a394b EA |
3824 | |
3825 | if (dev_priv->mm.suspended) { | |
673a394b | 3826 | mutex_unlock(&dev->struct_mutex); |
a198bc80 CW |
3827 | ret = -EBUSY; |
3828 | goto pre_mutex_err; | |
673a394b EA |
3829 | } |
3830 | ||
ac94a962 | 3831 | /* Look up object handles */ |
673a394b | 3832 | for (i = 0; i < args->buffer_count; i++) { |
7e318e18 CW |
3833 | struct drm_i915_gem_object *obj_priv; |
3834 | ||
9af90d19 | 3835 | object_list[i] = drm_gem_object_lookup(dev, file, |
673a394b EA |
3836 | exec_list[i].handle); |
3837 | if (object_list[i] == NULL) { | |
3838 | DRM_ERROR("Invalid object handle %d at index %d\n", | |
3839 | exec_list[i].handle, i); | |
0ce907f8 CW |
3840 | /* prevent error path from reading uninitialized data */ |
3841 | args->buffer_count = i + 1; | |
bf79cb91 | 3842 | ret = -ENOENT; |
673a394b EA |
3843 | goto err; |
3844 | } | |
b70d11da | 3845 | |
23010e43 | 3846 | obj_priv = to_intel_bo(object_list[i]); |
b70d11da KH |
3847 | if (obj_priv->in_execbuffer) { |
3848 | DRM_ERROR("Object %p appears more than once in object list\n", | |
3849 | object_list[i]); | |
0ce907f8 CW |
3850 | /* prevent error path from reading uninitialized data */ |
3851 | args->buffer_count = i + 1; | |
bf79cb91 | 3852 | ret = -EINVAL; |
b70d11da KH |
3853 | goto err; |
3854 | } | |
3855 | obj_priv->in_execbuffer = true; | |
ac94a962 | 3856 | } |
673a394b | 3857 | |
9af90d19 CW |
3858 | /* Move the objects en-masse into the GTT, evicting if necessary. */ |
3859 | ret = i915_gem_execbuffer_pin(dev, file, | |
3860 | object_list, exec_list, | |
3861 | args->buffer_count); | |
3862 | if (ret) | |
3863 | goto err; | |
ac94a962 | 3864 | |
9af90d19 CW |
3865 | /* The objects are in their final locations, apply the relocations. */ |
3866 | for (i = 0; i < args->buffer_count; i++) { | |
3867 | struct drm_i915_gem_object *obj = to_intel_bo(object_list[i]); | |
3868 | obj->base.pending_read_domains = 0; | |
3869 | obj->base.pending_write_domain = 0; | |
3870 | ret = i915_gem_execbuffer_relocate(obj, file, &exec_list[i]); | |
3871 | if (ret) | |
ac94a962 | 3872 | goto err; |
673a394b EA |
3873 | } |
3874 | ||
3875 | /* Set the pending read domains for the batch buffer to COMMAND */ | |
3876 | batch_obj = object_list[args->buffer_count-1]; | |
5f26a2c7 CW |
3877 | if (batch_obj->pending_write_domain) { |
3878 | DRM_ERROR("Attempting to use self-modifying batch buffer\n"); | |
3879 | ret = -EINVAL; | |
3880 | goto err; | |
3881 | } | |
3882 | batch_obj->pending_read_domains |= I915_GEM_DOMAIN_COMMAND; | |
673a394b | 3883 | |
9af90d19 CW |
3884 | /* Sanity check the batch buffer */ |
3885 | exec_offset = to_intel_bo(batch_obj)->gtt_offset; | |
3886 | ret = i915_gem_check_execbuffer(args, exec_offset); | |
83d60795 CW |
3887 | if (ret != 0) { |
3888 | DRM_ERROR("execbuf with invalid offset/length\n"); | |
3889 | goto err; | |
3890 | } | |
3891 | ||
13b29289 CW |
3892 | ret = i915_gem_execbuffer_move_to_gpu(dev, file, ring, |
3893 | object_list, args->buffer_count); | |
3894 | if (ret) | |
3895 | goto err; | |
673a394b | 3896 | |
673a394b EA |
3897 | #if WATCH_COHERENCY |
3898 | for (i = 0; i < args->buffer_count; i++) { | |
3899 | i915_gem_object_check_coherency(object_list[i], | |
3900 | exec_list[i].handle); | |
3901 | } | |
3902 | #endif | |
3903 | ||
673a394b | 3904 | #if WATCH_EXEC |
6911a9b8 | 3905 | i915_gem_dump_object(batch_obj, |
673a394b EA |
3906 | args->batch_len, |
3907 | __func__, | |
3908 | ~0); | |
3909 | #endif | |
3910 | ||
e59f2bac CW |
3911 | /* Check for any pending flips. As we only maintain a flip queue depth |
3912 | * of 1, we can simply insert a WAIT for the next display flip prior | |
3913 | * to executing the batch and avoid stalling the CPU. | |
3914 | */ | |
3915 | flips = 0; | |
3916 | for (i = 0; i < args->buffer_count; i++) { | |
3917 | if (object_list[i]->write_domain) | |
3918 | flips |= atomic_read(&to_intel_bo(object_list[i])->pending_flip); | |
3919 | } | |
3920 | if (flips) { | |
3921 | int plane, flip_mask; | |
3922 | ||
3923 | for (plane = 0; flips >> plane; plane++) { | |
3924 | if (((flips >> plane) & 1) == 0) | |
3925 | continue; | |
3926 | ||
3927 | if (plane) | |
3928 | flip_mask = MI_WAIT_FOR_PLANE_B_FLIP; | |
3929 | else | |
3930 | flip_mask = MI_WAIT_FOR_PLANE_A_FLIP; | |
3931 | ||
e1f99ce6 CW |
3932 | ret = intel_ring_begin(ring, 2); |
3933 | if (ret) | |
3934 | goto err; | |
3935 | ||
78501eac CW |
3936 | intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask); |
3937 | intel_ring_emit(ring, MI_NOOP); | |
3938 | intel_ring_advance(ring); | |
e59f2bac CW |
3939 | } |
3940 | } | |
3941 | ||
673a394b | 3942 | /* Exec the batchbuffer */ |
78501eac | 3943 | ret = ring->dispatch_execbuffer(ring, args, cliprects, exec_offset); |
673a394b EA |
3944 | if (ret) { |
3945 | DRM_ERROR("dispatch failed %d\n", ret); | |
3946 | goto err; | |
3947 | } | |
3948 | ||
673a394b EA |
3949 | for (i = 0; i < args->buffer_count; i++) { |
3950 | struct drm_gem_object *obj = object_list[i]; | |
673a394b | 3951 | |
7e318e18 CW |
3952 | obj->read_domains = obj->pending_read_domains; |
3953 | obj->write_domain = obj->pending_write_domain; | |
3954 | ||
617dbe27 | 3955 | i915_gem_object_move_to_active(obj, ring); |
7e318e18 CW |
3956 | if (obj->write_domain) { |
3957 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); | |
3958 | obj_priv->dirty = 1; | |
3959 | list_move_tail(&obj_priv->gpu_write_list, | |
64193406 | 3960 | &ring->gpu_write_list); |
7e318e18 CW |
3961 | intel_mark_busy(dev, obj); |
3962 | } | |
3963 | ||
3964 | trace_i915_gem_object_change_domain(obj, | |
3965 | obj->read_domains, | |
3966 | obj->write_domain); | |
673a394b | 3967 | } |
673a394b | 3968 | |
7e318e18 CW |
3969 | /* |
3970 | * Ensure that the commands in the batch buffer are | |
3971 | * finished before the interrupt fires | |
3972 | */ | |
3973 | i915_retire_commands(dev, ring); | |
3974 | ||
3cce469c CW |
3975 | if (i915_add_request(dev, file, request, ring)) |
3976 | ring->outstanding_lazy_request = true; | |
3977 | else | |
3978 | request = NULL; | |
673a394b | 3979 | |
673a394b | 3980 | err: |
b70d11da | 3981 | for (i = 0; i < args->buffer_count; i++) { |
7e318e18 CW |
3982 | if (object_list[i] == NULL) |
3983 | break; | |
3984 | ||
3985 | to_intel_bo(object_list[i])->in_execbuffer = false; | |
aad87dff | 3986 | drm_gem_object_unreference(object_list[i]); |
b70d11da | 3987 | } |
673a394b | 3988 | |
673a394b EA |
3989 | mutex_unlock(&dev->struct_mutex); |
3990 | ||
93533c29 | 3991 | pre_mutex_err: |
8e7d2b2c | 3992 | drm_free_large(object_list); |
9a298b2a | 3993 | kfree(cliprects); |
8dc5d147 | 3994 | kfree(request); |
673a394b EA |
3995 | |
3996 | return ret; | |
3997 | } | |
3998 | ||
76446cac JB |
3999 | /* |
4000 | * Legacy execbuffer just creates an exec2 list from the original exec object | |
4001 | * list array and passes it to the real function. | |
4002 | */ | |
4003 | int | |
4004 | i915_gem_execbuffer(struct drm_device *dev, void *data, | |
4005 | struct drm_file *file_priv) | |
4006 | { | |
4007 | struct drm_i915_gem_execbuffer *args = data; | |
4008 | struct drm_i915_gem_execbuffer2 exec2; | |
4009 | struct drm_i915_gem_exec_object *exec_list = NULL; | |
4010 | struct drm_i915_gem_exec_object2 *exec2_list = NULL; | |
4011 | int ret, i; | |
4012 | ||
4013 | #if WATCH_EXEC | |
4014 | DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n", | |
4015 | (int) args->buffers_ptr, args->buffer_count, args->batch_len); | |
4016 | #endif | |
4017 | ||
4018 | if (args->buffer_count < 1) { | |
4019 | DRM_ERROR("execbuf with %d buffers\n", args->buffer_count); | |
4020 | return -EINVAL; | |
4021 | } | |
4022 | ||
4023 | /* Copy in the exec list from userland */ | |
4024 | exec_list = drm_malloc_ab(sizeof(*exec_list), args->buffer_count); | |
4025 | exec2_list = drm_malloc_ab(sizeof(*exec2_list), args->buffer_count); | |
4026 | if (exec_list == NULL || exec2_list == NULL) { | |
4027 | DRM_ERROR("Failed to allocate exec list for %d buffers\n", | |
4028 | args->buffer_count); | |
4029 | drm_free_large(exec_list); | |
4030 | drm_free_large(exec2_list); | |
4031 | return -ENOMEM; | |
4032 | } | |
4033 | ret = copy_from_user(exec_list, | |
4034 | (struct drm_i915_relocation_entry __user *) | |
4035 | (uintptr_t) args->buffers_ptr, | |
4036 | sizeof(*exec_list) * args->buffer_count); | |
4037 | if (ret != 0) { | |
4038 | DRM_ERROR("copy %d exec entries failed %d\n", | |
4039 | args->buffer_count, ret); | |
4040 | drm_free_large(exec_list); | |
4041 | drm_free_large(exec2_list); | |
4042 | return -EFAULT; | |
4043 | } | |
4044 | ||
4045 | for (i = 0; i < args->buffer_count; i++) { | |
4046 | exec2_list[i].handle = exec_list[i].handle; | |
4047 | exec2_list[i].relocation_count = exec_list[i].relocation_count; | |
4048 | exec2_list[i].relocs_ptr = exec_list[i].relocs_ptr; | |
4049 | exec2_list[i].alignment = exec_list[i].alignment; | |
4050 | exec2_list[i].offset = exec_list[i].offset; | |
a6c45cf0 | 4051 | if (INTEL_INFO(dev)->gen < 4) |
76446cac JB |
4052 | exec2_list[i].flags = EXEC_OBJECT_NEEDS_FENCE; |
4053 | else | |
4054 | exec2_list[i].flags = 0; | |
4055 | } | |
4056 | ||
4057 | exec2.buffers_ptr = args->buffers_ptr; | |
4058 | exec2.buffer_count = args->buffer_count; | |
4059 | exec2.batch_start_offset = args->batch_start_offset; | |
4060 | exec2.batch_len = args->batch_len; | |
4061 | exec2.DR1 = args->DR1; | |
4062 | exec2.DR4 = args->DR4; | |
4063 | exec2.num_cliprects = args->num_cliprects; | |
4064 | exec2.cliprects_ptr = args->cliprects_ptr; | |
852835f3 | 4065 | exec2.flags = I915_EXEC_RENDER; |
76446cac JB |
4066 | |
4067 | ret = i915_gem_do_execbuffer(dev, data, file_priv, &exec2, exec2_list); | |
4068 | if (!ret) { | |
4069 | /* Copy the new buffer offsets back to the user's exec list. */ | |
4070 | for (i = 0; i < args->buffer_count; i++) | |
4071 | exec_list[i].offset = exec2_list[i].offset; | |
4072 | /* ... and back out to userspace */ | |
4073 | ret = copy_to_user((struct drm_i915_relocation_entry __user *) | |
4074 | (uintptr_t) args->buffers_ptr, | |
4075 | exec_list, | |
4076 | sizeof(*exec_list) * args->buffer_count); | |
4077 | if (ret) { | |
4078 | ret = -EFAULT; | |
4079 | DRM_ERROR("failed to copy %d exec entries " | |
4080 | "back to user (%d)\n", | |
4081 | args->buffer_count, ret); | |
4082 | } | |
76446cac JB |
4083 | } |
4084 | ||
4085 | drm_free_large(exec_list); | |
4086 | drm_free_large(exec2_list); | |
4087 | return ret; | |
4088 | } | |
4089 | ||
4090 | int | |
4091 | i915_gem_execbuffer2(struct drm_device *dev, void *data, | |
4092 | struct drm_file *file_priv) | |
4093 | { | |
4094 | struct drm_i915_gem_execbuffer2 *args = data; | |
4095 | struct drm_i915_gem_exec_object2 *exec2_list = NULL; | |
4096 | int ret; | |
4097 | ||
4098 | #if WATCH_EXEC | |
4099 | DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n", | |
4100 | (int) args->buffers_ptr, args->buffer_count, args->batch_len); | |
4101 | #endif | |
4102 | ||
4103 | if (args->buffer_count < 1) { | |
4104 | DRM_ERROR("execbuf2 with %d buffers\n", args->buffer_count); | |
4105 | return -EINVAL; | |
4106 | } | |
4107 | ||
4108 | exec2_list = drm_malloc_ab(sizeof(*exec2_list), args->buffer_count); | |
4109 | if (exec2_list == NULL) { | |
4110 | DRM_ERROR("Failed to allocate exec list for %d buffers\n", | |
4111 | args->buffer_count); | |
4112 | return -ENOMEM; | |
4113 | } | |
4114 | ret = copy_from_user(exec2_list, | |
4115 | (struct drm_i915_relocation_entry __user *) | |
4116 | (uintptr_t) args->buffers_ptr, | |
4117 | sizeof(*exec2_list) * args->buffer_count); | |
4118 | if (ret != 0) { | |
4119 | DRM_ERROR("copy %d exec entries failed %d\n", | |
4120 | args->buffer_count, ret); | |
4121 | drm_free_large(exec2_list); | |
4122 | return -EFAULT; | |
4123 | } | |
4124 | ||
4125 | ret = i915_gem_do_execbuffer(dev, data, file_priv, args, exec2_list); | |
4126 | if (!ret) { | |
4127 | /* Copy the new buffer offsets back to the user's exec list. */ | |
4128 | ret = copy_to_user((struct drm_i915_relocation_entry __user *) | |
4129 | (uintptr_t) args->buffers_ptr, | |
4130 | exec2_list, | |
4131 | sizeof(*exec2_list) * args->buffer_count); | |
4132 | if (ret) { | |
4133 | ret = -EFAULT; | |
4134 | DRM_ERROR("failed to copy %d exec entries " | |
4135 | "back to user (%d)\n", | |
4136 | args->buffer_count, ret); | |
4137 | } | |
4138 | } | |
4139 | ||
4140 | drm_free_large(exec2_list); | |
4141 | return ret; | |
4142 | } | |
4143 | ||
673a394b | 4144 | int |
920afa77 | 4145 | i915_gem_object_pin(struct drm_gem_object *obj, uint32_t alignment, |
a00b10c3 | 4146 | bool mappable, bool need_fence) |
673a394b EA |
4147 | { |
4148 | struct drm_device *dev = obj->dev; | |
f13d3f73 | 4149 | struct drm_i915_private *dev_priv = dev->dev_private; |
23010e43 | 4150 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
673a394b EA |
4151 | int ret; |
4152 | ||
778c3544 | 4153 | BUG_ON(obj_priv->pin_count == DRM_I915_GEM_OBJECT_MAX_PIN_COUNT); |
085ce264 | 4154 | BUG_ON(need_fence && !mappable); |
23bc5982 | 4155 | WARN_ON(i915_verify_lists(dev)); |
ac0c6b5a CW |
4156 | |
4157 | if (obj_priv->gtt_space != NULL) { | |
a00b10c3 CW |
4158 | if ((alignment && obj_priv->gtt_offset & (alignment - 1)) || |
4159 | (need_fence && !obj_priv->fenceable) || | |
4160 | (mappable && !obj_priv->mappable)) { | |
ae7d49d8 CW |
4161 | WARN(obj_priv->pin_count, |
4162 | "bo is already pinned with incorrect alignment:" | |
a00b10c3 CW |
4163 | " offset=%x, req.alignment=%x, need_fence=%d, fenceable=%d, mappable=%d, cpu_accessible=%d\n", |
4164 | obj_priv->gtt_offset, alignment, | |
4165 | need_fence, obj_priv->fenceable, | |
4166 | mappable, obj_priv->mappable); | |
ac0c6b5a CW |
4167 | ret = i915_gem_object_unbind(obj); |
4168 | if (ret) | |
4169 | return ret; | |
4170 | } | |
4171 | } | |
4172 | ||
673a394b | 4173 | if (obj_priv->gtt_space == NULL) { |
a00b10c3 CW |
4174 | ret = i915_gem_object_bind_to_gtt(obj, alignment, |
4175 | mappable, need_fence); | |
9731129c | 4176 | if (ret) |
673a394b | 4177 | return ret; |
22c344e9 | 4178 | } |
76446cac | 4179 | |
7465378f | 4180 | if (obj_priv->pin_count++ == 0) { |
a00b10c3 | 4181 | i915_gem_info_add_pin(dev_priv, obj_priv, mappable); |
f13d3f73 | 4182 | if (!obj_priv->active) |
69dc4987 | 4183 | list_move_tail(&obj_priv->mm_list, |
f13d3f73 | 4184 | &dev_priv->mm.pinned_list); |
673a394b | 4185 | } |
fb7d516a | 4186 | BUG_ON(!obj_priv->pin_mappable && mappable); |
673a394b | 4187 | |
23bc5982 | 4188 | WARN_ON(i915_verify_lists(dev)); |
673a394b EA |
4189 | return 0; |
4190 | } | |
4191 | ||
4192 | void | |
4193 | i915_gem_object_unpin(struct drm_gem_object *obj) | |
4194 | { | |
4195 | struct drm_device *dev = obj->dev; | |
4196 | drm_i915_private_t *dev_priv = dev->dev_private; | |
23010e43 | 4197 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
673a394b | 4198 | |
23bc5982 | 4199 | WARN_ON(i915_verify_lists(dev)); |
7465378f | 4200 | BUG_ON(obj_priv->pin_count == 0); |
673a394b EA |
4201 | BUG_ON(obj_priv->gtt_space == NULL); |
4202 | ||
7465378f | 4203 | if (--obj_priv->pin_count == 0) { |
f13d3f73 | 4204 | if (!obj_priv->active) |
69dc4987 | 4205 | list_move_tail(&obj_priv->mm_list, |
673a394b | 4206 | &dev_priv->mm.inactive_list); |
a00b10c3 | 4207 | i915_gem_info_remove_pin(dev_priv, obj_priv); |
673a394b | 4208 | } |
23bc5982 | 4209 | WARN_ON(i915_verify_lists(dev)); |
673a394b EA |
4210 | } |
4211 | ||
4212 | int | |
4213 | i915_gem_pin_ioctl(struct drm_device *dev, void *data, | |
4214 | struct drm_file *file_priv) | |
4215 | { | |
4216 | struct drm_i915_gem_pin *args = data; | |
4217 | struct drm_gem_object *obj; | |
4218 | struct drm_i915_gem_object *obj_priv; | |
4219 | int ret; | |
4220 | ||
1d7cfea1 CW |
4221 | ret = i915_mutex_lock_interruptible(dev); |
4222 | if (ret) | |
4223 | return ret; | |
673a394b EA |
4224 | |
4225 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); | |
4226 | if (obj == NULL) { | |
1d7cfea1 CW |
4227 | ret = -ENOENT; |
4228 | goto unlock; | |
673a394b | 4229 | } |
23010e43 | 4230 | obj_priv = to_intel_bo(obj); |
673a394b | 4231 | |
bb6baf76 CW |
4232 | if (obj_priv->madv != I915_MADV_WILLNEED) { |
4233 | DRM_ERROR("Attempting to pin a purgeable buffer\n"); | |
1d7cfea1 CW |
4234 | ret = -EINVAL; |
4235 | goto out; | |
3ef94daa CW |
4236 | } |
4237 | ||
79e53945 JB |
4238 | if (obj_priv->pin_filp != NULL && obj_priv->pin_filp != file_priv) { |
4239 | DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n", | |
4240 | args->handle); | |
1d7cfea1 CW |
4241 | ret = -EINVAL; |
4242 | goto out; | |
79e53945 JB |
4243 | } |
4244 | ||
4245 | obj_priv->user_pin_count++; | |
4246 | obj_priv->pin_filp = file_priv; | |
4247 | if (obj_priv->user_pin_count == 1) { | |
a00b10c3 CW |
4248 | ret = i915_gem_object_pin(obj, args->alignment, |
4249 | true, obj_priv->tiling_mode); | |
1d7cfea1 CW |
4250 | if (ret) |
4251 | goto out; | |
673a394b EA |
4252 | } |
4253 | ||
4254 | /* XXX - flush the CPU caches for pinned objects | |
4255 | * as the X server doesn't manage domains yet | |
4256 | */ | |
e47c68e9 | 4257 | i915_gem_object_flush_cpu_write_domain(obj); |
673a394b | 4258 | args->offset = obj_priv->gtt_offset; |
1d7cfea1 | 4259 | out: |
673a394b | 4260 | drm_gem_object_unreference(obj); |
1d7cfea1 | 4261 | unlock: |
673a394b | 4262 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 4263 | return ret; |
673a394b EA |
4264 | } |
4265 | ||
4266 | int | |
4267 | i915_gem_unpin_ioctl(struct drm_device *dev, void *data, | |
4268 | struct drm_file *file_priv) | |
4269 | { | |
4270 | struct drm_i915_gem_pin *args = data; | |
4271 | struct drm_gem_object *obj; | |
79e53945 | 4272 | struct drm_i915_gem_object *obj_priv; |
76c1dec1 | 4273 | int ret; |
673a394b | 4274 | |
1d7cfea1 CW |
4275 | ret = i915_mutex_lock_interruptible(dev); |
4276 | if (ret) | |
4277 | return ret; | |
673a394b EA |
4278 | |
4279 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); | |
4280 | if (obj == NULL) { | |
1d7cfea1 CW |
4281 | ret = -ENOENT; |
4282 | goto unlock; | |
673a394b | 4283 | } |
23010e43 | 4284 | obj_priv = to_intel_bo(obj); |
76c1dec1 | 4285 | |
79e53945 JB |
4286 | if (obj_priv->pin_filp != file_priv) { |
4287 | DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n", | |
4288 | args->handle); | |
1d7cfea1 CW |
4289 | ret = -EINVAL; |
4290 | goto out; | |
79e53945 JB |
4291 | } |
4292 | obj_priv->user_pin_count--; | |
4293 | if (obj_priv->user_pin_count == 0) { | |
4294 | obj_priv->pin_filp = NULL; | |
4295 | i915_gem_object_unpin(obj); | |
4296 | } | |
673a394b | 4297 | |
1d7cfea1 | 4298 | out: |
673a394b | 4299 | drm_gem_object_unreference(obj); |
1d7cfea1 | 4300 | unlock: |
673a394b | 4301 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 4302 | return ret; |
673a394b EA |
4303 | } |
4304 | ||
4305 | int | |
4306 | i915_gem_busy_ioctl(struct drm_device *dev, void *data, | |
4307 | struct drm_file *file_priv) | |
4308 | { | |
4309 | struct drm_i915_gem_busy *args = data; | |
4310 | struct drm_gem_object *obj; | |
4311 | struct drm_i915_gem_object *obj_priv; | |
30dbf0c0 CW |
4312 | int ret; |
4313 | ||
76c1dec1 | 4314 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 4315 | if (ret) |
76c1dec1 | 4316 | return ret; |
673a394b | 4317 | |
673a394b EA |
4318 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); |
4319 | if (obj == NULL) { | |
1d7cfea1 CW |
4320 | ret = -ENOENT; |
4321 | goto unlock; | |
673a394b | 4322 | } |
1d7cfea1 | 4323 | obj_priv = to_intel_bo(obj); |
d1b851fc | 4324 | |
0be555b6 CW |
4325 | /* Count all active objects as busy, even if they are currently not used |
4326 | * by the gpu. Users of this interface expect objects to eventually | |
4327 | * become non-busy without any further actions, therefore emit any | |
4328 | * necessary flushes here. | |
c4de0a5d | 4329 | */ |
0be555b6 CW |
4330 | args->busy = obj_priv->active; |
4331 | if (args->busy) { | |
4332 | /* Unconditionally flush objects, even when the gpu still uses this | |
4333 | * object. Userspace calling this function indicates that it wants to | |
4334 | * use this buffer rather sooner than later, so issuing the required | |
4335 | * flush earlier is beneficial. | |
4336 | */ | |
c78ec30b CW |
4337 | if (obj->write_domain & I915_GEM_GPU_DOMAINS) |
4338 | i915_gem_flush_ring(dev, file_priv, | |
9220434a CW |
4339 | obj_priv->ring, |
4340 | 0, obj->write_domain); | |
0be555b6 CW |
4341 | |
4342 | /* Update the active list for the hardware's current position. | |
4343 | * Otherwise this only updates on a delayed timer or when irqs | |
4344 | * are actually unmasked, and our working set ends up being | |
4345 | * larger than required. | |
4346 | */ | |
4347 | i915_gem_retire_requests_ring(dev, obj_priv->ring); | |
4348 | ||
4349 | args->busy = obj_priv->active; | |
4350 | } | |
673a394b EA |
4351 | |
4352 | drm_gem_object_unreference(obj); | |
1d7cfea1 | 4353 | unlock: |
673a394b | 4354 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 4355 | return ret; |
673a394b EA |
4356 | } |
4357 | ||
4358 | int | |
4359 | i915_gem_throttle_ioctl(struct drm_device *dev, void *data, | |
4360 | struct drm_file *file_priv) | |
4361 | { | |
4362 | return i915_gem_ring_throttle(dev, file_priv); | |
4363 | } | |
4364 | ||
3ef94daa CW |
4365 | int |
4366 | i915_gem_madvise_ioctl(struct drm_device *dev, void *data, | |
4367 | struct drm_file *file_priv) | |
4368 | { | |
4369 | struct drm_i915_gem_madvise *args = data; | |
4370 | struct drm_gem_object *obj; | |
4371 | struct drm_i915_gem_object *obj_priv; | |
76c1dec1 | 4372 | int ret; |
3ef94daa CW |
4373 | |
4374 | switch (args->madv) { | |
4375 | case I915_MADV_DONTNEED: | |
4376 | case I915_MADV_WILLNEED: | |
4377 | break; | |
4378 | default: | |
4379 | return -EINVAL; | |
4380 | } | |
4381 | ||
1d7cfea1 CW |
4382 | ret = i915_mutex_lock_interruptible(dev); |
4383 | if (ret) | |
4384 | return ret; | |
4385 | ||
3ef94daa CW |
4386 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); |
4387 | if (obj == NULL) { | |
1d7cfea1 CW |
4388 | ret = -ENOENT; |
4389 | goto unlock; | |
3ef94daa | 4390 | } |
23010e43 | 4391 | obj_priv = to_intel_bo(obj); |
3ef94daa CW |
4392 | |
4393 | if (obj_priv->pin_count) { | |
1d7cfea1 CW |
4394 | ret = -EINVAL; |
4395 | goto out; | |
3ef94daa CW |
4396 | } |
4397 | ||
bb6baf76 CW |
4398 | if (obj_priv->madv != __I915_MADV_PURGED) |
4399 | obj_priv->madv = args->madv; | |
3ef94daa | 4400 | |
2d7ef395 CW |
4401 | /* if the object is no longer bound, discard its backing storage */ |
4402 | if (i915_gem_object_is_purgeable(obj_priv) && | |
4403 | obj_priv->gtt_space == NULL) | |
4404 | i915_gem_object_truncate(obj); | |
4405 | ||
bb6baf76 CW |
4406 | args->retained = obj_priv->madv != __I915_MADV_PURGED; |
4407 | ||
1d7cfea1 | 4408 | out: |
3ef94daa | 4409 | drm_gem_object_unreference(obj); |
1d7cfea1 | 4410 | unlock: |
3ef94daa | 4411 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 4412 | return ret; |
3ef94daa CW |
4413 | } |
4414 | ||
ac52bc56 DV |
4415 | struct drm_gem_object * i915_gem_alloc_object(struct drm_device *dev, |
4416 | size_t size) | |
4417 | { | |
73aa808f | 4418 | struct drm_i915_private *dev_priv = dev->dev_private; |
c397b908 | 4419 | struct drm_i915_gem_object *obj; |
ac52bc56 | 4420 | |
c397b908 DV |
4421 | obj = kzalloc(sizeof(*obj), GFP_KERNEL); |
4422 | if (obj == NULL) | |
4423 | return NULL; | |
673a394b | 4424 | |
c397b908 DV |
4425 | if (drm_gem_object_init(dev, &obj->base, size) != 0) { |
4426 | kfree(obj); | |
4427 | return NULL; | |
4428 | } | |
673a394b | 4429 | |
73aa808f CW |
4430 | i915_gem_info_add_obj(dev_priv, size); |
4431 | ||
c397b908 DV |
4432 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; |
4433 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; | |
673a394b | 4434 | |
c397b908 | 4435 | obj->agp_type = AGP_USER_MEMORY; |
62b8b215 | 4436 | obj->base.driver_private = NULL; |
c397b908 | 4437 | obj->fence_reg = I915_FENCE_REG_NONE; |
69dc4987 CW |
4438 | INIT_LIST_HEAD(&obj->mm_list); |
4439 | INIT_LIST_HEAD(&obj->ring_list); | |
c397b908 | 4440 | INIT_LIST_HEAD(&obj->gpu_write_list); |
c397b908 | 4441 | obj->madv = I915_MADV_WILLNEED; |
a00b10c3 CW |
4442 | obj->fenceable = true; |
4443 | obj->mappable = true; | |
de151cf6 | 4444 | |
c397b908 DV |
4445 | return &obj->base; |
4446 | } | |
4447 | ||
4448 | int i915_gem_init_object(struct drm_gem_object *obj) | |
4449 | { | |
4450 | BUG(); | |
de151cf6 | 4451 | |
673a394b EA |
4452 | return 0; |
4453 | } | |
4454 | ||
be72615b | 4455 | static void i915_gem_free_object_tail(struct drm_gem_object *obj) |
673a394b | 4456 | { |
de151cf6 | 4457 | struct drm_device *dev = obj->dev; |
be72615b | 4458 | drm_i915_private_t *dev_priv = dev->dev_private; |
23010e43 | 4459 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
be72615b | 4460 | int ret; |
673a394b | 4461 | |
be72615b CW |
4462 | ret = i915_gem_object_unbind(obj); |
4463 | if (ret == -ERESTARTSYS) { | |
69dc4987 | 4464 | list_move(&obj_priv->mm_list, |
be72615b CW |
4465 | &dev_priv->mm.deferred_free_list); |
4466 | return; | |
4467 | } | |
673a394b | 4468 | |
39a01d1f | 4469 | if (obj->map_list.map) |
7e616158 | 4470 | i915_gem_free_mmap_offset(obj); |
de151cf6 | 4471 | |
c397b908 | 4472 | drm_gem_object_release(obj); |
73aa808f | 4473 | i915_gem_info_remove_obj(dev_priv, obj->size); |
c397b908 | 4474 | |
9a298b2a | 4475 | kfree(obj_priv->page_cpu_valid); |
280b713b | 4476 | kfree(obj_priv->bit_17); |
c397b908 | 4477 | kfree(obj_priv); |
673a394b EA |
4478 | } |
4479 | ||
be72615b CW |
4480 | void i915_gem_free_object(struct drm_gem_object *obj) |
4481 | { | |
4482 | struct drm_device *dev = obj->dev; | |
4483 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); | |
4484 | ||
4485 | trace_i915_gem_object_destroy(obj); | |
4486 | ||
4487 | while (obj_priv->pin_count > 0) | |
4488 | i915_gem_object_unpin(obj); | |
4489 | ||
4490 | if (obj_priv->phys_obj) | |
4491 | i915_gem_detach_phys_object(dev, obj); | |
4492 | ||
4493 | i915_gem_free_object_tail(obj); | |
4494 | } | |
4495 | ||
29105ccc CW |
4496 | int |
4497 | i915_gem_idle(struct drm_device *dev) | |
4498 | { | |
4499 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4500 | int ret; | |
28dfe52a | 4501 | |
29105ccc | 4502 | mutex_lock(&dev->struct_mutex); |
1c5d22f7 | 4503 | |
87acb0a5 | 4504 | if (dev_priv->mm.suspended) { |
29105ccc CW |
4505 | mutex_unlock(&dev->struct_mutex); |
4506 | return 0; | |
28dfe52a EA |
4507 | } |
4508 | ||
29105ccc | 4509 | ret = i915_gpu_idle(dev); |
6dbe2772 KP |
4510 | if (ret) { |
4511 | mutex_unlock(&dev->struct_mutex); | |
673a394b | 4512 | return ret; |
6dbe2772 | 4513 | } |
673a394b | 4514 | |
29105ccc CW |
4515 | /* Under UMS, be paranoid and evict. */ |
4516 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) { | |
5eac3ab4 | 4517 | ret = i915_gem_evict_inactive(dev, false); |
29105ccc CW |
4518 | if (ret) { |
4519 | mutex_unlock(&dev->struct_mutex); | |
4520 | return ret; | |
4521 | } | |
4522 | } | |
4523 | ||
4524 | /* Hack! Don't let anybody do execbuf while we don't control the chip. | |
4525 | * We need to replace this with a semaphore, or something. | |
4526 | * And not confound mm.suspended! | |
4527 | */ | |
4528 | dev_priv->mm.suspended = 1; | |
bc0c7f14 | 4529 | del_timer_sync(&dev_priv->hangcheck_timer); |
29105ccc CW |
4530 | |
4531 | i915_kernel_lost_context(dev); | |
6dbe2772 | 4532 | i915_gem_cleanup_ringbuffer(dev); |
29105ccc | 4533 | |
6dbe2772 KP |
4534 | mutex_unlock(&dev->struct_mutex); |
4535 | ||
29105ccc CW |
4536 | /* Cancel the retire work handler, which should be idle now. */ |
4537 | cancel_delayed_work_sync(&dev_priv->mm.retire_work); | |
4538 | ||
673a394b EA |
4539 | return 0; |
4540 | } | |
4541 | ||
e552eb70 JB |
4542 | /* |
4543 | * 965+ support PIPE_CONTROL commands, which provide finer grained control | |
4544 | * over cache flushing. | |
4545 | */ | |
8187a2b7 | 4546 | static int |
e552eb70 JB |
4547 | i915_gem_init_pipe_control(struct drm_device *dev) |
4548 | { | |
4549 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4550 | struct drm_gem_object *obj; | |
4551 | struct drm_i915_gem_object *obj_priv; | |
4552 | int ret; | |
4553 | ||
34dc4d44 | 4554 | obj = i915_gem_alloc_object(dev, 4096); |
e552eb70 JB |
4555 | if (obj == NULL) { |
4556 | DRM_ERROR("Failed to allocate seqno page\n"); | |
4557 | ret = -ENOMEM; | |
4558 | goto err; | |
4559 | } | |
4560 | obj_priv = to_intel_bo(obj); | |
4561 | obj_priv->agp_type = AGP_USER_CACHED_MEMORY; | |
4562 | ||
a00b10c3 | 4563 | ret = i915_gem_object_pin(obj, 4096, true, false); |
e552eb70 JB |
4564 | if (ret) |
4565 | goto err_unref; | |
4566 | ||
4567 | dev_priv->seqno_gfx_addr = obj_priv->gtt_offset; | |
4568 | dev_priv->seqno_page = kmap(obj_priv->pages[0]); | |
4569 | if (dev_priv->seqno_page == NULL) | |
4570 | goto err_unpin; | |
4571 | ||
4572 | dev_priv->seqno_obj = obj; | |
4573 | memset(dev_priv->seqno_page, 0, PAGE_SIZE); | |
4574 | ||
4575 | return 0; | |
4576 | ||
4577 | err_unpin: | |
4578 | i915_gem_object_unpin(obj); | |
4579 | err_unref: | |
4580 | drm_gem_object_unreference(obj); | |
4581 | err: | |
4582 | return ret; | |
4583 | } | |
4584 | ||
8187a2b7 ZN |
4585 | |
4586 | static void | |
e552eb70 JB |
4587 | i915_gem_cleanup_pipe_control(struct drm_device *dev) |
4588 | { | |
4589 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4590 | struct drm_gem_object *obj; | |
4591 | struct drm_i915_gem_object *obj_priv; | |
4592 | ||
4593 | obj = dev_priv->seqno_obj; | |
4594 | obj_priv = to_intel_bo(obj); | |
4595 | kunmap(obj_priv->pages[0]); | |
4596 | i915_gem_object_unpin(obj); | |
4597 | drm_gem_object_unreference(obj); | |
4598 | dev_priv->seqno_obj = NULL; | |
4599 | ||
4600 | dev_priv->seqno_page = NULL; | |
673a394b EA |
4601 | } |
4602 | ||
8187a2b7 ZN |
4603 | int |
4604 | i915_gem_init_ringbuffer(struct drm_device *dev) | |
4605 | { | |
4606 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4607 | int ret; | |
68f95ba9 | 4608 | |
8187a2b7 ZN |
4609 | if (HAS_PIPE_CONTROL(dev)) { |
4610 | ret = i915_gem_init_pipe_control(dev); | |
4611 | if (ret) | |
4612 | return ret; | |
4613 | } | |
68f95ba9 | 4614 | |
5c1143bb | 4615 | ret = intel_init_render_ring_buffer(dev); |
68f95ba9 CW |
4616 | if (ret) |
4617 | goto cleanup_pipe_control; | |
4618 | ||
4619 | if (HAS_BSD(dev)) { | |
5c1143bb | 4620 | ret = intel_init_bsd_ring_buffer(dev); |
68f95ba9 CW |
4621 | if (ret) |
4622 | goto cleanup_render_ring; | |
d1b851fc | 4623 | } |
68f95ba9 | 4624 | |
549f7365 CW |
4625 | if (HAS_BLT(dev)) { |
4626 | ret = intel_init_blt_ring_buffer(dev); | |
4627 | if (ret) | |
4628 | goto cleanup_bsd_ring; | |
4629 | } | |
4630 | ||
6f392d54 CW |
4631 | dev_priv->next_seqno = 1; |
4632 | ||
68f95ba9 CW |
4633 | return 0; |
4634 | ||
549f7365 | 4635 | cleanup_bsd_ring: |
78501eac | 4636 | intel_cleanup_ring_buffer(&dev_priv->bsd_ring); |
68f95ba9 | 4637 | cleanup_render_ring: |
78501eac | 4638 | intel_cleanup_ring_buffer(&dev_priv->render_ring); |
68f95ba9 CW |
4639 | cleanup_pipe_control: |
4640 | if (HAS_PIPE_CONTROL(dev)) | |
4641 | i915_gem_cleanup_pipe_control(dev); | |
8187a2b7 ZN |
4642 | return ret; |
4643 | } | |
4644 | ||
4645 | void | |
4646 | i915_gem_cleanup_ringbuffer(struct drm_device *dev) | |
4647 | { | |
4648 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4649 | ||
78501eac CW |
4650 | intel_cleanup_ring_buffer(&dev_priv->render_ring); |
4651 | intel_cleanup_ring_buffer(&dev_priv->bsd_ring); | |
4652 | intel_cleanup_ring_buffer(&dev_priv->blt_ring); | |
8187a2b7 ZN |
4653 | if (HAS_PIPE_CONTROL(dev)) |
4654 | i915_gem_cleanup_pipe_control(dev); | |
4655 | } | |
4656 | ||
673a394b EA |
4657 | int |
4658 | i915_gem_entervt_ioctl(struct drm_device *dev, void *data, | |
4659 | struct drm_file *file_priv) | |
4660 | { | |
4661 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4662 | int ret; | |
4663 | ||
79e53945 JB |
4664 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
4665 | return 0; | |
4666 | ||
ba1234d1 | 4667 | if (atomic_read(&dev_priv->mm.wedged)) { |
673a394b | 4668 | DRM_ERROR("Reenabling wedged hardware, good luck\n"); |
ba1234d1 | 4669 | atomic_set(&dev_priv->mm.wedged, 0); |
673a394b EA |
4670 | } |
4671 | ||
673a394b | 4672 | mutex_lock(&dev->struct_mutex); |
9bb2d6f9 EA |
4673 | dev_priv->mm.suspended = 0; |
4674 | ||
4675 | ret = i915_gem_init_ringbuffer(dev); | |
d816f6ac WF |
4676 | if (ret != 0) { |
4677 | mutex_unlock(&dev->struct_mutex); | |
9bb2d6f9 | 4678 | return ret; |
d816f6ac | 4679 | } |
9bb2d6f9 | 4680 | |
69dc4987 | 4681 | BUG_ON(!list_empty(&dev_priv->mm.active_list)); |
852835f3 | 4682 | BUG_ON(!list_empty(&dev_priv->render_ring.active_list)); |
87acb0a5 | 4683 | BUG_ON(!list_empty(&dev_priv->bsd_ring.active_list)); |
549f7365 | 4684 | BUG_ON(!list_empty(&dev_priv->blt_ring.active_list)); |
673a394b EA |
4685 | BUG_ON(!list_empty(&dev_priv->mm.flushing_list)); |
4686 | BUG_ON(!list_empty(&dev_priv->mm.inactive_list)); | |
852835f3 | 4687 | BUG_ON(!list_empty(&dev_priv->render_ring.request_list)); |
87acb0a5 | 4688 | BUG_ON(!list_empty(&dev_priv->bsd_ring.request_list)); |
549f7365 | 4689 | BUG_ON(!list_empty(&dev_priv->blt_ring.request_list)); |
673a394b | 4690 | mutex_unlock(&dev->struct_mutex); |
dbb19d30 | 4691 | |
5f35308b CW |
4692 | ret = drm_irq_install(dev); |
4693 | if (ret) | |
4694 | goto cleanup_ringbuffer; | |
dbb19d30 | 4695 | |
673a394b | 4696 | return 0; |
5f35308b CW |
4697 | |
4698 | cleanup_ringbuffer: | |
4699 | mutex_lock(&dev->struct_mutex); | |
4700 | i915_gem_cleanup_ringbuffer(dev); | |
4701 | dev_priv->mm.suspended = 1; | |
4702 | mutex_unlock(&dev->struct_mutex); | |
4703 | ||
4704 | return ret; | |
673a394b EA |
4705 | } |
4706 | ||
4707 | int | |
4708 | i915_gem_leavevt_ioctl(struct drm_device *dev, void *data, | |
4709 | struct drm_file *file_priv) | |
4710 | { | |
79e53945 JB |
4711 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
4712 | return 0; | |
4713 | ||
dbb19d30 | 4714 | drm_irq_uninstall(dev); |
e6890f6f | 4715 | return i915_gem_idle(dev); |
673a394b EA |
4716 | } |
4717 | ||
4718 | void | |
4719 | i915_gem_lastclose(struct drm_device *dev) | |
4720 | { | |
4721 | int ret; | |
673a394b | 4722 | |
e806b495 EA |
4723 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
4724 | return; | |
4725 | ||
6dbe2772 KP |
4726 | ret = i915_gem_idle(dev); |
4727 | if (ret) | |
4728 | DRM_ERROR("failed to idle hardware: %d\n", ret); | |
673a394b EA |
4729 | } |
4730 | ||
64193406 CW |
4731 | static void |
4732 | init_ring_lists(struct intel_ring_buffer *ring) | |
4733 | { | |
4734 | INIT_LIST_HEAD(&ring->active_list); | |
4735 | INIT_LIST_HEAD(&ring->request_list); | |
4736 | INIT_LIST_HEAD(&ring->gpu_write_list); | |
4737 | } | |
4738 | ||
673a394b EA |
4739 | void |
4740 | i915_gem_load(struct drm_device *dev) | |
4741 | { | |
b5aa8a0f | 4742 | int i; |
673a394b EA |
4743 | drm_i915_private_t *dev_priv = dev->dev_private; |
4744 | ||
69dc4987 | 4745 | INIT_LIST_HEAD(&dev_priv->mm.active_list); |
673a394b EA |
4746 | INIT_LIST_HEAD(&dev_priv->mm.flushing_list); |
4747 | INIT_LIST_HEAD(&dev_priv->mm.inactive_list); | |
f13d3f73 | 4748 | INIT_LIST_HEAD(&dev_priv->mm.pinned_list); |
a09ba7fa | 4749 | INIT_LIST_HEAD(&dev_priv->mm.fence_list); |
be72615b | 4750 | INIT_LIST_HEAD(&dev_priv->mm.deferred_free_list); |
64193406 CW |
4751 | init_ring_lists(&dev_priv->render_ring); |
4752 | init_ring_lists(&dev_priv->bsd_ring); | |
4753 | init_ring_lists(&dev_priv->blt_ring); | |
007cc8ac DV |
4754 | for (i = 0; i < 16; i++) |
4755 | INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list); | |
673a394b EA |
4756 | INIT_DELAYED_WORK(&dev_priv->mm.retire_work, |
4757 | i915_gem_retire_work_handler); | |
30dbf0c0 | 4758 | init_completion(&dev_priv->error_completion); |
31169714 | 4759 | |
94400120 DA |
4760 | /* On GEN3 we really need to make sure the ARB C3 LP bit is set */ |
4761 | if (IS_GEN3(dev)) { | |
4762 | u32 tmp = I915_READ(MI_ARB_STATE); | |
4763 | if (!(tmp & MI_ARB_C3_LP_WRITE_ENABLE)) { | |
4764 | /* arb state is a masked write, so set bit + bit in mask */ | |
4765 | tmp = MI_ARB_C3_LP_WRITE_ENABLE | (MI_ARB_C3_LP_WRITE_ENABLE << MI_ARB_MASK_SHIFT); | |
4766 | I915_WRITE(MI_ARB_STATE, tmp); | |
4767 | } | |
4768 | } | |
4769 | ||
de151cf6 | 4770 | /* Old X drivers will take 0-2 for front, back, depth buffers */ |
b397c836 EA |
4771 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) |
4772 | dev_priv->fence_reg_start = 3; | |
de151cf6 | 4773 | |
a6c45cf0 | 4774 | if (INTEL_INFO(dev)->gen >= 4 || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) |
de151cf6 JB |
4775 | dev_priv->num_fence_regs = 16; |
4776 | else | |
4777 | dev_priv->num_fence_regs = 8; | |
4778 | ||
b5aa8a0f | 4779 | /* Initialize fence registers to zero */ |
a6c45cf0 CW |
4780 | switch (INTEL_INFO(dev)->gen) { |
4781 | case 6: | |
4782 | for (i = 0; i < 16; i++) | |
4783 | I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + (i * 8), 0); | |
4784 | break; | |
4785 | case 5: | |
4786 | case 4: | |
b5aa8a0f GH |
4787 | for (i = 0; i < 16; i++) |
4788 | I915_WRITE64(FENCE_REG_965_0 + (i * 8), 0); | |
a6c45cf0 CW |
4789 | break; |
4790 | case 3: | |
b5aa8a0f GH |
4791 | if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) |
4792 | for (i = 0; i < 8; i++) | |
4793 | I915_WRITE(FENCE_REG_945_8 + (i * 4), 0); | |
a6c45cf0 CW |
4794 | case 2: |
4795 | for (i = 0; i < 8; i++) | |
4796 | I915_WRITE(FENCE_REG_830_0 + (i * 4), 0); | |
4797 | break; | |
b5aa8a0f | 4798 | } |
673a394b | 4799 | i915_gem_detect_bit_6_swizzle(dev); |
6b95a207 | 4800 | init_waitqueue_head(&dev_priv->pending_flip_queue); |
17250b71 CW |
4801 | |
4802 | dev_priv->mm.inactive_shrinker.shrink = i915_gem_inactive_shrink; | |
4803 | dev_priv->mm.inactive_shrinker.seeks = DEFAULT_SEEKS; | |
4804 | register_shrinker(&dev_priv->mm.inactive_shrinker); | |
673a394b | 4805 | } |
71acb5eb DA |
4806 | |
4807 | /* | |
4808 | * Create a physically contiguous memory object for this object | |
4809 | * e.g. for cursor + overlay regs | |
4810 | */ | |
995b6762 CW |
4811 | static int i915_gem_init_phys_object(struct drm_device *dev, |
4812 | int id, int size, int align) | |
71acb5eb DA |
4813 | { |
4814 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4815 | struct drm_i915_gem_phys_object *phys_obj; | |
4816 | int ret; | |
4817 | ||
4818 | if (dev_priv->mm.phys_objs[id - 1] || !size) | |
4819 | return 0; | |
4820 | ||
9a298b2a | 4821 | phys_obj = kzalloc(sizeof(struct drm_i915_gem_phys_object), GFP_KERNEL); |
71acb5eb DA |
4822 | if (!phys_obj) |
4823 | return -ENOMEM; | |
4824 | ||
4825 | phys_obj->id = id; | |
4826 | ||
6eeefaf3 | 4827 | phys_obj->handle = drm_pci_alloc(dev, size, align); |
71acb5eb DA |
4828 | if (!phys_obj->handle) { |
4829 | ret = -ENOMEM; | |
4830 | goto kfree_obj; | |
4831 | } | |
4832 | #ifdef CONFIG_X86 | |
4833 | set_memory_wc((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE); | |
4834 | #endif | |
4835 | ||
4836 | dev_priv->mm.phys_objs[id - 1] = phys_obj; | |
4837 | ||
4838 | return 0; | |
4839 | kfree_obj: | |
9a298b2a | 4840 | kfree(phys_obj); |
71acb5eb DA |
4841 | return ret; |
4842 | } | |
4843 | ||
995b6762 | 4844 | static void i915_gem_free_phys_object(struct drm_device *dev, int id) |
71acb5eb DA |
4845 | { |
4846 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4847 | struct drm_i915_gem_phys_object *phys_obj; | |
4848 | ||
4849 | if (!dev_priv->mm.phys_objs[id - 1]) | |
4850 | return; | |
4851 | ||
4852 | phys_obj = dev_priv->mm.phys_objs[id - 1]; | |
4853 | if (phys_obj->cur_obj) { | |
4854 | i915_gem_detach_phys_object(dev, phys_obj->cur_obj); | |
4855 | } | |
4856 | ||
4857 | #ifdef CONFIG_X86 | |
4858 | set_memory_wb((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE); | |
4859 | #endif | |
4860 | drm_pci_free(dev, phys_obj->handle); | |
4861 | kfree(phys_obj); | |
4862 | dev_priv->mm.phys_objs[id - 1] = NULL; | |
4863 | } | |
4864 | ||
4865 | void i915_gem_free_all_phys_object(struct drm_device *dev) | |
4866 | { | |
4867 | int i; | |
4868 | ||
260883c8 | 4869 | for (i = I915_GEM_PHYS_CURSOR_0; i <= I915_MAX_PHYS_OBJECT; i++) |
71acb5eb DA |
4870 | i915_gem_free_phys_object(dev, i); |
4871 | } | |
4872 | ||
4873 | void i915_gem_detach_phys_object(struct drm_device *dev, | |
4874 | struct drm_gem_object *obj) | |
4875 | { | |
e5281ccd CW |
4876 | struct address_space *mapping = obj->filp->f_path.dentry->d_inode->i_mapping; |
4877 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); | |
4878 | char *vaddr; | |
71acb5eb | 4879 | int i; |
71acb5eb DA |
4880 | int page_count; |
4881 | ||
71acb5eb DA |
4882 | if (!obj_priv->phys_obj) |
4883 | return; | |
e5281ccd | 4884 | vaddr = obj_priv->phys_obj->handle->vaddr; |
71acb5eb DA |
4885 | |
4886 | page_count = obj->size / PAGE_SIZE; | |
4887 | ||
4888 | for (i = 0; i < page_count; i++) { | |
e5281ccd CW |
4889 | struct page *page = read_cache_page_gfp(mapping, i, |
4890 | GFP_HIGHUSER | __GFP_RECLAIMABLE); | |
4891 | if (!IS_ERR(page)) { | |
4892 | char *dst = kmap_atomic(page); | |
4893 | memcpy(dst, vaddr + i*PAGE_SIZE, PAGE_SIZE); | |
4894 | kunmap_atomic(dst); | |
4895 | ||
4896 | drm_clflush_pages(&page, 1); | |
4897 | ||
4898 | set_page_dirty(page); | |
4899 | mark_page_accessed(page); | |
4900 | page_cache_release(page); | |
4901 | } | |
71acb5eb | 4902 | } |
71acb5eb | 4903 | drm_agp_chipset_flush(dev); |
d78b47b9 | 4904 | |
71acb5eb DA |
4905 | obj_priv->phys_obj->cur_obj = NULL; |
4906 | obj_priv->phys_obj = NULL; | |
4907 | } | |
4908 | ||
4909 | int | |
4910 | i915_gem_attach_phys_object(struct drm_device *dev, | |
6eeefaf3 CW |
4911 | struct drm_gem_object *obj, |
4912 | int id, | |
4913 | int align) | |
71acb5eb | 4914 | { |
e5281ccd | 4915 | struct address_space *mapping = obj->filp->f_path.dentry->d_inode->i_mapping; |
71acb5eb DA |
4916 | drm_i915_private_t *dev_priv = dev->dev_private; |
4917 | struct drm_i915_gem_object *obj_priv; | |
4918 | int ret = 0; | |
4919 | int page_count; | |
4920 | int i; | |
4921 | ||
4922 | if (id > I915_MAX_PHYS_OBJECT) | |
4923 | return -EINVAL; | |
4924 | ||
23010e43 | 4925 | obj_priv = to_intel_bo(obj); |
71acb5eb DA |
4926 | |
4927 | if (obj_priv->phys_obj) { | |
4928 | if (obj_priv->phys_obj->id == id) | |
4929 | return 0; | |
4930 | i915_gem_detach_phys_object(dev, obj); | |
4931 | } | |
4932 | ||
71acb5eb DA |
4933 | /* create a new object */ |
4934 | if (!dev_priv->mm.phys_objs[id - 1]) { | |
4935 | ret = i915_gem_init_phys_object(dev, id, | |
6eeefaf3 | 4936 | obj->size, align); |
71acb5eb | 4937 | if (ret) { |
aeb565df | 4938 | DRM_ERROR("failed to init phys object %d size: %zu\n", id, obj->size); |
e5281ccd | 4939 | return ret; |
71acb5eb DA |
4940 | } |
4941 | } | |
4942 | ||
4943 | /* bind to the object */ | |
4944 | obj_priv->phys_obj = dev_priv->mm.phys_objs[id - 1]; | |
4945 | obj_priv->phys_obj->cur_obj = obj; | |
4946 | ||
71acb5eb DA |
4947 | page_count = obj->size / PAGE_SIZE; |
4948 | ||
4949 | for (i = 0; i < page_count; i++) { | |
e5281ccd CW |
4950 | struct page *page; |
4951 | char *dst, *src; | |
4952 | ||
4953 | page = read_cache_page_gfp(mapping, i, | |
4954 | GFP_HIGHUSER | __GFP_RECLAIMABLE); | |
4955 | if (IS_ERR(page)) | |
4956 | return PTR_ERR(page); | |
71acb5eb | 4957 | |
ff75b9bc | 4958 | src = kmap_atomic(page); |
e5281ccd | 4959 | dst = obj_priv->phys_obj->handle->vaddr + (i * PAGE_SIZE); |
71acb5eb | 4960 | memcpy(dst, src, PAGE_SIZE); |
3e4d3af5 | 4961 | kunmap_atomic(src); |
71acb5eb | 4962 | |
e5281ccd CW |
4963 | mark_page_accessed(page); |
4964 | page_cache_release(page); | |
4965 | } | |
d78b47b9 | 4966 | |
71acb5eb | 4967 | return 0; |
71acb5eb DA |
4968 | } |
4969 | ||
4970 | static int | |
4971 | i915_gem_phys_pwrite(struct drm_device *dev, struct drm_gem_object *obj, | |
4972 | struct drm_i915_gem_pwrite *args, | |
4973 | struct drm_file *file_priv) | |
4974 | { | |
23010e43 | 4975 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
71acb5eb DA |
4976 | void *obj_addr; |
4977 | int ret; | |
4978 | char __user *user_data; | |
4979 | ||
4980 | user_data = (char __user *) (uintptr_t) args->data_ptr; | |
4981 | obj_addr = obj_priv->phys_obj->handle->vaddr + args->offset; | |
4982 | ||
44d98a61 | 4983 | DRM_DEBUG_DRIVER("obj_addr %p, %lld\n", obj_addr, args->size); |
71acb5eb DA |
4984 | ret = copy_from_user(obj_addr, user_data, args->size); |
4985 | if (ret) | |
4986 | return -EFAULT; | |
4987 | ||
4988 | drm_agp_chipset_flush(dev); | |
4989 | return 0; | |
4990 | } | |
b962442e | 4991 | |
f787a5f5 | 4992 | void i915_gem_release(struct drm_device *dev, struct drm_file *file) |
b962442e | 4993 | { |
f787a5f5 | 4994 | struct drm_i915_file_private *file_priv = file->driver_priv; |
b962442e EA |
4995 | |
4996 | /* Clean up our request list when the client is going away, so that | |
4997 | * later retire_requests won't dereference our soon-to-be-gone | |
4998 | * file_priv. | |
4999 | */ | |
1c25595f | 5000 | spin_lock(&file_priv->mm.lock); |
f787a5f5 CW |
5001 | while (!list_empty(&file_priv->mm.request_list)) { |
5002 | struct drm_i915_gem_request *request; | |
5003 | ||
5004 | request = list_first_entry(&file_priv->mm.request_list, | |
5005 | struct drm_i915_gem_request, | |
5006 | client_list); | |
5007 | list_del(&request->client_list); | |
5008 | request->file_priv = NULL; | |
5009 | } | |
1c25595f | 5010 | spin_unlock(&file_priv->mm.lock); |
b962442e | 5011 | } |
31169714 | 5012 | |
1637ef41 CW |
5013 | static int |
5014 | i915_gpu_is_active(struct drm_device *dev) | |
5015 | { | |
5016 | drm_i915_private_t *dev_priv = dev->dev_private; | |
5017 | int lists_empty; | |
5018 | ||
1637ef41 | 5019 | lists_empty = list_empty(&dev_priv->mm.flushing_list) && |
17250b71 | 5020 | list_empty(&dev_priv->mm.active_list); |
1637ef41 CW |
5021 | |
5022 | return !lists_empty; | |
5023 | } | |
5024 | ||
31169714 | 5025 | static int |
17250b71 CW |
5026 | i915_gem_inactive_shrink(struct shrinker *shrinker, |
5027 | int nr_to_scan, | |
5028 | gfp_t gfp_mask) | |
31169714 | 5029 | { |
17250b71 CW |
5030 | struct drm_i915_private *dev_priv = |
5031 | container_of(shrinker, | |
5032 | struct drm_i915_private, | |
5033 | mm.inactive_shrinker); | |
5034 | struct drm_device *dev = dev_priv->dev; | |
5035 | struct drm_i915_gem_object *obj, *next; | |
5036 | int cnt; | |
5037 | ||
5038 | if (!mutex_trylock(&dev->struct_mutex)) | |
bbe2e11a | 5039 | return 0; |
31169714 CW |
5040 | |
5041 | /* "fast-path" to count number of available objects */ | |
5042 | if (nr_to_scan == 0) { | |
17250b71 CW |
5043 | cnt = 0; |
5044 | list_for_each_entry(obj, | |
5045 | &dev_priv->mm.inactive_list, | |
5046 | mm_list) | |
5047 | cnt++; | |
5048 | mutex_unlock(&dev->struct_mutex); | |
5049 | return cnt / 100 * sysctl_vfs_cache_pressure; | |
31169714 CW |
5050 | } |
5051 | ||
1637ef41 | 5052 | rescan: |
31169714 | 5053 | /* first scan for clean buffers */ |
17250b71 | 5054 | i915_gem_retire_requests(dev); |
31169714 | 5055 | |
17250b71 CW |
5056 | list_for_each_entry_safe(obj, next, |
5057 | &dev_priv->mm.inactive_list, | |
5058 | mm_list) { | |
5059 | if (i915_gem_object_is_purgeable(obj)) { | |
5060 | i915_gem_object_unbind(&obj->base); | |
5061 | if (--nr_to_scan == 0) | |
5062 | break; | |
31169714 | 5063 | } |
31169714 CW |
5064 | } |
5065 | ||
5066 | /* second pass, evict/count anything still on the inactive list */ | |
17250b71 CW |
5067 | cnt = 0; |
5068 | list_for_each_entry_safe(obj, next, | |
5069 | &dev_priv->mm.inactive_list, | |
5070 | mm_list) { | |
5071 | if (nr_to_scan) { | |
5072 | i915_gem_object_unbind(&obj->base); | |
5073 | nr_to_scan--; | |
5074 | } else | |
5075 | cnt++; | |
5076 | } | |
5077 | ||
5078 | if (nr_to_scan && i915_gpu_is_active(dev)) { | |
1637ef41 CW |
5079 | /* |
5080 | * We are desperate for pages, so as a last resort, wait | |
5081 | * for the GPU to finish and discard whatever we can. | |
5082 | * This has a dramatic impact to reduce the number of | |
5083 | * OOM-killer events whilst running the GPU aggressively. | |
5084 | */ | |
17250b71 | 5085 | if (i915_gpu_idle(dev) == 0) |
1637ef41 CW |
5086 | goto rescan; |
5087 | } | |
17250b71 CW |
5088 | mutex_unlock(&dev->struct_mutex); |
5089 | return cnt / 100 * sysctl_vfs_cache_pressure; | |
31169714 | 5090 | } |