]>
Commit | Line | Data |
---|---|---|
673a394b EA |
1 | /* |
2 | * Copyright © 2008 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | * | |
26 | */ | |
27 | ||
28 | #include "drmP.h" | |
29 | #include "drm.h" | |
30 | #include "i915_drm.h" | |
31 | #include "i915_drv.h" | |
1c5d22f7 | 32 | #include "i915_trace.h" |
652c393a | 33 | #include "intel_drv.h" |
5a0e3ad6 | 34 | #include <linux/slab.h> |
673a394b | 35 | #include <linux/swap.h> |
79e53945 | 36 | #include <linux/pci.h> |
673a394b | 37 | |
88241785 | 38 | static __must_check int i915_gem_object_flush_gpu_write_domain(struct drm_i915_gem_object *obj); |
05394f39 CW |
39 | static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj); |
40 | static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj); | |
88241785 CW |
41 | static __must_check int i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, |
42 | bool write); | |
43 | static __must_check int i915_gem_object_set_cpu_read_domain_range(struct drm_i915_gem_object *obj, | |
44 | uint64_t offset, | |
45 | uint64_t size); | |
05394f39 | 46 | static void i915_gem_object_set_to_full_cpu_read_domain(struct drm_i915_gem_object *obj); |
88241785 CW |
47 | static __must_check int i915_gem_object_bind_to_gtt(struct drm_i915_gem_object *obj, |
48 | unsigned alignment, | |
49 | bool map_and_fenceable); | |
d9e86c0e CW |
50 | static void i915_gem_clear_fence_reg(struct drm_device *dev, |
51 | struct drm_i915_fence_reg *reg); | |
05394f39 CW |
52 | static int i915_gem_phys_pwrite(struct drm_device *dev, |
53 | struct drm_i915_gem_object *obj, | |
71acb5eb | 54 | struct drm_i915_gem_pwrite *args, |
05394f39 CW |
55 | struct drm_file *file); |
56 | static void i915_gem_free_object_tail(struct drm_i915_gem_object *obj); | |
673a394b | 57 | |
17250b71 CW |
58 | static int i915_gem_inactive_shrink(struct shrinker *shrinker, |
59 | int nr_to_scan, | |
60 | gfp_t gfp_mask); | |
61 | ||
31169714 | 62 | |
73aa808f CW |
63 | /* some bookkeeping */ |
64 | static void i915_gem_info_add_obj(struct drm_i915_private *dev_priv, | |
65 | size_t size) | |
66 | { | |
67 | dev_priv->mm.object_count++; | |
68 | dev_priv->mm.object_memory += size; | |
69 | } | |
70 | ||
71 | static void i915_gem_info_remove_obj(struct drm_i915_private *dev_priv, | |
72 | size_t size) | |
73 | { | |
74 | dev_priv->mm.object_count--; | |
75 | dev_priv->mm.object_memory -= size; | |
76 | } | |
77 | ||
21dd3734 CW |
78 | static int |
79 | i915_gem_wait_for_error(struct drm_device *dev) | |
30dbf0c0 CW |
80 | { |
81 | struct drm_i915_private *dev_priv = dev->dev_private; | |
82 | struct completion *x = &dev_priv->error_completion; | |
83 | unsigned long flags; | |
84 | int ret; | |
85 | ||
86 | if (!atomic_read(&dev_priv->mm.wedged)) | |
87 | return 0; | |
88 | ||
89 | ret = wait_for_completion_interruptible(x); | |
90 | if (ret) | |
91 | return ret; | |
92 | ||
21dd3734 CW |
93 | if (atomic_read(&dev_priv->mm.wedged)) { |
94 | /* GPU is hung, bump the completion count to account for | |
95 | * the token we just consumed so that we never hit zero and | |
96 | * end up waiting upon a subsequent completion event that | |
97 | * will never happen. | |
98 | */ | |
99 | spin_lock_irqsave(&x->wait.lock, flags); | |
100 | x->done++; | |
101 | spin_unlock_irqrestore(&x->wait.lock, flags); | |
102 | } | |
103 | return 0; | |
30dbf0c0 CW |
104 | } |
105 | ||
54cf91dc | 106 | int i915_mutex_lock_interruptible(struct drm_device *dev) |
76c1dec1 | 107 | { |
76c1dec1 CW |
108 | int ret; |
109 | ||
21dd3734 | 110 | ret = i915_gem_wait_for_error(dev); |
76c1dec1 CW |
111 | if (ret) |
112 | return ret; | |
113 | ||
114 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
115 | if (ret) | |
116 | return ret; | |
117 | ||
23bc5982 | 118 | WARN_ON(i915_verify_lists(dev)); |
76c1dec1 CW |
119 | return 0; |
120 | } | |
30dbf0c0 | 121 | |
7d1c4804 | 122 | static inline bool |
05394f39 | 123 | i915_gem_object_is_inactive(struct drm_i915_gem_object *obj) |
7d1c4804 | 124 | { |
05394f39 | 125 | return obj->gtt_space && !obj->active && obj->pin_count == 0; |
7d1c4804 CW |
126 | } |
127 | ||
2021746e CW |
128 | void i915_gem_do_init(struct drm_device *dev, |
129 | unsigned long start, | |
130 | unsigned long mappable_end, | |
131 | unsigned long end) | |
673a394b EA |
132 | { |
133 | drm_i915_private_t *dev_priv = dev->dev_private; | |
673a394b | 134 | |
bee4a186 | 135 | drm_mm_init(&dev_priv->mm.gtt_space, start, end - start); |
673a394b | 136 | |
bee4a186 CW |
137 | dev_priv->mm.gtt_start = start; |
138 | dev_priv->mm.gtt_mappable_end = mappable_end; | |
139 | dev_priv->mm.gtt_end = end; | |
73aa808f | 140 | dev_priv->mm.gtt_total = end - start; |
fb7d516a | 141 | dev_priv->mm.mappable_gtt_total = min(end, mappable_end) - start; |
bee4a186 CW |
142 | |
143 | /* Take over this portion of the GTT */ | |
144 | intel_gtt_clear_range(start / PAGE_SIZE, (end-start) / PAGE_SIZE); | |
79e53945 | 145 | } |
673a394b | 146 | |
79e53945 JB |
147 | int |
148 | i915_gem_init_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 149 | struct drm_file *file) |
79e53945 JB |
150 | { |
151 | struct drm_i915_gem_init *args = data; | |
2021746e CW |
152 | |
153 | if (args->gtt_start >= args->gtt_end || | |
154 | (args->gtt_end | args->gtt_start) & (PAGE_SIZE - 1)) | |
155 | return -EINVAL; | |
79e53945 JB |
156 | |
157 | mutex_lock(&dev->struct_mutex); | |
2021746e | 158 | i915_gem_do_init(dev, args->gtt_start, args->gtt_end, args->gtt_end); |
673a394b EA |
159 | mutex_unlock(&dev->struct_mutex); |
160 | ||
2021746e | 161 | return 0; |
673a394b EA |
162 | } |
163 | ||
5a125c3c EA |
164 | int |
165 | i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 166 | struct drm_file *file) |
5a125c3c | 167 | { |
73aa808f | 168 | struct drm_i915_private *dev_priv = dev->dev_private; |
5a125c3c | 169 | struct drm_i915_gem_get_aperture *args = data; |
6299f992 CW |
170 | struct drm_i915_gem_object *obj; |
171 | size_t pinned; | |
5a125c3c EA |
172 | |
173 | if (!(dev->driver->driver_features & DRIVER_GEM)) | |
174 | return -ENODEV; | |
175 | ||
6299f992 | 176 | pinned = 0; |
73aa808f | 177 | mutex_lock(&dev->struct_mutex); |
6299f992 CW |
178 | list_for_each_entry(obj, &dev_priv->mm.pinned_list, mm_list) |
179 | pinned += obj->gtt_space->size; | |
73aa808f | 180 | mutex_unlock(&dev->struct_mutex); |
5a125c3c | 181 | |
6299f992 CW |
182 | args->aper_size = dev_priv->mm.gtt_total; |
183 | args->aper_available_size = args->aper_size -pinned; | |
184 | ||
5a125c3c EA |
185 | return 0; |
186 | } | |
187 | ||
673a394b EA |
188 | /** |
189 | * Creates a new mm object and returns a handle to it. | |
190 | */ | |
191 | int | |
192 | i915_gem_create_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 193 | struct drm_file *file) |
673a394b EA |
194 | { |
195 | struct drm_i915_gem_create *args = data; | |
05394f39 | 196 | struct drm_i915_gem_object *obj; |
a1a2d1d3 PP |
197 | int ret; |
198 | u32 handle; | |
673a394b EA |
199 | |
200 | args->size = roundup(args->size, PAGE_SIZE); | |
201 | ||
202 | /* Allocate the new object */ | |
ac52bc56 | 203 | obj = i915_gem_alloc_object(dev, args->size); |
673a394b EA |
204 | if (obj == NULL) |
205 | return -ENOMEM; | |
206 | ||
05394f39 | 207 | ret = drm_gem_handle_create(file, &obj->base, &handle); |
1dfd9754 | 208 | if (ret) { |
05394f39 CW |
209 | drm_gem_object_release(&obj->base); |
210 | i915_gem_info_remove_obj(dev->dev_private, obj->base.size); | |
202f2fef | 211 | kfree(obj); |
673a394b | 212 | return ret; |
1dfd9754 | 213 | } |
673a394b | 214 | |
202f2fef | 215 | /* drop reference from allocate - handle holds it now */ |
05394f39 | 216 | drm_gem_object_unreference(&obj->base); |
202f2fef CW |
217 | trace_i915_gem_object_create(obj); |
218 | ||
1dfd9754 | 219 | args->handle = handle; |
673a394b EA |
220 | return 0; |
221 | } | |
222 | ||
05394f39 | 223 | static int i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj) |
280b713b | 224 | { |
05394f39 | 225 | drm_i915_private_t *dev_priv = obj->base.dev->dev_private; |
280b713b EA |
226 | |
227 | return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 && | |
05394f39 | 228 | obj->tiling_mode != I915_TILING_NONE; |
280b713b EA |
229 | } |
230 | ||
99a03df5 | 231 | static inline void |
40123c1f EA |
232 | slow_shmem_copy(struct page *dst_page, |
233 | int dst_offset, | |
234 | struct page *src_page, | |
235 | int src_offset, | |
236 | int length) | |
237 | { | |
238 | char *dst_vaddr, *src_vaddr; | |
239 | ||
99a03df5 CW |
240 | dst_vaddr = kmap(dst_page); |
241 | src_vaddr = kmap(src_page); | |
40123c1f EA |
242 | |
243 | memcpy(dst_vaddr + dst_offset, src_vaddr + src_offset, length); | |
244 | ||
99a03df5 CW |
245 | kunmap(src_page); |
246 | kunmap(dst_page); | |
40123c1f EA |
247 | } |
248 | ||
99a03df5 | 249 | static inline void |
280b713b EA |
250 | slow_shmem_bit17_copy(struct page *gpu_page, |
251 | int gpu_offset, | |
252 | struct page *cpu_page, | |
253 | int cpu_offset, | |
254 | int length, | |
255 | int is_read) | |
256 | { | |
257 | char *gpu_vaddr, *cpu_vaddr; | |
258 | ||
259 | /* Use the unswizzled path if this page isn't affected. */ | |
260 | if ((page_to_phys(gpu_page) & (1 << 17)) == 0) { | |
261 | if (is_read) | |
262 | return slow_shmem_copy(cpu_page, cpu_offset, | |
263 | gpu_page, gpu_offset, length); | |
264 | else | |
265 | return slow_shmem_copy(gpu_page, gpu_offset, | |
266 | cpu_page, cpu_offset, length); | |
267 | } | |
268 | ||
99a03df5 CW |
269 | gpu_vaddr = kmap(gpu_page); |
270 | cpu_vaddr = kmap(cpu_page); | |
280b713b EA |
271 | |
272 | /* Copy the data, XORing A6 with A17 (1). The user already knows he's | |
273 | * XORing with the other bits (A9 for Y, A9 and A10 for X) | |
274 | */ | |
275 | while (length > 0) { | |
276 | int cacheline_end = ALIGN(gpu_offset + 1, 64); | |
277 | int this_length = min(cacheline_end - gpu_offset, length); | |
278 | int swizzled_gpu_offset = gpu_offset ^ 64; | |
279 | ||
280 | if (is_read) { | |
281 | memcpy(cpu_vaddr + cpu_offset, | |
282 | gpu_vaddr + swizzled_gpu_offset, | |
283 | this_length); | |
284 | } else { | |
285 | memcpy(gpu_vaddr + swizzled_gpu_offset, | |
286 | cpu_vaddr + cpu_offset, | |
287 | this_length); | |
288 | } | |
289 | cpu_offset += this_length; | |
290 | gpu_offset += this_length; | |
291 | length -= this_length; | |
292 | } | |
293 | ||
99a03df5 CW |
294 | kunmap(cpu_page); |
295 | kunmap(gpu_page); | |
280b713b EA |
296 | } |
297 | ||
eb01459f EA |
298 | /** |
299 | * This is the fast shmem pread path, which attempts to copy_from_user directly | |
300 | * from the backing pages of the object to the user's address space. On a | |
301 | * fault, it fails so we can fall back to i915_gem_shmem_pwrite_slow(). | |
302 | */ | |
303 | static int | |
05394f39 CW |
304 | i915_gem_shmem_pread_fast(struct drm_device *dev, |
305 | struct drm_i915_gem_object *obj, | |
eb01459f | 306 | struct drm_i915_gem_pread *args, |
05394f39 | 307 | struct drm_file *file) |
eb01459f | 308 | { |
05394f39 | 309 | struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping; |
eb01459f | 310 | ssize_t remain; |
e5281ccd | 311 | loff_t offset; |
eb01459f EA |
312 | char __user *user_data; |
313 | int page_offset, page_length; | |
eb01459f EA |
314 | |
315 | user_data = (char __user *) (uintptr_t) args->data_ptr; | |
316 | remain = args->size; | |
317 | ||
eb01459f EA |
318 | offset = args->offset; |
319 | ||
320 | while (remain > 0) { | |
e5281ccd CW |
321 | struct page *page; |
322 | char *vaddr; | |
323 | int ret; | |
324 | ||
eb01459f EA |
325 | /* Operation in this page |
326 | * | |
eb01459f EA |
327 | * page_offset = offset within page |
328 | * page_length = bytes to copy for this page | |
329 | */ | |
eb01459f EA |
330 | page_offset = offset & (PAGE_SIZE-1); |
331 | page_length = remain; | |
332 | if ((page_offset + remain) > PAGE_SIZE) | |
333 | page_length = PAGE_SIZE - page_offset; | |
334 | ||
e5281ccd CW |
335 | page = read_cache_page_gfp(mapping, offset >> PAGE_SHIFT, |
336 | GFP_HIGHUSER | __GFP_RECLAIMABLE); | |
337 | if (IS_ERR(page)) | |
338 | return PTR_ERR(page); | |
339 | ||
340 | vaddr = kmap_atomic(page); | |
341 | ret = __copy_to_user_inatomic(user_data, | |
342 | vaddr + page_offset, | |
343 | page_length); | |
344 | kunmap_atomic(vaddr); | |
345 | ||
346 | mark_page_accessed(page); | |
347 | page_cache_release(page); | |
348 | if (ret) | |
4f27b75d | 349 | return -EFAULT; |
eb01459f EA |
350 | |
351 | remain -= page_length; | |
352 | user_data += page_length; | |
353 | offset += page_length; | |
354 | } | |
355 | ||
4f27b75d | 356 | return 0; |
eb01459f EA |
357 | } |
358 | ||
359 | /** | |
360 | * This is the fallback shmem pread path, which allocates temporary storage | |
361 | * in kernel space to copy_to_user into outside of the struct_mutex, so we | |
362 | * can copy out of the object's backing pages while holding the struct mutex | |
363 | * and not take page faults. | |
364 | */ | |
365 | static int | |
05394f39 CW |
366 | i915_gem_shmem_pread_slow(struct drm_device *dev, |
367 | struct drm_i915_gem_object *obj, | |
eb01459f | 368 | struct drm_i915_gem_pread *args, |
05394f39 | 369 | struct drm_file *file) |
eb01459f | 370 | { |
05394f39 | 371 | struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping; |
eb01459f EA |
372 | struct mm_struct *mm = current->mm; |
373 | struct page **user_pages; | |
374 | ssize_t remain; | |
375 | loff_t offset, pinned_pages, i; | |
376 | loff_t first_data_page, last_data_page, num_pages; | |
e5281ccd CW |
377 | int shmem_page_offset; |
378 | int data_page_index, data_page_offset; | |
eb01459f EA |
379 | int page_length; |
380 | int ret; | |
381 | uint64_t data_ptr = args->data_ptr; | |
280b713b | 382 | int do_bit17_swizzling; |
eb01459f EA |
383 | |
384 | remain = args->size; | |
385 | ||
386 | /* Pin the user pages containing the data. We can't fault while | |
387 | * holding the struct mutex, yet we want to hold it while | |
388 | * dereferencing the user data. | |
389 | */ | |
390 | first_data_page = data_ptr / PAGE_SIZE; | |
391 | last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE; | |
392 | num_pages = last_data_page - first_data_page + 1; | |
393 | ||
4f27b75d | 394 | user_pages = drm_malloc_ab(num_pages, sizeof(struct page *)); |
eb01459f EA |
395 | if (user_pages == NULL) |
396 | return -ENOMEM; | |
397 | ||
4f27b75d | 398 | mutex_unlock(&dev->struct_mutex); |
eb01459f EA |
399 | down_read(&mm->mmap_sem); |
400 | pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr, | |
e5e9ecde | 401 | num_pages, 1, 0, user_pages, NULL); |
eb01459f | 402 | up_read(&mm->mmap_sem); |
4f27b75d | 403 | mutex_lock(&dev->struct_mutex); |
eb01459f EA |
404 | if (pinned_pages < num_pages) { |
405 | ret = -EFAULT; | |
4f27b75d | 406 | goto out; |
eb01459f EA |
407 | } |
408 | ||
4f27b75d CW |
409 | ret = i915_gem_object_set_cpu_read_domain_range(obj, |
410 | args->offset, | |
411 | args->size); | |
07f73f69 | 412 | if (ret) |
4f27b75d | 413 | goto out; |
eb01459f | 414 | |
4f27b75d | 415 | do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj); |
eb01459f | 416 | |
eb01459f EA |
417 | offset = args->offset; |
418 | ||
419 | while (remain > 0) { | |
e5281ccd CW |
420 | struct page *page; |
421 | ||
eb01459f EA |
422 | /* Operation in this page |
423 | * | |
eb01459f EA |
424 | * shmem_page_offset = offset within page in shmem file |
425 | * data_page_index = page number in get_user_pages return | |
426 | * data_page_offset = offset with data_page_index page. | |
427 | * page_length = bytes to copy for this page | |
428 | */ | |
eb01459f EA |
429 | shmem_page_offset = offset & ~PAGE_MASK; |
430 | data_page_index = data_ptr / PAGE_SIZE - first_data_page; | |
431 | data_page_offset = data_ptr & ~PAGE_MASK; | |
432 | ||
433 | page_length = remain; | |
434 | if ((shmem_page_offset + page_length) > PAGE_SIZE) | |
435 | page_length = PAGE_SIZE - shmem_page_offset; | |
436 | if ((data_page_offset + page_length) > PAGE_SIZE) | |
437 | page_length = PAGE_SIZE - data_page_offset; | |
438 | ||
e5281ccd CW |
439 | page = read_cache_page_gfp(mapping, offset >> PAGE_SHIFT, |
440 | GFP_HIGHUSER | __GFP_RECLAIMABLE); | |
441 | if (IS_ERR(page)) | |
442 | return PTR_ERR(page); | |
443 | ||
280b713b | 444 | if (do_bit17_swizzling) { |
e5281ccd | 445 | slow_shmem_bit17_copy(page, |
280b713b | 446 | shmem_page_offset, |
99a03df5 CW |
447 | user_pages[data_page_index], |
448 | data_page_offset, | |
449 | page_length, | |
450 | 1); | |
451 | } else { | |
452 | slow_shmem_copy(user_pages[data_page_index], | |
453 | data_page_offset, | |
e5281ccd | 454 | page, |
99a03df5 CW |
455 | shmem_page_offset, |
456 | page_length); | |
280b713b | 457 | } |
eb01459f | 458 | |
e5281ccd CW |
459 | mark_page_accessed(page); |
460 | page_cache_release(page); | |
461 | ||
eb01459f EA |
462 | remain -= page_length; |
463 | data_ptr += page_length; | |
464 | offset += page_length; | |
465 | } | |
466 | ||
4f27b75d | 467 | out: |
eb01459f EA |
468 | for (i = 0; i < pinned_pages; i++) { |
469 | SetPageDirty(user_pages[i]); | |
e5281ccd | 470 | mark_page_accessed(user_pages[i]); |
eb01459f EA |
471 | page_cache_release(user_pages[i]); |
472 | } | |
8e7d2b2c | 473 | drm_free_large(user_pages); |
eb01459f EA |
474 | |
475 | return ret; | |
476 | } | |
477 | ||
673a394b EA |
478 | /** |
479 | * Reads data from the object referenced by handle. | |
480 | * | |
481 | * On error, the contents of *data are undefined. | |
482 | */ | |
483 | int | |
484 | i915_gem_pread_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 485 | struct drm_file *file) |
673a394b EA |
486 | { |
487 | struct drm_i915_gem_pread *args = data; | |
05394f39 | 488 | struct drm_i915_gem_object *obj; |
35b62a89 | 489 | int ret = 0; |
673a394b | 490 | |
51311d0a CW |
491 | if (args->size == 0) |
492 | return 0; | |
493 | ||
494 | if (!access_ok(VERIFY_WRITE, | |
495 | (char __user *)(uintptr_t)args->data_ptr, | |
496 | args->size)) | |
497 | return -EFAULT; | |
498 | ||
499 | ret = fault_in_pages_writeable((char __user *)(uintptr_t)args->data_ptr, | |
500 | args->size); | |
501 | if (ret) | |
502 | return -EFAULT; | |
503 | ||
4f27b75d | 504 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 505 | if (ret) |
4f27b75d | 506 | return ret; |
673a394b | 507 | |
05394f39 | 508 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
1d7cfea1 CW |
509 | if (obj == NULL) { |
510 | ret = -ENOENT; | |
511 | goto unlock; | |
4f27b75d | 512 | } |
673a394b | 513 | |
7dcd2499 | 514 | /* Bounds check source. */ |
05394f39 CW |
515 | if (args->offset > obj->base.size || |
516 | args->size > obj->base.size - args->offset) { | |
ce9d419d | 517 | ret = -EINVAL; |
35b62a89 | 518 | goto out; |
ce9d419d CW |
519 | } |
520 | ||
db53a302 CW |
521 | trace_i915_gem_object_pread(obj, args->offset, args->size); |
522 | ||
4f27b75d CW |
523 | ret = i915_gem_object_set_cpu_read_domain_range(obj, |
524 | args->offset, | |
525 | args->size); | |
526 | if (ret) | |
e5281ccd | 527 | goto out; |
4f27b75d CW |
528 | |
529 | ret = -EFAULT; | |
530 | if (!i915_gem_object_needs_bit17_swizzle(obj)) | |
05394f39 | 531 | ret = i915_gem_shmem_pread_fast(dev, obj, args, file); |
4f27b75d | 532 | if (ret == -EFAULT) |
05394f39 | 533 | ret = i915_gem_shmem_pread_slow(dev, obj, args, file); |
673a394b | 534 | |
35b62a89 | 535 | out: |
05394f39 | 536 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 537 | unlock: |
4f27b75d | 538 | mutex_unlock(&dev->struct_mutex); |
eb01459f | 539 | return ret; |
673a394b EA |
540 | } |
541 | ||
0839ccb8 KP |
542 | /* This is the fast write path which cannot handle |
543 | * page faults in the source data | |
9b7530cc | 544 | */ |
0839ccb8 KP |
545 | |
546 | static inline int | |
547 | fast_user_write(struct io_mapping *mapping, | |
548 | loff_t page_base, int page_offset, | |
549 | char __user *user_data, | |
550 | int length) | |
9b7530cc | 551 | { |
9b7530cc | 552 | char *vaddr_atomic; |
0839ccb8 | 553 | unsigned long unwritten; |
9b7530cc | 554 | |
3e4d3af5 | 555 | vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base); |
0839ccb8 KP |
556 | unwritten = __copy_from_user_inatomic_nocache(vaddr_atomic + page_offset, |
557 | user_data, length); | |
3e4d3af5 | 558 | io_mapping_unmap_atomic(vaddr_atomic); |
fbd5a26d | 559 | return unwritten; |
0839ccb8 KP |
560 | } |
561 | ||
562 | /* Here's the write path which can sleep for | |
563 | * page faults | |
564 | */ | |
565 | ||
ab34c226 | 566 | static inline void |
3de09aa3 EA |
567 | slow_kernel_write(struct io_mapping *mapping, |
568 | loff_t gtt_base, int gtt_offset, | |
569 | struct page *user_page, int user_offset, | |
570 | int length) | |
0839ccb8 | 571 | { |
ab34c226 CW |
572 | char __iomem *dst_vaddr; |
573 | char *src_vaddr; | |
0839ccb8 | 574 | |
ab34c226 CW |
575 | dst_vaddr = io_mapping_map_wc(mapping, gtt_base); |
576 | src_vaddr = kmap(user_page); | |
577 | ||
578 | memcpy_toio(dst_vaddr + gtt_offset, | |
579 | src_vaddr + user_offset, | |
580 | length); | |
581 | ||
582 | kunmap(user_page); | |
583 | io_mapping_unmap(dst_vaddr); | |
9b7530cc LT |
584 | } |
585 | ||
3de09aa3 EA |
586 | /** |
587 | * This is the fast pwrite path, where we copy the data directly from the | |
588 | * user into the GTT, uncached. | |
589 | */ | |
673a394b | 590 | static int |
05394f39 CW |
591 | i915_gem_gtt_pwrite_fast(struct drm_device *dev, |
592 | struct drm_i915_gem_object *obj, | |
3de09aa3 | 593 | struct drm_i915_gem_pwrite *args, |
05394f39 | 594 | struct drm_file *file) |
673a394b | 595 | { |
0839ccb8 | 596 | drm_i915_private_t *dev_priv = dev->dev_private; |
673a394b | 597 | ssize_t remain; |
0839ccb8 | 598 | loff_t offset, page_base; |
673a394b | 599 | char __user *user_data; |
0839ccb8 | 600 | int page_offset, page_length; |
673a394b EA |
601 | |
602 | user_data = (char __user *) (uintptr_t) args->data_ptr; | |
603 | remain = args->size; | |
673a394b | 604 | |
05394f39 | 605 | offset = obj->gtt_offset + args->offset; |
673a394b EA |
606 | |
607 | while (remain > 0) { | |
608 | /* Operation in this page | |
609 | * | |
0839ccb8 KP |
610 | * page_base = page offset within aperture |
611 | * page_offset = offset within page | |
612 | * page_length = bytes to copy for this page | |
673a394b | 613 | */ |
0839ccb8 KP |
614 | page_base = (offset & ~(PAGE_SIZE-1)); |
615 | page_offset = offset & (PAGE_SIZE-1); | |
616 | page_length = remain; | |
617 | if ((page_offset + remain) > PAGE_SIZE) | |
618 | page_length = PAGE_SIZE - page_offset; | |
619 | ||
0839ccb8 | 620 | /* If we get a fault while copying data, then (presumably) our |
3de09aa3 EA |
621 | * source page isn't available. Return the error and we'll |
622 | * retry in the slow path. | |
0839ccb8 | 623 | */ |
fbd5a26d CW |
624 | if (fast_user_write(dev_priv->mm.gtt_mapping, page_base, |
625 | page_offset, user_data, page_length)) | |
626 | ||
627 | return -EFAULT; | |
673a394b | 628 | |
0839ccb8 KP |
629 | remain -= page_length; |
630 | user_data += page_length; | |
631 | offset += page_length; | |
673a394b | 632 | } |
673a394b | 633 | |
fbd5a26d | 634 | return 0; |
673a394b EA |
635 | } |
636 | ||
3de09aa3 EA |
637 | /** |
638 | * This is the fallback GTT pwrite path, which uses get_user_pages to pin | |
639 | * the memory and maps it using kmap_atomic for copying. | |
640 | * | |
641 | * This code resulted in x11perf -rgb10text consuming about 10% more CPU | |
642 | * than using i915_gem_gtt_pwrite_fast on a G45 (32-bit). | |
643 | */ | |
3043c60c | 644 | static int |
05394f39 CW |
645 | i915_gem_gtt_pwrite_slow(struct drm_device *dev, |
646 | struct drm_i915_gem_object *obj, | |
3de09aa3 | 647 | struct drm_i915_gem_pwrite *args, |
05394f39 | 648 | struct drm_file *file) |
673a394b | 649 | { |
3de09aa3 EA |
650 | drm_i915_private_t *dev_priv = dev->dev_private; |
651 | ssize_t remain; | |
652 | loff_t gtt_page_base, offset; | |
653 | loff_t first_data_page, last_data_page, num_pages; | |
654 | loff_t pinned_pages, i; | |
655 | struct page **user_pages; | |
656 | struct mm_struct *mm = current->mm; | |
657 | int gtt_page_offset, data_page_offset, data_page_index, page_length; | |
673a394b | 658 | int ret; |
3de09aa3 EA |
659 | uint64_t data_ptr = args->data_ptr; |
660 | ||
661 | remain = args->size; | |
662 | ||
663 | /* Pin the user pages containing the data. We can't fault while | |
664 | * holding the struct mutex, and all of the pwrite implementations | |
665 | * want to hold it while dereferencing the user data. | |
666 | */ | |
667 | first_data_page = data_ptr / PAGE_SIZE; | |
668 | last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE; | |
669 | num_pages = last_data_page - first_data_page + 1; | |
670 | ||
fbd5a26d | 671 | user_pages = drm_malloc_ab(num_pages, sizeof(struct page *)); |
3de09aa3 EA |
672 | if (user_pages == NULL) |
673 | return -ENOMEM; | |
674 | ||
fbd5a26d | 675 | mutex_unlock(&dev->struct_mutex); |
3de09aa3 EA |
676 | down_read(&mm->mmap_sem); |
677 | pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr, | |
678 | num_pages, 0, 0, user_pages, NULL); | |
679 | up_read(&mm->mmap_sem); | |
fbd5a26d | 680 | mutex_lock(&dev->struct_mutex); |
3de09aa3 EA |
681 | if (pinned_pages < num_pages) { |
682 | ret = -EFAULT; | |
683 | goto out_unpin_pages; | |
684 | } | |
673a394b | 685 | |
d9e86c0e CW |
686 | ret = i915_gem_object_set_to_gtt_domain(obj, true); |
687 | if (ret) | |
688 | goto out_unpin_pages; | |
689 | ||
690 | ret = i915_gem_object_put_fence(obj); | |
3de09aa3 | 691 | if (ret) |
fbd5a26d | 692 | goto out_unpin_pages; |
3de09aa3 | 693 | |
05394f39 | 694 | offset = obj->gtt_offset + args->offset; |
3de09aa3 EA |
695 | |
696 | while (remain > 0) { | |
697 | /* Operation in this page | |
698 | * | |
699 | * gtt_page_base = page offset within aperture | |
700 | * gtt_page_offset = offset within page in aperture | |
701 | * data_page_index = page number in get_user_pages return | |
702 | * data_page_offset = offset with data_page_index page. | |
703 | * page_length = bytes to copy for this page | |
704 | */ | |
705 | gtt_page_base = offset & PAGE_MASK; | |
706 | gtt_page_offset = offset & ~PAGE_MASK; | |
707 | data_page_index = data_ptr / PAGE_SIZE - first_data_page; | |
708 | data_page_offset = data_ptr & ~PAGE_MASK; | |
709 | ||
710 | page_length = remain; | |
711 | if ((gtt_page_offset + page_length) > PAGE_SIZE) | |
712 | page_length = PAGE_SIZE - gtt_page_offset; | |
713 | if ((data_page_offset + page_length) > PAGE_SIZE) | |
714 | page_length = PAGE_SIZE - data_page_offset; | |
715 | ||
ab34c226 CW |
716 | slow_kernel_write(dev_priv->mm.gtt_mapping, |
717 | gtt_page_base, gtt_page_offset, | |
718 | user_pages[data_page_index], | |
719 | data_page_offset, | |
720 | page_length); | |
3de09aa3 EA |
721 | |
722 | remain -= page_length; | |
723 | offset += page_length; | |
724 | data_ptr += page_length; | |
725 | } | |
726 | ||
3de09aa3 EA |
727 | out_unpin_pages: |
728 | for (i = 0; i < pinned_pages; i++) | |
729 | page_cache_release(user_pages[i]); | |
8e7d2b2c | 730 | drm_free_large(user_pages); |
3de09aa3 EA |
731 | |
732 | return ret; | |
733 | } | |
734 | ||
40123c1f EA |
735 | /** |
736 | * This is the fast shmem pwrite path, which attempts to directly | |
737 | * copy_from_user into the kmapped pages backing the object. | |
738 | */ | |
3043c60c | 739 | static int |
05394f39 CW |
740 | i915_gem_shmem_pwrite_fast(struct drm_device *dev, |
741 | struct drm_i915_gem_object *obj, | |
40123c1f | 742 | struct drm_i915_gem_pwrite *args, |
05394f39 | 743 | struct drm_file *file) |
673a394b | 744 | { |
05394f39 | 745 | struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping; |
40123c1f | 746 | ssize_t remain; |
e5281ccd | 747 | loff_t offset; |
40123c1f EA |
748 | char __user *user_data; |
749 | int page_offset, page_length; | |
40123c1f EA |
750 | |
751 | user_data = (char __user *) (uintptr_t) args->data_ptr; | |
752 | remain = args->size; | |
673a394b | 753 | |
40123c1f | 754 | offset = args->offset; |
05394f39 | 755 | obj->dirty = 1; |
40123c1f EA |
756 | |
757 | while (remain > 0) { | |
e5281ccd CW |
758 | struct page *page; |
759 | char *vaddr; | |
760 | int ret; | |
761 | ||
40123c1f EA |
762 | /* Operation in this page |
763 | * | |
40123c1f EA |
764 | * page_offset = offset within page |
765 | * page_length = bytes to copy for this page | |
766 | */ | |
40123c1f EA |
767 | page_offset = offset & (PAGE_SIZE-1); |
768 | page_length = remain; | |
769 | if ((page_offset + remain) > PAGE_SIZE) | |
770 | page_length = PAGE_SIZE - page_offset; | |
771 | ||
e5281ccd CW |
772 | page = read_cache_page_gfp(mapping, offset >> PAGE_SHIFT, |
773 | GFP_HIGHUSER | __GFP_RECLAIMABLE); | |
774 | if (IS_ERR(page)) | |
775 | return PTR_ERR(page); | |
776 | ||
777 | vaddr = kmap_atomic(page, KM_USER0); | |
778 | ret = __copy_from_user_inatomic(vaddr + page_offset, | |
779 | user_data, | |
780 | page_length); | |
781 | kunmap_atomic(vaddr, KM_USER0); | |
782 | ||
783 | set_page_dirty(page); | |
784 | mark_page_accessed(page); | |
785 | page_cache_release(page); | |
786 | ||
787 | /* If we get a fault while copying data, then (presumably) our | |
788 | * source page isn't available. Return the error and we'll | |
789 | * retry in the slow path. | |
790 | */ | |
791 | if (ret) | |
fbd5a26d | 792 | return -EFAULT; |
40123c1f EA |
793 | |
794 | remain -= page_length; | |
795 | user_data += page_length; | |
796 | offset += page_length; | |
797 | } | |
798 | ||
fbd5a26d | 799 | return 0; |
40123c1f EA |
800 | } |
801 | ||
802 | /** | |
803 | * This is the fallback shmem pwrite path, which uses get_user_pages to pin | |
804 | * the memory and maps it using kmap_atomic for copying. | |
805 | * | |
806 | * This avoids taking mmap_sem for faulting on the user's address while the | |
807 | * struct_mutex is held. | |
808 | */ | |
809 | static int | |
05394f39 CW |
810 | i915_gem_shmem_pwrite_slow(struct drm_device *dev, |
811 | struct drm_i915_gem_object *obj, | |
40123c1f | 812 | struct drm_i915_gem_pwrite *args, |
05394f39 | 813 | struct drm_file *file) |
40123c1f | 814 | { |
05394f39 | 815 | struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping; |
40123c1f EA |
816 | struct mm_struct *mm = current->mm; |
817 | struct page **user_pages; | |
818 | ssize_t remain; | |
819 | loff_t offset, pinned_pages, i; | |
820 | loff_t first_data_page, last_data_page, num_pages; | |
e5281ccd | 821 | int shmem_page_offset; |
40123c1f EA |
822 | int data_page_index, data_page_offset; |
823 | int page_length; | |
824 | int ret; | |
825 | uint64_t data_ptr = args->data_ptr; | |
280b713b | 826 | int do_bit17_swizzling; |
40123c1f EA |
827 | |
828 | remain = args->size; | |
829 | ||
830 | /* Pin the user pages containing the data. We can't fault while | |
831 | * holding the struct mutex, and all of the pwrite implementations | |
832 | * want to hold it while dereferencing the user data. | |
833 | */ | |
834 | first_data_page = data_ptr / PAGE_SIZE; | |
835 | last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE; | |
836 | num_pages = last_data_page - first_data_page + 1; | |
837 | ||
4f27b75d | 838 | user_pages = drm_malloc_ab(num_pages, sizeof(struct page *)); |
40123c1f EA |
839 | if (user_pages == NULL) |
840 | return -ENOMEM; | |
841 | ||
fbd5a26d | 842 | mutex_unlock(&dev->struct_mutex); |
40123c1f EA |
843 | down_read(&mm->mmap_sem); |
844 | pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr, | |
845 | num_pages, 0, 0, user_pages, NULL); | |
846 | up_read(&mm->mmap_sem); | |
fbd5a26d | 847 | mutex_lock(&dev->struct_mutex); |
40123c1f EA |
848 | if (pinned_pages < num_pages) { |
849 | ret = -EFAULT; | |
fbd5a26d | 850 | goto out; |
673a394b EA |
851 | } |
852 | ||
fbd5a26d | 853 | ret = i915_gem_object_set_to_cpu_domain(obj, 1); |
07f73f69 | 854 | if (ret) |
fbd5a26d | 855 | goto out; |
40123c1f | 856 | |
fbd5a26d | 857 | do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj); |
40123c1f | 858 | |
673a394b | 859 | offset = args->offset; |
05394f39 | 860 | obj->dirty = 1; |
673a394b | 861 | |
40123c1f | 862 | while (remain > 0) { |
e5281ccd CW |
863 | struct page *page; |
864 | ||
40123c1f EA |
865 | /* Operation in this page |
866 | * | |
40123c1f EA |
867 | * shmem_page_offset = offset within page in shmem file |
868 | * data_page_index = page number in get_user_pages return | |
869 | * data_page_offset = offset with data_page_index page. | |
870 | * page_length = bytes to copy for this page | |
871 | */ | |
40123c1f EA |
872 | shmem_page_offset = offset & ~PAGE_MASK; |
873 | data_page_index = data_ptr / PAGE_SIZE - first_data_page; | |
874 | data_page_offset = data_ptr & ~PAGE_MASK; | |
875 | ||
876 | page_length = remain; | |
877 | if ((shmem_page_offset + page_length) > PAGE_SIZE) | |
878 | page_length = PAGE_SIZE - shmem_page_offset; | |
879 | if ((data_page_offset + page_length) > PAGE_SIZE) | |
880 | page_length = PAGE_SIZE - data_page_offset; | |
881 | ||
e5281ccd CW |
882 | page = read_cache_page_gfp(mapping, offset >> PAGE_SHIFT, |
883 | GFP_HIGHUSER | __GFP_RECLAIMABLE); | |
884 | if (IS_ERR(page)) { | |
885 | ret = PTR_ERR(page); | |
886 | goto out; | |
887 | } | |
888 | ||
280b713b | 889 | if (do_bit17_swizzling) { |
e5281ccd | 890 | slow_shmem_bit17_copy(page, |
280b713b EA |
891 | shmem_page_offset, |
892 | user_pages[data_page_index], | |
893 | data_page_offset, | |
99a03df5 CW |
894 | page_length, |
895 | 0); | |
896 | } else { | |
e5281ccd | 897 | slow_shmem_copy(page, |
99a03df5 CW |
898 | shmem_page_offset, |
899 | user_pages[data_page_index], | |
900 | data_page_offset, | |
901 | page_length); | |
280b713b | 902 | } |
40123c1f | 903 | |
e5281ccd CW |
904 | set_page_dirty(page); |
905 | mark_page_accessed(page); | |
906 | page_cache_release(page); | |
907 | ||
40123c1f EA |
908 | remain -= page_length; |
909 | data_ptr += page_length; | |
910 | offset += page_length; | |
673a394b EA |
911 | } |
912 | ||
fbd5a26d | 913 | out: |
40123c1f EA |
914 | for (i = 0; i < pinned_pages; i++) |
915 | page_cache_release(user_pages[i]); | |
8e7d2b2c | 916 | drm_free_large(user_pages); |
673a394b | 917 | |
40123c1f | 918 | return ret; |
673a394b EA |
919 | } |
920 | ||
921 | /** | |
922 | * Writes data to the object referenced by handle. | |
923 | * | |
924 | * On error, the contents of the buffer that were to be modified are undefined. | |
925 | */ | |
926 | int | |
927 | i915_gem_pwrite_ioctl(struct drm_device *dev, void *data, | |
fbd5a26d | 928 | struct drm_file *file) |
673a394b EA |
929 | { |
930 | struct drm_i915_gem_pwrite *args = data; | |
05394f39 | 931 | struct drm_i915_gem_object *obj; |
51311d0a CW |
932 | int ret; |
933 | ||
934 | if (args->size == 0) | |
935 | return 0; | |
936 | ||
937 | if (!access_ok(VERIFY_READ, | |
938 | (char __user *)(uintptr_t)args->data_ptr, | |
939 | args->size)) | |
940 | return -EFAULT; | |
941 | ||
942 | ret = fault_in_pages_readable((char __user *)(uintptr_t)args->data_ptr, | |
943 | args->size); | |
944 | if (ret) | |
945 | return -EFAULT; | |
673a394b | 946 | |
fbd5a26d | 947 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 948 | if (ret) |
fbd5a26d | 949 | return ret; |
1d7cfea1 | 950 | |
05394f39 | 951 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
1d7cfea1 CW |
952 | if (obj == NULL) { |
953 | ret = -ENOENT; | |
954 | goto unlock; | |
fbd5a26d | 955 | } |
673a394b | 956 | |
7dcd2499 | 957 | /* Bounds check destination. */ |
05394f39 CW |
958 | if (args->offset > obj->base.size || |
959 | args->size > obj->base.size - args->offset) { | |
ce9d419d | 960 | ret = -EINVAL; |
35b62a89 | 961 | goto out; |
ce9d419d CW |
962 | } |
963 | ||
db53a302 CW |
964 | trace_i915_gem_object_pwrite(obj, args->offset, args->size); |
965 | ||
673a394b EA |
966 | /* We can only do the GTT pwrite on untiled buffers, as otherwise |
967 | * it would end up going through the fenced access, and we'll get | |
968 | * different detiling behavior between reading and writing. | |
969 | * pread/pwrite currently are reading and writing from the CPU | |
970 | * perspective, requiring manual detiling by the client. | |
971 | */ | |
05394f39 | 972 | if (obj->phys_obj) |
fbd5a26d | 973 | ret = i915_gem_phys_pwrite(dev, obj, args, file); |
d9e86c0e | 974 | else if (obj->gtt_space && |
05394f39 | 975 | obj->base.write_domain != I915_GEM_DOMAIN_CPU) { |
75e9e915 | 976 | ret = i915_gem_object_pin(obj, 0, true); |
fbd5a26d CW |
977 | if (ret) |
978 | goto out; | |
979 | ||
d9e86c0e CW |
980 | ret = i915_gem_object_set_to_gtt_domain(obj, true); |
981 | if (ret) | |
982 | goto out_unpin; | |
983 | ||
984 | ret = i915_gem_object_put_fence(obj); | |
fbd5a26d CW |
985 | if (ret) |
986 | goto out_unpin; | |
987 | ||
988 | ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file); | |
989 | if (ret == -EFAULT) | |
990 | ret = i915_gem_gtt_pwrite_slow(dev, obj, args, file); | |
991 | ||
992 | out_unpin: | |
993 | i915_gem_object_unpin(obj); | |
40123c1f | 994 | } else { |
fbd5a26d CW |
995 | ret = i915_gem_object_set_to_cpu_domain(obj, 1); |
996 | if (ret) | |
e5281ccd | 997 | goto out; |
673a394b | 998 | |
fbd5a26d CW |
999 | ret = -EFAULT; |
1000 | if (!i915_gem_object_needs_bit17_swizzle(obj)) | |
1001 | ret = i915_gem_shmem_pwrite_fast(dev, obj, args, file); | |
1002 | if (ret == -EFAULT) | |
1003 | ret = i915_gem_shmem_pwrite_slow(dev, obj, args, file); | |
fbd5a26d | 1004 | } |
673a394b | 1005 | |
35b62a89 | 1006 | out: |
05394f39 | 1007 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 1008 | unlock: |
fbd5a26d | 1009 | mutex_unlock(&dev->struct_mutex); |
673a394b EA |
1010 | return ret; |
1011 | } | |
1012 | ||
1013 | /** | |
2ef7eeaa EA |
1014 | * Called when user space prepares to use an object with the CPU, either |
1015 | * through the mmap ioctl's mapping or a GTT mapping. | |
673a394b EA |
1016 | */ |
1017 | int | |
1018 | i915_gem_set_domain_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 1019 | struct drm_file *file) |
673a394b EA |
1020 | { |
1021 | struct drm_i915_gem_set_domain *args = data; | |
05394f39 | 1022 | struct drm_i915_gem_object *obj; |
2ef7eeaa EA |
1023 | uint32_t read_domains = args->read_domains; |
1024 | uint32_t write_domain = args->write_domain; | |
673a394b EA |
1025 | int ret; |
1026 | ||
1027 | if (!(dev->driver->driver_features & DRIVER_GEM)) | |
1028 | return -ENODEV; | |
1029 | ||
2ef7eeaa | 1030 | /* Only handle setting domains to types used by the CPU. */ |
21d509e3 | 1031 | if (write_domain & I915_GEM_GPU_DOMAINS) |
2ef7eeaa EA |
1032 | return -EINVAL; |
1033 | ||
21d509e3 | 1034 | if (read_domains & I915_GEM_GPU_DOMAINS) |
2ef7eeaa EA |
1035 | return -EINVAL; |
1036 | ||
1037 | /* Having something in the write domain implies it's in the read | |
1038 | * domain, and only that read domain. Enforce that in the request. | |
1039 | */ | |
1040 | if (write_domain != 0 && read_domains != write_domain) | |
1041 | return -EINVAL; | |
1042 | ||
76c1dec1 | 1043 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 1044 | if (ret) |
76c1dec1 | 1045 | return ret; |
1d7cfea1 | 1046 | |
05394f39 | 1047 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
1d7cfea1 CW |
1048 | if (obj == NULL) { |
1049 | ret = -ENOENT; | |
1050 | goto unlock; | |
76c1dec1 | 1051 | } |
673a394b | 1052 | |
2ef7eeaa EA |
1053 | if (read_domains & I915_GEM_DOMAIN_GTT) { |
1054 | ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0); | |
02354392 EA |
1055 | |
1056 | /* Silently promote "you're not bound, there was nothing to do" | |
1057 | * to success, since the client was just asking us to | |
1058 | * make sure everything was done. | |
1059 | */ | |
1060 | if (ret == -EINVAL) | |
1061 | ret = 0; | |
2ef7eeaa | 1062 | } else { |
e47c68e9 | 1063 | ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0); |
2ef7eeaa EA |
1064 | } |
1065 | ||
05394f39 | 1066 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 1067 | unlock: |
673a394b EA |
1068 | mutex_unlock(&dev->struct_mutex); |
1069 | return ret; | |
1070 | } | |
1071 | ||
1072 | /** | |
1073 | * Called when user space has done writes to this buffer | |
1074 | */ | |
1075 | int | |
1076 | i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 1077 | struct drm_file *file) |
673a394b EA |
1078 | { |
1079 | struct drm_i915_gem_sw_finish *args = data; | |
05394f39 | 1080 | struct drm_i915_gem_object *obj; |
673a394b EA |
1081 | int ret = 0; |
1082 | ||
1083 | if (!(dev->driver->driver_features & DRIVER_GEM)) | |
1084 | return -ENODEV; | |
1085 | ||
76c1dec1 | 1086 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 1087 | if (ret) |
76c1dec1 | 1088 | return ret; |
1d7cfea1 | 1089 | |
05394f39 | 1090 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
673a394b | 1091 | if (obj == NULL) { |
1d7cfea1 CW |
1092 | ret = -ENOENT; |
1093 | goto unlock; | |
673a394b EA |
1094 | } |
1095 | ||
673a394b | 1096 | /* Pinned buffers may be scanout, so flush the cache */ |
05394f39 | 1097 | if (obj->pin_count) |
e47c68e9 EA |
1098 | i915_gem_object_flush_cpu_write_domain(obj); |
1099 | ||
05394f39 | 1100 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 1101 | unlock: |
673a394b EA |
1102 | mutex_unlock(&dev->struct_mutex); |
1103 | return ret; | |
1104 | } | |
1105 | ||
1106 | /** | |
1107 | * Maps the contents of an object, returning the address it is mapped | |
1108 | * into. | |
1109 | * | |
1110 | * While the mapping holds a reference on the contents of the object, it doesn't | |
1111 | * imply a ref on the object itself. | |
1112 | */ | |
1113 | int | |
1114 | i915_gem_mmap_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 1115 | struct drm_file *file) |
673a394b | 1116 | { |
da761a6e | 1117 | struct drm_i915_private *dev_priv = dev->dev_private; |
673a394b EA |
1118 | struct drm_i915_gem_mmap *args = data; |
1119 | struct drm_gem_object *obj; | |
673a394b EA |
1120 | unsigned long addr; |
1121 | ||
1122 | if (!(dev->driver->driver_features & DRIVER_GEM)) | |
1123 | return -ENODEV; | |
1124 | ||
05394f39 | 1125 | obj = drm_gem_object_lookup(dev, file, args->handle); |
673a394b | 1126 | if (obj == NULL) |
bf79cb91 | 1127 | return -ENOENT; |
673a394b | 1128 | |
da761a6e CW |
1129 | if (obj->size > dev_priv->mm.gtt_mappable_end) { |
1130 | drm_gem_object_unreference_unlocked(obj); | |
1131 | return -E2BIG; | |
1132 | } | |
1133 | ||
673a394b EA |
1134 | down_write(¤t->mm->mmap_sem); |
1135 | addr = do_mmap(obj->filp, 0, args->size, | |
1136 | PROT_READ | PROT_WRITE, MAP_SHARED, | |
1137 | args->offset); | |
1138 | up_write(¤t->mm->mmap_sem); | |
bc9025bd | 1139 | drm_gem_object_unreference_unlocked(obj); |
673a394b EA |
1140 | if (IS_ERR((void *)addr)) |
1141 | return addr; | |
1142 | ||
1143 | args->addr_ptr = (uint64_t) addr; | |
1144 | ||
1145 | return 0; | |
1146 | } | |
1147 | ||
de151cf6 JB |
1148 | /** |
1149 | * i915_gem_fault - fault a page into the GTT | |
1150 | * vma: VMA in question | |
1151 | * vmf: fault info | |
1152 | * | |
1153 | * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped | |
1154 | * from userspace. The fault handler takes care of binding the object to | |
1155 | * the GTT (if needed), allocating and programming a fence register (again, | |
1156 | * only if needed based on whether the old reg is still valid or the object | |
1157 | * is tiled) and inserting a new PTE into the faulting process. | |
1158 | * | |
1159 | * Note that the faulting process may involve evicting existing objects | |
1160 | * from the GTT and/or fence registers to make room. So performance may | |
1161 | * suffer if the GTT working set is large or there are few fence registers | |
1162 | * left. | |
1163 | */ | |
1164 | int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf) | |
1165 | { | |
05394f39 CW |
1166 | struct drm_i915_gem_object *obj = to_intel_bo(vma->vm_private_data); |
1167 | struct drm_device *dev = obj->base.dev; | |
7d1c4804 | 1168 | drm_i915_private_t *dev_priv = dev->dev_private; |
de151cf6 JB |
1169 | pgoff_t page_offset; |
1170 | unsigned long pfn; | |
1171 | int ret = 0; | |
0f973f27 | 1172 | bool write = !!(vmf->flags & FAULT_FLAG_WRITE); |
de151cf6 JB |
1173 | |
1174 | /* We don't use vmf->pgoff since that has the fake offset */ | |
1175 | page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >> | |
1176 | PAGE_SHIFT; | |
1177 | ||
d9bc7e9f CW |
1178 | ret = i915_mutex_lock_interruptible(dev); |
1179 | if (ret) | |
1180 | goto out; | |
a00b10c3 | 1181 | |
db53a302 CW |
1182 | trace_i915_gem_object_fault(obj, page_offset, true, write); |
1183 | ||
d9bc7e9f | 1184 | /* Now bind it into the GTT if needed */ |
919926ae CW |
1185 | if (!obj->map_and_fenceable) { |
1186 | ret = i915_gem_object_unbind(obj); | |
1187 | if (ret) | |
1188 | goto unlock; | |
a00b10c3 | 1189 | } |
05394f39 | 1190 | if (!obj->gtt_space) { |
75e9e915 | 1191 | ret = i915_gem_object_bind_to_gtt(obj, 0, true); |
c715089f CW |
1192 | if (ret) |
1193 | goto unlock; | |
de151cf6 JB |
1194 | } |
1195 | ||
4a684a41 CW |
1196 | ret = i915_gem_object_set_to_gtt_domain(obj, write); |
1197 | if (ret) | |
1198 | goto unlock; | |
1199 | ||
d9e86c0e CW |
1200 | if (obj->tiling_mode == I915_TILING_NONE) |
1201 | ret = i915_gem_object_put_fence(obj); | |
1202 | else | |
1203 | ret = i915_gem_object_get_fence(obj, NULL, true); | |
1204 | if (ret) | |
1205 | goto unlock; | |
de151cf6 | 1206 | |
05394f39 CW |
1207 | if (i915_gem_object_is_inactive(obj)) |
1208 | list_move_tail(&obj->mm_list, &dev_priv->mm.inactive_list); | |
7d1c4804 | 1209 | |
6299f992 CW |
1210 | obj->fault_mappable = true; |
1211 | ||
05394f39 | 1212 | pfn = ((dev->agp->base + obj->gtt_offset) >> PAGE_SHIFT) + |
de151cf6 JB |
1213 | page_offset; |
1214 | ||
1215 | /* Finally, remap it using the new GTT offset */ | |
1216 | ret = vm_insert_pfn(vma, (unsigned long)vmf->virtual_address, pfn); | |
c715089f | 1217 | unlock: |
de151cf6 | 1218 | mutex_unlock(&dev->struct_mutex); |
d9bc7e9f | 1219 | out: |
de151cf6 | 1220 | switch (ret) { |
d9bc7e9f | 1221 | case -EIO: |
045e769a | 1222 | case -EAGAIN: |
d9bc7e9f CW |
1223 | /* Give the error handler a chance to run and move the |
1224 | * objects off the GPU active list. Next time we service the | |
1225 | * fault, we should be able to transition the page into the | |
1226 | * GTT without touching the GPU (and so avoid further | |
1227 | * EIO/EGAIN). If the GPU is wedged, then there is no issue | |
1228 | * with coherency, just lost writes. | |
1229 | */ | |
045e769a | 1230 | set_need_resched(); |
c715089f CW |
1231 | case 0: |
1232 | case -ERESTARTSYS: | |
1233 | return VM_FAULT_NOPAGE; | |
de151cf6 | 1234 | case -ENOMEM: |
de151cf6 | 1235 | return VM_FAULT_OOM; |
de151cf6 | 1236 | default: |
c715089f | 1237 | return VM_FAULT_SIGBUS; |
de151cf6 JB |
1238 | } |
1239 | } | |
1240 | ||
1241 | /** | |
1242 | * i915_gem_create_mmap_offset - create a fake mmap offset for an object | |
1243 | * @obj: obj in question | |
1244 | * | |
1245 | * GEM memory mapping works by handing back to userspace a fake mmap offset | |
1246 | * it can use in a subsequent mmap(2) call. The DRM core code then looks | |
1247 | * up the object based on the offset and sets up the various memory mapping | |
1248 | * structures. | |
1249 | * | |
1250 | * This routine allocates and attaches a fake offset for @obj. | |
1251 | */ | |
1252 | static int | |
05394f39 | 1253 | i915_gem_create_mmap_offset(struct drm_i915_gem_object *obj) |
de151cf6 | 1254 | { |
05394f39 | 1255 | struct drm_device *dev = obj->base.dev; |
de151cf6 | 1256 | struct drm_gem_mm *mm = dev->mm_private; |
de151cf6 | 1257 | struct drm_map_list *list; |
f77d390c | 1258 | struct drm_local_map *map; |
de151cf6 JB |
1259 | int ret = 0; |
1260 | ||
1261 | /* Set the object up for mmap'ing */ | |
05394f39 | 1262 | list = &obj->base.map_list; |
9a298b2a | 1263 | list->map = kzalloc(sizeof(struct drm_map_list), GFP_KERNEL); |
de151cf6 JB |
1264 | if (!list->map) |
1265 | return -ENOMEM; | |
1266 | ||
1267 | map = list->map; | |
1268 | map->type = _DRM_GEM; | |
05394f39 | 1269 | map->size = obj->base.size; |
de151cf6 JB |
1270 | map->handle = obj; |
1271 | ||
1272 | /* Get a DRM GEM mmap offset allocated... */ | |
1273 | list->file_offset_node = drm_mm_search_free(&mm->offset_manager, | |
05394f39 CW |
1274 | obj->base.size / PAGE_SIZE, |
1275 | 0, 0); | |
de151cf6 | 1276 | if (!list->file_offset_node) { |
05394f39 CW |
1277 | DRM_ERROR("failed to allocate offset for bo %d\n", |
1278 | obj->base.name); | |
9e0ae534 | 1279 | ret = -ENOSPC; |
de151cf6 JB |
1280 | goto out_free_list; |
1281 | } | |
1282 | ||
1283 | list->file_offset_node = drm_mm_get_block(list->file_offset_node, | |
05394f39 CW |
1284 | obj->base.size / PAGE_SIZE, |
1285 | 0); | |
de151cf6 JB |
1286 | if (!list->file_offset_node) { |
1287 | ret = -ENOMEM; | |
1288 | goto out_free_list; | |
1289 | } | |
1290 | ||
1291 | list->hash.key = list->file_offset_node->start; | |
9e0ae534 CW |
1292 | ret = drm_ht_insert_item(&mm->offset_hash, &list->hash); |
1293 | if (ret) { | |
de151cf6 JB |
1294 | DRM_ERROR("failed to add to map hash\n"); |
1295 | goto out_free_mm; | |
1296 | } | |
1297 | ||
de151cf6 JB |
1298 | return 0; |
1299 | ||
1300 | out_free_mm: | |
1301 | drm_mm_put_block(list->file_offset_node); | |
1302 | out_free_list: | |
9a298b2a | 1303 | kfree(list->map); |
39a01d1f | 1304 | list->map = NULL; |
de151cf6 JB |
1305 | |
1306 | return ret; | |
1307 | } | |
1308 | ||
901782b2 CW |
1309 | /** |
1310 | * i915_gem_release_mmap - remove physical page mappings | |
1311 | * @obj: obj in question | |
1312 | * | |
af901ca1 | 1313 | * Preserve the reservation of the mmapping with the DRM core code, but |
901782b2 CW |
1314 | * relinquish ownership of the pages back to the system. |
1315 | * | |
1316 | * It is vital that we remove the page mapping if we have mapped a tiled | |
1317 | * object through the GTT and then lose the fence register due to | |
1318 | * resource pressure. Similarly if the object has been moved out of the | |
1319 | * aperture, than pages mapped into userspace must be revoked. Removing the | |
1320 | * mapping will then trigger a page fault on the next user access, allowing | |
1321 | * fixup by i915_gem_fault(). | |
1322 | */ | |
d05ca301 | 1323 | void |
05394f39 | 1324 | i915_gem_release_mmap(struct drm_i915_gem_object *obj) |
901782b2 | 1325 | { |
6299f992 CW |
1326 | if (!obj->fault_mappable) |
1327 | return; | |
901782b2 | 1328 | |
6299f992 CW |
1329 | unmap_mapping_range(obj->base.dev->dev_mapping, |
1330 | (loff_t)obj->base.map_list.hash.key<<PAGE_SHIFT, | |
1331 | obj->base.size, 1); | |
fb7d516a | 1332 | |
6299f992 | 1333 | obj->fault_mappable = false; |
901782b2 CW |
1334 | } |
1335 | ||
ab00b3e5 | 1336 | static void |
05394f39 | 1337 | i915_gem_free_mmap_offset(struct drm_i915_gem_object *obj) |
ab00b3e5 | 1338 | { |
05394f39 | 1339 | struct drm_device *dev = obj->base.dev; |
ab00b3e5 | 1340 | struct drm_gem_mm *mm = dev->mm_private; |
05394f39 | 1341 | struct drm_map_list *list = &obj->base.map_list; |
ab00b3e5 | 1342 | |
ab00b3e5 | 1343 | drm_ht_remove_item(&mm->offset_hash, &list->hash); |
39a01d1f CW |
1344 | drm_mm_put_block(list->file_offset_node); |
1345 | kfree(list->map); | |
1346 | list->map = NULL; | |
ab00b3e5 JB |
1347 | } |
1348 | ||
92b88aeb CW |
1349 | static uint32_t |
1350 | i915_gem_get_gtt_size(struct drm_i915_gem_object *obj) | |
1351 | { | |
1352 | struct drm_device *dev = obj->base.dev; | |
1353 | uint32_t size; | |
1354 | ||
1355 | if (INTEL_INFO(dev)->gen >= 4 || | |
1356 | obj->tiling_mode == I915_TILING_NONE) | |
1357 | return obj->base.size; | |
1358 | ||
1359 | /* Previous chips need a power-of-two fence region when tiling */ | |
1360 | if (INTEL_INFO(dev)->gen == 3) | |
1361 | size = 1024*1024; | |
1362 | else | |
1363 | size = 512*1024; | |
1364 | ||
1365 | while (size < obj->base.size) | |
1366 | size <<= 1; | |
1367 | ||
1368 | return size; | |
1369 | } | |
1370 | ||
de151cf6 JB |
1371 | /** |
1372 | * i915_gem_get_gtt_alignment - return required GTT alignment for an object | |
1373 | * @obj: object to check | |
1374 | * | |
1375 | * Return the required GTT alignment for an object, taking into account | |
5e783301 | 1376 | * potential fence register mapping. |
de151cf6 JB |
1377 | */ |
1378 | static uint32_t | |
05394f39 | 1379 | i915_gem_get_gtt_alignment(struct drm_i915_gem_object *obj) |
de151cf6 | 1380 | { |
05394f39 | 1381 | struct drm_device *dev = obj->base.dev; |
de151cf6 JB |
1382 | |
1383 | /* | |
1384 | * Minimum alignment is 4k (GTT page size), but might be greater | |
1385 | * if a fence register is needed for the object. | |
1386 | */ | |
a00b10c3 | 1387 | if (INTEL_INFO(dev)->gen >= 4 || |
05394f39 | 1388 | obj->tiling_mode == I915_TILING_NONE) |
de151cf6 JB |
1389 | return 4096; |
1390 | ||
a00b10c3 CW |
1391 | /* |
1392 | * Previous chips need to be aligned to the size of the smallest | |
1393 | * fence register that can contain the object. | |
1394 | */ | |
05394f39 | 1395 | return i915_gem_get_gtt_size(obj); |
a00b10c3 CW |
1396 | } |
1397 | ||
5e783301 DV |
1398 | /** |
1399 | * i915_gem_get_unfenced_gtt_alignment - return required GTT alignment for an | |
1400 | * unfenced object | |
1401 | * @obj: object to check | |
1402 | * | |
1403 | * Return the required GTT alignment for an object, only taking into account | |
1404 | * unfenced tiled surface requirements. | |
1405 | */ | |
1406 | static uint32_t | |
05394f39 | 1407 | i915_gem_get_unfenced_gtt_alignment(struct drm_i915_gem_object *obj) |
5e783301 | 1408 | { |
05394f39 | 1409 | struct drm_device *dev = obj->base.dev; |
5e783301 DV |
1410 | int tile_height; |
1411 | ||
1412 | /* | |
1413 | * Minimum alignment is 4k (GTT page size) for sane hw. | |
1414 | */ | |
1415 | if (INTEL_INFO(dev)->gen >= 4 || IS_G33(dev) || | |
05394f39 | 1416 | obj->tiling_mode == I915_TILING_NONE) |
5e783301 DV |
1417 | return 4096; |
1418 | ||
1419 | /* | |
1420 | * Older chips need unfenced tiled buffers to be aligned to the left | |
1421 | * edge of an even tile row (where tile rows are counted as if the bo is | |
1422 | * placed in a fenced gtt region). | |
1423 | */ | |
1424 | if (IS_GEN2(dev) || | |
05394f39 | 1425 | (obj->tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev))) |
5e783301 DV |
1426 | tile_height = 32; |
1427 | else | |
1428 | tile_height = 8; | |
1429 | ||
05394f39 | 1430 | return tile_height * obj->stride * 2; |
5e783301 DV |
1431 | } |
1432 | ||
de151cf6 JB |
1433 | /** |
1434 | * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing | |
1435 | * @dev: DRM device | |
1436 | * @data: GTT mapping ioctl data | |
05394f39 | 1437 | * @file: GEM object info |
de151cf6 JB |
1438 | * |
1439 | * Simply returns the fake offset to userspace so it can mmap it. | |
1440 | * The mmap call will end up in drm_gem_mmap(), which will set things | |
1441 | * up so we can get faults in the handler above. | |
1442 | * | |
1443 | * The fault handler will take care of binding the object into the GTT | |
1444 | * (since it may have been evicted to make room for something), allocating | |
1445 | * a fence register, and mapping the appropriate aperture address into | |
1446 | * userspace. | |
1447 | */ | |
1448 | int | |
1449 | i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 1450 | struct drm_file *file) |
de151cf6 | 1451 | { |
da761a6e | 1452 | struct drm_i915_private *dev_priv = dev->dev_private; |
de151cf6 | 1453 | struct drm_i915_gem_mmap_gtt *args = data; |
05394f39 | 1454 | struct drm_i915_gem_object *obj; |
de151cf6 JB |
1455 | int ret; |
1456 | ||
1457 | if (!(dev->driver->driver_features & DRIVER_GEM)) | |
1458 | return -ENODEV; | |
1459 | ||
76c1dec1 | 1460 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 1461 | if (ret) |
76c1dec1 | 1462 | return ret; |
de151cf6 | 1463 | |
05394f39 | 1464 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
1d7cfea1 CW |
1465 | if (obj == NULL) { |
1466 | ret = -ENOENT; | |
1467 | goto unlock; | |
1468 | } | |
de151cf6 | 1469 | |
05394f39 | 1470 | if (obj->base.size > dev_priv->mm.gtt_mappable_end) { |
da761a6e CW |
1471 | ret = -E2BIG; |
1472 | goto unlock; | |
1473 | } | |
1474 | ||
05394f39 | 1475 | if (obj->madv != I915_MADV_WILLNEED) { |
ab18282d | 1476 | DRM_ERROR("Attempting to mmap a purgeable buffer\n"); |
1d7cfea1 CW |
1477 | ret = -EINVAL; |
1478 | goto out; | |
ab18282d CW |
1479 | } |
1480 | ||
05394f39 | 1481 | if (!obj->base.map_list.map) { |
de151cf6 | 1482 | ret = i915_gem_create_mmap_offset(obj); |
1d7cfea1 CW |
1483 | if (ret) |
1484 | goto out; | |
de151cf6 JB |
1485 | } |
1486 | ||
05394f39 | 1487 | args->offset = (u64)obj->base.map_list.hash.key << PAGE_SHIFT; |
de151cf6 | 1488 | |
1d7cfea1 | 1489 | out: |
05394f39 | 1490 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 1491 | unlock: |
de151cf6 | 1492 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 1493 | return ret; |
de151cf6 JB |
1494 | } |
1495 | ||
e5281ccd | 1496 | static int |
05394f39 | 1497 | i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj, |
e5281ccd CW |
1498 | gfp_t gfpmask) |
1499 | { | |
e5281ccd CW |
1500 | int page_count, i; |
1501 | struct address_space *mapping; | |
1502 | struct inode *inode; | |
1503 | struct page *page; | |
1504 | ||
1505 | /* Get the list of pages out of our struct file. They'll be pinned | |
1506 | * at this point until we release them. | |
1507 | */ | |
05394f39 CW |
1508 | page_count = obj->base.size / PAGE_SIZE; |
1509 | BUG_ON(obj->pages != NULL); | |
1510 | obj->pages = drm_malloc_ab(page_count, sizeof(struct page *)); | |
1511 | if (obj->pages == NULL) | |
e5281ccd CW |
1512 | return -ENOMEM; |
1513 | ||
05394f39 | 1514 | inode = obj->base.filp->f_path.dentry->d_inode; |
e5281ccd CW |
1515 | mapping = inode->i_mapping; |
1516 | for (i = 0; i < page_count; i++) { | |
1517 | page = read_cache_page_gfp(mapping, i, | |
1518 | GFP_HIGHUSER | | |
1519 | __GFP_COLD | | |
1520 | __GFP_RECLAIMABLE | | |
1521 | gfpmask); | |
1522 | if (IS_ERR(page)) | |
1523 | goto err_pages; | |
1524 | ||
05394f39 | 1525 | obj->pages[i] = page; |
e5281ccd CW |
1526 | } |
1527 | ||
05394f39 | 1528 | if (obj->tiling_mode != I915_TILING_NONE) |
e5281ccd CW |
1529 | i915_gem_object_do_bit_17_swizzle(obj); |
1530 | ||
1531 | return 0; | |
1532 | ||
1533 | err_pages: | |
1534 | while (i--) | |
05394f39 | 1535 | page_cache_release(obj->pages[i]); |
e5281ccd | 1536 | |
05394f39 CW |
1537 | drm_free_large(obj->pages); |
1538 | obj->pages = NULL; | |
e5281ccd CW |
1539 | return PTR_ERR(page); |
1540 | } | |
1541 | ||
5cdf5881 | 1542 | static void |
05394f39 | 1543 | i915_gem_object_put_pages_gtt(struct drm_i915_gem_object *obj) |
673a394b | 1544 | { |
05394f39 | 1545 | int page_count = obj->base.size / PAGE_SIZE; |
673a394b EA |
1546 | int i; |
1547 | ||
05394f39 | 1548 | BUG_ON(obj->madv == __I915_MADV_PURGED); |
673a394b | 1549 | |
05394f39 | 1550 | if (obj->tiling_mode != I915_TILING_NONE) |
280b713b EA |
1551 | i915_gem_object_save_bit_17_swizzle(obj); |
1552 | ||
05394f39 CW |
1553 | if (obj->madv == I915_MADV_DONTNEED) |
1554 | obj->dirty = 0; | |
3ef94daa CW |
1555 | |
1556 | for (i = 0; i < page_count; i++) { | |
05394f39 CW |
1557 | if (obj->dirty) |
1558 | set_page_dirty(obj->pages[i]); | |
3ef94daa | 1559 | |
05394f39 CW |
1560 | if (obj->madv == I915_MADV_WILLNEED) |
1561 | mark_page_accessed(obj->pages[i]); | |
3ef94daa | 1562 | |
05394f39 | 1563 | page_cache_release(obj->pages[i]); |
3ef94daa | 1564 | } |
05394f39 | 1565 | obj->dirty = 0; |
673a394b | 1566 | |
05394f39 CW |
1567 | drm_free_large(obj->pages); |
1568 | obj->pages = NULL; | |
673a394b EA |
1569 | } |
1570 | ||
54cf91dc | 1571 | void |
05394f39 | 1572 | i915_gem_object_move_to_active(struct drm_i915_gem_object *obj, |
1ec14ad3 CW |
1573 | struct intel_ring_buffer *ring, |
1574 | u32 seqno) | |
673a394b | 1575 | { |
05394f39 | 1576 | struct drm_device *dev = obj->base.dev; |
69dc4987 | 1577 | struct drm_i915_private *dev_priv = dev->dev_private; |
617dbe27 | 1578 | |
852835f3 | 1579 | BUG_ON(ring == NULL); |
05394f39 | 1580 | obj->ring = ring; |
673a394b EA |
1581 | |
1582 | /* Add a reference if we're newly entering the active list. */ | |
05394f39 CW |
1583 | if (!obj->active) { |
1584 | drm_gem_object_reference(&obj->base); | |
1585 | obj->active = 1; | |
673a394b | 1586 | } |
e35a41de | 1587 | |
673a394b | 1588 | /* Move from whatever list we were on to the tail of execution. */ |
05394f39 CW |
1589 | list_move_tail(&obj->mm_list, &dev_priv->mm.active_list); |
1590 | list_move_tail(&obj->ring_list, &ring->active_list); | |
caea7476 | 1591 | |
05394f39 | 1592 | obj->last_rendering_seqno = seqno; |
caea7476 CW |
1593 | if (obj->fenced_gpu_access) { |
1594 | struct drm_i915_fence_reg *reg; | |
1595 | ||
1596 | BUG_ON(obj->fence_reg == I915_FENCE_REG_NONE); | |
1597 | ||
1598 | obj->last_fenced_seqno = seqno; | |
1599 | obj->last_fenced_ring = ring; | |
1600 | ||
1601 | reg = &dev_priv->fence_regs[obj->fence_reg]; | |
1602 | list_move_tail(®->lru_list, &dev_priv->mm.fence_list); | |
1603 | } | |
1604 | } | |
1605 | ||
1606 | static void | |
1607 | i915_gem_object_move_off_active(struct drm_i915_gem_object *obj) | |
1608 | { | |
1609 | list_del_init(&obj->ring_list); | |
1610 | obj->last_rendering_seqno = 0; | |
673a394b EA |
1611 | } |
1612 | ||
ce44b0ea | 1613 | static void |
05394f39 | 1614 | i915_gem_object_move_to_flushing(struct drm_i915_gem_object *obj) |
ce44b0ea | 1615 | { |
05394f39 | 1616 | struct drm_device *dev = obj->base.dev; |
ce44b0ea | 1617 | drm_i915_private_t *dev_priv = dev->dev_private; |
ce44b0ea | 1618 | |
05394f39 CW |
1619 | BUG_ON(!obj->active); |
1620 | list_move_tail(&obj->mm_list, &dev_priv->mm.flushing_list); | |
caea7476 CW |
1621 | |
1622 | i915_gem_object_move_off_active(obj); | |
1623 | } | |
1624 | ||
1625 | static void | |
1626 | i915_gem_object_move_to_inactive(struct drm_i915_gem_object *obj) | |
1627 | { | |
1628 | struct drm_device *dev = obj->base.dev; | |
1629 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1630 | ||
1631 | if (obj->pin_count != 0) | |
1632 | list_move_tail(&obj->mm_list, &dev_priv->mm.pinned_list); | |
1633 | else | |
1634 | list_move_tail(&obj->mm_list, &dev_priv->mm.inactive_list); | |
1635 | ||
1636 | BUG_ON(!list_empty(&obj->gpu_write_list)); | |
1637 | BUG_ON(!obj->active); | |
1638 | obj->ring = NULL; | |
1639 | ||
1640 | i915_gem_object_move_off_active(obj); | |
1641 | obj->fenced_gpu_access = false; | |
caea7476 CW |
1642 | |
1643 | obj->active = 0; | |
87ca9c8a | 1644 | obj->pending_gpu_write = false; |
caea7476 CW |
1645 | drm_gem_object_unreference(&obj->base); |
1646 | ||
1647 | WARN_ON(i915_verify_lists(dev)); | |
ce44b0ea | 1648 | } |
673a394b | 1649 | |
963b4836 CW |
1650 | /* Immediately discard the backing storage */ |
1651 | static void | |
05394f39 | 1652 | i915_gem_object_truncate(struct drm_i915_gem_object *obj) |
963b4836 | 1653 | { |
bb6baf76 | 1654 | struct inode *inode; |
963b4836 | 1655 | |
ae9fed6b CW |
1656 | /* Our goal here is to return as much of the memory as |
1657 | * is possible back to the system as we are called from OOM. | |
1658 | * To do this we must instruct the shmfs to drop all of its | |
1659 | * backing pages, *now*. Here we mirror the actions taken | |
1660 | * when by shmem_delete_inode() to release the backing store. | |
1661 | */ | |
05394f39 | 1662 | inode = obj->base.filp->f_path.dentry->d_inode; |
ae9fed6b CW |
1663 | truncate_inode_pages(inode->i_mapping, 0); |
1664 | if (inode->i_op->truncate_range) | |
1665 | inode->i_op->truncate_range(inode, 0, (loff_t)-1); | |
bb6baf76 | 1666 | |
05394f39 | 1667 | obj->madv = __I915_MADV_PURGED; |
963b4836 CW |
1668 | } |
1669 | ||
1670 | static inline int | |
05394f39 | 1671 | i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj) |
963b4836 | 1672 | { |
05394f39 | 1673 | return obj->madv == I915_MADV_DONTNEED; |
963b4836 CW |
1674 | } |
1675 | ||
63560396 | 1676 | static void |
db53a302 CW |
1677 | i915_gem_process_flushing_list(struct intel_ring_buffer *ring, |
1678 | uint32_t flush_domains) | |
63560396 | 1679 | { |
05394f39 | 1680 | struct drm_i915_gem_object *obj, *next; |
63560396 | 1681 | |
05394f39 | 1682 | list_for_each_entry_safe(obj, next, |
64193406 | 1683 | &ring->gpu_write_list, |
63560396 | 1684 | gpu_write_list) { |
05394f39 CW |
1685 | if (obj->base.write_domain & flush_domains) { |
1686 | uint32_t old_write_domain = obj->base.write_domain; | |
63560396 | 1687 | |
05394f39 CW |
1688 | obj->base.write_domain = 0; |
1689 | list_del_init(&obj->gpu_write_list); | |
1ec14ad3 | 1690 | i915_gem_object_move_to_active(obj, ring, |
db53a302 | 1691 | i915_gem_next_request_seqno(ring)); |
63560396 | 1692 | |
63560396 | 1693 | trace_i915_gem_object_change_domain(obj, |
05394f39 | 1694 | obj->base.read_domains, |
63560396 DV |
1695 | old_write_domain); |
1696 | } | |
1697 | } | |
1698 | } | |
8187a2b7 | 1699 | |
3cce469c | 1700 | int |
db53a302 | 1701 | i915_add_request(struct intel_ring_buffer *ring, |
f787a5f5 | 1702 | struct drm_file *file, |
db53a302 | 1703 | struct drm_i915_gem_request *request) |
673a394b | 1704 | { |
db53a302 | 1705 | drm_i915_private_t *dev_priv = ring->dev->dev_private; |
673a394b EA |
1706 | uint32_t seqno; |
1707 | int was_empty; | |
3cce469c CW |
1708 | int ret; |
1709 | ||
1710 | BUG_ON(request == NULL); | |
673a394b | 1711 | |
3cce469c CW |
1712 | ret = ring->add_request(ring, &seqno); |
1713 | if (ret) | |
1714 | return ret; | |
673a394b | 1715 | |
db53a302 | 1716 | trace_i915_gem_request_add(ring, seqno); |
673a394b EA |
1717 | |
1718 | request->seqno = seqno; | |
852835f3 | 1719 | request->ring = ring; |
673a394b | 1720 | request->emitted_jiffies = jiffies; |
852835f3 ZN |
1721 | was_empty = list_empty(&ring->request_list); |
1722 | list_add_tail(&request->list, &ring->request_list); | |
1723 | ||
db53a302 CW |
1724 | if (file) { |
1725 | struct drm_i915_file_private *file_priv = file->driver_priv; | |
1726 | ||
1c25595f | 1727 | spin_lock(&file_priv->mm.lock); |
f787a5f5 | 1728 | request->file_priv = file_priv; |
b962442e | 1729 | list_add_tail(&request->client_list, |
f787a5f5 | 1730 | &file_priv->mm.request_list); |
1c25595f | 1731 | spin_unlock(&file_priv->mm.lock); |
b962442e | 1732 | } |
673a394b | 1733 | |
db53a302 CW |
1734 | ring->outstanding_lazy_request = false; |
1735 | ||
f65d9421 | 1736 | if (!dev_priv->mm.suspended) { |
b3b079db CW |
1737 | mod_timer(&dev_priv->hangcheck_timer, |
1738 | jiffies + msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)); | |
f65d9421 | 1739 | if (was_empty) |
b3b079db CW |
1740 | queue_delayed_work(dev_priv->wq, |
1741 | &dev_priv->mm.retire_work, HZ); | |
f65d9421 | 1742 | } |
3cce469c | 1743 | return 0; |
673a394b EA |
1744 | } |
1745 | ||
f787a5f5 CW |
1746 | static inline void |
1747 | i915_gem_request_remove_from_client(struct drm_i915_gem_request *request) | |
673a394b | 1748 | { |
1c25595f | 1749 | struct drm_i915_file_private *file_priv = request->file_priv; |
673a394b | 1750 | |
1c25595f CW |
1751 | if (!file_priv) |
1752 | return; | |
1c5d22f7 | 1753 | |
1c25595f CW |
1754 | spin_lock(&file_priv->mm.lock); |
1755 | list_del(&request->client_list); | |
1756 | request->file_priv = NULL; | |
1757 | spin_unlock(&file_priv->mm.lock); | |
673a394b | 1758 | } |
673a394b | 1759 | |
dfaae392 CW |
1760 | static void i915_gem_reset_ring_lists(struct drm_i915_private *dev_priv, |
1761 | struct intel_ring_buffer *ring) | |
9375e446 | 1762 | { |
dfaae392 CW |
1763 | while (!list_empty(&ring->request_list)) { |
1764 | struct drm_i915_gem_request *request; | |
673a394b | 1765 | |
dfaae392 CW |
1766 | request = list_first_entry(&ring->request_list, |
1767 | struct drm_i915_gem_request, | |
1768 | list); | |
de151cf6 | 1769 | |
dfaae392 | 1770 | list_del(&request->list); |
f787a5f5 | 1771 | i915_gem_request_remove_from_client(request); |
dfaae392 CW |
1772 | kfree(request); |
1773 | } | |
673a394b | 1774 | |
dfaae392 | 1775 | while (!list_empty(&ring->active_list)) { |
05394f39 | 1776 | struct drm_i915_gem_object *obj; |
9375e446 | 1777 | |
05394f39 CW |
1778 | obj = list_first_entry(&ring->active_list, |
1779 | struct drm_i915_gem_object, | |
1780 | ring_list); | |
9375e446 | 1781 | |
05394f39 CW |
1782 | obj->base.write_domain = 0; |
1783 | list_del_init(&obj->gpu_write_list); | |
1784 | i915_gem_object_move_to_inactive(obj); | |
673a394b EA |
1785 | } |
1786 | } | |
1787 | ||
312817a3 CW |
1788 | static void i915_gem_reset_fences(struct drm_device *dev) |
1789 | { | |
1790 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1791 | int i; | |
1792 | ||
1793 | for (i = 0; i < 16; i++) { | |
1794 | struct drm_i915_fence_reg *reg = &dev_priv->fence_regs[i]; | |
7d2cb39c CW |
1795 | struct drm_i915_gem_object *obj = reg->obj; |
1796 | ||
1797 | if (!obj) | |
1798 | continue; | |
1799 | ||
1800 | if (obj->tiling_mode) | |
1801 | i915_gem_release_mmap(obj); | |
1802 | ||
d9e86c0e CW |
1803 | reg->obj->fence_reg = I915_FENCE_REG_NONE; |
1804 | reg->obj->fenced_gpu_access = false; | |
1805 | reg->obj->last_fenced_seqno = 0; | |
1806 | reg->obj->last_fenced_ring = NULL; | |
1807 | i915_gem_clear_fence_reg(dev, reg); | |
312817a3 CW |
1808 | } |
1809 | } | |
1810 | ||
069efc1d | 1811 | void i915_gem_reset(struct drm_device *dev) |
673a394b | 1812 | { |
77f01230 | 1813 | struct drm_i915_private *dev_priv = dev->dev_private; |
05394f39 | 1814 | struct drm_i915_gem_object *obj; |
1ec14ad3 | 1815 | int i; |
673a394b | 1816 | |
1ec14ad3 CW |
1817 | for (i = 0; i < I915_NUM_RINGS; i++) |
1818 | i915_gem_reset_ring_lists(dev_priv, &dev_priv->ring[i]); | |
dfaae392 CW |
1819 | |
1820 | /* Remove anything from the flushing lists. The GPU cache is likely | |
1821 | * to be lost on reset along with the data, so simply move the | |
1822 | * lost bo to the inactive list. | |
1823 | */ | |
1824 | while (!list_empty(&dev_priv->mm.flushing_list)) { | |
05394f39 CW |
1825 | obj= list_first_entry(&dev_priv->mm.flushing_list, |
1826 | struct drm_i915_gem_object, | |
1827 | mm_list); | |
dfaae392 | 1828 | |
05394f39 CW |
1829 | obj->base.write_domain = 0; |
1830 | list_del_init(&obj->gpu_write_list); | |
1831 | i915_gem_object_move_to_inactive(obj); | |
dfaae392 CW |
1832 | } |
1833 | ||
1834 | /* Move everything out of the GPU domains to ensure we do any | |
1835 | * necessary invalidation upon reuse. | |
1836 | */ | |
05394f39 | 1837 | list_for_each_entry(obj, |
77f01230 | 1838 | &dev_priv->mm.inactive_list, |
69dc4987 | 1839 | mm_list) |
77f01230 | 1840 | { |
05394f39 | 1841 | obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS; |
77f01230 | 1842 | } |
069efc1d CW |
1843 | |
1844 | /* The fence registers are invalidated so clear them out */ | |
312817a3 | 1845 | i915_gem_reset_fences(dev); |
673a394b EA |
1846 | } |
1847 | ||
1848 | /** | |
1849 | * This function clears the request list as sequence numbers are passed. | |
1850 | */ | |
b09a1fec | 1851 | static void |
db53a302 | 1852 | i915_gem_retire_requests_ring(struct intel_ring_buffer *ring) |
673a394b | 1853 | { |
673a394b | 1854 | uint32_t seqno; |
1ec14ad3 | 1855 | int i; |
673a394b | 1856 | |
db53a302 | 1857 | if (list_empty(&ring->request_list)) |
6c0594a3 KW |
1858 | return; |
1859 | ||
db53a302 | 1860 | WARN_ON(i915_verify_lists(ring->dev)); |
673a394b | 1861 | |
78501eac | 1862 | seqno = ring->get_seqno(ring); |
1ec14ad3 | 1863 | |
076e2c0e | 1864 | for (i = 0; i < ARRAY_SIZE(ring->sync_seqno); i++) |
1ec14ad3 CW |
1865 | if (seqno >= ring->sync_seqno[i]) |
1866 | ring->sync_seqno[i] = 0; | |
1867 | ||
852835f3 | 1868 | while (!list_empty(&ring->request_list)) { |
673a394b | 1869 | struct drm_i915_gem_request *request; |
673a394b | 1870 | |
852835f3 | 1871 | request = list_first_entry(&ring->request_list, |
673a394b EA |
1872 | struct drm_i915_gem_request, |
1873 | list); | |
673a394b | 1874 | |
dfaae392 | 1875 | if (!i915_seqno_passed(seqno, request->seqno)) |
b84d5f0c CW |
1876 | break; |
1877 | ||
db53a302 | 1878 | trace_i915_gem_request_retire(ring, request->seqno); |
b84d5f0c CW |
1879 | |
1880 | list_del(&request->list); | |
f787a5f5 | 1881 | i915_gem_request_remove_from_client(request); |
b84d5f0c CW |
1882 | kfree(request); |
1883 | } | |
673a394b | 1884 | |
b84d5f0c CW |
1885 | /* Move any buffers on the active list that are no longer referenced |
1886 | * by the ringbuffer to the flushing/inactive lists as appropriate. | |
1887 | */ | |
1888 | while (!list_empty(&ring->active_list)) { | |
05394f39 | 1889 | struct drm_i915_gem_object *obj; |
b84d5f0c | 1890 | |
05394f39 CW |
1891 | obj= list_first_entry(&ring->active_list, |
1892 | struct drm_i915_gem_object, | |
1893 | ring_list); | |
673a394b | 1894 | |
05394f39 | 1895 | if (!i915_seqno_passed(seqno, obj->last_rendering_seqno)) |
673a394b | 1896 | break; |
b84d5f0c | 1897 | |
05394f39 | 1898 | if (obj->base.write_domain != 0) |
b84d5f0c CW |
1899 | i915_gem_object_move_to_flushing(obj); |
1900 | else | |
1901 | i915_gem_object_move_to_inactive(obj); | |
673a394b | 1902 | } |
9d34e5db | 1903 | |
db53a302 CW |
1904 | if (unlikely(ring->trace_irq_seqno && |
1905 | i915_seqno_passed(seqno, ring->trace_irq_seqno))) { | |
1ec14ad3 | 1906 | ring->irq_put(ring); |
db53a302 | 1907 | ring->trace_irq_seqno = 0; |
9d34e5db | 1908 | } |
23bc5982 | 1909 | |
db53a302 | 1910 | WARN_ON(i915_verify_lists(ring->dev)); |
673a394b EA |
1911 | } |
1912 | ||
b09a1fec CW |
1913 | void |
1914 | i915_gem_retire_requests(struct drm_device *dev) | |
1915 | { | |
1916 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1ec14ad3 | 1917 | int i; |
b09a1fec | 1918 | |
be72615b | 1919 | if (!list_empty(&dev_priv->mm.deferred_free_list)) { |
05394f39 | 1920 | struct drm_i915_gem_object *obj, *next; |
be72615b CW |
1921 | |
1922 | /* We must be careful that during unbind() we do not | |
1923 | * accidentally infinitely recurse into retire requests. | |
1924 | * Currently: | |
1925 | * retire -> free -> unbind -> wait -> retire_ring | |
1926 | */ | |
05394f39 | 1927 | list_for_each_entry_safe(obj, next, |
be72615b | 1928 | &dev_priv->mm.deferred_free_list, |
69dc4987 | 1929 | mm_list) |
05394f39 | 1930 | i915_gem_free_object_tail(obj); |
be72615b CW |
1931 | } |
1932 | ||
1ec14ad3 | 1933 | for (i = 0; i < I915_NUM_RINGS; i++) |
db53a302 | 1934 | i915_gem_retire_requests_ring(&dev_priv->ring[i]); |
b09a1fec CW |
1935 | } |
1936 | ||
75ef9da2 | 1937 | static void |
673a394b EA |
1938 | i915_gem_retire_work_handler(struct work_struct *work) |
1939 | { | |
1940 | drm_i915_private_t *dev_priv; | |
1941 | struct drm_device *dev; | |
0a58705b CW |
1942 | bool idle; |
1943 | int i; | |
673a394b EA |
1944 | |
1945 | dev_priv = container_of(work, drm_i915_private_t, | |
1946 | mm.retire_work.work); | |
1947 | dev = dev_priv->dev; | |
1948 | ||
891b48cf CW |
1949 | /* Come back later if the device is busy... */ |
1950 | if (!mutex_trylock(&dev->struct_mutex)) { | |
1951 | queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ); | |
1952 | return; | |
1953 | } | |
1954 | ||
b09a1fec | 1955 | i915_gem_retire_requests(dev); |
d1b851fc | 1956 | |
0a58705b CW |
1957 | /* Send a periodic flush down the ring so we don't hold onto GEM |
1958 | * objects indefinitely. | |
1959 | */ | |
1960 | idle = true; | |
1961 | for (i = 0; i < I915_NUM_RINGS; i++) { | |
1962 | struct intel_ring_buffer *ring = &dev_priv->ring[i]; | |
1963 | ||
1964 | if (!list_empty(&ring->gpu_write_list)) { | |
1965 | struct drm_i915_gem_request *request; | |
1966 | int ret; | |
1967 | ||
db53a302 CW |
1968 | ret = i915_gem_flush_ring(ring, |
1969 | 0, I915_GEM_GPU_DOMAINS); | |
0a58705b CW |
1970 | request = kzalloc(sizeof(*request), GFP_KERNEL); |
1971 | if (ret || request == NULL || | |
db53a302 | 1972 | i915_add_request(ring, NULL, request)) |
0a58705b CW |
1973 | kfree(request); |
1974 | } | |
1975 | ||
1976 | idle &= list_empty(&ring->request_list); | |
1977 | } | |
1978 | ||
1979 | if (!dev_priv->mm.suspended && !idle) | |
9c9fe1f8 | 1980 | queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ); |
0a58705b | 1981 | |
673a394b EA |
1982 | mutex_unlock(&dev->struct_mutex); |
1983 | } | |
1984 | ||
db53a302 CW |
1985 | /** |
1986 | * Waits for a sequence number to be signaled, and cleans up the | |
1987 | * request and object lists appropriately for that event. | |
1988 | */ | |
5a5a0c64 | 1989 | int |
db53a302 CW |
1990 | i915_wait_request(struct intel_ring_buffer *ring, |
1991 | uint32_t seqno, | |
1992 | bool interruptible) | |
673a394b | 1993 | { |
db53a302 | 1994 | drm_i915_private_t *dev_priv = ring->dev->dev_private; |
802c7eb6 | 1995 | u32 ier; |
673a394b EA |
1996 | int ret = 0; |
1997 | ||
1998 | BUG_ON(seqno == 0); | |
1999 | ||
d9bc7e9f CW |
2000 | if (atomic_read(&dev_priv->mm.wedged)) { |
2001 | struct completion *x = &dev_priv->error_completion; | |
2002 | bool recovery_complete; | |
2003 | unsigned long flags; | |
2004 | ||
2005 | /* Give the error handler a chance to run. */ | |
2006 | spin_lock_irqsave(&x->wait.lock, flags); | |
2007 | recovery_complete = x->done > 0; | |
2008 | spin_unlock_irqrestore(&x->wait.lock, flags); | |
2009 | ||
2010 | return recovery_complete ? -EIO : -EAGAIN; | |
2011 | } | |
30dbf0c0 | 2012 | |
5d97eb69 | 2013 | if (seqno == ring->outstanding_lazy_request) { |
3cce469c CW |
2014 | struct drm_i915_gem_request *request; |
2015 | ||
2016 | request = kzalloc(sizeof(*request), GFP_KERNEL); | |
2017 | if (request == NULL) | |
e35a41de | 2018 | return -ENOMEM; |
3cce469c | 2019 | |
db53a302 | 2020 | ret = i915_add_request(ring, NULL, request); |
3cce469c CW |
2021 | if (ret) { |
2022 | kfree(request); | |
2023 | return ret; | |
2024 | } | |
2025 | ||
2026 | seqno = request->seqno; | |
e35a41de | 2027 | } |
ffed1d09 | 2028 | |
78501eac | 2029 | if (!i915_seqno_passed(ring->get_seqno(ring), seqno)) { |
db53a302 | 2030 | if (HAS_PCH_SPLIT(ring->dev)) |
036a4a7d ZW |
2031 | ier = I915_READ(DEIER) | I915_READ(GTIER); |
2032 | else | |
2033 | ier = I915_READ(IER); | |
802c7eb6 JB |
2034 | if (!ier) { |
2035 | DRM_ERROR("something (likely vbetool) disabled " | |
2036 | "interrupts, re-enabling\n"); | |
db53a302 CW |
2037 | i915_driver_irq_preinstall(ring->dev); |
2038 | i915_driver_irq_postinstall(ring->dev); | |
802c7eb6 JB |
2039 | } |
2040 | ||
db53a302 | 2041 | trace_i915_gem_request_wait_begin(ring, seqno); |
1c5d22f7 | 2042 | |
b2223497 | 2043 | ring->waiting_seqno = seqno; |
b13c2b96 CW |
2044 | if (ring->irq_get(ring)) { |
2045 | if (interruptible) | |
2046 | ret = wait_event_interruptible(ring->irq_queue, | |
2047 | i915_seqno_passed(ring->get_seqno(ring), seqno) | |
2048 | || atomic_read(&dev_priv->mm.wedged)); | |
2049 | else | |
2050 | wait_event(ring->irq_queue, | |
2051 | i915_seqno_passed(ring->get_seqno(ring), seqno) | |
2052 | || atomic_read(&dev_priv->mm.wedged)); | |
2053 | ||
2054 | ring->irq_put(ring); | |
b5ba177d CW |
2055 | } else if (wait_for(i915_seqno_passed(ring->get_seqno(ring), |
2056 | seqno) || | |
2057 | atomic_read(&dev_priv->mm.wedged), 3000)) | |
2058 | ret = -EBUSY; | |
b2223497 | 2059 | ring->waiting_seqno = 0; |
1c5d22f7 | 2060 | |
db53a302 | 2061 | trace_i915_gem_request_wait_end(ring, seqno); |
673a394b | 2062 | } |
ba1234d1 | 2063 | if (atomic_read(&dev_priv->mm.wedged)) |
30dbf0c0 | 2064 | ret = -EAGAIN; |
673a394b EA |
2065 | |
2066 | if (ret && ret != -ERESTARTSYS) | |
8bff917c | 2067 | DRM_ERROR("%s returns %d (awaiting %d at %d, next %d)\n", |
78501eac | 2068 | __func__, ret, seqno, ring->get_seqno(ring), |
8bff917c | 2069 | dev_priv->next_seqno); |
673a394b EA |
2070 | |
2071 | /* Directly dispatch request retiring. While we have the work queue | |
2072 | * to handle this, the waiter on a request often wants an associated | |
2073 | * buffer to have made it to the inactive list, and we would need | |
2074 | * a separate wait queue to handle that. | |
2075 | */ | |
2076 | if (ret == 0) | |
db53a302 | 2077 | i915_gem_retire_requests_ring(ring); |
673a394b EA |
2078 | |
2079 | return ret; | |
2080 | } | |
2081 | ||
673a394b EA |
2082 | /** |
2083 | * Ensures that all rendering to the object has completed and the object is | |
2084 | * safe to unbind from the GTT or access from the CPU. | |
2085 | */ | |
54cf91dc | 2086 | int |
05394f39 | 2087 | i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj, |
2cf34d7b | 2088 | bool interruptible) |
673a394b | 2089 | { |
673a394b EA |
2090 | int ret; |
2091 | ||
e47c68e9 EA |
2092 | /* This function only exists to support waiting for existing rendering, |
2093 | * not for emitting required flushes. | |
673a394b | 2094 | */ |
05394f39 | 2095 | BUG_ON((obj->base.write_domain & I915_GEM_GPU_DOMAINS) != 0); |
673a394b EA |
2096 | |
2097 | /* If there is rendering queued on the buffer being evicted, wait for | |
2098 | * it. | |
2099 | */ | |
05394f39 | 2100 | if (obj->active) { |
db53a302 CW |
2101 | ret = i915_wait_request(obj->ring, |
2102 | obj->last_rendering_seqno, | |
2103 | interruptible); | |
2cf34d7b | 2104 | if (ret) |
673a394b EA |
2105 | return ret; |
2106 | } | |
2107 | ||
2108 | return 0; | |
2109 | } | |
2110 | ||
2111 | /** | |
2112 | * Unbinds an object from the GTT aperture. | |
2113 | */ | |
0f973f27 | 2114 | int |
05394f39 | 2115 | i915_gem_object_unbind(struct drm_i915_gem_object *obj) |
673a394b | 2116 | { |
673a394b EA |
2117 | int ret = 0; |
2118 | ||
05394f39 | 2119 | if (obj->gtt_space == NULL) |
673a394b EA |
2120 | return 0; |
2121 | ||
05394f39 | 2122 | if (obj->pin_count != 0) { |
673a394b EA |
2123 | DRM_ERROR("Attempting to unbind pinned buffer\n"); |
2124 | return -EINVAL; | |
2125 | } | |
2126 | ||
5323fd04 EA |
2127 | /* blow away mappings if mapped through GTT */ |
2128 | i915_gem_release_mmap(obj); | |
2129 | ||
673a394b EA |
2130 | /* Move the object to the CPU domain to ensure that |
2131 | * any possible CPU writes while it's not in the GTT | |
2132 | * are flushed when we go to remap it. This will | |
2133 | * also ensure that all pending GPU writes are finished | |
2134 | * before we unbind. | |
2135 | */ | |
e47c68e9 | 2136 | ret = i915_gem_object_set_to_cpu_domain(obj, 1); |
8dc1775d | 2137 | if (ret == -ERESTARTSYS) |
673a394b | 2138 | return ret; |
8dc1775d CW |
2139 | /* Continue on if we fail due to EIO, the GPU is hung so we |
2140 | * should be safe and we need to cleanup or else we might | |
2141 | * cause memory corruption through use-after-free. | |
2142 | */ | |
812ed492 CW |
2143 | if (ret) { |
2144 | i915_gem_clflush_object(obj); | |
05394f39 | 2145 | obj->base.read_domains = obj->base.write_domain = I915_GEM_DOMAIN_CPU; |
812ed492 | 2146 | } |
673a394b | 2147 | |
96b47b65 | 2148 | /* release the fence reg _after_ flushing */ |
d9e86c0e CW |
2149 | ret = i915_gem_object_put_fence(obj); |
2150 | if (ret == -ERESTARTSYS) | |
2151 | return ret; | |
96b47b65 | 2152 | |
db53a302 CW |
2153 | trace_i915_gem_object_unbind(obj); |
2154 | ||
7c2e6fdf | 2155 | i915_gem_gtt_unbind_object(obj); |
e5281ccd | 2156 | i915_gem_object_put_pages_gtt(obj); |
673a394b | 2157 | |
6299f992 | 2158 | list_del_init(&obj->gtt_list); |
05394f39 | 2159 | list_del_init(&obj->mm_list); |
75e9e915 | 2160 | /* Avoid an unnecessary call to unbind on rebind. */ |
05394f39 | 2161 | obj->map_and_fenceable = true; |
673a394b | 2162 | |
05394f39 CW |
2163 | drm_mm_put_block(obj->gtt_space); |
2164 | obj->gtt_space = NULL; | |
2165 | obj->gtt_offset = 0; | |
673a394b | 2166 | |
05394f39 | 2167 | if (i915_gem_object_is_purgeable(obj)) |
963b4836 CW |
2168 | i915_gem_object_truncate(obj); |
2169 | ||
8dc1775d | 2170 | return ret; |
673a394b EA |
2171 | } |
2172 | ||
88241785 | 2173 | int |
db53a302 | 2174 | i915_gem_flush_ring(struct intel_ring_buffer *ring, |
54cf91dc CW |
2175 | uint32_t invalidate_domains, |
2176 | uint32_t flush_domains) | |
2177 | { | |
88241785 CW |
2178 | int ret; |
2179 | ||
db53a302 CW |
2180 | trace_i915_gem_ring_flush(ring, invalidate_domains, flush_domains); |
2181 | ||
88241785 CW |
2182 | ret = ring->flush(ring, invalidate_domains, flush_domains); |
2183 | if (ret) | |
2184 | return ret; | |
2185 | ||
db53a302 | 2186 | i915_gem_process_flushing_list(ring, flush_domains); |
88241785 | 2187 | return 0; |
54cf91dc CW |
2188 | } |
2189 | ||
db53a302 | 2190 | static int i915_ring_idle(struct intel_ring_buffer *ring) |
a56ba56c | 2191 | { |
88241785 CW |
2192 | int ret; |
2193 | ||
395b70be | 2194 | if (list_empty(&ring->gpu_write_list) && list_empty(&ring->active_list)) |
64193406 CW |
2195 | return 0; |
2196 | ||
88241785 | 2197 | if (!list_empty(&ring->gpu_write_list)) { |
db53a302 | 2198 | ret = i915_gem_flush_ring(ring, |
0ac74c6b | 2199 | I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS); |
88241785 CW |
2200 | if (ret) |
2201 | return ret; | |
2202 | } | |
2203 | ||
db53a302 CW |
2204 | return i915_wait_request(ring, |
2205 | i915_gem_next_request_seqno(ring), | |
2206 | true); | |
a56ba56c CW |
2207 | } |
2208 | ||
b47eb4a2 | 2209 | int |
4df2faf4 DV |
2210 | i915_gpu_idle(struct drm_device *dev) |
2211 | { | |
2212 | drm_i915_private_t *dev_priv = dev->dev_private; | |
2213 | bool lists_empty; | |
1ec14ad3 | 2214 | int ret, i; |
4df2faf4 | 2215 | |
d1b851fc | 2216 | lists_empty = (list_empty(&dev_priv->mm.flushing_list) && |
395b70be | 2217 | list_empty(&dev_priv->mm.active_list)); |
4df2faf4 DV |
2218 | if (lists_empty) |
2219 | return 0; | |
2220 | ||
2221 | /* Flush everything onto the inactive list. */ | |
1ec14ad3 | 2222 | for (i = 0; i < I915_NUM_RINGS; i++) { |
db53a302 | 2223 | ret = i915_ring_idle(&dev_priv->ring[i]); |
1ec14ad3 CW |
2224 | if (ret) |
2225 | return ret; | |
2226 | } | |
4df2faf4 | 2227 | |
8a1a49f9 | 2228 | return 0; |
4df2faf4 DV |
2229 | } |
2230 | ||
c6642782 DV |
2231 | static int sandybridge_write_fence_reg(struct drm_i915_gem_object *obj, |
2232 | struct intel_ring_buffer *pipelined) | |
4e901fdc | 2233 | { |
05394f39 | 2234 | struct drm_device *dev = obj->base.dev; |
4e901fdc | 2235 | drm_i915_private_t *dev_priv = dev->dev_private; |
05394f39 CW |
2236 | u32 size = obj->gtt_space->size; |
2237 | int regnum = obj->fence_reg; | |
4e901fdc EA |
2238 | uint64_t val; |
2239 | ||
05394f39 | 2240 | val = (uint64_t)((obj->gtt_offset + size - 4096) & |
c6642782 | 2241 | 0xfffff000) << 32; |
05394f39 CW |
2242 | val |= obj->gtt_offset & 0xfffff000; |
2243 | val |= (uint64_t)((obj->stride / 128) - 1) << | |
4e901fdc EA |
2244 | SANDYBRIDGE_FENCE_PITCH_SHIFT; |
2245 | ||
05394f39 | 2246 | if (obj->tiling_mode == I915_TILING_Y) |
4e901fdc EA |
2247 | val |= 1 << I965_FENCE_TILING_Y_SHIFT; |
2248 | val |= I965_FENCE_REG_VALID; | |
2249 | ||
c6642782 DV |
2250 | if (pipelined) { |
2251 | int ret = intel_ring_begin(pipelined, 6); | |
2252 | if (ret) | |
2253 | return ret; | |
2254 | ||
2255 | intel_ring_emit(pipelined, MI_NOOP); | |
2256 | intel_ring_emit(pipelined, MI_LOAD_REGISTER_IMM(2)); | |
2257 | intel_ring_emit(pipelined, FENCE_REG_SANDYBRIDGE_0 + regnum*8); | |
2258 | intel_ring_emit(pipelined, (u32)val); | |
2259 | intel_ring_emit(pipelined, FENCE_REG_SANDYBRIDGE_0 + regnum*8 + 4); | |
2260 | intel_ring_emit(pipelined, (u32)(val >> 32)); | |
2261 | intel_ring_advance(pipelined); | |
2262 | } else | |
2263 | I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + regnum * 8, val); | |
2264 | ||
2265 | return 0; | |
4e901fdc EA |
2266 | } |
2267 | ||
c6642782 DV |
2268 | static int i965_write_fence_reg(struct drm_i915_gem_object *obj, |
2269 | struct intel_ring_buffer *pipelined) | |
de151cf6 | 2270 | { |
05394f39 | 2271 | struct drm_device *dev = obj->base.dev; |
de151cf6 | 2272 | drm_i915_private_t *dev_priv = dev->dev_private; |
05394f39 CW |
2273 | u32 size = obj->gtt_space->size; |
2274 | int regnum = obj->fence_reg; | |
de151cf6 JB |
2275 | uint64_t val; |
2276 | ||
05394f39 | 2277 | val = (uint64_t)((obj->gtt_offset + size - 4096) & |
de151cf6 | 2278 | 0xfffff000) << 32; |
05394f39 CW |
2279 | val |= obj->gtt_offset & 0xfffff000; |
2280 | val |= ((obj->stride / 128) - 1) << I965_FENCE_PITCH_SHIFT; | |
2281 | if (obj->tiling_mode == I915_TILING_Y) | |
de151cf6 JB |
2282 | val |= 1 << I965_FENCE_TILING_Y_SHIFT; |
2283 | val |= I965_FENCE_REG_VALID; | |
2284 | ||
c6642782 DV |
2285 | if (pipelined) { |
2286 | int ret = intel_ring_begin(pipelined, 6); | |
2287 | if (ret) | |
2288 | return ret; | |
2289 | ||
2290 | intel_ring_emit(pipelined, MI_NOOP); | |
2291 | intel_ring_emit(pipelined, MI_LOAD_REGISTER_IMM(2)); | |
2292 | intel_ring_emit(pipelined, FENCE_REG_965_0 + regnum*8); | |
2293 | intel_ring_emit(pipelined, (u32)val); | |
2294 | intel_ring_emit(pipelined, FENCE_REG_965_0 + regnum*8 + 4); | |
2295 | intel_ring_emit(pipelined, (u32)(val >> 32)); | |
2296 | intel_ring_advance(pipelined); | |
2297 | } else | |
2298 | I915_WRITE64(FENCE_REG_965_0 + regnum * 8, val); | |
2299 | ||
2300 | return 0; | |
de151cf6 JB |
2301 | } |
2302 | ||
c6642782 DV |
2303 | static int i915_write_fence_reg(struct drm_i915_gem_object *obj, |
2304 | struct intel_ring_buffer *pipelined) | |
de151cf6 | 2305 | { |
05394f39 | 2306 | struct drm_device *dev = obj->base.dev; |
de151cf6 | 2307 | drm_i915_private_t *dev_priv = dev->dev_private; |
05394f39 | 2308 | u32 size = obj->gtt_space->size; |
c6642782 | 2309 | u32 fence_reg, val, pitch_val; |
0f973f27 | 2310 | int tile_width; |
de151cf6 | 2311 | |
c6642782 DV |
2312 | if (WARN((obj->gtt_offset & ~I915_FENCE_START_MASK) || |
2313 | (size & -size) != size || | |
2314 | (obj->gtt_offset & (size - 1)), | |
2315 | "object 0x%08x [fenceable? %d] not 1M or pot-size (0x%08x) aligned\n", | |
2316 | obj->gtt_offset, obj->map_and_fenceable, size)) | |
2317 | return -EINVAL; | |
de151cf6 | 2318 | |
c6642782 | 2319 | if (obj->tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev)) |
0f973f27 | 2320 | tile_width = 128; |
de151cf6 | 2321 | else |
0f973f27 JB |
2322 | tile_width = 512; |
2323 | ||
2324 | /* Note: pitch better be a power of two tile widths */ | |
05394f39 | 2325 | pitch_val = obj->stride / tile_width; |
0f973f27 | 2326 | pitch_val = ffs(pitch_val) - 1; |
de151cf6 | 2327 | |
05394f39 CW |
2328 | val = obj->gtt_offset; |
2329 | if (obj->tiling_mode == I915_TILING_Y) | |
de151cf6 | 2330 | val |= 1 << I830_FENCE_TILING_Y_SHIFT; |
a00b10c3 | 2331 | val |= I915_FENCE_SIZE_BITS(size); |
de151cf6 JB |
2332 | val |= pitch_val << I830_FENCE_PITCH_SHIFT; |
2333 | val |= I830_FENCE_REG_VALID; | |
2334 | ||
05394f39 | 2335 | fence_reg = obj->fence_reg; |
a00b10c3 CW |
2336 | if (fence_reg < 8) |
2337 | fence_reg = FENCE_REG_830_0 + fence_reg * 4; | |
dc529a4f | 2338 | else |
a00b10c3 | 2339 | fence_reg = FENCE_REG_945_8 + (fence_reg - 8) * 4; |
c6642782 DV |
2340 | |
2341 | if (pipelined) { | |
2342 | int ret = intel_ring_begin(pipelined, 4); | |
2343 | if (ret) | |
2344 | return ret; | |
2345 | ||
2346 | intel_ring_emit(pipelined, MI_NOOP); | |
2347 | intel_ring_emit(pipelined, MI_LOAD_REGISTER_IMM(1)); | |
2348 | intel_ring_emit(pipelined, fence_reg); | |
2349 | intel_ring_emit(pipelined, val); | |
2350 | intel_ring_advance(pipelined); | |
2351 | } else | |
2352 | I915_WRITE(fence_reg, val); | |
2353 | ||
2354 | return 0; | |
de151cf6 JB |
2355 | } |
2356 | ||
c6642782 DV |
2357 | static int i830_write_fence_reg(struct drm_i915_gem_object *obj, |
2358 | struct intel_ring_buffer *pipelined) | |
de151cf6 | 2359 | { |
05394f39 | 2360 | struct drm_device *dev = obj->base.dev; |
de151cf6 | 2361 | drm_i915_private_t *dev_priv = dev->dev_private; |
05394f39 CW |
2362 | u32 size = obj->gtt_space->size; |
2363 | int regnum = obj->fence_reg; | |
de151cf6 JB |
2364 | uint32_t val; |
2365 | uint32_t pitch_val; | |
2366 | ||
c6642782 DV |
2367 | if (WARN((obj->gtt_offset & ~I830_FENCE_START_MASK) || |
2368 | (size & -size) != size || | |
2369 | (obj->gtt_offset & (size - 1)), | |
2370 | "object 0x%08x not 512K or pot-size 0x%08x aligned\n", | |
2371 | obj->gtt_offset, size)) | |
2372 | return -EINVAL; | |
de151cf6 | 2373 | |
05394f39 | 2374 | pitch_val = obj->stride / 128; |
e76a16de | 2375 | pitch_val = ffs(pitch_val) - 1; |
e76a16de | 2376 | |
05394f39 CW |
2377 | val = obj->gtt_offset; |
2378 | if (obj->tiling_mode == I915_TILING_Y) | |
de151cf6 | 2379 | val |= 1 << I830_FENCE_TILING_Y_SHIFT; |
c6642782 | 2380 | val |= I830_FENCE_SIZE_BITS(size); |
de151cf6 JB |
2381 | val |= pitch_val << I830_FENCE_PITCH_SHIFT; |
2382 | val |= I830_FENCE_REG_VALID; | |
2383 | ||
c6642782 DV |
2384 | if (pipelined) { |
2385 | int ret = intel_ring_begin(pipelined, 4); | |
2386 | if (ret) | |
2387 | return ret; | |
2388 | ||
2389 | intel_ring_emit(pipelined, MI_NOOP); | |
2390 | intel_ring_emit(pipelined, MI_LOAD_REGISTER_IMM(1)); | |
2391 | intel_ring_emit(pipelined, FENCE_REG_830_0 + regnum*4); | |
2392 | intel_ring_emit(pipelined, val); | |
2393 | intel_ring_advance(pipelined); | |
2394 | } else | |
2395 | I915_WRITE(FENCE_REG_830_0 + regnum * 4, val); | |
2396 | ||
2397 | return 0; | |
de151cf6 JB |
2398 | } |
2399 | ||
d9e86c0e CW |
2400 | static bool ring_passed_seqno(struct intel_ring_buffer *ring, u32 seqno) |
2401 | { | |
2402 | return i915_seqno_passed(ring->get_seqno(ring), seqno); | |
2403 | } | |
2404 | ||
2405 | static int | |
2406 | i915_gem_object_flush_fence(struct drm_i915_gem_object *obj, | |
2407 | struct intel_ring_buffer *pipelined, | |
2408 | bool interruptible) | |
2409 | { | |
2410 | int ret; | |
2411 | ||
2412 | if (obj->fenced_gpu_access) { | |
88241785 | 2413 | if (obj->base.write_domain & I915_GEM_GPU_DOMAINS) { |
db53a302 | 2414 | ret = i915_gem_flush_ring(obj->last_fenced_ring, |
88241785 CW |
2415 | 0, obj->base.write_domain); |
2416 | if (ret) | |
2417 | return ret; | |
2418 | } | |
d9e86c0e CW |
2419 | |
2420 | obj->fenced_gpu_access = false; | |
2421 | } | |
2422 | ||
2423 | if (obj->last_fenced_seqno && pipelined != obj->last_fenced_ring) { | |
2424 | if (!ring_passed_seqno(obj->last_fenced_ring, | |
2425 | obj->last_fenced_seqno)) { | |
db53a302 CW |
2426 | ret = i915_wait_request(obj->last_fenced_ring, |
2427 | obj->last_fenced_seqno, | |
2428 | interruptible); | |
2429 | ||
d9e86c0e CW |
2430 | if (ret) |
2431 | return ret; | |
2432 | } | |
2433 | ||
2434 | obj->last_fenced_seqno = 0; | |
2435 | obj->last_fenced_ring = NULL; | |
2436 | } | |
2437 | ||
63256ec5 CW |
2438 | /* Ensure that all CPU reads are completed before installing a fence |
2439 | * and all writes before removing the fence. | |
2440 | */ | |
2441 | if (obj->base.read_domains & I915_GEM_DOMAIN_GTT) | |
2442 | mb(); | |
2443 | ||
d9e86c0e CW |
2444 | return 0; |
2445 | } | |
2446 | ||
2447 | int | |
2448 | i915_gem_object_put_fence(struct drm_i915_gem_object *obj) | |
2449 | { | |
2450 | int ret; | |
2451 | ||
2452 | if (obj->tiling_mode) | |
2453 | i915_gem_release_mmap(obj); | |
2454 | ||
2455 | ret = i915_gem_object_flush_fence(obj, NULL, true); | |
2456 | if (ret) | |
2457 | return ret; | |
2458 | ||
2459 | if (obj->fence_reg != I915_FENCE_REG_NONE) { | |
2460 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; | |
2461 | i915_gem_clear_fence_reg(obj->base.dev, | |
2462 | &dev_priv->fence_regs[obj->fence_reg]); | |
2463 | ||
2464 | obj->fence_reg = I915_FENCE_REG_NONE; | |
2465 | } | |
2466 | ||
2467 | return 0; | |
2468 | } | |
2469 | ||
2470 | static struct drm_i915_fence_reg * | |
2471 | i915_find_fence_reg(struct drm_device *dev, | |
2472 | struct intel_ring_buffer *pipelined) | |
ae3db24a | 2473 | { |
ae3db24a | 2474 | struct drm_i915_private *dev_priv = dev->dev_private; |
d9e86c0e CW |
2475 | struct drm_i915_fence_reg *reg, *first, *avail; |
2476 | int i; | |
ae3db24a DV |
2477 | |
2478 | /* First try to find a free reg */ | |
d9e86c0e | 2479 | avail = NULL; |
ae3db24a DV |
2480 | for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) { |
2481 | reg = &dev_priv->fence_regs[i]; | |
2482 | if (!reg->obj) | |
d9e86c0e | 2483 | return reg; |
ae3db24a | 2484 | |
05394f39 | 2485 | if (!reg->obj->pin_count) |
d9e86c0e | 2486 | avail = reg; |
ae3db24a DV |
2487 | } |
2488 | ||
d9e86c0e CW |
2489 | if (avail == NULL) |
2490 | return NULL; | |
ae3db24a DV |
2491 | |
2492 | /* None available, try to steal one or wait for a user to finish */ | |
d9e86c0e CW |
2493 | avail = first = NULL; |
2494 | list_for_each_entry(reg, &dev_priv->mm.fence_list, lru_list) { | |
2495 | if (reg->obj->pin_count) | |
ae3db24a DV |
2496 | continue; |
2497 | ||
d9e86c0e CW |
2498 | if (first == NULL) |
2499 | first = reg; | |
2500 | ||
2501 | if (!pipelined || | |
2502 | !reg->obj->last_fenced_ring || | |
2503 | reg->obj->last_fenced_ring == pipelined) { | |
2504 | avail = reg; | |
2505 | break; | |
2506 | } | |
ae3db24a DV |
2507 | } |
2508 | ||
d9e86c0e CW |
2509 | if (avail == NULL) |
2510 | avail = first; | |
ae3db24a | 2511 | |
a00b10c3 | 2512 | return avail; |
ae3db24a DV |
2513 | } |
2514 | ||
de151cf6 | 2515 | /** |
d9e86c0e | 2516 | * i915_gem_object_get_fence - set up a fence reg for an object |
de151cf6 | 2517 | * @obj: object to map through a fence reg |
d9e86c0e CW |
2518 | * @pipelined: ring on which to queue the change, or NULL for CPU access |
2519 | * @interruptible: must we wait uninterruptibly for the register to retire? | |
de151cf6 JB |
2520 | * |
2521 | * When mapping objects through the GTT, userspace wants to be able to write | |
2522 | * to them without having to worry about swizzling if the object is tiled. | |
2523 | * | |
2524 | * This function walks the fence regs looking for a free one for @obj, | |
2525 | * stealing one if it can't find any. | |
2526 | * | |
2527 | * It then sets up the reg based on the object's properties: address, pitch | |
2528 | * and tiling format. | |
2529 | */ | |
8c4b8c3f | 2530 | int |
d9e86c0e CW |
2531 | i915_gem_object_get_fence(struct drm_i915_gem_object *obj, |
2532 | struct intel_ring_buffer *pipelined, | |
2533 | bool interruptible) | |
de151cf6 | 2534 | { |
05394f39 | 2535 | struct drm_device *dev = obj->base.dev; |
79e53945 | 2536 | struct drm_i915_private *dev_priv = dev->dev_private; |
d9e86c0e | 2537 | struct drm_i915_fence_reg *reg; |
ae3db24a | 2538 | int ret; |
de151cf6 | 2539 | |
6bda10d1 CW |
2540 | /* XXX disable pipelining. There are bugs. Shocking. */ |
2541 | pipelined = NULL; | |
2542 | ||
d9e86c0e | 2543 | /* Just update our place in the LRU if our fence is getting reused. */ |
05394f39 CW |
2544 | if (obj->fence_reg != I915_FENCE_REG_NONE) { |
2545 | reg = &dev_priv->fence_regs[obj->fence_reg]; | |
007cc8ac | 2546 | list_move_tail(®->lru_list, &dev_priv->mm.fence_list); |
d9e86c0e CW |
2547 | |
2548 | if (!obj->fenced_gpu_access && !obj->last_fenced_seqno) | |
2549 | pipelined = NULL; | |
2550 | ||
2551 | if (!pipelined) { | |
2552 | if (reg->setup_seqno) { | |
2553 | if (!ring_passed_seqno(obj->last_fenced_ring, | |
2554 | reg->setup_seqno)) { | |
db53a302 CW |
2555 | ret = i915_wait_request(obj->last_fenced_ring, |
2556 | reg->setup_seqno, | |
2557 | interruptible); | |
d9e86c0e CW |
2558 | if (ret) |
2559 | return ret; | |
2560 | } | |
2561 | ||
2562 | reg->setup_seqno = 0; | |
2563 | } | |
2564 | } else if (obj->last_fenced_ring && | |
2565 | obj->last_fenced_ring != pipelined) { | |
2566 | ret = i915_gem_object_flush_fence(obj, | |
2567 | pipelined, | |
2568 | interruptible); | |
2569 | if (ret) | |
2570 | return ret; | |
2571 | } else if (obj->tiling_changed) { | |
2572 | if (obj->fenced_gpu_access) { | |
88241785 | 2573 | if (obj->base.write_domain & I915_GEM_GPU_DOMAINS) { |
db53a302 | 2574 | ret = i915_gem_flush_ring(obj->ring, |
88241785 CW |
2575 | 0, obj->base.write_domain); |
2576 | if (ret) | |
2577 | return ret; | |
2578 | } | |
d9e86c0e CW |
2579 | |
2580 | obj->fenced_gpu_access = false; | |
2581 | } | |
2582 | } | |
2583 | ||
2584 | if (!obj->fenced_gpu_access && !obj->last_fenced_seqno) | |
2585 | pipelined = NULL; | |
2586 | BUG_ON(!pipelined && reg->setup_seqno); | |
2587 | ||
2588 | if (obj->tiling_changed) { | |
2589 | if (pipelined) { | |
2590 | reg->setup_seqno = | |
db53a302 | 2591 | i915_gem_next_request_seqno(pipelined); |
d9e86c0e CW |
2592 | obj->last_fenced_seqno = reg->setup_seqno; |
2593 | obj->last_fenced_ring = pipelined; | |
2594 | } | |
2595 | goto update; | |
2596 | } | |
2597 | ||
a09ba7fa EA |
2598 | return 0; |
2599 | } | |
2600 | ||
d9e86c0e CW |
2601 | reg = i915_find_fence_reg(dev, pipelined); |
2602 | if (reg == NULL) | |
2603 | return -ENOSPC; | |
de151cf6 | 2604 | |
d9e86c0e CW |
2605 | ret = i915_gem_object_flush_fence(obj, pipelined, interruptible); |
2606 | if (ret) | |
ae3db24a | 2607 | return ret; |
de151cf6 | 2608 | |
d9e86c0e CW |
2609 | if (reg->obj) { |
2610 | struct drm_i915_gem_object *old = reg->obj; | |
2611 | ||
2612 | drm_gem_object_reference(&old->base); | |
2613 | ||
2614 | if (old->tiling_mode) | |
2615 | i915_gem_release_mmap(old); | |
2616 | ||
d9e86c0e | 2617 | ret = i915_gem_object_flush_fence(old, |
6bda10d1 | 2618 | pipelined, |
d9e86c0e CW |
2619 | interruptible); |
2620 | if (ret) { | |
2621 | drm_gem_object_unreference(&old->base); | |
2622 | return ret; | |
2623 | } | |
2624 | ||
2625 | if (old->last_fenced_seqno == 0 && obj->last_fenced_seqno == 0) | |
2626 | pipelined = NULL; | |
2627 | ||
2628 | old->fence_reg = I915_FENCE_REG_NONE; | |
2629 | old->last_fenced_ring = pipelined; | |
2630 | old->last_fenced_seqno = | |
db53a302 | 2631 | pipelined ? i915_gem_next_request_seqno(pipelined) : 0; |
d9e86c0e CW |
2632 | |
2633 | drm_gem_object_unreference(&old->base); | |
2634 | } else if (obj->last_fenced_seqno == 0) | |
2635 | pipelined = NULL; | |
a09ba7fa | 2636 | |
de151cf6 | 2637 | reg->obj = obj; |
d9e86c0e CW |
2638 | list_move_tail(®->lru_list, &dev_priv->mm.fence_list); |
2639 | obj->fence_reg = reg - dev_priv->fence_regs; | |
2640 | obj->last_fenced_ring = pipelined; | |
de151cf6 | 2641 | |
d9e86c0e | 2642 | reg->setup_seqno = |
db53a302 | 2643 | pipelined ? i915_gem_next_request_seqno(pipelined) : 0; |
d9e86c0e CW |
2644 | obj->last_fenced_seqno = reg->setup_seqno; |
2645 | ||
2646 | update: | |
2647 | obj->tiling_changed = false; | |
e259befd CW |
2648 | switch (INTEL_INFO(dev)->gen) { |
2649 | case 6: | |
c6642782 | 2650 | ret = sandybridge_write_fence_reg(obj, pipelined); |
e259befd CW |
2651 | break; |
2652 | case 5: | |
2653 | case 4: | |
c6642782 | 2654 | ret = i965_write_fence_reg(obj, pipelined); |
e259befd CW |
2655 | break; |
2656 | case 3: | |
c6642782 | 2657 | ret = i915_write_fence_reg(obj, pipelined); |
e259befd CW |
2658 | break; |
2659 | case 2: | |
c6642782 | 2660 | ret = i830_write_fence_reg(obj, pipelined); |
e259befd CW |
2661 | break; |
2662 | } | |
d9ddcb96 | 2663 | |
c6642782 | 2664 | return ret; |
de151cf6 JB |
2665 | } |
2666 | ||
2667 | /** | |
2668 | * i915_gem_clear_fence_reg - clear out fence register info | |
2669 | * @obj: object to clear | |
2670 | * | |
2671 | * Zeroes out the fence register itself and clears out the associated | |
05394f39 | 2672 | * data structures in dev_priv and obj. |
de151cf6 JB |
2673 | */ |
2674 | static void | |
d9e86c0e CW |
2675 | i915_gem_clear_fence_reg(struct drm_device *dev, |
2676 | struct drm_i915_fence_reg *reg) | |
de151cf6 | 2677 | { |
79e53945 | 2678 | drm_i915_private_t *dev_priv = dev->dev_private; |
d9e86c0e | 2679 | uint32_t fence_reg = reg - dev_priv->fence_regs; |
de151cf6 | 2680 | |
e259befd CW |
2681 | switch (INTEL_INFO(dev)->gen) { |
2682 | case 6: | |
d9e86c0e | 2683 | I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + fence_reg*8, 0); |
e259befd CW |
2684 | break; |
2685 | case 5: | |
2686 | case 4: | |
d9e86c0e | 2687 | I915_WRITE64(FENCE_REG_965_0 + fence_reg*8, 0); |
e259befd CW |
2688 | break; |
2689 | case 3: | |
d9e86c0e CW |
2690 | if (fence_reg >= 8) |
2691 | fence_reg = FENCE_REG_945_8 + (fence_reg - 8) * 4; | |
dc529a4f | 2692 | else |
e259befd | 2693 | case 2: |
d9e86c0e | 2694 | fence_reg = FENCE_REG_830_0 + fence_reg * 4; |
dc529a4f EA |
2695 | |
2696 | I915_WRITE(fence_reg, 0); | |
e259befd | 2697 | break; |
dc529a4f | 2698 | } |
de151cf6 | 2699 | |
007cc8ac | 2700 | list_del_init(®->lru_list); |
d9e86c0e CW |
2701 | reg->obj = NULL; |
2702 | reg->setup_seqno = 0; | |
52dc7d32 CW |
2703 | } |
2704 | ||
673a394b EA |
2705 | /** |
2706 | * Finds free space in the GTT aperture and binds the object there. | |
2707 | */ | |
2708 | static int | |
05394f39 | 2709 | i915_gem_object_bind_to_gtt(struct drm_i915_gem_object *obj, |
920afa77 | 2710 | unsigned alignment, |
75e9e915 | 2711 | bool map_and_fenceable) |
673a394b | 2712 | { |
05394f39 | 2713 | struct drm_device *dev = obj->base.dev; |
673a394b | 2714 | drm_i915_private_t *dev_priv = dev->dev_private; |
673a394b | 2715 | struct drm_mm_node *free_space; |
a00b10c3 | 2716 | gfp_t gfpmask = __GFP_NORETRY | __GFP_NOWARN; |
5e783301 | 2717 | u32 size, fence_size, fence_alignment, unfenced_alignment; |
75e9e915 | 2718 | bool mappable, fenceable; |
07f73f69 | 2719 | int ret; |
673a394b | 2720 | |
05394f39 | 2721 | if (obj->madv != I915_MADV_WILLNEED) { |
3ef94daa CW |
2722 | DRM_ERROR("Attempting to bind a purgeable object\n"); |
2723 | return -EINVAL; | |
2724 | } | |
2725 | ||
05394f39 CW |
2726 | fence_size = i915_gem_get_gtt_size(obj); |
2727 | fence_alignment = i915_gem_get_gtt_alignment(obj); | |
2728 | unfenced_alignment = i915_gem_get_unfenced_gtt_alignment(obj); | |
a00b10c3 | 2729 | |
673a394b | 2730 | if (alignment == 0) |
5e783301 DV |
2731 | alignment = map_and_fenceable ? fence_alignment : |
2732 | unfenced_alignment; | |
75e9e915 | 2733 | if (map_and_fenceable && alignment & (fence_alignment - 1)) { |
673a394b EA |
2734 | DRM_ERROR("Invalid object alignment requested %u\n", alignment); |
2735 | return -EINVAL; | |
2736 | } | |
2737 | ||
05394f39 | 2738 | size = map_and_fenceable ? fence_size : obj->base.size; |
a00b10c3 | 2739 | |
654fc607 CW |
2740 | /* If the object is bigger than the entire aperture, reject it early |
2741 | * before evicting everything in a vain attempt to find space. | |
2742 | */ | |
05394f39 | 2743 | if (obj->base.size > |
75e9e915 | 2744 | (map_and_fenceable ? dev_priv->mm.gtt_mappable_end : dev_priv->mm.gtt_total)) { |
654fc607 CW |
2745 | DRM_ERROR("Attempting to bind an object larger than the aperture\n"); |
2746 | return -E2BIG; | |
2747 | } | |
2748 | ||
673a394b | 2749 | search_free: |
75e9e915 | 2750 | if (map_and_fenceable) |
920afa77 DV |
2751 | free_space = |
2752 | drm_mm_search_free_in_range(&dev_priv->mm.gtt_space, | |
a00b10c3 | 2753 | size, alignment, 0, |
920afa77 DV |
2754 | dev_priv->mm.gtt_mappable_end, |
2755 | 0); | |
2756 | else | |
2757 | free_space = drm_mm_search_free(&dev_priv->mm.gtt_space, | |
a00b10c3 | 2758 | size, alignment, 0); |
920afa77 DV |
2759 | |
2760 | if (free_space != NULL) { | |
75e9e915 | 2761 | if (map_and_fenceable) |
05394f39 | 2762 | obj->gtt_space = |
920afa77 | 2763 | drm_mm_get_block_range_generic(free_space, |
a00b10c3 | 2764 | size, alignment, 0, |
920afa77 DV |
2765 | dev_priv->mm.gtt_mappable_end, |
2766 | 0); | |
2767 | else | |
05394f39 | 2768 | obj->gtt_space = |
a00b10c3 | 2769 | drm_mm_get_block(free_space, size, alignment); |
920afa77 | 2770 | } |
05394f39 | 2771 | if (obj->gtt_space == NULL) { |
673a394b EA |
2772 | /* If the gtt is empty and we're still having trouble |
2773 | * fitting our object in, we're out of memory. | |
2774 | */ | |
75e9e915 DV |
2775 | ret = i915_gem_evict_something(dev, size, alignment, |
2776 | map_and_fenceable); | |
9731129c | 2777 | if (ret) |
673a394b | 2778 | return ret; |
9731129c | 2779 | |
673a394b EA |
2780 | goto search_free; |
2781 | } | |
2782 | ||
e5281ccd | 2783 | ret = i915_gem_object_get_pages_gtt(obj, gfpmask); |
673a394b | 2784 | if (ret) { |
05394f39 CW |
2785 | drm_mm_put_block(obj->gtt_space); |
2786 | obj->gtt_space = NULL; | |
07f73f69 CW |
2787 | |
2788 | if (ret == -ENOMEM) { | |
809b6334 CW |
2789 | /* first try to reclaim some memory by clearing the GTT */ |
2790 | ret = i915_gem_evict_everything(dev, false); | |
07f73f69 | 2791 | if (ret) { |
07f73f69 | 2792 | /* now try to shrink everyone else */ |
4bdadb97 CW |
2793 | if (gfpmask) { |
2794 | gfpmask = 0; | |
2795 | goto search_free; | |
07f73f69 CW |
2796 | } |
2797 | ||
809b6334 | 2798 | return -ENOMEM; |
07f73f69 CW |
2799 | } |
2800 | ||
2801 | goto search_free; | |
2802 | } | |
2803 | ||
673a394b EA |
2804 | return ret; |
2805 | } | |
2806 | ||
7c2e6fdf DV |
2807 | ret = i915_gem_gtt_bind_object(obj); |
2808 | if (ret) { | |
e5281ccd | 2809 | i915_gem_object_put_pages_gtt(obj); |
05394f39 CW |
2810 | drm_mm_put_block(obj->gtt_space); |
2811 | obj->gtt_space = NULL; | |
07f73f69 | 2812 | |
809b6334 | 2813 | if (i915_gem_evict_everything(dev, false)) |
07f73f69 | 2814 | return ret; |
07f73f69 CW |
2815 | |
2816 | goto search_free; | |
673a394b | 2817 | } |
673a394b | 2818 | |
6299f992 | 2819 | list_add_tail(&obj->gtt_list, &dev_priv->mm.gtt_list); |
05394f39 | 2820 | list_add_tail(&obj->mm_list, &dev_priv->mm.inactive_list); |
bf1a1092 | 2821 | |
673a394b EA |
2822 | /* Assert that the object is not currently in any GPU domain. As it |
2823 | * wasn't in the GTT, there shouldn't be any way it could have been in | |
2824 | * a GPU cache | |
2825 | */ | |
05394f39 CW |
2826 | BUG_ON(obj->base.read_domains & I915_GEM_GPU_DOMAINS); |
2827 | BUG_ON(obj->base.write_domain & I915_GEM_GPU_DOMAINS); | |
673a394b | 2828 | |
6299f992 | 2829 | obj->gtt_offset = obj->gtt_space->start; |
1c5d22f7 | 2830 | |
75e9e915 | 2831 | fenceable = |
05394f39 CW |
2832 | obj->gtt_space->size == fence_size && |
2833 | (obj->gtt_space->start & (fence_alignment -1)) == 0; | |
a00b10c3 | 2834 | |
75e9e915 | 2835 | mappable = |
05394f39 | 2836 | obj->gtt_offset + obj->base.size <= dev_priv->mm.gtt_mappable_end; |
a00b10c3 | 2837 | |
05394f39 | 2838 | obj->map_and_fenceable = mappable && fenceable; |
75e9e915 | 2839 | |
db53a302 | 2840 | trace_i915_gem_object_bind(obj, map_and_fenceable); |
673a394b EA |
2841 | return 0; |
2842 | } | |
2843 | ||
2844 | void | |
05394f39 | 2845 | i915_gem_clflush_object(struct drm_i915_gem_object *obj) |
673a394b | 2846 | { |
673a394b EA |
2847 | /* If we don't have a page list set up, then we're not pinned |
2848 | * to GPU, and we can ignore the cache flush because it'll happen | |
2849 | * again at bind time. | |
2850 | */ | |
05394f39 | 2851 | if (obj->pages == NULL) |
673a394b EA |
2852 | return; |
2853 | ||
1c5d22f7 | 2854 | trace_i915_gem_object_clflush(obj); |
cfa16a0d | 2855 | |
05394f39 | 2856 | drm_clflush_pages(obj->pages, obj->base.size / PAGE_SIZE); |
673a394b EA |
2857 | } |
2858 | ||
e47c68e9 | 2859 | /** Flushes any GPU write domain for the object if it's dirty. */ |
88241785 | 2860 | static int |
3619df03 | 2861 | i915_gem_object_flush_gpu_write_domain(struct drm_i915_gem_object *obj) |
e47c68e9 | 2862 | { |
05394f39 | 2863 | if ((obj->base.write_domain & I915_GEM_GPU_DOMAINS) == 0) |
88241785 | 2864 | return 0; |
e47c68e9 EA |
2865 | |
2866 | /* Queue the GPU write cache flushing we need. */ | |
db53a302 | 2867 | return i915_gem_flush_ring(obj->ring, 0, obj->base.write_domain); |
e47c68e9 EA |
2868 | } |
2869 | ||
2870 | /** Flushes the GTT write domain for the object if it's dirty. */ | |
2871 | static void | |
05394f39 | 2872 | i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj) |
e47c68e9 | 2873 | { |
1c5d22f7 CW |
2874 | uint32_t old_write_domain; |
2875 | ||
05394f39 | 2876 | if (obj->base.write_domain != I915_GEM_DOMAIN_GTT) |
e47c68e9 EA |
2877 | return; |
2878 | ||
63256ec5 | 2879 | /* No actual flushing is required for the GTT write domain. Writes |
e47c68e9 EA |
2880 | * to it immediately go to main memory as far as we know, so there's |
2881 | * no chipset flush. It also doesn't land in render cache. | |
63256ec5 CW |
2882 | * |
2883 | * However, we do have to enforce the order so that all writes through | |
2884 | * the GTT land before any writes to the device, such as updates to | |
2885 | * the GATT itself. | |
e47c68e9 | 2886 | */ |
63256ec5 CW |
2887 | wmb(); |
2888 | ||
4a684a41 CW |
2889 | i915_gem_release_mmap(obj); |
2890 | ||
05394f39 CW |
2891 | old_write_domain = obj->base.write_domain; |
2892 | obj->base.write_domain = 0; | |
1c5d22f7 CW |
2893 | |
2894 | trace_i915_gem_object_change_domain(obj, | |
05394f39 | 2895 | obj->base.read_domains, |
1c5d22f7 | 2896 | old_write_domain); |
e47c68e9 EA |
2897 | } |
2898 | ||
2899 | /** Flushes the CPU write domain for the object if it's dirty. */ | |
2900 | static void | |
05394f39 | 2901 | i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj) |
e47c68e9 | 2902 | { |
1c5d22f7 | 2903 | uint32_t old_write_domain; |
e47c68e9 | 2904 | |
05394f39 | 2905 | if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) |
e47c68e9 EA |
2906 | return; |
2907 | ||
2908 | i915_gem_clflush_object(obj); | |
40ce6575 | 2909 | intel_gtt_chipset_flush(); |
05394f39 CW |
2910 | old_write_domain = obj->base.write_domain; |
2911 | obj->base.write_domain = 0; | |
1c5d22f7 CW |
2912 | |
2913 | trace_i915_gem_object_change_domain(obj, | |
05394f39 | 2914 | obj->base.read_domains, |
1c5d22f7 | 2915 | old_write_domain); |
e47c68e9 EA |
2916 | } |
2917 | ||
2ef7eeaa EA |
2918 | /** |
2919 | * Moves a single object to the GTT read, and possibly write domain. | |
2920 | * | |
2921 | * This function returns when the move is complete, including waiting on | |
2922 | * flushes to occur. | |
2923 | */ | |
79e53945 | 2924 | int |
2021746e | 2925 | i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write) |
2ef7eeaa | 2926 | { |
1c5d22f7 | 2927 | uint32_t old_write_domain, old_read_domains; |
e47c68e9 | 2928 | int ret; |
2ef7eeaa | 2929 | |
02354392 | 2930 | /* Not valid to be called on unbound objects. */ |
05394f39 | 2931 | if (obj->gtt_space == NULL) |
02354392 EA |
2932 | return -EINVAL; |
2933 | ||
8d7e3de1 CW |
2934 | if (obj->base.write_domain == I915_GEM_DOMAIN_GTT) |
2935 | return 0; | |
2936 | ||
88241785 CW |
2937 | ret = i915_gem_object_flush_gpu_write_domain(obj); |
2938 | if (ret) | |
2939 | return ret; | |
2940 | ||
87ca9c8a CW |
2941 | if (obj->pending_gpu_write || write) { |
2942 | ret = i915_gem_object_wait_rendering(obj, true); | |
2943 | if (ret) | |
2944 | return ret; | |
2945 | } | |
2dafb1e0 | 2946 | |
7213342d | 2947 | i915_gem_object_flush_cpu_write_domain(obj); |
1c5d22f7 | 2948 | |
05394f39 CW |
2949 | old_write_domain = obj->base.write_domain; |
2950 | old_read_domains = obj->base.read_domains; | |
1c5d22f7 | 2951 | |
e47c68e9 EA |
2952 | /* It should now be out of any other write domains, and we can update |
2953 | * the domain values for our changes. | |
2954 | */ | |
05394f39 CW |
2955 | BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) != 0); |
2956 | obj->base.read_domains |= I915_GEM_DOMAIN_GTT; | |
e47c68e9 | 2957 | if (write) { |
05394f39 CW |
2958 | obj->base.read_domains = I915_GEM_DOMAIN_GTT; |
2959 | obj->base.write_domain = I915_GEM_DOMAIN_GTT; | |
2960 | obj->dirty = 1; | |
2ef7eeaa EA |
2961 | } |
2962 | ||
1c5d22f7 CW |
2963 | trace_i915_gem_object_change_domain(obj, |
2964 | old_read_domains, | |
2965 | old_write_domain); | |
2966 | ||
e47c68e9 EA |
2967 | return 0; |
2968 | } | |
2969 | ||
b9241ea3 ZW |
2970 | /* |
2971 | * Prepare buffer for display plane. Use uninterruptible for possible flush | |
2972 | * wait, as in modesetting process we're not supposed to be interrupted. | |
2973 | */ | |
2974 | int | |
05394f39 | 2975 | i915_gem_object_set_to_display_plane(struct drm_i915_gem_object *obj, |
919926ae | 2976 | struct intel_ring_buffer *pipelined) |
b9241ea3 | 2977 | { |
ba3d8d74 | 2978 | uint32_t old_read_domains; |
b9241ea3 ZW |
2979 | int ret; |
2980 | ||
2981 | /* Not valid to be called on unbound objects. */ | |
05394f39 | 2982 | if (obj->gtt_space == NULL) |
b9241ea3 ZW |
2983 | return -EINVAL; |
2984 | ||
88241785 CW |
2985 | ret = i915_gem_object_flush_gpu_write_domain(obj); |
2986 | if (ret) | |
2987 | return ret; | |
2988 | ||
b9241ea3 | 2989 | |
ced270fa | 2990 | /* Currently, we are always called from an non-interruptible context. */ |
0be73284 | 2991 | if (pipelined != obj->ring) { |
ced270fa CW |
2992 | ret = i915_gem_object_wait_rendering(obj, false); |
2993 | if (ret) | |
b9241ea3 ZW |
2994 | return ret; |
2995 | } | |
2996 | ||
b118c1e3 CW |
2997 | i915_gem_object_flush_cpu_write_domain(obj); |
2998 | ||
05394f39 CW |
2999 | old_read_domains = obj->base.read_domains; |
3000 | obj->base.read_domains |= I915_GEM_DOMAIN_GTT; | |
b9241ea3 ZW |
3001 | |
3002 | trace_i915_gem_object_change_domain(obj, | |
3003 | old_read_domains, | |
05394f39 | 3004 | obj->base.write_domain); |
b9241ea3 ZW |
3005 | |
3006 | return 0; | |
3007 | } | |
3008 | ||
85345517 CW |
3009 | int |
3010 | i915_gem_object_flush_gpu(struct drm_i915_gem_object *obj, | |
3011 | bool interruptible) | |
3012 | { | |
88241785 CW |
3013 | int ret; |
3014 | ||
85345517 CW |
3015 | if (!obj->active) |
3016 | return 0; | |
3017 | ||
88241785 | 3018 | if (obj->base.write_domain & I915_GEM_GPU_DOMAINS) { |
db53a302 | 3019 | ret = i915_gem_flush_ring(obj->ring, 0, obj->base.write_domain); |
88241785 CW |
3020 | if (ret) |
3021 | return ret; | |
3022 | } | |
85345517 | 3023 | |
05394f39 | 3024 | return i915_gem_object_wait_rendering(obj, interruptible); |
85345517 CW |
3025 | } |
3026 | ||
e47c68e9 EA |
3027 | /** |
3028 | * Moves a single object to the CPU read, and possibly write domain. | |
3029 | * | |
3030 | * This function returns when the move is complete, including waiting on | |
3031 | * flushes to occur. | |
3032 | */ | |
3033 | static int | |
919926ae | 3034 | i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write) |
e47c68e9 | 3035 | { |
1c5d22f7 | 3036 | uint32_t old_write_domain, old_read_domains; |
e47c68e9 EA |
3037 | int ret; |
3038 | ||
8d7e3de1 CW |
3039 | if (obj->base.write_domain == I915_GEM_DOMAIN_CPU) |
3040 | return 0; | |
3041 | ||
88241785 CW |
3042 | ret = i915_gem_object_flush_gpu_write_domain(obj); |
3043 | if (ret) | |
3044 | return ret; | |
3045 | ||
de18a29e DV |
3046 | ret = i915_gem_object_wait_rendering(obj, true); |
3047 | if (ret) | |
e47c68e9 | 3048 | return ret; |
2ef7eeaa | 3049 | |
e47c68e9 | 3050 | i915_gem_object_flush_gtt_write_domain(obj); |
2ef7eeaa | 3051 | |
e47c68e9 EA |
3052 | /* If we have a partially-valid cache of the object in the CPU, |
3053 | * finish invalidating it and free the per-page flags. | |
2ef7eeaa | 3054 | */ |
e47c68e9 | 3055 | i915_gem_object_set_to_full_cpu_read_domain(obj); |
2ef7eeaa | 3056 | |
05394f39 CW |
3057 | old_write_domain = obj->base.write_domain; |
3058 | old_read_domains = obj->base.read_domains; | |
1c5d22f7 | 3059 | |
e47c68e9 | 3060 | /* Flush the CPU cache if it's still invalid. */ |
05394f39 | 3061 | if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) { |
2ef7eeaa | 3062 | i915_gem_clflush_object(obj); |
2ef7eeaa | 3063 | |
05394f39 | 3064 | obj->base.read_domains |= I915_GEM_DOMAIN_CPU; |
2ef7eeaa EA |
3065 | } |
3066 | ||
3067 | /* It should now be out of any other write domains, and we can update | |
3068 | * the domain values for our changes. | |
3069 | */ | |
05394f39 | 3070 | BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) != 0); |
e47c68e9 EA |
3071 | |
3072 | /* If we're writing through the CPU, then the GPU read domains will | |
3073 | * need to be invalidated at next use. | |
3074 | */ | |
3075 | if (write) { | |
05394f39 CW |
3076 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; |
3077 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; | |
e47c68e9 | 3078 | } |
2ef7eeaa | 3079 | |
1c5d22f7 CW |
3080 | trace_i915_gem_object_change_domain(obj, |
3081 | old_read_domains, | |
3082 | old_write_domain); | |
3083 | ||
2ef7eeaa EA |
3084 | return 0; |
3085 | } | |
3086 | ||
673a394b | 3087 | /** |
e47c68e9 | 3088 | * Moves the object from a partially CPU read to a full one. |
673a394b | 3089 | * |
e47c68e9 EA |
3090 | * Note that this only resolves i915_gem_object_set_cpu_read_domain_range(), |
3091 | * and doesn't handle transitioning from !(read_domains & I915_GEM_DOMAIN_CPU). | |
673a394b | 3092 | */ |
e47c68e9 | 3093 | static void |
05394f39 | 3094 | i915_gem_object_set_to_full_cpu_read_domain(struct drm_i915_gem_object *obj) |
673a394b | 3095 | { |
05394f39 | 3096 | if (!obj->page_cpu_valid) |
e47c68e9 EA |
3097 | return; |
3098 | ||
3099 | /* If we're partially in the CPU read domain, finish moving it in. | |
3100 | */ | |
05394f39 | 3101 | if (obj->base.read_domains & I915_GEM_DOMAIN_CPU) { |
e47c68e9 EA |
3102 | int i; |
3103 | ||
05394f39 CW |
3104 | for (i = 0; i <= (obj->base.size - 1) / PAGE_SIZE; i++) { |
3105 | if (obj->page_cpu_valid[i]) | |
e47c68e9 | 3106 | continue; |
05394f39 | 3107 | drm_clflush_pages(obj->pages + i, 1); |
e47c68e9 | 3108 | } |
e47c68e9 EA |
3109 | } |
3110 | ||
3111 | /* Free the page_cpu_valid mappings which are now stale, whether | |
3112 | * or not we've got I915_GEM_DOMAIN_CPU. | |
3113 | */ | |
05394f39 CW |
3114 | kfree(obj->page_cpu_valid); |
3115 | obj->page_cpu_valid = NULL; | |
e47c68e9 EA |
3116 | } |
3117 | ||
3118 | /** | |
3119 | * Set the CPU read domain on a range of the object. | |
3120 | * | |
3121 | * The object ends up with I915_GEM_DOMAIN_CPU in its read flags although it's | |
3122 | * not entirely valid. The page_cpu_valid member of the object flags which | |
3123 | * pages have been flushed, and will be respected by | |
3124 | * i915_gem_object_set_to_cpu_domain() if it's called on to get a valid mapping | |
3125 | * of the whole object. | |
3126 | * | |
3127 | * This function returns when the move is complete, including waiting on | |
3128 | * flushes to occur. | |
3129 | */ | |
3130 | static int | |
05394f39 | 3131 | i915_gem_object_set_cpu_read_domain_range(struct drm_i915_gem_object *obj, |
e47c68e9 EA |
3132 | uint64_t offset, uint64_t size) |
3133 | { | |
1c5d22f7 | 3134 | uint32_t old_read_domains; |
e47c68e9 | 3135 | int i, ret; |
673a394b | 3136 | |
05394f39 | 3137 | if (offset == 0 && size == obj->base.size) |
e47c68e9 | 3138 | return i915_gem_object_set_to_cpu_domain(obj, 0); |
673a394b | 3139 | |
88241785 CW |
3140 | ret = i915_gem_object_flush_gpu_write_domain(obj); |
3141 | if (ret) | |
3142 | return ret; | |
3143 | ||
de18a29e DV |
3144 | ret = i915_gem_object_wait_rendering(obj, true); |
3145 | if (ret) | |
6a47baa6 | 3146 | return ret; |
de18a29e | 3147 | |
e47c68e9 EA |
3148 | i915_gem_object_flush_gtt_write_domain(obj); |
3149 | ||
3150 | /* If we're already fully in the CPU read domain, we're done. */ | |
05394f39 CW |
3151 | if (obj->page_cpu_valid == NULL && |
3152 | (obj->base.read_domains & I915_GEM_DOMAIN_CPU) != 0) | |
e47c68e9 | 3153 | return 0; |
673a394b | 3154 | |
e47c68e9 EA |
3155 | /* Otherwise, create/clear the per-page CPU read domain flag if we're |
3156 | * newly adding I915_GEM_DOMAIN_CPU | |
3157 | */ | |
05394f39 CW |
3158 | if (obj->page_cpu_valid == NULL) { |
3159 | obj->page_cpu_valid = kzalloc(obj->base.size / PAGE_SIZE, | |
3160 | GFP_KERNEL); | |
3161 | if (obj->page_cpu_valid == NULL) | |
e47c68e9 | 3162 | return -ENOMEM; |
05394f39 CW |
3163 | } else if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) |
3164 | memset(obj->page_cpu_valid, 0, obj->base.size / PAGE_SIZE); | |
673a394b EA |
3165 | |
3166 | /* Flush the cache on any pages that are still invalid from the CPU's | |
3167 | * perspective. | |
3168 | */ | |
e47c68e9 EA |
3169 | for (i = offset / PAGE_SIZE; i <= (offset + size - 1) / PAGE_SIZE; |
3170 | i++) { | |
05394f39 | 3171 | if (obj->page_cpu_valid[i]) |
673a394b EA |
3172 | continue; |
3173 | ||
05394f39 | 3174 | drm_clflush_pages(obj->pages + i, 1); |
673a394b | 3175 | |
05394f39 | 3176 | obj->page_cpu_valid[i] = 1; |
673a394b EA |
3177 | } |
3178 | ||
e47c68e9 EA |
3179 | /* It should now be out of any other write domains, and we can update |
3180 | * the domain values for our changes. | |
3181 | */ | |
05394f39 | 3182 | BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) != 0); |
e47c68e9 | 3183 | |
05394f39 CW |
3184 | old_read_domains = obj->base.read_domains; |
3185 | obj->base.read_domains |= I915_GEM_DOMAIN_CPU; | |
e47c68e9 | 3186 | |
1c5d22f7 CW |
3187 | trace_i915_gem_object_change_domain(obj, |
3188 | old_read_domains, | |
05394f39 | 3189 | obj->base.write_domain); |
1c5d22f7 | 3190 | |
673a394b EA |
3191 | return 0; |
3192 | } | |
3193 | ||
673a394b EA |
3194 | /* Throttle our rendering by waiting until the ring has completed our requests |
3195 | * emitted over 20 msec ago. | |
3196 | * | |
b962442e EA |
3197 | * Note that if we were to use the current jiffies each time around the loop, |
3198 | * we wouldn't escape the function with any frames outstanding if the time to | |
3199 | * render a frame was over 20ms. | |
3200 | * | |
673a394b EA |
3201 | * This should get us reasonable parallelism between CPU and GPU but also |
3202 | * relatively low latency when blocking on a particular request to finish. | |
3203 | */ | |
40a5f0de | 3204 | static int |
f787a5f5 | 3205 | i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file) |
40a5f0de | 3206 | { |
f787a5f5 CW |
3207 | struct drm_i915_private *dev_priv = dev->dev_private; |
3208 | struct drm_i915_file_private *file_priv = file->driver_priv; | |
b962442e | 3209 | unsigned long recent_enough = jiffies - msecs_to_jiffies(20); |
f787a5f5 CW |
3210 | struct drm_i915_gem_request *request; |
3211 | struct intel_ring_buffer *ring = NULL; | |
3212 | u32 seqno = 0; | |
3213 | int ret; | |
93533c29 | 3214 | |
e110e8d6 CW |
3215 | if (atomic_read(&dev_priv->mm.wedged)) |
3216 | return -EIO; | |
3217 | ||
1c25595f | 3218 | spin_lock(&file_priv->mm.lock); |
f787a5f5 | 3219 | list_for_each_entry(request, &file_priv->mm.request_list, client_list) { |
b962442e EA |
3220 | if (time_after_eq(request->emitted_jiffies, recent_enough)) |
3221 | break; | |
40a5f0de | 3222 | |
f787a5f5 CW |
3223 | ring = request->ring; |
3224 | seqno = request->seqno; | |
b962442e | 3225 | } |
1c25595f | 3226 | spin_unlock(&file_priv->mm.lock); |
40a5f0de | 3227 | |
f787a5f5 CW |
3228 | if (seqno == 0) |
3229 | return 0; | |
2bc43b5c | 3230 | |
f787a5f5 | 3231 | ret = 0; |
78501eac | 3232 | if (!i915_seqno_passed(ring->get_seqno(ring), seqno)) { |
f787a5f5 CW |
3233 | /* And wait for the seqno passing without holding any locks and |
3234 | * causing extra latency for others. This is safe as the irq | |
3235 | * generation is designed to be run atomically and so is | |
3236 | * lockless. | |
3237 | */ | |
b13c2b96 CW |
3238 | if (ring->irq_get(ring)) { |
3239 | ret = wait_event_interruptible(ring->irq_queue, | |
3240 | i915_seqno_passed(ring->get_seqno(ring), seqno) | |
3241 | || atomic_read(&dev_priv->mm.wedged)); | |
3242 | ring->irq_put(ring); | |
40a5f0de | 3243 | |
b13c2b96 CW |
3244 | if (ret == 0 && atomic_read(&dev_priv->mm.wedged)) |
3245 | ret = -EIO; | |
3246 | } | |
40a5f0de EA |
3247 | } |
3248 | ||
f787a5f5 CW |
3249 | if (ret == 0) |
3250 | queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, 0); | |
40a5f0de EA |
3251 | |
3252 | return ret; | |
3253 | } | |
3254 | ||
673a394b | 3255 | int |
05394f39 CW |
3256 | i915_gem_object_pin(struct drm_i915_gem_object *obj, |
3257 | uint32_t alignment, | |
75e9e915 | 3258 | bool map_and_fenceable) |
673a394b | 3259 | { |
05394f39 | 3260 | struct drm_device *dev = obj->base.dev; |
f13d3f73 | 3261 | struct drm_i915_private *dev_priv = dev->dev_private; |
673a394b EA |
3262 | int ret; |
3263 | ||
05394f39 | 3264 | BUG_ON(obj->pin_count == DRM_I915_GEM_OBJECT_MAX_PIN_COUNT); |
23bc5982 | 3265 | WARN_ON(i915_verify_lists(dev)); |
ac0c6b5a | 3266 | |
05394f39 CW |
3267 | if (obj->gtt_space != NULL) { |
3268 | if ((alignment && obj->gtt_offset & (alignment - 1)) || | |
3269 | (map_and_fenceable && !obj->map_and_fenceable)) { | |
3270 | WARN(obj->pin_count, | |
ae7d49d8 | 3271 | "bo is already pinned with incorrect alignment:" |
75e9e915 DV |
3272 | " offset=%x, req.alignment=%x, req.map_and_fenceable=%d," |
3273 | " obj->map_and_fenceable=%d\n", | |
05394f39 | 3274 | obj->gtt_offset, alignment, |
75e9e915 | 3275 | map_and_fenceable, |
05394f39 | 3276 | obj->map_and_fenceable); |
ac0c6b5a CW |
3277 | ret = i915_gem_object_unbind(obj); |
3278 | if (ret) | |
3279 | return ret; | |
3280 | } | |
3281 | } | |
3282 | ||
05394f39 | 3283 | if (obj->gtt_space == NULL) { |
a00b10c3 | 3284 | ret = i915_gem_object_bind_to_gtt(obj, alignment, |
75e9e915 | 3285 | map_and_fenceable); |
9731129c | 3286 | if (ret) |
673a394b | 3287 | return ret; |
22c344e9 | 3288 | } |
76446cac | 3289 | |
05394f39 | 3290 | if (obj->pin_count++ == 0) { |
05394f39 CW |
3291 | if (!obj->active) |
3292 | list_move_tail(&obj->mm_list, | |
f13d3f73 | 3293 | &dev_priv->mm.pinned_list); |
673a394b | 3294 | } |
6299f992 | 3295 | obj->pin_mappable |= map_and_fenceable; |
673a394b | 3296 | |
23bc5982 | 3297 | WARN_ON(i915_verify_lists(dev)); |
673a394b EA |
3298 | return 0; |
3299 | } | |
3300 | ||
3301 | void | |
05394f39 | 3302 | i915_gem_object_unpin(struct drm_i915_gem_object *obj) |
673a394b | 3303 | { |
05394f39 | 3304 | struct drm_device *dev = obj->base.dev; |
673a394b | 3305 | drm_i915_private_t *dev_priv = dev->dev_private; |
673a394b | 3306 | |
23bc5982 | 3307 | WARN_ON(i915_verify_lists(dev)); |
05394f39 CW |
3308 | BUG_ON(obj->pin_count == 0); |
3309 | BUG_ON(obj->gtt_space == NULL); | |
673a394b | 3310 | |
05394f39 CW |
3311 | if (--obj->pin_count == 0) { |
3312 | if (!obj->active) | |
3313 | list_move_tail(&obj->mm_list, | |
673a394b | 3314 | &dev_priv->mm.inactive_list); |
6299f992 | 3315 | obj->pin_mappable = false; |
673a394b | 3316 | } |
23bc5982 | 3317 | WARN_ON(i915_verify_lists(dev)); |
673a394b EA |
3318 | } |
3319 | ||
3320 | int | |
3321 | i915_gem_pin_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 3322 | struct drm_file *file) |
673a394b EA |
3323 | { |
3324 | struct drm_i915_gem_pin *args = data; | |
05394f39 | 3325 | struct drm_i915_gem_object *obj; |
673a394b EA |
3326 | int ret; |
3327 | ||
1d7cfea1 CW |
3328 | ret = i915_mutex_lock_interruptible(dev); |
3329 | if (ret) | |
3330 | return ret; | |
673a394b | 3331 | |
05394f39 | 3332 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
673a394b | 3333 | if (obj == NULL) { |
1d7cfea1 CW |
3334 | ret = -ENOENT; |
3335 | goto unlock; | |
673a394b | 3336 | } |
673a394b | 3337 | |
05394f39 | 3338 | if (obj->madv != I915_MADV_WILLNEED) { |
bb6baf76 | 3339 | DRM_ERROR("Attempting to pin a purgeable buffer\n"); |
1d7cfea1 CW |
3340 | ret = -EINVAL; |
3341 | goto out; | |
3ef94daa CW |
3342 | } |
3343 | ||
05394f39 | 3344 | if (obj->pin_filp != NULL && obj->pin_filp != file) { |
79e53945 JB |
3345 | DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n", |
3346 | args->handle); | |
1d7cfea1 CW |
3347 | ret = -EINVAL; |
3348 | goto out; | |
79e53945 JB |
3349 | } |
3350 | ||
05394f39 CW |
3351 | obj->user_pin_count++; |
3352 | obj->pin_filp = file; | |
3353 | if (obj->user_pin_count == 1) { | |
75e9e915 | 3354 | ret = i915_gem_object_pin(obj, args->alignment, true); |
1d7cfea1 CW |
3355 | if (ret) |
3356 | goto out; | |
673a394b EA |
3357 | } |
3358 | ||
3359 | /* XXX - flush the CPU caches for pinned objects | |
3360 | * as the X server doesn't manage domains yet | |
3361 | */ | |
e47c68e9 | 3362 | i915_gem_object_flush_cpu_write_domain(obj); |
05394f39 | 3363 | args->offset = obj->gtt_offset; |
1d7cfea1 | 3364 | out: |
05394f39 | 3365 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 3366 | unlock: |
673a394b | 3367 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 3368 | return ret; |
673a394b EA |
3369 | } |
3370 | ||
3371 | int | |
3372 | i915_gem_unpin_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 3373 | struct drm_file *file) |
673a394b EA |
3374 | { |
3375 | struct drm_i915_gem_pin *args = data; | |
05394f39 | 3376 | struct drm_i915_gem_object *obj; |
76c1dec1 | 3377 | int ret; |
673a394b | 3378 | |
1d7cfea1 CW |
3379 | ret = i915_mutex_lock_interruptible(dev); |
3380 | if (ret) | |
3381 | return ret; | |
673a394b | 3382 | |
05394f39 | 3383 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
673a394b | 3384 | if (obj == NULL) { |
1d7cfea1 CW |
3385 | ret = -ENOENT; |
3386 | goto unlock; | |
673a394b | 3387 | } |
76c1dec1 | 3388 | |
05394f39 | 3389 | if (obj->pin_filp != file) { |
79e53945 JB |
3390 | DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n", |
3391 | args->handle); | |
1d7cfea1 CW |
3392 | ret = -EINVAL; |
3393 | goto out; | |
79e53945 | 3394 | } |
05394f39 CW |
3395 | obj->user_pin_count--; |
3396 | if (obj->user_pin_count == 0) { | |
3397 | obj->pin_filp = NULL; | |
79e53945 JB |
3398 | i915_gem_object_unpin(obj); |
3399 | } | |
673a394b | 3400 | |
1d7cfea1 | 3401 | out: |
05394f39 | 3402 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 3403 | unlock: |
673a394b | 3404 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 3405 | return ret; |
673a394b EA |
3406 | } |
3407 | ||
3408 | int | |
3409 | i915_gem_busy_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 3410 | struct drm_file *file) |
673a394b EA |
3411 | { |
3412 | struct drm_i915_gem_busy *args = data; | |
05394f39 | 3413 | struct drm_i915_gem_object *obj; |
30dbf0c0 CW |
3414 | int ret; |
3415 | ||
76c1dec1 | 3416 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 3417 | if (ret) |
76c1dec1 | 3418 | return ret; |
673a394b | 3419 | |
05394f39 | 3420 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
673a394b | 3421 | if (obj == NULL) { |
1d7cfea1 CW |
3422 | ret = -ENOENT; |
3423 | goto unlock; | |
673a394b | 3424 | } |
d1b851fc | 3425 | |
0be555b6 CW |
3426 | /* Count all active objects as busy, even if they are currently not used |
3427 | * by the gpu. Users of this interface expect objects to eventually | |
3428 | * become non-busy without any further actions, therefore emit any | |
3429 | * necessary flushes here. | |
c4de0a5d | 3430 | */ |
05394f39 | 3431 | args->busy = obj->active; |
0be555b6 CW |
3432 | if (args->busy) { |
3433 | /* Unconditionally flush objects, even when the gpu still uses this | |
3434 | * object. Userspace calling this function indicates that it wants to | |
3435 | * use this buffer rather sooner than later, so issuing the required | |
3436 | * flush earlier is beneficial. | |
3437 | */ | |
1a1c6976 | 3438 | if (obj->base.write_domain & I915_GEM_GPU_DOMAINS) { |
db53a302 | 3439 | ret = i915_gem_flush_ring(obj->ring, |
88241785 | 3440 | 0, obj->base.write_domain); |
1a1c6976 CW |
3441 | } else if (obj->ring->outstanding_lazy_request == |
3442 | obj->last_rendering_seqno) { | |
3443 | struct drm_i915_gem_request *request; | |
3444 | ||
7a194876 CW |
3445 | /* This ring is not being cleared by active usage, |
3446 | * so emit a request to do so. | |
3447 | */ | |
1a1c6976 CW |
3448 | request = kzalloc(sizeof(*request), GFP_KERNEL); |
3449 | if (request) | |
db53a302 | 3450 | ret = i915_add_request(obj->ring, NULL,request); |
1a1c6976 | 3451 | else |
7a194876 CW |
3452 | ret = -ENOMEM; |
3453 | } | |
0be555b6 CW |
3454 | |
3455 | /* Update the active list for the hardware's current position. | |
3456 | * Otherwise this only updates on a delayed timer or when irqs | |
3457 | * are actually unmasked, and our working set ends up being | |
3458 | * larger than required. | |
3459 | */ | |
db53a302 | 3460 | i915_gem_retire_requests_ring(obj->ring); |
0be555b6 | 3461 | |
05394f39 | 3462 | args->busy = obj->active; |
0be555b6 | 3463 | } |
673a394b | 3464 | |
05394f39 | 3465 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 3466 | unlock: |
673a394b | 3467 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 3468 | return ret; |
673a394b EA |
3469 | } |
3470 | ||
3471 | int | |
3472 | i915_gem_throttle_ioctl(struct drm_device *dev, void *data, | |
3473 | struct drm_file *file_priv) | |
3474 | { | |
3475 | return i915_gem_ring_throttle(dev, file_priv); | |
3476 | } | |
3477 | ||
3ef94daa CW |
3478 | int |
3479 | i915_gem_madvise_ioctl(struct drm_device *dev, void *data, | |
3480 | struct drm_file *file_priv) | |
3481 | { | |
3482 | struct drm_i915_gem_madvise *args = data; | |
05394f39 | 3483 | struct drm_i915_gem_object *obj; |
76c1dec1 | 3484 | int ret; |
3ef94daa CW |
3485 | |
3486 | switch (args->madv) { | |
3487 | case I915_MADV_DONTNEED: | |
3488 | case I915_MADV_WILLNEED: | |
3489 | break; | |
3490 | default: | |
3491 | return -EINVAL; | |
3492 | } | |
3493 | ||
1d7cfea1 CW |
3494 | ret = i915_mutex_lock_interruptible(dev); |
3495 | if (ret) | |
3496 | return ret; | |
3497 | ||
05394f39 | 3498 | obj = to_intel_bo(drm_gem_object_lookup(dev, file_priv, args->handle)); |
3ef94daa | 3499 | if (obj == NULL) { |
1d7cfea1 CW |
3500 | ret = -ENOENT; |
3501 | goto unlock; | |
3ef94daa | 3502 | } |
3ef94daa | 3503 | |
05394f39 | 3504 | if (obj->pin_count) { |
1d7cfea1 CW |
3505 | ret = -EINVAL; |
3506 | goto out; | |
3ef94daa CW |
3507 | } |
3508 | ||
05394f39 CW |
3509 | if (obj->madv != __I915_MADV_PURGED) |
3510 | obj->madv = args->madv; | |
3ef94daa | 3511 | |
2d7ef395 | 3512 | /* if the object is no longer bound, discard its backing storage */ |
05394f39 CW |
3513 | if (i915_gem_object_is_purgeable(obj) && |
3514 | obj->gtt_space == NULL) | |
2d7ef395 CW |
3515 | i915_gem_object_truncate(obj); |
3516 | ||
05394f39 | 3517 | args->retained = obj->madv != __I915_MADV_PURGED; |
bb6baf76 | 3518 | |
1d7cfea1 | 3519 | out: |
05394f39 | 3520 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 3521 | unlock: |
3ef94daa | 3522 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 3523 | return ret; |
3ef94daa CW |
3524 | } |
3525 | ||
05394f39 CW |
3526 | struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev, |
3527 | size_t size) | |
ac52bc56 | 3528 | { |
73aa808f | 3529 | struct drm_i915_private *dev_priv = dev->dev_private; |
c397b908 | 3530 | struct drm_i915_gem_object *obj; |
ac52bc56 | 3531 | |
c397b908 DV |
3532 | obj = kzalloc(sizeof(*obj), GFP_KERNEL); |
3533 | if (obj == NULL) | |
3534 | return NULL; | |
673a394b | 3535 | |
c397b908 DV |
3536 | if (drm_gem_object_init(dev, &obj->base, size) != 0) { |
3537 | kfree(obj); | |
3538 | return NULL; | |
3539 | } | |
673a394b | 3540 | |
73aa808f CW |
3541 | i915_gem_info_add_obj(dev_priv, size); |
3542 | ||
c397b908 DV |
3543 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; |
3544 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; | |
673a394b | 3545 | |
c397b908 | 3546 | obj->agp_type = AGP_USER_MEMORY; |
62b8b215 | 3547 | obj->base.driver_private = NULL; |
c397b908 | 3548 | obj->fence_reg = I915_FENCE_REG_NONE; |
69dc4987 | 3549 | INIT_LIST_HEAD(&obj->mm_list); |
93a37f20 | 3550 | INIT_LIST_HEAD(&obj->gtt_list); |
69dc4987 | 3551 | INIT_LIST_HEAD(&obj->ring_list); |
432e58ed | 3552 | INIT_LIST_HEAD(&obj->exec_list); |
c397b908 | 3553 | INIT_LIST_HEAD(&obj->gpu_write_list); |
c397b908 | 3554 | obj->madv = I915_MADV_WILLNEED; |
75e9e915 DV |
3555 | /* Avoid an unnecessary call to unbind on the first bind. */ |
3556 | obj->map_and_fenceable = true; | |
de151cf6 | 3557 | |
05394f39 | 3558 | return obj; |
c397b908 DV |
3559 | } |
3560 | ||
3561 | int i915_gem_init_object(struct drm_gem_object *obj) | |
3562 | { | |
3563 | BUG(); | |
de151cf6 | 3564 | |
673a394b EA |
3565 | return 0; |
3566 | } | |
3567 | ||
05394f39 | 3568 | static void i915_gem_free_object_tail(struct drm_i915_gem_object *obj) |
673a394b | 3569 | { |
05394f39 | 3570 | struct drm_device *dev = obj->base.dev; |
be72615b | 3571 | drm_i915_private_t *dev_priv = dev->dev_private; |
be72615b | 3572 | int ret; |
673a394b | 3573 | |
be72615b CW |
3574 | ret = i915_gem_object_unbind(obj); |
3575 | if (ret == -ERESTARTSYS) { | |
05394f39 | 3576 | list_move(&obj->mm_list, |
be72615b CW |
3577 | &dev_priv->mm.deferred_free_list); |
3578 | return; | |
3579 | } | |
673a394b | 3580 | |
05394f39 | 3581 | if (obj->base.map_list.map) |
7e616158 | 3582 | i915_gem_free_mmap_offset(obj); |
de151cf6 | 3583 | |
05394f39 CW |
3584 | drm_gem_object_release(&obj->base); |
3585 | i915_gem_info_remove_obj(dev_priv, obj->base.size); | |
c397b908 | 3586 | |
05394f39 CW |
3587 | kfree(obj->page_cpu_valid); |
3588 | kfree(obj->bit_17); | |
3589 | kfree(obj); | |
db53a302 CW |
3590 | |
3591 | trace_i915_gem_object_destroy(obj); | |
673a394b EA |
3592 | } |
3593 | ||
05394f39 | 3594 | void i915_gem_free_object(struct drm_gem_object *gem_obj) |
be72615b | 3595 | { |
05394f39 CW |
3596 | struct drm_i915_gem_object *obj = to_intel_bo(gem_obj); |
3597 | struct drm_device *dev = obj->base.dev; | |
be72615b | 3598 | |
05394f39 | 3599 | while (obj->pin_count > 0) |
be72615b CW |
3600 | i915_gem_object_unpin(obj); |
3601 | ||
05394f39 | 3602 | if (obj->phys_obj) |
be72615b CW |
3603 | i915_gem_detach_phys_object(dev, obj); |
3604 | ||
3605 | i915_gem_free_object_tail(obj); | |
3606 | } | |
3607 | ||
29105ccc CW |
3608 | int |
3609 | i915_gem_idle(struct drm_device *dev) | |
3610 | { | |
3611 | drm_i915_private_t *dev_priv = dev->dev_private; | |
3612 | int ret; | |
28dfe52a | 3613 | |
29105ccc | 3614 | mutex_lock(&dev->struct_mutex); |
1c5d22f7 | 3615 | |
87acb0a5 | 3616 | if (dev_priv->mm.suspended) { |
29105ccc CW |
3617 | mutex_unlock(&dev->struct_mutex); |
3618 | return 0; | |
28dfe52a EA |
3619 | } |
3620 | ||
29105ccc | 3621 | ret = i915_gpu_idle(dev); |
6dbe2772 KP |
3622 | if (ret) { |
3623 | mutex_unlock(&dev->struct_mutex); | |
673a394b | 3624 | return ret; |
6dbe2772 | 3625 | } |
673a394b | 3626 | |
29105ccc CW |
3627 | /* Under UMS, be paranoid and evict. */ |
3628 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) { | |
5eac3ab4 | 3629 | ret = i915_gem_evict_inactive(dev, false); |
29105ccc CW |
3630 | if (ret) { |
3631 | mutex_unlock(&dev->struct_mutex); | |
3632 | return ret; | |
3633 | } | |
3634 | } | |
3635 | ||
312817a3 CW |
3636 | i915_gem_reset_fences(dev); |
3637 | ||
29105ccc CW |
3638 | /* Hack! Don't let anybody do execbuf while we don't control the chip. |
3639 | * We need to replace this with a semaphore, or something. | |
3640 | * And not confound mm.suspended! | |
3641 | */ | |
3642 | dev_priv->mm.suspended = 1; | |
bc0c7f14 | 3643 | del_timer_sync(&dev_priv->hangcheck_timer); |
29105ccc CW |
3644 | |
3645 | i915_kernel_lost_context(dev); | |
6dbe2772 | 3646 | i915_gem_cleanup_ringbuffer(dev); |
29105ccc | 3647 | |
6dbe2772 KP |
3648 | mutex_unlock(&dev->struct_mutex); |
3649 | ||
29105ccc CW |
3650 | /* Cancel the retire work handler, which should be idle now. */ |
3651 | cancel_delayed_work_sync(&dev_priv->mm.retire_work); | |
3652 | ||
673a394b EA |
3653 | return 0; |
3654 | } | |
3655 | ||
8187a2b7 ZN |
3656 | int |
3657 | i915_gem_init_ringbuffer(struct drm_device *dev) | |
3658 | { | |
3659 | drm_i915_private_t *dev_priv = dev->dev_private; | |
3660 | int ret; | |
68f95ba9 | 3661 | |
5c1143bb | 3662 | ret = intel_init_render_ring_buffer(dev); |
68f95ba9 | 3663 | if (ret) |
b6913e4b | 3664 | return ret; |
68f95ba9 CW |
3665 | |
3666 | if (HAS_BSD(dev)) { | |
5c1143bb | 3667 | ret = intel_init_bsd_ring_buffer(dev); |
68f95ba9 CW |
3668 | if (ret) |
3669 | goto cleanup_render_ring; | |
d1b851fc | 3670 | } |
68f95ba9 | 3671 | |
549f7365 CW |
3672 | if (HAS_BLT(dev)) { |
3673 | ret = intel_init_blt_ring_buffer(dev); | |
3674 | if (ret) | |
3675 | goto cleanup_bsd_ring; | |
3676 | } | |
3677 | ||
6f392d54 CW |
3678 | dev_priv->next_seqno = 1; |
3679 | ||
68f95ba9 CW |
3680 | return 0; |
3681 | ||
549f7365 | 3682 | cleanup_bsd_ring: |
1ec14ad3 | 3683 | intel_cleanup_ring_buffer(&dev_priv->ring[VCS]); |
68f95ba9 | 3684 | cleanup_render_ring: |
1ec14ad3 | 3685 | intel_cleanup_ring_buffer(&dev_priv->ring[RCS]); |
8187a2b7 ZN |
3686 | return ret; |
3687 | } | |
3688 | ||
3689 | void | |
3690 | i915_gem_cleanup_ringbuffer(struct drm_device *dev) | |
3691 | { | |
3692 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1ec14ad3 | 3693 | int i; |
8187a2b7 | 3694 | |
1ec14ad3 CW |
3695 | for (i = 0; i < I915_NUM_RINGS; i++) |
3696 | intel_cleanup_ring_buffer(&dev_priv->ring[i]); | |
8187a2b7 ZN |
3697 | } |
3698 | ||
673a394b EA |
3699 | int |
3700 | i915_gem_entervt_ioctl(struct drm_device *dev, void *data, | |
3701 | struct drm_file *file_priv) | |
3702 | { | |
3703 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1ec14ad3 | 3704 | int ret, i; |
673a394b | 3705 | |
79e53945 JB |
3706 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
3707 | return 0; | |
3708 | ||
ba1234d1 | 3709 | if (atomic_read(&dev_priv->mm.wedged)) { |
673a394b | 3710 | DRM_ERROR("Reenabling wedged hardware, good luck\n"); |
ba1234d1 | 3711 | atomic_set(&dev_priv->mm.wedged, 0); |
673a394b EA |
3712 | } |
3713 | ||
673a394b | 3714 | mutex_lock(&dev->struct_mutex); |
9bb2d6f9 EA |
3715 | dev_priv->mm.suspended = 0; |
3716 | ||
3717 | ret = i915_gem_init_ringbuffer(dev); | |
d816f6ac WF |
3718 | if (ret != 0) { |
3719 | mutex_unlock(&dev->struct_mutex); | |
9bb2d6f9 | 3720 | return ret; |
d816f6ac | 3721 | } |
9bb2d6f9 | 3722 | |
69dc4987 | 3723 | BUG_ON(!list_empty(&dev_priv->mm.active_list)); |
673a394b EA |
3724 | BUG_ON(!list_empty(&dev_priv->mm.flushing_list)); |
3725 | BUG_ON(!list_empty(&dev_priv->mm.inactive_list)); | |
1ec14ad3 CW |
3726 | for (i = 0; i < I915_NUM_RINGS; i++) { |
3727 | BUG_ON(!list_empty(&dev_priv->ring[i].active_list)); | |
3728 | BUG_ON(!list_empty(&dev_priv->ring[i].request_list)); | |
3729 | } | |
673a394b | 3730 | mutex_unlock(&dev->struct_mutex); |
dbb19d30 | 3731 | |
5f35308b CW |
3732 | ret = drm_irq_install(dev); |
3733 | if (ret) | |
3734 | goto cleanup_ringbuffer; | |
dbb19d30 | 3735 | |
673a394b | 3736 | return 0; |
5f35308b CW |
3737 | |
3738 | cleanup_ringbuffer: | |
3739 | mutex_lock(&dev->struct_mutex); | |
3740 | i915_gem_cleanup_ringbuffer(dev); | |
3741 | dev_priv->mm.suspended = 1; | |
3742 | mutex_unlock(&dev->struct_mutex); | |
3743 | ||
3744 | return ret; | |
673a394b EA |
3745 | } |
3746 | ||
3747 | int | |
3748 | i915_gem_leavevt_ioctl(struct drm_device *dev, void *data, | |
3749 | struct drm_file *file_priv) | |
3750 | { | |
79e53945 JB |
3751 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
3752 | return 0; | |
3753 | ||
dbb19d30 | 3754 | drm_irq_uninstall(dev); |
e6890f6f | 3755 | return i915_gem_idle(dev); |
673a394b EA |
3756 | } |
3757 | ||
3758 | void | |
3759 | i915_gem_lastclose(struct drm_device *dev) | |
3760 | { | |
3761 | int ret; | |
673a394b | 3762 | |
e806b495 EA |
3763 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
3764 | return; | |
3765 | ||
6dbe2772 KP |
3766 | ret = i915_gem_idle(dev); |
3767 | if (ret) | |
3768 | DRM_ERROR("failed to idle hardware: %d\n", ret); | |
673a394b EA |
3769 | } |
3770 | ||
64193406 CW |
3771 | static void |
3772 | init_ring_lists(struct intel_ring_buffer *ring) | |
3773 | { | |
3774 | INIT_LIST_HEAD(&ring->active_list); | |
3775 | INIT_LIST_HEAD(&ring->request_list); | |
3776 | INIT_LIST_HEAD(&ring->gpu_write_list); | |
3777 | } | |
3778 | ||
673a394b EA |
3779 | void |
3780 | i915_gem_load(struct drm_device *dev) | |
3781 | { | |
b5aa8a0f | 3782 | int i; |
673a394b EA |
3783 | drm_i915_private_t *dev_priv = dev->dev_private; |
3784 | ||
69dc4987 | 3785 | INIT_LIST_HEAD(&dev_priv->mm.active_list); |
673a394b EA |
3786 | INIT_LIST_HEAD(&dev_priv->mm.flushing_list); |
3787 | INIT_LIST_HEAD(&dev_priv->mm.inactive_list); | |
f13d3f73 | 3788 | INIT_LIST_HEAD(&dev_priv->mm.pinned_list); |
a09ba7fa | 3789 | INIT_LIST_HEAD(&dev_priv->mm.fence_list); |
be72615b | 3790 | INIT_LIST_HEAD(&dev_priv->mm.deferred_free_list); |
93a37f20 | 3791 | INIT_LIST_HEAD(&dev_priv->mm.gtt_list); |
1ec14ad3 CW |
3792 | for (i = 0; i < I915_NUM_RINGS; i++) |
3793 | init_ring_lists(&dev_priv->ring[i]); | |
007cc8ac DV |
3794 | for (i = 0; i < 16; i++) |
3795 | INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list); | |
673a394b EA |
3796 | INIT_DELAYED_WORK(&dev_priv->mm.retire_work, |
3797 | i915_gem_retire_work_handler); | |
30dbf0c0 | 3798 | init_completion(&dev_priv->error_completion); |
31169714 | 3799 | |
94400120 DA |
3800 | /* On GEN3 we really need to make sure the ARB C3 LP bit is set */ |
3801 | if (IS_GEN3(dev)) { | |
3802 | u32 tmp = I915_READ(MI_ARB_STATE); | |
3803 | if (!(tmp & MI_ARB_C3_LP_WRITE_ENABLE)) { | |
3804 | /* arb state is a masked write, so set bit + bit in mask */ | |
3805 | tmp = MI_ARB_C3_LP_WRITE_ENABLE | (MI_ARB_C3_LP_WRITE_ENABLE << MI_ARB_MASK_SHIFT); | |
3806 | I915_WRITE(MI_ARB_STATE, tmp); | |
3807 | } | |
3808 | } | |
3809 | ||
72bfa19c CW |
3810 | dev_priv->relative_constants_mode = I915_EXEC_CONSTANTS_REL_GENERAL; |
3811 | ||
de151cf6 | 3812 | /* Old X drivers will take 0-2 for front, back, depth buffers */ |
b397c836 EA |
3813 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) |
3814 | dev_priv->fence_reg_start = 3; | |
de151cf6 | 3815 | |
a6c45cf0 | 3816 | if (INTEL_INFO(dev)->gen >= 4 || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) |
de151cf6 JB |
3817 | dev_priv->num_fence_regs = 16; |
3818 | else | |
3819 | dev_priv->num_fence_regs = 8; | |
3820 | ||
b5aa8a0f | 3821 | /* Initialize fence registers to zero */ |
a6c45cf0 CW |
3822 | switch (INTEL_INFO(dev)->gen) { |
3823 | case 6: | |
3824 | for (i = 0; i < 16; i++) | |
3825 | I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + (i * 8), 0); | |
3826 | break; | |
3827 | case 5: | |
3828 | case 4: | |
b5aa8a0f GH |
3829 | for (i = 0; i < 16; i++) |
3830 | I915_WRITE64(FENCE_REG_965_0 + (i * 8), 0); | |
a6c45cf0 CW |
3831 | break; |
3832 | case 3: | |
b5aa8a0f GH |
3833 | if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) |
3834 | for (i = 0; i < 8; i++) | |
3835 | I915_WRITE(FENCE_REG_945_8 + (i * 4), 0); | |
a6c45cf0 CW |
3836 | case 2: |
3837 | for (i = 0; i < 8; i++) | |
3838 | I915_WRITE(FENCE_REG_830_0 + (i * 4), 0); | |
3839 | break; | |
b5aa8a0f | 3840 | } |
673a394b | 3841 | i915_gem_detect_bit_6_swizzle(dev); |
6b95a207 | 3842 | init_waitqueue_head(&dev_priv->pending_flip_queue); |
17250b71 CW |
3843 | |
3844 | dev_priv->mm.inactive_shrinker.shrink = i915_gem_inactive_shrink; | |
3845 | dev_priv->mm.inactive_shrinker.seeks = DEFAULT_SEEKS; | |
3846 | register_shrinker(&dev_priv->mm.inactive_shrinker); | |
673a394b | 3847 | } |
71acb5eb DA |
3848 | |
3849 | /* | |
3850 | * Create a physically contiguous memory object for this object | |
3851 | * e.g. for cursor + overlay regs | |
3852 | */ | |
995b6762 CW |
3853 | static int i915_gem_init_phys_object(struct drm_device *dev, |
3854 | int id, int size, int align) | |
71acb5eb DA |
3855 | { |
3856 | drm_i915_private_t *dev_priv = dev->dev_private; | |
3857 | struct drm_i915_gem_phys_object *phys_obj; | |
3858 | int ret; | |
3859 | ||
3860 | if (dev_priv->mm.phys_objs[id - 1] || !size) | |
3861 | return 0; | |
3862 | ||
9a298b2a | 3863 | phys_obj = kzalloc(sizeof(struct drm_i915_gem_phys_object), GFP_KERNEL); |
71acb5eb DA |
3864 | if (!phys_obj) |
3865 | return -ENOMEM; | |
3866 | ||
3867 | phys_obj->id = id; | |
3868 | ||
6eeefaf3 | 3869 | phys_obj->handle = drm_pci_alloc(dev, size, align); |
71acb5eb DA |
3870 | if (!phys_obj->handle) { |
3871 | ret = -ENOMEM; | |
3872 | goto kfree_obj; | |
3873 | } | |
3874 | #ifdef CONFIG_X86 | |
3875 | set_memory_wc((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE); | |
3876 | #endif | |
3877 | ||
3878 | dev_priv->mm.phys_objs[id - 1] = phys_obj; | |
3879 | ||
3880 | return 0; | |
3881 | kfree_obj: | |
9a298b2a | 3882 | kfree(phys_obj); |
71acb5eb DA |
3883 | return ret; |
3884 | } | |
3885 | ||
995b6762 | 3886 | static void i915_gem_free_phys_object(struct drm_device *dev, int id) |
71acb5eb DA |
3887 | { |
3888 | drm_i915_private_t *dev_priv = dev->dev_private; | |
3889 | struct drm_i915_gem_phys_object *phys_obj; | |
3890 | ||
3891 | if (!dev_priv->mm.phys_objs[id - 1]) | |
3892 | return; | |
3893 | ||
3894 | phys_obj = dev_priv->mm.phys_objs[id - 1]; | |
3895 | if (phys_obj->cur_obj) { | |
3896 | i915_gem_detach_phys_object(dev, phys_obj->cur_obj); | |
3897 | } | |
3898 | ||
3899 | #ifdef CONFIG_X86 | |
3900 | set_memory_wb((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE); | |
3901 | #endif | |
3902 | drm_pci_free(dev, phys_obj->handle); | |
3903 | kfree(phys_obj); | |
3904 | dev_priv->mm.phys_objs[id - 1] = NULL; | |
3905 | } | |
3906 | ||
3907 | void i915_gem_free_all_phys_object(struct drm_device *dev) | |
3908 | { | |
3909 | int i; | |
3910 | ||
260883c8 | 3911 | for (i = I915_GEM_PHYS_CURSOR_0; i <= I915_MAX_PHYS_OBJECT; i++) |
71acb5eb DA |
3912 | i915_gem_free_phys_object(dev, i); |
3913 | } | |
3914 | ||
3915 | void i915_gem_detach_phys_object(struct drm_device *dev, | |
05394f39 | 3916 | struct drm_i915_gem_object *obj) |
71acb5eb | 3917 | { |
05394f39 | 3918 | struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping; |
e5281ccd | 3919 | char *vaddr; |
71acb5eb | 3920 | int i; |
71acb5eb DA |
3921 | int page_count; |
3922 | ||
05394f39 | 3923 | if (!obj->phys_obj) |
71acb5eb | 3924 | return; |
05394f39 | 3925 | vaddr = obj->phys_obj->handle->vaddr; |
71acb5eb | 3926 | |
05394f39 | 3927 | page_count = obj->base.size / PAGE_SIZE; |
71acb5eb | 3928 | for (i = 0; i < page_count; i++) { |
e5281ccd CW |
3929 | struct page *page = read_cache_page_gfp(mapping, i, |
3930 | GFP_HIGHUSER | __GFP_RECLAIMABLE); | |
3931 | if (!IS_ERR(page)) { | |
3932 | char *dst = kmap_atomic(page); | |
3933 | memcpy(dst, vaddr + i*PAGE_SIZE, PAGE_SIZE); | |
3934 | kunmap_atomic(dst); | |
3935 | ||
3936 | drm_clflush_pages(&page, 1); | |
3937 | ||
3938 | set_page_dirty(page); | |
3939 | mark_page_accessed(page); | |
3940 | page_cache_release(page); | |
3941 | } | |
71acb5eb | 3942 | } |
40ce6575 | 3943 | intel_gtt_chipset_flush(); |
d78b47b9 | 3944 | |
05394f39 CW |
3945 | obj->phys_obj->cur_obj = NULL; |
3946 | obj->phys_obj = NULL; | |
71acb5eb DA |
3947 | } |
3948 | ||
3949 | int | |
3950 | i915_gem_attach_phys_object(struct drm_device *dev, | |
05394f39 | 3951 | struct drm_i915_gem_object *obj, |
6eeefaf3 CW |
3952 | int id, |
3953 | int align) | |
71acb5eb | 3954 | { |
05394f39 | 3955 | struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping; |
71acb5eb | 3956 | drm_i915_private_t *dev_priv = dev->dev_private; |
71acb5eb DA |
3957 | int ret = 0; |
3958 | int page_count; | |
3959 | int i; | |
3960 | ||
3961 | if (id > I915_MAX_PHYS_OBJECT) | |
3962 | return -EINVAL; | |
3963 | ||
05394f39 CW |
3964 | if (obj->phys_obj) { |
3965 | if (obj->phys_obj->id == id) | |
71acb5eb DA |
3966 | return 0; |
3967 | i915_gem_detach_phys_object(dev, obj); | |
3968 | } | |
3969 | ||
71acb5eb DA |
3970 | /* create a new object */ |
3971 | if (!dev_priv->mm.phys_objs[id - 1]) { | |
3972 | ret = i915_gem_init_phys_object(dev, id, | |
05394f39 | 3973 | obj->base.size, align); |
71acb5eb | 3974 | if (ret) { |
05394f39 CW |
3975 | DRM_ERROR("failed to init phys object %d size: %zu\n", |
3976 | id, obj->base.size); | |
e5281ccd | 3977 | return ret; |
71acb5eb DA |
3978 | } |
3979 | } | |
3980 | ||
3981 | /* bind to the object */ | |
05394f39 CW |
3982 | obj->phys_obj = dev_priv->mm.phys_objs[id - 1]; |
3983 | obj->phys_obj->cur_obj = obj; | |
71acb5eb | 3984 | |
05394f39 | 3985 | page_count = obj->base.size / PAGE_SIZE; |
71acb5eb DA |
3986 | |
3987 | for (i = 0; i < page_count; i++) { | |
e5281ccd CW |
3988 | struct page *page; |
3989 | char *dst, *src; | |
3990 | ||
3991 | page = read_cache_page_gfp(mapping, i, | |
3992 | GFP_HIGHUSER | __GFP_RECLAIMABLE); | |
3993 | if (IS_ERR(page)) | |
3994 | return PTR_ERR(page); | |
71acb5eb | 3995 | |
ff75b9bc | 3996 | src = kmap_atomic(page); |
05394f39 | 3997 | dst = obj->phys_obj->handle->vaddr + (i * PAGE_SIZE); |
71acb5eb | 3998 | memcpy(dst, src, PAGE_SIZE); |
3e4d3af5 | 3999 | kunmap_atomic(src); |
71acb5eb | 4000 | |
e5281ccd CW |
4001 | mark_page_accessed(page); |
4002 | page_cache_release(page); | |
4003 | } | |
d78b47b9 | 4004 | |
71acb5eb | 4005 | return 0; |
71acb5eb DA |
4006 | } |
4007 | ||
4008 | static int | |
05394f39 CW |
4009 | i915_gem_phys_pwrite(struct drm_device *dev, |
4010 | struct drm_i915_gem_object *obj, | |
71acb5eb DA |
4011 | struct drm_i915_gem_pwrite *args, |
4012 | struct drm_file *file_priv) | |
4013 | { | |
05394f39 | 4014 | void *vaddr = obj->phys_obj->handle->vaddr + args->offset; |
b47b30cc | 4015 | char __user *user_data = (char __user *) (uintptr_t) args->data_ptr; |
71acb5eb | 4016 | |
b47b30cc CW |
4017 | if (__copy_from_user_inatomic_nocache(vaddr, user_data, args->size)) { |
4018 | unsigned long unwritten; | |
4019 | ||
4020 | /* The physical object once assigned is fixed for the lifetime | |
4021 | * of the obj, so we can safely drop the lock and continue | |
4022 | * to access vaddr. | |
4023 | */ | |
4024 | mutex_unlock(&dev->struct_mutex); | |
4025 | unwritten = copy_from_user(vaddr, user_data, args->size); | |
4026 | mutex_lock(&dev->struct_mutex); | |
4027 | if (unwritten) | |
4028 | return -EFAULT; | |
4029 | } | |
71acb5eb | 4030 | |
40ce6575 | 4031 | intel_gtt_chipset_flush(); |
71acb5eb DA |
4032 | return 0; |
4033 | } | |
b962442e | 4034 | |
f787a5f5 | 4035 | void i915_gem_release(struct drm_device *dev, struct drm_file *file) |
b962442e | 4036 | { |
f787a5f5 | 4037 | struct drm_i915_file_private *file_priv = file->driver_priv; |
b962442e EA |
4038 | |
4039 | /* Clean up our request list when the client is going away, so that | |
4040 | * later retire_requests won't dereference our soon-to-be-gone | |
4041 | * file_priv. | |
4042 | */ | |
1c25595f | 4043 | spin_lock(&file_priv->mm.lock); |
f787a5f5 CW |
4044 | while (!list_empty(&file_priv->mm.request_list)) { |
4045 | struct drm_i915_gem_request *request; | |
4046 | ||
4047 | request = list_first_entry(&file_priv->mm.request_list, | |
4048 | struct drm_i915_gem_request, | |
4049 | client_list); | |
4050 | list_del(&request->client_list); | |
4051 | request->file_priv = NULL; | |
4052 | } | |
1c25595f | 4053 | spin_unlock(&file_priv->mm.lock); |
b962442e | 4054 | } |
31169714 | 4055 | |
1637ef41 CW |
4056 | static int |
4057 | i915_gpu_is_active(struct drm_device *dev) | |
4058 | { | |
4059 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4060 | int lists_empty; | |
4061 | ||
1637ef41 | 4062 | lists_empty = list_empty(&dev_priv->mm.flushing_list) && |
17250b71 | 4063 | list_empty(&dev_priv->mm.active_list); |
1637ef41 CW |
4064 | |
4065 | return !lists_empty; | |
4066 | } | |
4067 | ||
31169714 | 4068 | static int |
17250b71 CW |
4069 | i915_gem_inactive_shrink(struct shrinker *shrinker, |
4070 | int nr_to_scan, | |
4071 | gfp_t gfp_mask) | |
31169714 | 4072 | { |
17250b71 CW |
4073 | struct drm_i915_private *dev_priv = |
4074 | container_of(shrinker, | |
4075 | struct drm_i915_private, | |
4076 | mm.inactive_shrinker); | |
4077 | struct drm_device *dev = dev_priv->dev; | |
4078 | struct drm_i915_gem_object *obj, *next; | |
4079 | int cnt; | |
4080 | ||
4081 | if (!mutex_trylock(&dev->struct_mutex)) | |
bbe2e11a | 4082 | return 0; |
31169714 CW |
4083 | |
4084 | /* "fast-path" to count number of available objects */ | |
4085 | if (nr_to_scan == 0) { | |
17250b71 CW |
4086 | cnt = 0; |
4087 | list_for_each_entry(obj, | |
4088 | &dev_priv->mm.inactive_list, | |
4089 | mm_list) | |
4090 | cnt++; | |
4091 | mutex_unlock(&dev->struct_mutex); | |
4092 | return cnt / 100 * sysctl_vfs_cache_pressure; | |
31169714 CW |
4093 | } |
4094 | ||
1637ef41 | 4095 | rescan: |
31169714 | 4096 | /* first scan for clean buffers */ |
17250b71 | 4097 | i915_gem_retire_requests(dev); |
31169714 | 4098 | |
17250b71 CW |
4099 | list_for_each_entry_safe(obj, next, |
4100 | &dev_priv->mm.inactive_list, | |
4101 | mm_list) { | |
4102 | if (i915_gem_object_is_purgeable(obj)) { | |
2021746e CW |
4103 | if (i915_gem_object_unbind(obj) == 0 && |
4104 | --nr_to_scan == 0) | |
17250b71 | 4105 | break; |
31169714 | 4106 | } |
31169714 CW |
4107 | } |
4108 | ||
4109 | /* second pass, evict/count anything still on the inactive list */ | |
17250b71 CW |
4110 | cnt = 0; |
4111 | list_for_each_entry_safe(obj, next, | |
4112 | &dev_priv->mm.inactive_list, | |
4113 | mm_list) { | |
2021746e CW |
4114 | if (nr_to_scan && |
4115 | i915_gem_object_unbind(obj) == 0) | |
17250b71 | 4116 | nr_to_scan--; |
2021746e | 4117 | else |
17250b71 CW |
4118 | cnt++; |
4119 | } | |
4120 | ||
4121 | if (nr_to_scan && i915_gpu_is_active(dev)) { | |
1637ef41 CW |
4122 | /* |
4123 | * We are desperate for pages, so as a last resort, wait | |
4124 | * for the GPU to finish and discard whatever we can. | |
4125 | * This has a dramatic impact to reduce the number of | |
4126 | * OOM-killer events whilst running the GPU aggressively. | |
4127 | */ | |
17250b71 | 4128 | if (i915_gpu_idle(dev) == 0) |
1637ef41 CW |
4129 | goto rescan; |
4130 | } | |
17250b71 CW |
4131 | mutex_unlock(&dev->struct_mutex); |
4132 | return cnt / 100 * sysctl_vfs_cache_pressure; | |
31169714 | 4133 | } |