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54cf91dc CW |
1 | /* |
2 | * Copyright © 2008,2010 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | * Chris Wilson <chris@chris-wilson.co.uk> | |
26 | * | |
27 | */ | |
28 | ||
760285e7 DH |
29 | #include <drm/drmP.h> |
30 | #include <drm/i915_drm.h> | |
54cf91dc CW |
31 | #include "i915_drv.h" |
32 | #include "i915_trace.h" | |
33 | #include "intel_drv.h" | |
f45b5557 | 34 | #include <linux/dma_remapping.h> |
54cf91dc | 35 | |
a415d355 CW |
36 | #define __EXEC_OBJECT_HAS_PIN (1<<31) |
37 | #define __EXEC_OBJECT_HAS_FENCE (1<<30) | |
d23db88c CW |
38 | #define __EXEC_OBJECT_NEEDS_BIAS (1<<28) |
39 | ||
40 | #define BATCH_OFFSET_BIAS (256*1024) | |
a415d355 | 41 | |
27173f1f BW |
42 | struct eb_vmas { |
43 | struct list_head vmas; | |
67731b87 | 44 | int and; |
eef90ccb | 45 | union { |
27173f1f | 46 | struct i915_vma *lut[0]; |
eef90ccb CW |
47 | struct hlist_head buckets[0]; |
48 | }; | |
67731b87 CW |
49 | }; |
50 | ||
27173f1f | 51 | static struct eb_vmas * |
17601cbc | 52 | eb_create(struct drm_i915_gem_execbuffer2 *args) |
67731b87 | 53 | { |
27173f1f | 54 | struct eb_vmas *eb = NULL; |
eef90ccb CW |
55 | |
56 | if (args->flags & I915_EXEC_HANDLE_LUT) { | |
b205ca57 | 57 | unsigned size = args->buffer_count; |
27173f1f BW |
58 | size *= sizeof(struct i915_vma *); |
59 | size += sizeof(struct eb_vmas); | |
eef90ccb CW |
60 | eb = kmalloc(size, GFP_TEMPORARY | __GFP_NOWARN | __GFP_NORETRY); |
61 | } | |
62 | ||
63 | if (eb == NULL) { | |
b205ca57 DV |
64 | unsigned size = args->buffer_count; |
65 | unsigned count = PAGE_SIZE / sizeof(struct hlist_head) / 2; | |
27b7c63a | 66 | BUILD_BUG_ON_NOT_POWER_OF_2(PAGE_SIZE / sizeof(struct hlist_head)); |
eef90ccb CW |
67 | while (count > 2*size) |
68 | count >>= 1; | |
69 | eb = kzalloc(count*sizeof(struct hlist_head) + | |
27173f1f | 70 | sizeof(struct eb_vmas), |
eef90ccb CW |
71 | GFP_TEMPORARY); |
72 | if (eb == NULL) | |
73 | return eb; | |
74 | ||
75 | eb->and = count - 1; | |
76 | } else | |
77 | eb->and = -args->buffer_count; | |
78 | ||
27173f1f | 79 | INIT_LIST_HEAD(&eb->vmas); |
67731b87 CW |
80 | return eb; |
81 | } | |
82 | ||
83 | static void | |
27173f1f | 84 | eb_reset(struct eb_vmas *eb) |
67731b87 | 85 | { |
eef90ccb CW |
86 | if (eb->and >= 0) |
87 | memset(eb->buckets, 0, (eb->and+1)*sizeof(struct hlist_head)); | |
67731b87 CW |
88 | } |
89 | ||
3b96eff4 | 90 | static int |
27173f1f BW |
91 | eb_lookup_vmas(struct eb_vmas *eb, |
92 | struct drm_i915_gem_exec_object2 *exec, | |
93 | const struct drm_i915_gem_execbuffer2 *args, | |
94 | struct i915_address_space *vm, | |
95 | struct drm_file *file) | |
3b96eff4 | 96 | { |
6f65e29a | 97 | struct drm_i915_private *dev_priv = vm->dev->dev_private; |
27173f1f BW |
98 | struct drm_i915_gem_object *obj; |
99 | struct list_head objects; | |
9ae9ab52 | 100 | int i, ret; |
3b96eff4 | 101 | |
27173f1f | 102 | INIT_LIST_HEAD(&objects); |
3b96eff4 | 103 | spin_lock(&file->table_lock); |
27173f1f BW |
104 | /* Grab a reference to the object and release the lock so we can lookup |
105 | * or create the VMA without using GFP_ATOMIC */ | |
eef90ccb | 106 | for (i = 0; i < args->buffer_count; i++) { |
3b96eff4 CW |
107 | obj = to_intel_bo(idr_find(&file->object_idr, exec[i].handle)); |
108 | if (obj == NULL) { | |
109 | spin_unlock(&file->table_lock); | |
110 | DRM_DEBUG("Invalid object handle %d at index %d\n", | |
111 | exec[i].handle, i); | |
27173f1f | 112 | ret = -ENOENT; |
9ae9ab52 | 113 | goto err; |
3b96eff4 CW |
114 | } |
115 | ||
27173f1f | 116 | if (!list_empty(&obj->obj_exec_link)) { |
3b96eff4 CW |
117 | spin_unlock(&file->table_lock); |
118 | DRM_DEBUG("Object %p [handle %d, index %d] appears more than once in object list\n", | |
119 | obj, exec[i].handle, i); | |
27173f1f | 120 | ret = -EINVAL; |
9ae9ab52 | 121 | goto err; |
3b96eff4 CW |
122 | } |
123 | ||
124 | drm_gem_object_reference(&obj->base); | |
27173f1f BW |
125 | list_add_tail(&obj->obj_exec_link, &objects); |
126 | } | |
127 | spin_unlock(&file->table_lock); | |
3b96eff4 | 128 | |
27173f1f | 129 | i = 0; |
9ae9ab52 | 130 | while (!list_empty(&objects)) { |
27173f1f | 131 | struct i915_vma *vma; |
6f65e29a BW |
132 | struct i915_address_space *bind_vm = vm; |
133 | ||
2c9f8d56 DV |
134 | if (exec[i].flags & EXEC_OBJECT_NEEDS_GTT && |
135 | USES_FULL_PPGTT(vm->dev)) { | |
136 | ret = -EINVAL; | |
a25eebb0 | 137 | goto err; |
2c9f8d56 DV |
138 | } |
139 | ||
6f65e29a BW |
140 | /* If we have secure dispatch, or the userspace assures us that |
141 | * they know what they're doing, use the GGTT VM. | |
142 | */ | |
a7c1d426 | 143 | if (((args->flags & I915_EXEC_SECURE) && |
6f65e29a BW |
144 | (i == (args->buffer_count - 1)))) |
145 | bind_vm = &dev_priv->gtt.base; | |
27173f1f | 146 | |
9ae9ab52 CW |
147 | obj = list_first_entry(&objects, |
148 | struct drm_i915_gem_object, | |
149 | obj_exec_link); | |
150 | ||
e656a6cb DV |
151 | /* |
152 | * NOTE: We can leak any vmas created here when something fails | |
153 | * later on. But that's no issue since vma_unbind can deal with | |
154 | * vmas which are not actually bound. And since only | |
155 | * lookup_or_create exists as an interface to get at the vma | |
156 | * from the (obj, vm) we don't run the risk of creating | |
157 | * duplicated vmas for the same vm. | |
158 | */ | |
6f65e29a | 159 | vma = i915_gem_obj_lookup_or_create_vma(obj, bind_vm); |
27173f1f | 160 | if (IS_ERR(vma)) { |
27173f1f BW |
161 | DRM_DEBUG("Failed to lookup VMA\n"); |
162 | ret = PTR_ERR(vma); | |
9ae9ab52 | 163 | goto err; |
27173f1f BW |
164 | } |
165 | ||
9ae9ab52 | 166 | /* Transfer ownership from the objects list to the vmas list. */ |
27173f1f | 167 | list_add_tail(&vma->exec_list, &eb->vmas); |
9ae9ab52 | 168 | list_del_init(&obj->obj_exec_link); |
27173f1f BW |
169 | |
170 | vma->exec_entry = &exec[i]; | |
eef90ccb | 171 | if (eb->and < 0) { |
27173f1f | 172 | eb->lut[i] = vma; |
eef90ccb CW |
173 | } else { |
174 | uint32_t handle = args->flags & I915_EXEC_HANDLE_LUT ? i : exec[i].handle; | |
27173f1f BW |
175 | vma->exec_handle = handle; |
176 | hlist_add_head(&vma->exec_node, | |
eef90ccb CW |
177 | &eb->buckets[handle & eb->and]); |
178 | } | |
27173f1f | 179 | ++i; |
3b96eff4 | 180 | } |
3b96eff4 | 181 | |
9ae9ab52 | 182 | return 0; |
27173f1f | 183 | |
27173f1f | 184 | |
9ae9ab52 | 185 | err: |
27173f1f BW |
186 | while (!list_empty(&objects)) { |
187 | obj = list_first_entry(&objects, | |
188 | struct drm_i915_gem_object, | |
189 | obj_exec_link); | |
190 | list_del_init(&obj->obj_exec_link); | |
9ae9ab52 | 191 | drm_gem_object_unreference(&obj->base); |
27173f1f | 192 | } |
9ae9ab52 CW |
193 | /* |
194 | * Objects already transfered to the vmas list will be unreferenced by | |
195 | * eb_destroy. | |
196 | */ | |
197 | ||
27173f1f | 198 | return ret; |
3b96eff4 CW |
199 | } |
200 | ||
27173f1f | 201 | static struct i915_vma *eb_get_vma(struct eb_vmas *eb, unsigned long handle) |
67731b87 | 202 | { |
eef90ccb CW |
203 | if (eb->and < 0) { |
204 | if (handle >= -eb->and) | |
205 | return NULL; | |
206 | return eb->lut[handle]; | |
207 | } else { | |
208 | struct hlist_head *head; | |
209 | struct hlist_node *node; | |
67731b87 | 210 | |
eef90ccb CW |
211 | head = &eb->buckets[handle & eb->and]; |
212 | hlist_for_each(node, head) { | |
27173f1f | 213 | struct i915_vma *vma; |
67731b87 | 214 | |
27173f1f BW |
215 | vma = hlist_entry(node, struct i915_vma, exec_node); |
216 | if (vma->exec_handle == handle) | |
217 | return vma; | |
eef90ccb CW |
218 | } |
219 | return NULL; | |
220 | } | |
67731b87 CW |
221 | } |
222 | ||
a415d355 CW |
223 | static void |
224 | i915_gem_execbuffer_unreserve_vma(struct i915_vma *vma) | |
225 | { | |
226 | struct drm_i915_gem_exec_object2 *entry; | |
227 | struct drm_i915_gem_object *obj = vma->obj; | |
228 | ||
229 | if (!drm_mm_node_allocated(&vma->node)) | |
230 | return; | |
231 | ||
232 | entry = vma->exec_entry; | |
233 | ||
234 | if (entry->flags & __EXEC_OBJECT_HAS_FENCE) | |
235 | i915_gem_object_unpin_fence(obj); | |
236 | ||
237 | if (entry->flags & __EXEC_OBJECT_HAS_PIN) | |
3d7f0f9d | 238 | vma->pin_count--; |
a415d355 CW |
239 | |
240 | entry->flags &= ~(__EXEC_OBJECT_HAS_FENCE | __EXEC_OBJECT_HAS_PIN); | |
241 | } | |
242 | ||
243 | static void eb_destroy(struct eb_vmas *eb) | |
244 | { | |
27173f1f BW |
245 | while (!list_empty(&eb->vmas)) { |
246 | struct i915_vma *vma; | |
bcffc3fa | 247 | |
27173f1f BW |
248 | vma = list_first_entry(&eb->vmas, |
249 | struct i915_vma, | |
bcffc3fa | 250 | exec_list); |
27173f1f | 251 | list_del_init(&vma->exec_list); |
a415d355 | 252 | i915_gem_execbuffer_unreserve_vma(vma); |
27173f1f | 253 | drm_gem_object_unreference(&vma->obj->base); |
bcffc3fa | 254 | } |
67731b87 CW |
255 | kfree(eb); |
256 | } | |
257 | ||
dabdfe02 CW |
258 | static inline int use_cpu_reloc(struct drm_i915_gem_object *obj) |
259 | { | |
2cc86b82 CW |
260 | return (HAS_LLC(obj->base.dev) || |
261 | obj->base.write_domain == I915_GEM_DOMAIN_CPU || | |
504c7267 | 262 | !obj->map_and_fenceable || |
dabdfe02 CW |
263 | obj->cache_level != I915_CACHE_NONE); |
264 | } | |
265 | ||
5032d871 RB |
266 | static int |
267 | relocate_entry_cpu(struct drm_i915_gem_object *obj, | |
d9ceb957 BW |
268 | struct drm_i915_gem_relocation_entry *reloc, |
269 | uint64_t target_offset) | |
5032d871 | 270 | { |
3c94ceee | 271 | struct drm_device *dev = obj->base.dev; |
5032d871 | 272 | uint32_t page_offset = offset_in_page(reloc->offset); |
d9ceb957 | 273 | uint64_t delta = reloc->delta + target_offset; |
5032d871 | 274 | char *vaddr; |
8b78f0e5 | 275 | int ret; |
5032d871 | 276 | |
2cc86b82 | 277 | ret = i915_gem_object_set_to_cpu_domain(obj, true); |
5032d871 RB |
278 | if (ret) |
279 | return ret; | |
280 | ||
281 | vaddr = kmap_atomic(i915_gem_object_get_page(obj, | |
282 | reloc->offset >> PAGE_SHIFT)); | |
d9ceb957 | 283 | *(uint32_t *)(vaddr + page_offset) = lower_32_bits(delta); |
3c94ceee BW |
284 | |
285 | if (INTEL_INFO(dev)->gen >= 8) { | |
286 | page_offset = offset_in_page(page_offset + sizeof(uint32_t)); | |
287 | ||
288 | if (page_offset == 0) { | |
289 | kunmap_atomic(vaddr); | |
290 | vaddr = kmap_atomic(i915_gem_object_get_page(obj, | |
291 | (reloc->offset + sizeof(uint32_t)) >> PAGE_SHIFT)); | |
292 | } | |
293 | ||
d9ceb957 | 294 | *(uint32_t *)(vaddr + page_offset) = upper_32_bits(delta); |
3c94ceee BW |
295 | } |
296 | ||
5032d871 RB |
297 | kunmap_atomic(vaddr); |
298 | ||
299 | return 0; | |
300 | } | |
301 | ||
302 | static int | |
303 | relocate_entry_gtt(struct drm_i915_gem_object *obj, | |
d9ceb957 BW |
304 | struct drm_i915_gem_relocation_entry *reloc, |
305 | uint64_t target_offset) | |
5032d871 RB |
306 | { |
307 | struct drm_device *dev = obj->base.dev; | |
308 | struct drm_i915_private *dev_priv = dev->dev_private; | |
d9ceb957 | 309 | uint64_t delta = reloc->delta + target_offset; |
5032d871 RB |
310 | uint32_t __iomem *reloc_entry; |
311 | void __iomem *reloc_page; | |
8b78f0e5 | 312 | int ret; |
5032d871 RB |
313 | |
314 | ret = i915_gem_object_set_to_gtt_domain(obj, true); | |
315 | if (ret) | |
316 | return ret; | |
317 | ||
318 | ret = i915_gem_object_put_fence(obj); | |
319 | if (ret) | |
320 | return ret; | |
321 | ||
322 | /* Map the page containing the relocation we're going to perform. */ | |
323 | reloc->offset += i915_gem_obj_ggtt_offset(obj); | |
324 | reloc_page = io_mapping_map_atomic_wc(dev_priv->gtt.mappable, | |
325 | reloc->offset & PAGE_MASK); | |
326 | reloc_entry = (uint32_t __iomem *) | |
327 | (reloc_page + offset_in_page(reloc->offset)); | |
d9ceb957 | 328 | iowrite32(lower_32_bits(delta), reloc_entry); |
3c94ceee BW |
329 | |
330 | if (INTEL_INFO(dev)->gen >= 8) { | |
331 | reloc_entry += 1; | |
332 | ||
333 | if (offset_in_page(reloc->offset + sizeof(uint32_t)) == 0) { | |
334 | io_mapping_unmap_atomic(reloc_page); | |
335 | reloc_page = io_mapping_map_atomic_wc( | |
336 | dev_priv->gtt.mappable, | |
337 | reloc->offset + sizeof(uint32_t)); | |
338 | reloc_entry = reloc_page; | |
339 | } | |
340 | ||
d9ceb957 | 341 | iowrite32(upper_32_bits(delta), reloc_entry); |
3c94ceee BW |
342 | } |
343 | ||
5032d871 RB |
344 | io_mapping_unmap_atomic(reloc_page); |
345 | ||
346 | return 0; | |
347 | } | |
348 | ||
54cf91dc CW |
349 | static int |
350 | i915_gem_execbuffer_relocate_entry(struct drm_i915_gem_object *obj, | |
27173f1f | 351 | struct eb_vmas *eb, |
3e7a0322 | 352 | struct drm_i915_gem_relocation_entry *reloc) |
54cf91dc CW |
353 | { |
354 | struct drm_device *dev = obj->base.dev; | |
355 | struct drm_gem_object *target_obj; | |
149c8407 | 356 | struct drm_i915_gem_object *target_i915_obj; |
27173f1f | 357 | struct i915_vma *target_vma; |
d9ceb957 | 358 | uint64_t target_offset; |
8b78f0e5 | 359 | int ret; |
54cf91dc | 360 | |
67731b87 | 361 | /* we've already hold a reference to all valid objects */ |
27173f1f BW |
362 | target_vma = eb_get_vma(eb, reloc->target_handle); |
363 | if (unlikely(target_vma == NULL)) | |
54cf91dc | 364 | return -ENOENT; |
27173f1f BW |
365 | target_i915_obj = target_vma->obj; |
366 | target_obj = &target_vma->obj->base; | |
54cf91dc | 367 | |
5ce09725 | 368 | target_offset = target_vma->node.start; |
54cf91dc | 369 | |
e844b990 EA |
370 | /* Sandybridge PPGTT errata: We need a global gtt mapping for MI and |
371 | * pipe_control writes because the gpu doesn't properly redirect them | |
372 | * through the ppgtt for non_secure batchbuffers. */ | |
373 | if (unlikely(IS_GEN6(dev) && | |
374 | reloc->write_domain == I915_GEM_DOMAIN_INSTRUCTION && | |
375 | !target_i915_obj->has_global_gtt_mapping)) { | |
3e7a0322 BW |
376 | struct i915_vma *vma = |
377 | list_first_entry(&target_i915_obj->vma_list, | |
378 | typeof(*vma), vma_link); | |
6f65e29a | 379 | vma->bind_vma(vma, target_i915_obj->cache_level, GLOBAL_BIND); |
e844b990 EA |
380 | } |
381 | ||
54cf91dc | 382 | /* Validate that the target is in a valid r/w GPU domain */ |
b8f7ab17 | 383 | if (unlikely(reloc->write_domain & (reloc->write_domain - 1))) { |
ff240199 | 384 | DRM_DEBUG("reloc with multiple write domains: " |
54cf91dc CW |
385 | "obj %p target %d offset %d " |
386 | "read %08x write %08x", | |
387 | obj, reloc->target_handle, | |
388 | (int) reloc->offset, | |
389 | reloc->read_domains, | |
390 | reloc->write_domain); | |
8b78f0e5 | 391 | return -EINVAL; |
54cf91dc | 392 | } |
4ca4a250 DV |
393 | if (unlikely((reloc->write_domain | reloc->read_domains) |
394 | & ~I915_GEM_GPU_DOMAINS)) { | |
ff240199 | 395 | DRM_DEBUG("reloc with read/write non-GPU domains: " |
54cf91dc CW |
396 | "obj %p target %d offset %d " |
397 | "read %08x write %08x", | |
398 | obj, reloc->target_handle, | |
399 | (int) reloc->offset, | |
400 | reloc->read_domains, | |
401 | reloc->write_domain); | |
8b78f0e5 | 402 | return -EINVAL; |
54cf91dc | 403 | } |
54cf91dc CW |
404 | |
405 | target_obj->pending_read_domains |= reloc->read_domains; | |
406 | target_obj->pending_write_domain |= reloc->write_domain; | |
407 | ||
408 | /* If the relocation already has the right value in it, no | |
409 | * more work needs to be done. | |
410 | */ | |
411 | if (target_offset == reloc->presumed_offset) | |
67731b87 | 412 | return 0; |
54cf91dc CW |
413 | |
414 | /* Check that the relocation address is valid... */ | |
3c94ceee BW |
415 | if (unlikely(reloc->offset > |
416 | obj->base.size - (INTEL_INFO(dev)->gen >= 8 ? 8 : 4))) { | |
ff240199 | 417 | DRM_DEBUG("Relocation beyond object bounds: " |
54cf91dc CW |
418 | "obj %p target %d offset %d size %d.\n", |
419 | obj, reloc->target_handle, | |
420 | (int) reloc->offset, | |
421 | (int) obj->base.size); | |
8b78f0e5 | 422 | return -EINVAL; |
54cf91dc | 423 | } |
b8f7ab17 | 424 | if (unlikely(reloc->offset & 3)) { |
ff240199 | 425 | DRM_DEBUG("Relocation not 4-byte aligned: " |
54cf91dc CW |
426 | "obj %p target %d offset %d.\n", |
427 | obj, reloc->target_handle, | |
428 | (int) reloc->offset); | |
8b78f0e5 | 429 | return -EINVAL; |
54cf91dc CW |
430 | } |
431 | ||
dabdfe02 CW |
432 | /* We can't wait for rendering with pagefaults disabled */ |
433 | if (obj->active && in_atomic()) | |
434 | return -EFAULT; | |
435 | ||
5032d871 | 436 | if (use_cpu_reloc(obj)) |
d9ceb957 | 437 | ret = relocate_entry_cpu(obj, reloc, target_offset); |
5032d871 | 438 | else |
d9ceb957 | 439 | ret = relocate_entry_gtt(obj, reloc, target_offset); |
54cf91dc | 440 | |
d4d36014 DV |
441 | if (ret) |
442 | return ret; | |
443 | ||
54cf91dc CW |
444 | /* and update the user's relocation entry */ |
445 | reloc->presumed_offset = target_offset; | |
446 | ||
67731b87 | 447 | return 0; |
54cf91dc CW |
448 | } |
449 | ||
450 | static int | |
27173f1f BW |
451 | i915_gem_execbuffer_relocate_vma(struct i915_vma *vma, |
452 | struct eb_vmas *eb) | |
54cf91dc | 453 | { |
1d83f442 CW |
454 | #define N_RELOC(x) ((x) / sizeof(struct drm_i915_gem_relocation_entry)) |
455 | struct drm_i915_gem_relocation_entry stack_reloc[N_RELOC(512)]; | |
54cf91dc | 456 | struct drm_i915_gem_relocation_entry __user *user_relocs; |
27173f1f | 457 | struct drm_i915_gem_exec_object2 *entry = vma->exec_entry; |
1d83f442 | 458 | int remain, ret; |
54cf91dc | 459 | |
2bb4629a | 460 | user_relocs = to_user_ptr(entry->relocs_ptr); |
54cf91dc | 461 | |
1d83f442 CW |
462 | remain = entry->relocation_count; |
463 | while (remain) { | |
464 | struct drm_i915_gem_relocation_entry *r = stack_reloc; | |
465 | int count = remain; | |
466 | if (count > ARRAY_SIZE(stack_reloc)) | |
467 | count = ARRAY_SIZE(stack_reloc); | |
468 | remain -= count; | |
469 | ||
470 | if (__copy_from_user_inatomic(r, user_relocs, count*sizeof(r[0]))) | |
54cf91dc CW |
471 | return -EFAULT; |
472 | ||
1d83f442 CW |
473 | do { |
474 | u64 offset = r->presumed_offset; | |
54cf91dc | 475 | |
3e7a0322 | 476 | ret = i915_gem_execbuffer_relocate_entry(vma->obj, eb, r); |
1d83f442 CW |
477 | if (ret) |
478 | return ret; | |
479 | ||
480 | if (r->presumed_offset != offset && | |
481 | __copy_to_user_inatomic(&user_relocs->presumed_offset, | |
482 | &r->presumed_offset, | |
483 | sizeof(r->presumed_offset))) { | |
484 | return -EFAULT; | |
485 | } | |
486 | ||
487 | user_relocs++; | |
488 | r++; | |
489 | } while (--count); | |
54cf91dc CW |
490 | } |
491 | ||
492 | return 0; | |
1d83f442 | 493 | #undef N_RELOC |
54cf91dc CW |
494 | } |
495 | ||
496 | static int | |
27173f1f BW |
497 | i915_gem_execbuffer_relocate_vma_slow(struct i915_vma *vma, |
498 | struct eb_vmas *eb, | |
499 | struct drm_i915_gem_relocation_entry *relocs) | |
54cf91dc | 500 | { |
27173f1f | 501 | const struct drm_i915_gem_exec_object2 *entry = vma->exec_entry; |
54cf91dc CW |
502 | int i, ret; |
503 | ||
504 | for (i = 0; i < entry->relocation_count; i++) { | |
3e7a0322 | 505 | ret = i915_gem_execbuffer_relocate_entry(vma->obj, eb, &relocs[i]); |
54cf91dc CW |
506 | if (ret) |
507 | return ret; | |
508 | } | |
509 | ||
510 | return 0; | |
511 | } | |
512 | ||
513 | static int | |
17601cbc | 514 | i915_gem_execbuffer_relocate(struct eb_vmas *eb) |
54cf91dc | 515 | { |
27173f1f | 516 | struct i915_vma *vma; |
d4aeee77 CW |
517 | int ret = 0; |
518 | ||
519 | /* This is the fast path and we cannot handle a pagefault whilst | |
520 | * holding the struct mutex lest the user pass in the relocations | |
521 | * contained within a mmaped bo. For in such a case we, the page | |
522 | * fault handler would call i915_gem_fault() and we would try to | |
523 | * acquire the struct mutex again. Obviously this is bad and so | |
524 | * lockdep complains vehemently. | |
525 | */ | |
526 | pagefault_disable(); | |
27173f1f BW |
527 | list_for_each_entry(vma, &eb->vmas, exec_list) { |
528 | ret = i915_gem_execbuffer_relocate_vma(vma, eb); | |
54cf91dc | 529 | if (ret) |
d4aeee77 | 530 | break; |
54cf91dc | 531 | } |
d4aeee77 | 532 | pagefault_enable(); |
54cf91dc | 533 | |
d4aeee77 | 534 | return ret; |
54cf91dc CW |
535 | } |
536 | ||
dabdfe02 | 537 | static int |
27173f1f | 538 | need_reloc_mappable(struct i915_vma *vma) |
dabdfe02 | 539 | { |
27173f1f BW |
540 | struct drm_i915_gem_exec_object2 *entry = vma->exec_entry; |
541 | return entry->relocation_count && !use_cpu_reloc(vma->obj) && | |
542 | i915_is_ggtt(vma->vm); | |
dabdfe02 CW |
543 | } |
544 | ||
1690e1eb | 545 | static int |
27173f1f | 546 | i915_gem_execbuffer_reserve_vma(struct i915_vma *vma, |
a4872ba6 | 547 | struct intel_engine_cs *ring, |
27173f1f | 548 | bool *need_reloc) |
1690e1eb | 549 | { |
6f65e29a | 550 | struct drm_i915_gem_object *obj = vma->obj; |
27173f1f | 551 | struct drm_i915_gem_exec_object2 *entry = vma->exec_entry; |
1690e1eb | 552 | bool has_fenced_gpu_access = INTEL_INFO(ring->dev)->gen < 4; |
1ec9e26d | 553 | bool need_fence; |
d23db88c | 554 | uint64_t flags; |
1690e1eb CW |
555 | int ret; |
556 | ||
1ec9e26d DV |
557 | flags = 0; |
558 | ||
1690e1eb CW |
559 | need_fence = |
560 | has_fenced_gpu_access && | |
561 | entry->flags & EXEC_OBJECT_NEEDS_FENCE && | |
562 | obj->tiling_mode != I915_TILING_NONE; | |
1ec9e26d DV |
563 | if (need_fence || need_reloc_mappable(vma)) |
564 | flags |= PIN_MAPPABLE; | |
1690e1eb | 565 | |
1ec9e26d | 566 | if (entry->flags & EXEC_OBJECT_NEEDS_GTT) |
bf3d149b | 567 | flags |= PIN_GLOBAL; |
d23db88c CW |
568 | if (entry->flags & __EXEC_OBJECT_NEEDS_BIAS) |
569 | flags |= BATCH_OFFSET_BIAS | PIN_OFFSET_BIAS; | |
1ec9e26d DV |
570 | |
571 | ret = i915_gem_object_pin(obj, vma->vm, entry->alignment, flags); | |
1690e1eb CW |
572 | if (ret) |
573 | return ret; | |
574 | ||
7788a765 CW |
575 | entry->flags |= __EXEC_OBJECT_HAS_PIN; |
576 | ||
1690e1eb CW |
577 | if (has_fenced_gpu_access) { |
578 | if (entry->flags & EXEC_OBJECT_NEEDS_FENCE) { | |
06d98131 | 579 | ret = i915_gem_object_get_fence(obj); |
9a5a53b3 | 580 | if (ret) |
7788a765 | 581 | return ret; |
1690e1eb | 582 | |
9a5a53b3 | 583 | if (i915_gem_object_pin_fence(obj)) |
1690e1eb | 584 | entry->flags |= __EXEC_OBJECT_HAS_FENCE; |
9a5a53b3 | 585 | |
7dd49065 | 586 | obj->pending_fenced_gpu_access = true; |
1690e1eb | 587 | } |
1690e1eb CW |
588 | } |
589 | ||
27173f1f BW |
590 | if (entry->offset != vma->node.start) { |
591 | entry->offset = vma->node.start; | |
ed5982e6 DV |
592 | *need_reloc = true; |
593 | } | |
594 | ||
595 | if (entry->flags & EXEC_OBJECT_WRITE) { | |
596 | obj->base.pending_read_domains = I915_GEM_DOMAIN_RENDER; | |
597 | obj->base.pending_write_domain = I915_GEM_DOMAIN_RENDER; | |
598 | } | |
599 | ||
1690e1eb | 600 | return 0; |
7788a765 | 601 | } |
1690e1eb | 602 | |
d23db88c CW |
603 | static bool |
604 | eb_vma_misplaced(struct i915_vma *vma, bool has_fenced_gpu_access) | |
605 | { | |
606 | struct drm_i915_gem_exec_object2 *entry = vma->exec_entry; | |
607 | struct drm_i915_gem_object *obj = vma->obj; | |
608 | bool need_fence, need_mappable; | |
609 | ||
610 | need_fence = | |
611 | has_fenced_gpu_access && | |
612 | entry->flags & EXEC_OBJECT_NEEDS_FENCE && | |
613 | obj->tiling_mode != I915_TILING_NONE; | |
614 | need_mappable = need_fence || need_reloc_mappable(vma); | |
615 | ||
616 | WARN_ON((need_mappable || need_fence) && | |
617 | !i915_is_ggtt(vma->vm)); | |
618 | ||
619 | if (entry->alignment && | |
620 | vma->node.start & (entry->alignment - 1)) | |
621 | return true; | |
622 | ||
623 | if (need_mappable && !obj->map_and_fenceable) | |
624 | return true; | |
625 | ||
626 | if (entry->flags & __EXEC_OBJECT_NEEDS_BIAS && | |
627 | vma->node.start < BATCH_OFFSET_BIAS) | |
628 | return true; | |
629 | ||
630 | return false; | |
631 | } | |
632 | ||
54cf91dc | 633 | static int |
a4872ba6 | 634 | i915_gem_execbuffer_reserve(struct intel_engine_cs *ring, |
27173f1f | 635 | struct list_head *vmas, |
ed5982e6 | 636 | bool *need_relocs) |
54cf91dc | 637 | { |
432e58ed | 638 | struct drm_i915_gem_object *obj; |
27173f1f | 639 | struct i915_vma *vma; |
68c8c17f | 640 | struct i915_address_space *vm; |
27173f1f | 641 | struct list_head ordered_vmas; |
7788a765 CW |
642 | bool has_fenced_gpu_access = INTEL_INFO(ring->dev)->gen < 4; |
643 | int retry; | |
6fe4f140 | 644 | |
68c8c17f BW |
645 | if (list_empty(vmas)) |
646 | return 0; | |
647 | ||
227f782e CW |
648 | i915_gem_retire_requests_ring(ring); |
649 | ||
68c8c17f BW |
650 | vm = list_first_entry(vmas, struct i915_vma, exec_list)->vm; |
651 | ||
27173f1f BW |
652 | INIT_LIST_HEAD(&ordered_vmas); |
653 | while (!list_empty(vmas)) { | |
6fe4f140 CW |
654 | struct drm_i915_gem_exec_object2 *entry; |
655 | bool need_fence, need_mappable; | |
656 | ||
27173f1f BW |
657 | vma = list_first_entry(vmas, struct i915_vma, exec_list); |
658 | obj = vma->obj; | |
659 | entry = vma->exec_entry; | |
6fe4f140 CW |
660 | |
661 | need_fence = | |
662 | has_fenced_gpu_access && | |
663 | entry->flags & EXEC_OBJECT_NEEDS_FENCE && | |
664 | obj->tiling_mode != I915_TILING_NONE; | |
27173f1f | 665 | need_mappable = need_fence || need_reloc_mappable(vma); |
6fe4f140 CW |
666 | |
667 | if (need_mappable) | |
27173f1f | 668 | list_move(&vma->exec_list, &ordered_vmas); |
6fe4f140 | 669 | else |
27173f1f | 670 | list_move_tail(&vma->exec_list, &ordered_vmas); |
595dad76 | 671 | |
ed5982e6 | 672 | obj->base.pending_read_domains = I915_GEM_GPU_DOMAINS & ~I915_GEM_DOMAIN_COMMAND; |
595dad76 | 673 | obj->base.pending_write_domain = 0; |
016fd0c1 | 674 | obj->pending_fenced_gpu_access = false; |
6fe4f140 | 675 | } |
27173f1f | 676 | list_splice(&ordered_vmas, vmas); |
54cf91dc CW |
677 | |
678 | /* Attempt to pin all of the buffers into the GTT. | |
679 | * This is done in 3 phases: | |
680 | * | |
681 | * 1a. Unbind all objects that do not match the GTT constraints for | |
682 | * the execbuffer (fenceable, mappable, alignment etc). | |
683 | * 1b. Increment pin count for already bound objects. | |
684 | * 2. Bind new objects. | |
685 | * 3. Decrement pin count. | |
686 | * | |
7788a765 | 687 | * This avoid unnecessary unbinding of later objects in order to make |
54cf91dc CW |
688 | * room for the earlier objects *unless* we need to defragment. |
689 | */ | |
690 | retry = 0; | |
691 | do { | |
7788a765 | 692 | int ret = 0; |
54cf91dc CW |
693 | |
694 | /* Unbind any ill-fitting objects or pin. */ | |
27173f1f | 695 | list_for_each_entry(vma, vmas, exec_list) { |
27173f1f | 696 | if (!drm_mm_node_allocated(&vma->node)) |
54cf91dc CW |
697 | continue; |
698 | ||
d23db88c | 699 | if (eb_vma_misplaced(vma, has_fenced_gpu_access)) |
27173f1f | 700 | ret = i915_vma_unbind(vma); |
54cf91dc | 701 | else |
27173f1f | 702 | ret = i915_gem_execbuffer_reserve_vma(vma, ring, need_relocs); |
432e58ed | 703 | if (ret) |
54cf91dc | 704 | goto err; |
54cf91dc CW |
705 | } |
706 | ||
707 | /* Bind fresh objects */ | |
27173f1f BW |
708 | list_for_each_entry(vma, vmas, exec_list) { |
709 | if (drm_mm_node_allocated(&vma->node)) | |
1690e1eb | 710 | continue; |
54cf91dc | 711 | |
27173f1f | 712 | ret = i915_gem_execbuffer_reserve_vma(vma, ring, need_relocs); |
7788a765 CW |
713 | if (ret) |
714 | goto err; | |
54cf91dc CW |
715 | } |
716 | ||
a415d355 | 717 | err: |
6c085a72 | 718 | if (ret != -ENOSPC || retry++) |
54cf91dc CW |
719 | return ret; |
720 | ||
a415d355 CW |
721 | /* Decrement pin count for bound objects */ |
722 | list_for_each_entry(vma, vmas, exec_list) | |
723 | i915_gem_execbuffer_unreserve_vma(vma); | |
724 | ||
68c8c17f | 725 | ret = i915_gem_evict_vm(vm, true); |
54cf91dc CW |
726 | if (ret) |
727 | return ret; | |
54cf91dc CW |
728 | } while (1); |
729 | } | |
730 | ||
731 | static int | |
732 | i915_gem_execbuffer_relocate_slow(struct drm_device *dev, | |
ed5982e6 | 733 | struct drm_i915_gem_execbuffer2 *args, |
54cf91dc | 734 | struct drm_file *file, |
a4872ba6 | 735 | struct intel_engine_cs *ring, |
27173f1f BW |
736 | struct eb_vmas *eb, |
737 | struct drm_i915_gem_exec_object2 *exec) | |
54cf91dc CW |
738 | { |
739 | struct drm_i915_gem_relocation_entry *reloc; | |
27173f1f BW |
740 | struct i915_address_space *vm; |
741 | struct i915_vma *vma; | |
ed5982e6 | 742 | bool need_relocs; |
dd6864a4 | 743 | int *reloc_offset; |
54cf91dc | 744 | int i, total, ret; |
b205ca57 | 745 | unsigned count = args->buffer_count; |
54cf91dc | 746 | |
27173f1f BW |
747 | if (WARN_ON(list_empty(&eb->vmas))) |
748 | return 0; | |
749 | ||
750 | vm = list_first_entry(&eb->vmas, struct i915_vma, exec_list)->vm; | |
751 | ||
67731b87 | 752 | /* We may process another execbuffer during the unlock... */ |
27173f1f BW |
753 | while (!list_empty(&eb->vmas)) { |
754 | vma = list_first_entry(&eb->vmas, struct i915_vma, exec_list); | |
755 | list_del_init(&vma->exec_list); | |
a415d355 | 756 | i915_gem_execbuffer_unreserve_vma(vma); |
27173f1f | 757 | drm_gem_object_unreference(&vma->obj->base); |
67731b87 CW |
758 | } |
759 | ||
54cf91dc CW |
760 | mutex_unlock(&dev->struct_mutex); |
761 | ||
762 | total = 0; | |
763 | for (i = 0; i < count; i++) | |
432e58ed | 764 | total += exec[i].relocation_count; |
54cf91dc | 765 | |
dd6864a4 | 766 | reloc_offset = drm_malloc_ab(count, sizeof(*reloc_offset)); |
54cf91dc | 767 | reloc = drm_malloc_ab(total, sizeof(*reloc)); |
dd6864a4 CW |
768 | if (reloc == NULL || reloc_offset == NULL) { |
769 | drm_free_large(reloc); | |
770 | drm_free_large(reloc_offset); | |
54cf91dc CW |
771 | mutex_lock(&dev->struct_mutex); |
772 | return -ENOMEM; | |
773 | } | |
774 | ||
775 | total = 0; | |
776 | for (i = 0; i < count; i++) { | |
777 | struct drm_i915_gem_relocation_entry __user *user_relocs; | |
262b6d36 CW |
778 | u64 invalid_offset = (u64)-1; |
779 | int j; | |
54cf91dc | 780 | |
2bb4629a | 781 | user_relocs = to_user_ptr(exec[i].relocs_ptr); |
54cf91dc CW |
782 | |
783 | if (copy_from_user(reloc+total, user_relocs, | |
432e58ed | 784 | exec[i].relocation_count * sizeof(*reloc))) { |
54cf91dc CW |
785 | ret = -EFAULT; |
786 | mutex_lock(&dev->struct_mutex); | |
787 | goto err; | |
788 | } | |
789 | ||
262b6d36 CW |
790 | /* As we do not update the known relocation offsets after |
791 | * relocating (due to the complexities in lock handling), | |
792 | * we need to mark them as invalid now so that we force the | |
793 | * relocation processing next time. Just in case the target | |
794 | * object is evicted and then rebound into its old | |
795 | * presumed_offset before the next execbuffer - if that | |
796 | * happened we would make the mistake of assuming that the | |
797 | * relocations were valid. | |
798 | */ | |
799 | for (j = 0; j < exec[i].relocation_count; j++) { | |
9aab8bff CW |
800 | if (__copy_to_user(&user_relocs[j].presumed_offset, |
801 | &invalid_offset, | |
802 | sizeof(invalid_offset))) { | |
262b6d36 CW |
803 | ret = -EFAULT; |
804 | mutex_lock(&dev->struct_mutex); | |
805 | goto err; | |
806 | } | |
807 | } | |
808 | ||
dd6864a4 | 809 | reloc_offset[i] = total; |
432e58ed | 810 | total += exec[i].relocation_count; |
54cf91dc CW |
811 | } |
812 | ||
813 | ret = i915_mutex_lock_interruptible(dev); | |
814 | if (ret) { | |
815 | mutex_lock(&dev->struct_mutex); | |
816 | goto err; | |
817 | } | |
818 | ||
67731b87 | 819 | /* reacquire the objects */ |
67731b87 | 820 | eb_reset(eb); |
27173f1f | 821 | ret = eb_lookup_vmas(eb, exec, args, vm, file); |
3b96eff4 CW |
822 | if (ret) |
823 | goto err; | |
67731b87 | 824 | |
ed5982e6 | 825 | need_relocs = (args->flags & I915_EXEC_NO_RELOC) == 0; |
27173f1f | 826 | ret = i915_gem_execbuffer_reserve(ring, &eb->vmas, &need_relocs); |
54cf91dc CW |
827 | if (ret) |
828 | goto err; | |
829 | ||
27173f1f BW |
830 | list_for_each_entry(vma, &eb->vmas, exec_list) { |
831 | int offset = vma->exec_entry - exec; | |
832 | ret = i915_gem_execbuffer_relocate_vma_slow(vma, eb, | |
833 | reloc + reloc_offset[offset]); | |
54cf91dc CW |
834 | if (ret) |
835 | goto err; | |
54cf91dc CW |
836 | } |
837 | ||
838 | /* Leave the user relocations as are, this is the painfully slow path, | |
839 | * and we want to avoid the complication of dropping the lock whilst | |
840 | * having buffers reserved in the aperture and so causing spurious | |
841 | * ENOSPC for random operations. | |
842 | */ | |
843 | ||
844 | err: | |
845 | drm_free_large(reloc); | |
dd6864a4 | 846 | drm_free_large(reloc_offset); |
54cf91dc CW |
847 | return ret; |
848 | } | |
849 | ||
54cf91dc | 850 | static int |
a4872ba6 | 851 | i915_gem_execbuffer_move_to_gpu(struct intel_engine_cs *ring, |
27173f1f | 852 | struct list_head *vmas) |
54cf91dc | 853 | { |
27173f1f | 854 | struct i915_vma *vma; |
6ac42f41 | 855 | uint32_t flush_domains = 0; |
000433b6 | 856 | bool flush_chipset = false; |
432e58ed | 857 | int ret; |
54cf91dc | 858 | |
27173f1f BW |
859 | list_for_each_entry(vma, vmas, exec_list) { |
860 | struct drm_i915_gem_object *obj = vma->obj; | |
6ac42f41 | 861 | ret = i915_gem_object_sync(obj, ring); |
c59a333f CW |
862 | if (ret) |
863 | return ret; | |
6ac42f41 DV |
864 | |
865 | if (obj->base.write_domain & I915_GEM_DOMAIN_CPU) | |
000433b6 | 866 | flush_chipset |= i915_gem_clflush_object(obj, false); |
6ac42f41 | 867 | |
6ac42f41 | 868 | flush_domains |= obj->base.write_domain; |
c59a333f CW |
869 | } |
870 | ||
000433b6 | 871 | if (flush_chipset) |
e76e9aeb | 872 | i915_gem_chipset_flush(ring->dev); |
6ac42f41 DV |
873 | |
874 | if (flush_domains & I915_GEM_DOMAIN_GTT) | |
875 | wmb(); | |
876 | ||
09cf7c9a CW |
877 | /* Unconditionally invalidate gpu caches and ensure that we do flush |
878 | * any residual writes from the previous batch. | |
879 | */ | |
a7b9761d | 880 | return intel_ring_invalidate_all_caches(ring); |
54cf91dc CW |
881 | } |
882 | ||
432e58ed CW |
883 | static bool |
884 | i915_gem_check_execbuffer(struct drm_i915_gem_execbuffer2 *exec) | |
54cf91dc | 885 | { |
ed5982e6 DV |
886 | if (exec->flags & __I915_EXEC_UNKNOWN_FLAGS) |
887 | return false; | |
888 | ||
432e58ed | 889 | return ((exec->batch_start_offset | exec->batch_len) & 0x7) == 0; |
54cf91dc CW |
890 | } |
891 | ||
892 | static int | |
893 | validate_exec_list(struct drm_i915_gem_exec_object2 *exec, | |
894 | int count) | |
895 | { | |
896 | int i; | |
b205ca57 DV |
897 | unsigned relocs_total = 0; |
898 | unsigned relocs_max = UINT_MAX / sizeof(struct drm_i915_gem_relocation_entry); | |
54cf91dc CW |
899 | |
900 | for (i = 0; i < count; i++) { | |
2bb4629a | 901 | char __user *ptr = to_user_ptr(exec[i].relocs_ptr); |
54cf91dc CW |
902 | int length; /* limited by fault_in_pages_readable() */ |
903 | ||
ed5982e6 DV |
904 | if (exec[i].flags & __EXEC_OBJECT_UNKNOWN_FLAGS) |
905 | return -EINVAL; | |
906 | ||
3118a4f6 KC |
907 | /* First check for malicious input causing overflow in |
908 | * the worst case where we need to allocate the entire | |
909 | * relocation tree as a single array. | |
910 | */ | |
911 | if (exec[i].relocation_count > relocs_max - relocs_total) | |
54cf91dc | 912 | return -EINVAL; |
3118a4f6 | 913 | relocs_total += exec[i].relocation_count; |
54cf91dc CW |
914 | |
915 | length = exec[i].relocation_count * | |
916 | sizeof(struct drm_i915_gem_relocation_entry); | |
30587535 KC |
917 | /* |
918 | * We must check that the entire relocation array is safe | |
919 | * to read, but since we may need to update the presumed | |
920 | * offsets during execution, check for full write access. | |
921 | */ | |
54cf91dc CW |
922 | if (!access_ok(VERIFY_WRITE, ptr, length)) |
923 | return -EFAULT; | |
924 | ||
d330a953 | 925 | if (likely(!i915.prefault_disable)) { |
0b74b508 XZ |
926 | if (fault_in_multipages_readable(ptr, length)) |
927 | return -EFAULT; | |
928 | } | |
54cf91dc CW |
929 | } |
930 | ||
931 | return 0; | |
932 | } | |
933 | ||
273497e5 | 934 | static struct intel_context * |
d299cce7 | 935 | i915_gem_validate_context(struct drm_device *dev, struct drm_file *file, |
a4872ba6 | 936 | struct intel_engine_cs *ring, const u32 ctx_id) |
d299cce7 | 937 | { |
273497e5 | 938 | struct intel_context *ctx = NULL; |
d299cce7 MK |
939 | struct i915_ctx_hang_stats *hs; |
940 | ||
821d66dd | 941 | if (ring->id != RCS && ctx_id != DEFAULT_CONTEXT_HANDLE) |
7c9c4b8f DV |
942 | return ERR_PTR(-EINVAL); |
943 | ||
41bde553 | 944 | ctx = i915_gem_context_get(file->driver_priv, ctx_id); |
72ad5c45 | 945 | if (IS_ERR(ctx)) |
41bde553 | 946 | return ctx; |
d299cce7 | 947 | |
41bde553 | 948 | hs = &ctx->hang_stats; |
d299cce7 MK |
949 | if (hs->banned) { |
950 | DRM_DEBUG("Context %u tried to submit while banned\n", ctx_id); | |
41bde553 | 951 | return ERR_PTR(-EIO); |
d299cce7 MK |
952 | } |
953 | ||
41bde553 | 954 | return ctx; |
d299cce7 MK |
955 | } |
956 | ||
432e58ed | 957 | static void |
27173f1f | 958 | i915_gem_execbuffer_move_to_active(struct list_head *vmas, |
a4872ba6 | 959 | struct intel_engine_cs *ring) |
432e58ed | 960 | { |
27173f1f | 961 | struct i915_vma *vma; |
432e58ed | 962 | |
27173f1f BW |
963 | list_for_each_entry(vma, vmas, exec_list) { |
964 | struct drm_i915_gem_object *obj = vma->obj; | |
69c2fc89 CW |
965 | u32 old_read = obj->base.read_domains; |
966 | u32 old_write = obj->base.write_domain; | |
db53a302 | 967 | |
432e58ed | 968 | obj->base.write_domain = obj->base.pending_write_domain; |
ed5982e6 DV |
969 | if (obj->base.write_domain == 0) |
970 | obj->base.pending_read_domains |= obj->base.read_domains; | |
971 | obj->base.read_domains = obj->base.pending_read_domains; | |
432e58ed CW |
972 | obj->fenced_gpu_access = obj->pending_fenced_gpu_access; |
973 | ||
e2d05a8b | 974 | i915_vma_move_to_active(vma, ring); |
432e58ed CW |
975 | if (obj->base.write_domain) { |
976 | obj->dirty = 1; | |
9d773091 | 977 | obj->last_write_seqno = intel_ring_get_seqno(ring); |
f99d7069 DV |
978 | |
979 | intel_fb_obj_invalidate(obj, ring); | |
c8725f3d CW |
980 | |
981 | /* update for the implicit flush after a batch */ | |
982 | obj->base.write_domain &= ~I915_GEM_GPU_DOMAINS; | |
432e58ed CW |
983 | } |
984 | ||
db53a302 | 985 | trace_i915_gem_object_change_domain(obj, old_read, old_write); |
432e58ed CW |
986 | } |
987 | } | |
988 | ||
54cf91dc CW |
989 | static void |
990 | i915_gem_execbuffer_retire_commands(struct drm_device *dev, | |
432e58ed | 991 | struct drm_file *file, |
a4872ba6 | 992 | struct intel_engine_cs *ring, |
7d736f4f | 993 | struct drm_i915_gem_object *obj) |
54cf91dc | 994 | { |
cc889e0f DV |
995 | /* Unconditionally force add_request to emit a full flush. */ |
996 | ring->gpu_caches_dirty = true; | |
54cf91dc | 997 | |
432e58ed | 998 | /* Add a breadcrumb for the completion of the batch buffer */ |
7d736f4f | 999 | (void)__i915_add_request(ring, file, obj, NULL); |
432e58ed | 1000 | } |
54cf91dc | 1001 | |
ae662d31 EA |
1002 | static int |
1003 | i915_reset_gen7_sol_offsets(struct drm_device *dev, | |
a4872ba6 | 1004 | struct intel_engine_cs *ring) |
ae662d31 | 1005 | { |
50227e1c | 1006 | struct drm_i915_private *dev_priv = dev->dev_private; |
ae662d31 EA |
1007 | int ret, i; |
1008 | ||
9d662da8 DV |
1009 | if (!IS_GEN7(dev) || ring != &dev_priv->ring[RCS]) { |
1010 | DRM_DEBUG("sol reset is gen7/rcs only\n"); | |
1011 | return -EINVAL; | |
1012 | } | |
ae662d31 EA |
1013 | |
1014 | ret = intel_ring_begin(ring, 4 * 3); | |
1015 | if (ret) | |
1016 | return ret; | |
1017 | ||
1018 | for (i = 0; i < 4; i++) { | |
1019 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); | |
1020 | intel_ring_emit(ring, GEN7_SO_WRITE_OFFSET(i)); | |
1021 | intel_ring_emit(ring, 0); | |
1022 | } | |
1023 | ||
1024 | intel_ring_advance(ring); | |
1025 | ||
1026 | return 0; | |
1027 | } | |
1028 | ||
a8ebba75 ZY |
1029 | /** |
1030 | * Find one BSD ring to dispatch the corresponding BSD command. | |
1031 | * The Ring ID is returned. | |
1032 | */ | |
1033 | static int gen8_dispatch_bsd_ring(struct drm_device *dev, | |
1034 | struct drm_file *file) | |
1035 | { | |
1036 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1037 | struct drm_i915_file_private *file_priv = file->driver_priv; | |
1038 | ||
1039 | /* Check whether the file_priv is using one ring */ | |
1040 | if (file_priv->bsd_ring) | |
1041 | return file_priv->bsd_ring->id; | |
1042 | else { | |
1043 | /* If no, use the ping-pong mechanism to select one ring */ | |
1044 | int ring_id; | |
1045 | ||
1046 | mutex_lock(&dev->struct_mutex); | |
bdf1e7e3 | 1047 | if (dev_priv->mm.bsd_ring_dispatch_index == 0) { |
a8ebba75 | 1048 | ring_id = VCS; |
bdf1e7e3 | 1049 | dev_priv->mm.bsd_ring_dispatch_index = 1; |
a8ebba75 ZY |
1050 | } else { |
1051 | ring_id = VCS2; | |
bdf1e7e3 | 1052 | dev_priv->mm.bsd_ring_dispatch_index = 0; |
a8ebba75 ZY |
1053 | } |
1054 | file_priv->bsd_ring = &dev_priv->ring[ring_id]; | |
1055 | mutex_unlock(&dev->struct_mutex); | |
1056 | return ring_id; | |
1057 | } | |
1058 | } | |
1059 | ||
d23db88c CW |
1060 | static struct drm_i915_gem_object * |
1061 | eb_get_batch(struct eb_vmas *eb) | |
1062 | { | |
1063 | struct i915_vma *vma = list_entry(eb->vmas.prev, typeof(*vma), exec_list); | |
1064 | ||
1065 | /* | |
1066 | * SNA is doing fancy tricks with compressing batch buffers, which leads | |
1067 | * to negative relocation deltas. Usually that works out ok since the | |
1068 | * relocate address is still positive, except when the batch is placed | |
1069 | * very low in the GTT. Ensure this doesn't happen. | |
1070 | * | |
1071 | * Note that actual hangs have only been observed on gen7, but for | |
1072 | * paranoia do it everywhere. | |
1073 | */ | |
1074 | vma->exec_entry->flags |= __EXEC_OBJECT_NEEDS_BIAS; | |
1075 | ||
1076 | return vma->obj; | |
1077 | } | |
1078 | ||
54cf91dc CW |
1079 | static int |
1080 | i915_gem_do_execbuffer(struct drm_device *dev, void *data, | |
1081 | struct drm_file *file, | |
1082 | struct drm_i915_gem_execbuffer2 *args, | |
41bde553 | 1083 | struct drm_i915_gem_exec_object2 *exec) |
54cf91dc | 1084 | { |
50227e1c | 1085 | struct drm_i915_private *dev_priv = dev->dev_private; |
27173f1f | 1086 | struct eb_vmas *eb; |
54cf91dc CW |
1087 | struct drm_i915_gem_object *batch_obj; |
1088 | struct drm_clip_rect *cliprects = NULL; | |
a4872ba6 | 1089 | struct intel_engine_cs *ring; |
273497e5 | 1090 | struct intel_context *ctx; |
41bde553 | 1091 | struct i915_address_space *vm; |
d299cce7 | 1092 | const u32 ctx_id = i915_execbuffer2_get_context_id(*args); |
9bcb144c | 1093 | u64 exec_start = args->batch_start_offset, exec_len; |
ed5982e6 | 1094 | u32 mask, flags; |
72bfa19c | 1095 | int ret, mode, i; |
ed5982e6 | 1096 | bool need_relocs; |
54cf91dc | 1097 | |
ed5982e6 | 1098 | if (!i915_gem_check_execbuffer(args)) |
432e58ed | 1099 | return -EINVAL; |
432e58ed CW |
1100 | |
1101 | ret = validate_exec_list(exec, args->buffer_count); | |
54cf91dc CW |
1102 | if (ret) |
1103 | return ret; | |
1104 | ||
d7d4eedd CW |
1105 | flags = 0; |
1106 | if (args->flags & I915_EXEC_SECURE) { | |
1107 | if (!file->is_master || !capable(CAP_SYS_ADMIN)) | |
1108 | return -EPERM; | |
1109 | ||
1110 | flags |= I915_DISPATCH_SECURE; | |
1111 | } | |
b45305fc DV |
1112 | if (args->flags & I915_EXEC_IS_PINNED) |
1113 | flags |= I915_DISPATCH_PINNED; | |
d7d4eedd | 1114 | |
b1a93306 | 1115 | if ((args->flags & I915_EXEC_RING_MASK) > LAST_USER_RING) { |
ff240199 | 1116 | DRM_DEBUG("execbuf with unknown ring: %d\n", |
54cf91dc CW |
1117 | (int)(args->flags & I915_EXEC_RING_MASK)); |
1118 | return -EINVAL; | |
1119 | } | |
ca01b12b BW |
1120 | |
1121 | if ((args->flags & I915_EXEC_RING_MASK) == I915_EXEC_DEFAULT) | |
1122 | ring = &dev_priv->ring[RCS]; | |
a8ebba75 ZY |
1123 | else if ((args->flags & I915_EXEC_RING_MASK) == I915_EXEC_BSD) { |
1124 | if (HAS_BSD2(dev)) { | |
1125 | int ring_id; | |
1126 | ring_id = gen8_dispatch_bsd_ring(dev, file); | |
1127 | ring = &dev_priv->ring[ring_id]; | |
1128 | } else | |
1129 | ring = &dev_priv->ring[VCS]; | |
1130 | } else | |
ca01b12b BW |
1131 | ring = &dev_priv->ring[(args->flags & I915_EXEC_RING_MASK) - 1]; |
1132 | ||
a15817cf CW |
1133 | if (!intel_ring_initialized(ring)) { |
1134 | DRM_DEBUG("execbuf with invalid ring: %d\n", | |
1135 | (int)(args->flags & I915_EXEC_RING_MASK)); | |
1136 | return -EINVAL; | |
1137 | } | |
54cf91dc | 1138 | |
72bfa19c | 1139 | mode = args->flags & I915_EXEC_CONSTANTS_MASK; |
84f9f938 | 1140 | mask = I915_EXEC_CONSTANTS_MASK; |
72bfa19c CW |
1141 | switch (mode) { |
1142 | case I915_EXEC_CONSTANTS_REL_GENERAL: | |
1143 | case I915_EXEC_CONSTANTS_ABSOLUTE: | |
1144 | case I915_EXEC_CONSTANTS_REL_SURFACE: | |
c0f5b82c DV |
1145 | if (mode != 0 && ring != &dev_priv->ring[RCS]) { |
1146 | DRM_DEBUG("non-0 rel constants mode on non-RCS\n"); | |
1147 | return -EINVAL; | |
1148 | } | |
1149 | ||
1150 | if (mode != dev_priv->relative_constants_mode) { | |
1151 | if (INTEL_INFO(dev)->gen < 4) { | |
1152 | DRM_DEBUG("no rel constants on pre-gen4\n"); | |
72bfa19c | 1153 | return -EINVAL; |
c0f5b82c | 1154 | } |
72bfa19c CW |
1155 | |
1156 | if (INTEL_INFO(dev)->gen > 5 && | |
c0f5b82c DV |
1157 | mode == I915_EXEC_CONSTANTS_REL_SURFACE) { |
1158 | DRM_DEBUG("rel surface constants mode invalid on gen5+\n"); | |
72bfa19c | 1159 | return -EINVAL; |
c0f5b82c | 1160 | } |
84f9f938 BW |
1161 | |
1162 | /* The HW changed the meaning on this bit on gen6 */ | |
1163 | if (INTEL_INFO(dev)->gen >= 6) | |
1164 | mask &= ~I915_EXEC_CONSTANTS_REL_SURFACE; | |
72bfa19c CW |
1165 | } |
1166 | break; | |
1167 | default: | |
ff240199 | 1168 | DRM_DEBUG("execbuf with unknown constants: %d\n", mode); |
72bfa19c CW |
1169 | return -EINVAL; |
1170 | } | |
1171 | ||
54cf91dc | 1172 | if (args->buffer_count < 1) { |
ff240199 | 1173 | DRM_DEBUG("execbuf with %d buffers\n", args->buffer_count); |
54cf91dc CW |
1174 | return -EINVAL; |
1175 | } | |
54cf91dc CW |
1176 | |
1177 | if (args->num_cliprects != 0) { | |
1ec14ad3 | 1178 | if (ring != &dev_priv->ring[RCS]) { |
ff240199 | 1179 | DRM_DEBUG("clip rectangles are only valid with the render ring\n"); |
c4e7a414 CW |
1180 | return -EINVAL; |
1181 | } | |
1182 | ||
6ebebc92 DV |
1183 | if (INTEL_INFO(dev)->gen >= 5) { |
1184 | DRM_DEBUG("clip rectangles are only valid on pre-gen5\n"); | |
1185 | return -EINVAL; | |
1186 | } | |
1187 | ||
44afb3a0 XW |
1188 | if (args->num_cliprects > UINT_MAX / sizeof(*cliprects)) { |
1189 | DRM_DEBUG("execbuf with %u cliprects\n", | |
1190 | args->num_cliprects); | |
1191 | return -EINVAL; | |
1192 | } | |
5e13a0c5 | 1193 | |
a1e22653 DV |
1194 | cliprects = kcalloc(args->num_cliprects, |
1195 | sizeof(*cliprects), | |
54cf91dc CW |
1196 | GFP_KERNEL); |
1197 | if (cliprects == NULL) { | |
1198 | ret = -ENOMEM; | |
1199 | goto pre_mutex_err; | |
1200 | } | |
1201 | ||
432e58ed | 1202 | if (copy_from_user(cliprects, |
2bb4629a VS |
1203 | to_user_ptr(args->cliprects_ptr), |
1204 | sizeof(*cliprects)*args->num_cliprects)) { | |
54cf91dc CW |
1205 | ret = -EFAULT; |
1206 | goto pre_mutex_err; | |
1207 | } | |
9cb34664 | 1208 | } else { |
ffd93f24 DV |
1209 | if (args->DR4 == 0xffffffff) { |
1210 | DRM_DEBUG("UXA submitting garbage DR4, fixing up\n"); | |
1211 | args->DR4 = 0; | |
1212 | } | |
1213 | ||
9cb34664 DV |
1214 | if (args->DR1 || args->DR4 || args->cliprects_ptr) { |
1215 | DRM_DEBUG("0 cliprects but dirt in cliprects fields\n"); | |
1216 | return -EINVAL; | |
1217 | } | |
54cf91dc CW |
1218 | } |
1219 | ||
f65c9168 PZ |
1220 | intel_runtime_pm_get(dev_priv); |
1221 | ||
54cf91dc CW |
1222 | ret = i915_mutex_lock_interruptible(dev); |
1223 | if (ret) | |
1224 | goto pre_mutex_err; | |
1225 | ||
db1b76ca | 1226 | if (dev_priv->ums.mm_suspended) { |
54cf91dc CW |
1227 | mutex_unlock(&dev->struct_mutex); |
1228 | ret = -EBUSY; | |
1229 | goto pre_mutex_err; | |
1230 | } | |
1231 | ||
7c9c4b8f | 1232 | ctx = i915_gem_validate_context(dev, file, ring, ctx_id); |
72ad5c45 | 1233 | if (IS_ERR(ctx)) { |
d299cce7 | 1234 | mutex_unlock(&dev->struct_mutex); |
41bde553 | 1235 | ret = PTR_ERR(ctx); |
d299cce7 | 1236 | goto pre_mutex_err; |
935f38d6 | 1237 | } |
41bde553 BW |
1238 | |
1239 | i915_gem_context_reference(ctx); | |
1240 | ||
7e0d96bc BW |
1241 | vm = ctx->vm; |
1242 | if (!USES_FULL_PPGTT(dev)) | |
1243 | vm = &dev_priv->gtt.base; | |
d299cce7 | 1244 | |
17601cbc | 1245 | eb = eb_create(args); |
67731b87 | 1246 | if (eb == NULL) { |
935f38d6 | 1247 | i915_gem_context_unreference(ctx); |
67731b87 CW |
1248 | mutex_unlock(&dev->struct_mutex); |
1249 | ret = -ENOMEM; | |
1250 | goto pre_mutex_err; | |
1251 | } | |
1252 | ||
54cf91dc | 1253 | /* Look up object handles */ |
27173f1f | 1254 | ret = eb_lookup_vmas(eb, exec, args, vm, file); |
3b96eff4 CW |
1255 | if (ret) |
1256 | goto err; | |
54cf91dc | 1257 | |
6fe4f140 | 1258 | /* take note of the batch buffer before we might reorder the lists */ |
d23db88c | 1259 | batch_obj = eb_get_batch(eb); |
6fe4f140 | 1260 | |
54cf91dc | 1261 | /* Move the objects en-masse into the GTT, evicting if necessary. */ |
ed5982e6 | 1262 | need_relocs = (args->flags & I915_EXEC_NO_RELOC) == 0; |
27173f1f | 1263 | ret = i915_gem_execbuffer_reserve(ring, &eb->vmas, &need_relocs); |
54cf91dc CW |
1264 | if (ret) |
1265 | goto err; | |
1266 | ||
1267 | /* The objects are in their final locations, apply the relocations. */ | |
ed5982e6 | 1268 | if (need_relocs) |
17601cbc | 1269 | ret = i915_gem_execbuffer_relocate(eb); |
54cf91dc CW |
1270 | if (ret) { |
1271 | if (ret == -EFAULT) { | |
ed5982e6 | 1272 | ret = i915_gem_execbuffer_relocate_slow(dev, args, file, ring, |
27173f1f | 1273 | eb, exec); |
54cf91dc CW |
1274 | BUG_ON(!mutex_is_locked(&dev->struct_mutex)); |
1275 | } | |
1276 | if (ret) | |
1277 | goto err; | |
1278 | } | |
1279 | ||
1280 | /* Set the pending read domains for the batch buffer to COMMAND */ | |
54cf91dc | 1281 | if (batch_obj->base.pending_write_domain) { |
ff240199 | 1282 | DRM_DEBUG("Attempting to use self-modifying batch buffer\n"); |
54cf91dc CW |
1283 | ret = -EINVAL; |
1284 | goto err; | |
1285 | } | |
1286 | batch_obj->base.pending_read_domains |= I915_GEM_DOMAIN_COMMAND; | |
1287 | ||
351e3db2 BV |
1288 | if (i915_needs_cmd_parser(ring)) { |
1289 | ret = i915_parse_cmds(ring, | |
1290 | batch_obj, | |
1291 | args->batch_start_offset, | |
1292 | file->is_master); | |
1293 | if (ret) | |
1294 | goto err; | |
1295 | ||
1296 | /* | |
1297 | * XXX: Actually do this when enabling batch copy... | |
1298 | * | |
1299 | * Set the DISPATCH_SECURE bit to remove the NON_SECURE bit | |
1300 | * from MI_BATCH_BUFFER_START commands issued in the | |
1301 | * dispatch_execbuffer implementations. We specifically don't | |
1302 | * want that set when the command parser is enabled. | |
1303 | */ | |
1304 | } | |
1305 | ||
d7d4eedd CW |
1306 | /* snb/ivb/vlv conflate the "batch in ppgtt" bit with the "non-secure |
1307 | * batch" bit. Hence we need to pin secure batches into the global gtt. | |
28cf5415 | 1308 | * hsw should have this fixed, but bdw mucks it up again. */ |
6f65e29a BW |
1309 | if (flags & I915_DISPATCH_SECURE && |
1310 | !batch_obj->has_global_gtt_mapping) { | |
1311 | /* When we have multiple VMs, we'll need to make sure that we | |
1312 | * allocate space first */ | |
1313 | struct i915_vma *vma = i915_gem_obj_to_ggtt(batch_obj); | |
1314 | BUG_ON(!vma); | |
1315 | vma->bind_vma(vma, batch_obj->cache_level, GLOBAL_BIND); | |
1316 | } | |
d7d4eedd | 1317 | |
7e0d96bc BW |
1318 | if (flags & I915_DISPATCH_SECURE) |
1319 | exec_start += i915_gem_obj_ggtt_offset(batch_obj); | |
1320 | else | |
1321 | exec_start += i915_gem_obj_offset(batch_obj, vm); | |
d7d4eedd | 1322 | |
27173f1f | 1323 | ret = i915_gem_execbuffer_move_to_gpu(ring, &eb->vmas); |
432e58ed | 1324 | if (ret) |
54cf91dc | 1325 | goto err; |
54cf91dc | 1326 | |
691e6415 | 1327 | ret = i915_switch_context(ring, ctx); |
0da5cec1 EA |
1328 | if (ret) |
1329 | goto err; | |
1330 | ||
e2971bda BW |
1331 | if (ring == &dev_priv->ring[RCS] && |
1332 | mode != dev_priv->relative_constants_mode) { | |
1333 | ret = intel_ring_begin(ring, 4); | |
1334 | if (ret) | |
1335 | goto err; | |
1336 | ||
1337 | intel_ring_emit(ring, MI_NOOP); | |
1338 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); | |
1339 | intel_ring_emit(ring, INSTPM); | |
84f9f938 | 1340 | intel_ring_emit(ring, mask << 16 | mode); |
e2971bda BW |
1341 | intel_ring_advance(ring); |
1342 | ||
1343 | dev_priv->relative_constants_mode = mode; | |
1344 | } | |
1345 | ||
ae662d31 EA |
1346 | if (args->flags & I915_EXEC_GEN7_SOL_RESET) { |
1347 | ret = i915_reset_gen7_sol_offsets(dev, ring); | |
1348 | if (ret) | |
1349 | goto err; | |
1350 | } | |
1351 | ||
7e0d96bc | 1352 | |
c4e7a414 CW |
1353 | exec_len = args->batch_len; |
1354 | if (cliprects) { | |
1355 | for (i = 0; i < args->num_cliprects; i++) { | |
1356 | ret = i915_emit_box(dev, &cliprects[i], | |
1357 | args->DR1, args->DR4); | |
1358 | if (ret) | |
1359 | goto err; | |
1360 | ||
1361 | ret = ring->dispatch_execbuffer(ring, | |
d7d4eedd CW |
1362 | exec_start, exec_len, |
1363 | flags); | |
c4e7a414 CW |
1364 | if (ret) |
1365 | goto err; | |
1366 | } | |
1367 | } else { | |
d7d4eedd CW |
1368 | ret = ring->dispatch_execbuffer(ring, |
1369 | exec_start, exec_len, | |
1370 | flags); | |
c4e7a414 CW |
1371 | if (ret) |
1372 | goto err; | |
1373 | } | |
54cf91dc | 1374 | |
9d773091 CW |
1375 | trace_i915_gem_ring_dispatch(ring, intel_ring_get_seqno(ring), flags); |
1376 | ||
27173f1f | 1377 | i915_gem_execbuffer_move_to_active(&eb->vmas, ring); |
7d736f4f | 1378 | i915_gem_execbuffer_retire_commands(dev, file, ring, batch_obj); |
54cf91dc CW |
1379 | |
1380 | err: | |
41bde553 BW |
1381 | /* the request owns the ref now */ |
1382 | i915_gem_context_unreference(ctx); | |
67731b87 | 1383 | eb_destroy(eb); |
54cf91dc CW |
1384 | |
1385 | mutex_unlock(&dev->struct_mutex); | |
1386 | ||
1387 | pre_mutex_err: | |
54cf91dc | 1388 | kfree(cliprects); |
f65c9168 PZ |
1389 | |
1390 | /* intel_gpu_busy should also get a ref, so it will free when the device | |
1391 | * is really idle. */ | |
1392 | intel_runtime_pm_put(dev_priv); | |
54cf91dc CW |
1393 | return ret; |
1394 | } | |
1395 | ||
1396 | /* | |
1397 | * Legacy execbuffer just creates an exec2 list from the original exec object | |
1398 | * list array and passes it to the real function. | |
1399 | */ | |
1400 | int | |
1401 | i915_gem_execbuffer(struct drm_device *dev, void *data, | |
1402 | struct drm_file *file) | |
1403 | { | |
1404 | struct drm_i915_gem_execbuffer *args = data; | |
1405 | struct drm_i915_gem_execbuffer2 exec2; | |
1406 | struct drm_i915_gem_exec_object *exec_list = NULL; | |
1407 | struct drm_i915_gem_exec_object2 *exec2_list = NULL; | |
1408 | int ret, i; | |
1409 | ||
54cf91dc | 1410 | if (args->buffer_count < 1) { |
ff240199 | 1411 | DRM_DEBUG("execbuf with %d buffers\n", args->buffer_count); |
54cf91dc CW |
1412 | return -EINVAL; |
1413 | } | |
1414 | ||
1415 | /* Copy in the exec list from userland */ | |
1416 | exec_list = drm_malloc_ab(sizeof(*exec_list), args->buffer_count); | |
1417 | exec2_list = drm_malloc_ab(sizeof(*exec2_list), args->buffer_count); | |
1418 | if (exec_list == NULL || exec2_list == NULL) { | |
ff240199 | 1419 | DRM_DEBUG("Failed to allocate exec list for %d buffers\n", |
54cf91dc CW |
1420 | args->buffer_count); |
1421 | drm_free_large(exec_list); | |
1422 | drm_free_large(exec2_list); | |
1423 | return -ENOMEM; | |
1424 | } | |
1425 | ret = copy_from_user(exec_list, | |
2bb4629a | 1426 | to_user_ptr(args->buffers_ptr), |
54cf91dc CW |
1427 | sizeof(*exec_list) * args->buffer_count); |
1428 | if (ret != 0) { | |
ff240199 | 1429 | DRM_DEBUG("copy %d exec entries failed %d\n", |
54cf91dc CW |
1430 | args->buffer_count, ret); |
1431 | drm_free_large(exec_list); | |
1432 | drm_free_large(exec2_list); | |
1433 | return -EFAULT; | |
1434 | } | |
1435 | ||
1436 | for (i = 0; i < args->buffer_count; i++) { | |
1437 | exec2_list[i].handle = exec_list[i].handle; | |
1438 | exec2_list[i].relocation_count = exec_list[i].relocation_count; | |
1439 | exec2_list[i].relocs_ptr = exec_list[i].relocs_ptr; | |
1440 | exec2_list[i].alignment = exec_list[i].alignment; | |
1441 | exec2_list[i].offset = exec_list[i].offset; | |
1442 | if (INTEL_INFO(dev)->gen < 4) | |
1443 | exec2_list[i].flags = EXEC_OBJECT_NEEDS_FENCE; | |
1444 | else | |
1445 | exec2_list[i].flags = 0; | |
1446 | } | |
1447 | ||
1448 | exec2.buffers_ptr = args->buffers_ptr; | |
1449 | exec2.buffer_count = args->buffer_count; | |
1450 | exec2.batch_start_offset = args->batch_start_offset; | |
1451 | exec2.batch_len = args->batch_len; | |
1452 | exec2.DR1 = args->DR1; | |
1453 | exec2.DR4 = args->DR4; | |
1454 | exec2.num_cliprects = args->num_cliprects; | |
1455 | exec2.cliprects_ptr = args->cliprects_ptr; | |
1456 | exec2.flags = I915_EXEC_RENDER; | |
6e0a69db | 1457 | i915_execbuffer2_set_context_id(exec2, 0); |
54cf91dc | 1458 | |
41bde553 | 1459 | ret = i915_gem_do_execbuffer(dev, data, file, &exec2, exec2_list); |
54cf91dc | 1460 | if (!ret) { |
9aab8bff CW |
1461 | struct drm_i915_gem_exec_object __user *user_exec_list = |
1462 | to_user_ptr(args->buffers_ptr); | |
1463 | ||
54cf91dc | 1464 | /* Copy the new buffer offsets back to the user's exec list. */ |
9aab8bff CW |
1465 | for (i = 0; i < args->buffer_count; i++) { |
1466 | ret = __copy_to_user(&user_exec_list[i].offset, | |
1467 | &exec2_list[i].offset, | |
1468 | sizeof(user_exec_list[i].offset)); | |
1469 | if (ret) { | |
1470 | ret = -EFAULT; | |
1471 | DRM_DEBUG("failed to copy %d exec entries " | |
1472 | "back to user (%d)\n", | |
1473 | args->buffer_count, ret); | |
1474 | break; | |
1475 | } | |
54cf91dc CW |
1476 | } |
1477 | } | |
1478 | ||
1479 | drm_free_large(exec_list); | |
1480 | drm_free_large(exec2_list); | |
1481 | return ret; | |
1482 | } | |
1483 | ||
1484 | int | |
1485 | i915_gem_execbuffer2(struct drm_device *dev, void *data, | |
1486 | struct drm_file *file) | |
1487 | { | |
1488 | struct drm_i915_gem_execbuffer2 *args = data; | |
1489 | struct drm_i915_gem_exec_object2 *exec2_list = NULL; | |
1490 | int ret; | |
1491 | ||
ed8cd3b2 XW |
1492 | if (args->buffer_count < 1 || |
1493 | args->buffer_count > UINT_MAX / sizeof(*exec2_list)) { | |
ff240199 | 1494 | DRM_DEBUG("execbuf2 with %d buffers\n", args->buffer_count); |
54cf91dc CW |
1495 | return -EINVAL; |
1496 | } | |
1497 | ||
9cb34664 DV |
1498 | if (args->rsvd2 != 0) { |
1499 | DRM_DEBUG("dirty rvsd2 field\n"); | |
1500 | return -EINVAL; | |
1501 | } | |
1502 | ||
8408c282 | 1503 | exec2_list = kmalloc(sizeof(*exec2_list)*args->buffer_count, |
419fa72a | 1504 | GFP_TEMPORARY | __GFP_NOWARN | __GFP_NORETRY); |
8408c282 CW |
1505 | if (exec2_list == NULL) |
1506 | exec2_list = drm_malloc_ab(sizeof(*exec2_list), | |
1507 | args->buffer_count); | |
54cf91dc | 1508 | if (exec2_list == NULL) { |
ff240199 | 1509 | DRM_DEBUG("Failed to allocate exec list for %d buffers\n", |
54cf91dc CW |
1510 | args->buffer_count); |
1511 | return -ENOMEM; | |
1512 | } | |
1513 | ret = copy_from_user(exec2_list, | |
2bb4629a | 1514 | to_user_ptr(args->buffers_ptr), |
54cf91dc CW |
1515 | sizeof(*exec2_list) * args->buffer_count); |
1516 | if (ret != 0) { | |
ff240199 | 1517 | DRM_DEBUG("copy %d exec entries failed %d\n", |
54cf91dc CW |
1518 | args->buffer_count, ret); |
1519 | drm_free_large(exec2_list); | |
1520 | return -EFAULT; | |
1521 | } | |
1522 | ||
41bde553 | 1523 | ret = i915_gem_do_execbuffer(dev, data, file, args, exec2_list); |
54cf91dc CW |
1524 | if (!ret) { |
1525 | /* Copy the new buffer offsets back to the user's exec list. */ | |
d593d992 | 1526 | struct drm_i915_gem_exec_object2 __user *user_exec_list = |
9aab8bff CW |
1527 | to_user_ptr(args->buffers_ptr); |
1528 | int i; | |
1529 | ||
1530 | for (i = 0; i < args->buffer_count; i++) { | |
1531 | ret = __copy_to_user(&user_exec_list[i].offset, | |
1532 | &exec2_list[i].offset, | |
1533 | sizeof(user_exec_list[i].offset)); | |
1534 | if (ret) { | |
1535 | ret = -EFAULT; | |
1536 | DRM_DEBUG("failed to copy %d exec entries " | |
1537 | "back to user\n", | |
1538 | args->buffer_count); | |
1539 | break; | |
1540 | } | |
54cf91dc CW |
1541 | } |
1542 | } | |
1543 | ||
1544 | drm_free_large(exec2_list); | |
1545 | return ret; | |
1546 | } |