]>
Commit | Line | Data |
---|---|---|
76aaf220 DV |
1 | /* |
2 | * Copyright © 2010 Daniel Vetter | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | */ | |
24 | ||
760285e7 DH |
25 | #include <drm/drmP.h> |
26 | #include <drm/i915_drm.h> | |
76aaf220 DV |
27 | #include "i915_drv.h" |
28 | #include "i915_trace.h" | |
29 | #include "intel_drv.h" | |
30 | ||
26b1ff35 BW |
31 | /* PPGTT stuff */ |
32 | #define GEN6_GTT_ADDR_ENCODE(addr) ((addr) | (((addr) >> 28) & 0xff0)) | |
33 | ||
34 | #define GEN6_PDE_VALID (1 << 0) | |
35 | /* gen6+ has bit 11-4 for physical addr bit 39-32 */ | |
36 | #define GEN6_PDE_ADDR_ENCODE(addr) GEN6_GTT_ADDR_ENCODE(addr) | |
37 | ||
38 | #define GEN6_PTE_VALID (1 << 0) | |
39 | #define GEN6_PTE_UNCACHED (1 << 1) | |
40 | #define HSW_PTE_UNCACHED (0) | |
41 | #define GEN6_PTE_CACHE_LLC (2 << 1) | |
42 | #define GEN6_PTE_CACHE_LLC_MLC (3 << 1) | |
43 | #define GEN6_PTE_ADDR_ENCODE(addr) GEN6_GTT_ADDR_ENCODE(addr) | |
44 | ||
2d04befb KG |
45 | static gen6_gtt_pte_t gen6_pte_encode(struct drm_device *dev, |
46 | dma_addr_t addr, | |
47 | enum i915_cache_level level) | |
54d12527 | 48 | { |
e7c2b58b | 49 | gen6_gtt_pte_t pte = GEN6_PTE_VALID; |
54d12527 | 50 | pte |= GEN6_PTE_ADDR_ENCODE(addr); |
e7210c3c BW |
51 | |
52 | switch (level) { | |
53 | case I915_CACHE_LLC_MLC: | |
9119708c | 54 | pte |= GEN6_PTE_CACHE_LLC_MLC; |
e7210c3c BW |
55 | break; |
56 | case I915_CACHE_LLC: | |
57 | pte |= GEN6_PTE_CACHE_LLC; | |
58 | break; | |
59 | case I915_CACHE_NONE: | |
9119708c | 60 | pte |= GEN6_PTE_UNCACHED; |
e7210c3c BW |
61 | break; |
62 | default: | |
63 | BUG(); | |
64 | } | |
65 | ||
54d12527 BW |
66 | return pte; |
67 | } | |
68 | ||
93c34e70 KG |
69 | #define BYT_PTE_WRITEABLE (1 << 1) |
70 | #define BYT_PTE_SNOOPED_BY_CPU_CACHES (1 << 2) | |
71 | ||
72 | static gen6_gtt_pte_t byt_pte_encode(struct drm_device *dev, | |
73 | dma_addr_t addr, | |
74 | enum i915_cache_level level) | |
75 | { | |
76 | gen6_gtt_pte_t pte = GEN6_PTE_VALID; | |
77 | pte |= GEN6_PTE_ADDR_ENCODE(addr); | |
78 | ||
79 | /* Mark the page as writeable. Other platforms don't have a | |
80 | * setting for read-only/writable, so this matches that behavior. | |
81 | */ | |
82 | pte |= BYT_PTE_WRITEABLE; | |
83 | ||
84 | if (level != I915_CACHE_NONE) | |
85 | pte |= BYT_PTE_SNOOPED_BY_CPU_CACHES; | |
86 | ||
87 | return pte; | |
88 | } | |
89 | ||
9119708c KG |
90 | static gen6_gtt_pte_t hsw_pte_encode(struct drm_device *dev, |
91 | dma_addr_t addr, | |
92 | enum i915_cache_level level) | |
93 | { | |
94 | gen6_gtt_pte_t pte = GEN6_PTE_VALID; | |
95 | pte |= GEN6_PTE_ADDR_ENCODE(addr); | |
96 | ||
97 | if (level != I915_CACHE_NONE) | |
98 | pte |= GEN6_PTE_CACHE_LLC; | |
99 | ||
100 | return pte; | |
101 | } | |
102 | ||
3e302542 | 103 | static void gen6_write_pdes(struct i915_hw_ppgtt *ppgtt) |
6197349b | 104 | { |
3e302542 | 105 | struct drm_i915_private *dev_priv = ppgtt->dev->dev_private; |
6197349b BW |
106 | gen6_gtt_pte_t __iomem *pd_addr; |
107 | uint32_t pd_entry; | |
108 | int i; | |
109 | ||
0a732870 | 110 | WARN_ON(ppgtt->pd_offset & 0x3f); |
6197349b BW |
111 | pd_addr = (gen6_gtt_pte_t __iomem*)dev_priv->gtt.gsm + |
112 | ppgtt->pd_offset / sizeof(gen6_gtt_pte_t); | |
113 | for (i = 0; i < ppgtt->num_pd_entries; i++) { | |
114 | dma_addr_t pt_addr; | |
115 | ||
116 | pt_addr = ppgtt->pt_dma_addr[i]; | |
117 | pd_entry = GEN6_PDE_ADDR_ENCODE(pt_addr); | |
118 | pd_entry |= GEN6_PDE_VALID; | |
119 | ||
120 | writel(pd_entry, pd_addr + i); | |
121 | } | |
122 | readl(pd_addr); | |
3e302542 BW |
123 | } |
124 | ||
125 | static int gen6_ppgtt_enable(struct drm_device *dev) | |
126 | { | |
127 | drm_i915_private_t *dev_priv = dev->dev_private; | |
128 | uint32_t pd_offset; | |
129 | struct intel_ring_buffer *ring; | |
130 | struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt; | |
131 | int i; | |
132 | ||
133 | BUG_ON(ppgtt->pd_offset & 0x3f); | |
134 | ||
135 | gen6_write_pdes(ppgtt); | |
6197349b BW |
136 | |
137 | pd_offset = ppgtt->pd_offset; | |
138 | pd_offset /= 64; /* in cachelines, */ | |
139 | pd_offset <<= 16; | |
140 | ||
141 | if (INTEL_INFO(dev)->gen == 6) { | |
142 | uint32_t ecochk, gab_ctl, ecobits; | |
143 | ||
144 | ecobits = I915_READ(GAC_ECO_BITS); | |
3b9d7888 VS |
145 | I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_SNB_BIT | |
146 | ECOBITS_PPGTT_CACHE64B); | |
6197349b BW |
147 | |
148 | gab_ctl = I915_READ(GAB_CTL); | |
149 | I915_WRITE(GAB_CTL, gab_ctl | GAB_CTL_CONT_AFTER_PAGEFAULT); | |
150 | ||
151 | ecochk = I915_READ(GAM_ECOCHK); | |
152 | I915_WRITE(GAM_ECOCHK, ecochk | ECOCHK_SNB_BIT | | |
153 | ECOCHK_PPGTT_CACHE64B); | |
154 | I915_WRITE(GFX_MODE, _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE)); | |
155 | } else if (INTEL_INFO(dev)->gen >= 7) { | |
a6f429a5 | 156 | uint32_t ecochk, ecobits; |
a65c2fcd VS |
157 | |
158 | ecobits = I915_READ(GAC_ECO_BITS); | |
159 | I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_PPGTT_CACHE64B); | |
160 | ||
a6f429a5 VS |
161 | ecochk = I915_READ(GAM_ECOCHK); |
162 | if (IS_HASWELL(dev)) { | |
163 | ecochk |= ECOCHK_PPGTT_WB_HSW; | |
164 | } else { | |
165 | ecochk |= ECOCHK_PPGTT_LLC_IVB; | |
166 | ecochk &= ~ECOCHK_PPGTT_GFDT_IVB; | |
167 | } | |
168 | I915_WRITE(GAM_ECOCHK, ecochk); | |
6197349b BW |
169 | /* GFX_MODE is per-ring on gen7+ */ |
170 | } | |
171 | ||
172 | for_each_ring(ring, dev_priv, i) { | |
173 | if (INTEL_INFO(dev)->gen >= 7) | |
174 | I915_WRITE(RING_MODE_GEN7(ring), | |
175 | _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE)); | |
176 | ||
177 | I915_WRITE(RING_PP_DIR_DCLV(ring), PP_DIR_DCLV_2G); | |
178 | I915_WRITE(RING_PP_DIR_BASE(ring), pd_offset); | |
179 | } | |
b7c36d25 | 180 | return 0; |
6197349b BW |
181 | } |
182 | ||
1d2a314c | 183 | /* PPGTT support for Sandybdrige/Gen6 and later */ |
def886c3 | 184 | static void gen6_ppgtt_clear_range(struct i915_hw_ppgtt *ppgtt, |
1d2a314c DV |
185 | unsigned first_entry, |
186 | unsigned num_entries) | |
187 | { | |
e7c2b58b | 188 | gen6_gtt_pte_t *pt_vaddr, scratch_pte; |
a15326a5 | 189 | unsigned act_pt = first_entry / I915_PPGTT_PT_ENTRIES; |
7bddb01f DV |
190 | unsigned first_pte = first_entry % I915_PPGTT_PT_ENTRIES; |
191 | unsigned last_pte, i; | |
1d2a314c | 192 | |
2d04befb KG |
193 | scratch_pte = ppgtt->pte_encode(ppgtt->dev, |
194 | ppgtt->scratch_page_dma_addr, | |
195 | I915_CACHE_LLC); | |
1d2a314c | 196 | |
7bddb01f DV |
197 | while (num_entries) { |
198 | last_pte = first_pte + num_entries; | |
199 | if (last_pte > I915_PPGTT_PT_ENTRIES) | |
200 | last_pte = I915_PPGTT_PT_ENTRIES; | |
201 | ||
a15326a5 | 202 | pt_vaddr = kmap_atomic(ppgtt->pt_pages[act_pt]); |
1d2a314c | 203 | |
7bddb01f DV |
204 | for (i = first_pte; i < last_pte; i++) |
205 | pt_vaddr[i] = scratch_pte; | |
1d2a314c DV |
206 | |
207 | kunmap_atomic(pt_vaddr); | |
1d2a314c | 208 | |
7bddb01f DV |
209 | num_entries -= last_pte - first_pte; |
210 | first_pte = 0; | |
a15326a5 | 211 | act_pt++; |
7bddb01f | 212 | } |
1d2a314c DV |
213 | } |
214 | ||
def886c3 DV |
215 | static void gen6_ppgtt_insert_entries(struct i915_hw_ppgtt *ppgtt, |
216 | struct sg_table *pages, | |
217 | unsigned first_entry, | |
218 | enum i915_cache_level cache_level) | |
219 | { | |
e7c2b58b | 220 | gen6_gtt_pte_t *pt_vaddr; |
a15326a5 | 221 | unsigned act_pt = first_entry / I915_PPGTT_PT_ENTRIES; |
6e995e23 ID |
222 | unsigned act_pte = first_entry % I915_PPGTT_PT_ENTRIES; |
223 | struct sg_page_iter sg_iter; | |
224 | ||
a15326a5 | 225 | pt_vaddr = kmap_atomic(ppgtt->pt_pages[act_pt]); |
6e995e23 ID |
226 | for_each_sg_page(pages->sgl, &sg_iter, pages->nents, 0) { |
227 | dma_addr_t page_addr; | |
228 | ||
2db76d7c | 229 | page_addr = sg_page_iter_dma_address(&sg_iter); |
2d04befb KG |
230 | pt_vaddr[act_pte] = ppgtt->pte_encode(ppgtt->dev, page_addr, |
231 | cache_level); | |
6e995e23 ID |
232 | if (++act_pte == I915_PPGTT_PT_ENTRIES) { |
233 | kunmap_atomic(pt_vaddr); | |
a15326a5 DV |
234 | act_pt++; |
235 | pt_vaddr = kmap_atomic(ppgtt->pt_pages[act_pt]); | |
6e995e23 | 236 | act_pte = 0; |
def886c3 | 237 | |
def886c3 | 238 | } |
def886c3 | 239 | } |
6e995e23 | 240 | kunmap_atomic(pt_vaddr); |
def886c3 DV |
241 | } |
242 | ||
3440d265 | 243 | static void gen6_ppgtt_cleanup(struct i915_hw_ppgtt *ppgtt) |
1d2a314c | 244 | { |
3440d265 DV |
245 | int i; |
246 | ||
247 | if (ppgtt->pt_dma_addr) { | |
248 | for (i = 0; i < ppgtt->num_pd_entries; i++) | |
249 | pci_unmap_page(ppgtt->dev->pdev, | |
250 | ppgtt->pt_dma_addr[i], | |
251 | 4096, PCI_DMA_BIDIRECTIONAL); | |
252 | } | |
253 | ||
254 | kfree(ppgtt->pt_dma_addr); | |
255 | for (i = 0; i < ppgtt->num_pd_entries; i++) | |
256 | __free_page(ppgtt->pt_pages[i]); | |
257 | kfree(ppgtt->pt_pages); | |
258 | kfree(ppgtt); | |
259 | } | |
260 | ||
261 | static int gen6_ppgtt_init(struct i915_hw_ppgtt *ppgtt) | |
262 | { | |
263 | struct drm_device *dev = ppgtt->dev; | |
1d2a314c | 264 | struct drm_i915_private *dev_priv = dev->dev_private; |
1d2a314c | 265 | unsigned first_pd_entry_in_global_pt; |
1d2a314c DV |
266 | int i; |
267 | int ret = -ENOMEM; | |
268 | ||
269 | /* ppgtt PDEs reside in the global gtt pagetable, which has 512*1024 | |
270 | * entries. For aliasing ppgtt support we just steal them at the end for | |
271 | * now. */ | |
e1b73cba | 272 | first_pd_entry_in_global_pt = gtt_total_entries(dev_priv->gtt); |
1d2a314c | 273 | |
9119708c KG |
274 | if (IS_HASWELL(dev)) { |
275 | ppgtt->pte_encode = hsw_pte_encode; | |
276 | } else if (IS_VALLEYVIEW(dev)) { | |
93c34e70 KG |
277 | ppgtt->pte_encode = byt_pte_encode; |
278 | } else { | |
279 | ppgtt->pte_encode = gen6_pte_encode; | |
280 | } | |
1d2a314c | 281 | ppgtt->num_pd_entries = I915_PPGTT_PD_ENTRIES; |
6197349b | 282 | ppgtt->enable = gen6_ppgtt_enable; |
def886c3 DV |
283 | ppgtt->clear_range = gen6_ppgtt_clear_range; |
284 | ppgtt->insert_entries = gen6_ppgtt_insert_entries; | |
3440d265 | 285 | ppgtt->cleanup = gen6_ppgtt_cleanup; |
1d2a314c DV |
286 | ppgtt->pt_pages = kzalloc(sizeof(struct page *)*ppgtt->num_pd_entries, |
287 | GFP_KERNEL); | |
288 | if (!ppgtt->pt_pages) | |
3440d265 | 289 | return -ENOMEM; |
1d2a314c DV |
290 | |
291 | for (i = 0; i < ppgtt->num_pd_entries; i++) { | |
292 | ppgtt->pt_pages[i] = alloc_page(GFP_KERNEL); | |
293 | if (!ppgtt->pt_pages[i]) | |
294 | goto err_pt_alloc; | |
295 | } | |
296 | ||
8d2e6308 BW |
297 | ppgtt->pt_dma_addr = kzalloc(sizeof(dma_addr_t) *ppgtt->num_pd_entries, |
298 | GFP_KERNEL); | |
299 | if (!ppgtt->pt_dma_addr) | |
300 | goto err_pt_alloc; | |
1d2a314c | 301 | |
8d2e6308 BW |
302 | for (i = 0; i < ppgtt->num_pd_entries; i++) { |
303 | dma_addr_t pt_addr; | |
211c568b | 304 | |
8d2e6308 BW |
305 | pt_addr = pci_map_page(dev->pdev, ppgtt->pt_pages[i], 0, 4096, |
306 | PCI_DMA_BIDIRECTIONAL); | |
1d2a314c | 307 | |
8d2e6308 BW |
308 | if (pci_dma_mapping_error(dev->pdev, pt_addr)) { |
309 | ret = -EIO; | |
310 | goto err_pd_pin; | |
1d2a314c | 311 | |
211c568b | 312 | } |
8d2e6308 | 313 | ppgtt->pt_dma_addr[i] = pt_addr; |
1d2a314c | 314 | } |
1d2a314c | 315 | |
def886c3 DV |
316 | ppgtt->clear_range(ppgtt, 0, |
317 | ppgtt->num_pd_entries*I915_PPGTT_PT_ENTRIES); | |
1d2a314c | 318 | |
e7c2b58b | 319 | ppgtt->pd_offset = first_pd_entry_in_global_pt * sizeof(gen6_gtt_pte_t); |
1d2a314c | 320 | |
1d2a314c DV |
321 | return 0; |
322 | ||
323 | err_pd_pin: | |
324 | if (ppgtt->pt_dma_addr) { | |
325 | for (i--; i >= 0; i--) | |
326 | pci_unmap_page(dev->pdev, ppgtt->pt_dma_addr[i], | |
327 | 4096, PCI_DMA_BIDIRECTIONAL); | |
328 | } | |
329 | err_pt_alloc: | |
330 | kfree(ppgtt->pt_dma_addr); | |
331 | for (i = 0; i < ppgtt->num_pd_entries; i++) { | |
332 | if (ppgtt->pt_pages[i]) | |
333 | __free_page(ppgtt->pt_pages[i]); | |
334 | } | |
335 | kfree(ppgtt->pt_pages); | |
3440d265 DV |
336 | |
337 | return ret; | |
338 | } | |
339 | ||
340 | static int i915_gem_init_aliasing_ppgtt(struct drm_device *dev) | |
341 | { | |
342 | struct drm_i915_private *dev_priv = dev->dev_private; | |
343 | struct i915_hw_ppgtt *ppgtt; | |
344 | int ret; | |
345 | ||
346 | ppgtt = kzalloc(sizeof(*ppgtt), GFP_KERNEL); | |
347 | if (!ppgtt) | |
348 | return -ENOMEM; | |
349 | ||
350 | ppgtt->dev = dev; | |
1e7d12d4 | 351 | ppgtt->scratch_page_dma_addr = dev_priv->gtt.scratch_page_dma; |
3440d265 | 352 | |
3ed124b2 BW |
353 | if (INTEL_INFO(dev)->gen < 8) |
354 | ret = gen6_ppgtt_init(ppgtt); | |
355 | else | |
356 | BUG(); | |
357 | ||
3440d265 DV |
358 | if (ret) |
359 | kfree(ppgtt); | |
360 | else | |
361 | dev_priv->mm.aliasing_ppgtt = ppgtt; | |
1d2a314c DV |
362 | |
363 | return ret; | |
364 | } | |
365 | ||
366 | void i915_gem_cleanup_aliasing_ppgtt(struct drm_device *dev) | |
367 | { | |
368 | struct drm_i915_private *dev_priv = dev->dev_private; | |
369 | struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt; | |
1d2a314c DV |
370 | |
371 | if (!ppgtt) | |
372 | return; | |
373 | ||
3440d265 | 374 | ppgtt->cleanup(ppgtt); |
5963cf04 | 375 | dev_priv->mm.aliasing_ppgtt = NULL; |
1d2a314c DV |
376 | } |
377 | ||
7bddb01f DV |
378 | void i915_ppgtt_bind_object(struct i915_hw_ppgtt *ppgtt, |
379 | struct drm_i915_gem_object *obj, | |
380 | enum i915_cache_level cache_level) | |
381 | { | |
def886c3 DV |
382 | ppgtt->insert_entries(ppgtt, obj->pages, |
383 | obj->gtt_space->start >> PAGE_SHIFT, | |
384 | cache_level); | |
7bddb01f DV |
385 | } |
386 | ||
387 | void i915_ppgtt_unbind_object(struct i915_hw_ppgtt *ppgtt, | |
388 | struct drm_i915_gem_object *obj) | |
389 | { | |
def886c3 DV |
390 | ppgtt->clear_range(ppgtt, |
391 | obj->gtt_space->start >> PAGE_SHIFT, | |
392 | obj->base.size >> PAGE_SHIFT); | |
7bddb01f DV |
393 | } |
394 | ||
a81cc00c BW |
395 | extern int intel_iommu_gfx_mapped; |
396 | /* Certain Gen5 chipsets require require idling the GPU before | |
397 | * unmapping anything from the GTT when VT-d is enabled. | |
398 | */ | |
399 | static inline bool needs_idle_maps(struct drm_device *dev) | |
400 | { | |
401 | #ifdef CONFIG_INTEL_IOMMU | |
402 | /* Query intel_iommu to see if we need the workaround. Presumably that | |
403 | * was loaded first. | |
404 | */ | |
405 | if (IS_GEN5(dev) && IS_MOBILE(dev) && intel_iommu_gfx_mapped) | |
406 | return true; | |
407 | #endif | |
408 | return false; | |
409 | } | |
410 | ||
5c042287 BW |
411 | static bool do_idling(struct drm_i915_private *dev_priv) |
412 | { | |
413 | bool ret = dev_priv->mm.interruptible; | |
414 | ||
a81cc00c | 415 | if (unlikely(dev_priv->gtt.do_idle_maps)) { |
5c042287 | 416 | dev_priv->mm.interruptible = false; |
b2da9fe5 | 417 | if (i915_gpu_idle(dev_priv->dev)) { |
5c042287 BW |
418 | DRM_ERROR("Couldn't idle GPU\n"); |
419 | /* Wait a bit, in hopes it avoids the hang */ | |
420 | udelay(10); | |
421 | } | |
422 | } | |
423 | ||
424 | return ret; | |
425 | } | |
426 | ||
427 | static void undo_idling(struct drm_i915_private *dev_priv, bool interruptible) | |
428 | { | |
a81cc00c | 429 | if (unlikely(dev_priv->gtt.do_idle_maps)) |
5c042287 BW |
430 | dev_priv->mm.interruptible = interruptible; |
431 | } | |
432 | ||
76aaf220 DV |
433 | void i915_gem_restore_gtt_mappings(struct drm_device *dev) |
434 | { | |
435 | struct drm_i915_private *dev_priv = dev->dev_private; | |
05394f39 | 436 | struct drm_i915_gem_object *obj; |
76aaf220 | 437 | |
bee4a186 | 438 | /* First fill our portion of the GTT with scratch pages */ |
7faf1ab2 DV |
439 | dev_priv->gtt.gtt_clear_range(dev, dev_priv->gtt.start / PAGE_SIZE, |
440 | dev_priv->gtt.total / PAGE_SIZE); | |
bee4a186 | 441 | |
6c085a72 | 442 | list_for_each_entry(obj, &dev_priv->mm.bound_list, gtt_list) { |
a8e93126 | 443 | i915_gem_clflush_object(obj); |
74163907 | 444 | i915_gem_gtt_bind_object(obj, obj->cache_level); |
76aaf220 DV |
445 | } |
446 | ||
e76e9aeb | 447 | i915_gem_chipset_flush(dev); |
76aaf220 | 448 | } |
7c2e6fdf | 449 | |
74163907 | 450 | int i915_gem_gtt_prepare_object(struct drm_i915_gem_object *obj) |
7c2e6fdf | 451 | { |
9da3da66 | 452 | if (obj->has_dma_mapping) |
74163907 | 453 | return 0; |
9da3da66 CW |
454 | |
455 | if (!dma_map_sg(&obj->base.dev->pdev->dev, | |
456 | obj->pages->sgl, obj->pages->nents, | |
457 | PCI_DMA_BIDIRECTIONAL)) | |
458 | return -ENOSPC; | |
459 | ||
460 | return 0; | |
7c2e6fdf DV |
461 | } |
462 | ||
e76e9aeb BW |
463 | /* |
464 | * Binds an object into the global gtt with the specified cache level. The object | |
465 | * will be accessible to the GPU via commands whose operands reference offsets | |
466 | * within the global GTT as well as accessible by the GPU through the GMADR | |
467 | * mapped BAR (dev_priv->mm.gtt->gtt). | |
468 | */ | |
7faf1ab2 DV |
469 | static void gen6_ggtt_insert_entries(struct drm_device *dev, |
470 | struct sg_table *st, | |
471 | unsigned int first_entry, | |
472 | enum i915_cache_level level) | |
e76e9aeb | 473 | { |
e76e9aeb | 474 | struct drm_i915_private *dev_priv = dev->dev_private; |
e7c2b58b BW |
475 | gen6_gtt_pte_t __iomem *gtt_entries = |
476 | (gen6_gtt_pte_t __iomem *)dev_priv->gtt.gsm + first_entry; | |
6e995e23 ID |
477 | int i = 0; |
478 | struct sg_page_iter sg_iter; | |
e76e9aeb BW |
479 | dma_addr_t addr; |
480 | ||
6e995e23 | 481 | for_each_sg_page(st->sgl, &sg_iter, st->nents, 0) { |
2db76d7c | 482 | addr = sg_page_iter_dma_address(&sg_iter); |
2d04befb KG |
483 | iowrite32(dev_priv->gtt.pte_encode(dev, addr, level), |
484 | >t_entries[i]); | |
6e995e23 | 485 | i++; |
e76e9aeb BW |
486 | } |
487 | ||
e76e9aeb BW |
488 | /* XXX: This serves as a posting read to make sure that the PTE has |
489 | * actually been updated. There is some concern that even though | |
490 | * registers and PTEs are within the same BAR that they are potentially | |
491 | * of NUMA access patterns. Therefore, even with the way we assume | |
492 | * hardware should work, we must keep this posting read for paranoia. | |
493 | */ | |
494 | if (i != 0) | |
960e3e42 | 495 | WARN_ON(readl(>t_entries[i-1]) |
2d04befb | 496 | != dev_priv->gtt.pte_encode(dev, addr, level)); |
0f9b91c7 BW |
497 | |
498 | /* This next bit makes the above posting read even more important. We | |
499 | * want to flush the TLBs only after we're certain all the PTE updates | |
500 | * have finished. | |
501 | */ | |
502 | I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN); | |
503 | POSTING_READ(GFX_FLSH_CNTL_GEN6); | |
e76e9aeb BW |
504 | } |
505 | ||
7faf1ab2 DV |
506 | static void gen6_ggtt_clear_range(struct drm_device *dev, |
507 | unsigned int first_entry, | |
508 | unsigned int num_entries) | |
509 | { | |
510 | struct drm_i915_private *dev_priv = dev->dev_private; | |
e7c2b58b BW |
511 | gen6_gtt_pte_t scratch_pte, __iomem *gtt_base = |
512 | (gen6_gtt_pte_t __iomem *) dev_priv->gtt.gsm + first_entry; | |
a54c0c27 | 513 | const int max_entries = gtt_total_entries(dev_priv->gtt) - first_entry; |
7faf1ab2 DV |
514 | int i; |
515 | ||
516 | if (WARN(num_entries > max_entries, | |
517 | "First entry = %d; Num entries = %d (max=%d)\n", | |
518 | first_entry, num_entries, max_entries)) | |
519 | num_entries = max_entries; | |
520 | ||
2d04befb KG |
521 | scratch_pte = dev_priv->gtt.pte_encode(dev, |
522 | dev_priv->gtt.scratch_page_dma, | |
523 | I915_CACHE_LLC); | |
7faf1ab2 DV |
524 | for (i = 0; i < num_entries; i++) |
525 | iowrite32(scratch_pte, >t_base[i]); | |
526 | readl(gtt_base); | |
527 | } | |
528 | ||
529 | ||
530 | static void i915_ggtt_insert_entries(struct drm_device *dev, | |
531 | struct sg_table *st, | |
532 | unsigned int pg_start, | |
533 | enum i915_cache_level cache_level) | |
534 | { | |
535 | unsigned int flags = (cache_level == I915_CACHE_NONE) ? | |
536 | AGP_USER_MEMORY : AGP_USER_CACHED_MEMORY; | |
537 | ||
538 | intel_gtt_insert_sg_entries(st, pg_start, flags); | |
539 | ||
540 | } | |
541 | ||
542 | static void i915_ggtt_clear_range(struct drm_device *dev, | |
543 | unsigned int first_entry, | |
544 | unsigned int num_entries) | |
545 | { | |
546 | intel_gtt_clear_range(first_entry, num_entries); | |
547 | } | |
548 | ||
549 | ||
74163907 DV |
550 | void i915_gem_gtt_bind_object(struct drm_i915_gem_object *obj, |
551 | enum i915_cache_level cache_level) | |
d5bd1449 CW |
552 | { |
553 | struct drm_device *dev = obj->base.dev; | |
7faf1ab2 DV |
554 | struct drm_i915_private *dev_priv = dev->dev_private; |
555 | ||
556 | dev_priv->gtt.gtt_insert_entries(dev, obj->pages, | |
557 | obj->gtt_space->start >> PAGE_SHIFT, | |
558 | cache_level); | |
d5bd1449 | 559 | |
74898d7e | 560 | obj->has_global_gtt_mapping = 1; |
d5bd1449 CW |
561 | } |
562 | ||
05394f39 | 563 | void i915_gem_gtt_unbind_object(struct drm_i915_gem_object *obj) |
74163907 | 564 | { |
7faf1ab2 DV |
565 | struct drm_device *dev = obj->base.dev; |
566 | struct drm_i915_private *dev_priv = dev->dev_private; | |
567 | ||
568 | dev_priv->gtt.gtt_clear_range(obj->base.dev, | |
569 | obj->gtt_space->start >> PAGE_SHIFT, | |
570 | obj->base.size >> PAGE_SHIFT); | |
74898d7e DV |
571 | |
572 | obj->has_global_gtt_mapping = 0; | |
74163907 DV |
573 | } |
574 | ||
575 | void i915_gem_gtt_finish_object(struct drm_i915_gem_object *obj) | |
7c2e6fdf | 576 | { |
5c042287 BW |
577 | struct drm_device *dev = obj->base.dev; |
578 | struct drm_i915_private *dev_priv = dev->dev_private; | |
579 | bool interruptible; | |
580 | ||
581 | interruptible = do_idling(dev_priv); | |
582 | ||
9da3da66 CW |
583 | if (!obj->has_dma_mapping) |
584 | dma_unmap_sg(&dev->pdev->dev, | |
585 | obj->pages->sgl, obj->pages->nents, | |
586 | PCI_DMA_BIDIRECTIONAL); | |
5c042287 BW |
587 | |
588 | undo_idling(dev_priv, interruptible); | |
7c2e6fdf | 589 | } |
644ec02b | 590 | |
42d6ab48 CW |
591 | static void i915_gtt_color_adjust(struct drm_mm_node *node, |
592 | unsigned long color, | |
593 | unsigned long *start, | |
594 | unsigned long *end) | |
595 | { | |
596 | if (node->color != color) | |
597 | *start += 4096; | |
598 | ||
599 | if (!list_empty(&node->node_list)) { | |
600 | node = list_entry(node->node_list.next, | |
601 | struct drm_mm_node, | |
602 | node_list); | |
603 | if (node->allocated && node->color != color) | |
604 | *end -= 4096; | |
605 | } | |
606 | } | |
d7e5008f BW |
607 | void i915_gem_setup_global_gtt(struct drm_device *dev, |
608 | unsigned long start, | |
609 | unsigned long mappable_end, | |
610 | unsigned long end) | |
644ec02b | 611 | { |
e78891ca BW |
612 | /* Let GEM Manage all of the aperture. |
613 | * | |
614 | * However, leave one page at the end still bound to the scratch page. | |
615 | * There are a number of places where the hardware apparently prefetches | |
616 | * past the end of the object, and we've seen multiple hangs with the | |
617 | * GPU head pointer stuck in a batchbuffer bound at the last page of the | |
618 | * aperture. One page should be enough to keep any prefetching inside | |
619 | * of the aperture. | |
620 | */ | |
644ec02b | 621 | drm_i915_private_t *dev_priv = dev->dev_private; |
ed2f3452 CW |
622 | struct drm_mm_node *entry; |
623 | struct drm_i915_gem_object *obj; | |
624 | unsigned long hole_start, hole_end; | |
644ec02b | 625 | |
35451cb6 BW |
626 | BUG_ON(mappable_end > end); |
627 | ||
ed2f3452 | 628 | /* Subtract the guard page ... */ |
d1dd20a9 | 629 | drm_mm_init(&dev_priv->mm.gtt_space, start, end - start - PAGE_SIZE); |
42d6ab48 CW |
630 | if (!HAS_LLC(dev)) |
631 | dev_priv->mm.gtt_space.color_adjust = i915_gtt_color_adjust; | |
644ec02b | 632 | |
ed2f3452 CW |
633 | /* Mark any preallocated objects as occupied */ |
634 | list_for_each_entry(obj, &dev_priv->mm.bound_list, gtt_list) { | |
635 | DRM_DEBUG_KMS("reserving preallocated space: %x + %zx\n", | |
636 | obj->gtt_offset, obj->base.size); | |
637 | ||
638 | BUG_ON(obj->gtt_space != I915_GTT_RESERVED); | |
639 | obj->gtt_space = drm_mm_create_block(&dev_priv->mm.gtt_space, | |
640 | obj->gtt_offset, | |
641 | obj->base.size, | |
642 | false); | |
643 | obj->has_global_gtt_mapping = 1; | |
644 | } | |
645 | ||
5d4545ae | 646 | dev_priv->gtt.start = start; |
5d4545ae | 647 | dev_priv->gtt.total = end - start; |
644ec02b | 648 | |
ed2f3452 CW |
649 | /* Clear any non-preallocated blocks */ |
650 | drm_mm_for_each_hole(entry, &dev_priv->mm.gtt_space, | |
651 | hole_start, hole_end) { | |
652 | DRM_DEBUG_KMS("clearing unused GTT space: [%lx, %lx]\n", | |
653 | hole_start, hole_end); | |
7faf1ab2 DV |
654 | dev_priv->gtt.gtt_clear_range(dev, hole_start / PAGE_SIZE, |
655 | (hole_end-hole_start) / PAGE_SIZE); | |
ed2f3452 CW |
656 | } |
657 | ||
658 | /* And finally clear the reserved guard page */ | |
7faf1ab2 | 659 | dev_priv->gtt.gtt_clear_range(dev, end / PAGE_SIZE - 1, 1); |
e76e9aeb BW |
660 | } |
661 | ||
d7e5008f BW |
662 | static bool |
663 | intel_enable_ppgtt(struct drm_device *dev) | |
664 | { | |
665 | if (i915_enable_ppgtt >= 0) | |
666 | return i915_enable_ppgtt; | |
667 | ||
668 | #ifdef CONFIG_INTEL_IOMMU | |
669 | /* Disable ppgtt on SNB if VT-d is on. */ | |
670 | if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped) | |
671 | return false; | |
672 | #endif | |
673 | ||
674 | return true; | |
675 | } | |
676 | ||
677 | void i915_gem_init_global_gtt(struct drm_device *dev) | |
678 | { | |
679 | struct drm_i915_private *dev_priv = dev->dev_private; | |
680 | unsigned long gtt_size, mappable_size; | |
d7e5008f | 681 | |
a54c0c27 | 682 | gtt_size = dev_priv->gtt.total; |
93d18799 | 683 | mappable_size = dev_priv->gtt.mappable_end; |
d7e5008f BW |
684 | |
685 | if (intel_enable_ppgtt(dev) && HAS_ALIASING_PPGTT(dev)) { | |
e78891ca | 686 | int ret; |
3eb1c005 BW |
687 | |
688 | if (INTEL_INFO(dev)->gen <= 7) { | |
689 | /* PPGTT pdes are stolen from global gtt ptes, so shrink the | |
690 | * aperture accordingly when using aliasing ppgtt. */ | |
691 | gtt_size -= I915_PPGTT_PD_ENTRIES*PAGE_SIZE; | |
692 | } | |
d7e5008f BW |
693 | |
694 | i915_gem_setup_global_gtt(dev, 0, mappable_size, gtt_size); | |
695 | ||
696 | ret = i915_gem_init_aliasing_ppgtt(dev); | |
e78891ca | 697 | if (!ret) |
d7e5008f | 698 | return; |
e78891ca BW |
699 | |
700 | DRM_ERROR("Aliased PPGTT setup failed %d\n", ret); | |
701 | drm_mm_takedown(&dev_priv->mm.gtt_space); | |
702 | gtt_size += I915_PPGTT_PD_ENTRIES*PAGE_SIZE; | |
d7e5008f | 703 | } |
e78891ca | 704 | i915_gem_setup_global_gtt(dev, 0, mappable_size, gtt_size); |
e76e9aeb BW |
705 | } |
706 | ||
707 | static int setup_scratch_page(struct drm_device *dev) | |
708 | { | |
709 | struct drm_i915_private *dev_priv = dev->dev_private; | |
710 | struct page *page; | |
711 | dma_addr_t dma_addr; | |
712 | ||
713 | page = alloc_page(GFP_KERNEL | GFP_DMA32 | __GFP_ZERO); | |
714 | if (page == NULL) | |
715 | return -ENOMEM; | |
716 | get_page(page); | |
717 | set_pages_uc(page, 1); | |
718 | ||
719 | #ifdef CONFIG_INTEL_IOMMU | |
720 | dma_addr = pci_map_page(dev->pdev, page, 0, PAGE_SIZE, | |
721 | PCI_DMA_BIDIRECTIONAL); | |
722 | if (pci_dma_mapping_error(dev->pdev, dma_addr)) | |
723 | return -EINVAL; | |
724 | #else | |
725 | dma_addr = page_to_phys(page); | |
726 | #endif | |
9c61a32d BW |
727 | dev_priv->gtt.scratch_page = page; |
728 | dev_priv->gtt.scratch_page_dma = dma_addr; | |
e76e9aeb BW |
729 | |
730 | return 0; | |
731 | } | |
732 | ||
733 | static void teardown_scratch_page(struct drm_device *dev) | |
734 | { | |
735 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9c61a32d BW |
736 | set_pages_wb(dev_priv->gtt.scratch_page, 1); |
737 | pci_unmap_page(dev->pdev, dev_priv->gtt.scratch_page_dma, | |
e76e9aeb | 738 | PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); |
9c61a32d BW |
739 | put_page(dev_priv->gtt.scratch_page); |
740 | __free_page(dev_priv->gtt.scratch_page); | |
e76e9aeb BW |
741 | } |
742 | ||
743 | static inline unsigned int gen6_get_total_gtt_size(u16 snb_gmch_ctl) | |
744 | { | |
745 | snb_gmch_ctl >>= SNB_GMCH_GGMS_SHIFT; | |
746 | snb_gmch_ctl &= SNB_GMCH_GGMS_MASK; | |
747 | return snb_gmch_ctl << 20; | |
748 | } | |
749 | ||
baa09f5f | 750 | static inline size_t gen6_get_stolen_size(u16 snb_gmch_ctl) |
e76e9aeb BW |
751 | { |
752 | snb_gmch_ctl >>= SNB_GMCH_GMS_SHIFT; | |
753 | snb_gmch_ctl &= SNB_GMCH_GMS_MASK; | |
754 | return snb_gmch_ctl << 25; /* 32 MB units */ | |
755 | } | |
756 | ||
baa09f5f BW |
757 | static int gen6_gmch_probe(struct drm_device *dev, |
758 | size_t *gtt_total, | |
41907ddc BW |
759 | size_t *stolen, |
760 | phys_addr_t *mappable_base, | |
761 | unsigned long *mappable_end) | |
e76e9aeb BW |
762 | { |
763 | struct drm_i915_private *dev_priv = dev->dev_private; | |
764 | phys_addr_t gtt_bus_addr; | |
baa09f5f | 765 | unsigned int gtt_size; |
e76e9aeb | 766 | u16 snb_gmch_ctl; |
e76e9aeb BW |
767 | int ret; |
768 | ||
41907ddc BW |
769 | *mappable_base = pci_resource_start(dev->pdev, 2); |
770 | *mappable_end = pci_resource_len(dev->pdev, 2); | |
771 | ||
baa09f5f BW |
772 | /* 64/512MB is the current min/max we actually know of, but this is just |
773 | * a coarse sanity check. | |
e76e9aeb | 774 | */ |
41907ddc | 775 | if ((*mappable_end < (64<<20) || (*mappable_end > (512<<20)))) { |
baa09f5f BW |
776 | DRM_ERROR("Unknown GMADR size (%lx)\n", |
777 | dev_priv->gtt.mappable_end); | |
778 | return -ENXIO; | |
e76e9aeb BW |
779 | } |
780 | ||
e76e9aeb BW |
781 | if (!pci_set_dma_mask(dev->pdev, DMA_BIT_MASK(40))) |
782 | pci_set_consistent_dma_mask(dev->pdev, DMA_BIT_MASK(40)); | |
e76e9aeb | 783 | pci_read_config_word(dev->pdev, SNB_GMCH_CTRL, &snb_gmch_ctl); |
baa09f5f | 784 | gtt_size = gen6_get_total_gtt_size(snb_gmch_ctl); |
e76e9aeb | 785 | |
c4ae25ec | 786 | *stolen = gen6_get_stolen_size(snb_gmch_ctl); |
e7c2b58b | 787 | *gtt_total = (gtt_size / sizeof(gen6_gtt_pte_t)) << PAGE_SHIFT; |
e76e9aeb | 788 | |
a93e4161 BW |
789 | /* For Modern GENs the PTEs and register space are split in the BAR */ |
790 | gtt_bus_addr = pci_resource_start(dev->pdev, 0) + | |
791 | (pci_resource_len(dev->pdev, 0) / 2); | |
792 | ||
baa09f5f | 793 | dev_priv->gtt.gsm = ioremap_wc(gtt_bus_addr, gtt_size); |
5d4545ae | 794 | if (!dev_priv->gtt.gsm) { |
e76e9aeb | 795 | DRM_ERROR("Failed to map the gtt page table\n"); |
baa09f5f | 796 | return -ENOMEM; |
e76e9aeb BW |
797 | } |
798 | ||
baa09f5f BW |
799 | ret = setup_scratch_page(dev); |
800 | if (ret) | |
801 | DRM_ERROR("Scratch setup failed\n"); | |
e76e9aeb | 802 | |
7faf1ab2 DV |
803 | dev_priv->gtt.gtt_clear_range = gen6_ggtt_clear_range; |
804 | dev_priv->gtt.gtt_insert_entries = gen6_ggtt_insert_entries; | |
805 | ||
e76e9aeb BW |
806 | return ret; |
807 | } | |
808 | ||
d93c6233 | 809 | static void gen6_gmch_remove(struct drm_device *dev) |
e76e9aeb BW |
810 | { |
811 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5d4545ae | 812 | iounmap(dev_priv->gtt.gsm); |
baa09f5f | 813 | teardown_scratch_page(dev_priv->dev); |
644ec02b | 814 | } |
baa09f5f BW |
815 | |
816 | static int i915_gmch_probe(struct drm_device *dev, | |
817 | size_t *gtt_total, | |
41907ddc BW |
818 | size_t *stolen, |
819 | phys_addr_t *mappable_base, | |
820 | unsigned long *mappable_end) | |
baa09f5f BW |
821 | { |
822 | struct drm_i915_private *dev_priv = dev->dev_private; | |
823 | int ret; | |
824 | ||
baa09f5f BW |
825 | ret = intel_gmch_probe(dev_priv->bridge_dev, dev_priv->dev->pdev, NULL); |
826 | if (!ret) { | |
827 | DRM_ERROR("failed to set up gmch\n"); | |
828 | return -EIO; | |
829 | } | |
830 | ||
41907ddc | 831 | intel_gtt_get(gtt_total, stolen, mappable_base, mappable_end); |
baa09f5f BW |
832 | |
833 | dev_priv->gtt.do_idle_maps = needs_idle_maps(dev_priv->dev); | |
834 | dev_priv->gtt.gtt_clear_range = i915_ggtt_clear_range; | |
835 | dev_priv->gtt.gtt_insert_entries = i915_ggtt_insert_entries; | |
836 | ||
837 | return 0; | |
838 | } | |
839 | ||
840 | static void i915_gmch_remove(struct drm_device *dev) | |
841 | { | |
842 | intel_gmch_remove(); | |
843 | } | |
844 | ||
845 | int i915_gem_gtt_init(struct drm_device *dev) | |
846 | { | |
847 | struct drm_i915_private *dev_priv = dev->dev_private; | |
848 | struct i915_gtt *gtt = &dev_priv->gtt; | |
baa09f5f BW |
849 | int ret; |
850 | ||
baa09f5f BW |
851 | if (INTEL_INFO(dev)->gen <= 5) { |
852 | dev_priv->gtt.gtt_probe = i915_gmch_probe; | |
853 | dev_priv->gtt.gtt_remove = i915_gmch_remove; | |
854 | } else { | |
855 | dev_priv->gtt.gtt_probe = gen6_gmch_probe; | |
856 | dev_priv->gtt.gtt_remove = gen6_gmch_remove; | |
9119708c KG |
857 | if (IS_HASWELL(dev)) { |
858 | dev_priv->gtt.pte_encode = hsw_pte_encode; | |
859 | } else if (IS_VALLEYVIEW(dev)) { | |
93c34e70 KG |
860 | dev_priv->gtt.pte_encode = byt_pte_encode; |
861 | } else { | |
862 | dev_priv->gtt.pte_encode = gen6_pte_encode; | |
863 | } | |
baa09f5f BW |
864 | } |
865 | ||
866 | ret = dev_priv->gtt.gtt_probe(dev, &dev_priv->gtt.total, | |
41907ddc BW |
867 | &dev_priv->gtt.stolen_size, |
868 | >t->mappable_base, | |
869 | >t->mappable_end); | |
a54c0c27 | 870 | if (ret) |
baa09f5f | 871 | return ret; |
baa09f5f | 872 | |
baa09f5f BW |
873 | /* GMADR is the PCI mmio aperture into the global GTT. */ |
874 | DRM_INFO("Memory usable by graphics device = %zdM\n", | |
875 | dev_priv->gtt.total >> 20); | |
876 | DRM_DEBUG_DRIVER("GMADR size = %ldM\n", | |
877 | dev_priv->gtt.mappable_end >> 20); | |
878 | DRM_DEBUG_DRIVER("GTT stolen size = %zdM\n", | |
879 | dev_priv->gtt.stolen_size >> 20); | |
880 | ||
881 | return 0; | |
882 | } |