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05235c53 CW |
1 | /* |
2 | * Copyright © 2008-2015 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | */ | |
24 | ||
fa545cbf | 25 | #include <linux/prefetch.h> |
b52992c0 | 26 | #include <linux/dma-fence-array.h> |
e6017571 IM |
27 | #include <linux/sched.h> |
28 | #include <linux/sched/clock.h> | |
f361bf4a | 29 | #include <linux/sched/signal.h> |
fa545cbf | 30 | |
05235c53 CW |
31 | #include "i915_drv.h" |
32 | ||
f54d1867 | 33 | static const char *i915_fence_get_driver_name(struct dma_fence *fence) |
04769652 CW |
34 | { |
35 | return "i915"; | |
36 | } | |
37 | ||
f54d1867 | 38 | static const char *i915_fence_get_timeline_name(struct dma_fence *fence) |
04769652 | 39 | { |
05506b5b CW |
40 | /* The timeline struct (as part of the ppgtt underneath a context) |
41 | * may be freed when the request is no longer in use by the GPU. | |
42 | * We could extend the life of a context to beyond that of all | |
43 | * fences, possibly keeping the hw resource around indefinitely, | |
44 | * or we just give them a false name. Since | |
45 | * dma_fence_ops.get_timeline_name is a debug feature, the occasional | |
46 | * lie seems justifiable. | |
47 | */ | |
48 | if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &fence->flags)) | |
49 | return "signaled"; | |
50 | ||
73cb9701 | 51 | return to_request(fence)->timeline->common->name; |
04769652 CW |
52 | } |
53 | ||
f54d1867 | 54 | static bool i915_fence_signaled(struct dma_fence *fence) |
04769652 CW |
55 | { |
56 | return i915_gem_request_completed(to_request(fence)); | |
57 | } | |
58 | ||
f54d1867 | 59 | static bool i915_fence_enable_signaling(struct dma_fence *fence) |
04769652 CW |
60 | { |
61 | if (i915_fence_signaled(fence)) | |
62 | return false; | |
63 | ||
f7b02a52 | 64 | intel_engine_enable_signaling(to_request(fence), true); |
9f90ff39 | 65 | return !i915_fence_signaled(fence); |
04769652 CW |
66 | } |
67 | ||
f54d1867 | 68 | static signed long i915_fence_wait(struct dma_fence *fence, |
04769652 | 69 | bool interruptible, |
e95433c7 | 70 | signed long timeout) |
04769652 | 71 | { |
e95433c7 | 72 | return i915_wait_request(to_request(fence), interruptible, timeout); |
04769652 CW |
73 | } |
74 | ||
f54d1867 | 75 | static void i915_fence_release(struct dma_fence *fence) |
04769652 CW |
76 | { |
77 | struct drm_i915_gem_request *req = to_request(fence); | |
78 | ||
fc158405 CW |
79 | /* The request is put onto a RCU freelist (i.e. the address |
80 | * is immediately reused), mark the fences as being freed now. | |
81 | * Otherwise the debugobjects for the fences are only marked as | |
82 | * freed when the slab cache itself is freed, and so we would get | |
83 | * caught trying to reuse dead objects. | |
84 | */ | |
85 | i915_sw_fence_fini(&req->submit); | |
fc158405 | 86 | |
04769652 CW |
87 | kmem_cache_free(req->i915->requests, req); |
88 | } | |
89 | ||
f54d1867 | 90 | const struct dma_fence_ops i915_fence_ops = { |
04769652 CW |
91 | .get_driver_name = i915_fence_get_driver_name, |
92 | .get_timeline_name = i915_fence_get_timeline_name, | |
93 | .enable_signaling = i915_fence_enable_signaling, | |
94 | .signaled = i915_fence_signaled, | |
95 | .wait = i915_fence_wait, | |
96 | .release = i915_fence_release, | |
04769652 CW |
97 | }; |
98 | ||
05235c53 CW |
99 | static inline void |
100 | i915_gem_request_remove_from_client(struct drm_i915_gem_request *request) | |
101 | { | |
c8659efa | 102 | struct drm_i915_file_private *file_priv; |
05235c53 | 103 | |
c8659efa | 104 | file_priv = request->file_priv; |
05235c53 CW |
105 | if (!file_priv) |
106 | return; | |
107 | ||
108 | spin_lock(&file_priv->mm.lock); | |
c8659efa CW |
109 | if (request->file_priv) { |
110 | list_del(&request->client_link); | |
111 | request->file_priv = NULL; | |
112 | } | |
05235c53 | 113 | spin_unlock(&file_priv->mm.lock); |
05235c53 CW |
114 | } |
115 | ||
52e54209 CW |
116 | static struct i915_dependency * |
117 | i915_dependency_alloc(struct drm_i915_private *i915) | |
118 | { | |
119 | return kmem_cache_alloc(i915->dependencies, GFP_KERNEL); | |
120 | } | |
121 | ||
122 | static void | |
123 | i915_dependency_free(struct drm_i915_private *i915, | |
124 | struct i915_dependency *dep) | |
125 | { | |
126 | kmem_cache_free(i915->dependencies, dep); | |
127 | } | |
128 | ||
129 | static void | |
130 | __i915_priotree_add_dependency(struct i915_priotree *pt, | |
131 | struct i915_priotree *signal, | |
132 | struct i915_dependency *dep, | |
133 | unsigned long flags) | |
134 | { | |
20311bd3 | 135 | INIT_LIST_HEAD(&dep->dfs_link); |
52e54209 CW |
136 | list_add(&dep->wait_link, &signal->waiters_list); |
137 | list_add(&dep->signal_link, &pt->signalers_list); | |
138 | dep->signaler = signal; | |
139 | dep->flags = flags; | |
140 | } | |
141 | ||
142 | static int | |
143 | i915_priotree_add_dependency(struct drm_i915_private *i915, | |
144 | struct i915_priotree *pt, | |
145 | struct i915_priotree *signal) | |
146 | { | |
147 | struct i915_dependency *dep; | |
148 | ||
149 | dep = i915_dependency_alloc(i915); | |
150 | if (!dep) | |
151 | return -ENOMEM; | |
152 | ||
153 | __i915_priotree_add_dependency(pt, signal, dep, I915_DEPENDENCY_ALLOC); | |
154 | return 0; | |
155 | } | |
156 | ||
157 | static void | |
158 | i915_priotree_fini(struct drm_i915_private *i915, struct i915_priotree *pt) | |
159 | { | |
160 | struct i915_dependency *dep, *next; | |
161 | ||
6c067579 | 162 | GEM_BUG_ON(!list_empty(&pt->link)); |
20311bd3 | 163 | |
52e54209 CW |
164 | /* Everyone we depended upon (the fences we wait to be signaled) |
165 | * should retire before us and remove themselves from our list. | |
166 | * However, retirement is run independently on each timeline and | |
167 | * so we may be called out-of-order. | |
168 | */ | |
169 | list_for_each_entry_safe(dep, next, &pt->signalers_list, signal_link) { | |
170 | list_del(&dep->wait_link); | |
171 | if (dep->flags & I915_DEPENDENCY_ALLOC) | |
172 | i915_dependency_free(i915, dep); | |
173 | } | |
174 | ||
175 | /* Remove ourselves from everyone who depends upon us */ | |
176 | list_for_each_entry_safe(dep, next, &pt->waiters_list, wait_link) { | |
177 | list_del(&dep->signal_link); | |
178 | if (dep->flags & I915_DEPENDENCY_ALLOC) | |
179 | i915_dependency_free(i915, dep); | |
180 | } | |
181 | } | |
182 | ||
183 | static void | |
184 | i915_priotree_init(struct i915_priotree *pt) | |
185 | { | |
186 | INIT_LIST_HEAD(&pt->signalers_list); | |
187 | INIT_LIST_HEAD(&pt->waiters_list); | |
6c067579 | 188 | INIT_LIST_HEAD(&pt->link); |
20311bd3 | 189 | pt->priority = INT_MIN; |
52e54209 CW |
190 | } |
191 | ||
12d3173b CW |
192 | static int reset_all_global_seqno(struct drm_i915_private *i915, u32 seqno) |
193 | { | |
12d3173b CW |
194 | struct intel_engine_cs *engine; |
195 | enum intel_engine_id id; | |
196 | int ret; | |
197 | ||
198 | /* Carefully retire all requests without writing to the rings */ | |
199 | ret = i915_gem_wait_for_idle(i915, | |
200 | I915_WAIT_INTERRUPTIBLE | | |
201 | I915_WAIT_LOCKED); | |
202 | if (ret) | |
203 | return ret; | |
204 | ||
12d3173b CW |
205 | /* If the seqno wraps around, we need to clear the breadcrumb rbtree */ |
206 | for_each_engine(engine, i915, id) { | |
ae351beb CW |
207 | struct i915_gem_timeline *timeline; |
208 | struct intel_timeline *tl = engine->timeline; | |
12d3173b CW |
209 | |
210 | if (!i915_seqno_passed(seqno, tl->seqno)) { | |
211 | /* spin until threads are complete */ | |
212 | while (intel_breadcrumbs_busy(engine)) | |
213 | cond_resched(); | |
214 | } | |
215 | ||
216 | /* Finally reset hw state */ | |
12d3173b | 217 | intel_engine_init_global_seqno(engine, seqno); |
2ca9faa5 | 218 | tl->seqno = seqno; |
12d3173b | 219 | |
ae351beb | 220 | list_for_each_entry(timeline, &i915->gt.timelines, link) |
7e8894e9 CW |
221 | memset(timeline->engine[id].global_sync, 0, |
222 | sizeof(timeline->engine[id].global_sync)); | |
12d3173b CW |
223 | } |
224 | ||
225 | return 0; | |
226 | } | |
227 | ||
228 | int i915_gem_set_global_seqno(struct drm_device *dev, u32 seqno) | |
229 | { | |
230 | struct drm_i915_private *dev_priv = to_i915(dev); | |
231 | ||
232 | lockdep_assert_held(&dev_priv->drm.struct_mutex); | |
233 | ||
234 | if (seqno == 0) | |
235 | return -EINVAL; | |
236 | ||
237 | /* HWS page needs to be set less than what we | |
238 | * will inject to ring | |
239 | */ | |
240 | return reset_all_global_seqno(dev_priv, seqno - 1); | |
241 | } | |
242 | ||
243 | static int reserve_seqno(struct intel_engine_cs *engine) | |
244 | { | |
245 | u32 active = ++engine->timeline->inflight_seqnos; | |
246 | u32 seqno = engine->timeline->seqno; | |
247 | int ret; | |
248 | ||
249 | /* Reservation is fine until we need to wrap around */ | |
250 | if (likely(!add_overflows(seqno, active))) | |
251 | return 0; | |
252 | ||
253 | ret = reset_all_global_seqno(engine->i915, 0); | |
254 | if (ret) { | |
255 | engine->timeline->inflight_seqnos--; | |
256 | return ret; | |
257 | } | |
258 | ||
259 | return 0; | |
260 | } | |
261 | ||
9b6586ae CW |
262 | static void unreserve_seqno(struct intel_engine_cs *engine) |
263 | { | |
264 | GEM_BUG_ON(!engine->timeline->inflight_seqnos); | |
265 | engine->timeline->inflight_seqnos--; | |
266 | } | |
267 | ||
fa545cbf CW |
268 | void i915_gem_retire_noop(struct i915_gem_active *active, |
269 | struct drm_i915_gem_request *request) | |
270 | { | |
271 | /* Space left intentionally blank */ | |
272 | } | |
273 | ||
cbb60b4b CW |
274 | static void advance_ring(struct drm_i915_gem_request *request) |
275 | { | |
276 | unsigned int tail; | |
277 | ||
278 | /* We know the GPU must have read the request to have | |
279 | * sent us the seqno + interrupt, so use the position | |
280 | * of tail of the request to update the last known position | |
281 | * of the GPU head. | |
282 | * | |
283 | * Note this requires that we are always called in request | |
284 | * completion order. | |
285 | */ | |
e6ba9992 CW |
286 | if (list_is_last(&request->ring_link, &request->ring->request_list)) { |
287 | /* We may race here with execlists resubmitting this request | |
288 | * as we retire it. The resubmission will move the ring->tail | |
289 | * forwards (to request->wa_tail). We either read the | |
290 | * current value that was written to hw, or the value that | |
291 | * is just about to be. Either works, if we miss the last two | |
292 | * noops - they are safe to be replayed on a reset. | |
293 | */ | |
294 | tail = READ_ONCE(request->ring->tail); | |
295 | } else { | |
cbb60b4b | 296 | tail = request->postfix; |
e6ba9992 | 297 | } |
cbb60b4b CW |
298 | list_del(&request->ring_link); |
299 | ||
300 | request->ring->head = tail; | |
301 | } | |
302 | ||
b0fd47ad CW |
303 | static void free_capture_list(struct drm_i915_gem_request *request) |
304 | { | |
305 | struct i915_gem_capture_list *capture; | |
306 | ||
307 | capture = request->capture_list; | |
308 | while (capture) { | |
309 | struct i915_gem_capture_list *next = capture->next; | |
310 | ||
311 | kfree(capture); | |
312 | capture = next; | |
313 | } | |
314 | } | |
315 | ||
05235c53 CW |
316 | static void i915_gem_request_retire(struct drm_i915_gem_request *request) |
317 | { | |
e8a9c58f | 318 | struct intel_engine_cs *engine = request->engine; |
fa545cbf CW |
319 | struct i915_gem_active *active, *next; |
320 | ||
4c7d62c6 | 321 | lockdep_assert_held(&request->i915->drm.struct_mutex); |
48bc2a4a | 322 | GEM_BUG_ON(!i915_sw_fence_signaled(&request->submit)); |
4c7d62c6 | 323 | GEM_BUG_ON(!i915_gem_request_completed(request)); |
4302055b | 324 | GEM_BUG_ON(!request->i915->gt.active_requests); |
4c7d62c6 | 325 | |
05235c53 | 326 | trace_i915_gem_request_retire(request); |
80b204bc | 327 | |
e8a9c58f | 328 | spin_lock_irq(&engine->timeline->lock); |
e95433c7 | 329 | list_del_init(&request->link); |
e8a9c58f | 330 | spin_unlock_irq(&engine->timeline->lock); |
05235c53 | 331 | |
4302055b CW |
332 | if (!--request->i915->gt.active_requests) { |
333 | GEM_BUG_ON(!request->i915->gt.awake); | |
334 | mod_delayed_work(request->i915->wq, | |
335 | &request->i915->gt.idle_work, | |
336 | msecs_to_jiffies(100)); | |
337 | } | |
9b6586ae | 338 | unreserve_seqno(request->engine); |
cbb60b4b | 339 | advance_ring(request); |
05235c53 | 340 | |
b0fd47ad CW |
341 | free_capture_list(request); |
342 | ||
fa545cbf CW |
343 | /* Walk through the active list, calling retire on each. This allows |
344 | * objects to track their GPU activity and mark themselves as idle | |
345 | * when their *last* active request is completed (updating state | |
346 | * tracking lists for eviction, active references for GEM, etc). | |
347 | * | |
348 | * As the ->retire() may free the node, we decouple it first and | |
349 | * pass along the auxiliary information (to avoid dereferencing | |
350 | * the node after the callback). | |
351 | */ | |
352 | list_for_each_entry_safe(active, next, &request->active_list, link) { | |
353 | /* In microbenchmarks or focusing upon time inside the kernel, | |
354 | * we may spend an inordinate amount of time simply handling | |
355 | * the retirement of requests and processing their callbacks. | |
356 | * Of which, this loop itself is particularly hot due to the | |
357 | * cache misses when jumping around the list of i915_gem_active. | |
358 | * So we try to keep this loop as streamlined as possible and | |
359 | * also prefetch the next i915_gem_active to try and hide | |
360 | * the likely cache miss. | |
361 | */ | |
362 | prefetchw(next); | |
363 | ||
364 | INIT_LIST_HEAD(&active->link); | |
0eafec6d | 365 | RCU_INIT_POINTER(active->request, NULL); |
fa545cbf CW |
366 | |
367 | active->retire(active, request); | |
368 | } | |
369 | ||
05235c53 CW |
370 | i915_gem_request_remove_from_client(request); |
371 | ||
e5e1fc47 | 372 | /* Retirement decays the ban score as it is a sign of ctx progress */ |
bc1d53c6 MK |
373 | if (request->ctx->ban_score > 0) |
374 | request->ctx->ban_score--; | |
e5e1fc47 | 375 | |
e8a9c58f CW |
376 | /* The backing object for the context is done after switching to the |
377 | * *next* context. Therefore we cannot retire the previous context until | |
378 | * the next context has already started running. However, since we | |
379 | * cannot take the required locks at i915_gem_request_submit() we | |
380 | * defer the unpinning of the active context to now, retirement of | |
381 | * the subsequent request. | |
382 | */ | |
383 | if (engine->last_retired_context) | |
384 | engine->context_unpin(engine, engine->last_retired_context); | |
385 | engine->last_retired_context = request->ctx; | |
d07f0e59 | 386 | |
7b92c1bd CW |
387 | spin_lock_irq(&request->lock); |
388 | if (request->waitboost) | |
389 | atomic_dec(&request->i915->rps.num_waiters); | |
390 | dma_fence_signal_locked(&request->fence); | |
391 | spin_unlock_irq(&request->lock); | |
52e54209 CW |
392 | |
393 | i915_priotree_fini(request->i915, &request->priotree); | |
e8a261ea | 394 | i915_gem_request_put(request); |
05235c53 CW |
395 | } |
396 | ||
397 | void i915_gem_request_retire_upto(struct drm_i915_gem_request *req) | |
398 | { | |
399 | struct intel_engine_cs *engine = req->engine; | |
400 | struct drm_i915_gem_request *tmp; | |
401 | ||
402 | lockdep_assert_held(&req->i915->drm.struct_mutex); | |
4ffd6e0c CW |
403 | GEM_BUG_ON(!i915_gem_request_completed(req)); |
404 | ||
e95433c7 CW |
405 | if (list_empty(&req->link)) |
406 | return; | |
05235c53 CW |
407 | |
408 | do { | |
73cb9701 | 409 | tmp = list_first_entry(&engine->timeline->requests, |
efdf7c06 | 410 | typeof(*tmp), link); |
05235c53 CW |
411 | |
412 | i915_gem_request_retire(tmp); | |
413 | } while (tmp != req); | |
05235c53 CW |
414 | } |
415 | ||
9b6586ae | 416 | static u32 timeline_get_seqno(struct intel_timeline *tl) |
05235c53 | 417 | { |
9b6586ae | 418 | return ++tl->seqno; |
28176ef4 CW |
419 | } |
420 | ||
d55ac5bf | 421 | void __i915_gem_request_submit(struct drm_i915_gem_request *request) |
5590af3e | 422 | { |
73cb9701 | 423 | struct intel_engine_cs *engine = request->engine; |
f2d13290 CW |
424 | struct intel_timeline *timeline; |
425 | u32 seqno; | |
5590af3e | 426 | |
e60a870d | 427 | GEM_BUG_ON(!irqs_disabled()); |
67520415 | 428 | lockdep_assert_held(&engine->timeline->lock); |
e60a870d | 429 | |
fe49789f CW |
430 | trace_i915_gem_request_execute(request); |
431 | ||
80b204bc CW |
432 | /* Transfer from per-context onto the global per-engine timeline */ |
433 | timeline = engine->timeline; | |
434 | GEM_BUG_ON(timeline == request->timeline); | |
5590af3e | 435 | |
9b6586ae | 436 | seqno = timeline_get_seqno(timeline); |
f2d13290 CW |
437 | GEM_BUG_ON(!seqno); |
438 | GEM_BUG_ON(i915_seqno_passed(intel_engine_get_seqno(engine), seqno)); | |
439 | ||
f2d13290 CW |
440 | /* We may be recursing from the signal callback of another i915 fence */ |
441 | spin_lock_nested(&request->lock, SINGLE_DEPTH_NESTING); | |
442 | request->global_seqno = seqno; | |
443 | if (test_bit(DMA_FENCE_FLAG_ENABLE_SIGNAL_BIT, &request->fence.flags)) | |
f7b02a52 | 444 | intel_engine_enable_signaling(request, false); |
f2d13290 CW |
445 | spin_unlock(&request->lock); |
446 | ||
caddfe71 CW |
447 | engine->emit_breadcrumb(request, |
448 | request->ring->vaddr + request->postfix); | |
5590af3e | 449 | |
bb89485e | 450 | spin_lock(&request->timeline->lock); |
80b204bc CW |
451 | list_move_tail(&request->link, &timeline->requests); |
452 | spin_unlock(&request->timeline->lock); | |
453 | ||
fe49789f | 454 | wake_up_all(&request->execute); |
d55ac5bf CW |
455 | } |
456 | ||
457 | void i915_gem_request_submit(struct drm_i915_gem_request *request) | |
458 | { | |
459 | struct intel_engine_cs *engine = request->engine; | |
460 | unsigned long flags; | |
23902e49 | 461 | |
d55ac5bf CW |
462 | /* Will be called from irq-context when using foreign fences. */ |
463 | spin_lock_irqsave(&engine->timeline->lock, flags); | |
464 | ||
465 | __i915_gem_request_submit(request); | |
466 | ||
467 | spin_unlock_irqrestore(&engine->timeline->lock, flags); | |
468 | } | |
469 | ||
d6a2289d | 470 | void __i915_gem_request_unsubmit(struct drm_i915_gem_request *request) |
d55ac5bf | 471 | { |
d6a2289d CW |
472 | struct intel_engine_cs *engine = request->engine; |
473 | struct intel_timeline *timeline; | |
d55ac5bf | 474 | |
e60a870d | 475 | GEM_BUG_ON(!irqs_disabled()); |
67520415 | 476 | lockdep_assert_held(&engine->timeline->lock); |
48bc2a4a | 477 | |
d6a2289d CW |
478 | /* Only unwind in reverse order, required so that the per-context list |
479 | * is kept in seqno/ring order. | |
480 | */ | |
481 | GEM_BUG_ON(request->global_seqno != engine->timeline->seqno); | |
482 | engine->timeline->seqno--; | |
80b204bc | 483 | |
d6a2289d CW |
484 | /* We may be recursing from the signal callback of another i915 fence */ |
485 | spin_lock_nested(&request->lock, SINGLE_DEPTH_NESTING); | |
486 | request->global_seqno = 0; | |
487 | if (test_bit(DMA_FENCE_FLAG_ENABLE_SIGNAL_BIT, &request->fence.flags)) | |
488 | intel_engine_cancel_signaling(request); | |
489 | spin_unlock(&request->lock); | |
490 | ||
491 | /* Transfer back from the global per-engine timeline to per-context */ | |
492 | timeline = request->timeline; | |
493 | GEM_BUG_ON(timeline == engine->timeline); | |
494 | ||
495 | spin_lock(&timeline->lock); | |
496 | list_move(&request->link, &timeline->requests); | |
497 | spin_unlock(&timeline->lock); | |
498 | ||
499 | /* We don't need to wake_up any waiters on request->execute, they | |
500 | * will get woken by any other event or us re-adding this request | |
501 | * to the engine timeline (__i915_gem_request_submit()). The waiters | |
502 | * should be quite adapt at finding that the request now has a new | |
503 | * global_seqno to the one they went to sleep on. | |
504 | */ | |
505 | } | |
506 | ||
507 | void i915_gem_request_unsubmit(struct drm_i915_gem_request *request) | |
508 | { | |
509 | struct intel_engine_cs *engine = request->engine; | |
510 | unsigned long flags; | |
511 | ||
512 | /* Will be called from irq-context when using foreign fences. */ | |
513 | spin_lock_irqsave(&engine->timeline->lock, flags); | |
514 | ||
515 | __i915_gem_request_unsubmit(request); | |
516 | ||
517 | spin_unlock_irqrestore(&engine->timeline->lock, flags); | |
5590af3e CW |
518 | } |
519 | ||
23902e49 | 520 | static int __i915_sw_fence_call |
d55ac5bf | 521 | submit_notify(struct i915_sw_fence *fence, enum i915_sw_fence_notify state) |
23902e49 | 522 | { |
48bc2a4a | 523 | struct drm_i915_gem_request *request = |
48bc2a4a | 524 | container_of(fence, typeof(*request), submit); |
48bc2a4a CW |
525 | |
526 | switch (state) { | |
527 | case FENCE_COMPLETE: | |
354d036f | 528 | trace_i915_gem_request_submit(request); |
d55ac5bf | 529 | request->engine->submit_request(request); |
48bc2a4a CW |
530 | break; |
531 | ||
532 | case FENCE_FREE: | |
533 | i915_gem_request_put(request); | |
534 | break; | |
535 | } | |
536 | ||
23902e49 CW |
537 | return NOTIFY_DONE; |
538 | } | |
539 | ||
8e637178 CW |
540 | /** |
541 | * i915_gem_request_alloc - allocate a request structure | |
542 | * | |
543 | * @engine: engine that we wish to issue the request on. | |
544 | * @ctx: context that the request will be associated with. | |
8e637178 CW |
545 | * |
546 | * Returns a pointer to the allocated request if successful, | |
547 | * or an error code if not. | |
548 | */ | |
549 | struct drm_i915_gem_request * | |
550 | i915_gem_request_alloc(struct intel_engine_cs *engine, | |
551 | struct i915_gem_context *ctx) | |
05235c53 CW |
552 | { |
553 | struct drm_i915_private *dev_priv = engine->i915; | |
05235c53 | 554 | struct drm_i915_gem_request *req; |
266a240b | 555 | struct intel_ring *ring; |
05235c53 CW |
556 | int ret; |
557 | ||
28176ef4 CW |
558 | lockdep_assert_held(&dev_priv->drm.struct_mutex); |
559 | ||
05235c53 | 560 | /* ABI: Before userspace accesses the GPU (e.g. execbuffer), report |
6ffb7d07 | 561 | * EIO if the GPU is already wedged. |
05235c53 | 562 | */ |
6ffb7d07 CW |
563 | if (i915_terminally_wedged(&dev_priv->gpu_error)) |
564 | return ERR_PTR(-EIO); | |
05235c53 | 565 | |
e8a9c58f CW |
566 | /* Pinning the contexts may generate requests in order to acquire |
567 | * GGTT space, so do this first before we reserve a seqno for | |
568 | * ourselves. | |
569 | */ | |
266a240b CW |
570 | ring = engine->context_pin(engine, ctx); |
571 | if (IS_ERR(ring)) | |
572 | return ERR_CAST(ring); | |
573 | GEM_BUG_ON(!ring); | |
28176ef4 | 574 | |
9b6586ae | 575 | ret = reserve_seqno(engine); |
e8a9c58f CW |
576 | if (ret) |
577 | goto err_unpin; | |
578 | ||
9b5f4e5e | 579 | /* Move the oldest request to the slab-cache (if not in use!) */ |
73cb9701 | 580 | req = list_first_entry_or_null(&engine->timeline->requests, |
efdf7c06 | 581 | typeof(*req), link); |
754c9fd5 | 582 | if (req && i915_gem_request_completed(req)) |
2a1d7752 | 583 | i915_gem_request_retire(req); |
9b5f4e5e | 584 | |
5a198b8c CW |
585 | /* Beware: Dragons be flying overhead. |
586 | * | |
587 | * We use RCU to look up requests in flight. The lookups may | |
588 | * race with the request being allocated from the slab freelist. | |
589 | * That is the request we are writing to here, may be in the process | |
1426f715 | 590 | * of being read by __i915_gem_active_get_rcu(). As such, |
5a198b8c CW |
591 | * we have to be very careful when overwriting the contents. During |
592 | * the RCU lookup, we change chase the request->engine pointer, | |
65e4760e | 593 | * read the request->global_seqno and increment the reference count. |
5a198b8c CW |
594 | * |
595 | * The reference count is incremented atomically. If it is zero, | |
596 | * the lookup knows the request is unallocated and complete. Otherwise, | |
597 | * it is either still in use, or has been reallocated and reset | |
f54d1867 CW |
598 | * with dma_fence_init(). This increment is safe for release as we |
599 | * check that the request we have a reference to and matches the active | |
5a198b8c CW |
600 | * request. |
601 | * | |
602 | * Before we increment the refcount, we chase the request->engine | |
603 | * pointer. We must not call kmem_cache_zalloc() or else we set | |
604 | * that pointer to NULL and cause a crash during the lookup. If | |
605 | * we see the request is completed (based on the value of the | |
606 | * old engine and seqno), the lookup is complete and reports NULL. | |
607 | * If we decide the request is not completed (new engine or seqno), | |
608 | * then we grab a reference and double check that it is still the | |
609 | * active request - which it won't be and restart the lookup. | |
610 | * | |
611 | * Do not use kmem_cache_zalloc() here! | |
612 | */ | |
613 | req = kmem_cache_alloc(dev_priv->requests, GFP_KERNEL); | |
28176ef4 CW |
614 | if (!req) { |
615 | ret = -ENOMEM; | |
616 | goto err_unreserve; | |
617 | } | |
05235c53 | 618 | |
80b204bc CW |
619 | req->timeline = i915_gem_context_lookup_timeline(ctx, engine); |
620 | GEM_BUG_ON(req->timeline == engine->timeline); | |
73cb9701 | 621 | |
04769652 | 622 | spin_lock_init(&req->lock); |
f54d1867 CW |
623 | dma_fence_init(&req->fence, |
624 | &i915_fence_ops, | |
625 | &req->lock, | |
73cb9701 | 626 | req->timeline->fence_context, |
9b6586ae | 627 | timeline_get_seqno(req->timeline)); |
04769652 | 628 | |
48bc2a4a CW |
629 | /* We bump the ref for the fence chain */ |
630 | i915_sw_fence_init(&i915_gem_request_get(req)->submit, submit_notify); | |
fe49789f | 631 | init_waitqueue_head(&req->execute); |
5590af3e | 632 | |
52e54209 CW |
633 | i915_priotree_init(&req->priotree); |
634 | ||
fa545cbf | 635 | INIT_LIST_HEAD(&req->active_list); |
05235c53 CW |
636 | req->i915 = dev_priv; |
637 | req->engine = engine; | |
e8a9c58f | 638 | req->ctx = ctx; |
266a240b | 639 | req->ring = ring; |
05235c53 | 640 | |
5a198b8c | 641 | /* No zalloc, must clear what we need by hand */ |
f2d13290 | 642 | req->global_seqno = 0; |
5a198b8c | 643 | req->file_priv = NULL; |
058d88c4 | 644 | req->batch = NULL; |
b0fd47ad | 645 | req->capture_list = NULL; |
7b92c1bd | 646 | req->waitboost = false; |
5a198b8c | 647 | |
05235c53 CW |
648 | /* |
649 | * Reserve space in the ring buffer for all the commands required to | |
650 | * eventually emit this request. This is to guarantee that the | |
651 | * i915_add_request() call can't fail. Note that the reserve may need | |
652 | * to be redone if the request is not actually submitted straight | |
653 | * away, e.g. because a GPU scheduler has deferred it. | |
654 | */ | |
655 | req->reserved_space = MIN_SPACE_FOR_ADD_REQUEST; | |
98f29e8d | 656 | GEM_BUG_ON(req->reserved_space < engine->emit_breadcrumb_sz); |
05235c53 | 657 | |
f73e7399 | 658 | ret = engine->request_alloc(req); |
05235c53 CW |
659 | if (ret) |
660 | goto err_ctx; | |
661 | ||
d045446d CW |
662 | /* Record the position of the start of the request so that |
663 | * should we detect the updated seqno part-way through the | |
664 | * GPU processing the request, we never over-estimate the | |
665 | * position of the head. | |
666 | */ | |
e6ba9992 | 667 | req->head = req->ring->emit; |
d045446d | 668 | |
9b6586ae CW |
669 | /* Check that we didn't interrupt ourselves with a new request */ |
670 | GEM_BUG_ON(req->timeline->seqno != req->fence.seqno); | |
8e637178 | 671 | return req; |
05235c53 CW |
672 | |
673 | err_ctx: | |
1618bdb8 CW |
674 | /* Make sure we didn't add ourselves to external state before freeing */ |
675 | GEM_BUG_ON(!list_empty(&req->active_list)); | |
676 | GEM_BUG_ON(!list_empty(&req->priotree.signalers_list)); | |
677 | GEM_BUG_ON(!list_empty(&req->priotree.waiters_list)); | |
678 | ||
05235c53 | 679 | kmem_cache_free(dev_priv->requests, req); |
28176ef4 | 680 | err_unreserve: |
9b6586ae | 681 | unreserve_seqno(engine); |
e8a9c58f CW |
682 | err_unpin: |
683 | engine->context_unpin(engine, ctx); | |
8e637178 | 684 | return ERR_PTR(ret); |
05235c53 CW |
685 | } |
686 | ||
a2bc4695 CW |
687 | static int |
688 | i915_gem_request_await_request(struct drm_i915_gem_request *to, | |
689 | struct drm_i915_gem_request *from) | |
690 | { | |
85e17f59 | 691 | int ret; |
a2bc4695 CW |
692 | |
693 | GEM_BUG_ON(to == from); | |
ceae14bd | 694 | GEM_BUG_ON(to->timeline == from->timeline); |
a2bc4695 | 695 | |
ade0b0c9 CW |
696 | if (i915_gem_request_completed(from)) |
697 | return 0; | |
698 | ||
52e54209 CW |
699 | if (to->engine->schedule) { |
700 | ret = i915_priotree_add_dependency(to->i915, | |
701 | &to->priotree, | |
702 | &from->priotree); | |
703 | if (ret < 0) | |
704 | return ret; | |
705 | } | |
706 | ||
73cb9701 CW |
707 | if (to->engine == from->engine) { |
708 | ret = i915_sw_fence_await_sw_fence_gfp(&to->submit, | |
709 | &from->submit, | |
710 | GFP_KERNEL); | |
711 | return ret < 0 ? ret : 0; | |
712 | } | |
713 | ||
6b567085 CW |
714 | if (to->engine->semaphore.sync_to) { |
715 | u32 seqno; | |
65e4760e | 716 | |
6b567085 | 717 | GEM_BUG_ON(!from->engine->semaphore.signal); |
fc9d4d2b | 718 | |
6b567085 CW |
719 | seqno = i915_gem_request_global_seqno(from); |
720 | if (!seqno) | |
fc9d4d2b | 721 | goto await_dma_fence; |
49f08598 | 722 | |
fc9d4d2b CW |
723 | if (seqno <= to->timeline->global_sync[from->engine->id]) |
724 | return 0; | |
725 | ||
726 | trace_i915_gem_ring_sync_to(to, from); | |
a2bc4695 CW |
727 | ret = to->engine->semaphore.sync_to(to, from); |
728 | if (ret) | |
729 | return ret; | |
fc9d4d2b CW |
730 | |
731 | to->timeline->global_sync[from->engine->id] = seqno; | |
6b567085 | 732 | return 0; |
a2bc4695 CW |
733 | } |
734 | ||
fc9d4d2b CW |
735 | await_dma_fence: |
736 | ret = i915_sw_fence_await_dma_fence(&to->submit, | |
737 | &from->fence, 0, | |
738 | GFP_KERNEL); | |
739 | return ret < 0 ? ret : 0; | |
a2bc4695 CW |
740 | } |
741 | ||
b52992c0 CW |
742 | int |
743 | i915_gem_request_await_dma_fence(struct drm_i915_gem_request *req, | |
744 | struct dma_fence *fence) | |
745 | { | |
29ef3fa9 CW |
746 | struct dma_fence **child = &fence; |
747 | unsigned int nchild = 1; | |
b52992c0 | 748 | int ret; |
b52992c0 CW |
749 | |
750 | /* Note that if the fence-array was created in signal-on-any mode, | |
751 | * we should *not* decompose it into its individual fences. However, | |
752 | * we don't currently store which mode the fence-array is operating | |
753 | * in. Fortunately, the only user of signal-on-any is private to | |
754 | * amdgpu and we should not see any incoming fence-array from | |
755 | * sync-file being in signal-on-any mode. | |
756 | */ | |
29ef3fa9 CW |
757 | if (dma_fence_is_array(fence)) { |
758 | struct dma_fence_array *array = to_dma_fence_array(fence); | |
759 | ||
760 | child = array->fences; | |
761 | nchild = array->num_fences; | |
762 | GEM_BUG_ON(!nchild); | |
763 | } | |
b52992c0 | 764 | |
29ef3fa9 CW |
765 | do { |
766 | fence = *child++; | |
767 | if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &fence->flags)) | |
768 | continue; | |
b52992c0 | 769 | |
ceae14bd CW |
770 | /* |
771 | * Requests on the same timeline are explicitly ordered, along | |
772 | * with their dependencies, by i915_add_request() which ensures | |
773 | * that requests are submitted in-order through each ring. | |
774 | */ | |
775 | if (fence->context == req->fence.context) | |
776 | continue; | |
777 | ||
47979480 CW |
778 | /* Squash repeated waits to the same timelines */ |
779 | if (fence->context != req->i915->mm.unordered_timeline && | |
780 | intel_timeline_sync_is_later(req->timeline, fence)) | |
781 | continue; | |
782 | ||
29ef3fa9 | 783 | if (dma_fence_is_i915(fence)) |
b52992c0 | 784 | ret = i915_gem_request_await_request(req, |
29ef3fa9 | 785 | to_request(fence)); |
b52992c0 | 786 | else |
29ef3fa9 CW |
787 | ret = i915_sw_fence_await_dma_fence(&req->submit, fence, |
788 | I915_FENCE_TIMEOUT, | |
b52992c0 CW |
789 | GFP_KERNEL); |
790 | if (ret < 0) | |
791 | return ret; | |
47979480 CW |
792 | |
793 | /* Record the latest fence used against each timeline */ | |
794 | if (fence->context != req->i915->mm.unordered_timeline) | |
795 | intel_timeline_sync_set(req->timeline, fence); | |
29ef3fa9 | 796 | } while (--nchild); |
b52992c0 CW |
797 | |
798 | return 0; | |
799 | } | |
800 | ||
a2bc4695 CW |
801 | /** |
802 | * i915_gem_request_await_object - set this request to (async) wait upon a bo | |
803 | * | |
804 | * @to: request we are wishing to use | |
805 | * @obj: object which may be in use on another ring. | |
806 | * | |
807 | * This code is meant to abstract object synchronization with the GPU. | |
808 | * Conceptually we serialise writes between engines inside the GPU. | |
809 | * We only allow one engine to write into a buffer at any time, but | |
810 | * multiple readers. To ensure each has a coherent view of memory, we must: | |
811 | * | |
812 | * - If there is an outstanding write request to the object, the new | |
813 | * request must wait for it to complete (either CPU or in hw, requests | |
814 | * on the same ring will be naturally ordered). | |
815 | * | |
816 | * - If we are a write request (pending_write_domain is set), the new | |
817 | * request must wait for outstanding read requests to complete. | |
818 | * | |
819 | * Returns 0 if successful, else propagates up the lower layer error. | |
820 | */ | |
821 | int | |
822 | i915_gem_request_await_object(struct drm_i915_gem_request *to, | |
823 | struct drm_i915_gem_object *obj, | |
824 | bool write) | |
825 | { | |
d07f0e59 CW |
826 | struct dma_fence *excl; |
827 | int ret = 0; | |
a2bc4695 CW |
828 | |
829 | if (write) { | |
d07f0e59 CW |
830 | struct dma_fence **shared; |
831 | unsigned int count, i; | |
832 | ||
833 | ret = reservation_object_get_fences_rcu(obj->resv, | |
834 | &excl, &count, &shared); | |
835 | if (ret) | |
836 | return ret; | |
837 | ||
838 | for (i = 0; i < count; i++) { | |
839 | ret = i915_gem_request_await_dma_fence(to, shared[i]); | |
840 | if (ret) | |
841 | break; | |
842 | ||
843 | dma_fence_put(shared[i]); | |
844 | } | |
845 | ||
846 | for (; i < count; i++) | |
847 | dma_fence_put(shared[i]); | |
848 | kfree(shared); | |
a2bc4695 | 849 | } else { |
d07f0e59 | 850 | excl = reservation_object_get_excl_rcu(obj->resv); |
a2bc4695 CW |
851 | } |
852 | ||
d07f0e59 CW |
853 | if (excl) { |
854 | if (ret == 0) | |
855 | ret = i915_gem_request_await_dma_fence(to, excl); | |
a2bc4695 | 856 | |
d07f0e59 | 857 | dma_fence_put(excl); |
a2bc4695 CW |
858 | } |
859 | ||
d07f0e59 | 860 | return ret; |
a2bc4695 CW |
861 | } |
862 | ||
05235c53 CW |
863 | static void i915_gem_mark_busy(const struct intel_engine_cs *engine) |
864 | { | |
865 | struct drm_i915_private *dev_priv = engine->i915; | |
866 | ||
05235c53 CW |
867 | if (dev_priv->gt.awake) |
868 | return; | |
869 | ||
4302055b CW |
870 | GEM_BUG_ON(!dev_priv->gt.active_requests); |
871 | ||
05235c53 CW |
872 | intel_runtime_pm_get_noresume(dev_priv); |
873 | dev_priv->gt.awake = true; | |
874 | ||
54b4f68f | 875 | intel_enable_gt_powersave(dev_priv); |
05235c53 CW |
876 | i915_update_gfx_val(dev_priv); |
877 | if (INTEL_GEN(dev_priv) >= 6) | |
878 | gen6_rps_busy(dev_priv); | |
879 | ||
880 | queue_delayed_work(dev_priv->wq, | |
881 | &dev_priv->gt.retire_work, | |
882 | round_jiffies_up_relative(HZ)); | |
883 | } | |
884 | ||
885 | /* | |
886 | * NB: This function is not allowed to fail. Doing so would mean the the | |
887 | * request is not being tracked for completion but the work itself is | |
888 | * going to happen on the hardware. This would be a Bad Thing(tm). | |
889 | */ | |
17f298cf | 890 | void __i915_add_request(struct drm_i915_gem_request *request, bool flush_caches) |
05235c53 | 891 | { |
95b2ab56 CW |
892 | struct intel_engine_cs *engine = request->engine; |
893 | struct intel_ring *ring = request->ring; | |
73cb9701 | 894 | struct intel_timeline *timeline = request->timeline; |
0a046a0e | 895 | struct drm_i915_gem_request *prev; |
73dec95e | 896 | u32 *cs; |
caddfe71 | 897 | int err; |
05235c53 | 898 | |
4c7d62c6 | 899 | lockdep_assert_held(&request->i915->drm.struct_mutex); |
0f25dff6 CW |
900 | trace_i915_gem_request_add(request); |
901 | ||
c781c978 CW |
902 | /* Make sure that no request gazumped us - if it was allocated after |
903 | * our i915_gem_request_alloc() and called __i915_add_request() before | |
904 | * us, the timeline will hold its seqno which is later than ours. | |
905 | */ | |
9b6586ae | 906 | GEM_BUG_ON(timeline->seqno != request->fence.seqno); |
c781c978 | 907 | |
05235c53 CW |
908 | /* |
909 | * To ensure that this call will not fail, space for its emissions | |
910 | * should already have been reserved in the ring buffer. Let the ring | |
911 | * know that it is time to use that space up. | |
912 | */ | |
05235c53 CW |
913 | request->reserved_space = 0; |
914 | ||
915 | /* | |
916 | * Emit any outstanding flushes - execbuf can fail to emit the flush | |
917 | * after having emitted the batchbuffer command. Hence we need to fix | |
918 | * things up similar to emitting the lazy request. The difference here | |
919 | * is that the flush _must_ happen before the next request, no matter | |
920 | * what. | |
921 | */ | |
922 | if (flush_caches) { | |
caddfe71 | 923 | err = engine->emit_flush(request, EMIT_FLUSH); |
c7fe7d25 | 924 | |
05235c53 | 925 | /* Not allowed to fail! */ |
caddfe71 | 926 | WARN(err, "engine->emit_flush() failed: %d!\n", err); |
05235c53 CW |
927 | } |
928 | ||
d045446d | 929 | /* Record the position of the start of the breadcrumb so that |
05235c53 CW |
930 | * should we detect the updated seqno part-way through the |
931 | * GPU processing the request, we never over-estimate the | |
d045446d | 932 | * position of the ring's HEAD. |
05235c53 | 933 | */ |
73dec95e TU |
934 | cs = intel_ring_begin(request, engine->emit_breadcrumb_sz); |
935 | GEM_BUG_ON(IS_ERR(cs)); | |
936 | request->postfix = intel_ring_offset(request, cs); | |
05235c53 | 937 | |
0f25dff6 CW |
938 | /* Seal the request and mark it as pending execution. Note that |
939 | * we may inspect this state, without holding any locks, during | |
940 | * hangcheck. Hence we apply the barrier to ensure that we do not | |
941 | * see a more recent value in the hws than we are tracking. | |
942 | */ | |
0a046a0e | 943 | |
73cb9701 | 944 | prev = i915_gem_active_raw(&timeline->last_request, |
0a046a0e | 945 | &request->i915->drm.struct_mutex); |
52e54209 | 946 | if (prev) { |
0a046a0e CW |
947 | i915_sw_fence_await_sw_fence(&request->submit, &prev->submit, |
948 | &request->submitq); | |
52e54209 CW |
949 | if (engine->schedule) |
950 | __i915_priotree_add_dependency(&request->priotree, | |
951 | &prev->priotree, | |
952 | &request->dep, | |
953 | 0); | |
954 | } | |
0a046a0e | 955 | |
80b204bc | 956 | spin_lock_irq(&timeline->lock); |
f2d13290 | 957 | list_add_tail(&request->link, &timeline->requests); |
80b204bc CW |
958 | spin_unlock_irq(&timeline->lock); |
959 | ||
9b6586ae | 960 | GEM_BUG_ON(timeline->seqno != request->fence.seqno); |
73cb9701 | 961 | i915_gem_active_set(&timeline->last_request, request); |
f2d13290 | 962 | |
0f25dff6 | 963 | list_add_tail(&request->ring_link, &ring->request_list); |
f2d13290 | 964 | request->emitted_jiffies = jiffies; |
0f25dff6 | 965 | |
9b6586ae CW |
966 | if (!request->i915->gt.active_requests++) |
967 | i915_gem_mark_busy(engine); | |
5590af3e | 968 | |
0de9136d CW |
969 | /* Let the backend know a new request has arrived that may need |
970 | * to adjust the existing execution schedule due to a high priority | |
971 | * request - i.e. we may want to preempt the current request in order | |
972 | * to run a high priority dependency chain *before* we can execute this | |
973 | * request. | |
974 | * | |
975 | * This is called before the request is ready to run so that we can | |
976 | * decide whether to preempt the entire chain so that it is ready to | |
977 | * run at the earliest possible convenience. | |
978 | */ | |
979 | if (engine->schedule) | |
9f792eba | 980 | engine->schedule(request, request->ctx->priority); |
0de9136d | 981 | |
5590af3e CW |
982 | local_bh_disable(); |
983 | i915_sw_fence_commit(&request->submit); | |
984 | local_bh_enable(); /* Kick the execlists tasklet if just scheduled */ | |
05235c53 CW |
985 | } |
986 | ||
987 | static unsigned long local_clock_us(unsigned int *cpu) | |
988 | { | |
989 | unsigned long t; | |
990 | ||
991 | /* Cheaply and approximately convert from nanoseconds to microseconds. | |
992 | * The result and subsequent calculations are also defined in the same | |
993 | * approximate microseconds units. The principal source of timing | |
994 | * error here is from the simple truncation. | |
995 | * | |
996 | * Note that local_clock() is only defined wrt to the current CPU; | |
997 | * the comparisons are no longer valid if we switch CPUs. Instead of | |
998 | * blocking preemption for the entire busywait, we can detect the CPU | |
999 | * switch and use that as indicator of system load and a reason to | |
1000 | * stop busywaiting, see busywait_stop(). | |
1001 | */ | |
1002 | *cpu = get_cpu(); | |
1003 | t = local_clock() >> 10; | |
1004 | put_cpu(); | |
1005 | ||
1006 | return t; | |
1007 | } | |
1008 | ||
1009 | static bool busywait_stop(unsigned long timeout, unsigned int cpu) | |
1010 | { | |
1011 | unsigned int this_cpu; | |
1012 | ||
1013 | if (time_after(local_clock_us(&this_cpu), timeout)) | |
1014 | return true; | |
1015 | ||
1016 | return this_cpu != cpu; | |
1017 | } | |
1018 | ||
1019 | bool __i915_spin_request(const struct drm_i915_gem_request *req, | |
754c9fd5 | 1020 | u32 seqno, int state, unsigned long timeout_us) |
05235c53 | 1021 | { |
c33ed067 CW |
1022 | struct intel_engine_cs *engine = req->engine; |
1023 | unsigned int irq, cpu; | |
05235c53 CW |
1024 | |
1025 | /* When waiting for high frequency requests, e.g. during synchronous | |
1026 | * rendering split between the CPU and GPU, the finite amount of time | |
1027 | * required to set up the irq and wait upon it limits the response | |
1028 | * rate. By busywaiting on the request completion for a short while we | |
1029 | * can service the high frequency waits as quick as possible. However, | |
1030 | * if it is a slow request, we want to sleep as quickly as possible. | |
1031 | * The tradeoff between waiting and sleeping is roughly the time it | |
1032 | * takes to sleep on a request, on the order of a microsecond. | |
1033 | */ | |
1034 | ||
c33ed067 | 1035 | irq = atomic_read(&engine->irq_count); |
05235c53 CW |
1036 | timeout_us += local_clock_us(&cpu); |
1037 | do { | |
754c9fd5 CW |
1038 | if (seqno != i915_gem_request_global_seqno(req)) |
1039 | break; | |
1040 | ||
1041 | if (i915_seqno_passed(intel_engine_get_seqno(req->engine), | |
1042 | seqno)) | |
05235c53 CW |
1043 | return true; |
1044 | ||
c33ed067 CW |
1045 | /* Seqno are meant to be ordered *before* the interrupt. If |
1046 | * we see an interrupt without a corresponding seqno advance, | |
1047 | * assume we won't see one in the near future but require | |
1048 | * the engine->seqno_barrier() to fixup coherency. | |
1049 | */ | |
1050 | if (atomic_read(&engine->irq_count) != irq) | |
1051 | break; | |
1052 | ||
05235c53 CW |
1053 | if (signal_pending_state(state, current)) |
1054 | break; | |
1055 | ||
1056 | if (busywait_stop(timeout_us, cpu)) | |
1057 | break; | |
1058 | ||
f2f09a4c | 1059 | cpu_relax(); |
05235c53 CW |
1060 | } while (!need_resched()); |
1061 | ||
1062 | return false; | |
1063 | } | |
1064 | ||
e0705114 | 1065 | static bool __i915_wait_request_check_and_reset(struct drm_i915_gem_request *request) |
4680816b | 1066 | { |
8c185eca | 1067 | if (likely(!i915_reset_handoff(&request->i915->gpu_error))) |
e0705114 | 1068 | return false; |
4680816b | 1069 | |
e0705114 CW |
1070 | __set_current_state(TASK_RUNNING); |
1071 | i915_reset(request->i915); | |
1072 | return true; | |
4680816b CW |
1073 | } |
1074 | ||
05235c53 | 1075 | /** |
776f3236 | 1076 | * i915_wait_request - wait until execution of request has finished |
e95433c7 | 1077 | * @req: the request to wait upon |
ea746f36 | 1078 | * @flags: how to wait |
e95433c7 CW |
1079 | * @timeout: how long to wait in jiffies |
1080 | * | |
1081 | * i915_wait_request() waits for the request to be completed, for a | |
1082 | * maximum of @timeout jiffies (with MAX_SCHEDULE_TIMEOUT implying an | |
1083 | * unbounded wait). | |
05235c53 | 1084 | * |
e95433c7 CW |
1085 | * If the caller holds the struct_mutex, the caller must pass I915_WAIT_LOCKED |
1086 | * in via the flags, and vice versa if the struct_mutex is not held, the caller | |
1087 | * must not specify that the wait is locked. | |
05235c53 | 1088 | * |
e95433c7 CW |
1089 | * Returns the remaining time (in jiffies) if the request completed, which may |
1090 | * be zero or -ETIME if the request is unfinished after the timeout expires. | |
1091 | * May return -EINTR is called with I915_WAIT_INTERRUPTIBLE and a signal is | |
1092 | * pending before the request completes. | |
05235c53 | 1093 | */ |
e95433c7 CW |
1094 | long i915_wait_request(struct drm_i915_gem_request *req, |
1095 | unsigned int flags, | |
1096 | long timeout) | |
05235c53 | 1097 | { |
ea746f36 CW |
1098 | const int state = flags & I915_WAIT_INTERRUPTIBLE ? |
1099 | TASK_INTERRUPTIBLE : TASK_UNINTERRUPTIBLE; | |
4b36b2e5 | 1100 | wait_queue_head_t *errq = &req->i915->gpu_error.wait_queue; |
a49625f9 CW |
1101 | DEFINE_WAIT_FUNC(reset, default_wake_function); |
1102 | DEFINE_WAIT_FUNC(exec, default_wake_function); | |
05235c53 | 1103 | struct intel_wait wait; |
05235c53 CW |
1104 | |
1105 | might_sleep(); | |
22dd3bb9 | 1106 | #if IS_ENABLED(CONFIG_LOCKDEP) |
e95433c7 CW |
1107 | GEM_BUG_ON(debug_locks && |
1108 | !!lockdep_is_held(&req->i915->drm.struct_mutex) != | |
22dd3bb9 CW |
1109 | !!(flags & I915_WAIT_LOCKED)); |
1110 | #endif | |
e95433c7 | 1111 | GEM_BUG_ON(timeout < 0); |
05235c53 | 1112 | |
05235c53 | 1113 | if (i915_gem_request_completed(req)) |
e95433c7 | 1114 | return timeout; |
05235c53 | 1115 | |
e95433c7 CW |
1116 | if (!timeout) |
1117 | return -ETIME; | |
05235c53 | 1118 | |
93692502 | 1119 | trace_i915_gem_request_wait_begin(req, flags); |
05235c53 | 1120 | |
a49625f9 | 1121 | add_wait_queue(&req->execute, &exec); |
7de53bf7 CW |
1122 | if (flags & I915_WAIT_LOCKED) |
1123 | add_wait_queue(errq, &reset); | |
1124 | ||
56299fb7 | 1125 | intel_wait_init(&wait, req); |
754c9fd5 | 1126 | |
d6a2289d | 1127 | restart: |
0f2f61d4 CW |
1128 | do { |
1129 | set_current_state(state); | |
1130 | if (intel_wait_update_request(&wait, req)) | |
1131 | break; | |
541ca6ed | 1132 | |
0f2f61d4 CW |
1133 | if (flags & I915_WAIT_LOCKED && |
1134 | __i915_wait_request_check_and_reset(req)) | |
1135 | continue; | |
05235c53 | 1136 | |
0f2f61d4 CW |
1137 | if (signal_pending_state(state, current)) { |
1138 | timeout = -ERESTARTSYS; | |
4680816b | 1139 | goto complete; |
0f2f61d4 | 1140 | } |
4680816b | 1141 | |
0f2f61d4 CW |
1142 | if (!timeout) { |
1143 | timeout = -ETIME; | |
1144 | goto complete; | |
1145 | } | |
541ca6ed | 1146 | |
0f2f61d4 CW |
1147 | timeout = io_schedule_timeout(timeout); |
1148 | } while (1); | |
4680816b | 1149 | |
0f2f61d4 | 1150 | GEM_BUG_ON(!intel_wait_has_seqno(&wait)); |
fe49789f | 1151 | GEM_BUG_ON(!i915_sw_fence_signaled(&req->submit)); |
4680816b | 1152 | |
437c3087 | 1153 | /* Optimistic short spin before touching IRQs */ |
05235c53 CW |
1154 | if (i915_spin_request(req, state, 5)) |
1155 | goto complete; | |
1156 | ||
1157 | set_current_state(state); | |
05235c53 CW |
1158 | if (intel_engine_add_wait(req->engine, &wait)) |
1159 | /* In order to check that we haven't missed the interrupt | |
1160 | * as we enabled it, we need to kick ourselves to do a | |
1161 | * coherent check on the seqno before we sleep. | |
1162 | */ | |
1163 | goto wakeup; | |
1164 | ||
24f417ec CW |
1165 | if (flags & I915_WAIT_LOCKED) |
1166 | __i915_wait_request_check_and_reset(req); | |
1167 | ||
05235c53 CW |
1168 | for (;;) { |
1169 | if (signal_pending_state(state, current)) { | |
e95433c7 | 1170 | timeout = -ERESTARTSYS; |
05235c53 CW |
1171 | break; |
1172 | } | |
1173 | ||
e95433c7 CW |
1174 | if (!timeout) { |
1175 | timeout = -ETIME; | |
05235c53 CW |
1176 | break; |
1177 | } | |
1178 | ||
e95433c7 CW |
1179 | timeout = io_schedule_timeout(timeout); |
1180 | ||
754c9fd5 CW |
1181 | if (intel_wait_complete(&wait) && |
1182 | intel_wait_check_request(&wait, req)) | |
05235c53 CW |
1183 | break; |
1184 | ||
1185 | set_current_state(state); | |
1186 | ||
1187 | wakeup: | |
1188 | /* Carefully check if the request is complete, giving time | |
1189 | * for the seqno to be visible following the interrupt. | |
1190 | * We also have to check in case we are kicked by the GPU | |
1191 | * reset in order to drop the struct_mutex. | |
1192 | */ | |
1193 | if (__i915_request_irq_complete(req)) | |
1194 | break; | |
1195 | ||
221fe799 CW |
1196 | /* If the GPU is hung, and we hold the lock, reset the GPU |
1197 | * and then check for completion. On a full reset, the engine's | |
1198 | * HW seqno will be advanced passed us and we are complete. | |
1199 | * If we do a partial reset, we have to wait for the GPU to | |
1200 | * resume and update the breadcrumb. | |
1201 | * | |
1202 | * If we don't hold the mutex, we can just wait for the worker | |
1203 | * to come along and update the breadcrumb (either directly | |
1204 | * itself, or indirectly by recovering the GPU). | |
1205 | */ | |
1206 | if (flags & I915_WAIT_LOCKED && | |
e0705114 | 1207 | __i915_wait_request_check_and_reset(req)) |
221fe799 | 1208 | continue; |
221fe799 | 1209 | |
05235c53 CW |
1210 | /* Only spin if we know the GPU is processing this request */ |
1211 | if (i915_spin_request(req, state, 2)) | |
1212 | break; | |
d6a2289d CW |
1213 | |
1214 | if (!intel_wait_check_request(&wait, req)) { | |
1215 | intel_engine_remove_wait(req->engine, &wait); | |
1216 | goto restart; | |
1217 | } | |
05235c53 | 1218 | } |
05235c53 CW |
1219 | |
1220 | intel_engine_remove_wait(req->engine, &wait); | |
05235c53 | 1221 | complete: |
a49625f9 | 1222 | __set_current_state(TASK_RUNNING); |
7de53bf7 CW |
1223 | if (flags & I915_WAIT_LOCKED) |
1224 | remove_wait_queue(errq, &reset); | |
a49625f9 | 1225 | remove_wait_queue(&req->execute, &exec); |
05235c53 CW |
1226 | trace_i915_gem_request_wait_end(req); |
1227 | ||
e95433c7 | 1228 | return timeout; |
05235c53 | 1229 | } |
4b8de8e6 | 1230 | |
28176ef4 | 1231 | static void engine_retire_requests(struct intel_engine_cs *engine) |
4b8de8e6 CW |
1232 | { |
1233 | struct drm_i915_gem_request *request, *next; | |
754c9fd5 CW |
1234 | u32 seqno = intel_engine_get_seqno(engine); |
1235 | LIST_HEAD(retire); | |
4b8de8e6 | 1236 | |
754c9fd5 | 1237 | spin_lock_irq(&engine->timeline->lock); |
73cb9701 CW |
1238 | list_for_each_entry_safe(request, next, |
1239 | &engine->timeline->requests, link) { | |
754c9fd5 CW |
1240 | if (!i915_seqno_passed(seqno, request->global_seqno)) |
1241 | break; | |
4b8de8e6 | 1242 | |
754c9fd5 | 1243 | list_move_tail(&request->link, &retire); |
4b8de8e6 | 1244 | } |
754c9fd5 CW |
1245 | spin_unlock_irq(&engine->timeline->lock); |
1246 | ||
1247 | list_for_each_entry_safe(request, next, &retire, link) | |
1248 | i915_gem_request_retire(request); | |
4b8de8e6 CW |
1249 | } |
1250 | ||
1251 | void i915_gem_retire_requests(struct drm_i915_private *dev_priv) | |
1252 | { | |
1253 | struct intel_engine_cs *engine; | |
28176ef4 | 1254 | enum intel_engine_id id; |
4b8de8e6 CW |
1255 | |
1256 | lockdep_assert_held(&dev_priv->drm.struct_mutex); | |
1257 | ||
28176ef4 | 1258 | if (!dev_priv->gt.active_requests) |
4b8de8e6 CW |
1259 | return; |
1260 | ||
28176ef4 CW |
1261 | for_each_engine(engine, dev_priv, id) |
1262 | engine_retire_requests(engine); | |
4b8de8e6 | 1263 | } |
c835c550 CW |
1264 | |
1265 | #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST) | |
1266 | #include "selftests/mock_request.c" | |
1267 | #include "selftests/i915_gem_request.c" | |
1268 | #endif |