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05235c53 CW |
1 | /* |
2 | * Copyright © 2008-2015 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | */ | |
24 | ||
fa545cbf | 25 | #include <linux/prefetch.h> |
b52992c0 | 26 | #include <linux/dma-fence-array.h> |
fa545cbf | 27 | |
05235c53 CW |
28 | #include "i915_drv.h" |
29 | ||
f54d1867 | 30 | static const char *i915_fence_get_driver_name(struct dma_fence *fence) |
04769652 CW |
31 | { |
32 | return "i915"; | |
33 | } | |
34 | ||
f54d1867 | 35 | static const char *i915_fence_get_timeline_name(struct dma_fence *fence) |
04769652 | 36 | { |
73cb9701 | 37 | return to_request(fence)->timeline->common->name; |
04769652 CW |
38 | } |
39 | ||
f54d1867 | 40 | static bool i915_fence_signaled(struct dma_fence *fence) |
04769652 CW |
41 | { |
42 | return i915_gem_request_completed(to_request(fence)); | |
43 | } | |
44 | ||
f54d1867 | 45 | static bool i915_fence_enable_signaling(struct dma_fence *fence) |
04769652 CW |
46 | { |
47 | if (i915_fence_signaled(fence)) | |
48 | return false; | |
49 | ||
50 | intel_engine_enable_signaling(to_request(fence)); | |
51 | return true; | |
52 | } | |
53 | ||
f54d1867 | 54 | static signed long i915_fence_wait(struct dma_fence *fence, |
04769652 | 55 | bool interruptible, |
e95433c7 | 56 | signed long timeout) |
04769652 | 57 | { |
e95433c7 | 58 | return i915_wait_request(to_request(fence), interruptible, timeout); |
04769652 CW |
59 | } |
60 | ||
f54d1867 | 61 | static void i915_fence_release(struct dma_fence *fence) |
04769652 CW |
62 | { |
63 | struct drm_i915_gem_request *req = to_request(fence); | |
64 | ||
fc158405 CW |
65 | /* The request is put onto a RCU freelist (i.e. the address |
66 | * is immediately reused), mark the fences as being freed now. | |
67 | * Otherwise the debugobjects for the fences are only marked as | |
68 | * freed when the slab cache itself is freed, and so we would get | |
69 | * caught trying to reuse dead objects. | |
70 | */ | |
71 | i915_sw_fence_fini(&req->submit); | |
72 | i915_sw_fence_fini(&req->execute); | |
73 | ||
04769652 CW |
74 | kmem_cache_free(req->i915->requests, req); |
75 | } | |
76 | ||
f54d1867 | 77 | const struct dma_fence_ops i915_fence_ops = { |
04769652 CW |
78 | .get_driver_name = i915_fence_get_driver_name, |
79 | .get_timeline_name = i915_fence_get_timeline_name, | |
80 | .enable_signaling = i915_fence_enable_signaling, | |
81 | .signaled = i915_fence_signaled, | |
82 | .wait = i915_fence_wait, | |
83 | .release = i915_fence_release, | |
04769652 CW |
84 | }; |
85 | ||
05235c53 CW |
86 | int i915_gem_request_add_to_client(struct drm_i915_gem_request *req, |
87 | struct drm_file *file) | |
88 | { | |
89 | struct drm_i915_private *dev_private; | |
90 | struct drm_i915_file_private *file_priv; | |
91 | ||
92 | WARN_ON(!req || !file || req->file_priv); | |
93 | ||
94 | if (!req || !file) | |
95 | return -EINVAL; | |
96 | ||
97 | if (req->file_priv) | |
98 | return -EINVAL; | |
99 | ||
100 | dev_private = req->i915; | |
101 | file_priv = file->driver_priv; | |
102 | ||
103 | spin_lock(&file_priv->mm.lock); | |
104 | req->file_priv = file_priv; | |
105 | list_add_tail(&req->client_list, &file_priv->mm.request_list); | |
106 | spin_unlock(&file_priv->mm.lock); | |
107 | ||
05235c53 CW |
108 | return 0; |
109 | } | |
110 | ||
111 | static inline void | |
112 | i915_gem_request_remove_from_client(struct drm_i915_gem_request *request) | |
113 | { | |
114 | struct drm_i915_file_private *file_priv = request->file_priv; | |
115 | ||
116 | if (!file_priv) | |
117 | return; | |
118 | ||
119 | spin_lock(&file_priv->mm.lock); | |
120 | list_del(&request->client_list); | |
121 | request->file_priv = NULL; | |
122 | spin_unlock(&file_priv->mm.lock); | |
05235c53 CW |
123 | } |
124 | ||
52e54209 CW |
125 | static struct i915_dependency * |
126 | i915_dependency_alloc(struct drm_i915_private *i915) | |
127 | { | |
128 | return kmem_cache_alloc(i915->dependencies, GFP_KERNEL); | |
129 | } | |
130 | ||
131 | static void | |
132 | i915_dependency_free(struct drm_i915_private *i915, | |
133 | struct i915_dependency *dep) | |
134 | { | |
135 | kmem_cache_free(i915->dependencies, dep); | |
136 | } | |
137 | ||
138 | static void | |
139 | __i915_priotree_add_dependency(struct i915_priotree *pt, | |
140 | struct i915_priotree *signal, | |
141 | struct i915_dependency *dep, | |
142 | unsigned long flags) | |
143 | { | |
20311bd3 | 144 | INIT_LIST_HEAD(&dep->dfs_link); |
52e54209 CW |
145 | list_add(&dep->wait_link, &signal->waiters_list); |
146 | list_add(&dep->signal_link, &pt->signalers_list); | |
147 | dep->signaler = signal; | |
148 | dep->flags = flags; | |
149 | } | |
150 | ||
151 | static int | |
152 | i915_priotree_add_dependency(struct drm_i915_private *i915, | |
153 | struct i915_priotree *pt, | |
154 | struct i915_priotree *signal) | |
155 | { | |
156 | struct i915_dependency *dep; | |
157 | ||
158 | dep = i915_dependency_alloc(i915); | |
159 | if (!dep) | |
160 | return -ENOMEM; | |
161 | ||
162 | __i915_priotree_add_dependency(pt, signal, dep, I915_DEPENDENCY_ALLOC); | |
163 | return 0; | |
164 | } | |
165 | ||
166 | static void | |
167 | i915_priotree_fini(struct drm_i915_private *i915, struct i915_priotree *pt) | |
168 | { | |
169 | struct i915_dependency *dep, *next; | |
170 | ||
20311bd3 CW |
171 | GEM_BUG_ON(!RB_EMPTY_NODE(&pt->node)); |
172 | ||
52e54209 CW |
173 | /* Everyone we depended upon (the fences we wait to be signaled) |
174 | * should retire before us and remove themselves from our list. | |
175 | * However, retirement is run independently on each timeline and | |
176 | * so we may be called out-of-order. | |
177 | */ | |
178 | list_for_each_entry_safe(dep, next, &pt->signalers_list, signal_link) { | |
179 | list_del(&dep->wait_link); | |
180 | if (dep->flags & I915_DEPENDENCY_ALLOC) | |
181 | i915_dependency_free(i915, dep); | |
182 | } | |
183 | ||
184 | /* Remove ourselves from everyone who depends upon us */ | |
185 | list_for_each_entry_safe(dep, next, &pt->waiters_list, wait_link) { | |
186 | list_del(&dep->signal_link); | |
187 | if (dep->flags & I915_DEPENDENCY_ALLOC) | |
188 | i915_dependency_free(i915, dep); | |
189 | } | |
190 | } | |
191 | ||
192 | static void | |
193 | i915_priotree_init(struct i915_priotree *pt) | |
194 | { | |
195 | INIT_LIST_HEAD(&pt->signalers_list); | |
196 | INIT_LIST_HEAD(&pt->waiters_list); | |
20311bd3 CW |
197 | RB_CLEAR_NODE(&pt->node); |
198 | pt->priority = INT_MIN; | |
52e54209 CW |
199 | } |
200 | ||
12d3173b CW |
201 | static int reset_all_global_seqno(struct drm_i915_private *i915, u32 seqno) |
202 | { | |
203 | struct i915_gem_timeline *timeline = &i915->gt.global_timeline; | |
204 | struct intel_engine_cs *engine; | |
205 | enum intel_engine_id id; | |
206 | int ret; | |
207 | ||
208 | /* Carefully retire all requests without writing to the rings */ | |
209 | ret = i915_gem_wait_for_idle(i915, | |
210 | I915_WAIT_INTERRUPTIBLE | | |
211 | I915_WAIT_LOCKED); | |
212 | if (ret) | |
213 | return ret; | |
214 | ||
215 | i915_gem_retire_requests(i915); | |
216 | GEM_BUG_ON(i915->gt.active_requests > 1); | |
217 | ||
218 | /* If the seqno wraps around, we need to clear the breadcrumb rbtree */ | |
219 | for_each_engine(engine, i915, id) { | |
220 | struct intel_timeline *tl = &timeline->engine[id]; | |
221 | ||
222 | if (!i915_seqno_passed(seqno, tl->seqno)) { | |
223 | /* spin until threads are complete */ | |
224 | while (intel_breadcrumbs_busy(engine)) | |
225 | cond_resched(); | |
226 | } | |
227 | ||
228 | /* Finally reset hw state */ | |
229 | tl->seqno = seqno; | |
230 | intel_engine_init_global_seqno(engine, seqno); | |
231 | } | |
232 | ||
233 | list_for_each_entry(timeline, &i915->gt.timelines, link) { | |
234 | for_each_engine(engine, i915, id) { | |
235 | struct intel_timeline *tl = &timeline->engine[id]; | |
236 | ||
237 | memset(tl->sync_seqno, 0, sizeof(tl->sync_seqno)); | |
238 | } | |
239 | } | |
240 | ||
241 | return 0; | |
242 | } | |
243 | ||
244 | int i915_gem_set_global_seqno(struct drm_device *dev, u32 seqno) | |
245 | { | |
246 | struct drm_i915_private *dev_priv = to_i915(dev); | |
247 | ||
248 | lockdep_assert_held(&dev_priv->drm.struct_mutex); | |
249 | ||
250 | if (seqno == 0) | |
251 | return -EINVAL; | |
252 | ||
253 | /* HWS page needs to be set less than what we | |
254 | * will inject to ring | |
255 | */ | |
256 | return reset_all_global_seqno(dev_priv, seqno - 1); | |
257 | } | |
258 | ||
259 | static int reserve_seqno(struct intel_engine_cs *engine) | |
260 | { | |
261 | u32 active = ++engine->timeline->inflight_seqnos; | |
262 | u32 seqno = engine->timeline->seqno; | |
263 | int ret; | |
264 | ||
265 | /* Reservation is fine until we need to wrap around */ | |
266 | if (likely(!add_overflows(seqno, active))) | |
267 | return 0; | |
268 | ||
269 | ret = reset_all_global_seqno(engine->i915, 0); | |
270 | if (ret) { | |
271 | engine->timeline->inflight_seqnos--; | |
272 | return ret; | |
273 | } | |
274 | ||
275 | return 0; | |
276 | } | |
277 | ||
9b6586ae CW |
278 | static void unreserve_seqno(struct intel_engine_cs *engine) |
279 | { | |
280 | GEM_BUG_ON(!engine->timeline->inflight_seqnos); | |
281 | engine->timeline->inflight_seqnos--; | |
282 | } | |
283 | ||
fa545cbf CW |
284 | void i915_gem_retire_noop(struct i915_gem_active *active, |
285 | struct drm_i915_gem_request *request) | |
286 | { | |
287 | /* Space left intentionally blank */ | |
288 | } | |
289 | ||
05235c53 CW |
290 | static void i915_gem_request_retire(struct drm_i915_gem_request *request) |
291 | { | |
e8a9c58f | 292 | struct intel_engine_cs *engine = request->engine; |
fa545cbf CW |
293 | struct i915_gem_active *active, *next; |
294 | ||
4c7d62c6 | 295 | lockdep_assert_held(&request->i915->drm.struct_mutex); |
48bc2a4a CW |
296 | GEM_BUG_ON(!i915_sw_fence_signaled(&request->submit)); |
297 | GEM_BUG_ON(!i915_sw_fence_signaled(&request->execute)); | |
4c7d62c6 | 298 | GEM_BUG_ON(!i915_gem_request_completed(request)); |
4302055b | 299 | GEM_BUG_ON(!request->i915->gt.active_requests); |
4c7d62c6 | 300 | |
05235c53 | 301 | trace_i915_gem_request_retire(request); |
80b204bc | 302 | |
e8a9c58f | 303 | spin_lock_irq(&engine->timeline->lock); |
e95433c7 | 304 | list_del_init(&request->link); |
e8a9c58f | 305 | spin_unlock_irq(&engine->timeline->lock); |
05235c53 CW |
306 | |
307 | /* We know the GPU must have read the request to have | |
308 | * sent us the seqno + interrupt, so use the position | |
309 | * of tail of the request to update the last known position | |
310 | * of the GPU head. | |
311 | * | |
312 | * Note this requires that we are always called in request | |
313 | * completion order. | |
314 | */ | |
675d9ad7 | 315 | list_del(&request->ring_link); |
1dae2dfb | 316 | request->ring->last_retired_head = request->postfix; |
4302055b CW |
317 | if (!--request->i915->gt.active_requests) { |
318 | GEM_BUG_ON(!request->i915->gt.awake); | |
319 | mod_delayed_work(request->i915->wq, | |
320 | &request->i915->gt.idle_work, | |
321 | msecs_to_jiffies(100)); | |
322 | } | |
9b6586ae | 323 | unreserve_seqno(request->engine); |
05235c53 | 324 | |
fa545cbf CW |
325 | /* Walk through the active list, calling retire on each. This allows |
326 | * objects to track their GPU activity and mark themselves as idle | |
327 | * when their *last* active request is completed (updating state | |
328 | * tracking lists for eviction, active references for GEM, etc). | |
329 | * | |
330 | * As the ->retire() may free the node, we decouple it first and | |
331 | * pass along the auxiliary information (to avoid dereferencing | |
332 | * the node after the callback). | |
333 | */ | |
334 | list_for_each_entry_safe(active, next, &request->active_list, link) { | |
335 | /* In microbenchmarks or focusing upon time inside the kernel, | |
336 | * we may spend an inordinate amount of time simply handling | |
337 | * the retirement of requests and processing their callbacks. | |
338 | * Of which, this loop itself is particularly hot due to the | |
339 | * cache misses when jumping around the list of i915_gem_active. | |
340 | * So we try to keep this loop as streamlined as possible and | |
341 | * also prefetch the next i915_gem_active to try and hide | |
342 | * the likely cache miss. | |
343 | */ | |
344 | prefetchw(next); | |
345 | ||
346 | INIT_LIST_HEAD(&active->link); | |
0eafec6d | 347 | RCU_INIT_POINTER(active->request, NULL); |
fa545cbf CW |
348 | |
349 | active->retire(active, request); | |
350 | } | |
351 | ||
05235c53 CW |
352 | i915_gem_request_remove_from_client(request); |
353 | ||
e5e1fc47 | 354 | /* Retirement decays the ban score as it is a sign of ctx progress */ |
bc1d53c6 MK |
355 | if (request->ctx->ban_score > 0) |
356 | request->ctx->ban_score--; | |
e5e1fc47 | 357 | |
e8a9c58f CW |
358 | /* The backing object for the context is done after switching to the |
359 | * *next* context. Therefore we cannot retire the previous context until | |
360 | * the next context has already started running. However, since we | |
361 | * cannot take the required locks at i915_gem_request_submit() we | |
362 | * defer the unpinning of the active context to now, retirement of | |
363 | * the subsequent request. | |
364 | */ | |
365 | if (engine->last_retired_context) | |
366 | engine->context_unpin(engine, engine->last_retired_context); | |
367 | engine->last_retired_context = request->ctx; | |
d07f0e59 CW |
368 | |
369 | dma_fence_signal(&request->fence); | |
52e54209 CW |
370 | |
371 | i915_priotree_fini(request->i915, &request->priotree); | |
e8a261ea | 372 | i915_gem_request_put(request); |
05235c53 CW |
373 | } |
374 | ||
375 | void i915_gem_request_retire_upto(struct drm_i915_gem_request *req) | |
376 | { | |
377 | struct intel_engine_cs *engine = req->engine; | |
378 | struct drm_i915_gem_request *tmp; | |
379 | ||
380 | lockdep_assert_held(&req->i915->drm.struct_mutex); | |
4ffd6e0c CW |
381 | GEM_BUG_ON(!i915_gem_request_completed(req)); |
382 | ||
e95433c7 CW |
383 | if (list_empty(&req->link)) |
384 | return; | |
05235c53 CW |
385 | |
386 | do { | |
73cb9701 | 387 | tmp = list_first_entry(&engine->timeline->requests, |
efdf7c06 | 388 | typeof(*tmp), link); |
05235c53 CW |
389 | |
390 | i915_gem_request_retire(tmp); | |
391 | } while (tmp != req); | |
05235c53 CW |
392 | } |
393 | ||
9b6586ae | 394 | static u32 timeline_get_seqno(struct intel_timeline *tl) |
28176ef4 | 395 | { |
9b6586ae | 396 | return ++tl->seqno; |
28176ef4 CW |
397 | } |
398 | ||
d55ac5bf | 399 | void __i915_gem_request_submit(struct drm_i915_gem_request *request) |
5590af3e | 400 | { |
73cb9701 | 401 | struct intel_engine_cs *engine = request->engine; |
f2d13290 CW |
402 | struct intel_timeline *timeline; |
403 | u32 seqno; | |
5590af3e | 404 | |
80b204bc CW |
405 | /* Transfer from per-context onto the global per-engine timeline */ |
406 | timeline = engine->timeline; | |
407 | GEM_BUG_ON(timeline == request->timeline); | |
d55ac5bf | 408 | assert_spin_locked(&timeline->lock); |
5590af3e | 409 | |
9b6586ae | 410 | seqno = timeline_get_seqno(timeline); |
f2d13290 CW |
411 | GEM_BUG_ON(!seqno); |
412 | GEM_BUG_ON(i915_seqno_passed(intel_engine_get_seqno(engine), seqno)); | |
413 | ||
f2d13290 CW |
414 | /* We may be recursing from the signal callback of another i915 fence */ |
415 | spin_lock_nested(&request->lock, SINGLE_DEPTH_NESTING); | |
416 | request->global_seqno = seqno; | |
417 | if (test_bit(DMA_FENCE_FLAG_ENABLE_SIGNAL_BIT, &request->fence.flags)) | |
418 | intel_engine_enable_signaling(request); | |
419 | spin_unlock(&request->lock); | |
420 | ||
421 | GEM_BUG_ON(!request->global_seqno); | |
caddfe71 CW |
422 | engine->emit_breadcrumb(request, |
423 | request->ring->vaddr + request->postfix); | |
5590af3e | 424 | |
bb89485e | 425 | spin_lock(&request->timeline->lock); |
80b204bc CW |
426 | list_move_tail(&request->link, &timeline->requests); |
427 | spin_unlock(&request->timeline->lock); | |
428 | ||
23902e49 | 429 | i915_sw_fence_commit(&request->execute); |
354d036f | 430 | trace_i915_gem_request_execute(request); |
d55ac5bf CW |
431 | } |
432 | ||
433 | void i915_gem_request_submit(struct drm_i915_gem_request *request) | |
434 | { | |
435 | struct intel_engine_cs *engine = request->engine; | |
436 | unsigned long flags; | |
23902e49 | 437 | |
d55ac5bf CW |
438 | /* Will be called from irq-context when using foreign fences. */ |
439 | spin_lock_irqsave(&engine->timeline->lock, flags); | |
440 | ||
441 | __i915_gem_request_submit(request); | |
442 | ||
443 | spin_unlock_irqrestore(&engine->timeline->lock, flags); | |
444 | } | |
445 | ||
446 | static int __i915_sw_fence_call | |
447 | submit_notify(struct i915_sw_fence *fence, enum i915_sw_fence_notify state) | |
448 | { | |
48bc2a4a CW |
449 | struct drm_i915_gem_request *request = |
450 | container_of(fence, typeof(*request), submit); | |
d55ac5bf | 451 | |
48bc2a4a CW |
452 | switch (state) { |
453 | case FENCE_COMPLETE: | |
354d036f | 454 | trace_i915_gem_request_submit(request); |
d55ac5bf | 455 | request->engine->submit_request(request); |
48bc2a4a CW |
456 | break; |
457 | ||
458 | case FENCE_FREE: | |
459 | i915_gem_request_put(request); | |
460 | break; | |
d55ac5bf | 461 | } |
80b204bc | 462 | |
5590af3e CW |
463 | return NOTIFY_DONE; |
464 | } | |
465 | ||
23902e49 CW |
466 | static int __i915_sw_fence_call |
467 | execute_notify(struct i915_sw_fence *fence, enum i915_sw_fence_notify state) | |
468 | { | |
48bc2a4a CW |
469 | struct drm_i915_gem_request *request = |
470 | container_of(fence, typeof(*request), execute); | |
471 | ||
472 | switch (state) { | |
473 | case FENCE_COMPLETE: | |
474 | break; | |
475 | ||
476 | case FENCE_FREE: | |
477 | i915_gem_request_put(request); | |
478 | break; | |
479 | } | |
480 | ||
23902e49 CW |
481 | return NOTIFY_DONE; |
482 | } | |
483 | ||
8e637178 CW |
484 | /** |
485 | * i915_gem_request_alloc - allocate a request structure | |
486 | * | |
487 | * @engine: engine that we wish to issue the request on. | |
488 | * @ctx: context that the request will be associated with. | |
489 | * This can be NULL if the request is not directly related to | |
490 | * any specific user context, in which case this function will | |
491 | * choose an appropriate context to use. | |
492 | * | |
493 | * Returns a pointer to the allocated request if successful, | |
494 | * or an error code if not. | |
495 | */ | |
496 | struct drm_i915_gem_request * | |
497 | i915_gem_request_alloc(struct intel_engine_cs *engine, | |
498 | struct i915_gem_context *ctx) | |
05235c53 CW |
499 | { |
500 | struct drm_i915_private *dev_priv = engine->i915; | |
05235c53 CW |
501 | struct drm_i915_gem_request *req; |
502 | int ret; | |
503 | ||
28176ef4 CW |
504 | lockdep_assert_held(&dev_priv->drm.struct_mutex); |
505 | ||
05235c53 | 506 | /* ABI: Before userspace accesses the GPU (e.g. execbuffer), report |
6ffb7d07 | 507 | * EIO if the GPU is already wedged. |
05235c53 | 508 | */ |
6ffb7d07 CW |
509 | if (i915_terminally_wedged(&dev_priv->gpu_error)) |
510 | return ERR_PTR(-EIO); | |
05235c53 | 511 | |
e8a9c58f CW |
512 | /* Pinning the contexts may generate requests in order to acquire |
513 | * GGTT space, so do this first before we reserve a seqno for | |
514 | * ourselves. | |
515 | */ | |
516 | ret = engine->context_pin(engine, ctx); | |
28176ef4 CW |
517 | if (ret) |
518 | return ERR_PTR(ret); | |
519 | ||
9b6586ae | 520 | ret = reserve_seqno(engine); |
e8a9c58f CW |
521 | if (ret) |
522 | goto err_unpin; | |
523 | ||
9b5f4e5e | 524 | /* Move the oldest request to the slab-cache (if not in use!) */ |
73cb9701 | 525 | req = list_first_entry_or_null(&engine->timeline->requests, |
efdf7c06 | 526 | typeof(*req), link); |
80b204bc | 527 | if (req && __i915_gem_request_completed(req)) |
2a1d7752 | 528 | i915_gem_request_retire(req); |
9b5f4e5e | 529 | |
5a198b8c CW |
530 | /* Beware: Dragons be flying overhead. |
531 | * | |
532 | * We use RCU to look up requests in flight. The lookups may | |
533 | * race with the request being allocated from the slab freelist. | |
534 | * That is the request we are writing to here, may be in the process | |
1426f715 | 535 | * of being read by __i915_gem_active_get_rcu(). As such, |
5a198b8c CW |
536 | * we have to be very careful when overwriting the contents. During |
537 | * the RCU lookup, we change chase the request->engine pointer, | |
65e4760e | 538 | * read the request->global_seqno and increment the reference count. |
5a198b8c CW |
539 | * |
540 | * The reference count is incremented atomically. If it is zero, | |
541 | * the lookup knows the request is unallocated and complete. Otherwise, | |
542 | * it is either still in use, or has been reallocated and reset | |
f54d1867 CW |
543 | * with dma_fence_init(). This increment is safe for release as we |
544 | * check that the request we have a reference to and matches the active | |
5a198b8c CW |
545 | * request. |
546 | * | |
547 | * Before we increment the refcount, we chase the request->engine | |
548 | * pointer. We must not call kmem_cache_zalloc() or else we set | |
549 | * that pointer to NULL and cause a crash during the lookup. If | |
550 | * we see the request is completed (based on the value of the | |
551 | * old engine and seqno), the lookup is complete and reports NULL. | |
552 | * If we decide the request is not completed (new engine or seqno), | |
553 | * then we grab a reference and double check that it is still the | |
554 | * active request - which it won't be and restart the lookup. | |
555 | * | |
556 | * Do not use kmem_cache_zalloc() here! | |
557 | */ | |
558 | req = kmem_cache_alloc(dev_priv->requests, GFP_KERNEL); | |
28176ef4 CW |
559 | if (!req) { |
560 | ret = -ENOMEM; | |
561 | goto err_unreserve; | |
562 | } | |
05235c53 | 563 | |
80b204bc CW |
564 | req->timeline = i915_gem_context_lookup_timeline(ctx, engine); |
565 | GEM_BUG_ON(req->timeline == engine->timeline); | |
73cb9701 | 566 | |
04769652 | 567 | spin_lock_init(&req->lock); |
f54d1867 CW |
568 | dma_fence_init(&req->fence, |
569 | &i915_fence_ops, | |
570 | &req->lock, | |
73cb9701 | 571 | req->timeline->fence_context, |
9b6586ae | 572 | timeline_get_seqno(req->timeline)); |
04769652 | 573 | |
48bc2a4a CW |
574 | /* We bump the ref for the fence chain */ |
575 | i915_sw_fence_init(&i915_gem_request_get(req)->submit, submit_notify); | |
576 | i915_sw_fence_init(&i915_gem_request_get(req)->execute, execute_notify); | |
577 | ||
23902e49 CW |
578 | /* Ensure that the execute fence completes after the submit fence - |
579 | * as we complete the execute fence from within the submit fence | |
580 | * callback, its completion would otherwise be visible first. | |
581 | */ | |
582 | i915_sw_fence_await_sw_fence(&req->execute, &req->submit, &req->execq); | |
5590af3e | 583 | |
52e54209 CW |
584 | i915_priotree_init(&req->priotree); |
585 | ||
fa545cbf | 586 | INIT_LIST_HEAD(&req->active_list); |
05235c53 CW |
587 | req->i915 = dev_priv; |
588 | req->engine = engine; | |
e8a9c58f | 589 | req->ctx = ctx; |
05235c53 | 590 | |
5a198b8c | 591 | /* No zalloc, must clear what we need by hand */ |
f2d13290 | 592 | req->global_seqno = 0; |
5a198b8c | 593 | req->file_priv = NULL; |
058d88c4 | 594 | req->batch = NULL; |
5a198b8c | 595 | |
05235c53 CW |
596 | /* |
597 | * Reserve space in the ring buffer for all the commands required to | |
598 | * eventually emit this request. This is to guarantee that the | |
599 | * i915_add_request() call can't fail. Note that the reserve may need | |
600 | * to be redone if the request is not actually submitted straight | |
601 | * away, e.g. because a GPU scheduler has deferred it. | |
602 | */ | |
603 | req->reserved_space = MIN_SPACE_FOR_ADD_REQUEST; | |
98f29e8d | 604 | GEM_BUG_ON(req->reserved_space < engine->emit_breadcrumb_sz); |
05235c53 | 605 | |
f73e7399 | 606 | ret = engine->request_alloc(req); |
05235c53 CW |
607 | if (ret) |
608 | goto err_ctx; | |
609 | ||
d045446d CW |
610 | /* Record the position of the start of the request so that |
611 | * should we detect the updated seqno part-way through the | |
612 | * GPU processing the request, we never over-estimate the | |
613 | * position of the head. | |
614 | */ | |
615 | req->head = req->ring->tail; | |
616 | ||
9b6586ae CW |
617 | /* Check that we didn't interrupt ourselves with a new request */ |
618 | GEM_BUG_ON(req->timeline->seqno != req->fence.seqno); | |
8e637178 | 619 | return req; |
05235c53 CW |
620 | |
621 | err_ctx: | |
1618bdb8 CW |
622 | /* Make sure we didn't add ourselves to external state before freeing */ |
623 | GEM_BUG_ON(!list_empty(&req->active_list)); | |
624 | GEM_BUG_ON(!list_empty(&req->priotree.signalers_list)); | |
625 | GEM_BUG_ON(!list_empty(&req->priotree.waiters_list)); | |
626 | ||
05235c53 | 627 | kmem_cache_free(dev_priv->requests, req); |
28176ef4 | 628 | err_unreserve: |
9b6586ae | 629 | unreserve_seqno(engine); |
e8a9c58f CW |
630 | err_unpin: |
631 | engine->context_unpin(engine, ctx); | |
8e637178 | 632 | return ERR_PTR(ret); |
05235c53 CW |
633 | } |
634 | ||
a2bc4695 CW |
635 | static int |
636 | i915_gem_request_await_request(struct drm_i915_gem_request *to, | |
637 | struct drm_i915_gem_request *from) | |
638 | { | |
85e17f59 | 639 | int ret; |
a2bc4695 CW |
640 | |
641 | GEM_BUG_ON(to == from); | |
642 | ||
52e54209 CW |
643 | if (to->engine->schedule) { |
644 | ret = i915_priotree_add_dependency(to->i915, | |
645 | &to->priotree, | |
646 | &from->priotree); | |
647 | if (ret < 0) | |
648 | return ret; | |
649 | } | |
650 | ||
73cb9701 | 651 | if (to->timeline == from->timeline) |
a2bc4695 CW |
652 | return 0; |
653 | ||
73cb9701 CW |
654 | if (to->engine == from->engine) { |
655 | ret = i915_sw_fence_await_sw_fence_gfp(&to->submit, | |
656 | &from->submit, | |
657 | GFP_KERNEL); | |
658 | return ret < 0 ? ret : 0; | |
659 | } | |
660 | ||
65e4760e CW |
661 | if (!from->global_seqno) { |
662 | ret = i915_sw_fence_await_dma_fence(&to->submit, | |
663 | &from->fence, 0, | |
664 | GFP_KERNEL); | |
665 | return ret < 0 ? ret : 0; | |
666 | } | |
667 | ||
85e17f59 | 668 | if (from->global_seqno <= to->timeline->sync_seqno[from->engine->id]) |
a2bc4695 CW |
669 | return 0; |
670 | ||
671 | trace_i915_gem_ring_sync_to(to, from); | |
672 | if (!i915.semaphores) { | |
0a046a0e CW |
673 | if (!i915_spin_request(from, TASK_INTERRUPTIBLE, 2)) { |
674 | ret = i915_sw_fence_await_dma_fence(&to->submit, | |
675 | &from->fence, 0, | |
676 | GFP_KERNEL); | |
677 | if (ret < 0) | |
678 | return ret; | |
679 | } | |
a2bc4695 CW |
680 | } else { |
681 | ret = to->engine->semaphore.sync_to(to, from); | |
682 | if (ret) | |
683 | return ret; | |
684 | } | |
685 | ||
85e17f59 | 686 | to->timeline->sync_seqno[from->engine->id] = from->global_seqno; |
a2bc4695 CW |
687 | return 0; |
688 | } | |
689 | ||
b52992c0 CW |
690 | int |
691 | i915_gem_request_await_dma_fence(struct drm_i915_gem_request *req, | |
692 | struct dma_fence *fence) | |
693 | { | |
694 | struct dma_fence_array *array; | |
695 | int ret; | |
696 | int i; | |
697 | ||
698 | if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &fence->flags)) | |
699 | return 0; | |
700 | ||
701 | if (dma_fence_is_i915(fence)) | |
702 | return i915_gem_request_await_request(req, to_request(fence)); | |
703 | ||
704 | if (!dma_fence_is_array(fence)) { | |
705 | ret = i915_sw_fence_await_dma_fence(&req->submit, | |
706 | fence, I915_FENCE_TIMEOUT, | |
707 | GFP_KERNEL); | |
708 | return ret < 0 ? ret : 0; | |
709 | } | |
710 | ||
711 | /* Note that if the fence-array was created in signal-on-any mode, | |
712 | * we should *not* decompose it into its individual fences. However, | |
713 | * we don't currently store which mode the fence-array is operating | |
714 | * in. Fortunately, the only user of signal-on-any is private to | |
715 | * amdgpu and we should not see any incoming fence-array from | |
716 | * sync-file being in signal-on-any mode. | |
717 | */ | |
718 | ||
719 | array = to_dma_fence_array(fence); | |
720 | for (i = 0; i < array->num_fences; i++) { | |
721 | struct dma_fence *child = array->fences[i]; | |
722 | ||
723 | if (dma_fence_is_i915(child)) | |
724 | ret = i915_gem_request_await_request(req, | |
725 | to_request(child)); | |
726 | else | |
727 | ret = i915_sw_fence_await_dma_fence(&req->submit, | |
728 | child, I915_FENCE_TIMEOUT, | |
729 | GFP_KERNEL); | |
730 | if (ret < 0) | |
731 | return ret; | |
732 | } | |
733 | ||
734 | return 0; | |
735 | } | |
736 | ||
a2bc4695 CW |
737 | /** |
738 | * i915_gem_request_await_object - set this request to (async) wait upon a bo | |
739 | * | |
740 | * @to: request we are wishing to use | |
741 | * @obj: object which may be in use on another ring. | |
742 | * | |
743 | * This code is meant to abstract object synchronization with the GPU. | |
744 | * Conceptually we serialise writes between engines inside the GPU. | |
745 | * We only allow one engine to write into a buffer at any time, but | |
746 | * multiple readers. To ensure each has a coherent view of memory, we must: | |
747 | * | |
748 | * - If there is an outstanding write request to the object, the new | |
749 | * request must wait for it to complete (either CPU or in hw, requests | |
750 | * on the same ring will be naturally ordered). | |
751 | * | |
752 | * - If we are a write request (pending_write_domain is set), the new | |
753 | * request must wait for outstanding read requests to complete. | |
754 | * | |
755 | * Returns 0 if successful, else propagates up the lower layer error. | |
756 | */ | |
757 | int | |
758 | i915_gem_request_await_object(struct drm_i915_gem_request *to, | |
759 | struct drm_i915_gem_object *obj, | |
760 | bool write) | |
761 | { | |
d07f0e59 CW |
762 | struct dma_fence *excl; |
763 | int ret = 0; | |
a2bc4695 CW |
764 | |
765 | if (write) { | |
d07f0e59 CW |
766 | struct dma_fence **shared; |
767 | unsigned int count, i; | |
768 | ||
769 | ret = reservation_object_get_fences_rcu(obj->resv, | |
770 | &excl, &count, &shared); | |
771 | if (ret) | |
772 | return ret; | |
773 | ||
774 | for (i = 0; i < count; i++) { | |
775 | ret = i915_gem_request_await_dma_fence(to, shared[i]); | |
776 | if (ret) | |
777 | break; | |
778 | ||
779 | dma_fence_put(shared[i]); | |
780 | } | |
781 | ||
782 | for (; i < count; i++) | |
783 | dma_fence_put(shared[i]); | |
784 | kfree(shared); | |
a2bc4695 | 785 | } else { |
d07f0e59 | 786 | excl = reservation_object_get_excl_rcu(obj->resv); |
a2bc4695 CW |
787 | } |
788 | ||
d07f0e59 CW |
789 | if (excl) { |
790 | if (ret == 0) | |
791 | ret = i915_gem_request_await_dma_fence(to, excl); | |
a2bc4695 | 792 | |
d07f0e59 | 793 | dma_fence_put(excl); |
a2bc4695 CW |
794 | } |
795 | ||
d07f0e59 | 796 | return ret; |
a2bc4695 CW |
797 | } |
798 | ||
05235c53 CW |
799 | static void i915_gem_mark_busy(const struct intel_engine_cs *engine) |
800 | { | |
801 | struct drm_i915_private *dev_priv = engine->i915; | |
802 | ||
05235c53 CW |
803 | if (dev_priv->gt.awake) |
804 | return; | |
805 | ||
4302055b CW |
806 | GEM_BUG_ON(!dev_priv->gt.active_requests); |
807 | ||
05235c53 CW |
808 | intel_runtime_pm_get_noresume(dev_priv); |
809 | dev_priv->gt.awake = true; | |
810 | ||
54b4f68f | 811 | intel_enable_gt_powersave(dev_priv); |
05235c53 CW |
812 | i915_update_gfx_val(dev_priv); |
813 | if (INTEL_GEN(dev_priv) >= 6) | |
814 | gen6_rps_busy(dev_priv); | |
815 | ||
816 | queue_delayed_work(dev_priv->wq, | |
817 | &dev_priv->gt.retire_work, | |
818 | round_jiffies_up_relative(HZ)); | |
819 | } | |
820 | ||
821 | /* | |
822 | * NB: This function is not allowed to fail. Doing so would mean the the | |
823 | * request is not being tracked for completion but the work itself is | |
824 | * going to happen on the hardware. This would be a Bad Thing(tm). | |
825 | */ | |
17f298cf | 826 | void __i915_add_request(struct drm_i915_gem_request *request, bool flush_caches) |
05235c53 | 827 | { |
95b2ab56 CW |
828 | struct intel_engine_cs *engine = request->engine; |
829 | struct intel_ring *ring = request->ring; | |
73cb9701 | 830 | struct intel_timeline *timeline = request->timeline; |
0a046a0e | 831 | struct drm_i915_gem_request *prev; |
73dec95e | 832 | u32 *cs; |
caddfe71 | 833 | int err; |
05235c53 | 834 | |
4c7d62c6 | 835 | lockdep_assert_held(&request->i915->drm.struct_mutex); |
0f25dff6 CW |
836 | trace_i915_gem_request_add(request); |
837 | ||
c781c978 CW |
838 | /* Make sure that no request gazumped us - if it was allocated after |
839 | * our i915_gem_request_alloc() and called __i915_add_request() before | |
840 | * us, the timeline will hold its seqno which is later than ours. | |
841 | */ | |
9b6586ae | 842 | GEM_BUG_ON(timeline->seqno != request->fence.seqno); |
c781c978 | 843 | |
05235c53 CW |
844 | /* |
845 | * To ensure that this call will not fail, space for its emissions | |
846 | * should already have been reserved in the ring buffer. Let the ring | |
847 | * know that it is time to use that space up. | |
848 | */ | |
05235c53 CW |
849 | request->reserved_space = 0; |
850 | ||
851 | /* | |
852 | * Emit any outstanding flushes - execbuf can fail to emit the flush | |
853 | * after having emitted the batchbuffer command. Hence we need to fix | |
854 | * things up similar to emitting the lazy request. The difference here | |
855 | * is that the flush _must_ happen before the next request, no matter | |
856 | * what. | |
857 | */ | |
858 | if (flush_caches) { | |
caddfe71 | 859 | err = engine->emit_flush(request, EMIT_FLUSH); |
c7fe7d25 | 860 | |
05235c53 | 861 | /* Not allowed to fail! */ |
caddfe71 | 862 | WARN(err, "engine->emit_flush() failed: %d!\n", err); |
05235c53 CW |
863 | } |
864 | ||
d045446d | 865 | /* Record the position of the start of the breadcrumb so that |
05235c53 CW |
866 | * should we detect the updated seqno part-way through the |
867 | * GPU processing the request, we never over-estimate the | |
d045446d | 868 | * position of the ring's HEAD. |
05235c53 | 869 | */ |
73dec95e TU |
870 | cs = intel_ring_begin(request, engine->emit_breadcrumb_sz); |
871 | GEM_BUG_ON(IS_ERR(cs)); | |
872 | request->postfix = intel_ring_offset(request, cs); | |
05235c53 | 873 | |
0f25dff6 CW |
874 | /* Seal the request and mark it as pending execution. Note that |
875 | * we may inspect this state, without holding any locks, during | |
876 | * hangcheck. Hence we apply the barrier to ensure that we do not | |
877 | * see a more recent value in the hws than we are tracking. | |
878 | */ | |
0a046a0e | 879 | |
73cb9701 | 880 | prev = i915_gem_active_raw(&timeline->last_request, |
0a046a0e | 881 | &request->i915->drm.struct_mutex); |
52e54209 | 882 | if (prev) { |
0a046a0e CW |
883 | i915_sw_fence_await_sw_fence(&request->submit, &prev->submit, |
884 | &request->submitq); | |
52e54209 CW |
885 | if (engine->schedule) |
886 | __i915_priotree_add_dependency(&request->priotree, | |
887 | &prev->priotree, | |
888 | &request->dep, | |
889 | 0); | |
890 | } | |
0a046a0e | 891 | |
80b204bc | 892 | spin_lock_irq(&timeline->lock); |
f2d13290 | 893 | list_add_tail(&request->link, &timeline->requests); |
80b204bc CW |
894 | spin_unlock_irq(&timeline->lock); |
895 | ||
9b6586ae | 896 | GEM_BUG_ON(timeline->seqno != request->fence.seqno); |
73cb9701 | 897 | i915_gem_active_set(&timeline->last_request, request); |
f2d13290 | 898 | |
0f25dff6 | 899 | list_add_tail(&request->ring_link, &ring->request_list); |
f2d13290 | 900 | request->emitted_jiffies = jiffies; |
0f25dff6 | 901 | |
9b6586ae CW |
902 | if (!request->i915->gt.active_requests++) |
903 | i915_gem_mark_busy(engine); | |
5590af3e | 904 | |
0de9136d CW |
905 | /* Let the backend know a new request has arrived that may need |
906 | * to adjust the existing execution schedule due to a high priority | |
907 | * request - i.e. we may want to preempt the current request in order | |
908 | * to run a high priority dependency chain *before* we can execute this | |
909 | * request. | |
910 | * | |
911 | * This is called before the request is ready to run so that we can | |
912 | * decide whether to preempt the entire chain so that it is ready to | |
913 | * run at the earliest possible convenience. | |
914 | */ | |
915 | if (engine->schedule) | |
9f792eba | 916 | engine->schedule(request, request->ctx->priority); |
0de9136d | 917 | |
5590af3e CW |
918 | local_bh_disable(); |
919 | i915_sw_fence_commit(&request->submit); | |
920 | local_bh_enable(); /* Kick the execlists tasklet if just scheduled */ | |
05235c53 CW |
921 | } |
922 | ||
221fe799 CW |
923 | static void reset_wait_queue(wait_queue_head_t *q, wait_queue_t *wait) |
924 | { | |
925 | unsigned long flags; | |
926 | ||
927 | spin_lock_irqsave(&q->lock, flags); | |
928 | if (list_empty(&wait->task_list)) | |
929 | __add_wait_queue(q, wait); | |
930 | spin_unlock_irqrestore(&q->lock, flags); | |
931 | } | |
932 | ||
05235c53 CW |
933 | static unsigned long local_clock_us(unsigned int *cpu) |
934 | { | |
935 | unsigned long t; | |
936 | ||
937 | /* Cheaply and approximately convert from nanoseconds to microseconds. | |
938 | * The result and subsequent calculations are also defined in the same | |
939 | * approximate microseconds units. The principal source of timing | |
940 | * error here is from the simple truncation. | |
941 | * | |
942 | * Note that local_clock() is only defined wrt to the current CPU; | |
943 | * the comparisons are no longer valid if we switch CPUs. Instead of | |
944 | * blocking preemption for the entire busywait, we can detect the CPU | |
945 | * switch and use that as indicator of system load and a reason to | |
946 | * stop busywaiting, see busywait_stop(). | |
947 | */ | |
948 | *cpu = get_cpu(); | |
949 | t = local_clock() >> 10; | |
950 | put_cpu(); | |
951 | ||
952 | return t; | |
953 | } | |
954 | ||
955 | static bool busywait_stop(unsigned long timeout, unsigned int cpu) | |
956 | { | |
957 | unsigned int this_cpu; | |
958 | ||
959 | if (time_after(local_clock_us(&this_cpu), timeout)) | |
960 | return true; | |
961 | ||
962 | return this_cpu != cpu; | |
963 | } | |
964 | ||
965 | bool __i915_spin_request(const struct drm_i915_gem_request *req, | |
966 | int state, unsigned long timeout_us) | |
967 | { | |
c33ed067 CW |
968 | struct intel_engine_cs *engine = req->engine; |
969 | unsigned int irq, cpu; | |
05235c53 CW |
970 | |
971 | /* When waiting for high frequency requests, e.g. during synchronous | |
972 | * rendering split between the CPU and GPU, the finite amount of time | |
973 | * required to set up the irq and wait upon it limits the response | |
974 | * rate. By busywaiting on the request completion for a short while we | |
975 | * can service the high frequency waits as quick as possible. However, | |
976 | * if it is a slow request, we want to sleep as quickly as possible. | |
977 | * The tradeoff between waiting and sleeping is roughly the time it | |
978 | * takes to sleep on a request, on the order of a microsecond. | |
979 | */ | |
980 | ||
c33ed067 | 981 | irq = atomic_read(&engine->irq_count); |
05235c53 CW |
982 | timeout_us += local_clock_us(&cpu); |
983 | do { | |
65e4760e | 984 | if (__i915_gem_request_completed(req)) |
05235c53 CW |
985 | return true; |
986 | ||
c33ed067 CW |
987 | /* Seqno are meant to be ordered *before* the interrupt. If |
988 | * we see an interrupt without a corresponding seqno advance, | |
989 | * assume we won't see one in the near future but require | |
990 | * the engine->seqno_barrier() to fixup coherency. | |
991 | */ | |
992 | if (atomic_read(&engine->irq_count) != irq) | |
993 | break; | |
994 | ||
05235c53 CW |
995 | if (signal_pending_state(state, current)) |
996 | break; | |
997 | ||
998 | if (busywait_stop(timeout_us, cpu)) | |
999 | break; | |
1000 | ||
f2f09a4c | 1001 | cpu_relax(); |
05235c53 CW |
1002 | } while (!need_resched()); |
1003 | ||
1004 | return false; | |
1005 | } | |
1006 | ||
4680816b | 1007 | static long |
23902e49 CW |
1008 | __i915_request_wait_for_execute(struct drm_i915_gem_request *request, |
1009 | unsigned int flags, | |
1010 | long timeout) | |
4680816b CW |
1011 | { |
1012 | const int state = flags & I915_WAIT_INTERRUPTIBLE ? | |
1013 | TASK_INTERRUPTIBLE : TASK_UNINTERRUPTIBLE; | |
1014 | wait_queue_head_t *q = &request->i915->gpu_error.wait_queue; | |
1015 | DEFINE_WAIT(reset); | |
1016 | DEFINE_WAIT(wait); | |
1017 | ||
1018 | if (flags & I915_WAIT_LOCKED) | |
1019 | add_wait_queue(q, &reset); | |
1020 | ||
1021 | do { | |
23902e49 | 1022 | prepare_to_wait(&request->execute.wait, &wait, state); |
4680816b | 1023 | |
23902e49 | 1024 | if (i915_sw_fence_done(&request->execute)) |
4680816b CW |
1025 | break; |
1026 | ||
1027 | if (flags & I915_WAIT_LOCKED && | |
1028 | i915_reset_in_progress(&request->i915->gpu_error)) { | |
1029 | __set_current_state(TASK_RUNNING); | |
1030 | i915_reset(request->i915); | |
1031 | reset_wait_queue(q, &reset); | |
1032 | continue; | |
1033 | } | |
1034 | ||
1035 | if (signal_pending_state(state, current)) { | |
1036 | timeout = -ERESTARTSYS; | |
1037 | break; | |
1038 | } | |
1039 | ||
969bb72c CW |
1040 | if (!timeout) { |
1041 | timeout = -ETIME; | |
1042 | break; | |
1043 | } | |
1044 | ||
4680816b | 1045 | timeout = io_schedule_timeout(timeout); |
969bb72c | 1046 | } while (1); |
23902e49 | 1047 | finish_wait(&request->execute.wait, &wait); |
4680816b CW |
1048 | |
1049 | if (flags & I915_WAIT_LOCKED) | |
1050 | remove_wait_queue(q, &reset); | |
1051 | ||
1052 | return timeout; | |
1053 | } | |
1054 | ||
05235c53 | 1055 | /** |
776f3236 | 1056 | * i915_wait_request - wait until execution of request has finished |
e95433c7 | 1057 | * @req: the request to wait upon |
ea746f36 | 1058 | * @flags: how to wait |
e95433c7 CW |
1059 | * @timeout: how long to wait in jiffies |
1060 | * | |
1061 | * i915_wait_request() waits for the request to be completed, for a | |
1062 | * maximum of @timeout jiffies (with MAX_SCHEDULE_TIMEOUT implying an | |
1063 | * unbounded wait). | |
05235c53 | 1064 | * |
e95433c7 CW |
1065 | * If the caller holds the struct_mutex, the caller must pass I915_WAIT_LOCKED |
1066 | * in via the flags, and vice versa if the struct_mutex is not held, the caller | |
1067 | * must not specify that the wait is locked. | |
05235c53 | 1068 | * |
e95433c7 CW |
1069 | * Returns the remaining time (in jiffies) if the request completed, which may |
1070 | * be zero or -ETIME if the request is unfinished after the timeout expires. | |
1071 | * May return -EINTR is called with I915_WAIT_INTERRUPTIBLE and a signal is | |
1072 | * pending before the request completes. | |
05235c53 | 1073 | */ |
e95433c7 CW |
1074 | long i915_wait_request(struct drm_i915_gem_request *req, |
1075 | unsigned int flags, | |
1076 | long timeout) | |
05235c53 | 1077 | { |
ea746f36 CW |
1078 | const int state = flags & I915_WAIT_INTERRUPTIBLE ? |
1079 | TASK_INTERRUPTIBLE : TASK_UNINTERRUPTIBLE; | |
4b36b2e5 | 1080 | wait_queue_head_t *errq = &req->i915->gpu_error.wait_queue; |
05235c53 CW |
1081 | DEFINE_WAIT(reset); |
1082 | struct intel_wait wait; | |
05235c53 CW |
1083 | |
1084 | might_sleep(); | |
22dd3bb9 | 1085 | #if IS_ENABLED(CONFIG_LOCKDEP) |
e95433c7 CW |
1086 | GEM_BUG_ON(debug_locks && |
1087 | !!lockdep_is_held(&req->i915->drm.struct_mutex) != | |
22dd3bb9 CW |
1088 | !!(flags & I915_WAIT_LOCKED)); |
1089 | #endif | |
e95433c7 | 1090 | GEM_BUG_ON(timeout < 0); |
05235c53 | 1091 | |
05235c53 | 1092 | if (i915_gem_request_completed(req)) |
e95433c7 | 1093 | return timeout; |
05235c53 | 1094 | |
e95433c7 CW |
1095 | if (!timeout) |
1096 | return -ETIME; | |
05235c53 | 1097 | |
93692502 | 1098 | trace_i915_gem_request_wait_begin(req, flags); |
05235c53 | 1099 | |
23902e49 CW |
1100 | if (!i915_sw_fence_done(&req->execute)) { |
1101 | timeout = __i915_request_wait_for_execute(req, flags, timeout); | |
4680816b CW |
1102 | if (timeout < 0) |
1103 | goto complete; | |
1104 | ||
23902e49 | 1105 | GEM_BUG_ON(!i915_sw_fence_done(&req->execute)); |
4680816b | 1106 | } |
23902e49 | 1107 | GEM_BUG_ON(!i915_sw_fence_done(&req->submit)); |
65e4760e | 1108 | GEM_BUG_ON(!req->global_seqno); |
4680816b | 1109 | |
437c3087 | 1110 | /* Optimistic short spin before touching IRQs */ |
05235c53 CW |
1111 | if (i915_spin_request(req, state, 5)) |
1112 | goto complete; | |
1113 | ||
1114 | set_current_state(state); | |
22dd3bb9 | 1115 | if (flags & I915_WAIT_LOCKED) |
4b36b2e5 | 1116 | add_wait_queue(errq, &reset); |
05235c53 | 1117 | |
65e4760e | 1118 | intel_wait_init(&wait, req->global_seqno); |
05235c53 CW |
1119 | if (intel_engine_add_wait(req->engine, &wait)) |
1120 | /* In order to check that we haven't missed the interrupt | |
1121 | * as we enabled it, we need to kick ourselves to do a | |
1122 | * coherent check on the seqno before we sleep. | |
1123 | */ | |
1124 | goto wakeup; | |
1125 | ||
1126 | for (;;) { | |
1127 | if (signal_pending_state(state, current)) { | |
e95433c7 | 1128 | timeout = -ERESTARTSYS; |
05235c53 CW |
1129 | break; |
1130 | } | |
1131 | ||
e95433c7 CW |
1132 | if (!timeout) { |
1133 | timeout = -ETIME; | |
05235c53 CW |
1134 | break; |
1135 | } | |
1136 | ||
e95433c7 CW |
1137 | timeout = io_schedule_timeout(timeout); |
1138 | ||
05235c53 CW |
1139 | if (intel_wait_complete(&wait)) |
1140 | break; | |
1141 | ||
1142 | set_current_state(state); | |
1143 | ||
1144 | wakeup: | |
1145 | /* Carefully check if the request is complete, giving time | |
1146 | * for the seqno to be visible following the interrupt. | |
1147 | * We also have to check in case we are kicked by the GPU | |
1148 | * reset in order to drop the struct_mutex. | |
1149 | */ | |
1150 | if (__i915_request_irq_complete(req)) | |
1151 | break; | |
1152 | ||
221fe799 CW |
1153 | /* If the GPU is hung, and we hold the lock, reset the GPU |
1154 | * and then check for completion. On a full reset, the engine's | |
1155 | * HW seqno will be advanced passed us and we are complete. | |
1156 | * If we do a partial reset, we have to wait for the GPU to | |
1157 | * resume and update the breadcrumb. | |
1158 | * | |
1159 | * If we don't hold the mutex, we can just wait for the worker | |
1160 | * to come along and update the breadcrumb (either directly | |
1161 | * itself, or indirectly by recovering the GPU). | |
1162 | */ | |
1163 | if (flags & I915_WAIT_LOCKED && | |
1164 | i915_reset_in_progress(&req->i915->gpu_error)) { | |
1165 | __set_current_state(TASK_RUNNING); | |
1166 | i915_reset(req->i915); | |
4b36b2e5 | 1167 | reset_wait_queue(errq, &reset); |
221fe799 CW |
1168 | continue; |
1169 | } | |
1170 | ||
05235c53 CW |
1171 | /* Only spin if we know the GPU is processing this request */ |
1172 | if (i915_spin_request(req, state, 2)) | |
1173 | break; | |
1174 | } | |
05235c53 CW |
1175 | |
1176 | intel_engine_remove_wait(req->engine, &wait); | |
22dd3bb9 | 1177 | if (flags & I915_WAIT_LOCKED) |
4b36b2e5 | 1178 | remove_wait_queue(errq, &reset); |
05235c53 | 1179 | __set_current_state(TASK_RUNNING); |
22dd3bb9 | 1180 | |
05235c53 CW |
1181 | complete: |
1182 | trace_i915_gem_request_wait_end(req); | |
1183 | ||
e95433c7 | 1184 | return timeout; |
05235c53 | 1185 | } |
4b8de8e6 | 1186 | |
28176ef4 | 1187 | static void engine_retire_requests(struct intel_engine_cs *engine) |
4b8de8e6 CW |
1188 | { |
1189 | struct drm_i915_gem_request *request, *next; | |
1190 | ||
73cb9701 CW |
1191 | list_for_each_entry_safe(request, next, |
1192 | &engine->timeline->requests, link) { | |
80b204bc | 1193 | if (!__i915_gem_request_completed(request)) |
28176ef4 | 1194 | return; |
4b8de8e6 CW |
1195 | |
1196 | i915_gem_request_retire(request); | |
1197 | } | |
1198 | } | |
1199 | ||
1200 | void i915_gem_retire_requests(struct drm_i915_private *dev_priv) | |
1201 | { | |
1202 | struct intel_engine_cs *engine; | |
28176ef4 | 1203 | enum intel_engine_id id; |
4b8de8e6 CW |
1204 | |
1205 | lockdep_assert_held(&dev_priv->drm.struct_mutex); | |
1206 | ||
28176ef4 | 1207 | if (!dev_priv->gt.active_requests) |
4b8de8e6 CW |
1208 | return; |
1209 | ||
28176ef4 CW |
1210 | for_each_engine(engine, dev_priv, id) |
1211 | engine_retire_requests(engine); | |
4b8de8e6 | 1212 | } |
c835c550 CW |
1213 | |
1214 | #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST) | |
1215 | #include "selftests/mock_request.c" | |
1216 | #include "selftests/i915_gem_request.c" | |
1217 | #endif |