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0d6aa60b | 1 | /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*- |
1da177e4 | 2 | */ |
0d6aa60b | 3 | /* |
1da177e4 LT |
4 | * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. |
5 | * All Rights Reserved. | |
bc54fd1a DA |
6 | * |
7 | * Permission is hereby granted, free of charge, to any person obtaining a | |
8 | * copy of this software and associated documentation files (the | |
9 | * "Software"), to deal in the Software without restriction, including | |
10 | * without limitation the rights to use, copy, modify, merge, publish, | |
11 | * distribute, sub license, and/or sell copies of the Software, and to | |
12 | * permit persons to whom the Software is furnished to do so, subject to | |
13 | * the following conditions: | |
14 | * | |
15 | * The above copyright notice and this permission notice (including the | |
16 | * next paragraph) shall be included in all copies or substantial portions | |
17 | * of the Software. | |
18 | * | |
19 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS | |
20 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
21 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. | |
22 | * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR | |
23 | * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, | |
24 | * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE | |
25 | * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. | |
26 | * | |
0d6aa60b | 27 | */ |
1da177e4 | 28 | |
a70491cc JP |
29 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
30 | ||
63eeaf38 | 31 | #include <linux/sysrq.h> |
5a0e3ad6 | 32 | #include <linux/slab.h> |
b2c88f5b | 33 | #include <linux/circ_buf.h> |
760285e7 DH |
34 | #include <drm/drmP.h> |
35 | #include <drm/i915_drm.h> | |
1da177e4 | 36 | #include "i915_drv.h" |
1c5d22f7 | 37 | #include "i915_trace.h" |
79e53945 | 38 | #include "intel_drv.h" |
1da177e4 | 39 | |
fca52a55 DV |
40 | /** |
41 | * DOC: interrupt handling | |
42 | * | |
43 | * These functions provide the basic support for enabling and disabling the | |
44 | * interrupt handling support. There's a lot more functionality in i915_irq.c | |
45 | * and related files, but that will be described in separate chapters. | |
46 | */ | |
47 | ||
e4ce95aa VS |
48 | static const u32 hpd_ilk[HPD_NUM_PINS] = { |
49 | [HPD_PORT_A] = DE_DP_A_HOTPLUG, | |
50 | }; | |
51 | ||
23bb4cb5 VS |
52 | static const u32 hpd_ivb[HPD_NUM_PINS] = { |
53 | [HPD_PORT_A] = DE_DP_A_HOTPLUG_IVB, | |
54 | }; | |
55 | ||
3a3b3c7d VS |
56 | static const u32 hpd_bdw[HPD_NUM_PINS] = { |
57 | [HPD_PORT_A] = GEN8_PORT_DP_A_HOTPLUG, | |
58 | }; | |
59 | ||
7c7e10db | 60 | static const u32 hpd_ibx[HPD_NUM_PINS] = { |
e5868a31 EE |
61 | [HPD_CRT] = SDE_CRT_HOTPLUG, |
62 | [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG, | |
63 | [HPD_PORT_B] = SDE_PORTB_HOTPLUG, | |
64 | [HPD_PORT_C] = SDE_PORTC_HOTPLUG, | |
65 | [HPD_PORT_D] = SDE_PORTD_HOTPLUG | |
66 | }; | |
67 | ||
7c7e10db | 68 | static const u32 hpd_cpt[HPD_NUM_PINS] = { |
e5868a31 | 69 | [HPD_CRT] = SDE_CRT_HOTPLUG_CPT, |
73c352a2 | 70 | [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG_CPT, |
e5868a31 EE |
71 | [HPD_PORT_B] = SDE_PORTB_HOTPLUG_CPT, |
72 | [HPD_PORT_C] = SDE_PORTC_HOTPLUG_CPT, | |
73 | [HPD_PORT_D] = SDE_PORTD_HOTPLUG_CPT | |
74 | }; | |
75 | ||
26951caf | 76 | static const u32 hpd_spt[HPD_NUM_PINS] = { |
74c0b395 | 77 | [HPD_PORT_A] = SDE_PORTA_HOTPLUG_SPT, |
26951caf XZ |
78 | [HPD_PORT_B] = SDE_PORTB_HOTPLUG_CPT, |
79 | [HPD_PORT_C] = SDE_PORTC_HOTPLUG_CPT, | |
80 | [HPD_PORT_D] = SDE_PORTD_HOTPLUG_CPT, | |
81 | [HPD_PORT_E] = SDE_PORTE_HOTPLUG_SPT | |
82 | }; | |
83 | ||
7c7e10db | 84 | static const u32 hpd_mask_i915[HPD_NUM_PINS] = { |
e5868a31 EE |
85 | [HPD_CRT] = CRT_HOTPLUG_INT_EN, |
86 | [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_EN, | |
87 | [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_EN, | |
88 | [HPD_PORT_B] = PORTB_HOTPLUG_INT_EN, | |
89 | [HPD_PORT_C] = PORTC_HOTPLUG_INT_EN, | |
90 | [HPD_PORT_D] = PORTD_HOTPLUG_INT_EN | |
91 | }; | |
92 | ||
7c7e10db | 93 | static const u32 hpd_status_g4x[HPD_NUM_PINS] = { |
e5868a31 EE |
94 | [HPD_CRT] = CRT_HOTPLUG_INT_STATUS, |
95 | [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_G4X, | |
96 | [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_G4X, | |
97 | [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS, | |
98 | [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS, | |
99 | [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS | |
100 | }; | |
101 | ||
4bca26d0 | 102 | static const u32 hpd_status_i915[HPD_NUM_PINS] = { |
e5868a31 EE |
103 | [HPD_CRT] = CRT_HOTPLUG_INT_STATUS, |
104 | [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_I915, | |
105 | [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_I915, | |
106 | [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS, | |
107 | [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS, | |
108 | [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS | |
109 | }; | |
110 | ||
e0a20ad7 SS |
111 | /* BXT hpd list */ |
112 | static const u32 hpd_bxt[HPD_NUM_PINS] = { | |
7f3561be | 113 | [HPD_PORT_A] = BXT_DE_PORT_HP_DDIA, |
e0a20ad7 SS |
114 | [HPD_PORT_B] = BXT_DE_PORT_HP_DDIB, |
115 | [HPD_PORT_C] = BXT_DE_PORT_HP_DDIC | |
116 | }; | |
117 | ||
5c502442 | 118 | /* IIR can theoretically queue up two events. Be paranoid. */ |
f86f3fb0 | 119 | #define GEN8_IRQ_RESET_NDX(type, which) do { \ |
5c502442 PZ |
120 | I915_WRITE(GEN8_##type##_IMR(which), 0xffffffff); \ |
121 | POSTING_READ(GEN8_##type##_IMR(which)); \ | |
122 | I915_WRITE(GEN8_##type##_IER(which), 0); \ | |
123 | I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \ | |
124 | POSTING_READ(GEN8_##type##_IIR(which)); \ | |
125 | I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \ | |
126 | POSTING_READ(GEN8_##type##_IIR(which)); \ | |
127 | } while (0) | |
128 | ||
f86f3fb0 | 129 | #define GEN5_IRQ_RESET(type) do { \ |
a9d356a6 | 130 | I915_WRITE(type##IMR, 0xffffffff); \ |
5c502442 | 131 | POSTING_READ(type##IMR); \ |
a9d356a6 | 132 | I915_WRITE(type##IER, 0); \ |
5c502442 PZ |
133 | I915_WRITE(type##IIR, 0xffffffff); \ |
134 | POSTING_READ(type##IIR); \ | |
135 | I915_WRITE(type##IIR, 0xffffffff); \ | |
136 | POSTING_READ(type##IIR); \ | |
a9d356a6 PZ |
137 | } while (0) |
138 | ||
337ba017 PZ |
139 | /* |
140 | * We should clear IMR at preinstall/uninstall, and just check at postinstall. | |
141 | */ | |
f0f59a00 VS |
142 | static void gen5_assert_iir_is_zero(struct drm_i915_private *dev_priv, |
143 | i915_reg_t reg) | |
b51a2842 VS |
144 | { |
145 | u32 val = I915_READ(reg); | |
146 | ||
147 | if (val == 0) | |
148 | return; | |
149 | ||
150 | WARN(1, "Interrupt register 0x%x is not zero: 0x%08x\n", | |
f0f59a00 | 151 | i915_mmio_reg_offset(reg), val); |
b51a2842 VS |
152 | I915_WRITE(reg, 0xffffffff); |
153 | POSTING_READ(reg); | |
154 | I915_WRITE(reg, 0xffffffff); | |
155 | POSTING_READ(reg); | |
156 | } | |
337ba017 | 157 | |
35079899 | 158 | #define GEN8_IRQ_INIT_NDX(type, which, imr_val, ier_val) do { \ |
b51a2842 | 159 | gen5_assert_iir_is_zero(dev_priv, GEN8_##type##_IIR(which)); \ |
35079899 | 160 | I915_WRITE(GEN8_##type##_IER(which), (ier_val)); \ |
7d1bd539 VS |
161 | I915_WRITE(GEN8_##type##_IMR(which), (imr_val)); \ |
162 | POSTING_READ(GEN8_##type##_IMR(which)); \ | |
35079899 PZ |
163 | } while (0) |
164 | ||
165 | #define GEN5_IRQ_INIT(type, imr_val, ier_val) do { \ | |
b51a2842 | 166 | gen5_assert_iir_is_zero(dev_priv, type##IIR); \ |
35079899 | 167 | I915_WRITE(type##IER, (ier_val)); \ |
7d1bd539 VS |
168 | I915_WRITE(type##IMR, (imr_val)); \ |
169 | POSTING_READ(type##IMR); \ | |
35079899 PZ |
170 | } while (0) |
171 | ||
c9a9a268 | 172 | static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir); |
26705e20 | 173 | static void gen9_guc_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir); |
c9a9a268 | 174 | |
0706f17c EE |
175 | /* For display hotplug interrupt */ |
176 | static inline void | |
177 | i915_hotplug_interrupt_update_locked(struct drm_i915_private *dev_priv, | |
178 | uint32_t mask, | |
179 | uint32_t bits) | |
180 | { | |
181 | uint32_t val; | |
182 | ||
67520415 | 183 | lockdep_assert_held(&dev_priv->irq_lock); |
0706f17c EE |
184 | WARN_ON(bits & ~mask); |
185 | ||
186 | val = I915_READ(PORT_HOTPLUG_EN); | |
187 | val &= ~mask; | |
188 | val |= bits; | |
189 | I915_WRITE(PORT_HOTPLUG_EN, val); | |
190 | } | |
191 | ||
192 | /** | |
193 | * i915_hotplug_interrupt_update - update hotplug interrupt enable | |
194 | * @dev_priv: driver private | |
195 | * @mask: bits to update | |
196 | * @bits: bits to enable | |
197 | * NOTE: the HPD enable bits are modified both inside and outside | |
198 | * of an interrupt context. To avoid that read-modify-write cycles | |
199 | * interfer, these bits are protected by a spinlock. Since this | |
200 | * function is usually not called from a context where the lock is | |
201 | * held already, this function acquires the lock itself. A non-locking | |
202 | * version is also available. | |
203 | */ | |
204 | void i915_hotplug_interrupt_update(struct drm_i915_private *dev_priv, | |
205 | uint32_t mask, | |
206 | uint32_t bits) | |
207 | { | |
208 | spin_lock_irq(&dev_priv->irq_lock); | |
209 | i915_hotplug_interrupt_update_locked(dev_priv, mask, bits); | |
210 | spin_unlock_irq(&dev_priv->irq_lock); | |
211 | } | |
212 | ||
d9dc34f1 VS |
213 | /** |
214 | * ilk_update_display_irq - update DEIMR | |
215 | * @dev_priv: driver private | |
216 | * @interrupt_mask: mask of interrupt bits to update | |
217 | * @enabled_irq_mask: mask of interrupt bits to enable | |
218 | */ | |
fbdedaea VS |
219 | void ilk_update_display_irq(struct drm_i915_private *dev_priv, |
220 | uint32_t interrupt_mask, | |
221 | uint32_t enabled_irq_mask) | |
036a4a7d | 222 | { |
d9dc34f1 VS |
223 | uint32_t new_val; |
224 | ||
67520415 | 225 | lockdep_assert_held(&dev_priv->irq_lock); |
4bc9d430 | 226 | |
d9dc34f1 VS |
227 | WARN_ON(enabled_irq_mask & ~interrupt_mask); |
228 | ||
9df7575f | 229 | if (WARN_ON(!intel_irqs_enabled(dev_priv))) |
c67a470b | 230 | return; |
c67a470b | 231 | |
d9dc34f1 VS |
232 | new_val = dev_priv->irq_mask; |
233 | new_val &= ~interrupt_mask; | |
234 | new_val |= (~enabled_irq_mask & interrupt_mask); | |
235 | ||
236 | if (new_val != dev_priv->irq_mask) { | |
237 | dev_priv->irq_mask = new_val; | |
1ec14ad3 | 238 | I915_WRITE(DEIMR, dev_priv->irq_mask); |
3143a2bf | 239 | POSTING_READ(DEIMR); |
036a4a7d ZW |
240 | } |
241 | } | |
242 | ||
43eaea13 PZ |
243 | /** |
244 | * ilk_update_gt_irq - update GTIMR | |
245 | * @dev_priv: driver private | |
246 | * @interrupt_mask: mask of interrupt bits to update | |
247 | * @enabled_irq_mask: mask of interrupt bits to enable | |
248 | */ | |
249 | static void ilk_update_gt_irq(struct drm_i915_private *dev_priv, | |
250 | uint32_t interrupt_mask, | |
251 | uint32_t enabled_irq_mask) | |
252 | { | |
67520415 | 253 | lockdep_assert_held(&dev_priv->irq_lock); |
43eaea13 | 254 | |
15a17aae DV |
255 | WARN_ON(enabled_irq_mask & ~interrupt_mask); |
256 | ||
9df7575f | 257 | if (WARN_ON(!intel_irqs_enabled(dev_priv))) |
c67a470b | 258 | return; |
c67a470b | 259 | |
43eaea13 PZ |
260 | dev_priv->gt_irq_mask &= ~interrupt_mask; |
261 | dev_priv->gt_irq_mask |= (~enabled_irq_mask & interrupt_mask); | |
262 | I915_WRITE(GTIMR, dev_priv->gt_irq_mask); | |
43eaea13 PZ |
263 | } |
264 | ||
480c8033 | 265 | void gen5_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask) |
43eaea13 PZ |
266 | { |
267 | ilk_update_gt_irq(dev_priv, mask, mask); | |
31bb59cc | 268 | POSTING_READ_FW(GTIMR); |
43eaea13 PZ |
269 | } |
270 | ||
480c8033 | 271 | void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask) |
43eaea13 PZ |
272 | { |
273 | ilk_update_gt_irq(dev_priv, mask, 0); | |
274 | } | |
275 | ||
f0f59a00 | 276 | static i915_reg_t gen6_pm_iir(struct drm_i915_private *dev_priv) |
b900b949 ID |
277 | { |
278 | return INTEL_INFO(dev_priv)->gen >= 8 ? GEN8_GT_IIR(2) : GEN6_PMIIR; | |
279 | } | |
280 | ||
f0f59a00 | 281 | static i915_reg_t gen6_pm_imr(struct drm_i915_private *dev_priv) |
a72fbc3a ID |
282 | { |
283 | return INTEL_INFO(dev_priv)->gen >= 8 ? GEN8_GT_IMR(2) : GEN6_PMIMR; | |
284 | } | |
285 | ||
f0f59a00 | 286 | static i915_reg_t gen6_pm_ier(struct drm_i915_private *dev_priv) |
b900b949 ID |
287 | { |
288 | return INTEL_INFO(dev_priv)->gen >= 8 ? GEN8_GT_IER(2) : GEN6_PMIER; | |
289 | } | |
290 | ||
edbfdb45 | 291 | /** |
81fd874e VS |
292 | * snb_update_pm_irq - update GEN6_PMIMR |
293 | * @dev_priv: driver private | |
294 | * @interrupt_mask: mask of interrupt bits to update | |
295 | * @enabled_irq_mask: mask of interrupt bits to enable | |
296 | */ | |
edbfdb45 PZ |
297 | static void snb_update_pm_irq(struct drm_i915_private *dev_priv, |
298 | uint32_t interrupt_mask, | |
299 | uint32_t enabled_irq_mask) | |
300 | { | |
605cd25b | 301 | uint32_t new_val; |
edbfdb45 | 302 | |
15a17aae DV |
303 | WARN_ON(enabled_irq_mask & ~interrupt_mask); |
304 | ||
67520415 | 305 | lockdep_assert_held(&dev_priv->irq_lock); |
edbfdb45 | 306 | |
f4e9af4f | 307 | new_val = dev_priv->pm_imr; |
f52ecbcf PZ |
308 | new_val &= ~interrupt_mask; |
309 | new_val |= (~enabled_irq_mask & interrupt_mask); | |
310 | ||
f4e9af4f AG |
311 | if (new_val != dev_priv->pm_imr) { |
312 | dev_priv->pm_imr = new_val; | |
313 | I915_WRITE(gen6_pm_imr(dev_priv), dev_priv->pm_imr); | |
a72fbc3a | 314 | POSTING_READ(gen6_pm_imr(dev_priv)); |
f52ecbcf | 315 | } |
edbfdb45 PZ |
316 | } |
317 | ||
f4e9af4f | 318 | void gen6_unmask_pm_irq(struct drm_i915_private *dev_priv, u32 mask) |
edbfdb45 | 319 | { |
9939fba2 ID |
320 | if (WARN_ON(!intel_irqs_enabled(dev_priv))) |
321 | return; | |
322 | ||
edbfdb45 PZ |
323 | snb_update_pm_irq(dev_priv, mask, mask); |
324 | } | |
325 | ||
f4e9af4f | 326 | static void __gen6_mask_pm_irq(struct drm_i915_private *dev_priv, u32 mask) |
edbfdb45 PZ |
327 | { |
328 | snb_update_pm_irq(dev_priv, mask, 0); | |
329 | } | |
330 | ||
f4e9af4f | 331 | void gen6_mask_pm_irq(struct drm_i915_private *dev_priv, u32 mask) |
9939fba2 ID |
332 | { |
333 | if (WARN_ON(!intel_irqs_enabled(dev_priv))) | |
334 | return; | |
335 | ||
f4e9af4f | 336 | __gen6_mask_pm_irq(dev_priv, mask); |
9939fba2 ID |
337 | } |
338 | ||
f4e9af4f | 339 | void gen6_reset_pm_iir(struct drm_i915_private *dev_priv, u32 reset_mask) |
3cc134e3 | 340 | { |
f0f59a00 | 341 | i915_reg_t reg = gen6_pm_iir(dev_priv); |
3cc134e3 | 342 | |
67520415 | 343 | lockdep_assert_held(&dev_priv->irq_lock); |
f4e9af4f AG |
344 | |
345 | I915_WRITE(reg, reset_mask); | |
346 | I915_WRITE(reg, reset_mask); | |
3cc134e3 | 347 | POSTING_READ(reg); |
f4e9af4f AG |
348 | } |
349 | ||
350 | void gen6_enable_pm_irq(struct drm_i915_private *dev_priv, u32 enable_mask) | |
351 | { | |
67520415 | 352 | lockdep_assert_held(&dev_priv->irq_lock); |
f4e9af4f AG |
353 | |
354 | dev_priv->pm_ier |= enable_mask; | |
355 | I915_WRITE(gen6_pm_ier(dev_priv), dev_priv->pm_ier); | |
356 | gen6_unmask_pm_irq(dev_priv, enable_mask); | |
357 | /* unmask_pm_irq provides an implicit barrier (POSTING_READ) */ | |
358 | } | |
359 | ||
360 | void gen6_disable_pm_irq(struct drm_i915_private *dev_priv, u32 disable_mask) | |
361 | { | |
67520415 | 362 | lockdep_assert_held(&dev_priv->irq_lock); |
f4e9af4f AG |
363 | |
364 | dev_priv->pm_ier &= ~disable_mask; | |
365 | __gen6_mask_pm_irq(dev_priv, disable_mask); | |
366 | I915_WRITE(gen6_pm_ier(dev_priv), dev_priv->pm_ier); | |
367 | /* though a barrier is missing here, but don't really need a one */ | |
368 | } | |
369 | ||
370 | void gen6_reset_rps_interrupts(struct drm_i915_private *dev_priv) | |
371 | { | |
372 | spin_lock_irq(&dev_priv->irq_lock); | |
373 | gen6_reset_pm_iir(dev_priv, dev_priv->pm_rps_events); | |
096fad9e | 374 | dev_priv->rps.pm_iir = 0; |
3cc134e3 ID |
375 | spin_unlock_irq(&dev_priv->irq_lock); |
376 | } | |
377 | ||
91d14251 | 378 | void gen6_enable_rps_interrupts(struct drm_i915_private *dev_priv) |
b900b949 | 379 | { |
f2a91d1a CW |
380 | if (READ_ONCE(dev_priv->rps.interrupts_enabled)) |
381 | return; | |
382 | ||
b900b949 | 383 | spin_lock_irq(&dev_priv->irq_lock); |
c33d247d CW |
384 | WARN_ON_ONCE(dev_priv->rps.pm_iir); |
385 | WARN_ON_ONCE(I915_READ(gen6_pm_iir(dev_priv)) & dev_priv->pm_rps_events); | |
d4d70aa5 | 386 | dev_priv->rps.interrupts_enabled = true; |
b900b949 | 387 | gen6_enable_pm_irq(dev_priv, dev_priv->pm_rps_events); |
78e68d36 | 388 | |
b900b949 ID |
389 | spin_unlock_irq(&dev_priv->irq_lock); |
390 | } | |
391 | ||
91d14251 | 392 | void gen6_disable_rps_interrupts(struct drm_i915_private *dev_priv) |
b900b949 | 393 | { |
f2a91d1a CW |
394 | if (!READ_ONCE(dev_priv->rps.interrupts_enabled)) |
395 | return; | |
396 | ||
d4d70aa5 ID |
397 | spin_lock_irq(&dev_priv->irq_lock); |
398 | dev_priv->rps.interrupts_enabled = false; | |
9939fba2 | 399 | |
b20e3cfe | 400 | I915_WRITE(GEN6_PMINTRMSK, gen6_sanitize_rps_pm_mask(dev_priv, ~0u)); |
9939fba2 | 401 | |
f4e9af4f | 402 | gen6_disable_pm_irq(dev_priv, dev_priv->pm_rps_events); |
58072ccb ID |
403 | |
404 | spin_unlock_irq(&dev_priv->irq_lock); | |
91c8a326 | 405 | synchronize_irq(dev_priv->drm.irq); |
c33d247d CW |
406 | |
407 | /* Now that we will not be generating any more work, flush any | |
408 | * outsanding tasks. As we are called on the RPS idle path, | |
409 | * we will reset the GPU to minimum frequencies, so the current | |
410 | * state of the worker can be discarded. | |
411 | */ | |
412 | cancel_work_sync(&dev_priv->rps.work); | |
413 | gen6_reset_rps_interrupts(dev_priv); | |
b900b949 ID |
414 | } |
415 | ||
26705e20 SAK |
416 | void gen9_reset_guc_interrupts(struct drm_i915_private *dev_priv) |
417 | { | |
418 | spin_lock_irq(&dev_priv->irq_lock); | |
419 | gen6_reset_pm_iir(dev_priv, dev_priv->pm_guc_events); | |
420 | spin_unlock_irq(&dev_priv->irq_lock); | |
421 | } | |
422 | ||
423 | void gen9_enable_guc_interrupts(struct drm_i915_private *dev_priv) | |
424 | { | |
425 | spin_lock_irq(&dev_priv->irq_lock); | |
426 | if (!dev_priv->guc.interrupts_enabled) { | |
427 | WARN_ON_ONCE(I915_READ(gen6_pm_iir(dev_priv)) & | |
428 | dev_priv->pm_guc_events); | |
429 | dev_priv->guc.interrupts_enabled = true; | |
430 | gen6_enable_pm_irq(dev_priv, dev_priv->pm_guc_events); | |
431 | } | |
432 | spin_unlock_irq(&dev_priv->irq_lock); | |
433 | } | |
434 | ||
435 | void gen9_disable_guc_interrupts(struct drm_i915_private *dev_priv) | |
436 | { | |
437 | spin_lock_irq(&dev_priv->irq_lock); | |
438 | dev_priv->guc.interrupts_enabled = false; | |
439 | ||
440 | gen6_disable_pm_irq(dev_priv, dev_priv->pm_guc_events); | |
441 | ||
442 | spin_unlock_irq(&dev_priv->irq_lock); | |
443 | synchronize_irq(dev_priv->drm.irq); | |
444 | ||
445 | gen9_reset_guc_interrupts(dev_priv); | |
446 | } | |
447 | ||
3a3b3c7d | 448 | /** |
81fd874e VS |
449 | * bdw_update_port_irq - update DE port interrupt |
450 | * @dev_priv: driver private | |
451 | * @interrupt_mask: mask of interrupt bits to update | |
452 | * @enabled_irq_mask: mask of interrupt bits to enable | |
453 | */ | |
3a3b3c7d VS |
454 | static void bdw_update_port_irq(struct drm_i915_private *dev_priv, |
455 | uint32_t interrupt_mask, | |
456 | uint32_t enabled_irq_mask) | |
457 | { | |
458 | uint32_t new_val; | |
459 | uint32_t old_val; | |
460 | ||
67520415 | 461 | lockdep_assert_held(&dev_priv->irq_lock); |
3a3b3c7d VS |
462 | |
463 | WARN_ON(enabled_irq_mask & ~interrupt_mask); | |
464 | ||
465 | if (WARN_ON(!intel_irqs_enabled(dev_priv))) | |
466 | return; | |
467 | ||
468 | old_val = I915_READ(GEN8_DE_PORT_IMR); | |
469 | ||
470 | new_val = old_val; | |
471 | new_val &= ~interrupt_mask; | |
472 | new_val |= (~enabled_irq_mask & interrupt_mask); | |
473 | ||
474 | if (new_val != old_val) { | |
475 | I915_WRITE(GEN8_DE_PORT_IMR, new_val); | |
476 | POSTING_READ(GEN8_DE_PORT_IMR); | |
477 | } | |
478 | } | |
479 | ||
013d3752 VS |
480 | /** |
481 | * bdw_update_pipe_irq - update DE pipe interrupt | |
482 | * @dev_priv: driver private | |
483 | * @pipe: pipe whose interrupt to update | |
484 | * @interrupt_mask: mask of interrupt bits to update | |
485 | * @enabled_irq_mask: mask of interrupt bits to enable | |
486 | */ | |
487 | void bdw_update_pipe_irq(struct drm_i915_private *dev_priv, | |
488 | enum pipe pipe, | |
489 | uint32_t interrupt_mask, | |
490 | uint32_t enabled_irq_mask) | |
491 | { | |
492 | uint32_t new_val; | |
493 | ||
67520415 | 494 | lockdep_assert_held(&dev_priv->irq_lock); |
013d3752 VS |
495 | |
496 | WARN_ON(enabled_irq_mask & ~interrupt_mask); | |
497 | ||
498 | if (WARN_ON(!intel_irqs_enabled(dev_priv))) | |
499 | return; | |
500 | ||
501 | new_val = dev_priv->de_irq_mask[pipe]; | |
502 | new_val &= ~interrupt_mask; | |
503 | new_val |= (~enabled_irq_mask & interrupt_mask); | |
504 | ||
505 | if (new_val != dev_priv->de_irq_mask[pipe]) { | |
506 | dev_priv->de_irq_mask[pipe] = new_val; | |
507 | I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]); | |
508 | POSTING_READ(GEN8_DE_PIPE_IMR(pipe)); | |
509 | } | |
510 | } | |
511 | ||
fee884ed DV |
512 | /** |
513 | * ibx_display_interrupt_update - update SDEIMR | |
514 | * @dev_priv: driver private | |
515 | * @interrupt_mask: mask of interrupt bits to update | |
516 | * @enabled_irq_mask: mask of interrupt bits to enable | |
517 | */ | |
47339cd9 DV |
518 | void ibx_display_interrupt_update(struct drm_i915_private *dev_priv, |
519 | uint32_t interrupt_mask, | |
520 | uint32_t enabled_irq_mask) | |
fee884ed DV |
521 | { |
522 | uint32_t sdeimr = I915_READ(SDEIMR); | |
523 | sdeimr &= ~interrupt_mask; | |
524 | sdeimr |= (~enabled_irq_mask & interrupt_mask); | |
525 | ||
15a17aae DV |
526 | WARN_ON(enabled_irq_mask & ~interrupt_mask); |
527 | ||
67520415 | 528 | lockdep_assert_held(&dev_priv->irq_lock); |
fee884ed | 529 | |
9df7575f | 530 | if (WARN_ON(!intel_irqs_enabled(dev_priv))) |
c67a470b | 531 | return; |
c67a470b | 532 | |
fee884ed DV |
533 | I915_WRITE(SDEIMR, sdeimr); |
534 | POSTING_READ(SDEIMR); | |
535 | } | |
8664281b | 536 | |
b5ea642a | 537 | static void |
755e9019 ID |
538 | __i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe, |
539 | u32 enable_mask, u32 status_mask) | |
7c463586 | 540 | { |
f0f59a00 | 541 | i915_reg_t reg = PIPESTAT(pipe); |
755e9019 | 542 | u32 pipestat = I915_READ(reg) & PIPESTAT_INT_ENABLE_MASK; |
7c463586 | 543 | |
67520415 | 544 | lockdep_assert_held(&dev_priv->irq_lock); |
d518ce50 | 545 | WARN_ON(!intel_irqs_enabled(dev_priv)); |
b79480ba | 546 | |
04feced9 VS |
547 | if (WARN_ONCE(enable_mask & ~PIPESTAT_INT_ENABLE_MASK || |
548 | status_mask & ~PIPESTAT_INT_STATUS_MASK, | |
549 | "pipe %c: enable_mask=0x%x, status_mask=0x%x\n", | |
550 | pipe_name(pipe), enable_mask, status_mask)) | |
755e9019 ID |
551 | return; |
552 | ||
553 | if ((pipestat & enable_mask) == enable_mask) | |
46c06a30 VS |
554 | return; |
555 | ||
91d181dd ID |
556 | dev_priv->pipestat_irq_mask[pipe] |= status_mask; |
557 | ||
46c06a30 | 558 | /* Enable the interrupt, clear any pending status */ |
755e9019 | 559 | pipestat |= enable_mask | status_mask; |
46c06a30 VS |
560 | I915_WRITE(reg, pipestat); |
561 | POSTING_READ(reg); | |
7c463586 KP |
562 | } |
563 | ||
b5ea642a | 564 | static void |
755e9019 ID |
565 | __i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe, |
566 | u32 enable_mask, u32 status_mask) | |
7c463586 | 567 | { |
f0f59a00 | 568 | i915_reg_t reg = PIPESTAT(pipe); |
755e9019 | 569 | u32 pipestat = I915_READ(reg) & PIPESTAT_INT_ENABLE_MASK; |
7c463586 | 570 | |
67520415 | 571 | lockdep_assert_held(&dev_priv->irq_lock); |
d518ce50 | 572 | WARN_ON(!intel_irqs_enabled(dev_priv)); |
b79480ba | 573 | |
04feced9 VS |
574 | if (WARN_ONCE(enable_mask & ~PIPESTAT_INT_ENABLE_MASK || |
575 | status_mask & ~PIPESTAT_INT_STATUS_MASK, | |
576 | "pipe %c: enable_mask=0x%x, status_mask=0x%x\n", | |
577 | pipe_name(pipe), enable_mask, status_mask)) | |
46c06a30 VS |
578 | return; |
579 | ||
755e9019 ID |
580 | if ((pipestat & enable_mask) == 0) |
581 | return; | |
582 | ||
91d181dd ID |
583 | dev_priv->pipestat_irq_mask[pipe] &= ~status_mask; |
584 | ||
755e9019 | 585 | pipestat &= ~enable_mask; |
46c06a30 VS |
586 | I915_WRITE(reg, pipestat); |
587 | POSTING_READ(reg); | |
7c463586 KP |
588 | } |
589 | ||
10c59c51 ID |
590 | static u32 vlv_get_pipestat_enable_mask(struct drm_device *dev, u32 status_mask) |
591 | { | |
592 | u32 enable_mask = status_mask << 16; | |
593 | ||
594 | /* | |
724a6905 VS |
595 | * On pipe A we don't support the PSR interrupt yet, |
596 | * on pipe B and C the same bit MBZ. | |
10c59c51 ID |
597 | */ |
598 | if (WARN_ON_ONCE(status_mask & PIPE_A_PSR_STATUS_VLV)) | |
599 | return 0; | |
724a6905 VS |
600 | /* |
601 | * On pipe B and C we don't support the PSR interrupt yet, on pipe | |
602 | * A the same bit is for perf counters which we don't use either. | |
603 | */ | |
604 | if (WARN_ON_ONCE(status_mask & PIPE_B_PSR_STATUS_VLV)) | |
605 | return 0; | |
10c59c51 ID |
606 | |
607 | enable_mask &= ~(PIPE_FIFO_UNDERRUN_STATUS | | |
608 | SPRITE0_FLIP_DONE_INT_EN_VLV | | |
609 | SPRITE1_FLIP_DONE_INT_EN_VLV); | |
610 | if (status_mask & SPRITE0_FLIP_DONE_INT_STATUS_VLV) | |
611 | enable_mask |= SPRITE0_FLIP_DONE_INT_EN_VLV; | |
612 | if (status_mask & SPRITE1_FLIP_DONE_INT_STATUS_VLV) | |
613 | enable_mask |= SPRITE1_FLIP_DONE_INT_EN_VLV; | |
614 | ||
615 | return enable_mask; | |
616 | } | |
617 | ||
755e9019 ID |
618 | void |
619 | i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe, | |
620 | u32 status_mask) | |
621 | { | |
622 | u32 enable_mask; | |
623 | ||
666a4537 | 624 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) |
91c8a326 | 625 | enable_mask = vlv_get_pipestat_enable_mask(&dev_priv->drm, |
10c59c51 ID |
626 | status_mask); |
627 | else | |
628 | enable_mask = status_mask << 16; | |
755e9019 ID |
629 | __i915_enable_pipestat(dev_priv, pipe, enable_mask, status_mask); |
630 | } | |
631 | ||
632 | void | |
633 | i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe, | |
634 | u32 status_mask) | |
635 | { | |
636 | u32 enable_mask; | |
637 | ||
666a4537 | 638 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) |
91c8a326 | 639 | enable_mask = vlv_get_pipestat_enable_mask(&dev_priv->drm, |
10c59c51 ID |
640 | status_mask); |
641 | else | |
642 | enable_mask = status_mask << 16; | |
755e9019 ID |
643 | __i915_disable_pipestat(dev_priv, pipe, enable_mask, status_mask); |
644 | } | |
645 | ||
01c66889 | 646 | /** |
f49e38dd | 647 | * i915_enable_asle_pipestat - enable ASLE pipestat for OpRegion |
14bb2c11 | 648 | * @dev_priv: i915 device private |
01c66889 | 649 | */ |
91d14251 | 650 | static void i915_enable_asle_pipestat(struct drm_i915_private *dev_priv) |
01c66889 | 651 | { |
91d14251 | 652 | if (!dev_priv->opregion.asle || !IS_MOBILE(dev_priv)) |
f49e38dd JN |
653 | return; |
654 | ||
13321786 | 655 | spin_lock_irq(&dev_priv->irq_lock); |
01c66889 | 656 | |
755e9019 | 657 | i915_enable_pipestat(dev_priv, PIPE_B, PIPE_LEGACY_BLC_EVENT_STATUS); |
91d14251 | 658 | if (INTEL_GEN(dev_priv) >= 4) |
3b6c42e8 | 659 | i915_enable_pipestat(dev_priv, PIPE_A, |
755e9019 | 660 | PIPE_LEGACY_BLC_EVENT_STATUS); |
1ec14ad3 | 661 | |
13321786 | 662 | spin_unlock_irq(&dev_priv->irq_lock); |
01c66889 ZY |
663 | } |
664 | ||
f75f3746 VS |
665 | /* |
666 | * This timing diagram depicts the video signal in and | |
667 | * around the vertical blanking period. | |
668 | * | |
669 | * Assumptions about the fictitious mode used in this example: | |
670 | * vblank_start >= 3 | |
671 | * vsync_start = vblank_start + 1 | |
672 | * vsync_end = vblank_start + 2 | |
673 | * vtotal = vblank_start + 3 | |
674 | * | |
675 | * start of vblank: | |
676 | * latch double buffered registers | |
677 | * increment frame counter (ctg+) | |
678 | * generate start of vblank interrupt (gen4+) | |
679 | * | | |
680 | * | frame start: | |
681 | * | generate frame start interrupt (aka. vblank interrupt) (gmch) | |
682 | * | may be shifted forward 1-3 extra lines via PIPECONF | |
683 | * | | | |
684 | * | | start of vsync: | |
685 | * | | generate vsync interrupt | |
686 | * | | | | |
687 | * ___xxxx___ ___xxxx___ ___xxxx___ ___xxxx___ ___xxxx___ ___xxxx | |
688 | * . \hs/ . \hs/ \hs/ \hs/ . \hs/ | |
689 | * ----va---> <-----------------vb--------------------> <--------va------------- | |
690 | * | | <----vs-----> | | |
691 | * -vbs-----> <---vbs+1---> <---vbs+2---> <-----0-----> <-----1-----> <-----2--- (scanline counter gen2) | |
692 | * -vbs-2---> <---vbs-1---> <---vbs-----> <---vbs+1---> <---vbs+2---> <-----0--- (scanline counter gen3+) | |
693 | * -vbs-2---> <---vbs-2---> <---vbs-1---> <---vbs-----> <---vbs+1---> <---vbs+2- (scanline counter hsw+ hdmi) | |
694 | * | | | | |
695 | * last visible pixel first visible pixel | |
696 | * | increment frame counter (gen3/4) | |
697 | * pixel counter = vblank_start * htotal pixel counter = 0 (gen3/4) | |
698 | * | |
699 | * x = horizontal active | |
700 | * _ = horizontal blanking | |
701 | * hs = horizontal sync | |
702 | * va = vertical active | |
703 | * vb = vertical blanking | |
704 | * vs = vertical sync | |
705 | * vbs = vblank_start (number) | |
706 | * | |
707 | * Summary: | |
708 | * - most events happen at the start of horizontal sync | |
709 | * - frame start happens at the start of horizontal blank, 1-4 lines | |
710 | * (depending on PIPECONF settings) after the start of vblank | |
711 | * - gen3/4 pixel and frame counter are synchronized with the start | |
712 | * of horizontal active on the first line of vertical active | |
713 | */ | |
714 | ||
42f52ef8 KP |
715 | /* Called from drm generic code, passed a 'crtc', which |
716 | * we use as a pipe index | |
717 | */ | |
88e72717 | 718 | static u32 i915_get_vblank_counter(struct drm_device *dev, unsigned int pipe) |
0a3e67a4 | 719 | { |
fac5e23e | 720 | struct drm_i915_private *dev_priv = to_i915(dev); |
f0f59a00 | 721 | i915_reg_t high_frame, low_frame; |
0b2a8e09 | 722 | u32 high1, high2, low, pixel, vbl_start, hsync_start, htotal; |
5caa0fea | 723 | const struct drm_display_mode *mode = &dev->vblank[pipe].hwmode; |
694e409d | 724 | unsigned long irqflags; |
0a3e67a4 | 725 | |
f3a5c3f6 DV |
726 | htotal = mode->crtc_htotal; |
727 | hsync_start = mode->crtc_hsync_start; | |
728 | vbl_start = mode->crtc_vblank_start; | |
729 | if (mode->flags & DRM_MODE_FLAG_INTERLACE) | |
730 | vbl_start = DIV_ROUND_UP(vbl_start, 2); | |
391f75e2 | 731 | |
0b2a8e09 VS |
732 | /* Convert to pixel count */ |
733 | vbl_start *= htotal; | |
734 | ||
735 | /* Start of vblank event occurs at start of hsync */ | |
736 | vbl_start -= htotal - hsync_start; | |
737 | ||
9db4a9c7 JB |
738 | high_frame = PIPEFRAME(pipe); |
739 | low_frame = PIPEFRAMEPIXEL(pipe); | |
5eddb70b | 740 | |
694e409d VS |
741 | spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); |
742 | ||
0a3e67a4 JB |
743 | /* |
744 | * High & low register fields aren't synchronized, so make sure | |
745 | * we get a low value that's stable across two reads of the high | |
746 | * register. | |
747 | */ | |
748 | do { | |
694e409d VS |
749 | high1 = I915_READ_FW(high_frame) & PIPE_FRAME_HIGH_MASK; |
750 | low = I915_READ_FW(low_frame); | |
751 | high2 = I915_READ_FW(high_frame) & PIPE_FRAME_HIGH_MASK; | |
0a3e67a4 JB |
752 | } while (high1 != high2); |
753 | ||
694e409d VS |
754 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); |
755 | ||
5eddb70b | 756 | high1 >>= PIPE_FRAME_HIGH_SHIFT; |
391f75e2 | 757 | pixel = low & PIPE_PIXEL_MASK; |
5eddb70b | 758 | low >>= PIPE_FRAME_LOW_SHIFT; |
391f75e2 VS |
759 | |
760 | /* | |
761 | * The frame counter increments at beginning of active. | |
762 | * Cook up a vblank counter by also checking the pixel | |
763 | * counter against vblank start. | |
764 | */ | |
edc08d0a | 765 | return (((high1 << 8) | low) + (pixel >= vbl_start)) & 0xffffff; |
0a3e67a4 JB |
766 | } |
767 | ||
974e59ba | 768 | static u32 g4x_get_vblank_counter(struct drm_device *dev, unsigned int pipe) |
9880b7a5 | 769 | { |
fac5e23e | 770 | struct drm_i915_private *dev_priv = to_i915(dev); |
9880b7a5 | 771 | |
649636ef | 772 | return I915_READ(PIPE_FRMCOUNT_G4X(pipe)); |
9880b7a5 JB |
773 | } |
774 | ||
75aa3f63 | 775 | /* I915_READ_FW, only for fast reads of display block, no need for forcewake etc. */ |
a225f079 VS |
776 | static int __intel_get_crtc_scanline(struct intel_crtc *crtc) |
777 | { | |
778 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 779 | struct drm_i915_private *dev_priv = to_i915(dev); |
5caa0fea DV |
780 | const struct drm_display_mode *mode; |
781 | struct drm_vblank_crtc *vblank; | |
a225f079 | 782 | enum pipe pipe = crtc->pipe; |
80715b2f | 783 | int position, vtotal; |
a225f079 | 784 | |
72259536 VS |
785 | if (!crtc->active) |
786 | return -1; | |
787 | ||
5caa0fea DV |
788 | vblank = &crtc->base.dev->vblank[drm_crtc_index(&crtc->base)]; |
789 | mode = &vblank->hwmode; | |
790 | ||
80715b2f | 791 | vtotal = mode->crtc_vtotal; |
a225f079 VS |
792 | if (mode->flags & DRM_MODE_FLAG_INTERLACE) |
793 | vtotal /= 2; | |
794 | ||
91d14251 | 795 | if (IS_GEN2(dev_priv)) |
75aa3f63 | 796 | position = I915_READ_FW(PIPEDSL(pipe)) & DSL_LINEMASK_GEN2; |
a225f079 | 797 | else |
75aa3f63 | 798 | position = I915_READ_FW(PIPEDSL(pipe)) & DSL_LINEMASK_GEN3; |
a225f079 | 799 | |
41b578fb JB |
800 | /* |
801 | * On HSW, the DSL reg (0x70000) appears to return 0 if we | |
802 | * read it just before the start of vblank. So try it again | |
803 | * so we don't accidentally end up spanning a vblank frame | |
804 | * increment, causing the pipe_update_end() code to squak at us. | |
805 | * | |
806 | * The nature of this problem means we can't simply check the ISR | |
807 | * bit and return the vblank start value; nor can we use the scanline | |
808 | * debug register in the transcoder as it appears to have the same | |
809 | * problem. We may need to extend this to include other platforms, | |
810 | * but so far testing only shows the problem on HSW. | |
811 | */ | |
91d14251 | 812 | if (HAS_DDI(dev_priv) && !position) { |
41b578fb JB |
813 | int i, temp; |
814 | ||
815 | for (i = 0; i < 100; i++) { | |
816 | udelay(1); | |
707bdd3f | 817 | temp = I915_READ_FW(PIPEDSL(pipe)) & DSL_LINEMASK_GEN3; |
41b578fb JB |
818 | if (temp != position) { |
819 | position = temp; | |
820 | break; | |
821 | } | |
822 | } | |
823 | } | |
824 | ||
a225f079 | 825 | /* |
80715b2f VS |
826 | * See update_scanline_offset() for the details on the |
827 | * scanline_offset adjustment. | |
a225f079 | 828 | */ |
80715b2f | 829 | return (position + crtc->scanline_offset) % vtotal; |
a225f079 VS |
830 | } |
831 | ||
1bf6ad62 DV |
832 | static bool i915_get_crtc_scanoutpos(struct drm_device *dev, unsigned int pipe, |
833 | bool in_vblank_irq, int *vpos, int *hpos, | |
834 | ktime_t *stime, ktime_t *etime, | |
835 | const struct drm_display_mode *mode) | |
0af7e4df | 836 | { |
fac5e23e | 837 | struct drm_i915_private *dev_priv = to_i915(dev); |
98187836 VS |
838 | struct intel_crtc *intel_crtc = intel_get_crtc_for_pipe(dev_priv, |
839 | pipe); | |
3aa18df8 | 840 | int position; |
78e8fc6b | 841 | int vbl_start, vbl_end, hsync_start, htotal, vtotal; |
0af7e4df | 842 | bool in_vbl = true; |
ad3543ed | 843 | unsigned long irqflags; |
0af7e4df | 844 | |
fc467a22 | 845 | if (WARN_ON(!mode->crtc_clock)) { |
0af7e4df | 846 | DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled " |
9db4a9c7 | 847 | "pipe %c\n", pipe_name(pipe)); |
1bf6ad62 | 848 | return false; |
0af7e4df MK |
849 | } |
850 | ||
c2baf4b7 | 851 | htotal = mode->crtc_htotal; |
78e8fc6b | 852 | hsync_start = mode->crtc_hsync_start; |
c2baf4b7 VS |
853 | vtotal = mode->crtc_vtotal; |
854 | vbl_start = mode->crtc_vblank_start; | |
855 | vbl_end = mode->crtc_vblank_end; | |
0af7e4df | 856 | |
d31faf65 VS |
857 | if (mode->flags & DRM_MODE_FLAG_INTERLACE) { |
858 | vbl_start = DIV_ROUND_UP(vbl_start, 2); | |
859 | vbl_end /= 2; | |
860 | vtotal /= 2; | |
861 | } | |
862 | ||
ad3543ed MK |
863 | /* |
864 | * Lock uncore.lock, as we will do multiple timing critical raw | |
865 | * register reads, potentially with preemption disabled, so the | |
866 | * following code must not block on uncore.lock. | |
867 | */ | |
868 | spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); | |
78e8fc6b | 869 | |
ad3543ed MK |
870 | /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */ |
871 | ||
872 | /* Get optional system timestamp before query. */ | |
873 | if (stime) | |
874 | *stime = ktime_get(); | |
875 | ||
91d14251 | 876 | if (IS_GEN2(dev_priv) || IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5) { |
0af7e4df MK |
877 | /* No obvious pixelcount register. Only query vertical |
878 | * scanout position from Display scan line register. | |
879 | */ | |
a225f079 | 880 | position = __intel_get_crtc_scanline(intel_crtc); |
0af7e4df MK |
881 | } else { |
882 | /* Have access to pixelcount since start of frame. | |
883 | * We can split this into vertical and horizontal | |
884 | * scanout position. | |
885 | */ | |
75aa3f63 | 886 | position = (I915_READ_FW(PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT; |
0af7e4df | 887 | |
3aa18df8 VS |
888 | /* convert to pixel counts */ |
889 | vbl_start *= htotal; | |
890 | vbl_end *= htotal; | |
891 | vtotal *= htotal; | |
78e8fc6b | 892 | |
7e78f1cb VS |
893 | /* |
894 | * In interlaced modes, the pixel counter counts all pixels, | |
895 | * so one field will have htotal more pixels. In order to avoid | |
896 | * the reported position from jumping backwards when the pixel | |
897 | * counter is beyond the length of the shorter field, just | |
898 | * clamp the position the length of the shorter field. This | |
899 | * matches how the scanline counter based position works since | |
900 | * the scanline counter doesn't count the two half lines. | |
901 | */ | |
902 | if (position >= vtotal) | |
903 | position = vtotal - 1; | |
904 | ||
78e8fc6b VS |
905 | /* |
906 | * Start of vblank interrupt is triggered at start of hsync, | |
907 | * just prior to the first active line of vblank. However we | |
908 | * consider lines to start at the leading edge of horizontal | |
909 | * active. So, should we get here before we've crossed into | |
910 | * the horizontal active of the first line in vblank, we would | |
911 | * not set the DRM_SCANOUTPOS_INVBL flag. In order to fix that, | |
912 | * always add htotal-hsync_start to the current pixel position. | |
913 | */ | |
914 | position = (position + htotal - hsync_start) % vtotal; | |
0af7e4df MK |
915 | } |
916 | ||
ad3543ed MK |
917 | /* Get optional system timestamp after query. */ |
918 | if (etime) | |
919 | *etime = ktime_get(); | |
920 | ||
921 | /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */ | |
922 | ||
923 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); | |
924 | ||
3aa18df8 VS |
925 | in_vbl = position >= vbl_start && position < vbl_end; |
926 | ||
927 | /* | |
928 | * While in vblank, position will be negative | |
929 | * counting up towards 0 at vbl_end. And outside | |
930 | * vblank, position will be positive counting | |
931 | * up since vbl_end. | |
932 | */ | |
933 | if (position >= vbl_start) | |
934 | position -= vbl_end; | |
935 | else | |
936 | position += vtotal - vbl_end; | |
0af7e4df | 937 | |
91d14251 | 938 | if (IS_GEN2(dev_priv) || IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5) { |
3aa18df8 VS |
939 | *vpos = position; |
940 | *hpos = 0; | |
941 | } else { | |
942 | *vpos = position / htotal; | |
943 | *hpos = position - (*vpos * htotal); | |
944 | } | |
0af7e4df | 945 | |
1bf6ad62 | 946 | return true; |
0af7e4df MK |
947 | } |
948 | ||
a225f079 VS |
949 | int intel_get_crtc_scanline(struct intel_crtc *crtc) |
950 | { | |
fac5e23e | 951 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
a225f079 VS |
952 | unsigned long irqflags; |
953 | int position; | |
954 | ||
955 | spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); | |
956 | position = __intel_get_crtc_scanline(crtc); | |
957 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); | |
958 | ||
959 | return position; | |
960 | } | |
961 | ||
91d14251 | 962 | static void ironlake_rps_change_irq_handler(struct drm_i915_private *dev_priv) |
f97108d1 | 963 | { |
b5b72e89 | 964 | u32 busy_up, busy_down, max_avg, min_avg; |
9270388e | 965 | u8 new_delay; |
9270388e | 966 | |
d0ecd7e2 | 967 | spin_lock(&mchdev_lock); |
f97108d1 | 968 | |
73edd18f DV |
969 | I915_WRITE16(MEMINTRSTS, I915_READ(MEMINTRSTS)); |
970 | ||
20e4d407 | 971 | new_delay = dev_priv->ips.cur_delay; |
9270388e | 972 | |
7648fa99 | 973 | I915_WRITE16(MEMINTRSTS, MEMINT_EVAL_CHG); |
b5b72e89 MG |
974 | busy_up = I915_READ(RCPREVBSYTUPAVG); |
975 | busy_down = I915_READ(RCPREVBSYTDNAVG); | |
f97108d1 JB |
976 | max_avg = I915_READ(RCBMAXAVG); |
977 | min_avg = I915_READ(RCBMINAVG); | |
978 | ||
979 | /* Handle RCS change request from hw */ | |
b5b72e89 | 980 | if (busy_up > max_avg) { |
20e4d407 DV |
981 | if (dev_priv->ips.cur_delay != dev_priv->ips.max_delay) |
982 | new_delay = dev_priv->ips.cur_delay - 1; | |
983 | if (new_delay < dev_priv->ips.max_delay) | |
984 | new_delay = dev_priv->ips.max_delay; | |
b5b72e89 | 985 | } else if (busy_down < min_avg) { |
20e4d407 DV |
986 | if (dev_priv->ips.cur_delay != dev_priv->ips.min_delay) |
987 | new_delay = dev_priv->ips.cur_delay + 1; | |
988 | if (new_delay > dev_priv->ips.min_delay) | |
989 | new_delay = dev_priv->ips.min_delay; | |
f97108d1 JB |
990 | } |
991 | ||
91d14251 | 992 | if (ironlake_set_drps(dev_priv, new_delay)) |
20e4d407 | 993 | dev_priv->ips.cur_delay = new_delay; |
f97108d1 | 994 | |
d0ecd7e2 | 995 | spin_unlock(&mchdev_lock); |
9270388e | 996 | |
f97108d1 JB |
997 | return; |
998 | } | |
999 | ||
0bc40be8 | 1000 | static void notify_ring(struct intel_engine_cs *engine) |
549f7365 | 1001 | { |
56299fb7 CW |
1002 | struct drm_i915_gem_request *rq = NULL; |
1003 | struct intel_wait *wait; | |
dffabc8f | 1004 | |
2246bea6 | 1005 | atomic_inc(&engine->irq_count); |
538b257d | 1006 | set_bit(ENGINE_IRQ_BREADCRUMB, &engine->irq_posted); |
56299fb7 | 1007 | |
61d3dc70 CW |
1008 | spin_lock(&engine->breadcrumbs.irq_lock); |
1009 | wait = engine->breadcrumbs.irq_wait; | |
56299fb7 CW |
1010 | if (wait) { |
1011 | /* We use a callback from the dma-fence to submit | |
1012 | * requests after waiting on our own requests. To | |
1013 | * ensure minimum delay in queuing the next request to | |
1014 | * hardware, signal the fence now rather than wait for | |
1015 | * the signaler to be woken up. We still wake up the | |
1016 | * waiter in order to handle the irq-seqno coherency | |
1017 | * issues (we may receive the interrupt before the | |
1018 | * seqno is written, see __i915_request_irq_complete()) | |
1019 | * and to handle coalescing of multiple seqno updates | |
1020 | * and many waiters. | |
1021 | */ | |
1022 | if (i915_seqno_passed(intel_engine_get_seqno(engine), | |
db93991b CW |
1023 | wait->seqno) && |
1024 | !test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, | |
1025 | &wait->request->fence.flags)) | |
24754d75 | 1026 | rq = i915_gem_request_get(wait->request); |
56299fb7 CW |
1027 | |
1028 | wake_up_process(wait->tsk); | |
67b807a8 CW |
1029 | } else { |
1030 | __intel_engine_disarm_breadcrumbs(engine); | |
56299fb7 | 1031 | } |
61d3dc70 | 1032 | spin_unlock(&engine->breadcrumbs.irq_lock); |
56299fb7 | 1033 | |
24754d75 | 1034 | if (rq) { |
56299fb7 | 1035 | dma_fence_signal(&rq->fence); |
24754d75 CW |
1036 | i915_gem_request_put(rq); |
1037 | } | |
56299fb7 CW |
1038 | |
1039 | trace_intel_engine_notify(engine, wait); | |
549f7365 CW |
1040 | } |
1041 | ||
43cf3bf0 CW |
1042 | static void vlv_c0_read(struct drm_i915_private *dev_priv, |
1043 | struct intel_rps_ei *ei) | |
31685c25 | 1044 | { |
679cb6c1 | 1045 | ei->ktime = ktime_get_raw(); |
43cf3bf0 CW |
1046 | ei->render_c0 = I915_READ(VLV_RENDER_C0_COUNT); |
1047 | ei->media_c0 = I915_READ(VLV_MEDIA_C0_COUNT); | |
1048 | } | |
31685c25 | 1049 | |
43cf3bf0 | 1050 | void gen6_rps_reset_ei(struct drm_i915_private *dev_priv) |
31685c25 | 1051 | { |
e0e8c7cb | 1052 | memset(&dev_priv->rps.ei, 0, sizeof(dev_priv->rps.ei)); |
43cf3bf0 | 1053 | } |
31685c25 | 1054 | |
43cf3bf0 CW |
1055 | static u32 vlv_wa_c0_ei(struct drm_i915_private *dev_priv, u32 pm_iir) |
1056 | { | |
e0e8c7cb | 1057 | const struct intel_rps_ei *prev = &dev_priv->rps.ei; |
43cf3bf0 CW |
1058 | struct intel_rps_ei now; |
1059 | u32 events = 0; | |
31685c25 | 1060 | |
e0e8c7cb | 1061 | if ((pm_iir & GEN6_PM_RP_UP_EI_EXPIRED) == 0) |
43cf3bf0 | 1062 | return 0; |
31685c25 | 1063 | |
43cf3bf0 | 1064 | vlv_c0_read(dev_priv, &now); |
31685c25 | 1065 | |
679cb6c1 | 1066 | if (prev->ktime) { |
e0e8c7cb | 1067 | u64 time, c0; |
569884e3 | 1068 | u32 render, media; |
e0e8c7cb | 1069 | |
679cb6c1 | 1070 | time = ktime_us_delta(now.ktime, prev->ktime); |
8f68d591 | 1071 | |
e0e8c7cb CW |
1072 | time *= dev_priv->czclk_freq; |
1073 | ||
1074 | /* Workload can be split between render + media, | |
1075 | * e.g. SwapBuffers being blitted in X after being rendered in | |
1076 | * mesa. To account for this we need to combine both engines | |
1077 | * into our activity counter. | |
1078 | */ | |
569884e3 CW |
1079 | render = now.render_c0 - prev->render_c0; |
1080 | media = now.media_c0 - prev->media_c0; | |
1081 | c0 = max(render, media); | |
6b7f6aa7 | 1082 | c0 *= 1000 * 100 << 8; /* to usecs and scale to threshold% */ |
e0e8c7cb CW |
1083 | |
1084 | if (c0 > time * dev_priv->rps.up_threshold) | |
1085 | events = GEN6_PM_RP_UP_THRESHOLD; | |
1086 | else if (c0 < time * dev_priv->rps.down_threshold) | |
1087 | events = GEN6_PM_RP_DOWN_THRESHOLD; | |
31685c25 D |
1088 | } |
1089 | ||
e0e8c7cb | 1090 | dev_priv->rps.ei = now; |
43cf3bf0 | 1091 | return events; |
31685c25 D |
1092 | } |
1093 | ||
4912d041 | 1094 | static void gen6_pm_rps_work(struct work_struct *work) |
3b8d8d91 | 1095 | { |
2d1013dd JN |
1096 | struct drm_i915_private *dev_priv = |
1097 | container_of(work, struct drm_i915_private, rps.work); | |
7c0a16ad | 1098 | bool client_boost = false; |
8d3afd7d | 1099 | int new_delay, adj, min, max; |
7c0a16ad | 1100 | u32 pm_iir = 0; |
4912d041 | 1101 | |
59cdb63d | 1102 | spin_lock_irq(&dev_priv->irq_lock); |
7c0a16ad CW |
1103 | if (dev_priv->rps.interrupts_enabled) { |
1104 | pm_iir = fetch_and_zero(&dev_priv->rps.pm_iir); | |
7b92c1bd | 1105 | client_boost = atomic_read(&dev_priv->rps.num_waiters); |
d4d70aa5 | 1106 | } |
59cdb63d | 1107 | spin_unlock_irq(&dev_priv->irq_lock); |
3b8d8d91 | 1108 | |
60611c13 | 1109 | /* Make sure we didn't queue anything we're not going to process. */ |
a6706b45 | 1110 | WARN_ON(pm_iir & ~dev_priv->pm_rps_events); |
8d3afd7d | 1111 | if ((pm_iir & dev_priv->pm_rps_events) == 0 && !client_boost) |
7c0a16ad | 1112 | goto out; |
3b8d8d91 | 1113 | |
4fc688ce | 1114 | mutex_lock(&dev_priv->rps.hw_lock); |
7b9e0ae6 | 1115 | |
43cf3bf0 CW |
1116 | pm_iir |= vlv_wa_c0_ei(dev_priv, pm_iir); |
1117 | ||
dd75fdc8 | 1118 | adj = dev_priv->rps.last_adj; |
edcf284b | 1119 | new_delay = dev_priv->rps.cur_freq; |
8d3afd7d CW |
1120 | min = dev_priv->rps.min_freq_softlimit; |
1121 | max = dev_priv->rps.max_freq_softlimit; | |
7b92c1bd | 1122 | if (client_boost) |
29ecd78d CW |
1123 | max = dev_priv->rps.max_freq; |
1124 | if (client_boost && new_delay < dev_priv->rps.boost_freq) { | |
1125 | new_delay = dev_priv->rps.boost_freq; | |
8d3afd7d CW |
1126 | adj = 0; |
1127 | } else if (pm_iir & GEN6_PM_RP_UP_THRESHOLD) { | |
dd75fdc8 CW |
1128 | if (adj > 0) |
1129 | adj *= 2; | |
edcf284b CW |
1130 | else /* CHV needs even encode values */ |
1131 | adj = IS_CHERRYVIEW(dev_priv) ? 2 : 1; | |
7e79a683 SAK |
1132 | |
1133 | if (new_delay >= dev_priv->rps.max_freq_softlimit) | |
1134 | adj = 0; | |
7b92c1bd | 1135 | } else if (client_boost) { |
f5a4c67d | 1136 | adj = 0; |
dd75fdc8 | 1137 | } else if (pm_iir & GEN6_PM_RP_DOWN_TIMEOUT) { |
b39fb297 BW |
1138 | if (dev_priv->rps.cur_freq > dev_priv->rps.efficient_freq) |
1139 | new_delay = dev_priv->rps.efficient_freq; | |
17136d54 | 1140 | else if (dev_priv->rps.cur_freq > dev_priv->rps.min_freq_softlimit) |
b39fb297 | 1141 | new_delay = dev_priv->rps.min_freq_softlimit; |
dd75fdc8 CW |
1142 | adj = 0; |
1143 | } else if (pm_iir & GEN6_PM_RP_DOWN_THRESHOLD) { | |
1144 | if (adj < 0) | |
1145 | adj *= 2; | |
edcf284b CW |
1146 | else /* CHV needs even encode values */ |
1147 | adj = IS_CHERRYVIEW(dev_priv) ? -2 : -1; | |
7e79a683 SAK |
1148 | |
1149 | if (new_delay <= dev_priv->rps.min_freq_softlimit) | |
1150 | adj = 0; | |
dd75fdc8 | 1151 | } else { /* unknown event */ |
edcf284b | 1152 | adj = 0; |
dd75fdc8 | 1153 | } |
3b8d8d91 | 1154 | |
edcf284b CW |
1155 | dev_priv->rps.last_adj = adj; |
1156 | ||
79249636 BW |
1157 | /* sysfs frequency interfaces may have snuck in while servicing the |
1158 | * interrupt | |
1159 | */ | |
edcf284b | 1160 | new_delay += adj; |
8d3afd7d | 1161 | new_delay = clamp_t(int, new_delay, min, max); |
27544369 | 1162 | |
9fcee2f7 CW |
1163 | if (intel_set_rps(dev_priv, new_delay)) { |
1164 | DRM_DEBUG_DRIVER("Failed to set new GPU frequency\n"); | |
1165 | dev_priv->rps.last_adj = 0; | |
1166 | } | |
3b8d8d91 | 1167 | |
4fc688ce | 1168 | mutex_unlock(&dev_priv->rps.hw_lock); |
7c0a16ad CW |
1169 | |
1170 | out: | |
1171 | /* Make sure not to corrupt PMIMR state used by ringbuffer on GEN6 */ | |
1172 | spin_lock_irq(&dev_priv->irq_lock); | |
1173 | if (dev_priv->rps.interrupts_enabled) | |
1174 | gen6_unmask_pm_irq(dev_priv, dev_priv->pm_rps_events); | |
1175 | spin_unlock_irq(&dev_priv->irq_lock); | |
3b8d8d91 JB |
1176 | } |
1177 | ||
e3689190 BW |
1178 | |
1179 | /** | |
1180 | * ivybridge_parity_work - Workqueue called when a parity error interrupt | |
1181 | * occurred. | |
1182 | * @work: workqueue struct | |
1183 | * | |
1184 | * Doesn't actually do anything except notify userspace. As a consequence of | |
1185 | * this event, userspace should try to remap the bad rows since statistically | |
1186 | * it is likely the same row is more likely to go bad again. | |
1187 | */ | |
1188 | static void ivybridge_parity_work(struct work_struct *work) | |
1189 | { | |
2d1013dd | 1190 | struct drm_i915_private *dev_priv = |
cefcff8f | 1191 | container_of(work, typeof(*dev_priv), l3_parity.error_work); |
e3689190 | 1192 | u32 error_status, row, bank, subbank; |
35a85ac6 | 1193 | char *parity_event[6]; |
e3689190 | 1194 | uint32_t misccpctl; |
35a85ac6 | 1195 | uint8_t slice = 0; |
e3689190 BW |
1196 | |
1197 | /* We must turn off DOP level clock gating to access the L3 registers. | |
1198 | * In order to prevent a get/put style interface, acquire struct mutex | |
1199 | * any time we access those registers. | |
1200 | */ | |
91c8a326 | 1201 | mutex_lock(&dev_priv->drm.struct_mutex); |
e3689190 | 1202 | |
35a85ac6 BW |
1203 | /* If we've screwed up tracking, just let the interrupt fire again */ |
1204 | if (WARN_ON(!dev_priv->l3_parity.which_slice)) | |
1205 | goto out; | |
1206 | ||
e3689190 BW |
1207 | misccpctl = I915_READ(GEN7_MISCCPCTL); |
1208 | I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE); | |
1209 | POSTING_READ(GEN7_MISCCPCTL); | |
1210 | ||
35a85ac6 | 1211 | while ((slice = ffs(dev_priv->l3_parity.which_slice)) != 0) { |
f0f59a00 | 1212 | i915_reg_t reg; |
e3689190 | 1213 | |
35a85ac6 | 1214 | slice--; |
2d1fe073 | 1215 | if (WARN_ON_ONCE(slice >= NUM_L3_SLICES(dev_priv))) |
35a85ac6 | 1216 | break; |
e3689190 | 1217 | |
35a85ac6 | 1218 | dev_priv->l3_parity.which_slice &= ~(1<<slice); |
e3689190 | 1219 | |
6fa1c5f1 | 1220 | reg = GEN7_L3CDERRST1(slice); |
e3689190 | 1221 | |
35a85ac6 BW |
1222 | error_status = I915_READ(reg); |
1223 | row = GEN7_PARITY_ERROR_ROW(error_status); | |
1224 | bank = GEN7_PARITY_ERROR_BANK(error_status); | |
1225 | subbank = GEN7_PARITY_ERROR_SUBBANK(error_status); | |
1226 | ||
1227 | I915_WRITE(reg, GEN7_PARITY_ERROR_VALID | GEN7_L3CDERRST1_ENABLE); | |
1228 | POSTING_READ(reg); | |
1229 | ||
1230 | parity_event[0] = I915_L3_PARITY_UEVENT "=1"; | |
1231 | parity_event[1] = kasprintf(GFP_KERNEL, "ROW=%d", row); | |
1232 | parity_event[2] = kasprintf(GFP_KERNEL, "BANK=%d", bank); | |
1233 | parity_event[3] = kasprintf(GFP_KERNEL, "SUBBANK=%d", subbank); | |
1234 | parity_event[4] = kasprintf(GFP_KERNEL, "SLICE=%d", slice); | |
1235 | parity_event[5] = NULL; | |
1236 | ||
91c8a326 | 1237 | kobject_uevent_env(&dev_priv->drm.primary->kdev->kobj, |
35a85ac6 | 1238 | KOBJ_CHANGE, parity_event); |
e3689190 | 1239 | |
35a85ac6 BW |
1240 | DRM_DEBUG("Parity error: Slice = %d, Row = %d, Bank = %d, Sub bank = %d.\n", |
1241 | slice, row, bank, subbank); | |
e3689190 | 1242 | |
35a85ac6 BW |
1243 | kfree(parity_event[4]); |
1244 | kfree(parity_event[3]); | |
1245 | kfree(parity_event[2]); | |
1246 | kfree(parity_event[1]); | |
1247 | } | |
e3689190 | 1248 | |
35a85ac6 | 1249 | I915_WRITE(GEN7_MISCCPCTL, misccpctl); |
e3689190 | 1250 | |
35a85ac6 BW |
1251 | out: |
1252 | WARN_ON(dev_priv->l3_parity.which_slice); | |
4cb21832 | 1253 | spin_lock_irq(&dev_priv->irq_lock); |
2d1fe073 | 1254 | gen5_enable_gt_irq(dev_priv, GT_PARITY_ERROR(dev_priv)); |
4cb21832 | 1255 | spin_unlock_irq(&dev_priv->irq_lock); |
35a85ac6 | 1256 | |
91c8a326 | 1257 | mutex_unlock(&dev_priv->drm.struct_mutex); |
e3689190 BW |
1258 | } |
1259 | ||
261e40b8 VS |
1260 | static void ivybridge_parity_error_irq_handler(struct drm_i915_private *dev_priv, |
1261 | u32 iir) | |
e3689190 | 1262 | { |
261e40b8 | 1263 | if (!HAS_L3_DPF(dev_priv)) |
e3689190 BW |
1264 | return; |
1265 | ||
d0ecd7e2 | 1266 | spin_lock(&dev_priv->irq_lock); |
261e40b8 | 1267 | gen5_disable_gt_irq(dev_priv, GT_PARITY_ERROR(dev_priv)); |
d0ecd7e2 | 1268 | spin_unlock(&dev_priv->irq_lock); |
e3689190 | 1269 | |
261e40b8 | 1270 | iir &= GT_PARITY_ERROR(dev_priv); |
35a85ac6 BW |
1271 | if (iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1) |
1272 | dev_priv->l3_parity.which_slice |= 1 << 1; | |
1273 | ||
1274 | if (iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT) | |
1275 | dev_priv->l3_parity.which_slice |= 1 << 0; | |
1276 | ||
a4da4fa4 | 1277 | queue_work(dev_priv->wq, &dev_priv->l3_parity.error_work); |
e3689190 BW |
1278 | } |
1279 | ||
261e40b8 | 1280 | static void ilk_gt_irq_handler(struct drm_i915_private *dev_priv, |
f1af8fc1 PZ |
1281 | u32 gt_iir) |
1282 | { | |
f8973c21 | 1283 | if (gt_iir & GT_RENDER_USER_INTERRUPT) |
3b3f1650 | 1284 | notify_ring(dev_priv->engine[RCS]); |
f1af8fc1 | 1285 | if (gt_iir & ILK_BSD_USER_INTERRUPT) |
3b3f1650 | 1286 | notify_ring(dev_priv->engine[VCS]); |
f1af8fc1 PZ |
1287 | } |
1288 | ||
261e40b8 | 1289 | static void snb_gt_irq_handler(struct drm_i915_private *dev_priv, |
e7b4c6b1 DV |
1290 | u32 gt_iir) |
1291 | { | |
f8973c21 | 1292 | if (gt_iir & GT_RENDER_USER_INTERRUPT) |
3b3f1650 | 1293 | notify_ring(dev_priv->engine[RCS]); |
cc609d5d | 1294 | if (gt_iir & GT_BSD_USER_INTERRUPT) |
3b3f1650 | 1295 | notify_ring(dev_priv->engine[VCS]); |
cc609d5d | 1296 | if (gt_iir & GT_BLT_USER_INTERRUPT) |
3b3f1650 | 1297 | notify_ring(dev_priv->engine[BCS]); |
e7b4c6b1 | 1298 | |
cc609d5d BW |
1299 | if (gt_iir & (GT_BLT_CS_ERROR_INTERRUPT | |
1300 | GT_BSD_CS_ERROR_INTERRUPT | | |
aaecdf61 DV |
1301 | GT_RENDER_CS_MASTER_ERROR_INTERRUPT)) |
1302 | DRM_DEBUG("Command parser error, gt_iir 0x%08x\n", gt_iir); | |
e3689190 | 1303 | |
261e40b8 VS |
1304 | if (gt_iir & GT_PARITY_ERROR(dev_priv)) |
1305 | ivybridge_parity_error_irq_handler(dev_priv, gt_iir); | |
e7b4c6b1 DV |
1306 | } |
1307 | ||
5d3d69d5 | 1308 | static void |
0bc40be8 | 1309 | gen8_cs_irq_handler(struct intel_engine_cs *engine, u32 iir, int test_shift) |
fbcc1a0c | 1310 | { |
31de7350 | 1311 | bool tasklet = false; |
f747026c CW |
1312 | |
1313 | if (iir & (GT_CONTEXT_SWITCH_INTERRUPT << test_shift)) { | |
a4b2b015 | 1314 | if (port_count(&engine->execlist_port[0])) { |
955a4b89 | 1315 | __set_bit(ENGINE_IRQ_EXECLIST, &engine->irq_posted); |
a4b2b015 CW |
1316 | tasklet = true; |
1317 | } | |
f747026c | 1318 | } |
31de7350 CW |
1319 | |
1320 | if (iir & (GT_RENDER_USER_INTERRUPT << test_shift)) { | |
1321 | notify_ring(engine); | |
1322 | tasklet |= i915.enable_guc_submission; | |
1323 | } | |
1324 | ||
1325 | if (tasklet) | |
1326 | tasklet_hi_schedule(&engine->irq_tasklet); | |
fbcc1a0c NH |
1327 | } |
1328 | ||
e30e251a VS |
1329 | static irqreturn_t gen8_gt_irq_ack(struct drm_i915_private *dev_priv, |
1330 | u32 master_ctl, | |
1331 | u32 gt_iir[4]) | |
abd58f01 | 1332 | { |
abd58f01 BW |
1333 | irqreturn_t ret = IRQ_NONE; |
1334 | ||
1335 | if (master_ctl & (GEN8_GT_RCS_IRQ | GEN8_GT_BCS_IRQ)) { | |
e30e251a VS |
1336 | gt_iir[0] = I915_READ_FW(GEN8_GT_IIR(0)); |
1337 | if (gt_iir[0]) { | |
1338 | I915_WRITE_FW(GEN8_GT_IIR(0), gt_iir[0]); | |
abd58f01 | 1339 | ret = IRQ_HANDLED; |
abd58f01 BW |
1340 | } else |
1341 | DRM_ERROR("The master control interrupt lied (GT0)!\n"); | |
1342 | } | |
1343 | ||
85f9b5f9 | 1344 | if (master_ctl & (GEN8_GT_VCS1_IRQ | GEN8_GT_VCS2_IRQ)) { |
e30e251a VS |
1345 | gt_iir[1] = I915_READ_FW(GEN8_GT_IIR(1)); |
1346 | if (gt_iir[1]) { | |
1347 | I915_WRITE_FW(GEN8_GT_IIR(1), gt_iir[1]); | |
abd58f01 | 1348 | ret = IRQ_HANDLED; |
0961021a | 1349 | } else |
abd58f01 | 1350 | DRM_ERROR("The master control interrupt lied (GT1)!\n"); |
0961021a BW |
1351 | } |
1352 | ||
abd58f01 | 1353 | if (master_ctl & GEN8_GT_VECS_IRQ) { |
e30e251a VS |
1354 | gt_iir[3] = I915_READ_FW(GEN8_GT_IIR(3)); |
1355 | if (gt_iir[3]) { | |
1356 | I915_WRITE_FW(GEN8_GT_IIR(3), gt_iir[3]); | |
abd58f01 | 1357 | ret = IRQ_HANDLED; |
abd58f01 BW |
1358 | } else |
1359 | DRM_ERROR("The master control interrupt lied (GT3)!\n"); | |
1360 | } | |
1361 | ||
26705e20 | 1362 | if (master_ctl & (GEN8_GT_PM_IRQ | GEN8_GT_GUC_IRQ)) { |
e30e251a | 1363 | gt_iir[2] = I915_READ_FW(GEN8_GT_IIR(2)); |
26705e20 SAK |
1364 | if (gt_iir[2] & (dev_priv->pm_rps_events | |
1365 | dev_priv->pm_guc_events)) { | |
cb0d205e | 1366 | I915_WRITE_FW(GEN8_GT_IIR(2), |
26705e20 SAK |
1367 | gt_iir[2] & (dev_priv->pm_rps_events | |
1368 | dev_priv->pm_guc_events)); | |
38cc46d7 | 1369 | ret = IRQ_HANDLED; |
0961021a BW |
1370 | } else |
1371 | DRM_ERROR("The master control interrupt lied (PM)!\n"); | |
1372 | } | |
1373 | ||
abd58f01 BW |
1374 | return ret; |
1375 | } | |
1376 | ||
e30e251a VS |
1377 | static void gen8_gt_irq_handler(struct drm_i915_private *dev_priv, |
1378 | u32 gt_iir[4]) | |
1379 | { | |
1380 | if (gt_iir[0]) { | |
3b3f1650 | 1381 | gen8_cs_irq_handler(dev_priv->engine[RCS], |
e30e251a | 1382 | gt_iir[0], GEN8_RCS_IRQ_SHIFT); |
3b3f1650 | 1383 | gen8_cs_irq_handler(dev_priv->engine[BCS], |
e30e251a VS |
1384 | gt_iir[0], GEN8_BCS_IRQ_SHIFT); |
1385 | } | |
1386 | ||
1387 | if (gt_iir[1]) { | |
3b3f1650 | 1388 | gen8_cs_irq_handler(dev_priv->engine[VCS], |
e30e251a | 1389 | gt_iir[1], GEN8_VCS1_IRQ_SHIFT); |
3b3f1650 | 1390 | gen8_cs_irq_handler(dev_priv->engine[VCS2], |
e30e251a VS |
1391 | gt_iir[1], GEN8_VCS2_IRQ_SHIFT); |
1392 | } | |
1393 | ||
1394 | if (gt_iir[3]) | |
3b3f1650 | 1395 | gen8_cs_irq_handler(dev_priv->engine[VECS], |
e30e251a VS |
1396 | gt_iir[3], GEN8_VECS_IRQ_SHIFT); |
1397 | ||
1398 | if (gt_iir[2] & dev_priv->pm_rps_events) | |
1399 | gen6_rps_irq_handler(dev_priv, gt_iir[2]); | |
26705e20 SAK |
1400 | |
1401 | if (gt_iir[2] & dev_priv->pm_guc_events) | |
1402 | gen9_guc_irq_handler(dev_priv, gt_iir[2]); | |
e30e251a VS |
1403 | } |
1404 | ||
63c88d22 ID |
1405 | static bool bxt_port_hotplug_long_detect(enum port port, u32 val) |
1406 | { | |
1407 | switch (port) { | |
1408 | case PORT_A: | |
195baa06 | 1409 | return val & PORTA_HOTPLUG_LONG_DETECT; |
63c88d22 ID |
1410 | case PORT_B: |
1411 | return val & PORTB_HOTPLUG_LONG_DETECT; | |
1412 | case PORT_C: | |
1413 | return val & PORTC_HOTPLUG_LONG_DETECT; | |
63c88d22 ID |
1414 | default: |
1415 | return false; | |
1416 | } | |
1417 | } | |
1418 | ||
6dbf30ce VS |
1419 | static bool spt_port_hotplug2_long_detect(enum port port, u32 val) |
1420 | { | |
1421 | switch (port) { | |
1422 | case PORT_E: | |
1423 | return val & PORTE_HOTPLUG_LONG_DETECT; | |
1424 | default: | |
1425 | return false; | |
1426 | } | |
1427 | } | |
1428 | ||
74c0b395 VS |
1429 | static bool spt_port_hotplug_long_detect(enum port port, u32 val) |
1430 | { | |
1431 | switch (port) { | |
1432 | case PORT_A: | |
1433 | return val & PORTA_HOTPLUG_LONG_DETECT; | |
1434 | case PORT_B: | |
1435 | return val & PORTB_HOTPLUG_LONG_DETECT; | |
1436 | case PORT_C: | |
1437 | return val & PORTC_HOTPLUG_LONG_DETECT; | |
1438 | case PORT_D: | |
1439 | return val & PORTD_HOTPLUG_LONG_DETECT; | |
1440 | default: | |
1441 | return false; | |
1442 | } | |
1443 | } | |
1444 | ||
e4ce95aa VS |
1445 | static bool ilk_port_hotplug_long_detect(enum port port, u32 val) |
1446 | { | |
1447 | switch (port) { | |
1448 | case PORT_A: | |
1449 | return val & DIGITAL_PORTA_HOTPLUG_LONG_DETECT; | |
1450 | default: | |
1451 | return false; | |
1452 | } | |
1453 | } | |
1454 | ||
676574df | 1455 | static bool pch_port_hotplug_long_detect(enum port port, u32 val) |
13cf5504 DA |
1456 | { |
1457 | switch (port) { | |
13cf5504 | 1458 | case PORT_B: |
676574df | 1459 | return val & PORTB_HOTPLUG_LONG_DETECT; |
13cf5504 | 1460 | case PORT_C: |
676574df | 1461 | return val & PORTC_HOTPLUG_LONG_DETECT; |
13cf5504 | 1462 | case PORT_D: |
676574df JN |
1463 | return val & PORTD_HOTPLUG_LONG_DETECT; |
1464 | default: | |
1465 | return false; | |
13cf5504 DA |
1466 | } |
1467 | } | |
1468 | ||
676574df | 1469 | static bool i9xx_port_hotplug_long_detect(enum port port, u32 val) |
13cf5504 DA |
1470 | { |
1471 | switch (port) { | |
13cf5504 | 1472 | case PORT_B: |
676574df | 1473 | return val & PORTB_HOTPLUG_INT_LONG_PULSE; |
13cf5504 | 1474 | case PORT_C: |
676574df | 1475 | return val & PORTC_HOTPLUG_INT_LONG_PULSE; |
13cf5504 | 1476 | case PORT_D: |
676574df JN |
1477 | return val & PORTD_HOTPLUG_INT_LONG_PULSE; |
1478 | default: | |
1479 | return false; | |
13cf5504 DA |
1480 | } |
1481 | } | |
1482 | ||
42db67d6 VS |
1483 | /* |
1484 | * Get a bit mask of pins that have triggered, and which ones may be long. | |
1485 | * This can be called multiple times with the same masks to accumulate | |
1486 | * hotplug detection results from several registers. | |
1487 | * | |
1488 | * Note that the caller is expected to zero out the masks initially. | |
1489 | */ | |
fd63e2a9 | 1490 | static void intel_get_hpd_pins(u32 *pin_mask, u32 *long_mask, |
8c841e57 | 1491 | u32 hotplug_trigger, u32 dig_hotplug_reg, |
fd63e2a9 ID |
1492 | const u32 hpd[HPD_NUM_PINS], |
1493 | bool long_pulse_detect(enum port port, u32 val)) | |
676574df | 1494 | { |
8c841e57 | 1495 | enum port port; |
676574df JN |
1496 | int i; |
1497 | ||
676574df | 1498 | for_each_hpd_pin(i) { |
8c841e57 JN |
1499 | if ((hpd[i] & hotplug_trigger) == 0) |
1500 | continue; | |
676574df | 1501 | |
8c841e57 JN |
1502 | *pin_mask |= BIT(i); |
1503 | ||
cc24fcdc ID |
1504 | if (!intel_hpd_pin_to_port(i, &port)) |
1505 | continue; | |
1506 | ||
fd63e2a9 | 1507 | if (long_pulse_detect(port, dig_hotplug_reg)) |
8c841e57 | 1508 | *long_mask |= BIT(i); |
676574df JN |
1509 | } |
1510 | ||
1511 | DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x, dig 0x%08x, pins 0x%08x\n", | |
1512 | hotplug_trigger, dig_hotplug_reg, *pin_mask); | |
1513 | ||
1514 | } | |
1515 | ||
91d14251 | 1516 | static void gmbus_irq_handler(struct drm_i915_private *dev_priv) |
515ac2bb | 1517 | { |
28c70f16 | 1518 | wake_up_all(&dev_priv->gmbus_wait_queue); |
515ac2bb DV |
1519 | } |
1520 | ||
91d14251 | 1521 | static void dp_aux_irq_handler(struct drm_i915_private *dev_priv) |
ce99c256 | 1522 | { |
9ee32fea | 1523 | wake_up_all(&dev_priv->gmbus_wait_queue); |
ce99c256 DV |
1524 | } |
1525 | ||
8bf1e9f1 | 1526 | #if defined(CONFIG_DEBUG_FS) |
91d14251 TU |
1527 | static void display_pipe_crc_irq_handler(struct drm_i915_private *dev_priv, |
1528 | enum pipe pipe, | |
277de95e DV |
1529 | uint32_t crc0, uint32_t crc1, |
1530 | uint32_t crc2, uint32_t crc3, | |
1531 | uint32_t crc4) | |
8bf1e9f1 | 1532 | { |
8bf1e9f1 SH |
1533 | struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe]; |
1534 | struct intel_pipe_crc_entry *entry; | |
8c6b709d TV |
1535 | struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe); |
1536 | struct drm_driver *driver = dev_priv->drm.driver; | |
1537 | uint32_t crcs[5]; | |
ac2300d4 | 1538 | int head, tail; |
b2c88f5b | 1539 | |
d538bbdf | 1540 | spin_lock(&pipe_crc->lock); |
8c6b709d TV |
1541 | if (pipe_crc->source) { |
1542 | if (!pipe_crc->entries) { | |
1543 | spin_unlock(&pipe_crc->lock); | |
1544 | DRM_DEBUG_KMS("spurious interrupt\n"); | |
1545 | return; | |
1546 | } | |
d538bbdf | 1547 | |
8c6b709d TV |
1548 | head = pipe_crc->head; |
1549 | tail = pipe_crc->tail; | |
b2c88f5b | 1550 | |
8c6b709d TV |
1551 | if (CIRC_SPACE(head, tail, INTEL_PIPE_CRC_ENTRIES_NR) < 1) { |
1552 | spin_unlock(&pipe_crc->lock); | |
1553 | DRM_ERROR("CRC buffer overflowing\n"); | |
1554 | return; | |
1555 | } | |
b2c88f5b | 1556 | |
8c6b709d | 1557 | entry = &pipe_crc->entries[head]; |
8bf1e9f1 | 1558 | |
8c6b709d TV |
1559 | entry->frame = driver->get_vblank_counter(&dev_priv->drm, pipe); |
1560 | entry->crc[0] = crc0; | |
1561 | entry->crc[1] = crc1; | |
1562 | entry->crc[2] = crc2; | |
1563 | entry->crc[3] = crc3; | |
1564 | entry->crc[4] = crc4; | |
b2c88f5b | 1565 | |
8c6b709d TV |
1566 | head = (head + 1) & (INTEL_PIPE_CRC_ENTRIES_NR - 1); |
1567 | pipe_crc->head = head; | |
d538bbdf | 1568 | |
8c6b709d | 1569 | spin_unlock(&pipe_crc->lock); |
07144428 | 1570 | |
8c6b709d TV |
1571 | wake_up_interruptible(&pipe_crc->wq); |
1572 | } else { | |
1573 | /* | |
1574 | * For some not yet identified reason, the first CRC is | |
1575 | * bonkers. So let's just wait for the next vblank and read | |
1576 | * out the buggy result. | |
1577 | * | |
1578 | * On CHV sometimes the second CRC is bonkers as well, so | |
1579 | * don't trust that one either. | |
1580 | */ | |
1581 | if (pipe_crc->skipped == 0 || | |
1582 | (IS_CHERRYVIEW(dev_priv) && pipe_crc->skipped == 1)) { | |
1583 | pipe_crc->skipped++; | |
1584 | spin_unlock(&pipe_crc->lock); | |
1585 | return; | |
1586 | } | |
1587 | spin_unlock(&pipe_crc->lock); | |
1588 | crcs[0] = crc0; | |
1589 | crcs[1] = crc1; | |
1590 | crcs[2] = crc2; | |
1591 | crcs[3] = crc3; | |
1592 | crcs[4] = crc4; | |
246ee524 TV |
1593 | drm_crtc_add_crc_entry(&crtc->base, true, |
1594 | drm_accurate_vblank_count(&crtc->base), | |
1595 | crcs); | |
8c6b709d | 1596 | } |
8bf1e9f1 | 1597 | } |
277de95e DV |
1598 | #else |
1599 | static inline void | |
91d14251 TU |
1600 | display_pipe_crc_irq_handler(struct drm_i915_private *dev_priv, |
1601 | enum pipe pipe, | |
277de95e DV |
1602 | uint32_t crc0, uint32_t crc1, |
1603 | uint32_t crc2, uint32_t crc3, | |
1604 | uint32_t crc4) {} | |
1605 | #endif | |
1606 | ||
eba94eb9 | 1607 | |
91d14251 TU |
1608 | static void hsw_pipe_crc_irq_handler(struct drm_i915_private *dev_priv, |
1609 | enum pipe pipe) | |
5a69b89f | 1610 | { |
91d14251 | 1611 | display_pipe_crc_irq_handler(dev_priv, pipe, |
277de95e DV |
1612 | I915_READ(PIPE_CRC_RES_1_IVB(pipe)), |
1613 | 0, 0, 0, 0); | |
5a69b89f DV |
1614 | } |
1615 | ||
91d14251 TU |
1616 | static void ivb_pipe_crc_irq_handler(struct drm_i915_private *dev_priv, |
1617 | enum pipe pipe) | |
eba94eb9 | 1618 | { |
91d14251 | 1619 | display_pipe_crc_irq_handler(dev_priv, pipe, |
277de95e DV |
1620 | I915_READ(PIPE_CRC_RES_1_IVB(pipe)), |
1621 | I915_READ(PIPE_CRC_RES_2_IVB(pipe)), | |
1622 | I915_READ(PIPE_CRC_RES_3_IVB(pipe)), | |
1623 | I915_READ(PIPE_CRC_RES_4_IVB(pipe)), | |
1624 | I915_READ(PIPE_CRC_RES_5_IVB(pipe))); | |
eba94eb9 | 1625 | } |
5b3a856b | 1626 | |
91d14251 TU |
1627 | static void i9xx_pipe_crc_irq_handler(struct drm_i915_private *dev_priv, |
1628 | enum pipe pipe) | |
5b3a856b | 1629 | { |
0b5c5ed0 DV |
1630 | uint32_t res1, res2; |
1631 | ||
91d14251 | 1632 | if (INTEL_GEN(dev_priv) >= 3) |
0b5c5ed0 DV |
1633 | res1 = I915_READ(PIPE_CRC_RES_RES1_I915(pipe)); |
1634 | else | |
1635 | res1 = 0; | |
1636 | ||
91d14251 | 1637 | if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv)) |
0b5c5ed0 DV |
1638 | res2 = I915_READ(PIPE_CRC_RES_RES2_G4X(pipe)); |
1639 | else | |
1640 | res2 = 0; | |
5b3a856b | 1641 | |
91d14251 | 1642 | display_pipe_crc_irq_handler(dev_priv, pipe, |
277de95e DV |
1643 | I915_READ(PIPE_CRC_RES_RED(pipe)), |
1644 | I915_READ(PIPE_CRC_RES_GREEN(pipe)), | |
1645 | I915_READ(PIPE_CRC_RES_BLUE(pipe)), | |
1646 | res1, res2); | |
5b3a856b | 1647 | } |
8bf1e9f1 | 1648 | |
1403c0d4 PZ |
1649 | /* The RPS events need forcewake, so we add them to a work queue and mask their |
1650 | * IMR bits until the work is done. Other interrupts can be processed without | |
1651 | * the work queue. */ | |
1652 | static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir) | |
baf02a1f | 1653 | { |
a6706b45 | 1654 | if (pm_iir & dev_priv->pm_rps_events) { |
59cdb63d | 1655 | spin_lock(&dev_priv->irq_lock); |
f4e9af4f | 1656 | gen6_mask_pm_irq(dev_priv, pm_iir & dev_priv->pm_rps_events); |
d4d70aa5 ID |
1657 | if (dev_priv->rps.interrupts_enabled) { |
1658 | dev_priv->rps.pm_iir |= pm_iir & dev_priv->pm_rps_events; | |
c33d247d | 1659 | schedule_work(&dev_priv->rps.work); |
d4d70aa5 | 1660 | } |
59cdb63d | 1661 | spin_unlock(&dev_priv->irq_lock); |
baf02a1f | 1662 | } |
baf02a1f | 1663 | |
c9a9a268 ID |
1664 | if (INTEL_INFO(dev_priv)->gen >= 8) |
1665 | return; | |
1666 | ||
2d1fe073 | 1667 | if (HAS_VEBOX(dev_priv)) { |
1403c0d4 | 1668 | if (pm_iir & PM_VEBOX_USER_INTERRUPT) |
3b3f1650 | 1669 | notify_ring(dev_priv->engine[VECS]); |
12638c57 | 1670 | |
aaecdf61 DV |
1671 | if (pm_iir & PM_VEBOX_CS_ERROR_INTERRUPT) |
1672 | DRM_DEBUG("Command parser error, pm_iir 0x%08x\n", pm_iir); | |
12638c57 | 1673 | } |
baf02a1f BW |
1674 | } |
1675 | ||
26705e20 SAK |
1676 | static void gen9_guc_irq_handler(struct drm_i915_private *dev_priv, u32 gt_iir) |
1677 | { | |
1678 | if (gt_iir & GEN9_GUC_TO_HOST_INT_EVENT) { | |
4100b2ab SAK |
1679 | /* Sample the log buffer flush related bits & clear them out now |
1680 | * itself from the message identity register to minimize the | |
1681 | * probability of losing a flush interrupt, when there are back | |
1682 | * to back flush interrupts. | |
1683 | * There can be a new flush interrupt, for different log buffer | |
1684 | * type (like for ISR), whilst Host is handling one (for DPC). | |
1685 | * Since same bit is used in message register for ISR & DPC, it | |
1686 | * could happen that GuC sets the bit for 2nd interrupt but Host | |
1687 | * clears out the bit on handling the 1st interrupt. | |
1688 | */ | |
1689 | u32 msg, flush; | |
1690 | ||
1691 | msg = I915_READ(SOFT_SCRATCH(15)); | |
a80bc45f AH |
1692 | flush = msg & (INTEL_GUC_RECV_MSG_CRASH_DUMP_POSTED | |
1693 | INTEL_GUC_RECV_MSG_FLUSH_LOG_BUFFER); | |
4100b2ab SAK |
1694 | if (flush) { |
1695 | /* Clear the message bits that are handled */ | |
1696 | I915_WRITE(SOFT_SCRATCH(15), msg & ~flush); | |
1697 | ||
1698 | /* Handle flush interrupt in bottom half */ | |
e7465473 OM |
1699 | queue_work(dev_priv->guc.log.runtime.flush_wq, |
1700 | &dev_priv->guc.log.runtime.flush_work); | |
5aa1ee4b AG |
1701 | |
1702 | dev_priv->guc.log.flush_interrupt_count++; | |
4100b2ab SAK |
1703 | } else { |
1704 | /* Not clearing of unhandled event bits won't result in | |
1705 | * re-triggering of the interrupt. | |
1706 | */ | |
1707 | } | |
26705e20 SAK |
1708 | } |
1709 | } | |
1710 | ||
5a21b665 | 1711 | static bool intel_pipe_handle_vblank(struct drm_i915_private *dev_priv, |
91d14251 | 1712 | enum pipe pipe) |
8d7849db | 1713 | { |
5a21b665 DV |
1714 | bool ret; |
1715 | ||
91c8a326 | 1716 | ret = drm_handle_vblank(&dev_priv->drm, pipe); |
5a21b665 | 1717 | if (ret) |
51cbaf01 | 1718 | intel_finish_page_flip_mmio(dev_priv, pipe); |
5a21b665 DV |
1719 | |
1720 | return ret; | |
8d7849db VS |
1721 | } |
1722 | ||
91d14251 TU |
1723 | static void valleyview_pipestat_irq_ack(struct drm_i915_private *dev_priv, |
1724 | u32 iir, u32 pipe_stats[I915_MAX_PIPES]) | |
c1874ed7 | 1725 | { |
c1874ed7 ID |
1726 | int pipe; |
1727 | ||
58ead0d7 | 1728 | spin_lock(&dev_priv->irq_lock); |
1ca993d2 VS |
1729 | |
1730 | if (!dev_priv->display_irqs_enabled) { | |
1731 | spin_unlock(&dev_priv->irq_lock); | |
1732 | return; | |
1733 | } | |
1734 | ||
055e393f | 1735 | for_each_pipe(dev_priv, pipe) { |
f0f59a00 | 1736 | i915_reg_t reg; |
bbb5eebf | 1737 | u32 mask, iir_bit = 0; |
91d181dd | 1738 | |
bbb5eebf DV |
1739 | /* |
1740 | * PIPESTAT bits get signalled even when the interrupt is | |
1741 | * disabled with the mask bits, and some of the status bits do | |
1742 | * not generate interrupts at all (like the underrun bit). Hence | |
1743 | * we need to be careful that we only handle what we want to | |
1744 | * handle. | |
1745 | */ | |
0f239f4c DV |
1746 | |
1747 | /* fifo underruns are filterered in the underrun handler. */ | |
1748 | mask = PIPE_FIFO_UNDERRUN_STATUS; | |
bbb5eebf DV |
1749 | |
1750 | switch (pipe) { | |
1751 | case PIPE_A: | |
1752 | iir_bit = I915_DISPLAY_PIPE_A_EVENT_INTERRUPT; | |
1753 | break; | |
1754 | case PIPE_B: | |
1755 | iir_bit = I915_DISPLAY_PIPE_B_EVENT_INTERRUPT; | |
1756 | break; | |
3278f67f VS |
1757 | case PIPE_C: |
1758 | iir_bit = I915_DISPLAY_PIPE_C_EVENT_INTERRUPT; | |
1759 | break; | |
bbb5eebf DV |
1760 | } |
1761 | if (iir & iir_bit) | |
1762 | mask |= dev_priv->pipestat_irq_mask[pipe]; | |
1763 | ||
1764 | if (!mask) | |
91d181dd ID |
1765 | continue; |
1766 | ||
1767 | reg = PIPESTAT(pipe); | |
bbb5eebf DV |
1768 | mask |= PIPESTAT_INT_ENABLE_MASK; |
1769 | pipe_stats[pipe] = I915_READ(reg) & mask; | |
c1874ed7 ID |
1770 | |
1771 | /* | |
1772 | * Clear the PIPE*STAT regs before the IIR | |
1773 | */ | |
91d181dd ID |
1774 | if (pipe_stats[pipe] & (PIPE_FIFO_UNDERRUN_STATUS | |
1775 | PIPESTAT_INT_STATUS_MASK)) | |
c1874ed7 ID |
1776 | I915_WRITE(reg, pipe_stats[pipe]); |
1777 | } | |
58ead0d7 | 1778 | spin_unlock(&dev_priv->irq_lock); |
2ecb8ca4 VS |
1779 | } |
1780 | ||
91d14251 | 1781 | static void valleyview_pipestat_irq_handler(struct drm_i915_private *dev_priv, |
2ecb8ca4 VS |
1782 | u32 pipe_stats[I915_MAX_PIPES]) |
1783 | { | |
2ecb8ca4 | 1784 | enum pipe pipe; |
c1874ed7 | 1785 | |
055e393f | 1786 | for_each_pipe(dev_priv, pipe) { |
5a21b665 DV |
1787 | if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS && |
1788 | intel_pipe_handle_vblank(dev_priv, pipe)) | |
1789 | intel_check_page_flip(dev_priv, pipe); | |
c1874ed7 | 1790 | |
5251f04e | 1791 | if (pipe_stats[pipe] & PLANE_FLIP_DONE_INT_STATUS_VLV) |
51cbaf01 | 1792 | intel_finish_page_flip_cs(dev_priv, pipe); |
c1874ed7 ID |
1793 | |
1794 | if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS) | |
91d14251 | 1795 | i9xx_pipe_crc_irq_handler(dev_priv, pipe); |
c1874ed7 | 1796 | |
1f7247c0 DV |
1797 | if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS) |
1798 | intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe); | |
c1874ed7 ID |
1799 | } |
1800 | ||
1801 | if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS) | |
91d14251 | 1802 | gmbus_irq_handler(dev_priv); |
c1874ed7 ID |
1803 | } |
1804 | ||
1ae3c34c | 1805 | static u32 i9xx_hpd_irq_ack(struct drm_i915_private *dev_priv) |
16c6c56b | 1806 | { |
16c6c56b VS |
1807 | u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT); |
1808 | ||
1ae3c34c VS |
1809 | if (hotplug_status) |
1810 | I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status); | |
16c6c56b | 1811 | |
1ae3c34c VS |
1812 | return hotplug_status; |
1813 | } | |
1814 | ||
91d14251 | 1815 | static void i9xx_hpd_irq_handler(struct drm_i915_private *dev_priv, |
1ae3c34c VS |
1816 | u32 hotplug_status) |
1817 | { | |
1818 | u32 pin_mask = 0, long_mask = 0; | |
16c6c56b | 1819 | |
91d14251 TU |
1820 | if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) || |
1821 | IS_CHERRYVIEW(dev_priv)) { | |
0d2e4297 | 1822 | u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_G4X; |
16c6c56b | 1823 | |
58f2cf24 VS |
1824 | if (hotplug_trigger) { |
1825 | intel_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger, | |
1826 | hotplug_trigger, hpd_status_g4x, | |
1827 | i9xx_port_hotplug_long_detect); | |
1828 | ||
91d14251 | 1829 | intel_hpd_irq_handler(dev_priv, pin_mask, long_mask); |
58f2cf24 | 1830 | } |
369712e8 JN |
1831 | |
1832 | if (hotplug_status & DP_AUX_CHANNEL_MASK_INT_STATUS_G4X) | |
91d14251 | 1833 | dp_aux_irq_handler(dev_priv); |
0d2e4297 JN |
1834 | } else { |
1835 | u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_I915; | |
16c6c56b | 1836 | |
58f2cf24 VS |
1837 | if (hotplug_trigger) { |
1838 | intel_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger, | |
44cc6c08 | 1839 | hotplug_trigger, hpd_status_i915, |
58f2cf24 | 1840 | i9xx_port_hotplug_long_detect); |
91d14251 | 1841 | intel_hpd_irq_handler(dev_priv, pin_mask, long_mask); |
58f2cf24 | 1842 | } |
3ff60f89 | 1843 | } |
16c6c56b VS |
1844 | } |
1845 | ||
ff1f525e | 1846 | static irqreturn_t valleyview_irq_handler(int irq, void *arg) |
7e231dbe | 1847 | { |
45a83f84 | 1848 | struct drm_device *dev = arg; |
fac5e23e | 1849 | struct drm_i915_private *dev_priv = to_i915(dev); |
7e231dbe | 1850 | irqreturn_t ret = IRQ_NONE; |
7e231dbe | 1851 | |
2dd2a883 ID |
1852 | if (!intel_irqs_enabled(dev_priv)) |
1853 | return IRQ_NONE; | |
1854 | ||
1f814dac ID |
1855 | /* IRQs are synced during runtime_suspend, we don't require a wakeref */ |
1856 | disable_rpm_wakeref_asserts(dev_priv); | |
1857 | ||
1e1cace9 | 1858 | do { |
6e814800 | 1859 | u32 iir, gt_iir, pm_iir; |
2ecb8ca4 | 1860 | u32 pipe_stats[I915_MAX_PIPES] = {}; |
1ae3c34c | 1861 | u32 hotplug_status = 0; |
a5e485a9 | 1862 | u32 ier = 0; |
3ff60f89 | 1863 | |
7e231dbe JB |
1864 | gt_iir = I915_READ(GTIIR); |
1865 | pm_iir = I915_READ(GEN6_PMIIR); | |
3ff60f89 | 1866 | iir = I915_READ(VLV_IIR); |
7e231dbe JB |
1867 | |
1868 | if (gt_iir == 0 && pm_iir == 0 && iir == 0) | |
1e1cace9 | 1869 | break; |
7e231dbe JB |
1870 | |
1871 | ret = IRQ_HANDLED; | |
1872 | ||
a5e485a9 VS |
1873 | /* |
1874 | * Theory on interrupt generation, based on empirical evidence: | |
1875 | * | |
1876 | * x = ((VLV_IIR & VLV_IER) || | |
1877 | * (((GT_IIR & GT_IER) || (GEN6_PMIIR & GEN6_PMIER)) && | |
1878 | * (VLV_MASTER_IER & MASTER_INTERRUPT_ENABLE))); | |
1879 | * | |
1880 | * A CPU interrupt will only be raised when 'x' has a 0->1 edge. | |
1881 | * Hence we clear MASTER_INTERRUPT_ENABLE and VLV_IER to | |
1882 | * guarantee the CPU interrupt will be raised again even if we | |
1883 | * don't end up clearing all the VLV_IIR, GT_IIR, GEN6_PMIIR | |
1884 | * bits this time around. | |
1885 | */ | |
4a0a0202 | 1886 | I915_WRITE(VLV_MASTER_IER, 0); |
a5e485a9 VS |
1887 | ier = I915_READ(VLV_IER); |
1888 | I915_WRITE(VLV_IER, 0); | |
4a0a0202 VS |
1889 | |
1890 | if (gt_iir) | |
1891 | I915_WRITE(GTIIR, gt_iir); | |
1892 | if (pm_iir) | |
1893 | I915_WRITE(GEN6_PMIIR, pm_iir); | |
1894 | ||
7ce4d1f2 | 1895 | if (iir & I915_DISPLAY_PORT_INTERRUPT) |
1ae3c34c | 1896 | hotplug_status = i9xx_hpd_irq_ack(dev_priv); |
7ce4d1f2 | 1897 | |
3ff60f89 OM |
1898 | /* Call regardless, as some status bits might not be |
1899 | * signalled in iir */ | |
91d14251 | 1900 | valleyview_pipestat_irq_ack(dev_priv, iir, pipe_stats); |
7ce4d1f2 | 1901 | |
eef57324 JA |
1902 | if (iir & (I915_LPE_PIPE_A_INTERRUPT | |
1903 | I915_LPE_PIPE_B_INTERRUPT)) | |
1904 | intel_lpe_audio_irq_handler(dev_priv); | |
1905 | ||
7ce4d1f2 VS |
1906 | /* |
1907 | * VLV_IIR is single buffered, and reflects the level | |
1908 | * from PIPESTAT/PORT_HOTPLUG_STAT, hence clear it last. | |
1909 | */ | |
1910 | if (iir) | |
1911 | I915_WRITE(VLV_IIR, iir); | |
4a0a0202 | 1912 | |
a5e485a9 | 1913 | I915_WRITE(VLV_IER, ier); |
4a0a0202 VS |
1914 | I915_WRITE(VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE); |
1915 | POSTING_READ(VLV_MASTER_IER); | |
1ae3c34c | 1916 | |
52894874 | 1917 | if (gt_iir) |
261e40b8 | 1918 | snb_gt_irq_handler(dev_priv, gt_iir); |
52894874 VS |
1919 | if (pm_iir) |
1920 | gen6_rps_irq_handler(dev_priv, pm_iir); | |
1921 | ||
1ae3c34c | 1922 | if (hotplug_status) |
91d14251 | 1923 | i9xx_hpd_irq_handler(dev_priv, hotplug_status); |
2ecb8ca4 | 1924 | |
91d14251 | 1925 | valleyview_pipestat_irq_handler(dev_priv, pipe_stats); |
1e1cace9 | 1926 | } while (0); |
7e231dbe | 1927 | |
1f814dac ID |
1928 | enable_rpm_wakeref_asserts(dev_priv); |
1929 | ||
7e231dbe JB |
1930 | return ret; |
1931 | } | |
1932 | ||
43f328d7 VS |
1933 | static irqreturn_t cherryview_irq_handler(int irq, void *arg) |
1934 | { | |
45a83f84 | 1935 | struct drm_device *dev = arg; |
fac5e23e | 1936 | struct drm_i915_private *dev_priv = to_i915(dev); |
43f328d7 | 1937 | irqreturn_t ret = IRQ_NONE; |
43f328d7 | 1938 | |
2dd2a883 ID |
1939 | if (!intel_irqs_enabled(dev_priv)) |
1940 | return IRQ_NONE; | |
1941 | ||
1f814dac ID |
1942 | /* IRQs are synced during runtime_suspend, we don't require a wakeref */ |
1943 | disable_rpm_wakeref_asserts(dev_priv); | |
1944 | ||
579de73b | 1945 | do { |
6e814800 | 1946 | u32 master_ctl, iir; |
e30e251a | 1947 | u32 gt_iir[4] = {}; |
2ecb8ca4 | 1948 | u32 pipe_stats[I915_MAX_PIPES] = {}; |
1ae3c34c | 1949 | u32 hotplug_status = 0; |
a5e485a9 VS |
1950 | u32 ier = 0; |
1951 | ||
8e5fd599 VS |
1952 | master_ctl = I915_READ(GEN8_MASTER_IRQ) & ~GEN8_MASTER_IRQ_CONTROL; |
1953 | iir = I915_READ(VLV_IIR); | |
43f328d7 | 1954 | |
8e5fd599 VS |
1955 | if (master_ctl == 0 && iir == 0) |
1956 | break; | |
43f328d7 | 1957 | |
27b6c122 OM |
1958 | ret = IRQ_HANDLED; |
1959 | ||
a5e485a9 VS |
1960 | /* |
1961 | * Theory on interrupt generation, based on empirical evidence: | |
1962 | * | |
1963 | * x = ((VLV_IIR & VLV_IER) || | |
1964 | * ((GEN8_MASTER_IRQ & ~GEN8_MASTER_IRQ_CONTROL) && | |
1965 | * (GEN8_MASTER_IRQ & GEN8_MASTER_IRQ_CONTROL))); | |
1966 | * | |
1967 | * A CPU interrupt will only be raised when 'x' has a 0->1 edge. | |
1968 | * Hence we clear GEN8_MASTER_IRQ_CONTROL and VLV_IER to | |
1969 | * guarantee the CPU interrupt will be raised again even if we | |
1970 | * don't end up clearing all the VLV_IIR and GEN8_MASTER_IRQ_CONTROL | |
1971 | * bits this time around. | |
1972 | */ | |
8e5fd599 | 1973 | I915_WRITE(GEN8_MASTER_IRQ, 0); |
a5e485a9 VS |
1974 | ier = I915_READ(VLV_IER); |
1975 | I915_WRITE(VLV_IER, 0); | |
43f328d7 | 1976 | |
e30e251a | 1977 | gen8_gt_irq_ack(dev_priv, master_ctl, gt_iir); |
43f328d7 | 1978 | |
7ce4d1f2 | 1979 | if (iir & I915_DISPLAY_PORT_INTERRUPT) |
1ae3c34c | 1980 | hotplug_status = i9xx_hpd_irq_ack(dev_priv); |
7ce4d1f2 | 1981 | |
27b6c122 OM |
1982 | /* Call regardless, as some status bits might not be |
1983 | * signalled in iir */ | |
91d14251 | 1984 | valleyview_pipestat_irq_ack(dev_priv, iir, pipe_stats); |
43f328d7 | 1985 | |
eef57324 JA |
1986 | if (iir & (I915_LPE_PIPE_A_INTERRUPT | |
1987 | I915_LPE_PIPE_B_INTERRUPT | | |
1988 | I915_LPE_PIPE_C_INTERRUPT)) | |
1989 | intel_lpe_audio_irq_handler(dev_priv); | |
1990 | ||
7ce4d1f2 VS |
1991 | /* |
1992 | * VLV_IIR is single buffered, and reflects the level | |
1993 | * from PIPESTAT/PORT_HOTPLUG_STAT, hence clear it last. | |
1994 | */ | |
1995 | if (iir) | |
1996 | I915_WRITE(VLV_IIR, iir); | |
1997 | ||
a5e485a9 | 1998 | I915_WRITE(VLV_IER, ier); |
e5328c43 | 1999 | I915_WRITE(GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL); |
8e5fd599 | 2000 | POSTING_READ(GEN8_MASTER_IRQ); |
1ae3c34c | 2001 | |
e30e251a VS |
2002 | gen8_gt_irq_handler(dev_priv, gt_iir); |
2003 | ||
1ae3c34c | 2004 | if (hotplug_status) |
91d14251 | 2005 | i9xx_hpd_irq_handler(dev_priv, hotplug_status); |
2ecb8ca4 | 2006 | |
91d14251 | 2007 | valleyview_pipestat_irq_handler(dev_priv, pipe_stats); |
579de73b | 2008 | } while (0); |
3278f67f | 2009 | |
1f814dac ID |
2010 | enable_rpm_wakeref_asserts(dev_priv); |
2011 | ||
43f328d7 VS |
2012 | return ret; |
2013 | } | |
2014 | ||
91d14251 TU |
2015 | static void ibx_hpd_irq_handler(struct drm_i915_private *dev_priv, |
2016 | u32 hotplug_trigger, | |
40e56410 VS |
2017 | const u32 hpd[HPD_NUM_PINS]) |
2018 | { | |
40e56410 VS |
2019 | u32 dig_hotplug_reg, pin_mask = 0, long_mask = 0; |
2020 | ||
6a39d7c9 JN |
2021 | /* |
2022 | * Somehow the PCH doesn't seem to really ack the interrupt to the CPU | |
2023 | * unless we touch the hotplug register, even if hotplug_trigger is | |
2024 | * zero. Not acking leads to "The master control interrupt lied (SDE)!" | |
2025 | * errors. | |
2026 | */ | |
40e56410 | 2027 | dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG); |
6a39d7c9 JN |
2028 | if (!hotplug_trigger) { |
2029 | u32 mask = PORTA_HOTPLUG_STATUS_MASK | | |
2030 | PORTD_HOTPLUG_STATUS_MASK | | |
2031 | PORTC_HOTPLUG_STATUS_MASK | | |
2032 | PORTB_HOTPLUG_STATUS_MASK; | |
2033 | dig_hotplug_reg &= ~mask; | |
2034 | } | |
2035 | ||
40e56410 | 2036 | I915_WRITE(PCH_PORT_HOTPLUG, dig_hotplug_reg); |
6a39d7c9 JN |
2037 | if (!hotplug_trigger) |
2038 | return; | |
40e56410 VS |
2039 | |
2040 | intel_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger, | |
2041 | dig_hotplug_reg, hpd, | |
2042 | pch_port_hotplug_long_detect); | |
2043 | ||
91d14251 | 2044 | intel_hpd_irq_handler(dev_priv, pin_mask, long_mask); |
40e56410 VS |
2045 | } |
2046 | ||
91d14251 | 2047 | static void ibx_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir) |
776ad806 | 2048 | { |
9db4a9c7 | 2049 | int pipe; |
b543fb04 | 2050 | u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK; |
13cf5504 | 2051 | |
91d14251 | 2052 | ibx_hpd_irq_handler(dev_priv, hotplug_trigger, hpd_ibx); |
91d131d2 | 2053 | |
cfc33bf7 VS |
2054 | if (pch_iir & SDE_AUDIO_POWER_MASK) { |
2055 | int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK) >> | |
2056 | SDE_AUDIO_POWER_SHIFT); | |
776ad806 | 2057 | DRM_DEBUG_DRIVER("PCH audio power change on port %d\n", |
cfc33bf7 VS |
2058 | port_name(port)); |
2059 | } | |
776ad806 | 2060 | |
ce99c256 | 2061 | if (pch_iir & SDE_AUX_MASK) |
91d14251 | 2062 | dp_aux_irq_handler(dev_priv); |
ce99c256 | 2063 | |
776ad806 | 2064 | if (pch_iir & SDE_GMBUS) |
91d14251 | 2065 | gmbus_irq_handler(dev_priv); |
776ad806 JB |
2066 | |
2067 | if (pch_iir & SDE_AUDIO_HDCP_MASK) | |
2068 | DRM_DEBUG_DRIVER("PCH HDCP audio interrupt\n"); | |
2069 | ||
2070 | if (pch_iir & SDE_AUDIO_TRANS_MASK) | |
2071 | DRM_DEBUG_DRIVER("PCH transcoder audio interrupt\n"); | |
2072 | ||
2073 | if (pch_iir & SDE_POISON) | |
2074 | DRM_ERROR("PCH poison interrupt\n"); | |
2075 | ||
9db4a9c7 | 2076 | if (pch_iir & SDE_FDI_MASK) |
055e393f | 2077 | for_each_pipe(dev_priv, pipe) |
9db4a9c7 JB |
2078 | DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n", |
2079 | pipe_name(pipe), | |
2080 | I915_READ(FDI_RX_IIR(pipe))); | |
776ad806 JB |
2081 | |
2082 | if (pch_iir & (SDE_TRANSB_CRC_DONE | SDE_TRANSA_CRC_DONE)) | |
2083 | DRM_DEBUG_DRIVER("PCH transcoder CRC done interrupt\n"); | |
2084 | ||
2085 | if (pch_iir & (SDE_TRANSB_CRC_ERR | SDE_TRANSA_CRC_ERR)) | |
2086 | DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n"); | |
2087 | ||
776ad806 | 2088 | if (pch_iir & SDE_TRANSA_FIFO_UNDER) |
a2196033 | 2089 | intel_pch_fifo_underrun_irq_handler(dev_priv, PIPE_A); |
8664281b PZ |
2090 | |
2091 | if (pch_iir & SDE_TRANSB_FIFO_UNDER) | |
a2196033 | 2092 | intel_pch_fifo_underrun_irq_handler(dev_priv, PIPE_B); |
8664281b PZ |
2093 | } |
2094 | ||
91d14251 | 2095 | static void ivb_err_int_handler(struct drm_i915_private *dev_priv) |
8664281b | 2096 | { |
8664281b | 2097 | u32 err_int = I915_READ(GEN7_ERR_INT); |
5a69b89f | 2098 | enum pipe pipe; |
8664281b | 2099 | |
de032bf4 PZ |
2100 | if (err_int & ERR_INT_POISON) |
2101 | DRM_ERROR("Poison interrupt\n"); | |
2102 | ||
055e393f | 2103 | for_each_pipe(dev_priv, pipe) { |
1f7247c0 DV |
2104 | if (err_int & ERR_INT_FIFO_UNDERRUN(pipe)) |
2105 | intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe); | |
8bf1e9f1 | 2106 | |
5a69b89f | 2107 | if (err_int & ERR_INT_PIPE_CRC_DONE(pipe)) { |
91d14251 TU |
2108 | if (IS_IVYBRIDGE(dev_priv)) |
2109 | ivb_pipe_crc_irq_handler(dev_priv, pipe); | |
5a69b89f | 2110 | else |
91d14251 | 2111 | hsw_pipe_crc_irq_handler(dev_priv, pipe); |
5a69b89f DV |
2112 | } |
2113 | } | |
8bf1e9f1 | 2114 | |
8664281b PZ |
2115 | I915_WRITE(GEN7_ERR_INT, err_int); |
2116 | } | |
2117 | ||
91d14251 | 2118 | static void cpt_serr_int_handler(struct drm_i915_private *dev_priv) |
8664281b | 2119 | { |
8664281b PZ |
2120 | u32 serr_int = I915_READ(SERR_INT); |
2121 | ||
de032bf4 PZ |
2122 | if (serr_int & SERR_INT_POISON) |
2123 | DRM_ERROR("PCH poison interrupt\n"); | |
2124 | ||
8664281b | 2125 | if (serr_int & SERR_INT_TRANS_A_FIFO_UNDERRUN) |
a2196033 | 2126 | intel_pch_fifo_underrun_irq_handler(dev_priv, PIPE_A); |
8664281b PZ |
2127 | |
2128 | if (serr_int & SERR_INT_TRANS_B_FIFO_UNDERRUN) | |
a2196033 | 2129 | intel_pch_fifo_underrun_irq_handler(dev_priv, PIPE_B); |
8664281b PZ |
2130 | |
2131 | if (serr_int & SERR_INT_TRANS_C_FIFO_UNDERRUN) | |
a2196033 | 2132 | intel_pch_fifo_underrun_irq_handler(dev_priv, PIPE_C); |
8664281b PZ |
2133 | |
2134 | I915_WRITE(SERR_INT, serr_int); | |
776ad806 JB |
2135 | } |
2136 | ||
91d14251 | 2137 | static void cpt_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir) |
23e81d69 | 2138 | { |
23e81d69 | 2139 | int pipe; |
6dbf30ce | 2140 | u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK_CPT; |
13cf5504 | 2141 | |
91d14251 | 2142 | ibx_hpd_irq_handler(dev_priv, hotplug_trigger, hpd_cpt); |
91d131d2 | 2143 | |
cfc33bf7 VS |
2144 | if (pch_iir & SDE_AUDIO_POWER_MASK_CPT) { |
2145 | int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK_CPT) >> | |
2146 | SDE_AUDIO_POWER_SHIFT_CPT); | |
2147 | DRM_DEBUG_DRIVER("PCH audio power change on port %c\n", | |
2148 | port_name(port)); | |
2149 | } | |
23e81d69 AJ |
2150 | |
2151 | if (pch_iir & SDE_AUX_MASK_CPT) | |
91d14251 | 2152 | dp_aux_irq_handler(dev_priv); |
23e81d69 AJ |
2153 | |
2154 | if (pch_iir & SDE_GMBUS_CPT) | |
91d14251 | 2155 | gmbus_irq_handler(dev_priv); |
23e81d69 AJ |
2156 | |
2157 | if (pch_iir & SDE_AUDIO_CP_REQ_CPT) | |
2158 | DRM_DEBUG_DRIVER("Audio CP request interrupt\n"); | |
2159 | ||
2160 | if (pch_iir & SDE_AUDIO_CP_CHG_CPT) | |
2161 | DRM_DEBUG_DRIVER("Audio CP change interrupt\n"); | |
2162 | ||
2163 | if (pch_iir & SDE_FDI_MASK_CPT) | |
055e393f | 2164 | for_each_pipe(dev_priv, pipe) |
23e81d69 AJ |
2165 | DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n", |
2166 | pipe_name(pipe), | |
2167 | I915_READ(FDI_RX_IIR(pipe))); | |
8664281b PZ |
2168 | |
2169 | if (pch_iir & SDE_ERROR_CPT) | |
91d14251 | 2170 | cpt_serr_int_handler(dev_priv); |
23e81d69 AJ |
2171 | } |
2172 | ||
91d14251 | 2173 | static void spt_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir) |
6dbf30ce | 2174 | { |
6dbf30ce VS |
2175 | u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK_SPT & |
2176 | ~SDE_PORTE_HOTPLUG_SPT; | |
2177 | u32 hotplug2_trigger = pch_iir & SDE_PORTE_HOTPLUG_SPT; | |
2178 | u32 pin_mask = 0, long_mask = 0; | |
2179 | ||
2180 | if (hotplug_trigger) { | |
2181 | u32 dig_hotplug_reg; | |
2182 | ||
2183 | dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG); | |
2184 | I915_WRITE(PCH_PORT_HOTPLUG, dig_hotplug_reg); | |
2185 | ||
2186 | intel_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger, | |
2187 | dig_hotplug_reg, hpd_spt, | |
74c0b395 | 2188 | spt_port_hotplug_long_detect); |
6dbf30ce VS |
2189 | } |
2190 | ||
2191 | if (hotplug2_trigger) { | |
2192 | u32 dig_hotplug_reg; | |
2193 | ||
2194 | dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG2); | |
2195 | I915_WRITE(PCH_PORT_HOTPLUG2, dig_hotplug_reg); | |
2196 | ||
2197 | intel_get_hpd_pins(&pin_mask, &long_mask, hotplug2_trigger, | |
2198 | dig_hotplug_reg, hpd_spt, | |
2199 | spt_port_hotplug2_long_detect); | |
2200 | } | |
2201 | ||
2202 | if (pin_mask) | |
91d14251 | 2203 | intel_hpd_irq_handler(dev_priv, pin_mask, long_mask); |
6dbf30ce VS |
2204 | |
2205 | if (pch_iir & SDE_GMBUS_CPT) | |
91d14251 | 2206 | gmbus_irq_handler(dev_priv); |
6dbf30ce VS |
2207 | } |
2208 | ||
91d14251 TU |
2209 | static void ilk_hpd_irq_handler(struct drm_i915_private *dev_priv, |
2210 | u32 hotplug_trigger, | |
40e56410 VS |
2211 | const u32 hpd[HPD_NUM_PINS]) |
2212 | { | |
40e56410 VS |
2213 | u32 dig_hotplug_reg, pin_mask = 0, long_mask = 0; |
2214 | ||
2215 | dig_hotplug_reg = I915_READ(DIGITAL_PORT_HOTPLUG_CNTRL); | |
2216 | I915_WRITE(DIGITAL_PORT_HOTPLUG_CNTRL, dig_hotplug_reg); | |
2217 | ||
2218 | intel_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger, | |
2219 | dig_hotplug_reg, hpd, | |
2220 | ilk_port_hotplug_long_detect); | |
2221 | ||
91d14251 | 2222 | intel_hpd_irq_handler(dev_priv, pin_mask, long_mask); |
40e56410 VS |
2223 | } |
2224 | ||
91d14251 TU |
2225 | static void ilk_display_irq_handler(struct drm_i915_private *dev_priv, |
2226 | u32 de_iir) | |
c008bc6e | 2227 | { |
40da17c2 | 2228 | enum pipe pipe; |
e4ce95aa VS |
2229 | u32 hotplug_trigger = de_iir & DE_DP_A_HOTPLUG; |
2230 | ||
40e56410 | 2231 | if (hotplug_trigger) |
91d14251 | 2232 | ilk_hpd_irq_handler(dev_priv, hotplug_trigger, hpd_ilk); |
c008bc6e PZ |
2233 | |
2234 | if (de_iir & DE_AUX_CHANNEL_A) | |
91d14251 | 2235 | dp_aux_irq_handler(dev_priv); |
c008bc6e PZ |
2236 | |
2237 | if (de_iir & DE_GSE) | |
91d14251 | 2238 | intel_opregion_asle_intr(dev_priv); |
c008bc6e | 2239 | |
c008bc6e PZ |
2240 | if (de_iir & DE_POISON) |
2241 | DRM_ERROR("Poison interrupt\n"); | |
2242 | ||
055e393f | 2243 | for_each_pipe(dev_priv, pipe) { |
5a21b665 DV |
2244 | if (de_iir & DE_PIPE_VBLANK(pipe) && |
2245 | intel_pipe_handle_vblank(dev_priv, pipe)) | |
2246 | intel_check_page_flip(dev_priv, pipe); | |
5b3a856b | 2247 | |
40da17c2 | 2248 | if (de_iir & DE_PIPE_FIFO_UNDERRUN(pipe)) |
1f7247c0 | 2249 | intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe); |
5b3a856b | 2250 | |
40da17c2 | 2251 | if (de_iir & DE_PIPE_CRC_DONE(pipe)) |
91d14251 | 2252 | i9xx_pipe_crc_irq_handler(dev_priv, pipe); |
c008bc6e | 2253 | |
40da17c2 | 2254 | /* plane/pipes map 1:1 on ilk+ */ |
5251f04e | 2255 | if (de_iir & DE_PLANE_FLIP_DONE(pipe)) |
51cbaf01 | 2256 | intel_finish_page_flip_cs(dev_priv, pipe); |
c008bc6e PZ |
2257 | } |
2258 | ||
2259 | /* check event from PCH */ | |
2260 | if (de_iir & DE_PCH_EVENT) { | |
2261 | u32 pch_iir = I915_READ(SDEIIR); | |
2262 | ||
91d14251 TU |
2263 | if (HAS_PCH_CPT(dev_priv)) |
2264 | cpt_irq_handler(dev_priv, pch_iir); | |
c008bc6e | 2265 | else |
91d14251 | 2266 | ibx_irq_handler(dev_priv, pch_iir); |
c008bc6e PZ |
2267 | |
2268 | /* should clear PCH hotplug event before clear CPU irq */ | |
2269 | I915_WRITE(SDEIIR, pch_iir); | |
2270 | } | |
2271 | ||
91d14251 TU |
2272 | if (IS_GEN5(dev_priv) && de_iir & DE_PCU_EVENT) |
2273 | ironlake_rps_change_irq_handler(dev_priv); | |
c008bc6e PZ |
2274 | } |
2275 | ||
91d14251 TU |
2276 | static void ivb_display_irq_handler(struct drm_i915_private *dev_priv, |
2277 | u32 de_iir) | |
9719fb98 | 2278 | { |
07d27e20 | 2279 | enum pipe pipe; |
23bb4cb5 VS |
2280 | u32 hotplug_trigger = de_iir & DE_DP_A_HOTPLUG_IVB; |
2281 | ||
40e56410 | 2282 | if (hotplug_trigger) |
91d14251 | 2283 | ilk_hpd_irq_handler(dev_priv, hotplug_trigger, hpd_ivb); |
9719fb98 PZ |
2284 | |
2285 | if (de_iir & DE_ERR_INT_IVB) | |
91d14251 | 2286 | ivb_err_int_handler(dev_priv); |
9719fb98 PZ |
2287 | |
2288 | if (de_iir & DE_AUX_CHANNEL_A_IVB) | |
91d14251 | 2289 | dp_aux_irq_handler(dev_priv); |
9719fb98 PZ |
2290 | |
2291 | if (de_iir & DE_GSE_IVB) | |
91d14251 | 2292 | intel_opregion_asle_intr(dev_priv); |
9719fb98 | 2293 | |
055e393f | 2294 | for_each_pipe(dev_priv, pipe) { |
5a21b665 DV |
2295 | if (de_iir & (DE_PIPE_VBLANK_IVB(pipe)) && |
2296 | intel_pipe_handle_vblank(dev_priv, pipe)) | |
2297 | intel_check_page_flip(dev_priv, pipe); | |
40da17c2 DV |
2298 | |
2299 | /* plane/pipes map 1:1 on ilk+ */ | |
5251f04e | 2300 | if (de_iir & DE_PLANE_FLIP_DONE_IVB(pipe)) |
51cbaf01 | 2301 | intel_finish_page_flip_cs(dev_priv, pipe); |
9719fb98 PZ |
2302 | } |
2303 | ||
2304 | /* check event from PCH */ | |
91d14251 | 2305 | if (!HAS_PCH_NOP(dev_priv) && (de_iir & DE_PCH_EVENT_IVB)) { |
9719fb98 PZ |
2306 | u32 pch_iir = I915_READ(SDEIIR); |
2307 | ||
91d14251 | 2308 | cpt_irq_handler(dev_priv, pch_iir); |
9719fb98 PZ |
2309 | |
2310 | /* clear PCH hotplug event before clear CPU irq */ | |
2311 | I915_WRITE(SDEIIR, pch_iir); | |
2312 | } | |
2313 | } | |
2314 | ||
72c90f62 OM |
2315 | /* |
2316 | * To handle irqs with the minimum potential races with fresh interrupts, we: | |
2317 | * 1 - Disable Master Interrupt Control. | |
2318 | * 2 - Find the source(s) of the interrupt. | |
2319 | * 3 - Clear the Interrupt Identity bits (IIR). | |
2320 | * 4 - Process the interrupt(s) that had bits set in the IIRs. | |
2321 | * 5 - Re-enable Master Interrupt Control. | |
2322 | */ | |
f1af8fc1 | 2323 | static irqreturn_t ironlake_irq_handler(int irq, void *arg) |
b1f14ad0 | 2324 | { |
45a83f84 | 2325 | struct drm_device *dev = arg; |
fac5e23e | 2326 | struct drm_i915_private *dev_priv = to_i915(dev); |
f1af8fc1 | 2327 | u32 de_iir, gt_iir, de_ier, sde_ier = 0; |
0e43406b | 2328 | irqreturn_t ret = IRQ_NONE; |
b1f14ad0 | 2329 | |
2dd2a883 ID |
2330 | if (!intel_irqs_enabled(dev_priv)) |
2331 | return IRQ_NONE; | |
2332 | ||
1f814dac ID |
2333 | /* IRQs are synced during runtime_suspend, we don't require a wakeref */ |
2334 | disable_rpm_wakeref_asserts(dev_priv); | |
2335 | ||
b1f14ad0 JB |
2336 | /* disable master interrupt before clearing iir */ |
2337 | de_ier = I915_READ(DEIER); | |
2338 | I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL); | |
23a78516 | 2339 | POSTING_READ(DEIER); |
b1f14ad0 | 2340 | |
44498aea PZ |
2341 | /* Disable south interrupts. We'll only write to SDEIIR once, so further |
2342 | * interrupts will will be stored on its back queue, and then we'll be | |
2343 | * able to process them after we restore SDEIER (as soon as we restore | |
2344 | * it, we'll get an interrupt if SDEIIR still has something to process | |
2345 | * due to its back queue). */ | |
91d14251 | 2346 | if (!HAS_PCH_NOP(dev_priv)) { |
ab5c608b BW |
2347 | sde_ier = I915_READ(SDEIER); |
2348 | I915_WRITE(SDEIER, 0); | |
2349 | POSTING_READ(SDEIER); | |
2350 | } | |
44498aea | 2351 | |
72c90f62 OM |
2352 | /* Find, clear, then process each source of interrupt */ |
2353 | ||
b1f14ad0 | 2354 | gt_iir = I915_READ(GTIIR); |
0e43406b | 2355 | if (gt_iir) { |
72c90f62 OM |
2356 | I915_WRITE(GTIIR, gt_iir); |
2357 | ret = IRQ_HANDLED; | |
91d14251 | 2358 | if (INTEL_GEN(dev_priv) >= 6) |
261e40b8 | 2359 | snb_gt_irq_handler(dev_priv, gt_iir); |
d8fc8a47 | 2360 | else |
261e40b8 | 2361 | ilk_gt_irq_handler(dev_priv, gt_iir); |
b1f14ad0 JB |
2362 | } |
2363 | ||
0e43406b CW |
2364 | de_iir = I915_READ(DEIIR); |
2365 | if (de_iir) { | |
72c90f62 OM |
2366 | I915_WRITE(DEIIR, de_iir); |
2367 | ret = IRQ_HANDLED; | |
91d14251 TU |
2368 | if (INTEL_GEN(dev_priv) >= 7) |
2369 | ivb_display_irq_handler(dev_priv, de_iir); | |
f1af8fc1 | 2370 | else |
91d14251 | 2371 | ilk_display_irq_handler(dev_priv, de_iir); |
b1f14ad0 JB |
2372 | } |
2373 | ||
91d14251 | 2374 | if (INTEL_GEN(dev_priv) >= 6) { |
f1af8fc1 PZ |
2375 | u32 pm_iir = I915_READ(GEN6_PMIIR); |
2376 | if (pm_iir) { | |
f1af8fc1 PZ |
2377 | I915_WRITE(GEN6_PMIIR, pm_iir); |
2378 | ret = IRQ_HANDLED; | |
72c90f62 | 2379 | gen6_rps_irq_handler(dev_priv, pm_iir); |
f1af8fc1 | 2380 | } |
0e43406b | 2381 | } |
b1f14ad0 | 2382 | |
b1f14ad0 JB |
2383 | I915_WRITE(DEIER, de_ier); |
2384 | POSTING_READ(DEIER); | |
91d14251 | 2385 | if (!HAS_PCH_NOP(dev_priv)) { |
ab5c608b BW |
2386 | I915_WRITE(SDEIER, sde_ier); |
2387 | POSTING_READ(SDEIER); | |
2388 | } | |
b1f14ad0 | 2389 | |
1f814dac ID |
2390 | /* IRQs are synced during runtime_suspend, we don't require a wakeref */ |
2391 | enable_rpm_wakeref_asserts(dev_priv); | |
2392 | ||
b1f14ad0 JB |
2393 | return ret; |
2394 | } | |
2395 | ||
91d14251 TU |
2396 | static void bxt_hpd_irq_handler(struct drm_i915_private *dev_priv, |
2397 | u32 hotplug_trigger, | |
40e56410 | 2398 | const u32 hpd[HPD_NUM_PINS]) |
d04a492d | 2399 | { |
cebd87a0 | 2400 | u32 dig_hotplug_reg, pin_mask = 0, long_mask = 0; |
d04a492d | 2401 | |
a52bb15b VS |
2402 | dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG); |
2403 | I915_WRITE(PCH_PORT_HOTPLUG, dig_hotplug_reg); | |
d04a492d | 2404 | |
cebd87a0 | 2405 | intel_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger, |
40e56410 | 2406 | dig_hotplug_reg, hpd, |
cebd87a0 | 2407 | bxt_port_hotplug_long_detect); |
40e56410 | 2408 | |
91d14251 | 2409 | intel_hpd_irq_handler(dev_priv, pin_mask, long_mask); |
d04a492d SS |
2410 | } |
2411 | ||
f11a0f46 TU |
2412 | static irqreturn_t |
2413 | gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl) | |
abd58f01 | 2414 | { |
abd58f01 | 2415 | irqreturn_t ret = IRQ_NONE; |
f11a0f46 | 2416 | u32 iir; |
c42664cc | 2417 | enum pipe pipe; |
88e04703 | 2418 | |
abd58f01 | 2419 | if (master_ctl & GEN8_DE_MISC_IRQ) { |
e32192e1 TU |
2420 | iir = I915_READ(GEN8_DE_MISC_IIR); |
2421 | if (iir) { | |
2422 | I915_WRITE(GEN8_DE_MISC_IIR, iir); | |
abd58f01 | 2423 | ret = IRQ_HANDLED; |
e32192e1 | 2424 | if (iir & GEN8_DE_MISC_GSE) |
91d14251 | 2425 | intel_opregion_asle_intr(dev_priv); |
38cc46d7 OM |
2426 | else |
2427 | DRM_ERROR("Unexpected DE Misc interrupt\n"); | |
abd58f01 | 2428 | } |
38cc46d7 OM |
2429 | else |
2430 | DRM_ERROR("The master control interrupt lied (DE MISC)!\n"); | |
abd58f01 BW |
2431 | } |
2432 | ||
6d766f02 | 2433 | if (master_ctl & GEN8_DE_PORT_IRQ) { |
e32192e1 TU |
2434 | iir = I915_READ(GEN8_DE_PORT_IIR); |
2435 | if (iir) { | |
2436 | u32 tmp_mask; | |
d04a492d | 2437 | bool found = false; |
cebd87a0 | 2438 | |
e32192e1 | 2439 | I915_WRITE(GEN8_DE_PORT_IIR, iir); |
6d766f02 | 2440 | ret = IRQ_HANDLED; |
88e04703 | 2441 | |
e32192e1 TU |
2442 | tmp_mask = GEN8_AUX_CHANNEL_A; |
2443 | if (INTEL_INFO(dev_priv)->gen >= 9) | |
2444 | tmp_mask |= GEN9_AUX_CHANNEL_B | | |
2445 | GEN9_AUX_CHANNEL_C | | |
2446 | GEN9_AUX_CHANNEL_D; | |
2447 | ||
2448 | if (iir & tmp_mask) { | |
91d14251 | 2449 | dp_aux_irq_handler(dev_priv); |
d04a492d SS |
2450 | found = true; |
2451 | } | |
2452 | ||
cc3f90f0 | 2453 | if (IS_GEN9_LP(dev_priv)) { |
e32192e1 TU |
2454 | tmp_mask = iir & BXT_DE_PORT_HOTPLUG_MASK; |
2455 | if (tmp_mask) { | |
91d14251 TU |
2456 | bxt_hpd_irq_handler(dev_priv, tmp_mask, |
2457 | hpd_bxt); | |
e32192e1 TU |
2458 | found = true; |
2459 | } | |
2460 | } else if (IS_BROADWELL(dev_priv)) { | |
2461 | tmp_mask = iir & GEN8_PORT_DP_A_HOTPLUG; | |
2462 | if (tmp_mask) { | |
91d14251 TU |
2463 | ilk_hpd_irq_handler(dev_priv, |
2464 | tmp_mask, hpd_bdw); | |
e32192e1 TU |
2465 | found = true; |
2466 | } | |
d04a492d SS |
2467 | } |
2468 | ||
cc3f90f0 | 2469 | if (IS_GEN9_LP(dev_priv) && (iir & BXT_DE_PORT_GMBUS)) { |
91d14251 | 2470 | gmbus_irq_handler(dev_priv); |
9e63743e SS |
2471 | found = true; |
2472 | } | |
2473 | ||
d04a492d | 2474 | if (!found) |
38cc46d7 | 2475 | DRM_ERROR("Unexpected DE Port interrupt\n"); |
6d766f02 | 2476 | } |
38cc46d7 OM |
2477 | else |
2478 | DRM_ERROR("The master control interrupt lied (DE PORT)!\n"); | |
6d766f02 DV |
2479 | } |
2480 | ||
055e393f | 2481 | for_each_pipe(dev_priv, pipe) { |
e32192e1 | 2482 | u32 flip_done, fault_errors; |
abd58f01 | 2483 | |
c42664cc DV |
2484 | if (!(master_ctl & GEN8_DE_PIPE_IRQ(pipe))) |
2485 | continue; | |
abd58f01 | 2486 | |
e32192e1 TU |
2487 | iir = I915_READ(GEN8_DE_PIPE_IIR(pipe)); |
2488 | if (!iir) { | |
2489 | DRM_ERROR("The master control interrupt lied (DE PIPE)!\n"); | |
2490 | continue; | |
2491 | } | |
770de83d | 2492 | |
e32192e1 TU |
2493 | ret = IRQ_HANDLED; |
2494 | I915_WRITE(GEN8_DE_PIPE_IIR(pipe), iir); | |
38cc46d7 | 2495 | |
5a21b665 DV |
2496 | if (iir & GEN8_PIPE_VBLANK && |
2497 | intel_pipe_handle_vblank(dev_priv, pipe)) | |
2498 | intel_check_page_flip(dev_priv, pipe); | |
770de83d | 2499 | |
e32192e1 TU |
2500 | flip_done = iir; |
2501 | if (INTEL_INFO(dev_priv)->gen >= 9) | |
2502 | flip_done &= GEN9_PIPE_PLANE1_FLIP_DONE; | |
2503 | else | |
2504 | flip_done &= GEN8_PIPE_PRIMARY_FLIP_DONE; | |
38cc46d7 | 2505 | |
5251f04e | 2506 | if (flip_done) |
51cbaf01 | 2507 | intel_finish_page_flip_cs(dev_priv, pipe); |
38cc46d7 | 2508 | |
e32192e1 | 2509 | if (iir & GEN8_PIPE_CDCLK_CRC_DONE) |
91d14251 | 2510 | hsw_pipe_crc_irq_handler(dev_priv, pipe); |
38cc46d7 | 2511 | |
e32192e1 TU |
2512 | if (iir & GEN8_PIPE_FIFO_UNDERRUN) |
2513 | intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe); | |
770de83d | 2514 | |
e32192e1 TU |
2515 | fault_errors = iir; |
2516 | if (INTEL_INFO(dev_priv)->gen >= 9) | |
2517 | fault_errors &= GEN9_DE_PIPE_IRQ_FAULT_ERRORS; | |
2518 | else | |
2519 | fault_errors &= GEN8_DE_PIPE_IRQ_FAULT_ERRORS; | |
770de83d | 2520 | |
e32192e1 | 2521 | if (fault_errors) |
1353ec38 | 2522 | DRM_ERROR("Fault errors on pipe %c: 0x%08x\n", |
e32192e1 TU |
2523 | pipe_name(pipe), |
2524 | fault_errors); | |
abd58f01 BW |
2525 | } |
2526 | ||
91d14251 | 2527 | if (HAS_PCH_SPLIT(dev_priv) && !HAS_PCH_NOP(dev_priv) && |
266ea3d9 | 2528 | master_ctl & GEN8_DE_PCH_IRQ) { |
92d03a80 DV |
2529 | /* |
2530 | * FIXME(BDW): Assume for now that the new interrupt handling | |
2531 | * scheme also closed the SDE interrupt handling race we've seen | |
2532 | * on older pch-split platforms. But this needs testing. | |
2533 | */ | |
e32192e1 TU |
2534 | iir = I915_READ(SDEIIR); |
2535 | if (iir) { | |
2536 | I915_WRITE(SDEIIR, iir); | |
92d03a80 | 2537 | ret = IRQ_HANDLED; |
6dbf30ce | 2538 | |
7b22b8c4 RV |
2539 | if (HAS_PCH_SPT(dev_priv) || HAS_PCH_KBP(dev_priv) || |
2540 | HAS_PCH_CNP(dev_priv)) | |
91d14251 | 2541 | spt_irq_handler(dev_priv, iir); |
6dbf30ce | 2542 | else |
91d14251 | 2543 | cpt_irq_handler(dev_priv, iir); |
2dfb0b81 JN |
2544 | } else { |
2545 | /* | |
2546 | * Like on previous PCH there seems to be something | |
2547 | * fishy going on with forwarding PCH interrupts. | |
2548 | */ | |
2549 | DRM_DEBUG_DRIVER("The master control interrupt lied (SDE)!\n"); | |
2550 | } | |
92d03a80 DV |
2551 | } |
2552 | ||
f11a0f46 TU |
2553 | return ret; |
2554 | } | |
2555 | ||
2556 | static irqreturn_t gen8_irq_handler(int irq, void *arg) | |
2557 | { | |
2558 | struct drm_device *dev = arg; | |
fac5e23e | 2559 | struct drm_i915_private *dev_priv = to_i915(dev); |
f11a0f46 | 2560 | u32 master_ctl; |
e30e251a | 2561 | u32 gt_iir[4] = {}; |
f11a0f46 TU |
2562 | irqreturn_t ret; |
2563 | ||
2564 | if (!intel_irqs_enabled(dev_priv)) | |
2565 | return IRQ_NONE; | |
2566 | ||
2567 | master_ctl = I915_READ_FW(GEN8_MASTER_IRQ); | |
2568 | master_ctl &= ~GEN8_MASTER_IRQ_CONTROL; | |
2569 | if (!master_ctl) | |
2570 | return IRQ_NONE; | |
2571 | ||
2572 | I915_WRITE_FW(GEN8_MASTER_IRQ, 0); | |
2573 | ||
2574 | /* IRQs are synced during runtime_suspend, we don't require a wakeref */ | |
2575 | disable_rpm_wakeref_asserts(dev_priv); | |
2576 | ||
2577 | /* Find, clear, then process each source of interrupt */ | |
e30e251a VS |
2578 | ret = gen8_gt_irq_ack(dev_priv, master_ctl, gt_iir); |
2579 | gen8_gt_irq_handler(dev_priv, gt_iir); | |
f11a0f46 TU |
2580 | ret |= gen8_de_irq_handler(dev_priv, master_ctl); |
2581 | ||
cb0d205e CW |
2582 | I915_WRITE_FW(GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL); |
2583 | POSTING_READ_FW(GEN8_MASTER_IRQ); | |
abd58f01 | 2584 | |
1f814dac ID |
2585 | enable_rpm_wakeref_asserts(dev_priv); |
2586 | ||
abd58f01 BW |
2587 | return ret; |
2588 | } | |
2589 | ||
36703e79 CW |
2590 | struct wedge_me { |
2591 | struct delayed_work work; | |
2592 | struct drm_i915_private *i915; | |
2593 | const char *name; | |
2594 | }; | |
2595 | ||
2596 | static void wedge_me(struct work_struct *work) | |
2597 | { | |
2598 | struct wedge_me *w = container_of(work, typeof(*w), work.work); | |
2599 | ||
2600 | dev_err(w->i915->drm.dev, | |
2601 | "%s timed out, cancelling all in-flight rendering.\n", | |
2602 | w->name); | |
2603 | i915_gem_set_wedged(w->i915); | |
2604 | } | |
2605 | ||
2606 | static void __init_wedge(struct wedge_me *w, | |
2607 | struct drm_i915_private *i915, | |
2608 | long timeout, | |
2609 | const char *name) | |
2610 | { | |
2611 | w->i915 = i915; | |
2612 | w->name = name; | |
2613 | ||
2614 | INIT_DELAYED_WORK_ONSTACK(&w->work, wedge_me); | |
2615 | schedule_delayed_work(&w->work, timeout); | |
2616 | } | |
2617 | ||
2618 | static void __fini_wedge(struct wedge_me *w) | |
2619 | { | |
2620 | cancel_delayed_work_sync(&w->work); | |
2621 | destroy_delayed_work_on_stack(&w->work); | |
2622 | w->i915 = NULL; | |
2623 | } | |
2624 | ||
2625 | #define i915_wedge_on_timeout(W, DEV, TIMEOUT) \ | |
2626 | for (__init_wedge((W), (DEV), (TIMEOUT), __func__); \ | |
2627 | (W)->i915; \ | |
2628 | __fini_wedge((W))) | |
2629 | ||
8a905236 | 2630 | /** |
d5367307 | 2631 | * i915_reset_device - do process context error handling work |
14bb2c11 | 2632 | * @dev_priv: i915 device private |
8a905236 JB |
2633 | * |
2634 | * Fire an error uevent so userspace can see that a hang or error | |
2635 | * was detected. | |
2636 | */ | |
d5367307 | 2637 | static void i915_reset_device(struct drm_i915_private *dev_priv) |
8a905236 | 2638 | { |
91c8a326 | 2639 | struct kobject *kobj = &dev_priv->drm.primary->kdev->kobj; |
cce723ed BW |
2640 | char *error_event[] = { I915_ERROR_UEVENT "=1", NULL }; |
2641 | char *reset_event[] = { I915_RESET_UEVENT "=1", NULL }; | |
2642 | char *reset_done_event[] = { I915_ERROR_UEVENT "=0", NULL }; | |
36703e79 | 2643 | struct wedge_me w; |
8a905236 | 2644 | |
c033666a | 2645 | kobject_uevent_env(kobj, KOBJ_CHANGE, error_event); |
f316a42c | 2646 | |
8af29b0c CW |
2647 | DRM_DEBUG_DRIVER("resetting chip\n"); |
2648 | kobject_uevent_env(kobj, KOBJ_CHANGE, reset_event); | |
2649 | ||
36703e79 CW |
2650 | /* Use a watchdog to ensure that our reset completes */ |
2651 | i915_wedge_on_timeout(&w, dev_priv, 5*HZ) { | |
2652 | intel_prepare_reset(dev_priv); | |
7514747d | 2653 | |
36703e79 CW |
2654 | /* Signal that locked waiters should reset the GPU */ |
2655 | set_bit(I915_RESET_HANDOFF, &dev_priv->gpu_error.flags); | |
2656 | wake_up_all(&dev_priv->gpu_error.wait_queue); | |
8c185eca | 2657 | |
36703e79 CW |
2658 | /* Wait for anyone holding the lock to wakeup, without |
2659 | * blocking indefinitely on struct_mutex. | |
780f262a | 2660 | */ |
36703e79 CW |
2661 | do { |
2662 | if (mutex_trylock(&dev_priv->drm.struct_mutex)) { | |
2663 | i915_reset(dev_priv); | |
2664 | mutex_unlock(&dev_priv->drm.struct_mutex); | |
2665 | } | |
2666 | } while (wait_on_bit_timeout(&dev_priv->gpu_error.flags, | |
2667 | I915_RESET_HANDOFF, | |
2668 | TASK_UNINTERRUPTIBLE, | |
2669 | 1)); | |
17e1df07 | 2670 | |
36703e79 CW |
2671 | intel_finish_reset(dev_priv); |
2672 | } | |
f454c694 | 2673 | |
780f262a | 2674 | if (!test_bit(I915_WEDGED, &dev_priv->gpu_error.flags)) |
8af29b0c CW |
2675 | kobject_uevent_env(kobj, |
2676 | KOBJ_CHANGE, reset_done_event); | |
8a905236 JB |
2677 | } |
2678 | ||
d636951e BW |
2679 | static inline void |
2680 | i915_err_print_instdone(struct drm_i915_private *dev_priv, | |
2681 | struct intel_instdone *instdone) | |
2682 | { | |
f9e61372 BW |
2683 | int slice; |
2684 | int subslice; | |
2685 | ||
d636951e BW |
2686 | pr_err(" INSTDONE: 0x%08x\n", instdone->instdone); |
2687 | ||
2688 | if (INTEL_GEN(dev_priv) <= 3) | |
2689 | return; | |
2690 | ||
2691 | pr_err(" SC_INSTDONE: 0x%08x\n", instdone->slice_common); | |
2692 | ||
2693 | if (INTEL_GEN(dev_priv) <= 6) | |
2694 | return; | |
2695 | ||
f9e61372 BW |
2696 | for_each_instdone_slice_subslice(dev_priv, slice, subslice) |
2697 | pr_err(" SAMPLER_INSTDONE[%d][%d]: 0x%08x\n", | |
2698 | slice, subslice, instdone->sampler[slice][subslice]); | |
2699 | ||
2700 | for_each_instdone_slice_subslice(dev_priv, slice, subslice) | |
2701 | pr_err(" ROW_INSTDONE[%d][%d]: 0x%08x\n", | |
2702 | slice, subslice, instdone->row[slice][subslice]); | |
d636951e BW |
2703 | } |
2704 | ||
eaa14c24 | 2705 | static void i915_clear_error_registers(struct drm_i915_private *dev_priv) |
8a905236 | 2706 | { |
eaa14c24 | 2707 | u32 eir; |
8a905236 | 2708 | |
eaa14c24 CW |
2709 | if (!IS_GEN2(dev_priv)) |
2710 | I915_WRITE(PGTBL_ER, I915_READ(PGTBL_ER)); | |
8a905236 | 2711 | |
eaa14c24 CW |
2712 | if (INTEL_GEN(dev_priv) < 4) |
2713 | I915_WRITE(IPEIR, I915_READ(IPEIR)); | |
2714 | else | |
2715 | I915_WRITE(IPEIR_I965, I915_READ(IPEIR_I965)); | |
8a905236 | 2716 | |
eaa14c24 | 2717 | I915_WRITE(EIR, I915_READ(EIR)); |
8a905236 JB |
2718 | eir = I915_READ(EIR); |
2719 | if (eir) { | |
2720 | /* | |
2721 | * some errors might have become stuck, | |
2722 | * mask them. | |
2723 | */ | |
eaa14c24 | 2724 | DRM_DEBUG_DRIVER("EIR stuck: 0x%08x, masking\n", eir); |
8a905236 JB |
2725 | I915_WRITE(EMR, I915_READ(EMR) | eir); |
2726 | I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT); | |
2727 | } | |
35aed2e6 CW |
2728 | } |
2729 | ||
2730 | /** | |
b8d24a06 | 2731 | * i915_handle_error - handle a gpu error |
14bb2c11 | 2732 | * @dev_priv: i915 device private |
14b730fc | 2733 | * @engine_mask: mask representing engines that are hung |
87c390b6 MT |
2734 | * @fmt: Error message format string |
2735 | * | |
aafd8581 | 2736 | * Do some basic checking of register state at error time and |
35aed2e6 CW |
2737 | * dump it to the syslog. Also call i915_capture_error_state() to make |
2738 | * sure we get a record and make it available in debugfs. Fire a uevent | |
2739 | * so userspace knows something bad happened (should trigger collection | |
2740 | * of a ring dump etc.). | |
2741 | */ | |
c033666a CW |
2742 | void i915_handle_error(struct drm_i915_private *dev_priv, |
2743 | u32 engine_mask, | |
58174462 | 2744 | const char *fmt, ...) |
35aed2e6 | 2745 | { |
142bc7d9 MT |
2746 | struct intel_engine_cs *engine; |
2747 | unsigned int tmp; | |
58174462 MK |
2748 | va_list args; |
2749 | char error_msg[80]; | |
35aed2e6 | 2750 | |
58174462 MK |
2751 | va_start(args, fmt); |
2752 | vscnprintf(error_msg, sizeof(error_msg), fmt, args); | |
2753 | va_end(args); | |
2754 | ||
1604a86d CW |
2755 | /* |
2756 | * In most cases it's guaranteed that we get here with an RPM | |
2757 | * reference held, for example because there is a pending GPU | |
2758 | * request that won't finish until the reset is done. This | |
2759 | * isn't the case at least when we get here by doing a | |
2760 | * simulated reset via debugfs, so get an RPM reference. | |
2761 | */ | |
2762 | intel_runtime_pm_get(dev_priv); | |
2763 | ||
c033666a | 2764 | i915_capture_error_state(dev_priv, engine_mask, error_msg); |
eaa14c24 | 2765 | i915_clear_error_registers(dev_priv); |
8a905236 | 2766 | |
142bc7d9 MT |
2767 | /* |
2768 | * Try engine reset when available. We fall back to full reset if | |
2769 | * single reset fails. | |
2770 | */ | |
2771 | if (intel_has_reset_engine(dev_priv)) { | |
2772 | for_each_engine_masked(engine, dev_priv, engine_mask, tmp) { | |
2773 | BUILD_BUG_ON(I915_RESET_HANDOFF >= I915_RESET_ENGINE); | |
2774 | if (test_and_set_bit(I915_RESET_ENGINE + engine->id, | |
2775 | &dev_priv->gpu_error.flags)) | |
2776 | continue; | |
2777 | ||
2778 | if (i915_reset_engine(engine) == 0) | |
2779 | engine_mask &= ~intel_engine_flag(engine); | |
2780 | ||
2781 | clear_bit(I915_RESET_ENGINE + engine->id, | |
2782 | &dev_priv->gpu_error.flags); | |
2783 | wake_up_bit(&dev_priv->gpu_error.flags, | |
2784 | I915_RESET_ENGINE + engine->id); | |
2785 | } | |
2786 | } | |
2787 | ||
8af29b0c | 2788 | if (!engine_mask) |
1604a86d | 2789 | goto out; |
ba1234d1 | 2790 | |
142bc7d9 | 2791 | /* Full reset needs the mutex, stop any other user trying to do so. */ |
d5367307 CW |
2792 | if (test_and_set_bit(I915_RESET_BACKOFF, &dev_priv->gpu_error.flags)) { |
2793 | wait_event(dev_priv->gpu_error.reset_queue, | |
2794 | !test_bit(I915_RESET_BACKOFF, | |
2795 | &dev_priv->gpu_error.flags)); | |
1604a86d | 2796 | goto out; |
d5367307 CW |
2797 | } |
2798 | ||
142bc7d9 MT |
2799 | /* Prevent any other reset-engine attempt. */ |
2800 | for_each_engine(engine, dev_priv, tmp) { | |
2801 | while (test_and_set_bit(I915_RESET_ENGINE + engine->id, | |
2802 | &dev_priv->gpu_error.flags)) | |
2803 | wait_on_bit(&dev_priv->gpu_error.flags, | |
2804 | I915_RESET_ENGINE + engine->id, | |
2805 | TASK_UNINTERRUPTIBLE); | |
2806 | } | |
2807 | ||
d5367307 | 2808 | i915_reset_device(dev_priv); |
8af29b0c | 2809 | |
142bc7d9 MT |
2810 | for_each_engine(engine, dev_priv, tmp) { |
2811 | clear_bit(I915_RESET_ENGINE + engine->id, | |
2812 | &dev_priv->gpu_error.flags); | |
2813 | } | |
2814 | ||
d5367307 CW |
2815 | clear_bit(I915_RESET_BACKOFF, &dev_priv->gpu_error.flags); |
2816 | wake_up_all(&dev_priv->gpu_error.reset_queue); | |
1604a86d CW |
2817 | |
2818 | out: | |
2819 | intel_runtime_pm_put(dev_priv); | |
8a905236 JB |
2820 | } |
2821 | ||
42f52ef8 KP |
2822 | /* Called from drm generic code, passed 'crtc' which |
2823 | * we use as a pipe index | |
2824 | */ | |
86e83e35 | 2825 | static int i8xx_enable_vblank(struct drm_device *dev, unsigned int pipe) |
0a3e67a4 | 2826 | { |
fac5e23e | 2827 | struct drm_i915_private *dev_priv = to_i915(dev); |
e9d21d7f | 2828 | unsigned long irqflags; |
71e0ffa5 | 2829 | |
1ec14ad3 | 2830 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); |
86e83e35 | 2831 | i915_enable_pipestat(dev_priv, pipe, PIPE_VBLANK_INTERRUPT_STATUS); |
1ec14ad3 | 2832 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
8692d00e | 2833 | |
0a3e67a4 JB |
2834 | return 0; |
2835 | } | |
2836 | ||
86e83e35 | 2837 | static int i965_enable_vblank(struct drm_device *dev, unsigned int pipe) |
f796cf8f | 2838 | { |
fac5e23e | 2839 | struct drm_i915_private *dev_priv = to_i915(dev); |
f796cf8f JB |
2840 | unsigned long irqflags; |
2841 | ||
f796cf8f | 2842 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); |
86e83e35 CW |
2843 | i915_enable_pipestat(dev_priv, pipe, |
2844 | PIPE_START_VBLANK_INTERRUPT_STATUS); | |
b1f14ad0 JB |
2845 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
2846 | ||
2847 | return 0; | |
2848 | } | |
2849 | ||
86e83e35 | 2850 | static int ironlake_enable_vblank(struct drm_device *dev, unsigned int pipe) |
7e231dbe | 2851 | { |
fac5e23e | 2852 | struct drm_i915_private *dev_priv = to_i915(dev); |
7e231dbe | 2853 | unsigned long irqflags; |
55b8f2a7 | 2854 | uint32_t bit = INTEL_GEN(dev_priv) >= 7 ? |
86e83e35 | 2855 | DE_PIPE_VBLANK_IVB(pipe) : DE_PIPE_VBLANK(pipe); |
7e231dbe | 2856 | |
7e231dbe | 2857 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); |
86e83e35 | 2858 | ilk_enable_display_irq(dev_priv, bit); |
7e231dbe JB |
2859 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
2860 | ||
2861 | return 0; | |
2862 | } | |
2863 | ||
88e72717 | 2864 | static int gen8_enable_vblank(struct drm_device *dev, unsigned int pipe) |
abd58f01 | 2865 | { |
fac5e23e | 2866 | struct drm_i915_private *dev_priv = to_i915(dev); |
abd58f01 | 2867 | unsigned long irqflags; |
abd58f01 | 2868 | |
abd58f01 | 2869 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); |
013d3752 | 2870 | bdw_enable_pipe_irq(dev_priv, pipe, GEN8_PIPE_VBLANK); |
abd58f01 | 2871 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
013d3752 | 2872 | |
abd58f01 BW |
2873 | return 0; |
2874 | } | |
2875 | ||
42f52ef8 KP |
2876 | /* Called from drm generic code, passed 'crtc' which |
2877 | * we use as a pipe index | |
2878 | */ | |
86e83e35 | 2879 | static void i8xx_disable_vblank(struct drm_device *dev, unsigned int pipe) |
0a3e67a4 | 2880 | { |
fac5e23e | 2881 | struct drm_i915_private *dev_priv = to_i915(dev); |
e9d21d7f | 2882 | unsigned long irqflags; |
0a3e67a4 | 2883 | |
1ec14ad3 | 2884 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); |
86e83e35 | 2885 | i915_disable_pipestat(dev_priv, pipe, PIPE_VBLANK_INTERRUPT_STATUS); |
f796cf8f JB |
2886 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
2887 | } | |
2888 | ||
86e83e35 | 2889 | static void i965_disable_vblank(struct drm_device *dev, unsigned int pipe) |
f796cf8f | 2890 | { |
fac5e23e | 2891 | struct drm_i915_private *dev_priv = to_i915(dev); |
f796cf8f JB |
2892 | unsigned long irqflags; |
2893 | ||
2894 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | |
86e83e35 CW |
2895 | i915_disable_pipestat(dev_priv, pipe, |
2896 | PIPE_START_VBLANK_INTERRUPT_STATUS); | |
b1f14ad0 JB |
2897 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
2898 | } | |
2899 | ||
86e83e35 | 2900 | static void ironlake_disable_vblank(struct drm_device *dev, unsigned int pipe) |
7e231dbe | 2901 | { |
fac5e23e | 2902 | struct drm_i915_private *dev_priv = to_i915(dev); |
7e231dbe | 2903 | unsigned long irqflags; |
55b8f2a7 | 2904 | uint32_t bit = INTEL_GEN(dev_priv) >= 7 ? |
86e83e35 | 2905 | DE_PIPE_VBLANK_IVB(pipe) : DE_PIPE_VBLANK(pipe); |
7e231dbe JB |
2906 | |
2907 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | |
86e83e35 | 2908 | ilk_disable_display_irq(dev_priv, bit); |
7e231dbe JB |
2909 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
2910 | } | |
2911 | ||
88e72717 | 2912 | static void gen8_disable_vblank(struct drm_device *dev, unsigned int pipe) |
abd58f01 | 2913 | { |
fac5e23e | 2914 | struct drm_i915_private *dev_priv = to_i915(dev); |
abd58f01 | 2915 | unsigned long irqflags; |
abd58f01 | 2916 | |
abd58f01 | 2917 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); |
013d3752 | 2918 | bdw_disable_pipe_irq(dev_priv, pipe, GEN8_PIPE_VBLANK); |
abd58f01 BW |
2919 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
2920 | } | |
2921 | ||
b243f530 | 2922 | static void ibx_irq_reset(struct drm_i915_private *dev_priv) |
91738a95 | 2923 | { |
6e266956 | 2924 | if (HAS_PCH_NOP(dev_priv)) |
91738a95 PZ |
2925 | return; |
2926 | ||
f86f3fb0 | 2927 | GEN5_IRQ_RESET(SDE); |
105b122e | 2928 | |
6e266956 | 2929 | if (HAS_PCH_CPT(dev_priv) || HAS_PCH_LPT(dev_priv)) |
105b122e | 2930 | I915_WRITE(SERR_INT, 0xffffffff); |
622364b6 | 2931 | } |
105b122e | 2932 | |
622364b6 PZ |
2933 | /* |
2934 | * SDEIER is also touched by the interrupt handler to work around missed PCH | |
2935 | * interrupts. Hence we can't update it after the interrupt handler is enabled - | |
2936 | * instead we unconditionally enable all PCH interrupt sources here, but then | |
2937 | * only unmask them as needed with SDEIMR. | |
2938 | * | |
2939 | * This function needs to be called before interrupts are enabled. | |
2940 | */ | |
2941 | static void ibx_irq_pre_postinstall(struct drm_device *dev) | |
2942 | { | |
fac5e23e | 2943 | struct drm_i915_private *dev_priv = to_i915(dev); |
622364b6 | 2944 | |
6e266956 | 2945 | if (HAS_PCH_NOP(dev_priv)) |
622364b6 PZ |
2946 | return; |
2947 | ||
2948 | WARN_ON(I915_READ(SDEIER) != 0); | |
91738a95 PZ |
2949 | I915_WRITE(SDEIER, 0xffffffff); |
2950 | POSTING_READ(SDEIER); | |
2951 | } | |
2952 | ||
b243f530 | 2953 | static void gen5_gt_irq_reset(struct drm_i915_private *dev_priv) |
d18ea1b5 | 2954 | { |
f86f3fb0 | 2955 | GEN5_IRQ_RESET(GT); |
b243f530 | 2956 | if (INTEL_GEN(dev_priv) >= 6) |
f86f3fb0 | 2957 | GEN5_IRQ_RESET(GEN6_PM); |
d18ea1b5 DV |
2958 | } |
2959 | ||
70591a41 VS |
2960 | static void vlv_display_irq_reset(struct drm_i915_private *dev_priv) |
2961 | { | |
2962 | enum pipe pipe; | |
2963 | ||
71b8b41d VS |
2964 | if (IS_CHERRYVIEW(dev_priv)) |
2965 | I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK_CHV); | |
2966 | else | |
2967 | I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK); | |
2968 | ||
ad22d106 | 2969 | i915_hotplug_interrupt_update_locked(dev_priv, 0xffffffff, 0); |
70591a41 VS |
2970 | I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); |
2971 | ||
ad22d106 VS |
2972 | for_each_pipe(dev_priv, pipe) { |
2973 | I915_WRITE(PIPESTAT(pipe), | |
2974 | PIPE_FIFO_UNDERRUN_STATUS | | |
2975 | PIPESTAT_INT_STATUS_MASK); | |
2976 | dev_priv->pipestat_irq_mask[pipe] = 0; | |
2977 | } | |
70591a41 VS |
2978 | |
2979 | GEN5_IRQ_RESET(VLV_); | |
ad22d106 | 2980 | dev_priv->irq_mask = ~0; |
70591a41 VS |
2981 | } |
2982 | ||
8bb61306 VS |
2983 | static void vlv_display_irq_postinstall(struct drm_i915_private *dev_priv) |
2984 | { | |
2985 | u32 pipestat_mask; | |
9ab981f2 | 2986 | u32 enable_mask; |
8bb61306 VS |
2987 | enum pipe pipe; |
2988 | ||
8bb61306 VS |
2989 | pipestat_mask = PLANE_FLIP_DONE_INT_STATUS_VLV | |
2990 | PIPE_CRC_DONE_INTERRUPT_STATUS; | |
2991 | ||
2992 | i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS); | |
2993 | for_each_pipe(dev_priv, pipe) | |
2994 | i915_enable_pipestat(dev_priv, pipe, pipestat_mask); | |
2995 | ||
9ab981f2 VS |
2996 | enable_mask = I915_DISPLAY_PORT_INTERRUPT | |
2997 | I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | | |
ebf5f921 VS |
2998 | I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | |
2999 | I915_LPE_PIPE_A_INTERRUPT | | |
3000 | I915_LPE_PIPE_B_INTERRUPT; | |
3001 | ||
8bb61306 | 3002 | if (IS_CHERRYVIEW(dev_priv)) |
ebf5f921 VS |
3003 | enable_mask |= I915_DISPLAY_PIPE_C_EVENT_INTERRUPT | |
3004 | I915_LPE_PIPE_C_INTERRUPT; | |
6b7eafc1 VS |
3005 | |
3006 | WARN_ON(dev_priv->irq_mask != ~0); | |
3007 | ||
9ab981f2 VS |
3008 | dev_priv->irq_mask = ~enable_mask; |
3009 | ||
3010 | GEN5_IRQ_INIT(VLV_, dev_priv->irq_mask, enable_mask); | |
8bb61306 VS |
3011 | } |
3012 | ||
3013 | /* drm_dma.h hooks | |
3014 | */ | |
3015 | static void ironlake_irq_reset(struct drm_device *dev) | |
3016 | { | |
fac5e23e | 3017 | struct drm_i915_private *dev_priv = to_i915(dev); |
8bb61306 VS |
3018 | |
3019 | I915_WRITE(HWSTAM, 0xffffffff); | |
3020 | ||
3021 | GEN5_IRQ_RESET(DE); | |
5db94019 | 3022 | if (IS_GEN7(dev_priv)) |
8bb61306 VS |
3023 | I915_WRITE(GEN7_ERR_INT, 0xffffffff); |
3024 | ||
b243f530 | 3025 | gen5_gt_irq_reset(dev_priv); |
8bb61306 | 3026 | |
b243f530 | 3027 | ibx_irq_reset(dev_priv); |
8bb61306 VS |
3028 | } |
3029 | ||
7e231dbe JB |
3030 | static void valleyview_irq_preinstall(struct drm_device *dev) |
3031 | { | |
fac5e23e | 3032 | struct drm_i915_private *dev_priv = to_i915(dev); |
7e231dbe | 3033 | |
34c7b8a7 VS |
3034 | I915_WRITE(VLV_MASTER_IER, 0); |
3035 | POSTING_READ(VLV_MASTER_IER); | |
3036 | ||
b243f530 | 3037 | gen5_gt_irq_reset(dev_priv); |
7e231dbe | 3038 | |
ad22d106 | 3039 | spin_lock_irq(&dev_priv->irq_lock); |
9918271e VS |
3040 | if (dev_priv->display_irqs_enabled) |
3041 | vlv_display_irq_reset(dev_priv); | |
ad22d106 | 3042 | spin_unlock_irq(&dev_priv->irq_lock); |
7e231dbe JB |
3043 | } |
3044 | ||
d6e3cca3 DV |
3045 | static void gen8_gt_irq_reset(struct drm_i915_private *dev_priv) |
3046 | { | |
3047 | GEN8_IRQ_RESET_NDX(GT, 0); | |
3048 | GEN8_IRQ_RESET_NDX(GT, 1); | |
3049 | GEN8_IRQ_RESET_NDX(GT, 2); | |
3050 | GEN8_IRQ_RESET_NDX(GT, 3); | |
3051 | } | |
3052 | ||
823f6b38 | 3053 | static void gen8_irq_reset(struct drm_device *dev) |
abd58f01 | 3054 | { |
fac5e23e | 3055 | struct drm_i915_private *dev_priv = to_i915(dev); |
abd58f01 BW |
3056 | int pipe; |
3057 | ||
abd58f01 BW |
3058 | I915_WRITE(GEN8_MASTER_IRQ, 0); |
3059 | POSTING_READ(GEN8_MASTER_IRQ); | |
3060 | ||
d6e3cca3 | 3061 | gen8_gt_irq_reset(dev_priv); |
abd58f01 | 3062 | |
055e393f | 3063 | for_each_pipe(dev_priv, pipe) |
f458ebbc DV |
3064 | if (intel_display_power_is_enabled(dev_priv, |
3065 | POWER_DOMAIN_PIPE(pipe))) | |
813bde43 | 3066 | GEN8_IRQ_RESET_NDX(DE_PIPE, pipe); |
abd58f01 | 3067 | |
f86f3fb0 PZ |
3068 | GEN5_IRQ_RESET(GEN8_DE_PORT_); |
3069 | GEN5_IRQ_RESET(GEN8_DE_MISC_); | |
3070 | GEN5_IRQ_RESET(GEN8_PCU_); | |
abd58f01 | 3071 | |
6e266956 | 3072 | if (HAS_PCH_SPLIT(dev_priv)) |
b243f530 | 3073 | ibx_irq_reset(dev_priv); |
abd58f01 | 3074 | } |
09f2344d | 3075 | |
4c6c03be DL |
3076 | void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv, |
3077 | unsigned int pipe_mask) | |
d49bdb0e | 3078 | { |
1180e206 | 3079 | uint32_t extra_ier = GEN8_PIPE_VBLANK | GEN8_PIPE_FIFO_UNDERRUN; |
6831f3e3 | 3080 | enum pipe pipe; |
d49bdb0e | 3081 | |
13321786 | 3082 | spin_lock_irq(&dev_priv->irq_lock); |
6831f3e3 VS |
3083 | for_each_pipe_masked(dev_priv, pipe, pipe_mask) |
3084 | GEN8_IRQ_INIT_NDX(DE_PIPE, pipe, | |
3085 | dev_priv->de_irq_mask[pipe], | |
3086 | ~dev_priv->de_irq_mask[pipe] | extra_ier); | |
13321786 | 3087 | spin_unlock_irq(&dev_priv->irq_lock); |
d49bdb0e PZ |
3088 | } |
3089 | ||
aae8ba84 VS |
3090 | void gen8_irq_power_well_pre_disable(struct drm_i915_private *dev_priv, |
3091 | unsigned int pipe_mask) | |
3092 | { | |
6831f3e3 VS |
3093 | enum pipe pipe; |
3094 | ||
aae8ba84 | 3095 | spin_lock_irq(&dev_priv->irq_lock); |
6831f3e3 VS |
3096 | for_each_pipe_masked(dev_priv, pipe, pipe_mask) |
3097 | GEN8_IRQ_RESET_NDX(DE_PIPE, pipe); | |
aae8ba84 VS |
3098 | spin_unlock_irq(&dev_priv->irq_lock); |
3099 | ||
3100 | /* make sure we're done processing display irqs */ | |
91c8a326 | 3101 | synchronize_irq(dev_priv->drm.irq); |
aae8ba84 VS |
3102 | } |
3103 | ||
43f328d7 VS |
3104 | static void cherryview_irq_preinstall(struct drm_device *dev) |
3105 | { | |
fac5e23e | 3106 | struct drm_i915_private *dev_priv = to_i915(dev); |
43f328d7 VS |
3107 | |
3108 | I915_WRITE(GEN8_MASTER_IRQ, 0); | |
3109 | POSTING_READ(GEN8_MASTER_IRQ); | |
3110 | ||
d6e3cca3 | 3111 | gen8_gt_irq_reset(dev_priv); |
43f328d7 VS |
3112 | |
3113 | GEN5_IRQ_RESET(GEN8_PCU_); | |
3114 | ||
ad22d106 | 3115 | spin_lock_irq(&dev_priv->irq_lock); |
9918271e VS |
3116 | if (dev_priv->display_irqs_enabled) |
3117 | vlv_display_irq_reset(dev_priv); | |
ad22d106 | 3118 | spin_unlock_irq(&dev_priv->irq_lock); |
43f328d7 VS |
3119 | } |
3120 | ||
91d14251 | 3121 | static u32 intel_hpd_enabled_irqs(struct drm_i915_private *dev_priv, |
87a02106 VS |
3122 | const u32 hpd[HPD_NUM_PINS]) |
3123 | { | |
87a02106 VS |
3124 | struct intel_encoder *encoder; |
3125 | u32 enabled_irqs = 0; | |
3126 | ||
91c8a326 | 3127 | for_each_intel_encoder(&dev_priv->drm, encoder) |
87a02106 VS |
3128 | if (dev_priv->hotplug.stats[encoder->hpd_pin].state == HPD_ENABLED) |
3129 | enabled_irqs |= hpd[encoder->hpd_pin]; | |
3130 | ||
3131 | return enabled_irqs; | |
3132 | } | |
3133 | ||
1a56b1a2 | 3134 | static void ibx_hpd_detection_setup(struct drm_i915_private *dev_priv) |
7fe0b973 | 3135 | { |
1a56b1a2 | 3136 | u32 hotplug; |
82a28bcf DV |
3137 | |
3138 | /* | |
3139 | * Enable digital hotplug on the PCH, and configure the DP short pulse | |
6dbf30ce VS |
3140 | * duration to 2ms (which is the minimum in the Display Port spec). |
3141 | * The pulse duration bits are reserved on LPT+. | |
82a28bcf | 3142 | */ |
7fe0b973 | 3143 | hotplug = I915_READ(PCH_PORT_HOTPLUG); |
1a56b1a2 ID |
3144 | hotplug &= ~(PORTB_PULSE_DURATION_MASK | |
3145 | PORTC_PULSE_DURATION_MASK | | |
3146 | PORTD_PULSE_DURATION_MASK); | |
7fe0b973 | 3147 | hotplug |= PORTB_HOTPLUG_ENABLE | PORTB_PULSE_DURATION_2ms; |
1a56b1a2 ID |
3148 | hotplug |= PORTC_HOTPLUG_ENABLE | PORTC_PULSE_DURATION_2ms; |
3149 | hotplug |= PORTD_HOTPLUG_ENABLE | PORTD_PULSE_DURATION_2ms; | |
0b2eb33e VS |
3150 | /* |
3151 | * When CPU and PCH are on the same package, port A | |
3152 | * HPD must be enabled in both north and south. | |
3153 | */ | |
91d14251 | 3154 | if (HAS_PCH_LPT_LP(dev_priv)) |
0b2eb33e | 3155 | hotplug |= PORTA_HOTPLUG_ENABLE; |
7fe0b973 | 3156 | I915_WRITE(PCH_PORT_HOTPLUG, hotplug); |
6dbf30ce | 3157 | } |
26951caf | 3158 | |
1a56b1a2 ID |
3159 | static void ibx_hpd_irq_setup(struct drm_i915_private *dev_priv) |
3160 | { | |
3161 | u32 hotplug_irqs, enabled_irqs; | |
3162 | ||
3163 | if (HAS_PCH_IBX(dev_priv)) { | |
3164 | hotplug_irqs = SDE_HOTPLUG_MASK; | |
3165 | enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_ibx); | |
3166 | } else { | |
3167 | hotplug_irqs = SDE_HOTPLUG_MASK_CPT; | |
3168 | enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_cpt); | |
3169 | } | |
3170 | ||
3171 | ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs); | |
3172 | ||
3173 | ibx_hpd_detection_setup(dev_priv); | |
3174 | } | |
3175 | ||
2a57d9cc | 3176 | static void spt_hpd_detection_setup(struct drm_i915_private *dev_priv) |
6dbf30ce | 3177 | { |
2a57d9cc | 3178 | u32 hotplug; |
6dbf30ce VS |
3179 | |
3180 | /* Enable digital hotplug on the PCH */ | |
3181 | hotplug = I915_READ(PCH_PORT_HOTPLUG); | |
2a57d9cc ID |
3182 | hotplug |= PORTA_HOTPLUG_ENABLE | |
3183 | PORTB_HOTPLUG_ENABLE | | |
3184 | PORTC_HOTPLUG_ENABLE | | |
3185 | PORTD_HOTPLUG_ENABLE; | |
6dbf30ce VS |
3186 | I915_WRITE(PCH_PORT_HOTPLUG, hotplug); |
3187 | ||
3188 | hotplug = I915_READ(PCH_PORT_HOTPLUG2); | |
3189 | hotplug |= PORTE_HOTPLUG_ENABLE; | |
3190 | I915_WRITE(PCH_PORT_HOTPLUG2, hotplug); | |
7fe0b973 KP |
3191 | } |
3192 | ||
2a57d9cc ID |
3193 | static void spt_hpd_irq_setup(struct drm_i915_private *dev_priv) |
3194 | { | |
3195 | u32 hotplug_irqs, enabled_irqs; | |
3196 | ||
3197 | hotplug_irqs = SDE_HOTPLUG_MASK_SPT; | |
3198 | enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_spt); | |
3199 | ||
3200 | ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs); | |
3201 | ||
3202 | spt_hpd_detection_setup(dev_priv); | |
3203 | } | |
3204 | ||
1a56b1a2 ID |
3205 | static void ilk_hpd_detection_setup(struct drm_i915_private *dev_priv) |
3206 | { | |
3207 | u32 hotplug; | |
3208 | ||
3209 | /* | |
3210 | * Enable digital hotplug on the CPU, and configure the DP short pulse | |
3211 | * duration to 2ms (which is the minimum in the Display Port spec) | |
3212 | * The pulse duration bits are reserved on HSW+. | |
3213 | */ | |
3214 | hotplug = I915_READ(DIGITAL_PORT_HOTPLUG_CNTRL); | |
3215 | hotplug &= ~DIGITAL_PORTA_PULSE_DURATION_MASK; | |
3216 | hotplug |= DIGITAL_PORTA_HOTPLUG_ENABLE | | |
3217 | DIGITAL_PORTA_PULSE_DURATION_2ms; | |
3218 | I915_WRITE(DIGITAL_PORT_HOTPLUG_CNTRL, hotplug); | |
3219 | } | |
3220 | ||
91d14251 | 3221 | static void ilk_hpd_irq_setup(struct drm_i915_private *dev_priv) |
e4ce95aa | 3222 | { |
1a56b1a2 | 3223 | u32 hotplug_irqs, enabled_irqs; |
e4ce95aa | 3224 | |
91d14251 | 3225 | if (INTEL_GEN(dev_priv) >= 8) { |
3a3b3c7d | 3226 | hotplug_irqs = GEN8_PORT_DP_A_HOTPLUG; |
91d14251 | 3227 | enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_bdw); |
3a3b3c7d VS |
3228 | |
3229 | bdw_update_port_irq(dev_priv, hotplug_irqs, enabled_irqs); | |
91d14251 | 3230 | } else if (INTEL_GEN(dev_priv) >= 7) { |
23bb4cb5 | 3231 | hotplug_irqs = DE_DP_A_HOTPLUG_IVB; |
91d14251 | 3232 | enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_ivb); |
3a3b3c7d VS |
3233 | |
3234 | ilk_update_display_irq(dev_priv, hotplug_irqs, enabled_irqs); | |
23bb4cb5 VS |
3235 | } else { |
3236 | hotplug_irqs = DE_DP_A_HOTPLUG; | |
91d14251 | 3237 | enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_ilk); |
e4ce95aa | 3238 | |
3a3b3c7d VS |
3239 | ilk_update_display_irq(dev_priv, hotplug_irqs, enabled_irqs); |
3240 | } | |
e4ce95aa | 3241 | |
1a56b1a2 | 3242 | ilk_hpd_detection_setup(dev_priv); |
e4ce95aa | 3243 | |
91d14251 | 3244 | ibx_hpd_irq_setup(dev_priv); |
e4ce95aa VS |
3245 | } |
3246 | ||
2a57d9cc ID |
3247 | static void __bxt_hpd_detection_setup(struct drm_i915_private *dev_priv, |
3248 | u32 enabled_irqs) | |
e0a20ad7 | 3249 | { |
2a57d9cc | 3250 | u32 hotplug; |
e0a20ad7 | 3251 | |
a52bb15b | 3252 | hotplug = I915_READ(PCH_PORT_HOTPLUG); |
2a57d9cc ID |
3253 | hotplug |= PORTA_HOTPLUG_ENABLE | |
3254 | PORTB_HOTPLUG_ENABLE | | |
3255 | PORTC_HOTPLUG_ENABLE; | |
d252bf68 SS |
3256 | |
3257 | DRM_DEBUG_KMS("Invert bit setting: hp_ctl:%x hp_port:%x\n", | |
3258 | hotplug, enabled_irqs); | |
3259 | hotplug &= ~BXT_DDI_HPD_INVERT_MASK; | |
3260 | ||
3261 | /* | |
3262 | * For BXT invert bit has to be set based on AOB design | |
3263 | * for HPD detection logic, update it based on VBT fields. | |
3264 | */ | |
d252bf68 SS |
3265 | if ((enabled_irqs & BXT_DE_PORT_HP_DDIA) && |
3266 | intel_bios_is_port_hpd_inverted(dev_priv, PORT_A)) | |
3267 | hotplug |= BXT_DDIA_HPD_INVERT; | |
3268 | if ((enabled_irqs & BXT_DE_PORT_HP_DDIB) && | |
3269 | intel_bios_is_port_hpd_inverted(dev_priv, PORT_B)) | |
3270 | hotplug |= BXT_DDIB_HPD_INVERT; | |
3271 | if ((enabled_irqs & BXT_DE_PORT_HP_DDIC) && | |
3272 | intel_bios_is_port_hpd_inverted(dev_priv, PORT_C)) | |
3273 | hotplug |= BXT_DDIC_HPD_INVERT; | |
3274 | ||
a52bb15b | 3275 | I915_WRITE(PCH_PORT_HOTPLUG, hotplug); |
e0a20ad7 SS |
3276 | } |
3277 | ||
2a57d9cc ID |
3278 | static void bxt_hpd_detection_setup(struct drm_i915_private *dev_priv) |
3279 | { | |
3280 | __bxt_hpd_detection_setup(dev_priv, BXT_DE_PORT_HOTPLUG_MASK); | |
3281 | } | |
3282 | ||
3283 | static void bxt_hpd_irq_setup(struct drm_i915_private *dev_priv) | |
3284 | { | |
3285 | u32 hotplug_irqs, enabled_irqs; | |
3286 | ||
3287 | enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_bxt); | |
3288 | hotplug_irqs = BXT_DE_PORT_HOTPLUG_MASK; | |
3289 | ||
3290 | bdw_update_port_irq(dev_priv, hotplug_irqs, enabled_irqs); | |
3291 | ||
3292 | __bxt_hpd_detection_setup(dev_priv, enabled_irqs); | |
3293 | } | |
3294 | ||
d46da437 PZ |
3295 | static void ibx_irq_postinstall(struct drm_device *dev) |
3296 | { | |
fac5e23e | 3297 | struct drm_i915_private *dev_priv = to_i915(dev); |
82a28bcf | 3298 | u32 mask; |
e5868a31 | 3299 | |
6e266956 | 3300 | if (HAS_PCH_NOP(dev_priv)) |
692a04cf DV |
3301 | return; |
3302 | ||
6e266956 | 3303 | if (HAS_PCH_IBX(dev_priv)) |
5c673b60 | 3304 | mask = SDE_GMBUS | SDE_AUX_MASK | SDE_POISON; |
105b122e | 3305 | else |
5c673b60 | 3306 | mask = SDE_GMBUS_CPT | SDE_AUX_MASK_CPT; |
8664281b | 3307 | |
b51a2842 | 3308 | gen5_assert_iir_is_zero(dev_priv, SDEIIR); |
d46da437 | 3309 | I915_WRITE(SDEIMR, ~mask); |
2a57d9cc ID |
3310 | |
3311 | if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv) || | |
3312 | HAS_PCH_LPT(dev_priv)) | |
1a56b1a2 | 3313 | ibx_hpd_detection_setup(dev_priv); |
2a57d9cc ID |
3314 | else |
3315 | spt_hpd_detection_setup(dev_priv); | |
d46da437 PZ |
3316 | } |
3317 | ||
0a9a8c91 DV |
3318 | static void gen5_gt_irq_postinstall(struct drm_device *dev) |
3319 | { | |
fac5e23e | 3320 | struct drm_i915_private *dev_priv = to_i915(dev); |
0a9a8c91 DV |
3321 | u32 pm_irqs, gt_irqs; |
3322 | ||
3323 | pm_irqs = gt_irqs = 0; | |
3324 | ||
3325 | dev_priv->gt_irq_mask = ~0; | |
3c9192bc | 3326 | if (HAS_L3_DPF(dev_priv)) { |
0a9a8c91 | 3327 | /* L3 parity interrupt is always unmasked. */ |
772c2a51 TU |
3328 | dev_priv->gt_irq_mask = ~GT_PARITY_ERROR(dev_priv); |
3329 | gt_irqs |= GT_PARITY_ERROR(dev_priv); | |
0a9a8c91 DV |
3330 | } |
3331 | ||
3332 | gt_irqs |= GT_RENDER_USER_INTERRUPT; | |
5db94019 | 3333 | if (IS_GEN5(dev_priv)) { |
f8973c21 | 3334 | gt_irqs |= ILK_BSD_USER_INTERRUPT; |
0a9a8c91 DV |
3335 | } else { |
3336 | gt_irqs |= GT_BLT_USER_INTERRUPT | GT_BSD_USER_INTERRUPT; | |
3337 | } | |
3338 | ||
35079899 | 3339 | GEN5_IRQ_INIT(GT, dev_priv->gt_irq_mask, gt_irqs); |
0a9a8c91 | 3340 | |
b243f530 | 3341 | if (INTEL_GEN(dev_priv) >= 6) { |
78e68d36 ID |
3342 | /* |
3343 | * RPS interrupts will get enabled/disabled on demand when RPS | |
3344 | * itself is enabled/disabled. | |
3345 | */ | |
f4e9af4f | 3346 | if (HAS_VEBOX(dev_priv)) { |
0a9a8c91 | 3347 | pm_irqs |= PM_VEBOX_USER_INTERRUPT; |
f4e9af4f AG |
3348 | dev_priv->pm_ier |= PM_VEBOX_USER_INTERRUPT; |
3349 | } | |
0a9a8c91 | 3350 | |
f4e9af4f AG |
3351 | dev_priv->pm_imr = 0xffffffff; |
3352 | GEN5_IRQ_INIT(GEN6_PM, dev_priv->pm_imr, pm_irqs); | |
0a9a8c91 DV |
3353 | } |
3354 | } | |
3355 | ||
f71d4af4 | 3356 | static int ironlake_irq_postinstall(struct drm_device *dev) |
036a4a7d | 3357 | { |
fac5e23e | 3358 | struct drm_i915_private *dev_priv = to_i915(dev); |
8e76f8dc PZ |
3359 | u32 display_mask, extra_mask; |
3360 | ||
b243f530 | 3361 | if (INTEL_GEN(dev_priv) >= 7) { |
8e76f8dc PZ |
3362 | display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE_IVB | |
3363 | DE_PCH_EVENT_IVB | DE_PLANEC_FLIP_DONE_IVB | | |
3364 | DE_PLANEB_FLIP_DONE_IVB | | |
5c673b60 | 3365 | DE_PLANEA_FLIP_DONE_IVB | DE_AUX_CHANNEL_A_IVB); |
8e76f8dc | 3366 | extra_mask = (DE_PIPEC_VBLANK_IVB | DE_PIPEB_VBLANK_IVB | |
23bb4cb5 VS |
3367 | DE_PIPEA_VBLANK_IVB | DE_ERR_INT_IVB | |
3368 | DE_DP_A_HOTPLUG_IVB); | |
8e76f8dc PZ |
3369 | } else { |
3370 | display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT | | |
3371 | DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE | | |
5b3a856b | 3372 | DE_AUX_CHANNEL_A | |
5b3a856b DV |
3373 | DE_PIPEB_CRC_DONE | DE_PIPEA_CRC_DONE | |
3374 | DE_POISON); | |
e4ce95aa VS |
3375 | extra_mask = (DE_PIPEA_VBLANK | DE_PIPEB_VBLANK | DE_PCU_EVENT | |
3376 | DE_PIPEB_FIFO_UNDERRUN | DE_PIPEA_FIFO_UNDERRUN | | |
3377 | DE_DP_A_HOTPLUG); | |
8e76f8dc | 3378 | } |
036a4a7d | 3379 | |
1ec14ad3 | 3380 | dev_priv->irq_mask = ~display_mask; |
036a4a7d | 3381 | |
0c841212 PZ |
3382 | I915_WRITE(HWSTAM, 0xeffe); |
3383 | ||
622364b6 PZ |
3384 | ibx_irq_pre_postinstall(dev); |
3385 | ||
35079899 | 3386 | GEN5_IRQ_INIT(DE, dev_priv->irq_mask, display_mask | extra_mask); |
036a4a7d | 3387 | |
0a9a8c91 | 3388 | gen5_gt_irq_postinstall(dev); |
036a4a7d | 3389 | |
1a56b1a2 ID |
3390 | ilk_hpd_detection_setup(dev_priv); |
3391 | ||
d46da437 | 3392 | ibx_irq_postinstall(dev); |
7fe0b973 | 3393 | |
50a0bc90 | 3394 | if (IS_IRONLAKE_M(dev_priv)) { |
6005ce42 DV |
3395 | /* Enable PCU event interrupts |
3396 | * | |
3397 | * spinlocking not required here for correctness since interrupt | |
4bc9d430 DV |
3398 | * setup is guaranteed to run in single-threaded context. But we |
3399 | * need it to make the assert_spin_locked happy. */ | |
d6207435 | 3400 | spin_lock_irq(&dev_priv->irq_lock); |
fbdedaea | 3401 | ilk_enable_display_irq(dev_priv, DE_PCU_EVENT); |
d6207435 | 3402 | spin_unlock_irq(&dev_priv->irq_lock); |
f97108d1 JB |
3403 | } |
3404 | ||
036a4a7d ZW |
3405 | return 0; |
3406 | } | |
3407 | ||
f8b79e58 ID |
3408 | void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv) |
3409 | { | |
67520415 | 3410 | lockdep_assert_held(&dev_priv->irq_lock); |
f8b79e58 ID |
3411 | |
3412 | if (dev_priv->display_irqs_enabled) | |
3413 | return; | |
3414 | ||
3415 | dev_priv->display_irqs_enabled = true; | |
3416 | ||
d6c69803 VS |
3417 | if (intel_irqs_enabled(dev_priv)) { |
3418 | vlv_display_irq_reset(dev_priv); | |
ad22d106 | 3419 | vlv_display_irq_postinstall(dev_priv); |
d6c69803 | 3420 | } |
f8b79e58 ID |
3421 | } |
3422 | ||
3423 | void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv) | |
3424 | { | |
67520415 | 3425 | lockdep_assert_held(&dev_priv->irq_lock); |
f8b79e58 ID |
3426 | |
3427 | if (!dev_priv->display_irqs_enabled) | |
3428 | return; | |
3429 | ||
3430 | dev_priv->display_irqs_enabled = false; | |
3431 | ||
950eabaf | 3432 | if (intel_irqs_enabled(dev_priv)) |
ad22d106 | 3433 | vlv_display_irq_reset(dev_priv); |
f8b79e58 ID |
3434 | } |
3435 | ||
0e6c9a9e VS |
3436 | |
3437 | static int valleyview_irq_postinstall(struct drm_device *dev) | |
3438 | { | |
fac5e23e | 3439 | struct drm_i915_private *dev_priv = to_i915(dev); |
0e6c9a9e | 3440 | |
0a9a8c91 | 3441 | gen5_gt_irq_postinstall(dev); |
7e231dbe | 3442 | |
ad22d106 | 3443 | spin_lock_irq(&dev_priv->irq_lock); |
9918271e VS |
3444 | if (dev_priv->display_irqs_enabled) |
3445 | vlv_display_irq_postinstall(dev_priv); | |
ad22d106 VS |
3446 | spin_unlock_irq(&dev_priv->irq_lock); |
3447 | ||
7e231dbe | 3448 | I915_WRITE(VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE); |
34c7b8a7 | 3449 | POSTING_READ(VLV_MASTER_IER); |
20afbda2 DV |
3450 | |
3451 | return 0; | |
3452 | } | |
3453 | ||
abd58f01 BW |
3454 | static void gen8_gt_irq_postinstall(struct drm_i915_private *dev_priv) |
3455 | { | |
abd58f01 BW |
3456 | /* These are interrupts we'll toggle with the ring mask register */ |
3457 | uint32_t gt_interrupts[] = { | |
3458 | GT_RENDER_USER_INTERRUPT << GEN8_RCS_IRQ_SHIFT | | |
73d477f6 | 3459 | GT_CONTEXT_SWITCH_INTERRUPT << GEN8_RCS_IRQ_SHIFT | |
73d477f6 OM |
3460 | GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT | |
3461 | GT_CONTEXT_SWITCH_INTERRUPT << GEN8_BCS_IRQ_SHIFT, | |
abd58f01 | 3462 | GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT | |
73d477f6 OM |
3463 | GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS1_IRQ_SHIFT | |
3464 | GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT | | |
3465 | GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS2_IRQ_SHIFT, | |
abd58f01 | 3466 | 0, |
73d477f6 OM |
3467 | GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT | |
3468 | GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VECS_IRQ_SHIFT | |
abd58f01 BW |
3469 | }; |
3470 | ||
98735739 TU |
3471 | if (HAS_L3_DPF(dev_priv)) |
3472 | gt_interrupts[0] |= GT_RENDER_L3_PARITY_ERROR_INTERRUPT; | |
3473 | ||
f4e9af4f AG |
3474 | dev_priv->pm_ier = 0x0; |
3475 | dev_priv->pm_imr = ~dev_priv->pm_ier; | |
9a2d2d87 D |
3476 | GEN8_IRQ_INIT_NDX(GT, 0, ~gt_interrupts[0], gt_interrupts[0]); |
3477 | GEN8_IRQ_INIT_NDX(GT, 1, ~gt_interrupts[1], gt_interrupts[1]); | |
78e68d36 ID |
3478 | /* |
3479 | * RPS interrupts will get enabled/disabled on demand when RPS itself | |
26705e20 | 3480 | * is enabled/disabled. Same wil be the case for GuC interrupts. |
78e68d36 | 3481 | */ |
f4e9af4f | 3482 | GEN8_IRQ_INIT_NDX(GT, 2, dev_priv->pm_imr, dev_priv->pm_ier); |
9a2d2d87 | 3483 | GEN8_IRQ_INIT_NDX(GT, 3, ~gt_interrupts[3], gt_interrupts[3]); |
abd58f01 BW |
3484 | } |
3485 | ||
3486 | static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv) | |
3487 | { | |
770de83d DL |
3488 | uint32_t de_pipe_masked = GEN8_PIPE_CDCLK_CRC_DONE; |
3489 | uint32_t de_pipe_enables; | |
3a3b3c7d VS |
3490 | u32 de_port_masked = GEN8_AUX_CHANNEL_A; |
3491 | u32 de_port_enables; | |
11825b0d | 3492 | u32 de_misc_masked = GEN8_DE_MISC_GSE; |
3a3b3c7d | 3493 | enum pipe pipe; |
770de83d | 3494 | |
b4834a50 | 3495 | if (INTEL_INFO(dev_priv)->gen >= 9) { |
770de83d DL |
3496 | de_pipe_masked |= GEN9_PIPE_PLANE1_FLIP_DONE | |
3497 | GEN9_DE_PIPE_IRQ_FAULT_ERRORS; | |
3a3b3c7d VS |
3498 | de_port_masked |= GEN9_AUX_CHANNEL_B | GEN9_AUX_CHANNEL_C | |
3499 | GEN9_AUX_CHANNEL_D; | |
cc3f90f0 | 3500 | if (IS_GEN9_LP(dev_priv)) |
3a3b3c7d VS |
3501 | de_port_masked |= BXT_DE_PORT_GMBUS; |
3502 | } else { | |
770de83d DL |
3503 | de_pipe_masked |= GEN8_PIPE_PRIMARY_FLIP_DONE | |
3504 | GEN8_DE_PIPE_IRQ_FAULT_ERRORS; | |
3a3b3c7d | 3505 | } |
770de83d DL |
3506 | |
3507 | de_pipe_enables = de_pipe_masked | GEN8_PIPE_VBLANK | | |
3508 | GEN8_PIPE_FIFO_UNDERRUN; | |
3509 | ||
3a3b3c7d | 3510 | de_port_enables = de_port_masked; |
cc3f90f0 | 3511 | if (IS_GEN9_LP(dev_priv)) |
a52bb15b VS |
3512 | de_port_enables |= BXT_DE_PORT_HOTPLUG_MASK; |
3513 | else if (IS_BROADWELL(dev_priv)) | |
3a3b3c7d VS |
3514 | de_port_enables |= GEN8_PORT_DP_A_HOTPLUG; |
3515 | ||
13b3a0a7 DV |
3516 | dev_priv->de_irq_mask[PIPE_A] = ~de_pipe_masked; |
3517 | dev_priv->de_irq_mask[PIPE_B] = ~de_pipe_masked; | |
3518 | dev_priv->de_irq_mask[PIPE_C] = ~de_pipe_masked; | |
abd58f01 | 3519 | |
055e393f | 3520 | for_each_pipe(dev_priv, pipe) |
f458ebbc | 3521 | if (intel_display_power_is_enabled(dev_priv, |
813bde43 PZ |
3522 | POWER_DOMAIN_PIPE(pipe))) |
3523 | GEN8_IRQ_INIT_NDX(DE_PIPE, pipe, | |
3524 | dev_priv->de_irq_mask[pipe], | |
3525 | de_pipe_enables); | |
abd58f01 | 3526 | |
3a3b3c7d | 3527 | GEN5_IRQ_INIT(GEN8_DE_PORT_, ~de_port_masked, de_port_enables); |
11825b0d | 3528 | GEN5_IRQ_INIT(GEN8_DE_MISC_, ~de_misc_masked, de_misc_masked); |
2a57d9cc ID |
3529 | |
3530 | if (IS_GEN9_LP(dev_priv)) | |
3531 | bxt_hpd_detection_setup(dev_priv); | |
1a56b1a2 ID |
3532 | else if (IS_BROADWELL(dev_priv)) |
3533 | ilk_hpd_detection_setup(dev_priv); | |
abd58f01 BW |
3534 | } |
3535 | ||
3536 | static int gen8_irq_postinstall(struct drm_device *dev) | |
3537 | { | |
fac5e23e | 3538 | struct drm_i915_private *dev_priv = to_i915(dev); |
abd58f01 | 3539 | |
6e266956 | 3540 | if (HAS_PCH_SPLIT(dev_priv)) |
266ea3d9 | 3541 | ibx_irq_pre_postinstall(dev); |
622364b6 | 3542 | |
abd58f01 BW |
3543 | gen8_gt_irq_postinstall(dev_priv); |
3544 | gen8_de_irq_postinstall(dev_priv); | |
3545 | ||
6e266956 | 3546 | if (HAS_PCH_SPLIT(dev_priv)) |
266ea3d9 | 3547 | ibx_irq_postinstall(dev); |
abd58f01 | 3548 | |
e5328c43 | 3549 | I915_WRITE(GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL); |
abd58f01 BW |
3550 | POSTING_READ(GEN8_MASTER_IRQ); |
3551 | ||
3552 | return 0; | |
3553 | } | |
3554 | ||
43f328d7 VS |
3555 | static int cherryview_irq_postinstall(struct drm_device *dev) |
3556 | { | |
fac5e23e | 3557 | struct drm_i915_private *dev_priv = to_i915(dev); |
43f328d7 | 3558 | |
43f328d7 VS |
3559 | gen8_gt_irq_postinstall(dev_priv); |
3560 | ||
ad22d106 | 3561 | spin_lock_irq(&dev_priv->irq_lock); |
9918271e VS |
3562 | if (dev_priv->display_irqs_enabled) |
3563 | vlv_display_irq_postinstall(dev_priv); | |
ad22d106 VS |
3564 | spin_unlock_irq(&dev_priv->irq_lock); |
3565 | ||
e5328c43 | 3566 | I915_WRITE(GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL); |
43f328d7 VS |
3567 | POSTING_READ(GEN8_MASTER_IRQ); |
3568 | ||
3569 | return 0; | |
3570 | } | |
3571 | ||
abd58f01 BW |
3572 | static void gen8_irq_uninstall(struct drm_device *dev) |
3573 | { | |
fac5e23e | 3574 | struct drm_i915_private *dev_priv = to_i915(dev); |
abd58f01 BW |
3575 | |
3576 | if (!dev_priv) | |
3577 | return; | |
3578 | ||
823f6b38 | 3579 | gen8_irq_reset(dev); |
abd58f01 BW |
3580 | } |
3581 | ||
7e231dbe JB |
3582 | static void valleyview_irq_uninstall(struct drm_device *dev) |
3583 | { | |
fac5e23e | 3584 | struct drm_i915_private *dev_priv = to_i915(dev); |
7e231dbe JB |
3585 | |
3586 | if (!dev_priv) | |
3587 | return; | |
3588 | ||
843d0e7d | 3589 | I915_WRITE(VLV_MASTER_IER, 0); |
34c7b8a7 | 3590 | POSTING_READ(VLV_MASTER_IER); |
843d0e7d | 3591 | |
b243f530 | 3592 | gen5_gt_irq_reset(dev_priv); |
893fce8e | 3593 | |
7e231dbe | 3594 | I915_WRITE(HWSTAM, 0xffffffff); |
f8b79e58 | 3595 | |
ad22d106 | 3596 | spin_lock_irq(&dev_priv->irq_lock); |
9918271e VS |
3597 | if (dev_priv->display_irqs_enabled) |
3598 | vlv_display_irq_reset(dev_priv); | |
ad22d106 | 3599 | spin_unlock_irq(&dev_priv->irq_lock); |
7e231dbe JB |
3600 | } |
3601 | ||
43f328d7 VS |
3602 | static void cherryview_irq_uninstall(struct drm_device *dev) |
3603 | { | |
fac5e23e | 3604 | struct drm_i915_private *dev_priv = to_i915(dev); |
43f328d7 VS |
3605 | |
3606 | if (!dev_priv) | |
3607 | return; | |
3608 | ||
3609 | I915_WRITE(GEN8_MASTER_IRQ, 0); | |
3610 | POSTING_READ(GEN8_MASTER_IRQ); | |
3611 | ||
a2c30fba | 3612 | gen8_gt_irq_reset(dev_priv); |
43f328d7 | 3613 | |
a2c30fba | 3614 | GEN5_IRQ_RESET(GEN8_PCU_); |
43f328d7 | 3615 | |
ad22d106 | 3616 | spin_lock_irq(&dev_priv->irq_lock); |
9918271e VS |
3617 | if (dev_priv->display_irqs_enabled) |
3618 | vlv_display_irq_reset(dev_priv); | |
ad22d106 | 3619 | spin_unlock_irq(&dev_priv->irq_lock); |
43f328d7 VS |
3620 | } |
3621 | ||
f71d4af4 | 3622 | static void ironlake_irq_uninstall(struct drm_device *dev) |
036a4a7d | 3623 | { |
fac5e23e | 3624 | struct drm_i915_private *dev_priv = to_i915(dev); |
4697995b JB |
3625 | |
3626 | if (!dev_priv) | |
3627 | return; | |
3628 | ||
be30b29f | 3629 | ironlake_irq_reset(dev); |
036a4a7d ZW |
3630 | } |
3631 | ||
a266c7d5 | 3632 | static void i8xx_irq_preinstall(struct drm_device * dev) |
1da177e4 | 3633 | { |
fac5e23e | 3634 | struct drm_i915_private *dev_priv = to_i915(dev); |
9db4a9c7 | 3635 | int pipe; |
91e3738e | 3636 | |
055e393f | 3637 | for_each_pipe(dev_priv, pipe) |
9db4a9c7 | 3638 | I915_WRITE(PIPESTAT(pipe), 0); |
a266c7d5 CW |
3639 | I915_WRITE16(IMR, 0xffff); |
3640 | I915_WRITE16(IER, 0x0); | |
3641 | POSTING_READ16(IER); | |
c2798b19 CW |
3642 | } |
3643 | ||
3644 | static int i8xx_irq_postinstall(struct drm_device *dev) | |
3645 | { | |
fac5e23e | 3646 | struct drm_i915_private *dev_priv = to_i915(dev); |
c2798b19 | 3647 | |
c2798b19 CW |
3648 | I915_WRITE16(EMR, |
3649 | ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH)); | |
3650 | ||
3651 | /* Unmask the interrupts that we always want on. */ | |
3652 | dev_priv->irq_mask = | |
3653 | ~(I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | | |
3654 | I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | | |
3655 | I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | | |
37ef01ab | 3656 | I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT); |
c2798b19 CW |
3657 | I915_WRITE16(IMR, dev_priv->irq_mask); |
3658 | ||
3659 | I915_WRITE16(IER, | |
3660 | I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | | |
3661 | I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | | |
c2798b19 CW |
3662 | I915_USER_INTERRUPT); |
3663 | POSTING_READ16(IER); | |
3664 | ||
379ef82d DV |
3665 | /* Interrupt setup is already guaranteed to be single-threaded, this is |
3666 | * just to make the assert_spin_locked check happy. */ | |
d6207435 | 3667 | spin_lock_irq(&dev_priv->irq_lock); |
755e9019 ID |
3668 | i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS); |
3669 | i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS); | |
d6207435 | 3670 | spin_unlock_irq(&dev_priv->irq_lock); |
379ef82d | 3671 | |
c2798b19 CW |
3672 | return 0; |
3673 | } | |
3674 | ||
5a21b665 DV |
3675 | /* |
3676 | * Returns true when a page flip has completed. | |
3677 | */ | |
3678 | static bool i8xx_handle_vblank(struct drm_i915_private *dev_priv, | |
3679 | int plane, int pipe, u32 iir) | |
3680 | { | |
3681 | u16 flip_pending = DISPLAY_PLANE_FLIP_PENDING(plane); | |
3682 | ||
3683 | if (!intel_pipe_handle_vblank(dev_priv, pipe)) | |
3684 | return false; | |
3685 | ||
3686 | if ((iir & flip_pending) == 0) | |
3687 | goto check_page_flip; | |
3688 | ||
3689 | /* We detect FlipDone by looking for the change in PendingFlip from '1' | |
3690 | * to '0' on the following vblank, i.e. IIR has the Pendingflip | |
3691 | * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence | |
3692 | * the flip is completed (no longer pending). Since this doesn't raise | |
3693 | * an interrupt per se, we watch for the change at vblank. | |
3694 | */ | |
3695 | if (I915_READ16(ISR) & flip_pending) | |
3696 | goto check_page_flip; | |
3697 | ||
3698 | intel_finish_page_flip_cs(dev_priv, pipe); | |
3699 | return true; | |
3700 | ||
3701 | check_page_flip: | |
3702 | intel_check_page_flip(dev_priv, pipe); | |
3703 | return false; | |
3704 | } | |
3705 | ||
ff1f525e | 3706 | static irqreturn_t i8xx_irq_handler(int irq, void *arg) |
c2798b19 | 3707 | { |
45a83f84 | 3708 | struct drm_device *dev = arg; |
fac5e23e | 3709 | struct drm_i915_private *dev_priv = to_i915(dev); |
c2798b19 CW |
3710 | u16 iir, new_iir; |
3711 | u32 pipe_stats[2]; | |
c2798b19 CW |
3712 | int pipe; |
3713 | u16 flip_mask = | |
3714 | I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | | |
3715 | I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT; | |
1f814dac | 3716 | irqreturn_t ret; |
c2798b19 | 3717 | |
2dd2a883 ID |
3718 | if (!intel_irqs_enabled(dev_priv)) |
3719 | return IRQ_NONE; | |
3720 | ||
1f814dac ID |
3721 | /* IRQs are synced during runtime_suspend, we don't require a wakeref */ |
3722 | disable_rpm_wakeref_asserts(dev_priv); | |
3723 | ||
3724 | ret = IRQ_NONE; | |
c2798b19 CW |
3725 | iir = I915_READ16(IIR); |
3726 | if (iir == 0) | |
1f814dac | 3727 | goto out; |
c2798b19 CW |
3728 | |
3729 | while (iir & ~flip_mask) { | |
3730 | /* Can't rely on pipestat interrupt bit in iir as it might | |
3731 | * have been cleared after the pipestat interrupt was received. | |
3732 | * It doesn't set the bit in iir again, but it still produces | |
3733 | * interrupts (for non-MSI). | |
3734 | */ | |
222c7f51 | 3735 | spin_lock(&dev_priv->irq_lock); |
c2798b19 | 3736 | if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT) |
aaecdf61 | 3737 | DRM_DEBUG("Command parser error, iir 0x%08x\n", iir); |
c2798b19 | 3738 | |
055e393f | 3739 | for_each_pipe(dev_priv, pipe) { |
f0f59a00 | 3740 | i915_reg_t reg = PIPESTAT(pipe); |
c2798b19 CW |
3741 | pipe_stats[pipe] = I915_READ(reg); |
3742 | ||
3743 | /* | |
3744 | * Clear the PIPE*STAT regs before the IIR | |
3745 | */ | |
2d9d2b0b | 3746 | if (pipe_stats[pipe] & 0x8000ffff) |
c2798b19 | 3747 | I915_WRITE(reg, pipe_stats[pipe]); |
c2798b19 | 3748 | } |
222c7f51 | 3749 | spin_unlock(&dev_priv->irq_lock); |
c2798b19 CW |
3750 | |
3751 | I915_WRITE16(IIR, iir & ~flip_mask); | |
3752 | new_iir = I915_READ16(IIR); /* Flush posted writes */ | |
3753 | ||
c2798b19 | 3754 | if (iir & I915_USER_INTERRUPT) |
3b3f1650 | 3755 | notify_ring(dev_priv->engine[RCS]); |
c2798b19 | 3756 | |
055e393f | 3757 | for_each_pipe(dev_priv, pipe) { |
5a21b665 DV |
3758 | int plane = pipe; |
3759 | if (HAS_FBC(dev_priv)) | |
3760 | plane = !plane; | |
3761 | ||
3762 | if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS && | |
3763 | i8xx_handle_vblank(dev_priv, plane, pipe, iir)) | |
3764 | flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(plane); | |
c2798b19 | 3765 | |
4356d586 | 3766 | if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS) |
91d14251 | 3767 | i9xx_pipe_crc_irq_handler(dev_priv, pipe); |
2d9d2b0b | 3768 | |
1f7247c0 DV |
3769 | if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS) |
3770 | intel_cpu_fifo_underrun_irq_handler(dev_priv, | |
3771 | pipe); | |
4356d586 | 3772 | } |
c2798b19 CW |
3773 | |
3774 | iir = new_iir; | |
3775 | } | |
1f814dac ID |
3776 | ret = IRQ_HANDLED; |
3777 | ||
3778 | out: | |
3779 | enable_rpm_wakeref_asserts(dev_priv); | |
c2798b19 | 3780 | |
1f814dac | 3781 | return ret; |
c2798b19 CW |
3782 | } |
3783 | ||
3784 | static void i8xx_irq_uninstall(struct drm_device * dev) | |
3785 | { | |
fac5e23e | 3786 | struct drm_i915_private *dev_priv = to_i915(dev); |
c2798b19 CW |
3787 | int pipe; |
3788 | ||
055e393f | 3789 | for_each_pipe(dev_priv, pipe) { |
c2798b19 CW |
3790 | /* Clear enable bits; then clear status bits */ |
3791 | I915_WRITE(PIPESTAT(pipe), 0); | |
3792 | I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe))); | |
3793 | } | |
3794 | I915_WRITE16(IMR, 0xffff); | |
3795 | I915_WRITE16(IER, 0x0); | |
3796 | I915_WRITE16(IIR, I915_READ16(IIR)); | |
3797 | } | |
3798 | ||
a266c7d5 CW |
3799 | static void i915_irq_preinstall(struct drm_device * dev) |
3800 | { | |
fac5e23e | 3801 | struct drm_i915_private *dev_priv = to_i915(dev); |
a266c7d5 CW |
3802 | int pipe; |
3803 | ||
56b857a5 | 3804 | if (I915_HAS_HOTPLUG(dev_priv)) { |
0706f17c | 3805 | i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0); |
a266c7d5 CW |
3806 | I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); |
3807 | } | |
3808 | ||
00d98ebd | 3809 | I915_WRITE16(HWSTAM, 0xeffe); |
055e393f | 3810 | for_each_pipe(dev_priv, pipe) |
a266c7d5 CW |
3811 | I915_WRITE(PIPESTAT(pipe), 0); |
3812 | I915_WRITE(IMR, 0xffffffff); | |
3813 | I915_WRITE(IER, 0x0); | |
3814 | POSTING_READ(IER); | |
3815 | } | |
3816 | ||
3817 | static int i915_irq_postinstall(struct drm_device *dev) | |
3818 | { | |
fac5e23e | 3819 | struct drm_i915_private *dev_priv = to_i915(dev); |
38bde180 | 3820 | u32 enable_mask; |
a266c7d5 | 3821 | |
38bde180 CW |
3822 | I915_WRITE(EMR, ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH)); |
3823 | ||
3824 | /* Unmask the interrupts that we always want on. */ | |
3825 | dev_priv->irq_mask = | |
3826 | ~(I915_ASLE_INTERRUPT | | |
3827 | I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | | |
3828 | I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | | |
3829 | I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | | |
37ef01ab | 3830 | I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT); |
38bde180 CW |
3831 | |
3832 | enable_mask = | |
3833 | I915_ASLE_INTERRUPT | | |
3834 | I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | | |
3835 | I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | | |
38bde180 CW |
3836 | I915_USER_INTERRUPT; |
3837 | ||
56b857a5 | 3838 | if (I915_HAS_HOTPLUG(dev_priv)) { |
0706f17c | 3839 | i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0); |
20afbda2 DV |
3840 | POSTING_READ(PORT_HOTPLUG_EN); |
3841 | ||
a266c7d5 CW |
3842 | /* Enable in IER... */ |
3843 | enable_mask |= I915_DISPLAY_PORT_INTERRUPT; | |
3844 | /* and unmask in IMR */ | |
3845 | dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT; | |
3846 | } | |
3847 | ||
a266c7d5 CW |
3848 | I915_WRITE(IMR, dev_priv->irq_mask); |
3849 | I915_WRITE(IER, enable_mask); | |
3850 | POSTING_READ(IER); | |
3851 | ||
91d14251 | 3852 | i915_enable_asle_pipestat(dev_priv); |
20afbda2 | 3853 | |
379ef82d DV |
3854 | /* Interrupt setup is already guaranteed to be single-threaded, this is |
3855 | * just to make the assert_spin_locked check happy. */ | |
d6207435 | 3856 | spin_lock_irq(&dev_priv->irq_lock); |
755e9019 ID |
3857 | i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS); |
3858 | i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS); | |
d6207435 | 3859 | spin_unlock_irq(&dev_priv->irq_lock); |
379ef82d | 3860 | |
20afbda2 DV |
3861 | return 0; |
3862 | } | |
3863 | ||
5a21b665 DV |
3864 | /* |
3865 | * Returns true when a page flip has completed. | |
3866 | */ | |
3867 | static bool i915_handle_vblank(struct drm_i915_private *dev_priv, | |
3868 | int plane, int pipe, u32 iir) | |
3869 | { | |
3870 | u32 flip_pending = DISPLAY_PLANE_FLIP_PENDING(plane); | |
3871 | ||
3872 | if (!intel_pipe_handle_vblank(dev_priv, pipe)) | |
3873 | return false; | |
3874 | ||
3875 | if ((iir & flip_pending) == 0) | |
3876 | goto check_page_flip; | |
3877 | ||
3878 | /* We detect FlipDone by looking for the change in PendingFlip from '1' | |
3879 | * to '0' on the following vblank, i.e. IIR has the Pendingflip | |
3880 | * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence | |
3881 | * the flip is completed (no longer pending). Since this doesn't raise | |
3882 | * an interrupt per se, we watch for the change at vblank. | |
3883 | */ | |
3884 | if (I915_READ(ISR) & flip_pending) | |
3885 | goto check_page_flip; | |
3886 | ||
3887 | intel_finish_page_flip_cs(dev_priv, pipe); | |
3888 | return true; | |
3889 | ||
3890 | check_page_flip: | |
3891 | intel_check_page_flip(dev_priv, pipe); | |
3892 | return false; | |
3893 | } | |
3894 | ||
ff1f525e | 3895 | static irqreturn_t i915_irq_handler(int irq, void *arg) |
a266c7d5 | 3896 | { |
45a83f84 | 3897 | struct drm_device *dev = arg; |
fac5e23e | 3898 | struct drm_i915_private *dev_priv = to_i915(dev); |
8291ee90 | 3899 | u32 iir, new_iir, pipe_stats[I915_MAX_PIPES]; |
38bde180 CW |
3900 | u32 flip_mask = |
3901 | I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | | |
3902 | I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT; | |
38bde180 | 3903 | int pipe, ret = IRQ_NONE; |
a266c7d5 | 3904 | |
2dd2a883 ID |
3905 | if (!intel_irqs_enabled(dev_priv)) |
3906 | return IRQ_NONE; | |
3907 | ||
1f814dac ID |
3908 | /* IRQs are synced during runtime_suspend, we don't require a wakeref */ |
3909 | disable_rpm_wakeref_asserts(dev_priv); | |
3910 | ||
a266c7d5 | 3911 | iir = I915_READ(IIR); |
38bde180 CW |
3912 | do { |
3913 | bool irq_received = (iir & ~flip_mask) != 0; | |
8291ee90 | 3914 | bool blc_event = false; |
a266c7d5 CW |
3915 | |
3916 | /* Can't rely on pipestat interrupt bit in iir as it might | |
3917 | * have been cleared after the pipestat interrupt was received. | |
3918 | * It doesn't set the bit in iir again, but it still produces | |
3919 | * interrupts (for non-MSI). | |
3920 | */ | |
222c7f51 | 3921 | spin_lock(&dev_priv->irq_lock); |
a266c7d5 | 3922 | if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT) |
aaecdf61 | 3923 | DRM_DEBUG("Command parser error, iir 0x%08x\n", iir); |
a266c7d5 | 3924 | |
055e393f | 3925 | for_each_pipe(dev_priv, pipe) { |
f0f59a00 | 3926 | i915_reg_t reg = PIPESTAT(pipe); |
a266c7d5 CW |
3927 | pipe_stats[pipe] = I915_READ(reg); |
3928 | ||
38bde180 | 3929 | /* Clear the PIPE*STAT regs before the IIR */ |
a266c7d5 | 3930 | if (pipe_stats[pipe] & 0x8000ffff) { |
a266c7d5 | 3931 | I915_WRITE(reg, pipe_stats[pipe]); |
38bde180 | 3932 | irq_received = true; |
a266c7d5 CW |
3933 | } |
3934 | } | |
222c7f51 | 3935 | spin_unlock(&dev_priv->irq_lock); |
a266c7d5 CW |
3936 | |
3937 | if (!irq_received) | |
3938 | break; | |
3939 | ||
a266c7d5 | 3940 | /* Consume port. Then clear IIR or we'll miss events */ |
91d14251 | 3941 | if (I915_HAS_HOTPLUG(dev_priv) && |
1ae3c34c VS |
3942 | iir & I915_DISPLAY_PORT_INTERRUPT) { |
3943 | u32 hotplug_status = i9xx_hpd_irq_ack(dev_priv); | |
3944 | if (hotplug_status) | |
91d14251 | 3945 | i9xx_hpd_irq_handler(dev_priv, hotplug_status); |
1ae3c34c | 3946 | } |
a266c7d5 | 3947 | |
38bde180 | 3948 | I915_WRITE(IIR, iir & ~flip_mask); |
a266c7d5 CW |
3949 | new_iir = I915_READ(IIR); /* Flush posted writes */ |
3950 | ||
a266c7d5 | 3951 | if (iir & I915_USER_INTERRUPT) |
3b3f1650 | 3952 | notify_ring(dev_priv->engine[RCS]); |
a266c7d5 | 3953 | |
055e393f | 3954 | for_each_pipe(dev_priv, pipe) { |
5a21b665 DV |
3955 | int plane = pipe; |
3956 | if (HAS_FBC(dev_priv)) | |
3957 | plane = !plane; | |
3958 | ||
3959 | if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS && | |
3960 | i915_handle_vblank(dev_priv, plane, pipe, iir)) | |
3961 | flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(plane); | |
a266c7d5 CW |
3962 | |
3963 | if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS) | |
3964 | blc_event = true; | |
4356d586 DV |
3965 | |
3966 | if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS) | |
91d14251 | 3967 | i9xx_pipe_crc_irq_handler(dev_priv, pipe); |
2d9d2b0b | 3968 | |
1f7247c0 DV |
3969 | if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS) |
3970 | intel_cpu_fifo_underrun_irq_handler(dev_priv, | |
3971 | pipe); | |
a266c7d5 CW |
3972 | } |
3973 | ||
a266c7d5 | 3974 | if (blc_event || (iir & I915_ASLE_INTERRUPT)) |
91d14251 | 3975 | intel_opregion_asle_intr(dev_priv); |
a266c7d5 CW |
3976 | |
3977 | /* With MSI, interrupts are only generated when iir | |
3978 | * transitions from zero to nonzero. If another bit got | |
3979 | * set while we were handling the existing iir bits, then | |
3980 | * we would never get another interrupt. | |
3981 | * | |
3982 | * This is fine on non-MSI as well, as if we hit this path | |
3983 | * we avoid exiting the interrupt handler only to generate | |
3984 | * another one. | |
3985 | * | |
3986 | * Note that for MSI this could cause a stray interrupt report | |
3987 | * if an interrupt landed in the time between writing IIR and | |
3988 | * the posting read. This should be rare enough to never | |
3989 | * trigger the 99% of 100,000 interrupts test for disabling | |
3990 | * stray interrupts. | |
3991 | */ | |
38bde180 | 3992 | ret = IRQ_HANDLED; |
a266c7d5 | 3993 | iir = new_iir; |
38bde180 | 3994 | } while (iir & ~flip_mask); |
a266c7d5 | 3995 | |
1f814dac ID |
3996 | enable_rpm_wakeref_asserts(dev_priv); |
3997 | ||
a266c7d5 CW |
3998 | return ret; |
3999 | } | |
4000 | ||
4001 | static void i915_irq_uninstall(struct drm_device * dev) | |
4002 | { | |
fac5e23e | 4003 | struct drm_i915_private *dev_priv = to_i915(dev); |
a266c7d5 CW |
4004 | int pipe; |
4005 | ||
56b857a5 | 4006 | if (I915_HAS_HOTPLUG(dev_priv)) { |
0706f17c | 4007 | i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0); |
a266c7d5 CW |
4008 | I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); |
4009 | } | |
4010 | ||
00d98ebd | 4011 | I915_WRITE16(HWSTAM, 0xffff); |
055e393f | 4012 | for_each_pipe(dev_priv, pipe) { |
55b39755 | 4013 | /* Clear enable bits; then clear status bits */ |
a266c7d5 | 4014 | I915_WRITE(PIPESTAT(pipe), 0); |
55b39755 CW |
4015 | I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe))); |
4016 | } | |
a266c7d5 CW |
4017 | I915_WRITE(IMR, 0xffffffff); |
4018 | I915_WRITE(IER, 0x0); | |
4019 | ||
a266c7d5 CW |
4020 | I915_WRITE(IIR, I915_READ(IIR)); |
4021 | } | |
4022 | ||
4023 | static void i965_irq_preinstall(struct drm_device * dev) | |
4024 | { | |
fac5e23e | 4025 | struct drm_i915_private *dev_priv = to_i915(dev); |
a266c7d5 CW |
4026 | int pipe; |
4027 | ||
0706f17c | 4028 | i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0); |
adca4730 | 4029 | I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); |
a266c7d5 CW |
4030 | |
4031 | I915_WRITE(HWSTAM, 0xeffe); | |
055e393f | 4032 | for_each_pipe(dev_priv, pipe) |
a266c7d5 CW |
4033 | I915_WRITE(PIPESTAT(pipe), 0); |
4034 | I915_WRITE(IMR, 0xffffffff); | |
4035 | I915_WRITE(IER, 0x0); | |
4036 | POSTING_READ(IER); | |
4037 | } | |
4038 | ||
4039 | static int i965_irq_postinstall(struct drm_device *dev) | |
4040 | { | |
fac5e23e | 4041 | struct drm_i915_private *dev_priv = to_i915(dev); |
bbba0a97 | 4042 | u32 enable_mask; |
a266c7d5 CW |
4043 | u32 error_mask; |
4044 | ||
a266c7d5 | 4045 | /* Unmask the interrupts that we always want on. */ |
bbba0a97 | 4046 | dev_priv->irq_mask = ~(I915_ASLE_INTERRUPT | |
adca4730 | 4047 | I915_DISPLAY_PORT_INTERRUPT | |
bbba0a97 CW |
4048 | I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | |
4049 | I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | | |
4050 | I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | | |
4051 | I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT | | |
4052 | I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT); | |
4053 | ||
4054 | enable_mask = ~dev_priv->irq_mask; | |
21ad8330 VS |
4055 | enable_mask &= ~(I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | |
4056 | I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT); | |
bbba0a97 CW |
4057 | enable_mask |= I915_USER_INTERRUPT; |
4058 | ||
91d14251 | 4059 | if (IS_G4X(dev_priv)) |
bbba0a97 | 4060 | enable_mask |= I915_BSD_USER_INTERRUPT; |
a266c7d5 | 4061 | |
b79480ba DV |
4062 | /* Interrupt setup is already guaranteed to be single-threaded, this is |
4063 | * just to make the assert_spin_locked check happy. */ | |
d6207435 | 4064 | spin_lock_irq(&dev_priv->irq_lock); |
755e9019 ID |
4065 | i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS); |
4066 | i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS); | |
4067 | i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS); | |
d6207435 | 4068 | spin_unlock_irq(&dev_priv->irq_lock); |
a266c7d5 | 4069 | |
a266c7d5 CW |
4070 | /* |
4071 | * Enable some error detection, note the instruction error mask | |
4072 | * bit is reserved, so we leave it masked. | |
4073 | */ | |
91d14251 | 4074 | if (IS_G4X(dev_priv)) { |
a266c7d5 CW |
4075 | error_mask = ~(GM45_ERROR_PAGE_TABLE | |
4076 | GM45_ERROR_MEM_PRIV | | |
4077 | GM45_ERROR_CP_PRIV | | |
4078 | I915_ERROR_MEMORY_REFRESH); | |
4079 | } else { | |
4080 | error_mask = ~(I915_ERROR_PAGE_TABLE | | |
4081 | I915_ERROR_MEMORY_REFRESH); | |
4082 | } | |
4083 | I915_WRITE(EMR, error_mask); | |
4084 | ||
4085 | I915_WRITE(IMR, dev_priv->irq_mask); | |
4086 | I915_WRITE(IER, enable_mask); | |
4087 | POSTING_READ(IER); | |
4088 | ||
0706f17c | 4089 | i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0); |
20afbda2 DV |
4090 | POSTING_READ(PORT_HOTPLUG_EN); |
4091 | ||
91d14251 | 4092 | i915_enable_asle_pipestat(dev_priv); |
20afbda2 DV |
4093 | |
4094 | return 0; | |
4095 | } | |
4096 | ||
91d14251 | 4097 | static void i915_hpd_irq_setup(struct drm_i915_private *dev_priv) |
20afbda2 | 4098 | { |
20afbda2 DV |
4099 | u32 hotplug_en; |
4100 | ||
67520415 | 4101 | lockdep_assert_held(&dev_priv->irq_lock); |
b5ea2d56 | 4102 | |
778eb334 VS |
4103 | /* Note HDMI and DP share hotplug bits */ |
4104 | /* enable bits are the same for all generations */ | |
91d14251 | 4105 | hotplug_en = intel_hpd_enabled_irqs(dev_priv, hpd_mask_i915); |
778eb334 VS |
4106 | /* Programming the CRT detection parameters tends |
4107 | to generate a spurious hotplug event about three | |
4108 | seconds later. So just do it once. | |
4109 | */ | |
91d14251 | 4110 | if (IS_G4X(dev_priv)) |
778eb334 | 4111 | hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64; |
778eb334 VS |
4112 | hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50; |
4113 | ||
4114 | /* Ignore TV since it's buggy */ | |
0706f17c | 4115 | i915_hotplug_interrupt_update_locked(dev_priv, |
f9e3dc78 JN |
4116 | HOTPLUG_INT_EN_MASK | |
4117 | CRT_HOTPLUG_VOLTAGE_COMPARE_MASK | | |
4118 | CRT_HOTPLUG_ACTIVATION_PERIOD_64, | |
4119 | hotplug_en); | |
a266c7d5 CW |
4120 | } |
4121 | ||
ff1f525e | 4122 | static irqreturn_t i965_irq_handler(int irq, void *arg) |
a266c7d5 | 4123 | { |
45a83f84 | 4124 | struct drm_device *dev = arg; |
fac5e23e | 4125 | struct drm_i915_private *dev_priv = to_i915(dev); |
a266c7d5 CW |
4126 | u32 iir, new_iir; |
4127 | u32 pipe_stats[I915_MAX_PIPES]; | |
a266c7d5 | 4128 | int ret = IRQ_NONE, pipe; |
21ad8330 VS |
4129 | u32 flip_mask = |
4130 | I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | | |
4131 | I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT; | |
a266c7d5 | 4132 | |
2dd2a883 ID |
4133 | if (!intel_irqs_enabled(dev_priv)) |
4134 | return IRQ_NONE; | |
4135 | ||
1f814dac ID |
4136 | /* IRQs are synced during runtime_suspend, we don't require a wakeref */ |
4137 | disable_rpm_wakeref_asserts(dev_priv); | |
4138 | ||
a266c7d5 CW |
4139 | iir = I915_READ(IIR); |
4140 | ||
a266c7d5 | 4141 | for (;;) { |
501e01d7 | 4142 | bool irq_received = (iir & ~flip_mask) != 0; |
2c8ba29f CW |
4143 | bool blc_event = false; |
4144 | ||
a266c7d5 CW |
4145 | /* Can't rely on pipestat interrupt bit in iir as it might |
4146 | * have been cleared after the pipestat interrupt was received. | |
4147 | * It doesn't set the bit in iir again, but it still produces | |
4148 | * interrupts (for non-MSI). | |
4149 | */ | |
222c7f51 | 4150 | spin_lock(&dev_priv->irq_lock); |
a266c7d5 | 4151 | if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT) |
aaecdf61 | 4152 | DRM_DEBUG("Command parser error, iir 0x%08x\n", iir); |
a266c7d5 | 4153 | |
055e393f | 4154 | for_each_pipe(dev_priv, pipe) { |
f0f59a00 | 4155 | i915_reg_t reg = PIPESTAT(pipe); |
a266c7d5 CW |
4156 | pipe_stats[pipe] = I915_READ(reg); |
4157 | ||
4158 | /* | |
4159 | * Clear the PIPE*STAT regs before the IIR | |
4160 | */ | |
4161 | if (pipe_stats[pipe] & 0x8000ffff) { | |
a266c7d5 | 4162 | I915_WRITE(reg, pipe_stats[pipe]); |
501e01d7 | 4163 | irq_received = true; |
a266c7d5 CW |
4164 | } |
4165 | } | |
222c7f51 | 4166 | spin_unlock(&dev_priv->irq_lock); |
a266c7d5 CW |
4167 | |
4168 | if (!irq_received) | |
4169 | break; | |
4170 | ||
4171 | ret = IRQ_HANDLED; | |
4172 | ||
4173 | /* Consume port. Then clear IIR or we'll miss events */ | |
1ae3c34c VS |
4174 | if (iir & I915_DISPLAY_PORT_INTERRUPT) { |
4175 | u32 hotplug_status = i9xx_hpd_irq_ack(dev_priv); | |
4176 | if (hotplug_status) | |
91d14251 | 4177 | i9xx_hpd_irq_handler(dev_priv, hotplug_status); |
1ae3c34c | 4178 | } |
a266c7d5 | 4179 | |
21ad8330 | 4180 | I915_WRITE(IIR, iir & ~flip_mask); |
a266c7d5 CW |
4181 | new_iir = I915_READ(IIR); /* Flush posted writes */ |
4182 | ||
a266c7d5 | 4183 | if (iir & I915_USER_INTERRUPT) |
3b3f1650 | 4184 | notify_ring(dev_priv->engine[RCS]); |
a266c7d5 | 4185 | if (iir & I915_BSD_USER_INTERRUPT) |
3b3f1650 | 4186 | notify_ring(dev_priv->engine[VCS]); |
a266c7d5 | 4187 | |
055e393f | 4188 | for_each_pipe(dev_priv, pipe) { |
5a21b665 DV |
4189 | if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS && |
4190 | i915_handle_vblank(dev_priv, pipe, pipe, iir)) | |
4191 | flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(pipe); | |
a266c7d5 CW |
4192 | |
4193 | if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS) | |
4194 | blc_event = true; | |
4356d586 DV |
4195 | |
4196 | if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS) | |
91d14251 | 4197 | i9xx_pipe_crc_irq_handler(dev_priv, pipe); |
a266c7d5 | 4198 | |
1f7247c0 DV |
4199 | if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS) |
4200 | intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe); | |
2d9d2b0b | 4201 | } |
a266c7d5 CW |
4202 | |
4203 | if (blc_event || (iir & I915_ASLE_INTERRUPT)) | |
91d14251 | 4204 | intel_opregion_asle_intr(dev_priv); |
a266c7d5 | 4205 | |
515ac2bb | 4206 | if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS) |
91d14251 | 4207 | gmbus_irq_handler(dev_priv); |
515ac2bb | 4208 | |
a266c7d5 CW |
4209 | /* With MSI, interrupts are only generated when iir |
4210 | * transitions from zero to nonzero. If another bit got | |
4211 | * set while we were handling the existing iir bits, then | |
4212 | * we would never get another interrupt. | |
4213 | * | |
4214 | * This is fine on non-MSI as well, as if we hit this path | |
4215 | * we avoid exiting the interrupt handler only to generate | |
4216 | * another one. | |
4217 | * | |
4218 | * Note that for MSI this could cause a stray interrupt report | |
4219 | * if an interrupt landed in the time between writing IIR and | |
4220 | * the posting read. This should be rare enough to never | |
4221 | * trigger the 99% of 100,000 interrupts test for disabling | |
4222 | * stray interrupts. | |
4223 | */ | |
4224 | iir = new_iir; | |
4225 | } | |
4226 | ||
1f814dac ID |
4227 | enable_rpm_wakeref_asserts(dev_priv); |
4228 | ||
a266c7d5 CW |
4229 | return ret; |
4230 | } | |
4231 | ||
4232 | static void i965_irq_uninstall(struct drm_device * dev) | |
4233 | { | |
fac5e23e | 4234 | struct drm_i915_private *dev_priv = to_i915(dev); |
a266c7d5 CW |
4235 | int pipe; |
4236 | ||
4237 | if (!dev_priv) | |
4238 | return; | |
4239 | ||
0706f17c | 4240 | i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0); |
adca4730 | 4241 | I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); |
a266c7d5 CW |
4242 | |
4243 | I915_WRITE(HWSTAM, 0xffffffff); | |
055e393f | 4244 | for_each_pipe(dev_priv, pipe) |
a266c7d5 CW |
4245 | I915_WRITE(PIPESTAT(pipe), 0); |
4246 | I915_WRITE(IMR, 0xffffffff); | |
4247 | I915_WRITE(IER, 0x0); | |
4248 | ||
055e393f | 4249 | for_each_pipe(dev_priv, pipe) |
a266c7d5 CW |
4250 | I915_WRITE(PIPESTAT(pipe), |
4251 | I915_READ(PIPESTAT(pipe)) & 0x8000ffff); | |
4252 | I915_WRITE(IIR, I915_READ(IIR)); | |
4253 | } | |
4254 | ||
fca52a55 DV |
4255 | /** |
4256 | * intel_irq_init - initializes irq support | |
4257 | * @dev_priv: i915 device instance | |
4258 | * | |
4259 | * This function initializes all the irq support including work items, timers | |
4260 | * and all the vtables. It does not setup the interrupt itself though. | |
4261 | */ | |
b963291c | 4262 | void intel_irq_init(struct drm_i915_private *dev_priv) |
f71d4af4 | 4263 | { |
91c8a326 | 4264 | struct drm_device *dev = &dev_priv->drm; |
cefcff8f | 4265 | int i; |
8b2e326d | 4266 | |
77913b39 JN |
4267 | intel_hpd_init_work(dev_priv); |
4268 | ||
c6a828d3 | 4269 | INIT_WORK(&dev_priv->rps.work, gen6_pm_rps_work); |
cefcff8f | 4270 | |
a4da4fa4 | 4271 | INIT_WORK(&dev_priv->l3_parity.error_work, ivybridge_parity_work); |
cefcff8f JL |
4272 | for (i = 0; i < MAX_L3_SLICES; ++i) |
4273 | dev_priv->l3_parity.remap_info[i] = NULL; | |
8b2e326d | 4274 | |
4805fe82 | 4275 | if (HAS_GUC_SCHED(dev_priv)) |
26705e20 SAK |
4276 | dev_priv->pm_guc_events = GEN9_GUC_TO_HOST_INT_EVENT; |
4277 | ||
a6706b45 | 4278 | /* Let's track the enabled rps events */ |
666a4537 | 4279 | if (IS_VALLEYVIEW(dev_priv)) |
6c65a587 | 4280 | /* WaGsvRC0ResidencyMethod:vlv */ |
e0e8c7cb | 4281 | dev_priv->pm_rps_events = GEN6_PM_RP_UP_EI_EXPIRED; |
31685c25 D |
4282 | else |
4283 | dev_priv->pm_rps_events = GEN6_PM_RPS_EVENTS; | |
a6706b45 | 4284 | |
5dd04556 | 4285 | dev_priv->rps.pm_intrmsk_mbz = 0; |
1800ad25 SAK |
4286 | |
4287 | /* | |
acf2dc22 | 4288 | * SNB,IVB,HSW can while VLV,CHV may hard hang on looping batchbuffer |
1800ad25 SAK |
4289 | * if GEN6_PM_UP_EI_EXPIRED is masked. |
4290 | * | |
4291 | * TODO: verify if this can be reproduced on VLV,CHV. | |
4292 | */ | |
acf2dc22 | 4293 | if (INTEL_INFO(dev_priv)->gen <= 7) |
5dd04556 | 4294 | dev_priv->rps.pm_intrmsk_mbz |= GEN6_PM_RP_UP_EI_EXPIRED; |
1800ad25 SAK |
4295 | |
4296 | if (INTEL_INFO(dev_priv)->gen >= 8) | |
655d49ef | 4297 | dev_priv->rps.pm_intrmsk_mbz |= GEN8_PMINTR_DISABLE_REDIRECT_TO_GUC; |
1800ad25 | 4298 | |
b963291c | 4299 | if (IS_GEN2(dev_priv)) { |
4194c088 | 4300 | /* Gen2 doesn't have a hardware frame counter */ |
4cdb83ec | 4301 | dev->max_vblank_count = 0; |
b963291c | 4302 | } else if (IS_G4X(dev_priv) || INTEL_INFO(dev_priv)->gen >= 5) { |
f71d4af4 | 4303 | dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */ |
fd8f507c | 4304 | dev->driver->get_vblank_counter = g4x_get_vblank_counter; |
391f75e2 VS |
4305 | } else { |
4306 | dev->driver->get_vblank_counter = i915_get_vblank_counter; | |
4307 | dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */ | |
f71d4af4 JB |
4308 | } |
4309 | ||
21da2700 VS |
4310 | /* |
4311 | * Opt out of the vblank disable timer on everything except gen2. | |
4312 | * Gen2 doesn't have a hardware frame counter and so depends on | |
4313 | * vblank interrupts to produce sane vblank seuquence numbers. | |
4314 | */ | |
b963291c | 4315 | if (!IS_GEN2(dev_priv)) |
21da2700 VS |
4316 | dev->vblank_disable_immediate = true; |
4317 | ||
262fd485 CW |
4318 | /* Most platforms treat the display irq block as an always-on |
4319 | * power domain. vlv/chv can disable it at runtime and need | |
4320 | * special care to avoid writing any of the display block registers | |
4321 | * outside of the power domain. We defer setting up the display irqs | |
4322 | * in this case to the runtime pm. | |
4323 | */ | |
4324 | dev_priv->display_irqs_enabled = true; | |
4325 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) | |
4326 | dev_priv->display_irqs_enabled = false; | |
4327 | ||
317eaa95 L |
4328 | dev_priv->hotplug.hpd_storm_threshold = HPD_STORM_DEFAULT_THRESHOLD; |
4329 | ||
1bf6ad62 | 4330 | dev->driver->get_vblank_timestamp = drm_calc_vbltimestamp_from_scanoutpos; |
f3a5c3f6 | 4331 | dev->driver->get_scanout_position = i915_get_crtc_scanoutpos; |
f71d4af4 | 4332 | |
b963291c | 4333 | if (IS_CHERRYVIEW(dev_priv)) { |
43f328d7 VS |
4334 | dev->driver->irq_handler = cherryview_irq_handler; |
4335 | dev->driver->irq_preinstall = cherryview_irq_preinstall; | |
4336 | dev->driver->irq_postinstall = cherryview_irq_postinstall; | |
4337 | dev->driver->irq_uninstall = cherryview_irq_uninstall; | |
86e83e35 CW |
4338 | dev->driver->enable_vblank = i965_enable_vblank; |
4339 | dev->driver->disable_vblank = i965_disable_vblank; | |
43f328d7 | 4340 | dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup; |
b963291c | 4341 | } else if (IS_VALLEYVIEW(dev_priv)) { |
7e231dbe JB |
4342 | dev->driver->irq_handler = valleyview_irq_handler; |
4343 | dev->driver->irq_preinstall = valleyview_irq_preinstall; | |
4344 | dev->driver->irq_postinstall = valleyview_irq_postinstall; | |
4345 | dev->driver->irq_uninstall = valleyview_irq_uninstall; | |
86e83e35 CW |
4346 | dev->driver->enable_vblank = i965_enable_vblank; |
4347 | dev->driver->disable_vblank = i965_disable_vblank; | |
fa00abe0 | 4348 | dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup; |
b963291c | 4349 | } else if (INTEL_INFO(dev_priv)->gen >= 8) { |
abd58f01 | 4350 | dev->driver->irq_handler = gen8_irq_handler; |
723761b8 | 4351 | dev->driver->irq_preinstall = gen8_irq_reset; |
abd58f01 BW |
4352 | dev->driver->irq_postinstall = gen8_irq_postinstall; |
4353 | dev->driver->irq_uninstall = gen8_irq_uninstall; | |
4354 | dev->driver->enable_vblank = gen8_enable_vblank; | |
4355 | dev->driver->disable_vblank = gen8_disable_vblank; | |
cc3f90f0 | 4356 | if (IS_GEN9_LP(dev_priv)) |
e0a20ad7 | 4357 | dev_priv->display.hpd_irq_setup = bxt_hpd_irq_setup; |
7b22b8c4 RV |
4358 | else if (HAS_PCH_SPT(dev_priv) || HAS_PCH_KBP(dev_priv) || |
4359 | HAS_PCH_CNP(dev_priv)) | |
6dbf30ce VS |
4360 | dev_priv->display.hpd_irq_setup = spt_hpd_irq_setup; |
4361 | else | |
3a3b3c7d | 4362 | dev_priv->display.hpd_irq_setup = ilk_hpd_irq_setup; |
6e266956 | 4363 | } else if (HAS_PCH_SPLIT(dev_priv)) { |
f71d4af4 | 4364 | dev->driver->irq_handler = ironlake_irq_handler; |
723761b8 | 4365 | dev->driver->irq_preinstall = ironlake_irq_reset; |
f71d4af4 JB |
4366 | dev->driver->irq_postinstall = ironlake_irq_postinstall; |
4367 | dev->driver->irq_uninstall = ironlake_irq_uninstall; | |
4368 | dev->driver->enable_vblank = ironlake_enable_vblank; | |
4369 | dev->driver->disable_vblank = ironlake_disable_vblank; | |
23bb4cb5 | 4370 | dev_priv->display.hpd_irq_setup = ilk_hpd_irq_setup; |
f71d4af4 | 4371 | } else { |
7e22dbbb | 4372 | if (IS_GEN2(dev_priv)) { |
c2798b19 CW |
4373 | dev->driver->irq_preinstall = i8xx_irq_preinstall; |
4374 | dev->driver->irq_postinstall = i8xx_irq_postinstall; | |
4375 | dev->driver->irq_handler = i8xx_irq_handler; | |
4376 | dev->driver->irq_uninstall = i8xx_irq_uninstall; | |
86e83e35 CW |
4377 | dev->driver->enable_vblank = i8xx_enable_vblank; |
4378 | dev->driver->disable_vblank = i8xx_disable_vblank; | |
7e22dbbb | 4379 | } else if (IS_GEN3(dev_priv)) { |
a266c7d5 CW |
4380 | dev->driver->irq_preinstall = i915_irq_preinstall; |
4381 | dev->driver->irq_postinstall = i915_irq_postinstall; | |
4382 | dev->driver->irq_uninstall = i915_irq_uninstall; | |
4383 | dev->driver->irq_handler = i915_irq_handler; | |
86e83e35 CW |
4384 | dev->driver->enable_vblank = i8xx_enable_vblank; |
4385 | dev->driver->disable_vblank = i8xx_disable_vblank; | |
c2798b19 | 4386 | } else { |
a266c7d5 CW |
4387 | dev->driver->irq_preinstall = i965_irq_preinstall; |
4388 | dev->driver->irq_postinstall = i965_irq_postinstall; | |
4389 | dev->driver->irq_uninstall = i965_irq_uninstall; | |
4390 | dev->driver->irq_handler = i965_irq_handler; | |
86e83e35 CW |
4391 | dev->driver->enable_vblank = i965_enable_vblank; |
4392 | dev->driver->disable_vblank = i965_disable_vblank; | |
c2798b19 | 4393 | } |
778eb334 VS |
4394 | if (I915_HAS_HOTPLUG(dev_priv)) |
4395 | dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup; | |
f71d4af4 JB |
4396 | } |
4397 | } | |
20afbda2 | 4398 | |
cefcff8f JL |
4399 | /** |
4400 | * intel_irq_fini - deinitializes IRQ support | |
4401 | * @i915: i915 device instance | |
4402 | * | |
4403 | * This function deinitializes all the IRQ support. | |
4404 | */ | |
4405 | void intel_irq_fini(struct drm_i915_private *i915) | |
4406 | { | |
4407 | int i; | |
4408 | ||
4409 | for (i = 0; i < MAX_L3_SLICES; ++i) | |
4410 | kfree(i915->l3_parity.remap_info[i]); | |
4411 | } | |
4412 | ||
fca52a55 DV |
4413 | /** |
4414 | * intel_irq_install - enables the hardware interrupt | |
4415 | * @dev_priv: i915 device instance | |
4416 | * | |
4417 | * This function enables the hardware interrupt handling, but leaves the hotplug | |
4418 | * handling still disabled. It is called after intel_irq_init(). | |
4419 | * | |
4420 | * In the driver load and resume code we need working interrupts in a few places | |
4421 | * but don't want to deal with the hassle of concurrent probe and hotplug | |
4422 | * workers. Hence the split into this two-stage approach. | |
4423 | */ | |
2aeb7d3a DV |
4424 | int intel_irq_install(struct drm_i915_private *dev_priv) |
4425 | { | |
4426 | /* | |
4427 | * We enable some interrupt sources in our postinstall hooks, so mark | |
4428 | * interrupts as enabled _before_ actually enabling them to avoid | |
4429 | * special cases in our ordering checks. | |
4430 | */ | |
4431 | dev_priv->pm.irqs_enabled = true; | |
4432 | ||
91c8a326 | 4433 | return drm_irq_install(&dev_priv->drm, dev_priv->drm.pdev->irq); |
2aeb7d3a DV |
4434 | } |
4435 | ||
fca52a55 DV |
4436 | /** |
4437 | * intel_irq_uninstall - finilizes all irq handling | |
4438 | * @dev_priv: i915 device instance | |
4439 | * | |
4440 | * This stops interrupt and hotplug handling and unregisters and frees all | |
4441 | * resources acquired in the init functions. | |
4442 | */ | |
2aeb7d3a DV |
4443 | void intel_irq_uninstall(struct drm_i915_private *dev_priv) |
4444 | { | |
91c8a326 | 4445 | drm_irq_uninstall(&dev_priv->drm); |
2aeb7d3a DV |
4446 | intel_hpd_cancel_work(dev_priv); |
4447 | dev_priv->pm.irqs_enabled = false; | |
4448 | } | |
4449 | ||
fca52a55 DV |
4450 | /** |
4451 | * intel_runtime_pm_disable_interrupts - runtime interrupt disabling | |
4452 | * @dev_priv: i915 device instance | |
4453 | * | |
4454 | * This function is used to disable interrupts at runtime, both in the runtime | |
4455 | * pm and the system suspend/resume code. | |
4456 | */ | |
b963291c | 4457 | void intel_runtime_pm_disable_interrupts(struct drm_i915_private *dev_priv) |
c67a470b | 4458 | { |
91c8a326 | 4459 | dev_priv->drm.driver->irq_uninstall(&dev_priv->drm); |
2aeb7d3a | 4460 | dev_priv->pm.irqs_enabled = false; |
91c8a326 | 4461 | synchronize_irq(dev_priv->drm.irq); |
c67a470b PZ |
4462 | } |
4463 | ||
fca52a55 DV |
4464 | /** |
4465 | * intel_runtime_pm_enable_interrupts - runtime interrupt enabling | |
4466 | * @dev_priv: i915 device instance | |
4467 | * | |
4468 | * This function is used to enable interrupts at runtime, both in the runtime | |
4469 | * pm and the system suspend/resume code. | |
4470 | */ | |
b963291c | 4471 | void intel_runtime_pm_enable_interrupts(struct drm_i915_private *dev_priv) |
c67a470b | 4472 | { |
2aeb7d3a | 4473 | dev_priv->pm.irqs_enabled = true; |
91c8a326 CW |
4474 | dev_priv->drm.driver->irq_preinstall(&dev_priv->drm); |
4475 | dev_priv->drm.driver->irq_postinstall(&dev_priv->drm); | |
c67a470b | 4476 | } |