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42f5551d CW |
1 | /* |
2 | * Copyright © 2016 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | */ | |
24 | ||
a09d0ba1 | 25 | #include <linux/console.h> |
42f5551d CW |
26 | #include <linux/vgaarb.h> |
27 | #include <linux/vga_switcheroo.h> | |
28 | ||
29 | #include "i915_drv.h" | |
953c7f82 | 30 | #include "i915_selftest.h" |
42f5551d CW |
31 | |
32 | #define GEN_DEFAULT_PIPEOFFSETS \ | |
33 | .pipe_offsets = { PIPE_A_OFFSET, PIPE_B_OFFSET, \ | |
34 | PIPE_C_OFFSET, PIPE_EDP_OFFSET }, \ | |
35 | .trans_offsets = { TRANSCODER_A_OFFSET, TRANSCODER_B_OFFSET, \ | |
36 | TRANSCODER_C_OFFSET, TRANSCODER_EDP_OFFSET }, \ | |
37 | .palette_offsets = { PALETTE_A_OFFSET, PALETTE_B_OFFSET } | |
38 | ||
39 | #define GEN_CHV_PIPEOFFSETS \ | |
40 | .pipe_offsets = { PIPE_A_OFFSET, PIPE_B_OFFSET, \ | |
41 | CHV_PIPE_C_OFFSET }, \ | |
42 | .trans_offsets = { TRANSCODER_A_OFFSET, TRANSCODER_B_OFFSET, \ | |
43 | CHV_TRANSCODER_C_OFFSET, }, \ | |
44 | .palette_offsets = { PALETTE_A_OFFSET, PALETTE_B_OFFSET, \ | |
45 | CHV_PALETTE_C_OFFSET } | |
46 | ||
47 | #define CURSOR_OFFSETS \ | |
48 | .cursor_offsets = { CURSOR_A_OFFSET, CURSOR_B_OFFSET, CHV_CURSOR_C_OFFSET } | |
49 | ||
50 | #define IVB_CURSOR_OFFSETS \ | |
51 | .cursor_offsets = { CURSOR_A_OFFSET, IVB_CURSOR_B_OFFSET, IVB_CURSOR_C_OFFSET } | |
52 | ||
53 | #define BDW_COLORS \ | |
54 | .color = { .degamma_lut_size = 512, .gamma_lut_size = 512 } | |
55 | #define CHV_COLORS \ | |
56 | .color = { .degamma_lut_size = 65, .gamma_lut_size = 257 } | |
4672770d RV |
57 | #define GLK_COLORS \ |
58 | .color = { .degamma_lut_size = 0, .gamma_lut_size = 1024 } | |
42f5551d | 59 | |
a5ce929b | 60 | /* Keep in gen based order, and chronological order within a gen */ |
0eec8dc7 CS |
61 | #define GEN2_FEATURES \ |
62 | .gen = 2, .num_pipes = 1, \ | |
63 | .has_overlay = 1, .overlay_needs_physical = 1, \ | |
804b8712 | 64 | .has_gmch_display = 1, \ |
3177659a | 65 | .hws_needs_physical = 1, \ |
f4ce766f | 66 | .unfenced_needs_alignment = 1, \ |
0eec8dc7 | 67 | .ring_mask = RENDER_RING, \ |
5d95c248 | 68 | .has_snoop = true, \ |
0eec8dc7 CS |
69 | GEN_DEFAULT_PIPEOFFSETS, \ |
70 | CURSOR_OFFSETS | |
71 | ||
5b54eddd | 72 | static const struct intel_device_info intel_i830_info __initconst = { |
0eec8dc7 | 73 | GEN2_FEATURES, |
2e0d26f8 | 74 | .platform = INTEL_I830, |
0eec8dc7 CS |
75 | .is_mobile = 1, .cursor_needs_physical = 1, |
76 | .num_pipes = 2, /* legal, last one wins */ | |
42f5551d CW |
77 | }; |
78 | ||
5b54eddd | 79 | static const struct intel_device_info intel_i845g_info __initconst = { |
0eec8dc7 | 80 | GEN2_FEATURES, |
2e0d26f8 | 81 | .platform = INTEL_I845G, |
42f5551d CW |
82 | }; |
83 | ||
5b54eddd | 84 | static const struct intel_device_info intel_i85x_info __initconst = { |
0eec8dc7 | 85 | GEN2_FEATURES, |
2e0d26f8 | 86 | .platform = INTEL_I85X, .is_mobile = 1, |
0eec8dc7 | 87 | .num_pipes = 2, /* legal, last one wins */ |
42f5551d | 88 | .cursor_needs_physical = 1, |
42f5551d | 89 | .has_fbc = 1, |
42f5551d CW |
90 | }; |
91 | ||
5b54eddd | 92 | static const struct intel_device_info intel_i865g_info __initconst = { |
0eec8dc7 | 93 | GEN2_FEATURES, |
2e0d26f8 | 94 | .platform = INTEL_I865G, |
42f5551d CW |
95 | }; |
96 | ||
54d2a6a1 CS |
97 | #define GEN3_FEATURES \ |
98 | .gen = 3, .num_pipes = 2, \ | |
804b8712 | 99 | .has_gmch_display = 1, \ |
54d2a6a1 | 100 | .ring_mask = RENDER_RING, \ |
5d95c248 | 101 | .has_snoop = true, \ |
54d2a6a1 CS |
102 | GEN_DEFAULT_PIPEOFFSETS, \ |
103 | CURSOR_OFFSETS | |
104 | ||
5b54eddd | 105 | static const struct intel_device_info intel_i915g_info __initconst = { |
54d2a6a1 | 106 | GEN3_FEATURES, |
2e0d26f8 | 107 | .platform = INTEL_I915G, .cursor_needs_physical = 1, |
42f5551d | 108 | .has_overlay = 1, .overlay_needs_physical = 1, |
3177659a | 109 | .hws_needs_physical = 1, |
f4ce766f | 110 | .unfenced_needs_alignment = 1, |
42f5551d | 111 | }; |
a5ce929b | 112 | |
5b54eddd | 113 | static const struct intel_device_info intel_i915gm_info __initconst = { |
54d2a6a1 | 114 | GEN3_FEATURES, |
2e0d26f8 | 115 | .platform = INTEL_I915GM, |
54d2a6a1 | 116 | .is_mobile = 1, |
42f5551d CW |
117 | .cursor_needs_physical = 1, |
118 | .has_overlay = 1, .overlay_needs_physical = 1, | |
119 | .supports_tv = 1, | |
120 | .has_fbc = 1, | |
3177659a | 121 | .hws_needs_physical = 1, |
f4ce766f | 122 | .unfenced_needs_alignment = 1, |
42f5551d | 123 | }; |
a5ce929b | 124 | |
5b54eddd | 125 | static const struct intel_device_info intel_i945g_info __initconst = { |
54d2a6a1 | 126 | GEN3_FEATURES, |
2e0d26f8 | 127 | .platform = INTEL_I945G, |
54d2a6a1 | 128 | .has_hotplug = 1, .cursor_needs_physical = 1, |
42f5551d | 129 | .has_overlay = 1, .overlay_needs_physical = 1, |
3177659a | 130 | .hws_needs_physical = 1, |
f4ce766f | 131 | .unfenced_needs_alignment = 1, |
42f5551d | 132 | }; |
a5ce929b | 133 | |
5b54eddd | 134 | static const struct intel_device_info intel_i945gm_info __initconst = { |
54d2a6a1 | 135 | GEN3_FEATURES, |
2e0d26f8 | 136 | .platform = INTEL_I945GM, .is_mobile = 1, |
42f5551d CW |
137 | .has_hotplug = 1, .cursor_needs_physical = 1, |
138 | .has_overlay = 1, .overlay_needs_physical = 1, | |
139 | .supports_tv = 1, | |
140 | .has_fbc = 1, | |
3177659a | 141 | .hws_needs_physical = 1, |
f4ce766f | 142 | .unfenced_needs_alignment = 1, |
42f5551d CW |
143 | }; |
144 | ||
5b54eddd | 145 | static const struct intel_device_info intel_g33_info __initconst = { |
a5ce929b JN |
146 | GEN3_FEATURES, |
147 | .platform = INTEL_G33, | |
148 | .has_hotplug = 1, | |
149 | .has_overlay = 1, | |
150 | }; | |
151 | ||
5b54eddd | 152 | static const struct intel_device_info intel_pineview_info __initconst = { |
a5ce929b | 153 | GEN3_FEATURES, |
73f67aa8 | 154 | .platform = INTEL_PINEVIEW, .is_mobile = 1, |
a5ce929b JN |
155 | .has_hotplug = 1, |
156 | .has_overlay = 1, | |
157 | }; | |
158 | ||
4d495bea CS |
159 | #define GEN4_FEATURES \ |
160 | .gen = 4, .num_pipes = 2, \ | |
161 | .has_hotplug = 1, \ | |
804b8712 | 162 | .has_gmch_display = 1, \ |
4d495bea | 163 | .ring_mask = RENDER_RING, \ |
5d95c248 | 164 | .has_snoop = true, \ |
4d495bea CS |
165 | GEN_DEFAULT_PIPEOFFSETS, \ |
166 | CURSOR_OFFSETS | |
167 | ||
5b54eddd | 168 | static const struct intel_device_info intel_i965g_info __initconst = { |
4d495bea | 169 | GEN4_FEATURES, |
c0f86832 | 170 | .platform = INTEL_I965G, |
42f5551d | 171 | .has_overlay = 1, |
3177659a | 172 | .hws_needs_physical = 1, |
df0700e5 | 173 | .has_snoop = false, |
42f5551d CW |
174 | }; |
175 | ||
5b54eddd | 176 | static const struct intel_device_info intel_i965gm_info __initconst = { |
4d495bea | 177 | GEN4_FEATURES, |
c0f86832 | 178 | .platform = INTEL_I965GM, |
4d495bea | 179 | .is_mobile = 1, .has_fbc = 1, |
42f5551d CW |
180 | .has_overlay = 1, |
181 | .supports_tv = 1, | |
3177659a | 182 | .hws_needs_physical = 1, |
df0700e5 | 183 | .has_snoop = false, |
42f5551d CW |
184 | }; |
185 | ||
5b54eddd | 186 | static const struct intel_device_info intel_g45_info __initconst = { |
4d495bea | 187 | GEN4_FEATURES, |
f69c11ae | 188 | .platform = INTEL_G45, |
4d495bea | 189 | .has_pipe_cxsr = 1, |
42f5551d | 190 | .ring_mask = RENDER_RING | BSD_RING, |
42f5551d CW |
191 | }; |
192 | ||
5b54eddd | 193 | static const struct intel_device_info intel_gm45_info __initconst = { |
4d495bea | 194 | GEN4_FEATURES, |
f69c11ae | 195 | .platform = INTEL_GM45, |
3177659a | 196 | .is_mobile = 1, .has_fbc = 1, |
4d495bea | 197 | .has_pipe_cxsr = 1, |
42f5551d CW |
198 | .supports_tv = 1, |
199 | .ring_mask = RENDER_RING | BSD_RING, | |
42f5551d CW |
200 | }; |
201 | ||
a1323380 CS |
202 | #define GEN5_FEATURES \ |
203 | .gen = 5, .num_pipes = 2, \ | |
3177659a | 204 | .has_hotplug = 1, \ |
a1323380 | 205 | .ring_mask = RENDER_RING | BSD_RING, \ |
5d95c248 | 206 | .has_snoop = true, \ |
a1323380 CS |
207 | GEN_DEFAULT_PIPEOFFSETS, \ |
208 | CURSOR_OFFSETS | |
209 | ||
5b54eddd | 210 | static const struct intel_device_info intel_ironlake_d_info __initconst = { |
a1323380 | 211 | GEN5_FEATURES, |
2e0d26f8 | 212 | .platform = INTEL_IRONLAKE, |
42f5551d CW |
213 | }; |
214 | ||
5b54eddd | 215 | static const struct intel_device_info intel_ironlake_m_info __initconst = { |
a1323380 | 216 | GEN5_FEATURES, |
2e0d26f8 | 217 | .platform = INTEL_IRONLAKE, |
c2d1a0ce | 218 | .is_mobile = 1, .has_fbc = 1, |
42f5551d CW |
219 | }; |
220 | ||
07db6be7 CS |
221 | #define GEN6_FEATURES \ |
222 | .gen = 6, .num_pipes = 2, \ | |
3177659a | 223 | .has_hotplug = 1, \ |
07db6be7 CS |
224 | .has_fbc = 1, \ |
225 | .ring_mask = RENDER_RING | BSD_RING | BLT_RING, \ | |
226 | .has_llc = 1, \ | |
86f3624b | 227 | .has_rc6 = 1, \ |
33b5bf82 | 228 | .has_rc6p = 1, \ |
9e1d0e60 | 229 | .has_aliasing_ppgtt = 1, \ |
07db6be7 CS |
230 | GEN_DEFAULT_PIPEOFFSETS, \ |
231 | CURSOR_OFFSETS | |
232 | ||
0890540e LL |
233 | #define SNB_D_PLATFORM \ |
234 | GEN6_FEATURES, \ | |
235 | .platform = INTEL_SANDYBRIDGE | |
236 | ||
5b54eddd | 237 | static const struct intel_device_info intel_sandybridge_d_gt1_info __initconst = { |
0890540e LL |
238 | SNB_D_PLATFORM, |
239 | .gt = 1, | |
42f5551d CW |
240 | }; |
241 | ||
5b54eddd | 242 | static const struct intel_device_info intel_sandybridge_d_gt2_info __initconst = { |
0890540e LL |
243 | SNB_D_PLATFORM, |
244 | .gt = 2, | |
245 | }; | |
246 | ||
247 | #define SNB_M_PLATFORM \ | |
248 | GEN6_FEATURES, \ | |
249 | .platform = INTEL_SANDYBRIDGE, \ | |
250 | .is_mobile = 1 | |
251 | ||
252 | ||
5b54eddd | 253 | static const struct intel_device_info intel_sandybridge_m_gt1_info __initconst = { |
0890540e LL |
254 | SNB_M_PLATFORM, |
255 | .gt = 1, | |
256 | }; | |
257 | ||
5b54eddd | 258 | static const struct intel_device_info intel_sandybridge_m_gt2_info __initconst = { |
0890540e LL |
259 | SNB_M_PLATFORM, |
260 | .gt = 2, | |
42f5551d CW |
261 | }; |
262 | ||
263 | #define GEN7_FEATURES \ | |
264 | .gen = 7, .num_pipes = 3, \ | |
3177659a | 265 | .has_hotplug = 1, \ |
42f5551d CW |
266 | .has_fbc = 1, \ |
267 | .ring_mask = RENDER_RING | BSD_RING | BLT_RING, \ | |
268 | .has_llc = 1, \ | |
86f3624b | 269 | .has_rc6 = 1, \ |
33b5bf82 | 270 | .has_rc6p = 1, \ |
9e1d0e60 MT |
271 | .has_aliasing_ppgtt = 1, \ |
272 | .has_full_ppgtt = 1, \ | |
42f5551d CW |
273 | GEN_DEFAULT_PIPEOFFSETS, \ |
274 | IVB_CURSOR_OFFSETS | |
275 | ||
0890540e LL |
276 | #define IVB_D_PLATFORM \ |
277 | GEN7_FEATURES, \ | |
278 | .platform = INTEL_IVYBRIDGE, \ | |
279 | .has_l3_dpf = 1 | |
280 | ||
5b54eddd | 281 | static const struct intel_device_info intel_ivybridge_d_gt1_info __initconst = { |
0890540e LL |
282 | IVB_D_PLATFORM, |
283 | .gt = 1, | |
42f5551d CW |
284 | }; |
285 | ||
5b54eddd | 286 | static const struct intel_device_info intel_ivybridge_d_gt2_info __initconst = { |
0890540e LL |
287 | IVB_D_PLATFORM, |
288 | .gt = 2, | |
289 | }; | |
290 | ||
291 | #define IVB_M_PLATFORM \ | |
292 | GEN7_FEATURES, \ | |
293 | .platform = INTEL_IVYBRIDGE, \ | |
294 | .is_mobile = 1, \ | |
295 | .has_l3_dpf = 1 | |
296 | ||
5b54eddd | 297 | static const struct intel_device_info intel_ivybridge_m_gt1_info __initconst = { |
0890540e LL |
298 | IVB_M_PLATFORM, |
299 | .gt = 1, | |
300 | }; | |
301 | ||
5b54eddd | 302 | static const struct intel_device_info intel_ivybridge_m_gt2_info __initconst = { |
0890540e LL |
303 | IVB_M_PLATFORM, |
304 | .gt = 2, | |
42f5551d CW |
305 | }; |
306 | ||
5b54eddd | 307 | static const struct intel_device_info intel_ivybridge_q_info __initconst = { |
42f5551d | 308 | GEN7_FEATURES, |
2e0d26f8 | 309 | .platform = INTEL_IVYBRIDGE, |
0890540e | 310 | .gt = 2, |
42f5551d | 311 | .num_pipes = 0, /* legal, last one wins */ |
ca9c4523 | 312 | .has_l3_dpf = 1, |
42f5551d CW |
313 | }; |
314 | ||
5b54eddd | 315 | static const struct intel_device_info intel_valleyview_info __initconst = { |
2e0d26f8 | 316 | .platform = INTEL_VALLEYVIEW, |
eb6f771b RV |
317 | .gen = 7, |
318 | .is_lp = 1, | |
319 | .num_pipes = 2, | |
320 | .has_psr = 1, | |
321 | .has_runtime_pm = 1, | |
322 | .has_rc6 = 1, | |
eb6f771b RV |
323 | .has_gmch_display = 1, |
324 | .has_hotplug = 1, | |
325 | .has_aliasing_ppgtt = 1, | |
326 | .has_full_ppgtt = 1, | |
5d95c248 | 327 | .has_snoop = true, |
eb6f771b RV |
328 | .ring_mask = RENDER_RING | BSD_RING | BLT_RING, |
329 | .display_mmio_offset = VLV_DISPLAY_BASE, | |
330 | GEN_DEFAULT_PIPEOFFSETS, | |
331 | CURSOR_OFFSETS | |
42f5551d CW |
332 | }; |
333 | ||
42a3ae88 | 334 | #define G75_FEATURES \ |
42f5551d CW |
335 | GEN7_FEATURES, \ |
336 | .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, \ | |
337 | .has_ddi = 1, \ | |
6e3b84d8 | 338 | .has_fpga_dbg = 1, \ |
4aa4c23f | 339 | .has_psr = 1, \ |
53233f08 | 340 | .has_resource_streamer = 1, \ |
1d3fe53b | 341 | .has_dp_mst = 1, \ |
33b5bf82 | 342 | .has_rc6p = 0 /* RC6p removed-by HSW */, \ |
4aa4c23f | 343 | .has_runtime_pm = 1 |
42f5551d | 344 | |
0890540e | 345 | #define HSW_PLATFORM \ |
42a3ae88 | 346 | G75_FEATURES, \ |
0890540e LL |
347 | .platform = INTEL_HASWELL, \ |
348 | .has_l3_dpf = 1 | |
349 | ||
5b54eddd | 350 | static const struct intel_device_info intel_haswell_gt1_info __initconst = { |
0890540e LL |
351 | HSW_PLATFORM, |
352 | .gt = 1, | |
353 | }; | |
354 | ||
5b54eddd | 355 | static const struct intel_device_info intel_haswell_gt2_info __initconst = { |
0890540e LL |
356 | HSW_PLATFORM, |
357 | .gt = 2, | |
358 | }; | |
359 | ||
5b54eddd | 360 | static const struct intel_device_info intel_haswell_gt3_info __initconst = { |
0890540e LL |
361 | HSW_PLATFORM, |
362 | .gt = 3, | |
42f5551d CW |
363 | }; |
364 | ||
42a3ae88 RV |
365 | #define GEN8_FEATURES \ |
366 | G75_FEATURES, \ | |
4586f1d0 | 367 | BDW_COLORS, \ |
dfc5148f | 368 | .has_logical_ring_contexts = 1, \ |
9e1d0e60 | 369 | .has_full_48bit_ppgtt = 1, \ |
142bc7d9 MT |
370 | .has_64bit_reloc = 1, \ |
371 | .has_reset_engine = 1 | |
42f5551d | 372 | |
94829de4 | 373 | #define BDW_PLATFORM \ |
42a3ae88 | 374 | GEN8_FEATURES, \ |
94829de4 RV |
375 | .gen = 8, \ |
376 | .platform = INTEL_BROADWELL | |
377 | ||
5b54eddd | 378 | static const struct intel_device_info intel_broadwell_gt1_info __initconst = { |
0890540e LL |
379 | BDW_PLATFORM, |
380 | .gt = 1, | |
381 | }; | |
382 | ||
5b54eddd | 383 | static const struct intel_device_info intel_broadwell_gt2_info __initconst = { |
94829de4 | 384 | BDW_PLATFORM, |
0890540e LL |
385 | .gt = 2, |
386 | }; | |
387 | ||
5b54eddd | 388 | static const struct intel_device_info intel_broadwell_rsvd_info __initconst = { |
0890540e LL |
389 | BDW_PLATFORM, |
390 | .gt = 3, | |
391 | /* According to the device ID those devices are GT3, they were | |
392 | * previously treated as not GT3, keep it like that. | |
393 | */ | |
42f5551d CW |
394 | }; |
395 | ||
5b54eddd | 396 | static const struct intel_device_info intel_broadwell_gt3_info __initconst = { |
94829de4 | 397 | BDW_PLATFORM, |
0890540e | 398 | .gt = 3, |
42f5551d CW |
399 | .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING, |
400 | }; | |
401 | ||
5b54eddd | 402 | static const struct intel_device_info intel_cherryview_info __initconst = { |
42f5551d | 403 | .gen = 8, .num_pipes = 3, |
3177659a | 404 | .has_hotplug = 1, |
8727dc09 | 405 | .is_lp = 1, |
42f5551d | 406 | .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, |
2e0d26f8 | 407 | .platform = INTEL_CHERRYVIEW, |
dfc5148f | 408 | .has_64bit_reloc = 1, |
6e3b84d8 | 409 | .has_psr = 1, |
4aa4c23f | 410 | .has_runtime_pm = 1, |
53233f08 | 411 | .has_resource_streamer = 1, |
86f3624b | 412 | .has_rc6 = 1, |
4586f1d0 | 413 | .has_logical_ring_contexts = 1, |
804b8712 | 414 | .has_gmch_display = 1, |
9e1d0e60 MT |
415 | .has_aliasing_ppgtt = 1, |
416 | .has_full_ppgtt = 1, | |
142bc7d9 | 417 | .has_reset_engine = 1, |
5d95c248 | 418 | .has_snoop = true, |
42f5551d CW |
419 | .display_mmio_offset = VLV_DISPLAY_BASE, |
420 | GEN_CHV_PIPEOFFSETS, | |
421 | CURSOR_OFFSETS, | |
422 | CHV_COLORS, | |
423 | }; | |
424 | ||
42a3ae88 RV |
425 | #define GEN9_FEATURES \ |
426 | GEN8_FEATURES, \ | |
94829de4 RV |
427 | .has_csr = 1, \ |
428 | .has_guc = 1, \ | |
4d6ef0da | 429 | .has_ipc = 1, \ |
94829de4 RV |
430 | .ddb_size = 896 |
431 | ||
42a3ae88 RV |
432 | #define SKL_PLATFORM \ |
433 | GEN9_FEATURES, \ | |
434 | .gen = 9, \ | |
435 | .platform = INTEL_SKYLAKE | |
436 | ||
5b54eddd | 437 | static const struct intel_device_info intel_skylake_gt1_info __initconst = { |
94829de4 | 438 | SKL_PLATFORM, |
0890540e | 439 | .gt = 1, |
42f5551d CW |
440 | }; |
441 | ||
5b54eddd | 442 | static const struct intel_device_info intel_skylake_gt2_info __initconst = { |
94829de4 | 443 | SKL_PLATFORM, |
0890540e LL |
444 | .gt = 2, |
445 | }; | |
446 | ||
447 | #define SKL_GT3_PLUS_PLATFORM \ | |
448 | SKL_PLATFORM, \ | |
449 | .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING | |
450 | ||
451 | ||
5b54eddd | 452 | static const struct intel_device_info intel_skylake_gt3_info __initconst = { |
0890540e LL |
453 | SKL_GT3_PLUS_PLATFORM, |
454 | .gt = 3, | |
455 | }; | |
456 | ||
5b54eddd | 457 | static const struct intel_device_info intel_skylake_gt4_info __initconst = { |
0890540e LL |
458 | SKL_GT3_PLUS_PLATFORM, |
459 | .gt = 4, | |
42f5551d CW |
460 | }; |
461 | ||
80fa66b6 RV |
462 | #define GEN9_LP_FEATURES \ |
463 | .gen = 9, \ | |
3e4274f8 | 464 | .is_lp = 1, \ |
80fa66b6 RV |
465 | .has_hotplug = 1, \ |
466 | .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, \ | |
467 | .num_pipes = 3, \ | |
468 | .has_64bit_reloc = 1, \ | |
469 | .has_ddi = 1, \ | |
470 | .has_fpga_dbg = 1, \ | |
471 | .has_fbc = 1, \ | |
495001c6 | 472 | .has_psr = 1, \ |
80fa66b6 RV |
473 | .has_runtime_pm = 1, \ |
474 | .has_pooled_eu = 0, \ | |
475 | .has_csr = 1, \ | |
476 | .has_resource_streamer = 1, \ | |
477 | .has_rc6 = 1, \ | |
478 | .has_dp_mst = 1, \ | |
80fa66b6 RV |
479 | .has_logical_ring_contexts = 1, \ |
480 | .has_guc = 1, \ | |
9e1d0e60 MT |
481 | .has_aliasing_ppgtt = 1, \ |
482 | .has_full_ppgtt = 1, \ | |
483 | .has_full_48bit_ppgtt = 1, \ | |
142bc7d9 | 484 | .has_reset_engine = 1, \ |
5d95c248 | 485 | .has_snoop = true, \ |
e57f1c02 | 486 | .has_ipc = 1, \ |
80fa66b6 RV |
487 | GEN_DEFAULT_PIPEOFFSETS, \ |
488 | IVB_CURSOR_OFFSETS, \ | |
489 | BDW_COLORS | |
490 | ||
5b54eddd | 491 | static const struct intel_device_info intel_broxton_info __initconst = { |
80fa66b6 | 492 | GEN9_LP_FEATURES, |
2e0d26f8 | 493 | .platform = INTEL_BROXTON, |
6f3fff60 | 494 | .ddb_size = 512, |
42f5551d CW |
495 | }; |
496 | ||
5b54eddd | 497 | static const struct intel_device_info intel_geminilake_info __initconst = { |
c22097fa | 498 | GEN9_LP_FEATURES, |
2e0d26f8 | 499 | .platform = INTEL_GEMINILAKE, |
c22097fa | 500 | .ddb_size = 1024, |
4672770d | 501 | GLK_COLORS, |
c22097fa ACO |
502 | }; |
503 | ||
94829de4 | 504 | #define KBL_PLATFORM \ |
42a3ae88 | 505 | GEN9_FEATURES, \ |
94829de4 | 506 | .gen = 9, \ |
42a3ae88 | 507 | .platform = INTEL_KABYLAKE |
94829de4 | 508 | |
5b54eddd | 509 | static const struct intel_device_info intel_kabylake_gt1_info __initconst = { |
94829de4 | 510 | KBL_PLATFORM, |
0890540e LL |
511 | .gt = 1, |
512 | }; | |
513 | ||
5b54eddd | 514 | static const struct intel_device_info intel_kabylake_gt2_info __initconst = { |
0890540e LL |
515 | KBL_PLATFORM, |
516 | .gt = 2, | |
42f5551d CW |
517 | }; |
518 | ||
5b54eddd | 519 | static const struct intel_device_info intel_kabylake_gt3_info __initconst = { |
94829de4 | 520 | KBL_PLATFORM, |
0890540e | 521 | .gt = 3, |
42f5551d CW |
522 | .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING, |
523 | }; | |
524 | ||
71851fa8 | 525 | #define CFL_PLATFORM \ |
42a3ae88 | 526 | GEN9_FEATURES, \ |
71851fa8 | 527 | .gen = 9, \ |
42a3ae88 | 528 | .platform = INTEL_COFFEELAKE |
71851fa8 | 529 | |
5b54eddd | 530 | static const struct intel_device_info intel_coffeelake_gt1_info __initconst = { |
0890540e LL |
531 | CFL_PLATFORM, |
532 | .gt = 1, | |
533 | }; | |
534 | ||
5b54eddd | 535 | static const struct intel_device_info intel_coffeelake_gt2_info __initconst = { |
71851fa8 | 536 | CFL_PLATFORM, |
0890540e | 537 | .gt = 2, |
71851fa8 RV |
538 | }; |
539 | ||
5b54eddd | 540 | static const struct intel_device_info intel_coffeelake_gt3_info __initconst = { |
71851fa8 | 541 | CFL_PLATFORM, |
0890540e | 542 | .gt = 3, |
71851fa8 RV |
543 | .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING, |
544 | }; | |
545 | ||
42a3ae88 RV |
546 | #define GEN10_FEATURES \ |
547 | GEN9_FEATURES, \ | |
548 | .ddb_size = 1024, \ | |
4672770d | 549 | GLK_COLORS |
42a3ae88 | 550 | |
5b54eddd | 551 | static const struct intel_device_info intel_cannonlake_gt2_info __initconst = { |
42a3ae88 | 552 | GEN10_FEATURES, |
413f3c19 RV |
553 | .is_alpha_support = 1, |
554 | .platform = INTEL_CANNONLAKE, | |
555 | .gen = 10, | |
0890540e | 556 | .gt = 2, |
413f3c19 RV |
557 | }; |
558 | ||
42f5551d CW |
559 | /* |
560 | * Make sure any device matches here are from most specific to most | |
561 | * general. For example, since the Quanta match is based on the subsystem | |
562 | * and subvendor IDs, we need it to come before the more general IVB | |
563 | * PCI ID matches, otherwise we'll use the wrong info struct above. | |
564 | */ | |
565 | static const struct pci_device_id pciidlist[] = { | |
566 | INTEL_I830_IDS(&intel_i830_info), | |
2a307c2e | 567 | INTEL_I845G_IDS(&intel_i845g_info), |
42f5551d CW |
568 | INTEL_I85X_IDS(&intel_i85x_info), |
569 | INTEL_I865G_IDS(&intel_i865g_info), | |
570 | INTEL_I915G_IDS(&intel_i915g_info), | |
571 | INTEL_I915GM_IDS(&intel_i915gm_info), | |
572 | INTEL_I945G_IDS(&intel_i945g_info), | |
573 | INTEL_I945GM_IDS(&intel_i945gm_info), | |
574 | INTEL_I965G_IDS(&intel_i965g_info), | |
575 | INTEL_G33_IDS(&intel_g33_info), | |
576 | INTEL_I965GM_IDS(&intel_i965gm_info), | |
577 | INTEL_GM45_IDS(&intel_gm45_info), | |
578 | INTEL_G45_IDS(&intel_g45_info), | |
579 | INTEL_PINEVIEW_IDS(&intel_pineview_info), | |
580 | INTEL_IRONLAKE_D_IDS(&intel_ironlake_d_info), | |
581 | INTEL_IRONLAKE_M_IDS(&intel_ironlake_m_info), | |
0890540e LL |
582 | INTEL_SNB_D_GT1_IDS(&intel_sandybridge_d_gt1_info), |
583 | INTEL_SNB_D_GT2_IDS(&intel_sandybridge_d_gt2_info), | |
584 | INTEL_SNB_M_GT1_IDS(&intel_sandybridge_m_gt1_info), | |
585 | INTEL_SNB_M_GT2_IDS(&intel_sandybridge_m_gt2_info), | |
42f5551d | 586 | INTEL_IVB_Q_IDS(&intel_ivybridge_q_info), /* must be first IVB */ |
0890540e LL |
587 | INTEL_IVB_M_GT1_IDS(&intel_ivybridge_m_gt1_info), |
588 | INTEL_IVB_M_GT2_IDS(&intel_ivybridge_m_gt2_info), | |
589 | INTEL_IVB_D_GT1_IDS(&intel_ivybridge_d_gt1_info), | |
590 | INTEL_IVB_D_GT2_IDS(&intel_ivybridge_d_gt2_info), | |
591 | INTEL_HSW_GT1_IDS(&intel_haswell_gt1_info), | |
592 | INTEL_HSW_GT2_IDS(&intel_haswell_gt2_info), | |
593 | INTEL_HSW_GT3_IDS(&intel_haswell_gt3_info), | |
8d9c20e1 | 594 | INTEL_VLV_IDS(&intel_valleyview_info), |
0890540e LL |
595 | INTEL_BDW_GT1_IDS(&intel_broadwell_gt1_info), |
596 | INTEL_BDW_GT2_IDS(&intel_broadwell_gt2_info), | |
8d9c20e1 | 597 | INTEL_BDW_GT3_IDS(&intel_broadwell_gt3_info), |
0890540e | 598 | INTEL_BDW_RSVD_IDS(&intel_broadwell_rsvd_info), |
42f5551d | 599 | INTEL_CHV_IDS(&intel_cherryview_info), |
0890540e LL |
600 | INTEL_SKL_GT1_IDS(&intel_skylake_gt1_info), |
601 | INTEL_SKL_GT2_IDS(&intel_skylake_gt2_info), | |
42f5551d | 602 | INTEL_SKL_GT3_IDS(&intel_skylake_gt3_info), |
0890540e | 603 | INTEL_SKL_GT4_IDS(&intel_skylake_gt4_info), |
42f5551d | 604 | INTEL_BXT_IDS(&intel_broxton_info), |
8363e3c3 | 605 | INTEL_GLK_IDS(&intel_geminilake_info), |
0890540e LL |
606 | INTEL_KBL_GT1_IDS(&intel_kabylake_gt1_info), |
607 | INTEL_KBL_GT2_IDS(&intel_kabylake_gt2_info), | |
42f5551d CW |
608 | INTEL_KBL_GT3_IDS(&intel_kabylake_gt3_info), |
609 | INTEL_KBL_GT4_IDS(&intel_kabylake_gt3_info), | |
0890540e LL |
610 | INTEL_CFL_S_GT1_IDS(&intel_coffeelake_gt1_info), |
611 | INTEL_CFL_S_GT2_IDS(&intel_coffeelake_gt2_info), | |
612 | INTEL_CFL_H_GT2_IDS(&intel_coffeelake_gt2_info), | |
613 | INTEL_CFL_U_GT3_IDS(&intel_coffeelake_gt3_info), | |
614 | INTEL_CNL_U_GT2_IDS(&intel_cannonlake_gt2_info), | |
615 | INTEL_CNL_Y_GT2_IDS(&intel_cannonlake_gt2_info), | |
42f5551d CW |
616 | {0, 0, 0} |
617 | }; | |
618 | MODULE_DEVICE_TABLE(pci, pciidlist); | |
619 | ||
953c7f82 CW |
620 | static void i915_pci_remove(struct pci_dev *pdev) |
621 | { | |
622 | struct drm_device *dev = pci_get_drvdata(pdev); | |
623 | ||
624 | i915_driver_unload(dev); | |
625 | drm_dev_unref(dev); | |
626 | } | |
627 | ||
42f5551d CW |
628 | static int i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent) |
629 | { | |
630 | struct intel_device_info *intel_info = | |
631 | (struct intel_device_info *) ent->driver_data; | |
953c7f82 | 632 | int err; |
42f5551d | 633 | |
4f044a88 | 634 | if (IS_ALPHA_SUPPORT(intel_info) && !i915_modparams.alpha_support) { |
c007fb4a JN |
635 | DRM_INFO("The driver support for your hardware in this kernel version is alpha quality\n" |
636 | "See CONFIG_DRM_I915_ALPHA_SUPPORT or i915.alpha_support module parameter\n" | |
637 | "to enable support in this kernel version, or check for kernel updates.\n"); | |
42f5551d CW |
638 | return -ENODEV; |
639 | } | |
640 | ||
641 | /* Only bind to function 0 of the device. Early generations | |
642 | * used function 1 as a placeholder for multi-head. This causes | |
643 | * us confusion instead, especially on the systems where both | |
644 | * functions have the same PCI-ID! | |
645 | */ | |
646 | if (PCI_FUNC(pdev->devfn)) | |
647 | return -ENODEV; | |
648 | ||
649 | /* | |
650 | * apple-gmux is needed on dual GPU MacBook Pro | |
651 | * to probe the panel if we're the inactive GPU. | |
652 | */ | |
653 | if (vga_switcheroo_client_probe_defer(pdev)) | |
654 | return -EPROBE_DEFER; | |
655 | ||
953c7f82 CW |
656 | err = i915_driver_load(pdev, ent); |
657 | if (err) | |
658 | return err; | |
42f5551d | 659 | |
953c7f82 CW |
660 | err = i915_live_selftests(pdev); |
661 | if (err) { | |
662 | i915_pci_remove(pdev); | |
663 | return err > 0 ? -ENOTTY : err; | |
664 | } | |
42f5551d | 665 | |
953c7f82 | 666 | return 0; |
42f5551d CW |
667 | } |
668 | ||
a09d0ba1 | 669 | static struct pci_driver i915_pci_driver = { |
42f5551d CW |
670 | .name = DRIVER_NAME, |
671 | .id_table = pciidlist, | |
672 | .probe = i915_pci_probe, | |
673 | .remove = i915_pci_remove, | |
674 | .driver.pm = &i915_pm_ops, | |
675 | }; | |
a09d0ba1 CW |
676 | |
677 | static int __init i915_init(void) | |
678 | { | |
679 | bool use_kms = true; | |
953c7f82 CW |
680 | int err; |
681 | ||
682 | err = i915_mock_selftests(); | |
683 | if (err) | |
684 | return err > 0 ? 0 : err; | |
a09d0ba1 CW |
685 | |
686 | /* | |
687 | * Enable KMS by default, unless explicitly overriden by | |
688 | * either the i915.modeset prarameter or by the | |
689 | * vga_text_mode_force boot option. | |
690 | */ | |
691 | ||
4f044a88 | 692 | if (i915_modparams.modeset == 0) |
a09d0ba1 CW |
693 | use_kms = false; |
694 | ||
4f044a88 | 695 | if (vgacon_text_force() && i915_modparams.modeset == -1) |
a09d0ba1 CW |
696 | use_kms = false; |
697 | ||
698 | if (!use_kms) { | |
699 | /* Silently fail loading to not upset userspace. */ | |
700 | DRM_DEBUG_DRIVER("KMS disabled.\n"); | |
701 | return 0; | |
702 | } | |
703 | ||
704 | return pci_register_driver(&i915_pci_driver); | |
705 | } | |
706 | ||
707 | static void __exit i915_exit(void) | |
708 | { | |
709 | if (!i915_pci_driver.driver.owner) | |
710 | return; | |
711 | ||
712 | pci_unregister_driver(&i915_pci_driver); | |
713 | } | |
714 | ||
715 | module_init(i915_init); | |
716 | module_exit(i915_exit); | |
717 | ||
718 | MODULE_AUTHOR("Tungsten Graphics, Inc."); | |
719 | MODULE_AUTHOR("Intel Corporation"); | |
720 | ||
721 | MODULE_DESCRIPTION(DRIVER_DESC); | |
722 | MODULE_LICENSE("GPL and additional rights"); |