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42f5551d CW |
1 | /* |
2 | * Copyright © 2016 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | */ | |
24 | ||
a09d0ba1 | 25 | #include <linux/console.h> |
42f5551d CW |
26 | #include <linux/vgaarb.h> |
27 | #include <linux/vga_switcheroo.h> | |
28 | ||
29 | #include "i915_drv.h" | |
953c7f82 | 30 | #include "i915_selftest.h" |
42f5551d CW |
31 | |
32 | #define GEN_DEFAULT_PIPEOFFSETS \ | |
33 | .pipe_offsets = { PIPE_A_OFFSET, PIPE_B_OFFSET, \ | |
34 | PIPE_C_OFFSET, PIPE_EDP_OFFSET }, \ | |
35 | .trans_offsets = { TRANSCODER_A_OFFSET, TRANSCODER_B_OFFSET, \ | |
36 | TRANSCODER_C_OFFSET, TRANSCODER_EDP_OFFSET }, \ | |
37 | .palette_offsets = { PALETTE_A_OFFSET, PALETTE_B_OFFSET } | |
38 | ||
39 | #define GEN_CHV_PIPEOFFSETS \ | |
40 | .pipe_offsets = { PIPE_A_OFFSET, PIPE_B_OFFSET, \ | |
41 | CHV_PIPE_C_OFFSET }, \ | |
42 | .trans_offsets = { TRANSCODER_A_OFFSET, TRANSCODER_B_OFFSET, \ | |
43 | CHV_TRANSCODER_C_OFFSET, }, \ | |
44 | .palette_offsets = { PALETTE_A_OFFSET, PALETTE_B_OFFSET, \ | |
45 | CHV_PALETTE_C_OFFSET } | |
46 | ||
47 | #define CURSOR_OFFSETS \ | |
48 | .cursor_offsets = { CURSOR_A_OFFSET, CURSOR_B_OFFSET, CHV_CURSOR_C_OFFSET } | |
49 | ||
50 | #define IVB_CURSOR_OFFSETS \ | |
51 | .cursor_offsets = { CURSOR_A_OFFSET, IVB_CURSOR_B_OFFSET, IVB_CURSOR_C_OFFSET } | |
52 | ||
53 | #define BDW_COLORS \ | |
54 | .color = { .degamma_lut_size = 512, .gamma_lut_size = 512 } | |
55 | #define CHV_COLORS \ | |
56 | .color = { .degamma_lut_size = 65, .gamma_lut_size = 257 } | |
4672770d RV |
57 | #define GLK_COLORS \ |
58 | .color = { .degamma_lut_size = 0, .gamma_lut_size = 1024 } | |
42f5551d | 59 | |
a5ce929b | 60 | /* Keep in gen based order, and chronological order within a gen */ |
2a9654b2 MA |
61 | |
62 | #define GEN_DEFAULT_PAGE_SIZES \ | |
63 | .page_sizes = I915_GTT_PAGE_SIZE_4K | |
64 | ||
0eec8dc7 CS |
65 | #define GEN2_FEATURES \ |
66 | .gen = 2, .num_pipes = 1, \ | |
67 | .has_overlay = 1, .overlay_needs_physical = 1, \ | |
804b8712 | 68 | .has_gmch_display = 1, \ |
3177659a | 69 | .hws_needs_physical = 1, \ |
f4ce766f | 70 | .unfenced_needs_alignment = 1, \ |
0eec8dc7 | 71 | .ring_mask = RENDER_RING, \ |
5d95c248 | 72 | .has_snoop = true, \ |
0eec8dc7 | 73 | GEN_DEFAULT_PIPEOFFSETS, \ |
2a9654b2 | 74 | GEN_DEFAULT_PAGE_SIZES, \ |
0eec8dc7 CS |
75 | CURSOR_OFFSETS |
76 | ||
5b54eddd | 77 | static const struct intel_device_info intel_i830_info __initconst = { |
0eec8dc7 | 78 | GEN2_FEATURES, |
2e0d26f8 | 79 | .platform = INTEL_I830, |
0eec8dc7 CS |
80 | .is_mobile = 1, .cursor_needs_physical = 1, |
81 | .num_pipes = 2, /* legal, last one wins */ | |
42f5551d CW |
82 | }; |
83 | ||
5b54eddd | 84 | static const struct intel_device_info intel_i845g_info __initconst = { |
0eec8dc7 | 85 | GEN2_FEATURES, |
2e0d26f8 | 86 | .platform = INTEL_I845G, |
42f5551d CW |
87 | }; |
88 | ||
5b54eddd | 89 | static const struct intel_device_info intel_i85x_info __initconst = { |
0eec8dc7 | 90 | GEN2_FEATURES, |
2e0d26f8 | 91 | .platform = INTEL_I85X, .is_mobile = 1, |
0eec8dc7 | 92 | .num_pipes = 2, /* legal, last one wins */ |
42f5551d | 93 | .cursor_needs_physical = 1, |
42f5551d | 94 | .has_fbc = 1, |
42f5551d CW |
95 | }; |
96 | ||
5b54eddd | 97 | static const struct intel_device_info intel_i865g_info __initconst = { |
0eec8dc7 | 98 | GEN2_FEATURES, |
2e0d26f8 | 99 | .platform = INTEL_I865G, |
42f5551d CW |
100 | }; |
101 | ||
54d2a6a1 CS |
102 | #define GEN3_FEATURES \ |
103 | .gen = 3, .num_pipes = 2, \ | |
804b8712 | 104 | .has_gmch_display = 1, \ |
54d2a6a1 | 105 | .ring_mask = RENDER_RING, \ |
5d95c248 | 106 | .has_snoop = true, \ |
54d2a6a1 | 107 | GEN_DEFAULT_PIPEOFFSETS, \ |
2a9654b2 | 108 | GEN_DEFAULT_PAGE_SIZES, \ |
54d2a6a1 CS |
109 | CURSOR_OFFSETS |
110 | ||
5b54eddd | 111 | static const struct intel_device_info intel_i915g_info __initconst = { |
54d2a6a1 | 112 | GEN3_FEATURES, |
2e0d26f8 | 113 | .platform = INTEL_I915G, .cursor_needs_physical = 1, |
42f5551d | 114 | .has_overlay = 1, .overlay_needs_physical = 1, |
3177659a | 115 | .hws_needs_physical = 1, |
f4ce766f | 116 | .unfenced_needs_alignment = 1, |
42f5551d | 117 | }; |
a5ce929b | 118 | |
5b54eddd | 119 | static const struct intel_device_info intel_i915gm_info __initconst = { |
54d2a6a1 | 120 | GEN3_FEATURES, |
2e0d26f8 | 121 | .platform = INTEL_I915GM, |
54d2a6a1 | 122 | .is_mobile = 1, |
42f5551d CW |
123 | .cursor_needs_physical = 1, |
124 | .has_overlay = 1, .overlay_needs_physical = 1, | |
125 | .supports_tv = 1, | |
126 | .has_fbc = 1, | |
3177659a | 127 | .hws_needs_physical = 1, |
f4ce766f | 128 | .unfenced_needs_alignment = 1, |
42f5551d | 129 | }; |
a5ce929b | 130 | |
5b54eddd | 131 | static const struct intel_device_info intel_i945g_info __initconst = { |
54d2a6a1 | 132 | GEN3_FEATURES, |
2e0d26f8 | 133 | .platform = INTEL_I945G, |
54d2a6a1 | 134 | .has_hotplug = 1, .cursor_needs_physical = 1, |
42f5551d | 135 | .has_overlay = 1, .overlay_needs_physical = 1, |
3177659a | 136 | .hws_needs_physical = 1, |
f4ce766f | 137 | .unfenced_needs_alignment = 1, |
42f5551d | 138 | }; |
a5ce929b | 139 | |
5b54eddd | 140 | static const struct intel_device_info intel_i945gm_info __initconst = { |
54d2a6a1 | 141 | GEN3_FEATURES, |
2e0d26f8 | 142 | .platform = INTEL_I945GM, .is_mobile = 1, |
42f5551d CW |
143 | .has_hotplug = 1, .cursor_needs_physical = 1, |
144 | .has_overlay = 1, .overlay_needs_physical = 1, | |
145 | .supports_tv = 1, | |
146 | .has_fbc = 1, | |
3177659a | 147 | .hws_needs_physical = 1, |
f4ce766f | 148 | .unfenced_needs_alignment = 1, |
42f5551d CW |
149 | }; |
150 | ||
5b54eddd | 151 | static const struct intel_device_info intel_g33_info __initconst = { |
a5ce929b JN |
152 | GEN3_FEATURES, |
153 | .platform = INTEL_G33, | |
154 | .has_hotplug = 1, | |
155 | .has_overlay = 1, | |
156 | }; | |
157 | ||
5b54eddd | 158 | static const struct intel_device_info intel_pineview_info __initconst = { |
a5ce929b | 159 | GEN3_FEATURES, |
73f67aa8 | 160 | .platform = INTEL_PINEVIEW, .is_mobile = 1, |
a5ce929b JN |
161 | .has_hotplug = 1, |
162 | .has_overlay = 1, | |
163 | }; | |
164 | ||
4d495bea CS |
165 | #define GEN4_FEATURES \ |
166 | .gen = 4, .num_pipes = 2, \ | |
167 | .has_hotplug = 1, \ | |
804b8712 | 168 | .has_gmch_display = 1, \ |
4d495bea | 169 | .ring_mask = RENDER_RING, \ |
5d95c248 | 170 | .has_snoop = true, \ |
4d495bea | 171 | GEN_DEFAULT_PIPEOFFSETS, \ |
2a9654b2 | 172 | GEN_DEFAULT_PAGE_SIZES, \ |
4d495bea CS |
173 | CURSOR_OFFSETS |
174 | ||
5b54eddd | 175 | static const struct intel_device_info intel_i965g_info __initconst = { |
4d495bea | 176 | GEN4_FEATURES, |
c0f86832 | 177 | .platform = INTEL_I965G, |
42f5551d | 178 | .has_overlay = 1, |
3177659a | 179 | .hws_needs_physical = 1, |
df0700e5 | 180 | .has_snoop = false, |
42f5551d CW |
181 | }; |
182 | ||
5b54eddd | 183 | static const struct intel_device_info intel_i965gm_info __initconst = { |
4d495bea | 184 | GEN4_FEATURES, |
c0f86832 | 185 | .platform = INTEL_I965GM, |
4d495bea | 186 | .is_mobile = 1, .has_fbc = 1, |
42f5551d CW |
187 | .has_overlay = 1, |
188 | .supports_tv = 1, | |
3177659a | 189 | .hws_needs_physical = 1, |
df0700e5 | 190 | .has_snoop = false, |
42f5551d CW |
191 | }; |
192 | ||
5b54eddd | 193 | static const struct intel_device_info intel_g45_info __initconst = { |
4d495bea | 194 | GEN4_FEATURES, |
f69c11ae | 195 | .platform = INTEL_G45, |
4d495bea | 196 | .has_pipe_cxsr = 1, |
42f5551d | 197 | .ring_mask = RENDER_RING | BSD_RING, |
42f5551d CW |
198 | }; |
199 | ||
5b54eddd | 200 | static const struct intel_device_info intel_gm45_info __initconst = { |
4d495bea | 201 | GEN4_FEATURES, |
f69c11ae | 202 | .platform = INTEL_GM45, |
3177659a | 203 | .is_mobile = 1, .has_fbc = 1, |
4d495bea | 204 | .has_pipe_cxsr = 1, |
42f5551d CW |
205 | .supports_tv = 1, |
206 | .ring_mask = RENDER_RING | BSD_RING, | |
42f5551d CW |
207 | }; |
208 | ||
a1323380 CS |
209 | #define GEN5_FEATURES \ |
210 | .gen = 5, .num_pipes = 2, \ | |
3177659a | 211 | .has_hotplug = 1, \ |
a1323380 | 212 | .ring_mask = RENDER_RING | BSD_RING, \ |
5d95c248 | 213 | .has_snoop = true, \ |
a1323380 | 214 | GEN_DEFAULT_PIPEOFFSETS, \ |
2a9654b2 | 215 | GEN_DEFAULT_PAGE_SIZES, \ |
a1323380 CS |
216 | CURSOR_OFFSETS |
217 | ||
5b54eddd | 218 | static const struct intel_device_info intel_ironlake_d_info __initconst = { |
a1323380 | 219 | GEN5_FEATURES, |
2e0d26f8 | 220 | .platform = INTEL_IRONLAKE, |
42f5551d CW |
221 | }; |
222 | ||
5b54eddd | 223 | static const struct intel_device_info intel_ironlake_m_info __initconst = { |
a1323380 | 224 | GEN5_FEATURES, |
2e0d26f8 | 225 | .platform = INTEL_IRONLAKE, |
c2d1a0ce | 226 | .is_mobile = 1, .has_fbc = 1, |
42f5551d CW |
227 | }; |
228 | ||
07db6be7 CS |
229 | #define GEN6_FEATURES \ |
230 | .gen = 6, .num_pipes = 2, \ | |
3177659a | 231 | .has_hotplug = 1, \ |
07db6be7 CS |
232 | .has_fbc = 1, \ |
233 | .ring_mask = RENDER_RING | BSD_RING | BLT_RING, \ | |
234 | .has_llc = 1, \ | |
86f3624b | 235 | .has_rc6 = 1, \ |
33b5bf82 | 236 | .has_rc6p = 1, \ |
9e1d0e60 | 237 | .has_aliasing_ppgtt = 1, \ |
07db6be7 | 238 | GEN_DEFAULT_PIPEOFFSETS, \ |
2a9654b2 | 239 | GEN_DEFAULT_PAGE_SIZES, \ |
07db6be7 CS |
240 | CURSOR_OFFSETS |
241 | ||
0890540e LL |
242 | #define SNB_D_PLATFORM \ |
243 | GEN6_FEATURES, \ | |
244 | .platform = INTEL_SANDYBRIDGE | |
245 | ||
5b54eddd | 246 | static const struct intel_device_info intel_sandybridge_d_gt1_info __initconst = { |
0890540e LL |
247 | SNB_D_PLATFORM, |
248 | .gt = 1, | |
42f5551d CW |
249 | }; |
250 | ||
5b54eddd | 251 | static const struct intel_device_info intel_sandybridge_d_gt2_info __initconst = { |
0890540e LL |
252 | SNB_D_PLATFORM, |
253 | .gt = 2, | |
254 | }; | |
255 | ||
256 | #define SNB_M_PLATFORM \ | |
257 | GEN6_FEATURES, \ | |
258 | .platform = INTEL_SANDYBRIDGE, \ | |
259 | .is_mobile = 1 | |
260 | ||
261 | ||
5b54eddd | 262 | static const struct intel_device_info intel_sandybridge_m_gt1_info __initconst = { |
0890540e LL |
263 | SNB_M_PLATFORM, |
264 | .gt = 1, | |
265 | }; | |
266 | ||
5b54eddd | 267 | static const struct intel_device_info intel_sandybridge_m_gt2_info __initconst = { |
0890540e LL |
268 | SNB_M_PLATFORM, |
269 | .gt = 2, | |
42f5551d CW |
270 | }; |
271 | ||
272 | #define GEN7_FEATURES \ | |
273 | .gen = 7, .num_pipes = 3, \ | |
3177659a | 274 | .has_hotplug = 1, \ |
42f5551d CW |
275 | .has_fbc = 1, \ |
276 | .ring_mask = RENDER_RING | BSD_RING | BLT_RING, \ | |
277 | .has_llc = 1, \ | |
86f3624b | 278 | .has_rc6 = 1, \ |
33b5bf82 | 279 | .has_rc6p = 1, \ |
9e1d0e60 MT |
280 | .has_aliasing_ppgtt = 1, \ |
281 | .has_full_ppgtt = 1, \ | |
42f5551d | 282 | GEN_DEFAULT_PIPEOFFSETS, \ |
2a9654b2 | 283 | GEN_DEFAULT_PAGE_SIZES, \ |
42f5551d CW |
284 | IVB_CURSOR_OFFSETS |
285 | ||
0890540e LL |
286 | #define IVB_D_PLATFORM \ |
287 | GEN7_FEATURES, \ | |
288 | .platform = INTEL_IVYBRIDGE, \ | |
289 | .has_l3_dpf = 1 | |
290 | ||
5b54eddd | 291 | static const struct intel_device_info intel_ivybridge_d_gt1_info __initconst = { |
0890540e LL |
292 | IVB_D_PLATFORM, |
293 | .gt = 1, | |
42f5551d CW |
294 | }; |
295 | ||
5b54eddd | 296 | static const struct intel_device_info intel_ivybridge_d_gt2_info __initconst = { |
0890540e LL |
297 | IVB_D_PLATFORM, |
298 | .gt = 2, | |
299 | }; | |
300 | ||
301 | #define IVB_M_PLATFORM \ | |
302 | GEN7_FEATURES, \ | |
303 | .platform = INTEL_IVYBRIDGE, \ | |
304 | .is_mobile = 1, \ | |
305 | .has_l3_dpf = 1 | |
306 | ||
5b54eddd | 307 | static const struct intel_device_info intel_ivybridge_m_gt1_info __initconst = { |
0890540e LL |
308 | IVB_M_PLATFORM, |
309 | .gt = 1, | |
310 | }; | |
311 | ||
5b54eddd | 312 | static const struct intel_device_info intel_ivybridge_m_gt2_info __initconst = { |
0890540e LL |
313 | IVB_M_PLATFORM, |
314 | .gt = 2, | |
42f5551d CW |
315 | }; |
316 | ||
5b54eddd | 317 | static const struct intel_device_info intel_ivybridge_q_info __initconst = { |
42f5551d | 318 | GEN7_FEATURES, |
2e0d26f8 | 319 | .platform = INTEL_IVYBRIDGE, |
0890540e | 320 | .gt = 2, |
42f5551d | 321 | .num_pipes = 0, /* legal, last one wins */ |
ca9c4523 | 322 | .has_l3_dpf = 1, |
42f5551d CW |
323 | }; |
324 | ||
5b54eddd | 325 | static const struct intel_device_info intel_valleyview_info __initconst = { |
2e0d26f8 | 326 | .platform = INTEL_VALLEYVIEW, |
eb6f771b RV |
327 | .gen = 7, |
328 | .is_lp = 1, | |
329 | .num_pipes = 2, | |
330 | .has_psr = 1, | |
331 | .has_runtime_pm = 1, | |
332 | .has_rc6 = 1, | |
eb6f771b RV |
333 | .has_gmch_display = 1, |
334 | .has_hotplug = 1, | |
335 | .has_aliasing_ppgtt = 1, | |
336 | .has_full_ppgtt = 1, | |
5d95c248 | 337 | .has_snoop = true, |
eb6f771b RV |
338 | .ring_mask = RENDER_RING | BSD_RING | BLT_RING, |
339 | .display_mmio_offset = VLV_DISPLAY_BASE, | |
2a9654b2 | 340 | GEN_DEFAULT_PAGE_SIZES, |
eb6f771b RV |
341 | GEN_DEFAULT_PIPEOFFSETS, |
342 | CURSOR_OFFSETS | |
42f5551d CW |
343 | }; |
344 | ||
42a3ae88 | 345 | #define G75_FEATURES \ |
42f5551d CW |
346 | GEN7_FEATURES, \ |
347 | .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, \ | |
348 | .has_ddi = 1, \ | |
6e3b84d8 | 349 | .has_fpga_dbg = 1, \ |
4aa4c23f | 350 | .has_psr = 1, \ |
53233f08 | 351 | .has_resource_streamer = 1, \ |
1d3fe53b | 352 | .has_dp_mst = 1, \ |
33b5bf82 | 353 | .has_rc6p = 0 /* RC6p removed-by HSW */, \ |
4aa4c23f | 354 | .has_runtime_pm = 1 |
42f5551d | 355 | |
0890540e | 356 | #define HSW_PLATFORM \ |
42a3ae88 | 357 | G75_FEATURES, \ |
0890540e LL |
358 | .platform = INTEL_HASWELL, \ |
359 | .has_l3_dpf = 1 | |
360 | ||
5b54eddd | 361 | static const struct intel_device_info intel_haswell_gt1_info __initconst = { |
0890540e LL |
362 | HSW_PLATFORM, |
363 | .gt = 1, | |
364 | }; | |
365 | ||
5b54eddd | 366 | static const struct intel_device_info intel_haswell_gt2_info __initconst = { |
0890540e LL |
367 | HSW_PLATFORM, |
368 | .gt = 2, | |
369 | }; | |
370 | ||
5b54eddd | 371 | static const struct intel_device_info intel_haswell_gt3_info __initconst = { |
0890540e LL |
372 | HSW_PLATFORM, |
373 | .gt = 3, | |
42f5551d CW |
374 | }; |
375 | ||
42a3ae88 RV |
376 | #define GEN8_FEATURES \ |
377 | G75_FEATURES, \ | |
4586f1d0 | 378 | BDW_COLORS, \ |
a883241c MA |
379 | .page_sizes = I915_GTT_PAGE_SIZE_4K | \ |
380 | I915_GTT_PAGE_SIZE_2M, \ | |
dfc5148f | 381 | .has_logical_ring_contexts = 1, \ |
9e1d0e60 | 382 | .has_full_48bit_ppgtt = 1, \ |
142bc7d9 MT |
383 | .has_64bit_reloc = 1, \ |
384 | .has_reset_engine = 1 | |
42f5551d | 385 | |
94829de4 | 386 | #define BDW_PLATFORM \ |
42a3ae88 | 387 | GEN8_FEATURES, \ |
94829de4 RV |
388 | .gen = 8, \ |
389 | .platform = INTEL_BROADWELL | |
390 | ||
5b54eddd | 391 | static const struct intel_device_info intel_broadwell_gt1_info __initconst = { |
0890540e LL |
392 | BDW_PLATFORM, |
393 | .gt = 1, | |
394 | }; | |
395 | ||
5b54eddd | 396 | static const struct intel_device_info intel_broadwell_gt2_info __initconst = { |
94829de4 | 397 | BDW_PLATFORM, |
0890540e LL |
398 | .gt = 2, |
399 | }; | |
400 | ||
5b54eddd | 401 | static const struct intel_device_info intel_broadwell_rsvd_info __initconst = { |
0890540e LL |
402 | BDW_PLATFORM, |
403 | .gt = 3, | |
404 | /* According to the device ID those devices are GT3, they were | |
405 | * previously treated as not GT3, keep it like that. | |
406 | */ | |
42f5551d CW |
407 | }; |
408 | ||
5b54eddd | 409 | static const struct intel_device_info intel_broadwell_gt3_info __initconst = { |
94829de4 | 410 | BDW_PLATFORM, |
0890540e | 411 | .gt = 3, |
42f5551d CW |
412 | .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING, |
413 | }; | |
414 | ||
5b54eddd | 415 | static const struct intel_device_info intel_cherryview_info __initconst = { |
42f5551d | 416 | .gen = 8, .num_pipes = 3, |
3177659a | 417 | .has_hotplug = 1, |
8727dc09 | 418 | .is_lp = 1, |
42f5551d | 419 | .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, |
2e0d26f8 | 420 | .platform = INTEL_CHERRYVIEW, |
dfc5148f | 421 | .has_64bit_reloc = 1, |
6e3b84d8 | 422 | .has_psr = 1, |
4aa4c23f | 423 | .has_runtime_pm = 1, |
53233f08 | 424 | .has_resource_streamer = 1, |
86f3624b | 425 | .has_rc6 = 1, |
4586f1d0 | 426 | .has_logical_ring_contexts = 1, |
804b8712 | 427 | .has_gmch_display = 1, |
9e1d0e60 MT |
428 | .has_aliasing_ppgtt = 1, |
429 | .has_full_ppgtt = 1, | |
142bc7d9 | 430 | .has_reset_engine = 1, |
5d95c248 | 431 | .has_snoop = true, |
42f5551d | 432 | .display_mmio_offset = VLV_DISPLAY_BASE, |
2a9654b2 | 433 | GEN_DEFAULT_PAGE_SIZES, |
42f5551d CW |
434 | GEN_CHV_PIPEOFFSETS, |
435 | CURSOR_OFFSETS, | |
436 | CHV_COLORS, | |
437 | }; | |
438 | ||
2a9654b2 | 439 | #define GEN9_DEFAULT_PAGE_SIZES \ |
f1f3f982 | 440 | .page_sizes = I915_GTT_PAGE_SIZE_4K | \ |
a883241c MA |
441 | I915_GTT_PAGE_SIZE_64K | \ |
442 | I915_GTT_PAGE_SIZE_2M | |
2a9654b2 | 443 | |
42a3ae88 RV |
444 | #define GEN9_FEATURES \ |
445 | GEN8_FEATURES, \ | |
2a9654b2 | 446 | GEN9_DEFAULT_PAGE_SIZES, \ |
beecec90 | 447 | .has_logical_ring_preemption = 1, \ |
94829de4 RV |
448 | .has_csr = 1, \ |
449 | .has_guc = 1, \ | |
4d6ef0da | 450 | .has_ipc = 1, \ |
94829de4 RV |
451 | .ddb_size = 896 |
452 | ||
42a3ae88 RV |
453 | #define SKL_PLATFORM \ |
454 | GEN9_FEATURES, \ | |
455 | .gen = 9, \ | |
456 | .platform = INTEL_SKYLAKE | |
457 | ||
5b54eddd | 458 | static const struct intel_device_info intel_skylake_gt1_info __initconst = { |
94829de4 | 459 | SKL_PLATFORM, |
0890540e | 460 | .gt = 1, |
42f5551d CW |
461 | }; |
462 | ||
5b54eddd | 463 | static const struct intel_device_info intel_skylake_gt2_info __initconst = { |
94829de4 | 464 | SKL_PLATFORM, |
0890540e LL |
465 | .gt = 2, |
466 | }; | |
467 | ||
468 | #define SKL_GT3_PLUS_PLATFORM \ | |
469 | SKL_PLATFORM, \ | |
470 | .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING | |
471 | ||
472 | ||
5b54eddd | 473 | static const struct intel_device_info intel_skylake_gt3_info __initconst = { |
0890540e LL |
474 | SKL_GT3_PLUS_PLATFORM, |
475 | .gt = 3, | |
476 | }; | |
477 | ||
5b54eddd | 478 | static const struct intel_device_info intel_skylake_gt4_info __initconst = { |
0890540e LL |
479 | SKL_GT3_PLUS_PLATFORM, |
480 | .gt = 4, | |
42f5551d CW |
481 | }; |
482 | ||
80fa66b6 RV |
483 | #define GEN9_LP_FEATURES \ |
484 | .gen = 9, \ | |
3e4274f8 | 485 | .is_lp = 1, \ |
80fa66b6 RV |
486 | .has_hotplug = 1, \ |
487 | .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, \ | |
488 | .num_pipes = 3, \ | |
489 | .has_64bit_reloc = 1, \ | |
490 | .has_ddi = 1, \ | |
491 | .has_fpga_dbg = 1, \ | |
492 | .has_fbc = 1, \ | |
495001c6 | 493 | .has_psr = 1, \ |
80fa66b6 RV |
494 | .has_runtime_pm = 1, \ |
495 | .has_pooled_eu = 0, \ | |
496 | .has_csr = 1, \ | |
497 | .has_resource_streamer = 1, \ | |
498 | .has_rc6 = 1, \ | |
499 | .has_dp_mst = 1, \ | |
80fa66b6 | 500 | .has_logical_ring_contexts = 1, \ |
beecec90 | 501 | .has_logical_ring_preemption = 1, \ |
80fa66b6 | 502 | .has_guc = 1, \ |
9e1d0e60 MT |
503 | .has_aliasing_ppgtt = 1, \ |
504 | .has_full_ppgtt = 1, \ | |
505 | .has_full_48bit_ppgtt = 1, \ | |
142bc7d9 | 506 | .has_reset_engine = 1, \ |
5d95c248 | 507 | .has_snoop = true, \ |
e57f1c02 | 508 | .has_ipc = 1, \ |
2a9654b2 | 509 | GEN9_DEFAULT_PAGE_SIZES, \ |
80fa66b6 RV |
510 | GEN_DEFAULT_PIPEOFFSETS, \ |
511 | IVB_CURSOR_OFFSETS, \ | |
512 | BDW_COLORS | |
513 | ||
5b54eddd | 514 | static const struct intel_device_info intel_broxton_info __initconst = { |
80fa66b6 | 515 | GEN9_LP_FEATURES, |
2e0d26f8 | 516 | .platform = INTEL_BROXTON, |
6f3fff60 | 517 | .ddb_size = 512, |
42f5551d CW |
518 | }; |
519 | ||
5b54eddd | 520 | static const struct intel_device_info intel_geminilake_info __initconst = { |
c22097fa | 521 | GEN9_LP_FEATURES, |
2e0d26f8 | 522 | .platform = INTEL_GEMINILAKE, |
c22097fa | 523 | .ddb_size = 1024, |
4672770d | 524 | GLK_COLORS, |
c22097fa ACO |
525 | }; |
526 | ||
94829de4 | 527 | #define KBL_PLATFORM \ |
42a3ae88 | 528 | GEN9_FEATURES, \ |
94829de4 | 529 | .gen = 9, \ |
42a3ae88 | 530 | .platform = INTEL_KABYLAKE |
94829de4 | 531 | |
5b54eddd | 532 | static const struct intel_device_info intel_kabylake_gt1_info __initconst = { |
94829de4 | 533 | KBL_PLATFORM, |
0890540e LL |
534 | .gt = 1, |
535 | }; | |
536 | ||
5b54eddd | 537 | static const struct intel_device_info intel_kabylake_gt2_info __initconst = { |
0890540e LL |
538 | KBL_PLATFORM, |
539 | .gt = 2, | |
42f5551d CW |
540 | }; |
541 | ||
5b54eddd | 542 | static const struct intel_device_info intel_kabylake_gt3_info __initconst = { |
94829de4 | 543 | KBL_PLATFORM, |
0890540e | 544 | .gt = 3, |
42f5551d CW |
545 | .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING, |
546 | }; | |
547 | ||
71851fa8 | 548 | #define CFL_PLATFORM \ |
42a3ae88 | 549 | GEN9_FEATURES, \ |
71851fa8 | 550 | .gen = 9, \ |
42a3ae88 | 551 | .platform = INTEL_COFFEELAKE |
71851fa8 | 552 | |
5b54eddd | 553 | static const struct intel_device_info intel_coffeelake_gt1_info __initconst = { |
0890540e LL |
554 | CFL_PLATFORM, |
555 | .gt = 1, | |
556 | }; | |
557 | ||
5b54eddd | 558 | static const struct intel_device_info intel_coffeelake_gt2_info __initconst = { |
71851fa8 | 559 | CFL_PLATFORM, |
0890540e | 560 | .gt = 2, |
71851fa8 RV |
561 | }; |
562 | ||
5b54eddd | 563 | static const struct intel_device_info intel_coffeelake_gt3_info __initconst = { |
71851fa8 | 564 | CFL_PLATFORM, |
0890540e | 565 | .gt = 3, |
71851fa8 RV |
566 | .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING, |
567 | }; | |
568 | ||
42a3ae88 RV |
569 | #define GEN10_FEATURES \ |
570 | GEN9_FEATURES, \ | |
571 | .ddb_size = 1024, \ | |
4672770d | 572 | GLK_COLORS |
42a3ae88 | 573 | |
5b54eddd | 574 | static const struct intel_device_info intel_cannonlake_gt2_info __initconst = { |
42a3ae88 | 575 | GEN10_FEATURES, |
413f3c19 RV |
576 | .is_alpha_support = 1, |
577 | .platform = INTEL_CANNONLAKE, | |
578 | .gen = 10, | |
0890540e | 579 | .gt = 2, |
413f3c19 RV |
580 | }; |
581 | ||
42f5551d CW |
582 | /* |
583 | * Make sure any device matches here are from most specific to most | |
584 | * general. For example, since the Quanta match is based on the subsystem | |
585 | * and subvendor IDs, we need it to come before the more general IVB | |
586 | * PCI ID matches, otherwise we'll use the wrong info struct above. | |
587 | */ | |
588 | static const struct pci_device_id pciidlist[] = { | |
589 | INTEL_I830_IDS(&intel_i830_info), | |
2a307c2e | 590 | INTEL_I845G_IDS(&intel_i845g_info), |
42f5551d CW |
591 | INTEL_I85X_IDS(&intel_i85x_info), |
592 | INTEL_I865G_IDS(&intel_i865g_info), | |
593 | INTEL_I915G_IDS(&intel_i915g_info), | |
594 | INTEL_I915GM_IDS(&intel_i915gm_info), | |
595 | INTEL_I945G_IDS(&intel_i945g_info), | |
596 | INTEL_I945GM_IDS(&intel_i945gm_info), | |
597 | INTEL_I965G_IDS(&intel_i965g_info), | |
598 | INTEL_G33_IDS(&intel_g33_info), | |
599 | INTEL_I965GM_IDS(&intel_i965gm_info), | |
600 | INTEL_GM45_IDS(&intel_gm45_info), | |
601 | INTEL_G45_IDS(&intel_g45_info), | |
602 | INTEL_PINEVIEW_IDS(&intel_pineview_info), | |
603 | INTEL_IRONLAKE_D_IDS(&intel_ironlake_d_info), | |
604 | INTEL_IRONLAKE_M_IDS(&intel_ironlake_m_info), | |
0890540e LL |
605 | INTEL_SNB_D_GT1_IDS(&intel_sandybridge_d_gt1_info), |
606 | INTEL_SNB_D_GT2_IDS(&intel_sandybridge_d_gt2_info), | |
607 | INTEL_SNB_M_GT1_IDS(&intel_sandybridge_m_gt1_info), | |
608 | INTEL_SNB_M_GT2_IDS(&intel_sandybridge_m_gt2_info), | |
42f5551d | 609 | INTEL_IVB_Q_IDS(&intel_ivybridge_q_info), /* must be first IVB */ |
0890540e LL |
610 | INTEL_IVB_M_GT1_IDS(&intel_ivybridge_m_gt1_info), |
611 | INTEL_IVB_M_GT2_IDS(&intel_ivybridge_m_gt2_info), | |
612 | INTEL_IVB_D_GT1_IDS(&intel_ivybridge_d_gt1_info), | |
613 | INTEL_IVB_D_GT2_IDS(&intel_ivybridge_d_gt2_info), | |
614 | INTEL_HSW_GT1_IDS(&intel_haswell_gt1_info), | |
615 | INTEL_HSW_GT2_IDS(&intel_haswell_gt2_info), | |
616 | INTEL_HSW_GT3_IDS(&intel_haswell_gt3_info), | |
8d9c20e1 | 617 | INTEL_VLV_IDS(&intel_valleyview_info), |
0890540e LL |
618 | INTEL_BDW_GT1_IDS(&intel_broadwell_gt1_info), |
619 | INTEL_BDW_GT2_IDS(&intel_broadwell_gt2_info), | |
8d9c20e1 | 620 | INTEL_BDW_GT3_IDS(&intel_broadwell_gt3_info), |
0890540e | 621 | INTEL_BDW_RSVD_IDS(&intel_broadwell_rsvd_info), |
42f5551d | 622 | INTEL_CHV_IDS(&intel_cherryview_info), |
0890540e LL |
623 | INTEL_SKL_GT1_IDS(&intel_skylake_gt1_info), |
624 | INTEL_SKL_GT2_IDS(&intel_skylake_gt2_info), | |
42f5551d | 625 | INTEL_SKL_GT3_IDS(&intel_skylake_gt3_info), |
0890540e | 626 | INTEL_SKL_GT4_IDS(&intel_skylake_gt4_info), |
42f5551d | 627 | INTEL_BXT_IDS(&intel_broxton_info), |
8363e3c3 | 628 | INTEL_GLK_IDS(&intel_geminilake_info), |
0890540e LL |
629 | INTEL_KBL_GT1_IDS(&intel_kabylake_gt1_info), |
630 | INTEL_KBL_GT2_IDS(&intel_kabylake_gt2_info), | |
42f5551d CW |
631 | INTEL_KBL_GT3_IDS(&intel_kabylake_gt3_info), |
632 | INTEL_KBL_GT4_IDS(&intel_kabylake_gt3_info), | |
0890540e LL |
633 | INTEL_CFL_S_GT1_IDS(&intel_coffeelake_gt1_info), |
634 | INTEL_CFL_S_GT2_IDS(&intel_coffeelake_gt2_info), | |
635 | INTEL_CFL_H_GT2_IDS(&intel_coffeelake_gt2_info), | |
636 | INTEL_CFL_U_GT3_IDS(&intel_coffeelake_gt3_info), | |
637 | INTEL_CNL_U_GT2_IDS(&intel_cannonlake_gt2_info), | |
638 | INTEL_CNL_Y_GT2_IDS(&intel_cannonlake_gt2_info), | |
42f5551d CW |
639 | {0, 0, 0} |
640 | }; | |
641 | MODULE_DEVICE_TABLE(pci, pciidlist); | |
642 | ||
953c7f82 CW |
643 | static void i915_pci_remove(struct pci_dev *pdev) |
644 | { | |
645 | struct drm_device *dev = pci_get_drvdata(pdev); | |
646 | ||
647 | i915_driver_unload(dev); | |
648 | drm_dev_unref(dev); | |
649 | } | |
650 | ||
42f5551d CW |
651 | static int i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent) |
652 | { | |
653 | struct intel_device_info *intel_info = | |
654 | (struct intel_device_info *) ent->driver_data; | |
953c7f82 | 655 | int err; |
42f5551d | 656 | |
4f044a88 | 657 | if (IS_ALPHA_SUPPORT(intel_info) && !i915_modparams.alpha_support) { |
c007fb4a JN |
658 | DRM_INFO("The driver support for your hardware in this kernel version is alpha quality\n" |
659 | "See CONFIG_DRM_I915_ALPHA_SUPPORT or i915.alpha_support module parameter\n" | |
660 | "to enable support in this kernel version, or check for kernel updates.\n"); | |
42f5551d CW |
661 | return -ENODEV; |
662 | } | |
663 | ||
664 | /* Only bind to function 0 of the device. Early generations | |
665 | * used function 1 as a placeholder for multi-head. This causes | |
666 | * us confusion instead, especially on the systems where both | |
667 | * functions have the same PCI-ID! | |
668 | */ | |
669 | if (PCI_FUNC(pdev->devfn)) | |
670 | return -ENODEV; | |
671 | ||
672 | /* | |
673 | * apple-gmux is needed on dual GPU MacBook Pro | |
674 | * to probe the panel if we're the inactive GPU. | |
675 | */ | |
676 | if (vga_switcheroo_client_probe_defer(pdev)) | |
677 | return -EPROBE_DEFER; | |
678 | ||
953c7f82 CW |
679 | err = i915_driver_load(pdev, ent); |
680 | if (err) | |
681 | return err; | |
42f5551d | 682 | |
953c7f82 CW |
683 | err = i915_live_selftests(pdev); |
684 | if (err) { | |
685 | i915_pci_remove(pdev); | |
686 | return err > 0 ? -ENOTTY : err; | |
687 | } | |
42f5551d | 688 | |
953c7f82 | 689 | return 0; |
42f5551d CW |
690 | } |
691 | ||
a09d0ba1 | 692 | static struct pci_driver i915_pci_driver = { |
42f5551d CW |
693 | .name = DRIVER_NAME, |
694 | .id_table = pciidlist, | |
695 | .probe = i915_pci_probe, | |
696 | .remove = i915_pci_remove, | |
697 | .driver.pm = &i915_pm_ops, | |
698 | }; | |
a09d0ba1 CW |
699 | |
700 | static int __init i915_init(void) | |
701 | { | |
702 | bool use_kms = true; | |
953c7f82 CW |
703 | int err; |
704 | ||
705 | err = i915_mock_selftests(); | |
706 | if (err) | |
707 | return err > 0 ? 0 : err; | |
a09d0ba1 CW |
708 | |
709 | /* | |
710 | * Enable KMS by default, unless explicitly overriden by | |
711 | * either the i915.modeset prarameter or by the | |
712 | * vga_text_mode_force boot option. | |
713 | */ | |
714 | ||
4f044a88 | 715 | if (i915_modparams.modeset == 0) |
a09d0ba1 CW |
716 | use_kms = false; |
717 | ||
4f044a88 | 718 | if (vgacon_text_force() && i915_modparams.modeset == -1) |
a09d0ba1 CW |
719 | use_kms = false; |
720 | ||
721 | if (!use_kms) { | |
722 | /* Silently fail loading to not upset userspace. */ | |
723 | DRM_DEBUG_DRIVER("KMS disabled.\n"); | |
724 | return 0; | |
725 | } | |
726 | ||
727 | return pci_register_driver(&i915_pci_driver); | |
728 | } | |
729 | ||
730 | static void __exit i915_exit(void) | |
731 | { | |
732 | if (!i915_pci_driver.driver.owner) | |
733 | return; | |
734 | ||
735 | pci_unregister_driver(&i915_pci_driver); | |
736 | } | |
737 | ||
738 | module_init(i915_init); | |
739 | module_exit(i915_exit); | |
740 | ||
741 | MODULE_AUTHOR("Tungsten Graphics, Inc."); | |
742 | MODULE_AUTHOR("Intel Corporation"); | |
743 | ||
744 | MODULE_DESCRIPTION(DRIVER_DESC); | |
745 | MODULE_LICENSE("GPL and additional rights"); |